PerfEvent: refactor perfevents in Backend

* add `dispatch2Iq_out_fire_cnt`, `issueQueue_enq_fire_cnt`, `issueQueue_full` event in scheduler
* add busytable event
* move collecting perfevents from

PerfEvent: refactor perfevents in Backend

* add `dispatch2Iq_out_fire_cnt`, `issueQueue_enq_fire_cnt`, `issueQueue_full` event in scheduler
* add busytable event
* move collecting perfevents from `ctrlBlock` to `backend`
* change `perfEventsCtrl` into `perfEventsBackend`

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NewCSR: remove disableXXfence bundle and useless IO, since all fence checks have been done in decode

NewCSR: fix hfence exception io

Fence: update disable sfence

Backend,XSTop: connect clint time to CSR

NewCSR: add full illegal check to `sfence` and the insts in `Svinval` extension

* Move the permission check for some insts to DecodeUnit.
* These insts are `sfence.vma`, `sinval.vma`, `sfence.w.inva

NewCSR: add full illegal check to `sfence` and the insts in `Svinval` extension

* Move the permission check for some insts to DecodeUnit.
* These insts are `sfence.vma`, `sinval.vma`, `sfence.w.inval`, `sfence.inval.ir`, `hfence.gvma`, `hinval.gvma`, `hfence.vvma` and `hinval.vvma`.

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IMSIC: update verilog module and io

NewCSR: add IMSIC

chore: bump chisel 6.5.0 (#3210)

Backend, RVH: fix coding conflicts between prefetch and hypervisor instruction (#3196)

Backend & MemBlock: feedback use lqidx instead of robidx for fix timing and fix bug of vld feedback (#3189)

Backend&MemBlock: feedback use sqidx instead of robidx and uopidx for fix timing (#3172)

build: bump chisel 3.6.1, scala 2.13.14, mill 0.11.8, etc. (#3118)

vstart: support vstart value update and handle vstart exception (#3109)

* after execute vset and vload/vstore(no exception) instructions, set
vstart to zero
* when execute vector instructions exce

vstart: support vstart value update and handle vstart exception (#3109)

* after execute vset and vload/vstore(no exception) instructions, set
vstart to zero
* when execute vector instructions except above instructions, raise
illegal instruction exception
* when modify vstart, blockback and flushpipe

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Og2ForVector: fix ImmInfo of vector Exus, it should delay 1 cycle in og2 (#3089)

vl: assign vl in csr to the value store in vl regfiles

Backend fixtiming: fix rab/exuwb/wbtorob timing (#3032)

rab:
fix commit/walk/special walk Count from popcount to priority mux
exuwb:
fix exuwb Nto1 logic: add int/fp/vec 3 wbpath to wbarbite

Backend fixtiming: fix rab/exuwb/wbtorob timing (#3032)

rab:
fix commit/walk/special walk Count from popcount to priority mux
exuwb:
fix exuwb Nto1 logic: add int/fp/vec 3 wbpath to wbarbiter
wbtorob:
fix writebacknum count: delete extra count for exu which cannot be compressed

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Backend: connect v0Wen vlWen to memBlock

Exu: connect V0Wen VlWen

WbDataPath: support v0 & vl split

DataPath: support v0 & vl split

Rename: v0 vl split

Backend: add some basic signals for v0 & vl split

vtype: fix bug when vsetvl instruction's rd and rs1 are x0 (#3039)

* fix uop split bug for vsetvl when rd and rs1 are 0, the first uop use
wrong source register
* fix vtype writeback logic, add mu

vtype: fix bug when vsetvl instruction's rd and rs1 are x0 (#3039)

* fix uop split bug for vsetvl when rd and rs1 are 0, the first uop use
wrong source register
* fix vtype writeback logic, add mux to choose vtype from intExu or
vfExu

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vtype: add valid signal for vsetvl instruction when calculate output