1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 23import utility.{Constantin, ZeroExt} 24import xiangshan._ 25import xiangshan.backend.Bundles.{DynInst, IssueQueueIQWakeUpBundle, LoadShouldCancel, MemExuInput, MemExuOutput, VPUCtrlSignals} 26import xiangshan.backend.ctrlblock.{DebugLSIO, LsTopdownInfo} 27import xiangshan.backend.datapath.DataConfig.{IntData, VecData, FpData} 28import xiangshan.backend.datapath.RdConfig.{IntRD, VfRD} 29import xiangshan.backend.datapath.WbConfig._ 30import xiangshan.backend.datapath._ 31import xiangshan.backend.dispatch.CoreDispatchTopDownIO 32import xiangshan.backend.exu.ExuBlock 33import xiangshan.backend.fu.vector.Bundles.{VConfig, VType} 34import xiangshan.backend.fu.{FenceIO, FenceToSbuffer, FuConfig, FuType, PerfCounterIO} 35import xiangshan.backend.issue.EntryBundles._ 36import xiangshan.backend.issue.{CancelNetwork, Scheduler, SchedulerImpBase} 37import xiangshan.backend.rob.{RobCoreTopDownIO, RobDebugRollingIO, RobLsqIO, RobPtr} 38import xiangshan.frontend.{FtqPtr, FtqRead, PreDecodeInfo} 39import xiangshan.mem.{LqPtr, LsqEnqIO, SqPtr} 40import scala.collection.mutable 41 42class Backend(val params: BackendParams)(implicit p: Parameters) extends LazyModule 43 with HasXSParameter { 44 45 override def shouldBeInlined: Boolean = false 46 47 // check read & write port config 48 params.configChecks 49 50 /* Only update the idx in mem-scheduler here 51 * Idx in other schedulers can be updated the same way if needed 52 * 53 * Also note that we filter out the 'stData issue-queues' when counting 54 */ 55 for ((ibp, idx) <- params.memSchdParams.get.issueBlockParams.filter(iq => iq.StdCnt == 0).zipWithIndex) { 56 ibp.updateIdx(idx) 57 } 58 59 println(params.iqWakeUpParams) 60 61 for ((schdCfg, i) <- params.allSchdParams.zipWithIndex) { 62 schdCfg.bindBackendParam(params) 63 } 64 65 for ((iqCfg, i) <- params.allIssueParams.zipWithIndex) { 66 iqCfg.bindBackendParam(params) 67 } 68 69 for ((exuCfg, i) <- params.allExuParams.zipWithIndex) { 70 exuCfg.bindBackendParam(params) 71 exuCfg.updateIQWakeUpConfigs(params.iqWakeUpParams) 72 exuCfg.updateExuIdx(i) 73 } 74 75 println("[Backend] ExuConfigs:") 76 for (exuCfg <- params.allExuParams) { 77 val fuConfigs = exuCfg.fuConfigs 78 val wbPortConfigs = exuCfg.wbPortConfigs 79 val immType = exuCfg.immType 80 81 println("[Backend] " + 82 s"${exuCfg.name}: " + 83 (if (exuCfg.fakeUnit) "fake, " else "") + 84 (if (exuCfg.hasLoadFu || exuCfg.hasHyldaFu) s"LdExuIdx(${backendParams.getLdExuIdx(exuCfg)})" else "") + 85 s"${fuConfigs.map(_.name).mkString("fu(s): {", ",", "}")}, " + 86 s"${wbPortConfigs.mkString("wb: {", ",", "}")}, " + 87 s"${immType.map(SelImm.mkString(_)).mkString("imm: {", ",", "}")}, " + 88 s"latMax(${exuCfg.latencyValMax}), ${exuCfg.fuLatancySet.mkString("lat: {", ",", "}")}, " + 89 s"srcReg(${exuCfg.numRegSrc})" 90 ) 91 require( 92 wbPortConfigs.collectFirst { case x: IntWB => x }.nonEmpty == 93 fuConfigs.map(_.writeIntRf).reduce(_ || _), 94 s"${exuCfg.name} int wb port has no priority" 95 ) 96 require( 97 wbPortConfigs.collectFirst { case x: FpWB => x }.nonEmpty == 98 fuConfigs.map(x => x.writeFpRf).reduce(_ || _), 99 s"${exuCfg.name} fp wb port has no priority" 100 ) 101 require( 102 wbPortConfigs.collectFirst { case x: VfWB => x }.nonEmpty == 103 fuConfigs.map(x => x.writeVecRf).reduce(_ || _), 104 s"${exuCfg.name} vec wb port has no priority" 105 ) 106 } 107 108 println(s"[Backend] all fu configs") 109 for (cfg <- FuConfig.allConfigs) { 110 println(s"[Backend] $cfg") 111 } 112 113 println(s"[Backend] Int RdConfigs: ExuName(Priority)") 114 for ((port, seq) <- params.getRdPortParams(IntData())) { 115 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 116 } 117 118 println(s"[Backend] Int WbConfigs: ExuName(Priority)") 119 for ((port, seq) <- params.getWbPortParams(IntData())) { 120 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 121 } 122 123 println(s"[Backend] Fp RdConfigs: ExuName(Priority)") 124 for ((port, seq) <- params.getRdPortParams(FpData())) { 125 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 126 } 127 128 println(s"[Backend] Fp WbConfigs: ExuName(Priority)") 129 for ((port, seq) <- params.getWbPortParams(FpData())) { 130 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 131 } 132 133 println(s"[Backend] Vf RdConfigs: ExuName(Priority)") 134 for ((port, seq) <- params.getRdPortParams(VecData())) { 135 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 136 } 137 138 println(s"[Backend] Vf WbConfigs: ExuName(Priority)") 139 for ((port, seq) <- params.getWbPortParams(VecData())) { 140 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 141 } 142 143 println(s"[Backend] Dispatch Configs:") 144 println(s"[Backend] Load IQ enq width(${params.numLoadDp}), Store IQ enq width(${params.numStoreDp})") 145 println(s"[Backend] Load DP width(${LSQLdEnqWidth}), Store DP width(${LSQStEnqWidth})") 146 147 params.updateCopyPdestInfo 148 println(s"[Backend] copyPdestInfo ${params.copyPdestInfo}") 149 params.allExuParams.map(_.copyNum) 150 val ctrlBlock = LazyModule(new CtrlBlock(params)) 151 val pcTargetMem = LazyModule(new PcTargetMem(params)) 152 val intScheduler = params.intSchdParams.map(x => LazyModule(new Scheduler(x))) 153 val fpScheduler = params.fpSchdParams.map(x => LazyModule(new Scheduler(x))) 154 val vfScheduler = params.vfSchdParams.map(x => LazyModule(new Scheduler(x))) 155 val memScheduler = params.memSchdParams.map(x => LazyModule(new Scheduler(x))) 156 val dataPath = LazyModule(new DataPath(params)) 157 val intExuBlock = params.intSchdParams.map(x => LazyModule(new ExuBlock(x))) 158 val fpExuBlock = params.fpSchdParams.map(x => LazyModule(new ExuBlock(x))) 159 val vfExuBlock = params.vfSchdParams.map(x => LazyModule(new ExuBlock(x))) 160 val wbFuBusyTable = LazyModule(new WbFuBusyTable(params)) 161 162 lazy val module = new BackendImp(this) 163} 164 165class BackendImp(override val wrapper: Backend)(implicit p: Parameters) extends LazyModuleImp(wrapper) 166 with HasXSParameter { 167 implicit private val params = wrapper.params 168 169 val io = IO(new BackendIO()(p, wrapper.params)) 170 171 private val ctrlBlock = wrapper.ctrlBlock.module 172 private val pcTargetMem = wrapper.pcTargetMem.module 173 private val intScheduler: SchedulerImpBase = wrapper.intScheduler.get.module 174 private val fpScheduler = wrapper.fpScheduler.get.module 175 private val vfScheduler = wrapper.vfScheduler.get.module 176 private val memScheduler = wrapper.memScheduler.get.module 177 private val dataPath = wrapper.dataPath.module 178 private val intExuBlock = wrapper.intExuBlock.get.module 179 private val fpExuBlock = wrapper.fpExuBlock.get.module 180 private val vfExuBlock = wrapper.vfExuBlock.get.module 181 private val og2ForVector = Module(new Og2ForVector(params)) 182 private val bypassNetwork = Module(new BypassNetwork) 183 private val wbDataPath = Module(new WbDataPath(params)) 184 private val wbFuBusyTable = wrapper.wbFuBusyTable.module 185 186 private val iqWakeUpMappedBundle: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = ( 187 intScheduler.io.toSchedulers.wakeupVec ++ 188 fpScheduler.io.toSchedulers.wakeupVec ++ 189 vfScheduler.io.toSchedulers.wakeupVec ++ 190 memScheduler.io.toSchedulers.wakeupVec 191 ).map(x => (x.bits.exuIdx, x)).toMap 192 193 println(s"[Backend] iq wake up keys: ${iqWakeUpMappedBundle.keys}") 194 195 wbFuBusyTable.io.in.intSchdBusyTable := intScheduler.io.wbFuBusyTable 196 wbFuBusyTable.io.in.fpSchdBusyTable := fpScheduler.io.wbFuBusyTable 197 wbFuBusyTable.io.in.vfSchdBusyTable := vfScheduler.io.wbFuBusyTable 198 wbFuBusyTable.io.in.memSchdBusyTable := memScheduler.io.wbFuBusyTable 199 intScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.intRespRead 200 fpScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.fpRespRead 201 vfScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.vfRespRead 202 memScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.memRespRead 203 dataPath.io.wbConfictRead := wbFuBusyTable.io.out.wbConflictRead 204 205 private val og1CancelOH: UInt = dataPath.io.og1CancelOH 206 private val og0CancelOH: UInt = dataPath.io.og0CancelOH 207 private val cancelToBusyTable = dataPath.io.cancelToBusyTable 208 private val vlIsZero = intExuBlock.io.vlIsZero.get 209 private val vlIsVlmax = intExuBlock.io.vlIsVlmax.get 210 211 ctrlBlock.io.intIQValidNumVec := intScheduler.io.intIQValidNumVec 212 ctrlBlock.io.fpIQValidNumVec := fpScheduler.io.fpIQValidNumVec 213 ctrlBlock.io.fromTop.hartId := io.fromTop.hartId 214 ctrlBlock.io.frontend <> io.frontend 215 ctrlBlock.io.fromWB.wbData <> wbDataPath.io.toCtrlBlock.writeback 216 ctrlBlock.io.fromMem.stIn <> io.mem.stIn 217 ctrlBlock.io.fromMem.violation <> io.mem.memoryViolation 218 ctrlBlock.io.lqCanAccept := io.mem.lqCanAccept 219 ctrlBlock.io.sqCanAccept := io.mem.sqCanAccept 220 ctrlBlock.io.csrCtrl <> intExuBlock.io.csrio.get.customCtrl 221 ctrlBlock.io.robio.csr.intrBitSet := intExuBlock.io.csrio.get.interrupt 222 ctrlBlock.io.robio.csr.trapTarget := intExuBlock.io.csrio.get.trapTarget 223 ctrlBlock.io.robio.csr.isXRet := intExuBlock.io.csrio.get.isXRet 224 ctrlBlock.io.robio.csr.wfiEvent := intExuBlock.io.csrio.get.wfi_event 225 ctrlBlock.io.robio.lsq <> io.mem.robLsqIO 226 ctrlBlock.io.robio.lsTopdownInfo <> io.mem.lsTopdownInfo 227 ctrlBlock.io.robio.debug_ls <> io.mem.debugLS 228 ctrlBlock.perfinfo := DontCare // TODO: Implement backend hpm 229 ctrlBlock.io.debugEnqLsq.canAccept := io.mem.lsqEnqIO.canAccept 230 ctrlBlock.io.debugEnqLsq.resp := io.mem.lsqEnqIO.resp 231 ctrlBlock.io.debugEnqLsq.req := memScheduler.io.memIO.get.lsqEnqIO.req 232 ctrlBlock.io.debugEnqLsq.needAlloc := memScheduler.io.memIO.get.lsqEnqIO.needAlloc 233 234 intScheduler.io.fromTop.hartId := io.fromTop.hartId 235 intScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 236 intScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 237 intScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.intUops 238 intScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 239 intScheduler.io.fpWriteBack := 0.U.asTypeOf(intScheduler.io.fpWriteBack) 240 intScheduler.io.vfWriteBack := 0.U.asTypeOf(intScheduler.io.vfWriteBack) 241 intScheduler.io.fromDataPath.resp := dataPath.io.toIntIQ 242 intScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 243 intScheduler.io.fromDataPath.og0Cancel := og0CancelOH 244 intScheduler.io.fromDataPath.og1Cancel := og1CancelOH 245 intScheduler.io.ldCancel := io.mem.ldCancel 246 intScheduler.io.fromDataPath.cancelToBusyTable := cancelToBusyTable 247 intScheduler.io.vlWriteBack.vlIsZero := false.B 248 intScheduler.io.vlWriteBack.vlIsVlmax := false.B 249 250 fpScheduler.io.fromTop.hartId := io.fromTop.hartId 251 fpScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 252 fpScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 253 fpScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.fpUops 254 fpScheduler.io.intWriteBack := 0.U.asTypeOf(fpScheduler.io.intWriteBack) 255 fpScheduler.io.fpWriteBack := wbDataPath.io.toFpPreg 256 fpScheduler.io.vfWriteBack := 0.U.asTypeOf(fpScheduler.io.vfWriteBack) 257 fpScheduler.io.fromDataPath.resp := dataPath.io.toFpIQ 258 fpScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 259 fpScheduler.io.fromDataPath.og0Cancel := og0CancelOH 260 fpScheduler.io.fromDataPath.og1Cancel := og1CancelOH 261 fpScheduler.io.ldCancel := io.mem.ldCancel 262 fpScheduler.io.fromDataPath.cancelToBusyTable := cancelToBusyTable 263 fpScheduler.io.vlWriteBack.vlIsZero := false.B 264 fpScheduler.io.vlWriteBack.vlIsVlmax := false.B 265 266 memScheduler.io.fromTop.hartId := io.fromTop.hartId 267 memScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 268 memScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 269 memScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.memUops 270 memScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 271 memScheduler.io.fpWriteBack := wbDataPath.io.toFpPreg 272 memScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 273 memScheduler.io.fromMem.get.scommit := io.mem.sqDeq 274 memScheduler.io.fromMem.get.lcommit := io.mem.lqDeq 275 memScheduler.io.fromMem.get.wakeup := io.mem.wakeup 276 memScheduler.io.fromMem.get.sqDeqPtr := io.mem.sqDeqPtr 277 memScheduler.io.fromMem.get.lqDeqPtr := io.mem.lqDeqPtr 278 memScheduler.io.fromMem.get.sqCancelCnt := io.mem.sqCancelCnt 279 memScheduler.io.fromMem.get.lqCancelCnt := io.mem.lqCancelCnt 280 memScheduler.io.fromMem.get.stIssuePtr := io.mem.stIssuePtr 281 require(memScheduler.io.fromMem.get.memWaitUpdateReq.robIdx.length == io.mem.stIn.length) 282 memScheduler.io.fromMem.get.memWaitUpdateReq.robIdx.zip(io.mem.stIn).foreach { case (sink, source) => 283 sink.valid := source.valid 284 sink.bits := source.bits.robIdx 285 } 286 memScheduler.io.fromMem.get.memWaitUpdateReq.sqIdx := DontCare // TODO 287 memScheduler.io.fromDataPath.resp := dataPath.io.toMemIQ 288 memScheduler.io.fromMem.get.ldaFeedback := io.mem.ldaIqFeedback 289 memScheduler.io.fromMem.get.staFeedback := io.mem.staIqFeedback 290 memScheduler.io.fromMem.get.hyuFeedback := io.mem.hyuIqFeedback 291 memScheduler.io.fromMem.get.vstuFeedback := io.mem.vstuIqFeedback 292 memScheduler.io.fromMem.get.vlduFeedback := io.mem.vlduIqFeedback 293 memScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 294 memScheduler.io.fromDataPath.og0Cancel := og0CancelOH 295 memScheduler.io.fromDataPath.og1Cancel := og1CancelOH 296 memScheduler.io.ldCancel := io.mem.ldCancel 297 memScheduler.io.fromDataPath.cancelToBusyTable := cancelToBusyTable 298 memScheduler.io.vlWriteBack.vlIsZero := vlIsZero 299 memScheduler.io.vlWriteBack.vlIsVlmax := vlIsVlmax 300 301 vfScheduler.io.fromTop.hartId := io.fromTop.hartId 302 vfScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 303 vfScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 304 vfScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.vfUops 305 vfScheduler.io.intWriteBack := 0.U.asTypeOf(vfScheduler.io.intWriteBack) 306 vfScheduler.io.fpWriteBack := 0.U.asTypeOf(vfScheduler.io.fpWriteBack) 307 vfScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 308 vfScheduler.io.fromDataPath.resp := dataPath.io.toVfIQ 309 vfScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 310 vfScheduler.io.fromDataPath.og0Cancel := og0CancelOH 311 vfScheduler.io.fromDataPath.og1Cancel := og1CancelOH 312 vfScheduler.io.ldCancel := io.mem.ldCancel 313 vfScheduler.io.fromDataPath.cancelToBusyTable := cancelToBusyTable 314 vfScheduler.io.vlWriteBack.vlIsZero := vlIsZero 315 vfScheduler.io.vlWriteBack.vlIsVlmax := vlIsVlmax 316 vfScheduler.io.fromOg2.get := og2ForVector.io.toVfIQ 317 318 dataPath.io.hartId := io.fromTop.hartId 319 dataPath.io.flush := ctrlBlock.io.toDataPath.flush 320 321 dataPath.io.fromIntIQ <> intScheduler.io.toDataPathAfterDelay 322 dataPath.io.fromFpIQ <> fpScheduler.io.toDataPathAfterDelay 323 dataPath.io.fromVfIQ <> vfScheduler.io.toDataPathAfterDelay 324 dataPath.io.fromMemIQ <> memScheduler.io.toDataPathAfterDelay 325 326 dataPath.io.ldCancel := io.mem.ldCancel 327 328 println(s"[Backend] wbDataPath.io.toIntPreg: ${wbDataPath.io.toIntPreg.size}, dataPath.io.fromIntWb: ${dataPath.io.fromIntWb.size}") 329 println(s"[Backend] wbDataPath.io.toVfPreg: ${wbDataPath.io.toVfPreg.size}, dataPath.io.fromFpWb: ${dataPath.io.fromVfWb.size}") 330 dataPath.io.fromIntWb := wbDataPath.io.toIntPreg 331 dataPath.io.fromFpWb := wbDataPath.io.toFpPreg 332 dataPath.io.fromVfWb := wbDataPath.io.toVfPreg 333 dataPath.io.debugIntRat .foreach(_ := ctrlBlock.io.debug_int_rat.get) 334 dataPath.io.debugFpRat .foreach(_ := ctrlBlock.io.debug_fp_rat.get) 335 dataPath.io.debugVecRat .foreach(_ := ctrlBlock.io.debug_vec_rat.get) 336 dataPath.io.debugVconfigRat.foreach(_ := ctrlBlock.io.debug_vconfig_rat.get) 337 338 og2ForVector.io.flush := ctrlBlock.io.toDataPath.flush 339 og2ForVector.io.ldCancel := io.mem.ldCancel 340 og2ForVector.io.fromOg1NoReg <> dataPath.io.toVecExu 341 342 bypassNetwork.io.fromDataPath.int <> dataPath.io.toIntExu 343 bypassNetwork.io.fromDataPath.fp <> dataPath.io.toFpExu 344 bypassNetwork.io.fromDataPath.vf <> og2ForVector.io.toVfExu 345 bypassNetwork.io.fromDataPath.mem <> dataPath.io.toMemExu 346 bypassNetwork.io.fromDataPath.immInfo := dataPath.io.og1ImmInfo 347 bypassNetwork.io.fromExus.connectExuOutput(_.int)(intExuBlock.io.out) 348 bypassNetwork.io.fromExus.connectExuOutput(_.fp)(fpExuBlock.io.out) 349 bypassNetwork.io.fromExus.connectExuOutput(_.vf)(vfExuBlock.io.out) 350 351 require(bypassNetwork.io.fromExus.mem.flatten.size == io.mem.writeBack.size, 352 s"bypassNetwork.io.fromExus.mem.flatten.size(${bypassNetwork.io.fromExus.mem.flatten.size}: ${bypassNetwork.io.fromExus.mem.map(_.size)}, " + 353 s"io.mem.writeback(${io.mem.writeBack.size})" 354 ) 355 bypassNetwork.io.fromExus.mem.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 356 sink.valid := source.valid 357 sink.bits.pdest := source.bits.uop.pdest 358 sink.bits.data := source.bits.data 359 } 360 361 362 intExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 363 for (i <- 0 until intExuBlock.io.in.length) { 364 for (j <- 0 until intExuBlock.io.in(i).length) { 365 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.int(i)(j).bits.loadDependency, io.mem.ldCancel) 366 NewPipelineConnect( 367 bypassNetwork.io.toExus.int(i)(j), intExuBlock.io.in(i)(j), intExuBlock.io.in(i)(j).fire, 368 Mux( 369 bypassNetwork.io.toExus.int(i)(j).fire, 370 bypassNetwork.io.toExus.int(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 371 intExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 372 ), 373 Option("bypassNetwork2intExuBlock") 374 ) 375 } 376 } 377 378 pcTargetMem.io.fromFrontendFtq := io.frontend.fromFtq 379 pcTargetMem.io.toDataPath <> dataPath.io.fromPcTargetMem 380 381 private val csrio = intExuBlock.io.csrio.get 382 csrio.hartId := io.fromTop.hartId 383 csrio.fpu.fflags := ctrlBlock.io.robio.csr.fflags 384 csrio.fpu.isIllegal := false.B // Todo: remove it 385 csrio.fpu.dirty_fs := ctrlBlock.io.robio.csr.dirty_fs 386 csrio.vpu <> 0.U.asTypeOf(csrio.vpu) // Todo 387 388 val fromVsetVType = intExuBlock.io.vtype.getOrElse(0.U.asTypeOf((Valid(new VType)))) 389 val vsetvlVType = RegEnable(fromVsetVType.bits, 0.U.asTypeOf(new VType), fromVsetVType.valid) 390 ctrlBlock.io.robio.vsetvlVType := vsetvlVType 391 392 val debugVconfig = dataPath.io.debugVconfig match { 393 case Some(x) => dataPath.io.debugVconfig.get.asTypeOf(new VConfig) 394 case None => 0.U.asTypeOf(new VConfig) 395 } 396 val commitVType = ctrlBlock.io.robio.commitVType.vtype 397 val hasVsetvl = ctrlBlock.io.robio.commitVType.hasVsetvl 398 val vtype = VType.toVtypeStruct(Mux(hasVsetvl, vsetvlVType, commitVType.bits)).asUInt 399 val debugVl = debugVconfig.vl 400 csrio.vpu.set_vxsat := ctrlBlock.io.robio.csr.vxsat 401 csrio.vpu.set_vstart.valid := ctrlBlock.io.robio.csr.vstart.valid 402 csrio.vpu.set_vstart.bits := ctrlBlock.io.robio.csr.vstart.bits 403 csrio.vpu.set_vtype.valid := ctrlBlock.io.robio.csr.vcsrFlag 404 //Todo here need change design 405 csrio.vpu.set_vtype.valid := commitVType.valid 406 csrio.vpu.set_vtype.bits := ZeroExt(vtype, XLEN) 407 csrio.vpu.set_vl.valid := ctrlBlock.io.robio.csr.vcsrFlag 408 csrio.vpu.set_vl.bits := ZeroExt(debugVl, XLEN) 409 csrio.vpu.dirty_vs := ctrlBlock.io.robio.csr.dirty_vs 410 csrio.exception := ctrlBlock.io.robio.exception 411 csrio.memExceptionVAddr := io.mem.exceptionAddr.vaddr 412 csrio.memExceptionGPAddr := io.mem.exceptionAddr.gpaddr 413 csrio.externalInterrupt := io.fromTop.externalInterrupt 414 csrio.distributedUpdate(0) := io.mem.csrDistributedUpdate 415 csrio.distributedUpdate(1) := io.frontendCsrDistributedUpdate 416 csrio.perf <> io.perf 417 csrio.perf.retiredInstr <> ctrlBlock.io.robio.csr.perfinfo.retiredInstr 418 csrio.perf.ctrlInfo <> ctrlBlock.io.perfInfo.ctrlInfo 419 csrio.perf.perfEventsCtrl <> ctrlBlock.getPerf 420 private val fenceio = intExuBlock.io.fenceio.get 421 io.fenceio <> fenceio 422 fenceio.disableSfence := csrio.disableSfence 423 fenceio.disableHfenceg := csrio.disableHfenceg 424 fenceio.disableHfencev := csrio.disableHfencev 425 fenceio.virtMode := csrio.customCtrl.virtMode 426 427 // to fpExuBlock 428 fpExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 429 for (i <- 0 until fpExuBlock.io.in.length) { 430 for (j <- 0 until fpExuBlock.io.in(i).length) { 431 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.fp(i)(j).bits.loadDependency, io.mem.ldCancel) 432 NewPipelineConnect( 433 bypassNetwork.io.toExus.fp(i)(j), fpExuBlock.io.in(i)(j), fpExuBlock.io.in(i)(j).fire, 434 Mux( 435 bypassNetwork.io.toExus.fp(i)(j).fire, 436 bypassNetwork.io.toExus.fp(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 437 fpExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 438 ), 439 Option("bypassNetwork2fpExuBlock") 440 ) 441 } 442 } 443 444 vfExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 445 for (i <- 0 until vfExuBlock.io.in.size) { 446 for (j <- 0 until vfExuBlock.io.in(i).size) { 447 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.vf(i)(j).bits.loadDependency, io.mem.ldCancel) 448 NewPipelineConnect( 449 bypassNetwork.io.toExus.vf(i)(j), vfExuBlock.io.in(i)(j), vfExuBlock.io.in(i)(j).fire, 450 Mux( 451 bypassNetwork.io.toExus.vf(i)(j).fire, 452 bypassNetwork.io.toExus.vf(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 453 vfExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 454 ), 455 Option("bypassNetwork2vfExuBlock") 456 ) 457 458 vfExuBlock.io.in(i)(j).bits.vpu.foreach(_.vstart := csrio.vpu.vstart) 459 } 460 } 461 462 intExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 463 fpExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 464 fpExuBlock.io.vxrm.foreach(_ := csrio.vpu.vxrm) 465 vfExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 466 vfExuBlock.io.vxrm.foreach(_ := csrio.vpu.vxrm) 467 468 wbDataPath.io.flush := ctrlBlock.io.redirect 469 wbDataPath.io.fromTop.hartId := io.fromTop.hartId 470 wbDataPath.io.fromIntExu <> intExuBlock.io.out 471 wbDataPath.io.fromFpExu <> fpExuBlock.io.out 472 wbDataPath.io.fromVfExu <> vfExuBlock.io.out 473 wbDataPath.io.fromMemExu.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 474 sink.valid := source.valid 475 source.ready := sink.ready 476 sink.bits.data := source.bits.data 477 sink.bits.pdest := source.bits.uop.pdest 478 sink.bits.robIdx := source.bits.uop.robIdx 479 sink.bits.intWen.foreach(_ := source.bits.uop.rfWen) 480 sink.bits.fpWen.foreach(_ := source.bits.uop.fpWen) 481 sink.bits.vecWen.foreach(_ := source.bits.uop.vecWen) 482 sink.bits.exceptionVec.foreach(_ := source.bits.uop.exceptionVec) 483 sink.bits.flushPipe.foreach(_ := source.bits.uop.flushPipe) 484 sink.bits.replay.foreach(_ := source.bits.uop.replayInst) 485 sink.bits.debug := source.bits.debug 486 sink.bits.debugInfo := source.bits.uop.debugInfo 487 sink.bits.lqIdx.foreach(_ := source.bits.uop.lqIdx) 488 sink.bits.sqIdx.foreach(_ := source.bits.uop.sqIdx) 489 sink.bits.predecodeInfo.foreach(_ := source.bits.uop.preDecodeInfo) 490 sink.bits.vls.foreach(x => { 491 x.vdIdx := source.bits.vdIdx.get 492 x.vdIdxInField := source.bits.vdIdxInField.get 493 x.vpu := source.bits.uop.vpu 494 x.oldVdPsrc := source.bits.uop.psrc(2) 495 x.isIndexed := VlduType.isIndexed(source.bits.uop.fuOpType) 496 x.isMasked := VlduType.isMasked(source.bits.uop.fuOpType) 497 }) 498 sink.bits.trigger.foreach(_ := source.bits.uop.trigger) 499 } 500 501 // to mem 502 private val memIssueParams = params.memSchdParams.get.issueBlockParams 503 private val memExuBlocksHasLDU = memIssueParams.map(_.exuBlockParams.map(x => x.hasLoadFu || x.hasHyldaFu)) 504 private val memExuBlocksHasVecLoad = memIssueParams.map(_.exuBlockParams.map(x => x.hasVLoadFu)) 505 println(s"[Backend] memExuBlocksHasLDU: $memExuBlocksHasLDU") 506 println(s"[Backend] memExuBlocksHasVecLoad: $memExuBlocksHasVecLoad") 507 508 private val toMem = Wire(bypassNetwork.io.toExus.mem.cloneType) 509 for (i <- toMem.indices) { 510 for (j <- toMem(i).indices) { 511 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.mem(i)(j).bits.loadDependency, io.mem.ldCancel) 512 val issueTimeout = 513 if (memExuBlocksHasLDU(i)(j)) 514 Counter(0 until 16, toMem(i)(j).valid && !toMem(i)(j).fire, bypassNetwork.io.toExus.mem(i)(j).fire)._2 515 else 516 false.B 517 518 if (memScheduler.io.loadFinalIssueResp(i).nonEmpty && memExuBlocksHasLDU(i)(j)) { 519 memScheduler.io.loadFinalIssueResp(i)(j).valid := issueTimeout 520 memScheduler.io.loadFinalIssueResp(i)(j).bits.fuType := toMem(i)(j).bits.fuType 521 memScheduler.io.loadFinalIssueResp(i)(j).bits.resp := RespType.block 522 memScheduler.io.loadFinalIssueResp(i)(j).bits.robIdx := toMem(i)(j).bits.robIdx 523 memScheduler.io.loadFinalIssueResp(i)(j).bits.uopIdx.foreach(_ := toMem(i)(j).bits.vpu.get.vuopIdx) 524 } 525 526 NewPipelineConnect( 527 bypassNetwork.io.toExus.mem(i)(j), toMem(i)(j), toMem(i)(j).fire, 528 Mux( 529 bypassNetwork.io.toExus.mem(i)(j).fire, 530 bypassNetwork.io.toExus.mem(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 531 toMem(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || issueTimeout 532 ), 533 Option("bypassNetwork2toMemExus") 534 ) 535 536 if (memScheduler.io.memAddrIssueResp(i).nonEmpty && memExuBlocksHasLDU(i)(j)) { 537 memScheduler.io.memAddrIssueResp(i)(j).valid := toMem(i)(j).fire && FuType.isLoad(toMem(i)(j).bits.fuType) 538 memScheduler.io.memAddrIssueResp(i)(j).bits.fuType := toMem(i)(j).bits.fuType 539 memScheduler.io.memAddrIssueResp(i)(j).bits.robIdx := toMem(i)(j).bits.robIdx 540 memScheduler.io.memAddrIssueResp(i)(j).bits.resp := RespType.success // for load inst, firing at toMem means issuing successfully 541 } 542 543 if (memScheduler.io.vecLoadIssueResp(i).nonEmpty && memExuBlocksHasVecLoad(i)(j)) { 544 memScheduler.io.vecLoadIssueResp(i)(j) match { 545 case resp => 546 resp.valid := toMem(i)(j).fire && LSUOpType.isVecLd(toMem(i)(j).bits.fuOpType) 547 resp.bits.fuType := toMem(i)(j).bits.fuType 548 resp.bits.robIdx := toMem(i)(j).bits.robIdx 549 resp.bits.uopIdx.get := toMem(i)(j).bits.vpu.get.vuopIdx 550 resp.bits.resp := RespType.success 551 } 552 dontTouch(memScheduler.io.vecLoadIssueResp(i)(j)) 553 } 554 } 555 } 556 557 io.mem.redirect := ctrlBlock.io.redirect 558 io.mem.issueUops.zip(toMem.flatten).foreach { case (sink, source) => 559 val enableMdp = Constantin.createRecord("EnableMdp", true) 560 sink.valid := source.valid 561 source.ready := sink.ready 562 sink.bits.iqIdx := source.bits.iqIdx 563 sink.bits.isFirstIssue := source.bits.isFirstIssue 564 sink.bits.uop := 0.U.asTypeOf(sink.bits.uop) 565 sink.bits.src := 0.U.asTypeOf(sink.bits.src) 566 sink.bits.src.zip(source.bits.src).foreach { case (l, r) => l := r} 567 sink.bits.uop.fuType := source.bits.fuType 568 sink.bits.uop.fuOpType := source.bits.fuOpType 569 sink.bits.uop.imm := source.bits.imm 570 sink.bits.uop.robIdx := source.bits.robIdx 571 sink.bits.uop.pdest := source.bits.pdest 572 sink.bits.uop.rfWen := source.bits.rfWen.getOrElse(false.B) 573 sink.bits.uop.fpWen := source.bits.fpWen.getOrElse(false.B) 574 sink.bits.uop.vecWen := source.bits.vecWen.getOrElse(false.B) 575 sink.bits.uop.flushPipe := source.bits.flushPipe.getOrElse(false.B) 576 sink.bits.uop.pc := source.bits.pc.getOrElse(0.U) 577 sink.bits.uop.loadWaitBit := Mux(enableMdp, source.bits.loadWaitBit.getOrElse(false.B), false.B) 578 sink.bits.uop.waitForRobIdx := Mux(enableMdp, source.bits.waitForRobIdx.getOrElse(0.U.asTypeOf(new RobPtr)), 0.U.asTypeOf(new RobPtr)) 579 sink.bits.uop.storeSetHit := Mux(enableMdp, source.bits.storeSetHit.getOrElse(false.B), false.B) 580 sink.bits.uop.loadWaitStrict := Mux(enableMdp, source.bits.loadWaitStrict.getOrElse(false.B), false.B) 581 sink.bits.uop.ssid := Mux(enableMdp, source.bits.ssid.getOrElse(0.U(SSIDWidth.W)), 0.U(SSIDWidth.W)) 582 sink.bits.uop.lqIdx := source.bits.lqIdx.getOrElse(0.U.asTypeOf(new LqPtr)) 583 sink.bits.uop.sqIdx := source.bits.sqIdx.getOrElse(0.U.asTypeOf(new SqPtr)) 584 sink.bits.uop.ftqPtr := source.bits.ftqIdx.getOrElse(0.U.asTypeOf(new FtqPtr)) 585 sink.bits.uop.ftqOffset := source.bits.ftqOffset.getOrElse(0.U) 586 sink.bits.uop.debugInfo := source.bits.perfDebugInfo 587 sink.bits.uop.vpu := source.bits.vpu.getOrElse(0.U.asTypeOf(new VPUCtrlSignals)) 588 sink.bits.uop.preDecodeInfo := source.bits.preDecode.getOrElse(0.U.asTypeOf(new PreDecodeInfo)) 589 sink.bits.uop.numLsElem := source.bits.numLsElem.getOrElse(0.U) // Todo: remove this bundle, keep only the one below 590 sink.bits.flowNum.foreach(_ := source.bits.numLsElem.get) 591 } 592 io.mem.loadFastMatch := memScheduler.io.toMem.get.loadFastMatch.map(_.fastMatch) 593 io.mem.loadFastImm := memScheduler.io.toMem.get.loadFastMatch.map(_.fastImm) 594 io.mem.tlbCsr := csrio.tlb 595 io.mem.csrCtrl := csrio.customCtrl 596 io.mem.sfence := fenceio.sfence 597 io.mem.isStoreException := CommitType.lsInstIsStore(ctrlBlock.io.robio.exception.bits.commitType) 598 io.mem.isVlsException := ctrlBlock.io.robio.exception.bits.vls 599 require(io.mem.loadPcRead.size == params.LduCnt) 600 io.mem.loadPcRead.zipWithIndex.foreach { case (loadPcRead, i) => 601 loadPcRead := ctrlBlock.io.memLdPcRead(i).data 602 ctrlBlock.io.memLdPcRead(i).vld := io.mem.issueLda(i).valid 603 ctrlBlock.io.memLdPcRead(i).ptr := io.mem.issueLda(i).bits.uop.ftqPtr 604 ctrlBlock.io.memLdPcRead(i).offset := io.mem.issueLda(i).bits.uop.ftqOffset 605 } 606 607 io.mem.storePcRead.zipWithIndex.foreach { case (storePcRead, i) => 608 storePcRead := ctrlBlock.io.memStPcRead(i).data 609 ctrlBlock.io.memStPcRead(i).vld := io.mem.issueSta(i).valid 610 ctrlBlock.io.memStPcRead(i).ptr := io.mem.issueSta(i).bits.uop.ftqPtr 611 ctrlBlock.io.memStPcRead(i).offset := io.mem.issueSta(i).bits.uop.ftqOffset 612 } 613 614 io.mem.hyuPcRead.zipWithIndex.foreach( { case (hyuPcRead, i) => 615 hyuPcRead := ctrlBlock.io.memHyPcRead(i).data 616 ctrlBlock.io.memHyPcRead(i).vld := io.mem.issueHylda(i).valid 617 ctrlBlock.io.memHyPcRead(i).ptr := io.mem.issueHylda(i).bits.uop.ftqPtr 618 ctrlBlock.io.memHyPcRead(i).offset := io.mem.issueHylda(i).bits.uop.ftqOffset 619 }) 620 621 ctrlBlock.io.robio.robHeadLsIssue := io.mem.issueUops.map(deq => deq.fire && deq.bits.uop.robIdx === ctrlBlock.io.robio.robDeqPtr).reduce(_ || _) 622 623 // mem io 624 io.mem.lsqEnqIO <> memScheduler.io.memIO.get.lsqEnqIO 625 io.mem.robLsqIO <> ctrlBlock.io.robio.lsq 626 627 io.frontendSfence := fenceio.sfence 628 io.frontendTlbCsr := csrio.tlb 629 io.frontendCsrCtrl := csrio.customCtrl 630 631 io.tlb <> csrio.tlb 632 633 io.csrCustomCtrl := csrio.customCtrl 634 635 io.toTop.cpuHalted := false.B // TODO: implement cpu halt 636 637 io.debugTopDown.fromRob := ctrlBlock.io.debugTopDown.fromRob 638 ctrlBlock.io.debugTopDown.fromCore := io.debugTopDown.fromCore 639 640 io.debugRolling := ctrlBlock.io.debugRolling 641 642 if(backendParams.debugEn) { 643 dontTouch(memScheduler.io) 644 dontTouch(dataPath.io.toMemExu) 645 dontTouch(wbDataPath.io.fromMemExu) 646 } 647} 648 649class BackendMemIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 650 // Since fast load replay always use load unit 0, Backend flips two load port to avoid conflicts 651 val flippedLda = true 652 // params alias 653 private val LoadQueueSize = VirtualLoadQueueSize 654 // In/Out // Todo: split it into one-direction bundle 655 val lsqEnqIO = Flipped(new LsqEnqIO) 656 val robLsqIO = new RobLsqIO 657 val ldaIqFeedback = Vec(params.LduCnt, Flipped(new MemRSFeedbackIO)) 658 val staIqFeedback = Vec(params.StaCnt, Flipped(new MemRSFeedbackIO)) 659 val hyuIqFeedback = Vec(params.HyuCnt, Flipped(new MemRSFeedbackIO)) 660 val vstuIqFeedback = Flipped(Vec(params.VstuCnt, new MemRSFeedbackIO(isVector = true))) 661 val vlduIqFeedback = Flipped(Vec(params.VlduCnt, new MemRSFeedbackIO(isVector = true))) 662 val ldCancel = Vec(params.LdExuCnt, Flipped(new LoadCancelIO)) 663 val wakeup = Vec(params.LdExuCnt, Flipped(Valid(new DynInst))) 664 val loadPcRead = Vec(params.LduCnt, Output(UInt(VAddrBits.W))) 665 val storePcRead = Vec(params.StaCnt, Output(UInt(VAddrBits.W))) 666 val hyuPcRead = Vec(params.HyuCnt, Output(UInt(VAddrBits.W))) 667 // Input 668 val writebackLda = Vec(params.LduCnt, Flipped(DecoupledIO(new MemExuOutput))) 669 val writebackSta = Vec(params.StaCnt, Flipped(DecoupledIO(new MemExuOutput))) 670 val writebackStd = Vec(params.StdCnt, Flipped(DecoupledIO(new MemExuOutput))) 671 val writebackHyuLda = Vec(params.HyuCnt, Flipped(DecoupledIO(new MemExuOutput))) 672 val writebackHyuSta = Vec(params.HyuCnt, Flipped(DecoupledIO(new MemExuOutput))) 673 val writebackVldu = Vec(params.VlduCnt, Flipped(DecoupledIO(new MemExuOutput(true)))) 674 675 val s3_delayed_load_error = Input(Vec(LoadPipelineWidth, Bool())) 676 val stIn = Input(Vec(params.StaExuCnt, ValidIO(new DynInst()))) 677 val memoryViolation = Flipped(ValidIO(new Redirect)) 678 val exceptionAddr = Input(new Bundle { 679 val vaddr = UInt(VAddrBits.W) 680 val gpaddr = UInt(GPAddrBits.W) 681 }) 682 val sqDeq = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) 683 val lqDeq = Input(UInt(log2Up(CommitWidth + 1).W)) 684 val sqDeqPtr = Input(new SqPtr) 685 val lqDeqPtr = Input(new LqPtr) 686 687 val lqCancelCnt = Input(UInt(log2Up(VirtualLoadQueueSize + 1).W)) 688 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 689 690 val lqCanAccept = Input(Bool()) 691 val sqCanAccept = Input(Bool()) 692 693 val otherFastWakeup = Flipped(Vec(params.LduCnt + params.HyuCnt, ValidIO(new DynInst))) 694 val stIssuePtr = Input(new SqPtr()) 695 696 val csrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 697 698 val debugLS = Flipped(Output(new DebugLSIO)) 699 700 val lsTopdownInfo = Vec(params.LduCnt + params.HyuCnt, Flipped(Output(new LsTopdownInfo))) 701 // Output 702 val redirect = ValidIO(new Redirect) // rob flush MemBlock 703 val issueLda = MixedVec(Seq.fill(params.LduCnt)(DecoupledIO(new MemExuInput()))) 704 val issueSta = MixedVec(Seq.fill(params.StaCnt)(DecoupledIO(new MemExuInput()))) 705 val issueStd = MixedVec(Seq.fill(params.StdCnt)(DecoupledIO(new MemExuInput()))) 706 val issueHylda = MixedVec(Seq.fill(params.HyuCnt)(DecoupledIO(new MemExuInput()))) 707 val issueHysta = MixedVec(Seq.fill(params.HyuCnt)(DecoupledIO(new MemExuInput()))) 708 val issueVldu = MixedVec(Seq.fill(params.VlduCnt)(DecoupledIO(new MemExuInput(true)))) 709 710 val loadFastMatch = Vec(params.LduCnt, Output(UInt(params.LduCnt.W))) 711 val loadFastImm = Vec(params.LduCnt, Output(UInt(12.W))) // Imm_I 712 713 val tlbCsr = Output(new TlbCsrBundle) 714 val csrCtrl = Output(new CustomCSRCtrlIO) 715 val sfence = Output(new SfenceBundle) 716 val isStoreException = Output(Bool()) 717 val isVlsException = Output(Bool()) 718 719 // ATTENTION: The issue ports' sequence order should be the same as IQs' deq config 720 private [backend] def issueUops: Seq[DecoupledIO[MemExuInput]] = { 721 issueSta ++ 722 issueHylda ++ issueHysta ++ 723 issueLda ++ 724 issueVldu ++ 725 issueStd 726 }.toSeq 727 728 // ATTENTION: The writeback ports' sequence order should be the same as IQs' deq config 729 private [backend] def writeBack: Seq[DecoupledIO[MemExuOutput]] = { 730 writebackSta ++ 731 writebackHyuLda ++ writebackHyuSta ++ 732 writebackLda ++ 733 writebackVldu ++ 734 writebackStd 735 } 736} 737 738class BackendIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 739 val fromTop = new Bundle { 740 val hartId = Input(UInt(hartIdLen.W)) 741 val externalInterrupt = new ExternalInterruptIO 742 } 743 744 val toTop = new Bundle { 745 val cpuHalted = Output(Bool()) 746 } 747 748 val fenceio = new FenceIO 749 // Todo: merge these bundles into BackendFrontendIO 750 val frontend = Flipped(new FrontendToCtrlIO) 751 val frontendSfence = Output(new SfenceBundle) 752 val frontendCsrCtrl = Output(new CustomCSRCtrlIO) 753 val frontendTlbCsr = Output(new TlbCsrBundle) 754 // distributed csr write 755 val frontendCsrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 756 757 val mem = new BackendMemIO 758 759 val perf = Input(new PerfCounterIO) 760 761 val tlb = Output(new TlbCsrBundle) 762 763 val csrCustomCtrl = Output(new CustomCSRCtrlIO) 764 765 val debugTopDown = new Bundle { 766 val fromRob = new RobCoreTopDownIO 767 val fromCore = new CoreDispatchTopDownIO 768 } 769 val debugRolling = new RobDebugRollingIO 770} 771