1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import device.MsiInfoBundle 23import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 24import system.HasSoCParameter 25import utility.{Constantin, ZeroExt} 26import xiangshan._ 27import xiangshan.backend.Bundles.{DynInst, IssueQueueIQWakeUpBundle, LoadShouldCancel, MemExuInput, MemExuOutput, VPUCtrlSignals} 28import xiangshan.backend.ctrlblock.{DebugLSIO, LsTopdownInfo} 29import xiangshan.backend.datapath.DataConfig.{IntData, VecData, FpData} 30import xiangshan.backend.datapath.RdConfig.{IntRD, VfRD} 31import xiangshan.backend.datapath.WbConfig._ 32import xiangshan.backend.datapath.DataConfig._ 33import xiangshan.backend.datapath._ 34import xiangshan.backend.dispatch.CoreDispatchTopDownIO 35import xiangshan.backend.exu.ExuBlock 36import xiangshan.backend.fu.vector.Bundles.{VConfig, VType} 37import xiangshan.backend.fu.{FenceIO, FenceToSbuffer, FuConfig, FuType, PerfCounterIO} 38import xiangshan.backend.issue.EntryBundles._ 39import xiangshan.backend.issue.{CancelNetwork, Scheduler, SchedulerImpBase} 40import xiangshan.backend.rob.{RobCoreTopDownIO, RobDebugRollingIO, RobLsqIO, RobPtr} 41import xiangshan.frontend.{FtqPtr, FtqRead, PreDecodeInfo} 42import xiangshan.mem.{LqPtr, LsqEnqIO, SqPtr} 43 44import scala.collection.mutable 45 46class Backend(val params: BackendParams)(implicit p: Parameters) extends LazyModule 47 with HasXSParameter { 48 49 override def shouldBeInlined: Boolean = false 50 51 // check read & write port config 52 params.configChecks 53 54 /* Only update the idx in mem-scheduler here 55 * Idx in other schedulers can be updated the same way if needed 56 * 57 * Also note that we filter out the 'stData issue-queues' when counting 58 */ 59 for ((ibp, idx) <- params.memSchdParams.get.issueBlockParams.filter(iq => iq.StdCnt == 0).zipWithIndex) { 60 ibp.updateIdx(idx) 61 } 62 63 println(params.iqWakeUpParams) 64 65 for ((schdCfg, i) <- params.allSchdParams.zipWithIndex) { 66 schdCfg.bindBackendParam(params) 67 } 68 69 for ((iqCfg, i) <- params.allIssueParams.zipWithIndex) { 70 iqCfg.bindBackendParam(params) 71 } 72 73 for ((exuCfg, i) <- params.allExuParams.zipWithIndex) { 74 exuCfg.bindBackendParam(params) 75 exuCfg.updateIQWakeUpConfigs(params.iqWakeUpParams) 76 exuCfg.updateExuIdx(i) 77 } 78 79 println("[Backend] ExuConfigs:") 80 for (exuCfg <- params.allExuParams) { 81 val fuConfigs = exuCfg.fuConfigs 82 val wbPortConfigs = exuCfg.wbPortConfigs 83 val immType = exuCfg.immType 84 85 println("[Backend] " + 86 s"${exuCfg.name}: " + 87 (if (exuCfg.fakeUnit) "fake, " else "") + 88 (if (exuCfg.hasLoadFu || exuCfg.hasHyldaFu) s"LdExuIdx(${backendParams.getLdExuIdx(exuCfg)})" else "") + 89 s"${fuConfigs.map(_.name).mkString("fu(s): {", ",", "}")}, " + 90 s"${wbPortConfigs.mkString("wb: {", ",", "}")}, " + 91 s"${immType.map(SelImm.mkString(_)).mkString("imm: {", ",", "}")}, " + 92 s"latMax(${exuCfg.latencyValMax}), ${exuCfg.fuLatancySet.mkString("lat: {", ",", "}")}, " + 93 s"srcReg(${exuCfg.numRegSrc})" 94 ) 95 require( 96 wbPortConfigs.collectFirst { case x: IntWB => x }.nonEmpty == 97 fuConfigs.map(_.writeIntRf).reduce(_ || _), 98 s"${exuCfg.name} int wb port has no priority" 99 ) 100 require( 101 wbPortConfigs.collectFirst { case x: FpWB => x }.nonEmpty == 102 fuConfigs.map(x => x.writeFpRf).reduce(_ || _), 103 s"${exuCfg.name} fp wb port has no priority" 104 ) 105 require( 106 wbPortConfigs.collectFirst { case x: VfWB => x }.nonEmpty == 107 fuConfigs.map(x => x.writeVecRf).reduce(_ || _), 108 s"${exuCfg.name} vec wb port has no priority" 109 ) 110 } 111 112 println(s"[Backend] all fu configs") 113 for (cfg <- FuConfig.allConfigs) { 114 println(s"[Backend] $cfg") 115 } 116 117 println(s"[Backend] Int RdConfigs: ExuName(Priority)") 118 for ((port, seq) <- params.getRdPortParams(IntData())) { 119 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 120 } 121 122 println(s"[Backend] Int WbConfigs: ExuName(Priority)") 123 for ((port, seq) <- params.getWbPortParams(IntData())) { 124 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 125 } 126 127 println(s"[Backend] Fp RdConfigs: ExuName(Priority)") 128 for ((port, seq) <- params.getRdPortParams(FpData())) { 129 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 130 } 131 132 println(s"[Backend] Fp WbConfigs: ExuName(Priority)") 133 for ((port, seq) <- params.getWbPortParams(FpData())) { 134 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 135 } 136 137 println(s"[Backend] Vf RdConfigs: ExuName(Priority)") 138 for ((port, seq) <- params.getRdPortParams(VecData())) { 139 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 140 } 141 142 println(s"[Backend] Vf WbConfigs: ExuName(Priority)") 143 for ((port, seq) <- params.getWbPortParams(VecData())) { 144 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 145 } 146 147 println(s"[Backend] Dispatch Configs:") 148 println(s"[Backend] Load IQ enq width(${params.numLoadDp}), Store IQ enq width(${params.numStoreDp})") 149 println(s"[Backend] Load DP width(${LSQLdEnqWidth}), Store DP width(${LSQStEnqWidth})") 150 151 params.updateCopyPdestInfo 152 println(s"[Backend] copyPdestInfo ${params.copyPdestInfo}") 153 params.allExuParams.map(_.copyNum) 154 val ctrlBlock = LazyModule(new CtrlBlock(params)) 155 val pcTargetMem = LazyModule(new PcTargetMem(params)) 156 val intScheduler = params.intSchdParams.map(x => LazyModule(new Scheduler(x))) 157 val fpScheduler = params.fpSchdParams.map(x => LazyModule(new Scheduler(x))) 158 val vfScheduler = params.vfSchdParams.map(x => LazyModule(new Scheduler(x))) 159 val memScheduler = params.memSchdParams.map(x => LazyModule(new Scheduler(x))) 160 val dataPath = LazyModule(new DataPath(params)) 161 val intExuBlock = params.intSchdParams.map(x => LazyModule(new ExuBlock(x))) 162 val fpExuBlock = params.fpSchdParams.map(x => LazyModule(new ExuBlock(x))) 163 val vfExuBlock = params.vfSchdParams.map(x => LazyModule(new ExuBlock(x))) 164 val wbFuBusyTable = LazyModule(new WbFuBusyTable(params)) 165 166 lazy val module = new BackendImp(this) 167} 168 169class BackendImp(override val wrapper: Backend)(implicit p: Parameters) extends LazyModuleImp(wrapper) 170 with HasXSParameter { 171 implicit private val params: BackendParams = wrapper.params 172 173 val io = IO(new BackendIO()(p, wrapper.params)) 174 175 private val ctrlBlock = wrapper.ctrlBlock.module 176 private val pcTargetMem = wrapper.pcTargetMem.module 177 private val intScheduler: SchedulerImpBase = wrapper.intScheduler.get.module 178 private val fpScheduler = wrapper.fpScheduler.get.module 179 private val vfScheduler = wrapper.vfScheduler.get.module 180 private val memScheduler = wrapper.memScheduler.get.module 181 private val dataPath = wrapper.dataPath.module 182 private val intExuBlock = wrapper.intExuBlock.get.module 183 private val fpExuBlock = wrapper.fpExuBlock.get.module 184 private val vfExuBlock = wrapper.vfExuBlock.get.module 185 private val og2ForVector = Module(new Og2ForVector(params)) 186 private val bypassNetwork = Module(new BypassNetwork) 187 private val wbDataPath = Module(new WbDataPath(params)) 188 private val wbFuBusyTable = wrapper.wbFuBusyTable.module 189 190 private val iqWakeUpMappedBundle: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = ( 191 intScheduler.io.toSchedulers.wakeupVec ++ 192 fpScheduler.io.toSchedulers.wakeupVec ++ 193 vfScheduler.io.toSchedulers.wakeupVec ++ 194 memScheduler.io.toSchedulers.wakeupVec 195 ).map(x => (x.bits.exuIdx, x)).toMap 196 197 println(s"[Backend] iq wake up keys: ${iqWakeUpMappedBundle.keys}") 198 199 wbFuBusyTable.io.in.intSchdBusyTable := intScheduler.io.wbFuBusyTable 200 wbFuBusyTable.io.in.fpSchdBusyTable := fpScheduler.io.wbFuBusyTable 201 wbFuBusyTable.io.in.vfSchdBusyTable := vfScheduler.io.wbFuBusyTable 202 wbFuBusyTable.io.in.memSchdBusyTable := memScheduler.io.wbFuBusyTable 203 intScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.intRespRead 204 fpScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.fpRespRead 205 vfScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.vfRespRead 206 memScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.memRespRead 207 dataPath.io.wbConfictRead := wbFuBusyTable.io.out.wbConflictRead 208 209 private val og1CancelOH: UInt = dataPath.io.og1CancelOH 210 private val og0CancelOH: UInt = dataPath.io.og0CancelOH 211 private val cancelToBusyTable = dataPath.io.cancelToBusyTable 212 private val vlIsZero = intExuBlock.io.vlIsZero.get 213 private val vlIsVlmax = intExuBlock.io.vlIsVlmax.get 214 215 ctrlBlock.io.intIQValidNumVec := intScheduler.io.intIQValidNumVec 216 ctrlBlock.io.fpIQValidNumVec := fpScheduler.io.fpIQValidNumVec 217 ctrlBlock.io.fromTop.hartId := io.fromTop.hartId 218 ctrlBlock.io.frontend <> io.frontend 219 ctrlBlock.io.fromCSR.toDecode := intExuBlock.io.csrToDecode.get 220 ctrlBlock.io.fromWB.wbData <> wbDataPath.io.toCtrlBlock.writeback 221 ctrlBlock.io.fromMem.stIn <> io.mem.stIn 222 ctrlBlock.io.fromMem.violation <> io.mem.memoryViolation 223 ctrlBlock.io.lqCanAccept := io.mem.lqCanAccept 224 ctrlBlock.io.sqCanAccept := io.mem.sqCanAccept 225 ctrlBlock.io.csrCtrl <> intExuBlock.io.csrio.get.customCtrl 226 ctrlBlock.io.robio.csr.intrBitSet := intExuBlock.io.csrio.get.interrupt 227 ctrlBlock.io.robio.csr.trapTarget := intExuBlock.io.csrio.get.trapTarget 228 ctrlBlock.io.robio.csr.isXRet := intExuBlock.io.csrio.get.isXRet 229 ctrlBlock.io.robio.csr.wfiEvent := intExuBlock.io.csrio.get.wfi_event 230 ctrlBlock.io.robio.lsq <> io.mem.robLsqIO 231 ctrlBlock.io.robio.lsTopdownInfo <> io.mem.lsTopdownInfo 232 ctrlBlock.io.robio.debug_ls <> io.mem.debugLS 233 ctrlBlock.perfinfo := DontCare // TODO: Implement backend hpm 234 ctrlBlock.io.debugEnqLsq.canAccept := io.mem.lsqEnqIO.canAccept 235 ctrlBlock.io.debugEnqLsq.resp := io.mem.lsqEnqIO.resp 236 ctrlBlock.io.debugEnqLsq.req := memScheduler.io.memIO.get.lsqEnqIO.req 237 ctrlBlock.io.debugEnqLsq.needAlloc := memScheduler.io.memIO.get.lsqEnqIO.needAlloc 238 239 intScheduler.io.fromTop.hartId := io.fromTop.hartId 240 intScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 241 intScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 242 intScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.intUops 243 intScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 244 intScheduler.io.fpWriteBack := 0.U.asTypeOf(intScheduler.io.fpWriteBack) 245 intScheduler.io.vfWriteBack := 0.U.asTypeOf(intScheduler.io.vfWriteBack) 246 intScheduler.io.v0WriteBack := 0.U.asTypeOf(intScheduler.io.v0WriteBack) 247 intScheduler.io.vlWriteBack := 0.U.asTypeOf(intScheduler.io.vlWriteBack) 248 intScheduler.io.fromDataPath.resp := dataPath.io.toIntIQ 249 intScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 250 intScheduler.io.fromDataPath.og0Cancel := og0CancelOH 251 intScheduler.io.fromDataPath.og1Cancel := og1CancelOH 252 intScheduler.io.ldCancel := io.mem.ldCancel 253 intScheduler.io.fromDataPath.cancelToBusyTable := cancelToBusyTable 254 intScheduler.io.vlWriteBackInfo.vlIsZero := false.B 255 intScheduler.io.vlWriteBackInfo.vlIsVlmax := false.B 256 257 fpScheduler.io.fromTop.hartId := io.fromTop.hartId 258 fpScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 259 fpScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 260 fpScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.fpUops 261 fpScheduler.io.intWriteBack := 0.U.asTypeOf(fpScheduler.io.intWriteBack) 262 fpScheduler.io.fpWriteBack := wbDataPath.io.toFpPreg 263 fpScheduler.io.vfWriteBack := 0.U.asTypeOf(fpScheduler.io.vfWriteBack) 264 fpScheduler.io.v0WriteBack := 0.U.asTypeOf(fpScheduler.io.v0WriteBack) 265 fpScheduler.io.vlWriteBack := 0.U.asTypeOf(fpScheduler.io.vlWriteBack) 266 fpScheduler.io.fromDataPath.resp := dataPath.io.toFpIQ 267 fpScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 268 fpScheduler.io.fromDataPath.og0Cancel := og0CancelOH 269 fpScheduler.io.fromDataPath.og1Cancel := og1CancelOH 270 fpScheduler.io.ldCancel := io.mem.ldCancel 271 fpScheduler.io.fromDataPath.cancelToBusyTable := cancelToBusyTable 272 fpScheduler.io.vlWriteBackInfo.vlIsZero := false.B 273 fpScheduler.io.vlWriteBackInfo.vlIsVlmax := false.B 274 275 memScheduler.io.fromTop.hartId := io.fromTop.hartId 276 memScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 277 memScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 278 memScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.memUops 279 memScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 280 memScheduler.io.fpWriteBack := wbDataPath.io.toFpPreg 281 memScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 282 memScheduler.io.v0WriteBack := wbDataPath.io.toV0Preg 283 memScheduler.io.vlWriteBack := wbDataPath.io.toVlPreg 284 memScheduler.io.fromMem.get.scommit := io.mem.sqDeq 285 memScheduler.io.fromMem.get.lcommit := io.mem.lqDeq 286 memScheduler.io.fromMem.get.wakeup := io.mem.wakeup 287 memScheduler.io.fromMem.get.sqDeqPtr := io.mem.sqDeqPtr 288 memScheduler.io.fromMem.get.lqDeqPtr := io.mem.lqDeqPtr 289 memScheduler.io.fromMem.get.sqCancelCnt := io.mem.sqCancelCnt 290 memScheduler.io.fromMem.get.lqCancelCnt := io.mem.lqCancelCnt 291 memScheduler.io.fromMem.get.stIssuePtr := io.mem.stIssuePtr 292 require(memScheduler.io.fromMem.get.memWaitUpdateReq.robIdx.length == io.mem.stIn.length) 293 memScheduler.io.fromMem.get.memWaitUpdateReq.robIdx.zip(io.mem.stIn).foreach { case (sink, source) => 294 sink.valid := source.valid 295 sink.bits := source.bits.robIdx 296 } 297 memScheduler.io.fromMem.get.memWaitUpdateReq.sqIdx := DontCare // TODO 298 memScheduler.io.fromDataPath.resp := dataPath.io.toMemIQ 299 memScheduler.io.fromMem.get.ldaFeedback := io.mem.ldaIqFeedback 300 memScheduler.io.fromMem.get.staFeedback := io.mem.staIqFeedback 301 memScheduler.io.fromMem.get.hyuFeedback := io.mem.hyuIqFeedback 302 memScheduler.io.fromMem.get.vstuFeedback := io.mem.vstuIqFeedback 303 memScheduler.io.fromMem.get.vlduFeedback := io.mem.vlduIqFeedback 304 memScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 305 memScheduler.io.fromDataPath.og0Cancel := og0CancelOH 306 memScheduler.io.fromDataPath.og1Cancel := og1CancelOH 307 memScheduler.io.ldCancel := io.mem.ldCancel 308 memScheduler.io.fromDataPath.cancelToBusyTable := cancelToBusyTable 309 memScheduler.io.vlWriteBackInfo.vlIsZero := vlIsZero 310 memScheduler.io.vlWriteBackInfo.vlIsVlmax := vlIsVlmax 311 312 vfScheduler.io.fromTop.hartId := io.fromTop.hartId 313 vfScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 314 vfScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 315 vfScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.vfUops 316 vfScheduler.io.intWriteBack := 0.U.asTypeOf(vfScheduler.io.intWriteBack) 317 vfScheduler.io.fpWriteBack := 0.U.asTypeOf(vfScheduler.io.fpWriteBack) 318 vfScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 319 vfScheduler.io.v0WriteBack := wbDataPath.io.toV0Preg 320 vfScheduler.io.vlWriteBack := wbDataPath.io.toVlPreg 321 vfScheduler.io.fromDataPath.resp := dataPath.io.toVfIQ 322 vfScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 323 vfScheduler.io.fromDataPath.og0Cancel := og0CancelOH 324 vfScheduler.io.fromDataPath.og1Cancel := og1CancelOH 325 vfScheduler.io.ldCancel := io.mem.ldCancel 326 vfScheduler.io.fromDataPath.cancelToBusyTable := cancelToBusyTable 327 vfScheduler.io.vlWriteBackInfo.vlIsZero := vlIsZero 328 vfScheduler.io.vlWriteBackInfo.vlIsVlmax := vlIsVlmax 329 vfScheduler.io.fromOg2.get := og2ForVector.io.toVfIQ 330 331 dataPath.io.hartId := io.fromTop.hartId 332 dataPath.io.flush := ctrlBlock.io.toDataPath.flush 333 334 dataPath.io.fromIntIQ <> intScheduler.io.toDataPathAfterDelay 335 dataPath.io.fromFpIQ <> fpScheduler.io.toDataPathAfterDelay 336 dataPath.io.fromVfIQ <> vfScheduler.io.toDataPathAfterDelay 337 dataPath.io.fromMemIQ <> memScheduler.io.toDataPathAfterDelay 338 339 dataPath.io.ldCancel := io.mem.ldCancel 340 341 println(s"[Backend] wbDataPath.io.toIntPreg: ${wbDataPath.io.toIntPreg.size}, dataPath.io.fromIntWb: ${dataPath.io.fromIntWb.size}") 342 println(s"[Backend] wbDataPath.io.toVfPreg: ${wbDataPath.io.toVfPreg.size}, dataPath.io.fromFpWb: ${dataPath.io.fromVfWb.size}") 343 dataPath.io.fromIntWb := wbDataPath.io.toIntPreg 344 dataPath.io.fromFpWb := wbDataPath.io.toFpPreg 345 dataPath.io.fromVfWb := wbDataPath.io.toVfPreg 346 dataPath.io.fromV0Wb := wbDataPath.io.toV0Preg 347 dataPath.io.fromVlWb := wbDataPath.io.toVlPreg 348 dataPath.io.debugIntRat .foreach(_ := ctrlBlock.io.debug_int_rat.get) 349 dataPath.io.debugFpRat .foreach(_ := ctrlBlock.io.debug_fp_rat.get) 350 dataPath.io.debugVecRat .foreach(_ := ctrlBlock.io.debug_vec_rat.get) 351 dataPath.io.debugV0Rat .foreach(_ := ctrlBlock.io.debug_v0_rat.get) 352 dataPath.io.debugVlRat .foreach(_ := ctrlBlock.io.debug_vl_rat.get) 353 354 og2ForVector.io.flush := ctrlBlock.io.toDataPath.flush 355 og2ForVector.io.ldCancel := io.mem.ldCancel 356 og2ForVector.io.fromOg1NoReg <> dataPath.io.toVecExu 357 og2ForVector.io.fromOg1ImmInfo := dataPath.io.og1ImmInfo.zip(params.allExuParams).filter(_._2.isVfExeUnit).map(_._1) 358 359 bypassNetwork.io.fromDataPath.int <> dataPath.io.toIntExu 360 bypassNetwork.io.fromDataPath.fp <> dataPath.io.toFpExu 361 bypassNetwork.io.fromDataPath.vf <> og2ForVector.io.toVfExu 362 bypassNetwork.io.fromDataPath.mem <> dataPath.io.toMemExu 363 bypassNetwork.io.fromDataPath.immInfo := dataPath.io.og1ImmInfo 364 bypassNetwork.io.fromDataPath.immInfo.zip(params.allExuParams).filter(_._2.isVfExeUnit).map(_._1).zip(og2ForVector.io.toVfImmInfo).map{ 365 case (vfImmInfo, og2ImmInfo) => vfImmInfo := og2ImmInfo 366 } 367 bypassNetwork.io.fromExus.connectExuOutput(_.int)(intExuBlock.io.out) 368 bypassNetwork.io.fromExus.connectExuOutput(_.fp)(fpExuBlock.io.out) 369 bypassNetwork.io.fromExus.connectExuOutput(_.vf)(vfExuBlock.io.out) 370 371 require(bypassNetwork.io.fromExus.mem.flatten.size == io.mem.writeBack.size, 372 s"bypassNetwork.io.fromExus.mem.flatten.size(${bypassNetwork.io.fromExus.mem.flatten.size}: ${bypassNetwork.io.fromExus.mem.map(_.size)}, " + 373 s"io.mem.writeback(${io.mem.writeBack.size})" 374 ) 375 bypassNetwork.io.fromExus.mem.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 376 sink.valid := source.valid 377 sink.bits.pdest := source.bits.uop.pdest 378 sink.bits.data := source.bits.data 379 } 380 381 382 intExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 383 for (i <- 0 until intExuBlock.io.in.length) { 384 for (j <- 0 until intExuBlock.io.in(i).length) { 385 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.int(i)(j).bits.loadDependency, io.mem.ldCancel) 386 NewPipelineConnect( 387 bypassNetwork.io.toExus.int(i)(j), intExuBlock.io.in(i)(j), intExuBlock.io.in(i)(j).fire, 388 Mux( 389 bypassNetwork.io.toExus.int(i)(j).fire, 390 bypassNetwork.io.toExus.int(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 391 intExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 392 ), 393 Option("bypassNetwork2intExuBlock") 394 ) 395 } 396 } 397 398 pcTargetMem.io.fromFrontendFtq := io.frontend.fromFtq 399 pcTargetMem.io.toDataPath <> dataPath.io.fromPcTargetMem 400 401 private val csrin = intExuBlock.io.csrin.get 402 csrin.hartId := io.fromTop.hartId 403 csrin.msiInfo := io.fromTop.msiInfo 404 csrin.clintTime := io.fromTop.clintTime 405 406 private val csrio = intExuBlock.io.csrio.get 407 csrio.hartId := io.fromTop.hartId 408 csrio.fpu.fflags := ctrlBlock.io.robio.csr.fflags 409 csrio.fpu.isIllegal := false.B // Todo: remove it 410 csrio.fpu.dirty_fs := ctrlBlock.io.robio.csr.dirty_fs 411 csrio.vpu <> WireDefault(0.U.asTypeOf(csrio.vpu)) // Todo 412 413 val fromIntExuVsetVType = intExuBlock.io.vtype.getOrElse(0.U.asTypeOf((Valid(new VType)))) 414 val fromVfExuVsetVType = vfExuBlock.io.vtype.getOrElse(0.U.asTypeOf((Valid(new VType)))) 415 val fromVsetVType = Mux(fromIntExuVsetVType.valid, fromIntExuVsetVType.bits, fromVfExuVsetVType.bits) 416 val vsetvlVType = RegEnable(fromVsetVType, 0.U.asTypeOf(new VType), fromIntExuVsetVType.valid || fromVfExuVsetVType.valid) 417 ctrlBlock.io.toDecode.vsetvlVType := vsetvlVType 418 419 val commitVType = ctrlBlock.io.robio.commitVType.vtype 420 val hasVsetvl = ctrlBlock.io.robio.commitVType.hasVsetvl 421 val vtype = VType.toVtypeStruct(Mux(hasVsetvl, vsetvlVType, commitVType.bits)).asUInt 422 423 // csr not store the value of vl, so when using difftest we assign the value of vl to debugVl 424 val debugVl_s0 = WireInit(UInt(VlData().dataWidth.W), 0.U) 425 val debugVl_s1 = WireInit(UInt(VlData().dataWidth.W), 0.U) 426 debugVl_s0 := dataPath.io.debugVl.getOrElse(0.U.asTypeOf(UInt(VlData().dataWidth.W))) 427 debugVl_s1 := RegNext(debugVl_s0) 428 csrio.vpu.set_vxsat := ctrlBlock.io.robio.csr.vxsat 429 csrio.vpu.set_vstart.valid := ctrlBlock.io.robio.csr.vstart.valid 430 csrio.vpu.set_vstart.bits := ctrlBlock.io.robio.csr.vstart.bits 431 ctrlBlock.io.toDecode.vstart := csrio.vpu.vstart 432 //Todo here need change design 433 csrio.vpu.set_vtype.valid := commitVType.valid 434 csrio.vpu.set_vtype.bits := ZeroExt(vtype, XLEN) 435 csrio.vpu.vl := ZeroExt(debugVl_s1, XLEN) 436 csrio.vpu.dirty_vs := ctrlBlock.io.robio.csr.dirty_vs 437 csrio.exception := ctrlBlock.io.robio.exception 438 csrio.memExceptionVAddr := io.mem.exceptionAddr.vaddr 439 csrio.memExceptionGPAddr := io.mem.exceptionAddr.gpaddr 440 csrio.externalInterrupt := io.fromTop.externalInterrupt 441 csrio.distributedUpdate(0) := io.mem.csrDistributedUpdate 442 csrio.distributedUpdate(1) := io.frontendCsrDistributedUpdate 443 csrio.perf <> io.perf 444 csrio.perf.retiredInstr <> ctrlBlock.io.robio.csr.perfinfo.retiredInstr 445 csrio.perf.ctrlInfo <> ctrlBlock.io.perfInfo.ctrlInfo 446 csrio.perf.perfEventsCtrl <> ctrlBlock.getPerf 447 private val fenceio = intExuBlock.io.fenceio.get 448 io.fenceio <> fenceio 449 private val CSRtoDecode_EX_II = intExuBlock.io.csrToDecode.get 450 fenceio.disableSfence := CSRtoDecode_EX_II.illegalInst.sfenceVMA || CSRtoDecode_EX_II.virtualInst.sfenceVMA 451 fenceio.disableHfenceg := CSRtoDecode_EX_II.illegalInst.hfenceGVMA || CSRtoDecode_EX_II.virtualInst.hfence 452 fenceio.disableHfencev := CSRtoDecode_EX_II.illegalInst.hfenceVVMA || CSRtoDecode_EX_II.virtualInst.hfence 453 454 // to fpExuBlock 455 fpExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 456 for (i <- 0 until fpExuBlock.io.in.length) { 457 for (j <- 0 until fpExuBlock.io.in(i).length) { 458 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.fp(i)(j).bits.loadDependency, io.mem.ldCancel) 459 NewPipelineConnect( 460 bypassNetwork.io.toExus.fp(i)(j), fpExuBlock.io.in(i)(j), fpExuBlock.io.in(i)(j).fire, 461 Mux( 462 bypassNetwork.io.toExus.fp(i)(j).fire, 463 bypassNetwork.io.toExus.fp(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 464 fpExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 465 ), 466 Option("bypassNetwork2fpExuBlock") 467 ) 468 } 469 } 470 471 vfExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 472 for (i <- 0 until vfExuBlock.io.in.size) { 473 for (j <- 0 until vfExuBlock.io.in(i).size) { 474 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.vf(i)(j).bits.loadDependency, io.mem.ldCancel) 475 NewPipelineConnect( 476 bypassNetwork.io.toExus.vf(i)(j), vfExuBlock.io.in(i)(j), vfExuBlock.io.in(i)(j).fire, 477 Mux( 478 bypassNetwork.io.toExus.vf(i)(j).fire, 479 bypassNetwork.io.toExus.vf(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 480 vfExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 481 ), 482 Option("bypassNetwork2vfExuBlock") 483 ) 484 485 } 486 } 487 488 intExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 489 fpExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 490 fpExuBlock.io.vxrm.foreach(_ := csrio.vpu.vxrm) 491 vfExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 492 vfExuBlock.io.vxrm.foreach(_ := csrio.vpu.vxrm) 493 494 wbDataPath.io.flush := ctrlBlock.io.redirect 495 wbDataPath.io.fromTop.hartId := io.fromTop.hartId 496 wbDataPath.io.fromIntExu <> intExuBlock.io.out 497 wbDataPath.io.fromFpExu <> fpExuBlock.io.out 498 wbDataPath.io.fromVfExu <> vfExuBlock.io.out 499 wbDataPath.io.fromMemExu.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 500 sink.valid := source.valid 501 source.ready := sink.ready 502 sink.bits.data := VecInit(Seq.fill(sink.bits.params.wbPathNum)(source.bits.data)) 503 sink.bits.pdest := source.bits.uop.pdest 504 sink.bits.robIdx := source.bits.uop.robIdx 505 sink.bits.intWen.foreach(_ := source.bits.uop.rfWen) 506 sink.bits.fpWen.foreach(_ := source.bits.uop.fpWen) 507 sink.bits.vecWen.foreach(_ := source.bits.uop.vecWen) 508 sink.bits.v0Wen.foreach(_ := source.bits.uop.v0Wen) 509 sink.bits.vlWen.foreach(_ := source.bits.uop.vlWen) 510 sink.bits.exceptionVec.foreach(_ := source.bits.uop.exceptionVec) 511 sink.bits.flushPipe.foreach(_ := source.bits.uop.flushPipe) 512 sink.bits.replay.foreach(_ := source.bits.uop.replayInst) 513 sink.bits.debug := source.bits.debug 514 sink.bits.debugInfo := source.bits.uop.debugInfo 515 sink.bits.lqIdx.foreach(_ := source.bits.uop.lqIdx) 516 sink.bits.sqIdx.foreach(_ := source.bits.uop.sqIdx) 517 sink.bits.predecodeInfo.foreach(_ := source.bits.uop.preDecodeInfo) 518 sink.bits.vls.foreach(x => { 519 x.vdIdx := source.bits.vdIdx.get 520 x.vdIdxInField := source.bits.vdIdxInField.get 521 x.vpu := source.bits.uop.vpu 522 x.oldVdPsrc := source.bits.uop.psrc(2) 523 x.isIndexed := VlduType.isIndexed(source.bits.uop.fuOpType) 524 x.isMasked := VlduType.isMasked(source.bits.uop.fuOpType) 525 }) 526 sink.bits.trigger.foreach(_ := source.bits.uop.trigger) 527 } 528 529 // to mem 530 private val memIssueParams = params.memSchdParams.get.issueBlockParams 531 private val memExuBlocksHasLDU = memIssueParams.map(_.exuBlockParams.map(x => x.hasLoadFu || x.hasHyldaFu)) 532 private val memExuBlocksHasVecLoad = memIssueParams.map(_.exuBlockParams.map(x => x.hasVLoadFu)) 533 println(s"[Backend] memExuBlocksHasLDU: $memExuBlocksHasLDU") 534 println(s"[Backend] memExuBlocksHasVecLoad: $memExuBlocksHasVecLoad") 535 536 private val toMem = Wire(bypassNetwork.io.toExus.mem.cloneType) 537 for (i <- toMem.indices) { 538 for (j <- toMem(i).indices) { 539 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.mem(i)(j).bits.loadDependency, io.mem.ldCancel) 540 val issueTimeout = 541 if (memExuBlocksHasLDU(i)(j)) 542 Counter(0 until 16, toMem(i)(j).valid && !toMem(i)(j).fire, bypassNetwork.io.toExus.mem(i)(j).fire)._2 543 else 544 false.B 545 546 if (memScheduler.io.loadFinalIssueResp(i).nonEmpty && memExuBlocksHasLDU(i)(j)) { 547 memScheduler.io.loadFinalIssueResp(i)(j).valid := issueTimeout 548 memScheduler.io.loadFinalIssueResp(i)(j).bits.fuType := toMem(i)(j).bits.fuType 549 memScheduler.io.loadFinalIssueResp(i)(j).bits.resp := RespType.block 550 memScheduler.io.loadFinalIssueResp(i)(j).bits.robIdx := toMem(i)(j).bits.robIdx 551 memScheduler.io.loadFinalIssueResp(i)(j).bits.uopIdx.foreach(_ := toMem(i)(j).bits.vpu.get.vuopIdx) 552 memScheduler.io.loadFinalIssueResp(i)(j).bits.sqIdx.foreach(_ := toMem(i)(j).bits.sqIdx.get) 553 memScheduler.io.loadFinalIssueResp(i)(j).bits.lqIdx.foreach(_ := toMem(i)(j).bits.lqIdx.get) 554 } 555 556 NewPipelineConnect( 557 bypassNetwork.io.toExus.mem(i)(j), toMem(i)(j), toMem(i)(j).fire, 558 Mux( 559 bypassNetwork.io.toExus.mem(i)(j).fire, 560 bypassNetwork.io.toExus.mem(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 561 toMem(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || issueTimeout 562 ), 563 Option("bypassNetwork2toMemExus") 564 ) 565 566 if (memScheduler.io.memAddrIssueResp(i).nonEmpty && memExuBlocksHasLDU(i)(j)) { 567 memScheduler.io.memAddrIssueResp(i)(j).valid := toMem(i)(j).fire && FuType.isLoad(toMem(i)(j).bits.fuType) 568 memScheduler.io.memAddrIssueResp(i)(j).bits.fuType := toMem(i)(j).bits.fuType 569 memScheduler.io.memAddrIssueResp(i)(j).bits.robIdx := toMem(i)(j).bits.robIdx 570 memScheduler.io.memAddrIssueResp(i)(j).bits.sqIdx.foreach(_ := toMem(i)(j).bits.sqIdx.get) 571 memScheduler.io.memAddrIssueResp(i)(j).bits.lqIdx.foreach(_ := toMem(i)(j).bits.lqIdx.get) 572 memScheduler.io.memAddrIssueResp(i)(j).bits.resp := RespType.success // for load inst, firing at toMem means issuing successfully 573 } 574 575 if (memScheduler.io.vecLoadIssueResp(i).nonEmpty && memExuBlocksHasVecLoad(i)(j)) { 576 memScheduler.io.vecLoadIssueResp(i)(j) match { 577 case resp => 578 resp.valid := toMem(i)(j).fire && VlduType.isVecLd(toMem(i)(j).bits.fuOpType) 579 resp.bits.fuType := toMem(i)(j).bits.fuType 580 resp.bits.robIdx := toMem(i)(j).bits.robIdx 581 resp.bits.uopIdx.get := toMem(i)(j).bits.vpu.get.vuopIdx 582 resp.bits.sqIdx.get := toMem(i)(j).bits.sqIdx.get 583 resp.bits.lqIdx.get := toMem(i)(j).bits.lqIdx.get 584 resp.bits.resp := RespType.success 585 } 586 if (backendParams.debugEn){ 587 dontTouch(memScheduler.io.vecLoadIssueResp(i)(j)) 588 } 589 } 590 } 591 } 592 593 io.mem.redirect := ctrlBlock.io.redirect 594 io.mem.issueUops.zip(toMem.flatten).foreach { case (sink, source) => 595 val enableMdp = Constantin.createRecord("EnableMdp", true) 596 sink.valid := source.valid 597 source.ready := sink.ready 598 sink.bits.iqIdx := source.bits.iqIdx 599 sink.bits.isFirstIssue := source.bits.isFirstIssue 600 sink.bits.uop := 0.U.asTypeOf(sink.bits.uop) 601 sink.bits.src := 0.U.asTypeOf(sink.bits.src) 602 sink.bits.src.zip(source.bits.src).foreach { case (l, r) => l := r} 603 sink.bits.uop.fuType := source.bits.fuType 604 sink.bits.uop.fuOpType := source.bits.fuOpType 605 sink.bits.uop.imm := source.bits.imm 606 sink.bits.uop.robIdx := source.bits.robIdx 607 sink.bits.uop.pdest := source.bits.pdest 608 sink.bits.uop.rfWen := source.bits.rfWen.getOrElse(false.B) 609 sink.bits.uop.fpWen := source.bits.fpWen.getOrElse(false.B) 610 sink.bits.uop.vecWen := source.bits.vecWen.getOrElse(false.B) 611 sink.bits.uop.v0Wen := source.bits.v0Wen.getOrElse(false.B) 612 sink.bits.uop.vlWen := source.bits.vlWen.getOrElse(false.B) 613 sink.bits.uop.flushPipe := source.bits.flushPipe.getOrElse(false.B) 614 sink.bits.uop.pc := source.bits.pc.getOrElse(0.U) 615 sink.bits.uop.loadWaitBit := Mux(enableMdp, source.bits.loadWaitBit.getOrElse(false.B), false.B) 616 sink.bits.uop.waitForRobIdx := Mux(enableMdp, source.bits.waitForRobIdx.getOrElse(0.U.asTypeOf(new RobPtr)), 0.U.asTypeOf(new RobPtr)) 617 sink.bits.uop.storeSetHit := Mux(enableMdp, source.bits.storeSetHit.getOrElse(false.B), false.B) 618 sink.bits.uop.loadWaitStrict := Mux(enableMdp, source.bits.loadWaitStrict.getOrElse(false.B), false.B) 619 sink.bits.uop.ssid := Mux(enableMdp, source.bits.ssid.getOrElse(0.U(SSIDWidth.W)), 0.U(SSIDWidth.W)) 620 sink.bits.uop.lqIdx := source.bits.lqIdx.getOrElse(0.U.asTypeOf(new LqPtr)) 621 sink.bits.uop.sqIdx := source.bits.sqIdx.getOrElse(0.U.asTypeOf(new SqPtr)) 622 sink.bits.uop.ftqPtr := source.bits.ftqIdx.getOrElse(0.U.asTypeOf(new FtqPtr)) 623 sink.bits.uop.ftqOffset := source.bits.ftqOffset.getOrElse(0.U) 624 sink.bits.uop.debugInfo := source.bits.perfDebugInfo 625 sink.bits.uop.vpu := source.bits.vpu.getOrElse(0.U.asTypeOf(new VPUCtrlSignals)) 626 sink.bits.uop.preDecodeInfo := source.bits.preDecode.getOrElse(0.U.asTypeOf(new PreDecodeInfo)) 627 sink.bits.uop.numLsElem := source.bits.numLsElem.getOrElse(0.U) // Todo: remove this bundle, keep only the one below 628 sink.bits.flowNum.foreach(_ := source.bits.numLsElem.get) 629 } 630 io.mem.loadFastMatch := memScheduler.io.toMem.get.loadFastMatch.map(_.fastMatch) 631 io.mem.loadFastImm := memScheduler.io.toMem.get.loadFastMatch.map(_.fastImm) 632 io.mem.tlbCsr := csrio.tlb 633 io.mem.csrCtrl := csrio.customCtrl 634 io.mem.sfence := fenceio.sfence 635 io.mem.isStoreException := CommitType.lsInstIsStore(ctrlBlock.io.robio.exception.bits.commitType) 636 io.mem.isVlsException := ctrlBlock.io.robio.exception.bits.vls 637 require(io.mem.loadPcRead.size == params.LduCnt) 638 io.mem.loadPcRead.zipWithIndex.foreach { case (loadPcRead, i) => 639 loadPcRead := ctrlBlock.io.memLdPcRead(i).data 640 ctrlBlock.io.memLdPcRead(i).vld := io.mem.issueLda(i).valid 641 ctrlBlock.io.memLdPcRead(i).ptr := io.mem.issueLda(i).bits.uop.ftqPtr 642 ctrlBlock.io.memLdPcRead(i).offset := io.mem.issueLda(i).bits.uop.ftqOffset 643 } 644 645 io.mem.storePcRead.zipWithIndex.foreach { case (storePcRead, i) => 646 storePcRead := ctrlBlock.io.memStPcRead(i).data 647 ctrlBlock.io.memStPcRead(i).vld := io.mem.issueSta(i).valid 648 ctrlBlock.io.memStPcRead(i).ptr := io.mem.issueSta(i).bits.uop.ftqPtr 649 ctrlBlock.io.memStPcRead(i).offset := io.mem.issueSta(i).bits.uop.ftqOffset 650 } 651 652 io.mem.hyuPcRead.zipWithIndex.foreach( { case (hyuPcRead, i) => 653 hyuPcRead := ctrlBlock.io.memHyPcRead(i).data 654 ctrlBlock.io.memHyPcRead(i).vld := io.mem.issueHylda(i).valid 655 ctrlBlock.io.memHyPcRead(i).ptr := io.mem.issueHylda(i).bits.uop.ftqPtr 656 ctrlBlock.io.memHyPcRead(i).offset := io.mem.issueHylda(i).bits.uop.ftqOffset 657 }) 658 659 ctrlBlock.io.robio.robHeadLsIssue := io.mem.issueUops.map(deq => deq.fire && deq.bits.uop.robIdx === ctrlBlock.io.robio.robDeqPtr).reduce(_ || _) 660 661 // mem io 662 io.mem.lsqEnqIO <> memScheduler.io.memIO.get.lsqEnqIO 663 io.mem.robLsqIO <> ctrlBlock.io.robio.lsq 664 665 io.frontendSfence := fenceio.sfence 666 io.frontendTlbCsr := csrio.tlb 667 io.frontendCsrCtrl := csrio.customCtrl 668 669 io.tlb <> csrio.tlb 670 671 io.csrCustomCtrl := csrio.customCtrl 672 673 io.toTop.cpuHalted := false.B // TODO: implement cpu halt 674 675 io.debugTopDown.fromRob := ctrlBlock.io.debugTopDown.fromRob 676 ctrlBlock.io.debugTopDown.fromCore := io.debugTopDown.fromCore 677 678 io.debugRolling := ctrlBlock.io.debugRolling 679 680 if(backendParams.debugEn) { 681 dontTouch(memScheduler.io) 682 dontTouch(dataPath.io.toMemExu) 683 dontTouch(wbDataPath.io.fromMemExu) 684 } 685} 686 687class BackendMemIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 688 // Since fast load replay always use load unit 0, Backend flips two load port to avoid conflicts 689 val flippedLda = true 690 // params alias 691 private val LoadQueueSize = VirtualLoadQueueSize 692 // In/Out // Todo: split it into one-direction bundle 693 val lsqEnqIO = Flipped(new LsqEnqIO) 694 val robLsqIO = new RobLsqIO 695 val ldaIqFeedback = Vec(params.LduCnt, Flipped(new MemRSFeedbackIO)) 696 val staIqFeedback = Vec(params.StaCnt, Flipped(new MemRSFeedbackIO)) 697 val hyuIqFeedback = Vec(params.HyuCnt, Flipped(new MemRSFeedbackIO)) 698 val vstuIqFeedback = Flipped(Vec(params.VstuCnt, new MemRSFeedbackIO(isVector = true))) 699 val vlduIqFeedback = Flipped(Vec(params.VlduCnt, new MemRSFeedbackIO(isVector = true))) 700 val ldCancel = Vec(params.LdExuCnt, Flipped(new LoadCancelIO)) 701 val wakeup = Vec(params.LdExuCnt, Flipped(Valid(new DynInst))) 702 val loadPcRead = Vec(params.LduCnt, Output(UInt(VAddrBits.W))) 703 val storePcRead = Vec(params.StaCnt, Output(UInt(VAddrBits.W))) 704 val hyuPcRead = Vec(params.HyuCnt, Output(UInt(VAddrBits.W))) 705 // Input 706 val writebackLda = Vec(params.LduCnt, Flipped(DecoupledIO(new MemExuOutput))) 707 val writebackSta = Vec(params.StaCnt, Flipped(DecoupledIO(new MemExuOutput))) 708 val writebackStd = Vec(params.StdCnt, Flipped(DecoupledIO(new MemExuOutput))) 709 val writebackHyuLda = Vec(params.HyuCnt, Flipped(DecoupledIO(new MemExuOutput))) 710 val writebackHyuSta = Vec(params.HyuCnt, Flipped(DecoupledIO(new MemExuOutput))) 711 val writebackVldu = Vec(params.VlduCnt, Flipped(DecoupledIO(new MemExuOutput(true)))) 712 713 val s3_delayed_load_error = Input(Vec(LoadPipelineWidth, Bool())) 714 val stIn = Input(Vec(params.StaExuCnt, ValidIO(new DynInst()))) 715 val memoryViolation = Flipped(ValidIO(new Redirect)) 716 val exceptionAddr = Input(new Bundle { 717 val vaddr = UInt(VAddrBits.W) 718 val gpaddr = UInt(GPAddrBits.W) 719 }) 720 val sqDeq = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) 721 val lqDeq = Input(UInt(log2Up(CommitWidth + 1).W)) 722 val sqDeqPtr = Input(new SqPtr) 723 val lqDeqPtr = Input(new LqPtr) 724 725 val lqCancelCnt = Input(UInt(log2Up(VirtualLoadQueueSize + 1).W)) 726 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 727 728 val lqCanAccept = Input(Bool()) 729 val sqCanAccept = Input(Bool()) 730 731 val otherFastWakeup = Flipped(Vec(params.LduCnt + params.HyuCnt, ValidIO(new DynInst))) 732 val stIssuePtr = Input(new SqPtr()) 733 734 val csrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 735 736 val debugLS = Flipped(Output(new DebugLSIO)) 737 738 val lsTopdownInfo = Vec(params.LduCnt + params.HyuCnt, Flipped(Output(new LsTopdownInfo))) 739 // Output 740 val redirect = ValidIO(new Redirect) // rob flush MemBlock 741 val issueLda = MixedVec(Seq.fill(params.LduCnt)(DecoupledIO(new MemExuInput()))) 742 val issueSta = MixedVec(Seq.fill(params.StaCnt)(DecoupledIO(new MemExuInput()))) 743 val issueStd = MixedVec(Seq.fill(params.StdCnt)(DecoupledIO(new MemExuInput()))) 744 val issueHylda = MixedVec(Seq.fill(params.HyuCnt)(DecoupledIO(new MemExuInput()))) 745 val issueHysta = MixedVec(Seq.fill(params.HyuCnt)(DecoupledIO(new MemExuInput()))) 746 val issueVldu = MixedVec(Seq.fill(params.VlduCnt)(DecoupledIO(new MemExuInput(true)))) 747 748 val loadFastMatch = Vec(params.LduCnt, Output(UInt(params.LduCnt.W))) 749 val loadFastImm = Vec(params.LduCnt, Output(UInt(12.W))) // Imm_I 750 751 val tlbCsr = Output(new TlbCsrBundle) 752 val csrCtrl = Output(new CustomCSRCtrlIO) 753 val sfence = Output(new SfenceBundle) 754 val isStoreException = Output(Bool()) 755 val isVlsException = Output(Bool()) 756 757 // ATTENTION: The issue ports' sequence order should be the same as IQs' deq config 758 private [backend] def issueUops: Seq[DecoupledIO[MemExuInput]] = { 759 issueSta ++ 760 issueHylda ++ issueHysta ++ 761 issueLda ++ 762 issueVldu ++ 763 issueStd 764 }.toSeq 765 766 // ATTENTION: The writeback ports' sequence order should be the same as IQs' deq config 767 private [backend] def writeBack: Seq[DecoupledIO[MemExuOutput]] = { 768 writebackSta ++ 769 writebackHyuLda ++ writebackHyuSta ++ 770 writebackLda ++ 771 writebackVldu ++ 772 writebackStd 773 } 774} 775 776class BackendIO(implicit p: Parameters, params: BackendParams) extends XSBundle with HasSoCParameter { 777 val fromTop = new Bundle { 778 val hartId = Input(UInt(hartIdLen.W)) 779 val externalInterrupt = new ExternalInterruptIO 780 val msiInfo = Input(ValidIO(new MsiInfoBundle)) 781 val clintTime = Input(ValidIO(UInt(64.W))) 782 } 783 784 val toTop = new Bundle { 785 val cpuHalted = Output(Bool()) 786 } 787 788 val fenceio = new FenceIO 789 // Todo: merge these bundles into BackendFrontendIO 790 val frontend = Flipped(new FrontendToCtrlIO) 791 val frontendSfence = Output(new SfenceBundle) 792 val frontendCsrCtrl = Output(new CustomCSRCtrlIO) 793 val frontendTlbCsr = Output(new TlbCsrBundle) 794 // distributed csr write 795 val frontendCsrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 796 797 val mem = new BackendMemIO 798 799 val perf = Input(new PerfCounterIO) 800 801 val tlb = Output(new TlbCsrBundle) 802 803 val csrCustomCtrl = Output(new CustomCSRCtrlIO) 804 805 val debugTopDown = new Bundle { 806 val fromRob = new RobCoreTopDownIO 807 val fromCore = new CoreDispatchTopDownIO 808 } 809 val debugRolling = new RobDebugRollingIO 810} 811