1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 23import utility.{Constantin, ZeroExt} 24import xiangshan._ 25import xiangshan.backend.Bundles.{DynInst, IssueQueueIQWakeUpBundle, LoadShouldCancel, MemExuInput, MemExuOutput, VPUCtrlSignals} 26import xiangshan.backend.ctrlblock.{DebugLSIO, LsTopdownInfo} 27import xiangshan.backend.datapath.DataConfig.{IntData, VecData, FpData} 28import xiangshan.backend.datapath.RdConfig.{IntRD, VfRD} 29import xiangshan.backend.datapath.WbConfig._ 30import xiangshan.backend.datapath.DataConfig._ 31import xiangshan.backend.datapath._ 32import xiangshan.backend.dispatch.CoreDispatchTopDownIO 33import xiangshan.backend.exu.ExuBlock 34import xiangshan.backend.fu.vector.Bundles.{VConfig, VType} 35import xiangshan.backend.fu.{FenceIO, FenceToSbuffer, FuConfig, FuType, PerfCounterIO} 36import xiangshan.backend.issue.EntryBundles._ 37import xiangshan.backend.issue.{CancelNetwork, Scheduler, SchedulerImpBase} 38import xiangshan.backend.rob.{RobCoreTopDownIO, RobDebugRollingIO, RobLsqIO, RobPtr} 39import xiangshan.frontend.{FtqPtr, FtqRead, PreDecodeInfo} 40import xiangshan.mem.{LqPtr, LsqEnqIO, SqPtr} 41import scala.collection.mutable 42 43class Backend(val params: BackendParams)(implicit p: Parameters) extends LazyModule 44 with HasXSParameter { 45 46 override def shouldBeInlined: Boolean = false 47 48 // check read & write port config 49 params.configChecks 50 51 /* Only update the idx in mem-scheduler here 52 * Idx in other schedulers can be updated the same way if needed 53 * 54 * Also note that we filter out the 'stData issue-queues' when counting 55 */ 56 for ((ibp, idx) <- params.memSchdParams.get.issueBlockParams.filter(iq => iq.StdCnt == 0).zipWithIndex) { 57 ibp.updateIdx(idx) 58 } 59 60 println(params.iqWakeUpParams) 61 62 for ((schdCfg, i) <- params.allSchdParams.zipWithIndex) { 63 schdCfg.bindBackendParam(params) 64 } 65 66 for ((iqCfg, i) <- params.allIssueParams.zipWithIndex) { 67 iqCfg.bindBackendParam(params) 68 } 69 70 for ((exuCfg, i) <- params.allExuParams.zipWithIndex) { 71 exuCfg.bindBackendParam(params) 72 exuCfg.updateIQWakeUpConfigs(params.iqWakeUpParams) 73 exuCfg.updateExuIdx(i) 74 } 75 76 println("[Backend] ExuConfigs:") 77 for (exuCfg <- params.allExuParams) { 78 val fuConfigs = exuCfg.fuConfigs 79 val wbPortConfigs = exuCfg.wbPortConfigs 80 val immType = exuCfg.immType 81 82 println("[Backend] " + 83 s"${exuCfg.name}: " + 84 (if (exuCfg.fakeUnit) "fake, " else "") + 85 (if (exuCfg.hasLoadFu || exuCfg.hasHyldaFu) s"LdExuIdx(${backendParams.getLdExuIdx(exuCfg)})" else "") + 86 s"${fuConfigs.map(_.name).mkString("fu(s): {", ",", "}")}, " + 87 s"${wbPortConfigs.mkString("wb: {", ",", "}")}, " + 88 s"${immType.map(SelImm.mkString(_)).mkString("imm: {", ",", "}")}, " + 89 s"latMax(${exuCfg.latencyValMax}), ${exuCfg.fuLatancySet.mkString("lat: {", ",", "}")}, " + 90 s"srcReg(${exuCfg.numRegSrc})" 91 ) 92 require( 93 wbPortConfigs.collectFirst { case x: IntWB => x }.nonEmpty == 94 fuConfigs.map(_.writeIntRf).reduce(_ || _), 95 s"${exuCfg.name} int wb port has no priority" 96 ) 97 require( 98 wbPortConfigs.collectFirst { case x: FpWB => x }.nonEmpty == 99 fuConfigs.map(x => x.writeFpRf).reduce(_ || _), 100 s"${exuCfg.name} fp wb port has no priority" 101 ) 102 require( 103 wbPortConfigs.collectFirst { case x: VfWB => x }.nonEmpty == 104 fuConfigs.map(x => x.writeVecRf).reduce(_ || _), 105 s"${exuCfg.name} vec wb port has no priority" 106 ) 107 } 108 109 println(s"[Backend] all fu configs") 110 for (cfg <- FuConfig.allConfigs) { 111 println(s"[Backend] $cfg") 112 } 113 114 println(s"[Backend] Int RdConfigs: ExuName(Priority)") 115 for ((port, seq) <- params.getRdPortParams(IntData())) { 116 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 117 } 118 119 println(s"[Backend] Int WbConfigs: ExuName(Priority)") 120 for ((port, seq) <- params.getWbPortParams(IntData())) { 121 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 122 } 123 124 println(s"[Backend] Fp RdConfigs: ExuName(Priority)") 125 for ((port, seq) <- params.getRdPortParams(FpData())) { 126 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 127 } 128 129 println(s"[Backend] Fp WbConfigs: ExuName(Priority)") 130 for ((port, seq) <- params.getWbPortParams(FpData())) { 131 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 132 } 133 134 println(s"[Backend] Vf RdConfigs: ExuName(Priority)") 135 for ((port, seq) <- params.getRdPortParams(VecData())) { 136 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 137 } 138 139 println(s"[Backend] Vf WbConfigs: ExuName(Priority)") 140 for ((port, seq) <- params.getWbPortParams(VecData())) { 141 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 142 } 143 144 println(s"[Backend] Dispatch Configs:") 145 println(s"[Backend] Load IQ enq width(${params.numLoadDp}), Store IQ enq width(${params.numStoreDp})") 146 println(s"[Backend] Load DP width(${LSQLdEnqWidth}), Store DP width(${LSQStEnqWidth})") 147 148 params.updateCopyPdestInfo 149 println(s"[Backend] copyPdestInfo ${params.copyPdestInfo}") 150 params.allExuParams.map(_.copyNum) 151 val ctrlBlock = LazyModule(new CtrlBlock(params)) 152 val pcTargetMem = LazyModule(new PcTargetMem(params)) 153 val intScheduler = params.intSchdParams.map(x => LazyModule(new Scheduler(x))) 154 val fpScheduler = params.fpSchdParams.map(x => LazyModule(new Scheduler(x))) 155 val vfScheduler = params.vfSchdParams.map(x => LazyModule(new Scheduler(x))) 156 val memScheduler = params.memSchdParams.map(x => LazyModule(new Scheduler(x))) 157 val dataPath = LazyModule(new DataPath(params)) 158 val intExuBlock = params.intSchdParams.map(x => LazyModule(new ExuBlock(x))) 159 val fpExuBlock = params.fpSchdParams.map(x => LazyModule(new ExuBlock(x))) 160 val vfExuBlock = params.vfSchdParams.map(x => LazyModule(new ExuBlock(x))) 161 val wbFuBusyTable = LazyModule(new WbFuBusyTable(params)) 162 163 lazy val module = new BackendImp(this) 164} 165 166class BackendImp(override val wrapper: Backend)(implicit p: Parameters) extends LazyModuleImp(wrapper) 167 with HasXSParameter { 168 implicit private val params = wrapper.params 169 170 val io = IO(new BackendIO()(p, wrapper.params)) 171 172 private val ctrlBlock = wrapper.ctrlBlock.module 173 private val pcTargetMem = wrapper.pcTargetMem.module 174 private val intScheduler: SchedulerImpBase = wrapper.intScheduler.get.module 175 private val fpScheduler = wrapper.fpScheduler.get.module 176 private val vfScheduler = wrapper.vfScheduler.get.module 177 private val memScheduler = wrapper.memScheduler.get.module 178 private val dataPath = wrapper.dataPath.module 179 private val intExuBlock = wrapper.intExuBlock.get.module 180 private val fpExuBlock = wrapper.fpExuBlock.get.module 181 private val vfExuBlock = wrapper.vfExuBlock.get.module 182 private val og2ForVector = Module(new Og2ForVector(params)) 183 private val bypassNetwork = Module(new BypassNetwork) 184 private val wbDataPath = Module(new WbDataPath(params)) 185 private val wbFuBusyTable = wrapper.wbFuBusyTable.module 186 187 private val iqWakeUpMappedBundle: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = ( 188 intScheduler.io.toSchedulers.wakeupVec ++ 189 fpScheduler.io.toSchedulers.wakeupVec ++ 190 vfScheduler.io.toSchedulers.wakeupVec ++ 191 memScheduler.io.toSchedulers.wakeupVec 192 ).map(x => (x.bits.exuIdx, x)).toMap 193 194 println(s"[Backend] iq wake up keys: ${iqWakeUpMappedBundle.keys}") 195 196 wbFuBusyTable.io.in.intSchdBusyTable := intScheduler.io.wbFuBusyTable 197 wbFuBusyTable.io.in.fpSchdBusyTable := fpScheduler.io.wbFuBusyTable 198 wbFuBusyTable.io.in.vfSchdBusyTable := vfScheduler.io.wbFuBusyTable 199 wbFuBusyTable.io.in.memSchdBusyTable := memScheduler.io.wbFuBusyTable 200 intScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.intRespRead 201 fpScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.fpRespRead 202 vfScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.vfRespRead 203 memScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.memRespRead 204 dataPath.io.wbConfictRead := wbFuBusyTable.io.out.wbConflictRead 205 206 private val og1CancelOH: UInt = dataPath.io.og1CancelOH 207 private val og0CancelOH: UInt = dataPath.io.og0CancelOH 208 private val cancelToBusyTable = dataPath.io.cancelToBusyTable 209 private val vlIsZero = intExuBlock.io.vlIsZero.get 210 private val vlIsVlmax = intExuBlock.io.vlIsVlmax.get 211 212 ctrlBlock.io.intIQValidNumVec := intScheduler.io.intIQValidNumVec 213 ctrlBlock.io.fpIQValidNumVec := fpScheduler.io.fpIQValidNumVec 214 ctrlBlock.io.fromTop.hartId := io.fromTop.hartId 215 ctrlBlock.io.frontend <> io.frontend 216 ctrlBlock.io.fromWB.wbData <> wbDataPath.io.toCtrlBlock.writeback 217 ctrlBlock.io.fromMem.stIn <> io.mem.stIn 218 ctrlBlock.io.fromMem.violation <> io.mem.memoryViolation 219 ctrlBlock.io.lqCanAccept := io.mem.lqCanAccept 220 ctrlBlock.io.sqCanAccept := io.mem.sqCanAccept 221 ctrlBlock.io.csrCtrl <> intExuBlock.io.csrio.get.customCtrl 222 ctrlBlock.io.robio.csr.intrBitSet := intExuBlock.io.csrio.get.interrupt 223 ctrlBlock.io.robio.csr.trapTarget := intExuBlock.io.csrio.get.trapTarget 224 ctrlBlock.io.robio.csr.isXRet := intExuBlock.io.csrio.get.isXRet 225 ctrlBlock.io.robio.csr.wfiEvent := intExuBlock.io.csrio.get.wfi_event 226 ctrlBlock.io.robio.lsq <> io.mem.robLsqIO 227 ctrlBlock.io.robio.lsTopdownInfo <> io.mem.lsTopdownInfo 228 ctrlBlock.io.robio.debug_ls <> io.mem.debugLS 229 ctrlBlock.perfinfo := DontCare // TODO: Implement backend hpm 230 ctrlBlock.io.debugEnqLsq.canAccept := io.mem.lsqEnqIO.canAccept 231 ctrlBlock.io.debugEnqLsq.resp := io.mem.lsqEnqIO.resp 232 ctrlBlock.io.debugEnqLsq.req := memScheduler.io.memIO.get.lsqEnqIO.req 233 ctrlBlock.io.debugEnqLsq.needAlloc := memScheduler.io.memIO.get.lsqEnqIO.needAlloc 234 235 intScheduler.io.fromTop.hartId := io.fromTop.hartId 236 intScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 237 intScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 238 intScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.intUops 239 intScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 240 intScheduler.io.fpWriteBack := 0.U.asTypeOf(intScheduler.io.fpWriteBack) 241 intScheduler.io.vfWriteBack := 0.U.asTypeOf(intScheduler.io.vfWriteBack) 242 intScheduler.io.v0WriteBack := 0.U.asTypeOf(intScheduler.io.v0WriteBack) 243 intScheduler.io.vlWriteBack := 0.U.asTypeOf(intScheduler.io.vlWriteBack) 244 intScheduler.io.fromDataPath.resp := dataPath.io.toIntIQ 245 intScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 246 intScheduler.io.fromDataPath.og0Cancel := og0CancelOH 247 intScheduler.io.fromDataPath.og1Cancel := og1CancelOH 248 intScheduler.io.ldCancel := io.mem.ldCancel 249 intScheduler.io.fromDataPath.cancelToBusyTable := cancelToBusyTable 250 intScheduler.io.vlWriteBackInfo.vlIsZero := false.B 251 intScheduler.io.vlWriteBackInfo.vlIsVlmax := false.B 252 253 fpScheduler.io.fromTop.hartId := io.fromTop.hartId 254 fpScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 255 fpScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 256 fpScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.fpUops 257 fpScheduler.io.intWriteBack := 0.U.asTypeOf(fpScheduler.io.intWriteBack) 258 fpScheduler.io.fpWriteBack := wbDataPath.io.toFpPreg 259 fpScheduler.io.vfWriteBack := 0.U.asTypeOf(fpScheduler.io.vfWriteBack) 260 fpScheduler.io.v0WriteBack := 0.U.asTypeOf(fpScheduler.io.v0WriteBack) 261 fpScheduler.io.vlWriteBack := 0.U.asTypeOf(fpScheduler.io.vlWriteBack) 262 fpScheduler.io.fromDataPath.resp := dataPath.io.toFpIQ 263 fpScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 264 fpScheduler.io.fromDataPath.og0Cancel := og0CancelOH 265 fpScheduler.io.fromDataPath.og1Cancel := og1CancelOH 266 fpScheduler.io.ldCancel := io.mem.ldCancel 267 fpScheduler.io.fromDataPath.cancelToBusyTable := cancelToBusyTable 268 fpScheduler.io.vlWriteBackInfo.vlIsZero := false.B 269 fpScheduler.io.vlWriteBackInfo.vlIsVlmax := false.B 270 271 memScheduler.io.fromTop.hartId := io.fromTop.hartId 272 memScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 273 memScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 274 memScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.memUops 275 memScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 276 memScheduler.io.fpWriteBack := wbDataPath.io.toFpPreg 277 memScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 278 memScheduler.io.v0WriteBack := wbDataPath.io.toV0Preg 279 memScheduler.io.vlWriteBack := wbDataPath.io.toVlPreg 280 memScheduler.io.fromMem.get.scommit := io.mem.sqDeq 281 memScheduler.io.fromMem.get.lcommit := io.mem.lqDeq 282 memScheduler.io.fromMem.get.wakeup := io.mem.wakeup 283 memScheduler.io.fromMem.get.sqDeqPtr := io.mem.sqDeqPtr 284 memScheduler.io.fromMem.get.lqDeqPtr := io.mem.lqDeqPtr 285 memScheduler.io.fromMem.get.sqCancelCnt := io.mem.sqCancelCnt 286 memScheduler.io.fromMem.get.lqCancelCnt := io.mem.lqCancelCnt 287 memScheduler.io.fromMem.get.stIssuePtr := io.mem.stIssuePtr 288 require(memScheduler.io.fromMem.get.memWaitUpdateReq.robIdx.length == io.mem.stIn.length) 289 memScheduler.io.fromMem.get.memWaitUpdateReq.robIdx.zip(io.mem.stIn).foreach { case (sink, source) => 290 sink.valid := source.valid 291 sink.bits := source.bits.robIdx 292 } 293 memScheduler.io.fromMem.get.memWaitUpdateReq.sqIdx := DontCare // TODO 294 memScheduler.io.fromDataPath.resp := dataPath.io.toMemIQ 295 memScheduler.io.fromMem.get.ldaFeedback := io.mem.ldaIqFeedback 296 memScheduler.io.fromMem.get.staFeedback := io.mem.staIqFeedback 297 memScheduler.io.fromMem.get.hyuFeedback := io.mem.hyuIqFeedback 298 memScheduler.io.fromMem.get.vstuFeedback := io.mem.vstuIqFeedback 299 memScheduler.io.fromMem.get.vlduFeedback := io.mem.vlduIqFeedback 300 memScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 301 memScheduler.io.fromDataPath.og0Cancel := og0CancelOH 302 memScheduler.io.fromDataPath.og1Cancel := og1CancelOH 303 memScheduler.io.ldCancel := io.mem.ldCancel 304 memScheduler.io.fromDataPath.cancelToBusyTable := cancelToBusyTable 305 memScheduler.io.vlWriteBackInfo.vlIsZero := vlIsZero 306 memScheduler.io.vlWriteBackInfo.vlIsVlmax := vlIsVlmax 307 308 vfScheduler.io.fromTop.hartId := io.fromTop.hartId 309 vfScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 310 vfScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 311 vfScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.vfUops 312 vfScheduler.io.intWriteBack := 0.U.asTypeOf(vfScheduler.io.intWriteBack) 313 vfScheduler.io.fpWriteBack := 0.U.asTypeOf(vfScheduler.io.fpWriteBack) 314 vfScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 315 vfScheduler.io.v0WriteBack := wbDataPath.io.toV0Preg 316 vfScheduler.io.vlWriteBack := wbDataPath.io.toVlPreg 317 vfScheduler.io.fromDataPath.resp := dataPath.io.toVfIQ 318 vfScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 319 vfScheduler.io.fromDataPath.og0Cancel := og0CancelOH 320 vfScheduler.io.fromDataPath.og1Cancel := og1CancelOH 321 vfScheduler.io.ldCancel := io.mem.ldCancel 322 vfScheduler.io.fromDataPath.cancelToBusyTable := cancelToBusyTable 323 vfScheduler.io.vlWriteBackInfo.vlIsZero := vlIsZero 324 vfScheduler.io.vlWriteBackInfo.vlIsVlmax := vlIsVlmax 325 vfScheduler.io.fromOg2.get := og2ForVector.io.toVfIQ 326 327 dataPath.io.hartId := io.fromTop.hartId 328 dataPath.io.flush := ctrlBlock.io.toDataPath.flush 329 330 dataPath.io.fromIntIQ <> intScheduler.io.toDataPathAfterDelay 331 dataPath.io.fromFpIQ <> fpScheduler.io.toDataPathAfterDelay 332 dataPath.io.fromVfIQ <> vfScheduler.io.toDataPathAfterDelay 333 dataPath.io.fromMemIQ <> memScheduler.io.toDataPathAfterDelay 334 335 dataPath.io.ldCancel := io.mem.ldCancel 336 337 println(s"[Backend] wbDataPath.io.toIntPreg: ${wbDataPath.io.toIntPreg.size}, dataPath.io.fromIntWb: ${dataPath.io.fromIntWb.size}") 338 println(s"[Backend] wbDataPath.io.toVfPreg: ${wbDataPath.io.toVfPreg.size}, dataPath.io.fromFpWb: ${dataPath.io.fromVfWb.size}") 339 dataPath.io.fromIntWb := wbDataPath.io.toIntPreg 340 dataPath.io.fromFpWb := wbDataPath.io.toFpPreg 341 dataPath.io.fromVfWb := wbDataPath.io.toVfPreg 342 dataPath.io.fromV0Wb := wbDataPath.io.toV0Preg 343 dataPath.io.fromVlWb := wbDataPath.io.toVlPreg 344 dataPath.io.debugIntRat .foreach(_ := ctrlBlock.io.debug_int_rat.get) 345 dataPath.io.debugFpRat .foreach(_ := ctrlBlock.io.debug_fp_rat.get) 346 dataPath.io.debugVecRat .foreach(_ := ctrlBlock.io.debug_vec_rat.get) 347 dataPath.io.debugV0Rat .foreach(_ := ctrlBlock.io.debug_v0_rat.get) 348 dataPath.io.debugVlRat .foreach(_ := ctrlBlock.io.debug_vl_rat.get) 349 350 og2ForVector.io.flush := ctrlBlock.io.toDataPath.flush 351 og2ForVector.io.ldCancel := io.mem.ldCancel 352 og2ForVector.io.fromOg1NoReg <> dataPath.io.toVecExu 353 354 bypassNetwork.io.fromDataPath.int <> dataPath.io.toIntExu 355 bypassNetwork.io.fromDataPath.fp <> dataPath.io.toFpExu 356 bypassNetwork.io.fromDataPath.vf <> og2ForVector.io.toVfExu 357 bypassNetwork.io.fromDataPath.mem <> dataPath.io.toMemExu 358 bypassNetwork.io.fromDataPath.immInfo := dataPath.io.og1ImmInfo 359 bypassNetwork.io.fromExus.connectExuOutput(_.int)(intExuBlock.io.out) 360 bypassNetwork.io.fromExus.connectExuOutput(_.fp)(fpExuBlock.io.out) 361 bypassNetwork.io.fromExus.connectExuOutput(_.vf)(vfExuBlock.io.out) 362 363 require(bypassNetwork.io.fromExus.mem.flatten.size == io.mem.writeBack.size, 364 s"bypassNetwork.io.fromExus.mem.flatten.size(${bypassNetwork.io.fromExus.mem.flatten.size}: ${bypassNetwork.io.fromExus.mem.map(_.size)}, " + 365 s"io.mem.writeback(${io.mem.writeBack.size})" 366 ) 367 bypassNetwork.io.fromExus.mem.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 368 sink.valid := source.valid 369 sink.bits.pdest := source.bits.uop.pdest 370 sink.bits.data := source.bits.data 371 } 372 373 374 intExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 375 for (i <- 0 until intExuBlock.io.in.length) { 376 for (j <- 0 until intExuBlock.io.in(i).length) { 377 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.int(i)(j).bits.loadDependency, io.mem.ldCancel) 378 NewPipelineConnect( 379 bypassNetwork.io.toExus.int(i)(j), intExuBlock.io.in(i)(j), intExuBlock.io.in(i)(j).fire, 380 Mux( 381 bypassNetwork.io.toExus.int(i)(j).fire, 382 bypassNetwork.io.toExus.int(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 383 intExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 384 ), 385 Option("bypassNetwork2intExuBlock") 386 ) 387 } 388 } 389 390 pcTargetMem.io.fromFrontendFtq := io.frontend.fromFtq 391 pcTargetMem.io.toDataPath <> dataPath.io.fromPcTargetMem 392 393 private val csrio = intExuBlock.io.csrio.get 394 csrio.hartId := io.fromTop.hartId 395 csrio.fpu.fflags := ctrlBlock.io.robio.csr.fflags 396 csrio.fpu.isIllegal := false.B // Todo: remove it 397 csrio.fpu.dirty_fs := ctrlBlock.io.robio.csr.dirty_fs 398 csrio.vpu <> 0.U.asTypeOf(csrio.vpu) // Todo 399 400 val fromIntExuVsetVType = intExuBlock.io.vtype.getOrElse(0.U.asTypeOf((Valid(new VType)))) 401 val fromVfExuVsetVType = vfExuBlock.io.vtype.getOrElse(0.U.asTypeOf((Valid(new VType)))) 402 val fromVsetVType = Mux(fromIntExuVsetVType.valid, fromIntExuVsetVType.bits, fromVfExuVsetVType.bits) 403 val vsetvlVType = RegEnable(fromVsetVType, 0.U.asTypeOf(new VType), fromIntExuVsetVType.valid || fromVfExuVsetVType.valid) 404 ctrlBlock.io.toDecode.vsetvlVType := vsetvlVType 405 406 val commitVType = ctrlBlock.io.robio.commitVType.vtype 407 val hasVsetvl = ctrlBlock.io.robio.commitVType.hasVsetvl 408 val vtype = VType.toVtypeStruct(Mux(hasVsetvl, vsetvlVType, commitVType.bits)).asUInt 409 410 // csr not store the value of vl, so when using difftest we assign the value of vl to debugVl 411 val debugVl_s0 = WireInit(UInt(VlData().dataWidth.W), 0.U) 412 val debugVl_s1 = WireInit(UInt(VlData().dataWidth.W), 0.U) 413 debugVl_s0 := dataPath.io.debugVl.getOrElse(0.U.asTypeOf(UInt(VlData().dataWidth.W))) 414 debugVl_s1 := RegNext(debugVl_s0) 415 csrio.vpu.set_vxsat := ctrlBlock.io.robio.csr.vxsat 416 csrio.vpu.set_vstart.valid := ctrlBlock.io.robio.csr.vstart.valid 417 csrio.vpu.set_vstart.bits := ctrlBlock.io.robio.csr.vstart.bits 418 //Todo here need change design 419 csrio.vpu.set_vtype.valid := commitVType.valid 420 csrio.vpu.set_vtype.bits := ZeroExt(vtype, XLEN) 421 csrio.vpu.vl := ZeroExt(debugVl_s1, XLEN) 422 csrio.vpu.dirty_vs := ctrlBlock.io.robio.csr.dirty_vs 423 csrio.exception := ctrlBlock.io.robio.exception 424 csrio.memExceptionVAddr := io.mem.exceptionAddr.vaddr 425 csrio.memExceptionGPAddr := io.mem.exceptionAddr.gpaddr 426 csrio.externalInterrupt := io.fromTop.externalInterrupt 427 csrio.distributedUpdate(0) := io.mem.csrDistributedUpdate 428 csrio.distributedUpdate(1) := io.frontendCsrDistributedUpdate 429 csrio.perf <> io.perf 430 csrio.perf.retiredInstr <> ctrlBlock.io.robio.csr.perfinfo.retiredInstr 431 csrio.perf.ctrlInfo <> ctrlBlock.io.perfInfo.ctrlInfo 432 csrio.perf.perfEventsCtrl <> ctrlBlock.getPerf 433 private val fenceio = intExuBlock.io.fenceio.get 434 io.fenceio <> fenceio 435 fenceio.disableSfence := csrio.disableSfence 436 fenceio.disableHfenceg := csrio.disableHfenceg 437 fenceio.disableHfencev := csrio.disableHfencev 438 fenceio.virtMode := csrio.customCtrl.virtMode 439 440 // to fpExuBlock 441 fpExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 442 for (i <- 0 until fpExuBlock.io.in.length) { 443 for (j <- 0 until fpExuBlock.io.in(i).length) { 444 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.fp(i)(j).bits.loadDependency, io.mem.ldCancel) 445 NewPipelineConnect( 446 bypassNetwork.io.toExus.fp(i)(j), fpExuBlock.io.in(i)(j), fpExuBlock.io.in(i)(j).fire, 447 Mux( 448 bypassNetwork.io.toExus.fp(i)(j).fire, 449 bypassNetwork.io.toExus.fp(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 450 fpExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 451 ), 452 Option("bypassNetwork2fpExuBlock") 453 ) 454 } 455 } 456 457 vfExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 458 for (i <- 0 until vfExuBlock.io.in.size) { 459 for (j <- 0 until vfExuBlock.io.in(i).size) { 460 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.vf(i)(j).bits.loadDependency, io.mem.ldCancel) 461 NewPipelineConnect( 462 bypassNetwork.io.toExus.vf(i)(j), vfExuBlock.io.in(i)(j), vfExuBlock.io.in(i)(j).fire, 463 Mux( 464 bypassNetwork.io.toExus.vf(i)(j).fire, 465 bypassNetwork.io.toExus.vf(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 466 vfExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 467 ), 468 Option("bypassNetwork2vfExuBlock") 469 ) 470 471 vfExuBlock.io.in(i)(j).bits.vpu.foreach(_.vstart := csrio.vpu.vstart) 472 } 473 } 474 475 intExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 476 fpExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 477 fpExuBlock.io.vxrm.foreach(_ := csrio.vpu.vxrm) 478 vfExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 479 vfExuBlock.io.vxrm.foreach(_ := csrio.vpu.vxrm) 480 481 wbDataPath.io.flush := ctrlBlock.io.redirect 482 wbDataPath.io.fromTop.hartId := io.fromTop.hartId 483 wbDataPath.io.fromIntExu <> intExuBlock.io.out 484 wbDataPath.io.fromFpExu <> fpExuBlock.io.out 485 wbDataPath.io.fromVfExu <> vfExuBlock.io.out 486 wbDataPath.io.fromMemExu.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 487 sink.valid := source.valid 488 source.ready := sink.ready 489 sink.bits.data := VecInit(Seq.fill(sink.bits.params.wbPathNum)(source.bits.data)) 490 sink.bits.pdest := source.bits.uop.pdest 491 sink.bits.robIdx := source.bits.uop.robIdx 492 sink.bits.intWen.foreach(_ := source.bits.uop.rfWen) 493 sink.bits.fpWen.foreach(_ := source.bits.uop.fpWen) 494 sink.bits.vecWen.foreach(_ := source.bits.uop.vecWen) 495 sink.bits.v0Wen.foreach(_ := source.bits.uop.v0Wen) 496 sink.bits.vlWen.foreach(_ := source.bits.uop.vlWen) 497 sink.bits.exceptionVec.foreach(_ := source.bits.uop.exceptionVec) 498 sink.bits.flushPipe.foreach(_ := source.bits.uop.flushPipe) 499 sink.bits.replay.foreach(_ := source.bits.uop.replayInst) 500 sink.bits.debug := source.bits.debug 501 sink.bits.debugInfo := source.bits.uop.debugInfo 502 sink.bits.lqIdx.foreach(_ := source.bits.uop.lqIdx) 503 sink.bits.sqIdx.foreach(_ := source.bits.uop.sqIdx) 504 sink.bits.predecodeInfo.foreach(_ := source.bits.uop.preDecodeInfo) 505 sink.bits.vls.foreach(x => { 506 x.vdIdx := source.bits.vdIdx.get 507 x.vdIdxInField := source.bits.vdIdxInField.get 508 x.vpu := source.bits.uop.vpu 509 x.oldVdPsrc := source.bits.uop.psrc(2) 510 x.isIndexed := VlduType.isIndexed(source.bits.uop.fuOpType) 511 x.isMasked := VlduType.isMasked(source.bits.uop.fuOpType) 512 }) 513 sink.bits.trigger.foreach(_ := source.bits.uop.trigger) 514 } 515 516 // to mem 517 private val memIssueParams = params.memSchdParams.get.issueBlockParams 518 private val memExuBlocksHasLDU = memIssueParams.map(_.exuBlockParams.map(x => x.hasLoadFu || x.hasHyldaFu)) 519 private val memExuBlocksHasVecLoad = memIssueParams.map(_.exuBlockParams.map(x => x.hasVLoadFu)) 520 println(s"[Backend] memExuBlocksHasLDU: $memExuBlocksHasLDU") 521 println(s"[Backend] memExuBlocksHasVecLoad: $memExuBlocksHasVecLoad") 522 523 private val toMem = Wire(bypassNetwork.io.toExus.mem.cloneType) 524 for (i <- toMem.indices) { 525 for (j <- toMem(i).indices) { 526 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.mem(i)(j).bits.loadDependency, io.mem.ldCancel) 527 val issueTimeout = 528 if (memExuBlocksHasLDU(i)(j)) 529 Counter(0 until 16, toMem(i)(j).valid && !toMem(i)(j).fire, bypassNetwork.io.toExus.mem(i)(j).fire)._2 530 else 531 false.B 532 533 if (memScheduler.io.loadFinalIssueResp(i).nonEmpty && memExuBlocksHasLDU(i)(j)) { 534 memScheduler.io.loadFinalIssueResp(i)(j).valid := issueTimeout 535 memScheduler.io.loadFinalIssueResp(i)(j).bits.fuType := toMem(i)(j).bits.fuType 536 memScheduler.io.loadFinalIssueResp(i)(j).bits.resp := RespType.block 537 memScheduler.io.loadFinalIssueResp(i)(j).bits.robIdx := toMem(i)(j).bits.robIdx 538 memScheduler.io.loadFinalIssueResp(i)(j).bits.uopIdx.foreach(_ := toMem(i)(j).bits.vpu.get.vuopIdx) 539 } 540 541 NewPipelineConnect( 542 bypassNetwork.io.toExus.mem(i)(j), toMem(i)(j), toMem(i)(j).fire, 543 Mux( 544 bypassNetwork.io.toExus.mem(i)(j).fire, 545 bypassNetwork.io.toExus.mem(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 546 toMem(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || issueTimeout 547 ), 548 Option("bypassNetwork2toMemExus") 549 ) 550 551 if (memScheduler.io.memAddrIssueResp(i).nonEmpty && memExuBlocksHasLDU(i)(j)) { 552 memScheduler.io.memAddrIssueResp(i)(j).valid := toMem(i)(j).fire && FuType.isLoad(toMem(i)(j).bits.fuType) 553 memScheduler.io.memAddrIssueResp(i)(j).bits.fuType := toMem(i)(j).bits.fuType 554 memScheduler.io.memAddrIssueResp(i)(j).bits.robIdx := toMem(i)(j).bits.robIdx 555 memScheduler.io.memAddrIssueResp(i)(j).bits.resp := RespType.success // for load inst, firing at toMem means issuing successfully 556 } 557 558 if (memScheduler.io.vecLoadIssueResp(i).nonEmpty && memExuBlocksHasVecLoad(i)(j)) { 559 memScheduler.io.vecLoadIssueResp(i)(j) match { 560 case resp => 561 resp.valid := toMem(i)(j).fire && LSUOpType.isVecLd(toMem(i)(j).bits.fuOpType) 562 resp.bits.fuType := toMem(i)(j).bits.fuType 563 resp.bits.robIdx := toMem(i)(j).bits.robIdx 564 resp.bits.uopIdx.get := toMem(i)(j).bits.vpu.get.vuopIdx 565 resp.bits.resp := RespType.success 566 } 567 dontTouch(memScheduler.io.vecLoadIssueResp(i)(j)) 568 } 569 } 570 } 571 572 io.mem.redirect := ctrlBlock.io.redirect 573 io.mem.issueUops.zip(toMem.flatten).foreach { case (sink, source) => 574 val enableMdp = Constantin.createRecord("EnableMdp", true) 575 sink.valid := source.valid 576 source.ready := sink.ready 577 sink.bits.iqIdx := source.bits.iqIdx 578 sink.bits.isFirstIssue := source.bits.isFirstIssue 579 sink.bits.uop := 0.U.asTypeOf(sink.bits.uop) 580 sink.bits.src := 0.U.asTypeOf(sink.bits.src) 581 sink.bits.src.zip(source.bits.src).foreach { case (l, r) => l := r} 582 sink.bits.uop.fuType := source.bits.fuType 583 sink.bits.uop.fuOpType := source.bits.fuOpType 584 sink.bits.uop.imm := source.bits.imm 585 sink.bits.uop.robIdx := source.bits.robIdx 586 sink.bits.uop.pdest := source.bits.pdest 587 sink.bits.uop.rfWen := source.bits.rfWen.getOrElse(false.B) 588 sink.bits.uop.fpWen := source.bits.fpWen.getOrElse(false.B) 589 sink.bits.uop.vecWen := source.bits.vecWen.getOrElse(false.B) 590 sink.bits.uop.v0Wen := source.bits.v0Wen.getOrElse(false.B) 591 sink.bits.uop.vlWen := source.bits.vlWen.getOrElse(false.B) 592 sink.bits.uop.flushPipe := source.bits.flushPipe.getOrElse(false.B) 593 sink.bits.uop.pc := source.bits.pc.getOrElse(0.U) 594 sink.bits.uop.loadWaitBit := Mux(enableMdp, source.bits.loadWaitBit.getOrElse(false.B), false.B) 595 sink.bits.uop.waitForRobIdx := Mux(enableMdp, source.bits.waitForRobIdx.getOrElse(0.U.asTypeOf(new RobPtr)), 0.U.asTypeOf(new RobPtr)) 596 sink.bits.uop.storeSetHit := Mux(enableMdp, source.bits.storeSetHit.getOrElse(false.B), false.B) 597 sink.bits.uop.loadWaitStrict := Mux(enableMdp, source.bits.loadWaitStrict.getOrElse(false.B), false.B) 598 sink.bits.uop.ssid := Mux(enableMdp, source.bits.ssid.getOrElse(0.U(SSIDWidth.W)), 0.U(SSIDWidth.W)) 599 sink.bits.uop.lqIdx := source.bits.lqIdx.getOrElse(0.U.asTypeOf(new LqPtr)) 600 sink.bits.uop.sqIdx := source.bits.sqIdx.getOrElse(0.U.asTypeOf(new SqPtr)) 601 sink.bits.uop.ftqPtr := source.bits.ftqIdx.getOrElse(0.U.asTypeOf(new FtqPtr)) 602 sink.bits.uop.ftqOffset := source.bits.ftqOffset.getOrElse(0.U) 603 sink.bits.uop.debugInfo := source.bits.perfDebugInfo 604 sink.bits.uop.vpu := source.bits.vpu.getOrElse(0.U.asTypeOf(new VPUCtrlSignals)) 605 sink.bits.uop.preDecodeInfo := source.bits.preDecode.getOrElse(0.U.asTypeOf(new PreDecodeInfo)) 606 sink.bits.uop.numLsElem := source.bits.numLsElem.getOrElse(0.U) // Todo: remove this bundle, keep only the one below 607 sink.bits.flowNum.foreach(_ := source.bits.numLsElem.get) 608 } 609 io.mem.loadFastMatch := memScheduler.io.toMem.get.loadFastMatch.map(_.fastMatch) 610 io.mem.loadFastImm := memScheduler.io.toMem.get.loadFastMatch.map(_.fastImm) 611 io.mem.tlbCsr := csrio.tlb 612 io.mem.csrCtrl := csrio.customCtrl 613 io.mem.sfence := fenceio.sfence 614 io.mem.isStoreException := CommitType.lsInstIsStore(ctrlBlock.io.robio.exception.bits.commitType) 615 io.mem.isVlsException := ctrlBlock.io.robio.exception.bits.vls 616 require(io.mem.loadPcRead.size == params.LduCnt) 617 io.mem.loadPcRead.zipWithIndex.foreach { case (loadPcRead, i) => 618 loadPcRead := ctrlBlock.io.memLdPcRead(i).data 619 ctrlBlock.io.memLdPcRead(i).vld := io.mem.issueLda(i).valid 620 ctrlBlock.io.memLdPcRead(i).ptr := io.mem.issueLda(i).bits.uop.ftqPtr 621 ctrlBlock.io.memLdPcRead(i).offset := io.mem.issueLda(i).bits.uop.ftqOffset 622 } 623 624 io.mem.storePcRead.zipWithIndex.foreach { case (storePcRead, i) => 625 storePcRead := ctrlBlock.io.memStPcRead(i).data 626 ctrlBlock.io.memStPcRead(i).vld := io.mem.issueSta(i).valid 627 ctrlBlock.io.memStPcRead(i).ptr := io.mem.issueSta(i).bits.uop.ftqPtr 628 ctrlBlock.io.memStPcRead(i).offset := io.mem.issueSta(i).bits.uop.ftqOffset 629 } 630 631 io.mem.hyuPcRead.zipWithIndex.foreach( { case (hyuPcRead, i) => 632 hyuPcRead := ctrlBlock.io.memHyPcRead(i).data 633 ctrlBlock.io.memHyPcRead(i).vld := io.mem.issueHylda(i).valid 634 ctrlBlock.io.memHyPcRead(i).ptr := io.mem.issueHylda(i).bits.uop.ftqPtr 635 ctrlBlock.io.memHyPcRead(i).offset := io.mem.issueHylda(i).bits.uop.ftqOffset 636 }) 637 638 ctrlBlock.io.robio.robHeadLsIssue := io.mem.issueUops.map(deq => deq.fire && deq.bits.uop.robIdx === ctrlBlock.io.robio.robDeqPtr).reduce(_ || _) 639 640 // mem io 641 io.mem.lsqEnqIO <> memScheduler.io.memIO.get.lsqEnqIO 642 io.mem.robLsqIO <> ctrlBlock.io.robio.lsq 643 644 io.frontendSfence := fenceio.sfence 645 io.frontendTlbCsr := csrio.tlb 646 io.frontendCsrCtrl := csrio.customCtrl 647 648 io.tlb <> csrio.tlb 649 650 io.csrCustomCtrl := csrio.customCtrl 651 652 io.toTop.cpuHalted := false.B // TODO: implement cpu halt 653 654 io.debugTopDown.fromRob := ctrlBlock.io.debugTopDown.fromRob 655 ctrlBlock.io.debugTopDown.fromCore := io.debugTopDown.fromCore 656 657 io.debugRolling := ctrlBlock.io.debugRolling 658 659 if(backendParams.debugEn) { 660 dontTouch(memScheduler.io) 661 dontTouch(dataPath.io.toMemExu) 662 dontTouch(wbDataPath.io.fromMemExu) 663 } 664} 665 666class BackendMemIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 667 // Since fast load replay always use load unit 0, Backend flips two load port to avoid conflicts 668 val flippedLda = true 669 // params alias 670 private val LoadQueueSize = VirtualLoadQueueSize 671 // In/Out // Todo: split it into one-direction bundle 672 val lsqEnqIO = Flipped(new LsqEnqIO) 673 val robLsqIO = new RobLsqIO 674 val ldaIqFeedback = Vec(params.LduCnt, Flipped(new MemRSFeedbackIO)) 675 val staIqFeedback = Vec(params.StaCnt, Flipped(new MemRSFeedbackIO)) 676 val hyuIqFeedback = Vec(params.HyuCnt, Flipped(new MemRSFeedbackIO)) 677 val vstuIqFeedback = Flipped(Vec(params.VstuCnt, new MemRSFeedbackIO(isVector = true))) 678 val vlduIqFeedback = Flipped(Vec(params.VlduCnt, new MemRSFeedbackIO(isVector = true))) 679 val ldCancel = Vec(params.LdExuCnt, Flipped(new LoadCancelIO)) 680 val wakeup = Vec(params.LdExuCnt, Flipped(Valid(new DynInst))) 681 val loadPcRead = Vec(params.LduCnt, Output(UInt(VAddrBits.W))) 682 val storePcRead = Vec(params.StaCnt, Output(UInt(VAddrBits.W))) 683 val hyuPcRead = Vec(params.HyuCnt, Output(UInt(VAddrBits.W))) 684 // Input 685 val writebackLda = Vec(params.LduCnt, Flipped(DecoupledIO(new MemExuOutput))) 686 val writebackSta = Vec(params.StaCnt, Flipped(DecoupledIO(new MemExuOutput))) 687 val writebackStd = Vec(params.StdCnt, Flipped(DecoupledIO(new MemExuOutput))) 688 val writebackHyuLda = Vec(params.HyuCnt, Flipped(DecoupledIO(new MemExuOutput))) 689 val writebackHyuSta = Vec(params.HyuCnt, Flipped(DecoupledIO(new MemExuOutput))) 690 val writebackVldu = Vec(params.VlduCnt, Flipped(DecoupledIO(new MemExuOutput(true)))) 691 692 val s3_delayed_load_error = Input(Vec(LoadPipelineWidth, Bool())) 693 val stIn = Input(Vec(params.StaExuCnt, ValidIO(new DynInst()))) 694 val memoryViolation = Flipped(ValidIO(new Redirect)) 695 val exceptionAddr = Input(new Bundle { 696 val vaddr = UInt(VAddrBits.W) 697 val gpaddr = UInt(GPAddrBits.W) 698 }) 699 val sqDeq = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) 700 val lqDeq = Input(UInt(log2Up(CommitWidth + 1).W)) 701 val sqDeqPtr = Input(new SqPtr) 702 val lqDeqPtr = Input(new LqPtr) 703 704 val lqCancelCnt = Input(UInt(log2Up(VirtualLoadQueueSize + 1).W)) 705 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 706 707 val lqCanAccept = Input(Bool()) 708 val sqCanAccept = Input(Bool()) 709 710 val otherFastWakeup = Flipped(Vec(params.LduCnt + params.HyuCnt, ValidIO(new DynInst))) 711 val stIssuePtr = Input(new SqPtr()) 712 713 val csrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 714 715 val debugLS = Flipped(Output(new DebugLSIO)) 716 717 val lsTopdownInfo = Vec(params.LduCnt + params.HyuCnt, Flipped(Output(new LsTopdownInfo))) 718 // Output 719 val redirect = ValidIO(new Redirect) // rob flush MemBlock 720 val issueLda = MixedVec(Seq.fill(params.LduCnt)(DecoupledIO(new MemExuInput()))) 721 val issueSta = MixedVec(Seq.fill(params.StaCnt)(DecoupledIO(new MemExuInput()))) 722 val issueStd = MixedVec(Seq.fill(params.StdCnt)(DecoupledIO(new MemExuInput()))) 723 val issueHylda = MixedVec(Seq.fill(params.HyuCnt)(DecoupledIO(new MemExuInput()))) 724 val issueHysta = MixedVec(Seq.fill(params.HyuCnt)(DecoupledIO(new MemExuInput()))) 725 val issueVldu = MixedVec(Seq.fill(params.VlduCnt)(DecoupledIO(new MemExuInput(true)))) 726 727 val loadFastMatch = Vec(params.LduCnt, Output(UInt(params.LduCnt.W))) 728 val loadFastImm = Vec(params.LduCnt, Output(UInt(12.W))) // Imm_I 729 730 val tlbCsr = Output(new TlbCsrBundle) 731 val csrCtrl = Output(new CustomCSRCtrlIO) 732 val sfence = Output(new SfenceBundle) 733 val isStoreException = Output(Bool()) 734 val isVlsException = Output(Bool()) 735 736 // ATTENTION: The issue ports' sequence order should be the same as IQs' deq config 737 private [backend] def issueUops: Seq[DecoupledIO[MemExuInput]] = { 738 issueSta ++ 739 issueHylda ++ issueHysta ++ 740 issueLda ++ 741 issueVldu ++ 742 issueStd 743 }.toSeq 744 745 // ATTENTION: The writeback ports' sequence order should be the same as IQs' deq config 746 private [backend] def writeBack: Seq[DecoupledIO[MemExuOutput]] = { 747 writebackSta ++ 748 writebackHyuLda ++ writebackHyuSta ++ 749 writebackLda ++ 750 writebackVldu ++ 751 writebackStd 752 } 753} 754 755class BackendIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 756 val fromTop = new Bundle { 757 val hartId = Input(UInt(hartIdLen.W)) 758 val externalInterrupt = new ExternalInterruptIO 759 } 760 761 val toTop = new Bundle { 762 val cpuHalted = Output(Bool()) 763 } 764 765 val fenceio = new FenceIO 766 // Todo: merge these bundles into BackendFrontendIO 767 val frontend = Flipped(new FrontendToCtrlIO) 768 val frontendSfence = Output(new SfenceBundle) 769 val frontendCsrCtrl = Output(new CustomCSRCtrlIO) 770 val frontendTlbCsr = Output(new TlbCsrBundle) 771 // distributed csr write 772 val frontendCsrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 773 774 val mem = new BackendMemIO 775 776 val perf = Input(new PerfCounterIO) 777 778 val tlb = Output(new TlbCsrBundle) 779 780 val csrCustomCtrl = Output(new CustomCSRCtrlIO) 781 782 val debugTopDown = new Bundle { 783 val fromRob = new RobCoreTopDownIO 784 val fromCore = new CoreDispatchTopDownIO 785 } 786 val debugRolling = new RobDebugRollingIO 787} 788