| #
89722029 |
| 06-Nov-2020 |
LinJiawei <[email protected]> |
Remove the final 'BoringUtils'
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| #
8b4ffe05 |
| 06-Nov-2020 |
LinJiawei <[email protected]> |
Merge remote-tracking branch 'origin/rs-new' into xs-fpu
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| #
be784967 |
| 05-Nov-2020 |
LinJiawei <[email protected]> |
Remove all boringutils except Regfile
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| #
58e26f5f |
| 05-Nov-2020 |
LinJiawei <[email protected]> |
Difftest: use exciting utils instead boring utils
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| #
2fdc488a |
| 05-Nov-2020 |
LinJiawei <[email protected]> |
Remove BoringUtils in fence unit
|
| #
f48ee482 |
| 03-Nov-2020 |
Yinan Xu <[email protected]> |
backend: connect externalInterrupt to CSR
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| #
ef74f7cb |
| 02-Nov-2020 |
LinJiawei <[email protected]> |
Merge remote-tracking branch 'origin/fix-boringutils' into xs-fpu
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| #
3fa7b737 |
| 02-Nov-2020 |
Yinan Xu <[email protected]> |
roq,csr: only raiseInterrupt when roq redirects an interrupt
Previously, CSR determines interrupt by redirect.valid && interruptBitEnable.
However, interruptBitEnable does not mean the redirect is a
roq,csr: only raiseInterrupt when roq redirects an interrupt
Previously, CSR determines interrupt by redirect.valid && interruptBitEnable.
However, interruptBitEnable does not mean the redirect is an interrupt.
We reuse isFlushPipe in Roq to represent an interrupt for CSR.
show more ...
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| #
8e8cb3b4 |
| 02-Nov-2020 |
Yinan Xu <[email protected]> |
xiangshan: remove noop code from repo
|
| #
35bfeecb |
| 02-Nov-2020 |
Yinan Xu <[email protected]> |
csr: use IO for mtip,msip,meip
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| #
3136ee6a |
| 02-Nov-2020 |
LinJiawei <[email protected]> |
Merge 'master' into 'xs-fpu'
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| #
7b62a3f6 |
| 02-Nov-2020 |
ZhangZifei <[email protected]> |
RSNew: fix bug of fbHitVec for tlbfeedback return no delay
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| #
19f0b6c7 |
| 01-Nov-2020 |
ZhangZifei <[email protected]> |
RSNew: (only) change validQueue to stateQueue
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| #
75345ac2 |
| 01-Nov-2020 |
ZhangZifei <[email protected]> |
Merge branch 'dev-memend' into rs-new
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| #
11131ea4 |
| 01-Nov-2020 |
Yinan Xu <[email protected]> |
mem,lsq: remove excitingutils for exception vaddr
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| #
48ae2f92 |
| 31-Oct-2020 |
William Wang <[email protected]> |
Merge remote-tracking branch 'origin/master' into dev-memend
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| #
16df83ad |
| 30-Oct-2020 |
ZhangZifei <[email protected]> |
RSNew: support multi-delay(may have bugs)
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| #
0ecbc6d6 |
| 30-Oct-2020 |
ZhangZifei <[email protected]> |
Merge branch 'master' into rs-new
|
| #
6c4a4192 |
| 26-Oct-2020 |
William Wang <[email protected]> |
[WIP] Memend: fix mem rf port width, add tlbFeedback
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| #
59a40467 |
| 26-Oct-2020 |
William Wang <[email protected]> |
[WIP] loadPipeline: fix wiring for loadPipeline
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| #
5801e7f2 |
| 25-Oct-2020 |
ZhangZifei <[email protected]> |
Merge branch 'master' into rs-new
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| #
bbb63ef4 |
| 25-Oct-2020 |
Yinan Xu <[email protected]> |
Merge branch 'dev-lsroq' into opt-dispatchqueue
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| #
7962cc88 |
| 23-Oct-2020 |
William Wang <[email protected]> |
Merge remote-tracking branch 'origin/opt-load-to-use' into dev-memend
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| #
185e8566 |
| 20-Oct-2020 |
William Wang <[email protected]> |
[WIP] Lsq: temporarily replace lsroqIdx with lq/sqIdx
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| #
bc86598f |
| 19-Oct-2020 |
William Wang <[email protected]> |
[WIP] Lsroq: fix unified lsroq wiring
|