1package xiangshan.backend 2 3import chisel3._ 4import chisel3.util._ 5import chisel3.util.experimental.BoringUtils 6import xiangshan._ 7import xiangshan.backend.decode.{DecodeBuffer, DecodeStage} 8import xiangshan.backend.rename.Rename 9import xiangshan.backend.brq.Brq 10import xiangshan.backend.dispatch.Dispatch 11import xiangshan.backend.exu._ 12import xiangshan.backend.fu.FunctionUnit 13import xiangshan.backend.issue.{IssueQueue, ReservationStation} 14import xiangshan.backend.regfile.{Regfile, RfWritePort} 15import xiangshan.backend.roq.Roq 16import xiangshan.mem._ 17import utils.ParallelOR 18 19/** Backend Pipeline: 20 * Decode -> Rename -> Dispatch-1 -> Dispatch-2 -> Issue -> Exe 21 */ 22class Backend extends XSModule 23 with NeedImpl { 24 val io = IO(new Bundle { 25 val frontend = Flipped(new FrontendToBackendIO) 26 val mem = Flipped(new MemToBackendIO) 27 val externalInterrupt = new ExternalInterruptIO 28 val sfence = Output(new SfenceBundle) 29 val fencei = Output(Bool()) 30 }) 31 32 33 val aluExeUnits =Array.tabulate(exuParameters.AluCnt)(_ => Module(new AluExeUnit)) 34 val jmpExeUnit = Module(new JmpExeUnit) 35 val mulExeUnits = Array.tabulate(exuParameters.MulCnt)(_ => Module(new MulExeUnit)) 36 val mduExeUnits = Array.tabulate(exuParameters.MduCnt)(_ => Module(new MulDivExeUnit)) 37 val fmacExeUnits = Array.tabulate(exuParameters.FmacCnt)(_ => Module(new FmacExeUnit)) 38 val fmiscExeUnits = Array.tabulate(exuParameters.FmiscCnt)(_ => Module(new FmiscExeUnit)) 39 // val fmiscDivSqrtExeUnits = Array.tabulate(exuParameters.FmiscDivSqrtCnt)(_ => Module(new FmiscDivSqrtExeUnit)) 40 val exeUnits = jmpExeUnit +: (aluExeUnits ++ mulExeUnits ++ mduExeUnits ++ fmacExeUnits ++ fmiscExeUnits) 41 exeUnits.foreach(_.io.csrOnly := DontCare) 42 exeUnits.foreach(_.io.mcommit := DontCare) 43 44 val decode = Module(new DecodeStage) 45 val brq = Module(new Brq) 46 val decBuf = Module(new DecodeBuffer) 47 val rename = Module(new Rename) 48 val dispatch = Module(new Dispatch) 49 val roq = Module(new Roq) 50 val intRf = Module(new Regfile( 51 numReadPorts = NRIntReadPorts, 52 numWirtePorts = NRIntWritePorts, 53 hasZero = true 54 )) 55 val fpRf = Module(new Regfile( 56 numReadPorts = NRFpReadPorts, 57 numWirtePorts = NRFpWritePorts, 58 hasZero = false 59 )) 60 val memRf = Module(new Regfile( 61 numReadPorts = 2*exuParameters.StuCnt + exuParameters.LduCnt, 62 numWirtePorts = NRIntWritePorts, 63 hasZero = true, 64 isMemRf = true 65 )) 66 67 // backend redirect, flush pipeline 68 val redirect = Mux( 69 roq.io.redirect.valid, 70 roq.io.redirect, 71 Mux( 72 brq.io.redirect.valid, 73 brq.io.redirect, 74 io.mem.replayAll 75 ) 76 ) 77 78 io.frontend.redirect := redirect 79 io.frontend.redirect.valid := redirect.valid && !redirect.bits.isReplay 80 81 val memConfigs = 82 Seq.fill(exuParameters.LduCnt)(Exu.ldExeUnitCfg) ++ 83 Seq.fill(exuParameters.StuCnt)(Exu.stExeUnitCfg) 84 85 val exuConfigs = exeUnits.map(_.config) ++ memConfigs 86 87 val exeWbReqs = exeUnits.map(_.io.out) ++ io.mem.ldout ++ io.mem.stout 88 89 def needWakeup(cfg: ExuConfig): Boolean = 90 (cfg.readIntRf && cfg.writeIntRf) || (cfg.readFpRf && cfg.writeFpRf) 91 92 def needData(a: ExuConfig, b: ExuConfig): Boolean = 93 (a.readIntRf && b.writeIntRf) || (a.readFpRf && b.writeFpRf) 94 95 val reservedStations = exeUnits. 96 zipWithIndex. 97 map({ case (exu, i) => 98 99 val cfg = exu.config 100 101 val wakeUpDateVec = exuConfigs.zip(exeWbReqs).filter(x => needData(cfg, x._1)).map(_._2) 102 val bypassCnt = exuConfigs.count(c => c.enableBypass && needData(cfg, c)) 103 104 println(s"exu:${cfg.name} wakeupCnt:${wakeUpDateVec.length} bypassCnt:$bypassCnt") 105 106 val rs = Module(new ReservationStation( 107 cfg, wakeUpDateVec.length, bypassCnt, cfg.enableBypass, false 108 )) 109 rs.io.redirect <> redirect 110 rs.io.numExist <> dispatch.io.numExist(i) 111 rs.io.enqCtrl <> dispatch.io.enqIQCtrl(i) 112 rs.io.enqData <> dispatch.io.enqIQData(i) 113 for( 114 (wakeUpPort, exuOut) <- 115 rs.io.wakeUpPorts.zip(wakeUpDateVec) 116 ){ 117 wakeUpPort.bits := exuOut.bits 118 wakeUpPort.valid := exuOut.valid 119 } 120 121 exu.io.in <> rs.io.deq 122 exu.io.redirect <> redirect 123 rs 124 }) 125 126 for( rs <- reservedStations){ 127 val bypassDataVec = exuConfigs.zip(exeWbReqs). 128 filter(x => x._1.enableBypass && needData(rs.exuCfg, x._1)).map(_._2) 129 130 rs.io.bypassUops <> reservedStations. 131 filter(x => x.enableBypass && needData(rs.exuCfg, x.exuCfg)). 132 map(_.io.selectedUop) 133 134 for(i <- bypassDataVec.indices){ 135 rs.io.bypassData(i).valid := bypassDataVec(i).valid 136 rs.io.bypassData(i).bits := bypassDataVec(i).bits 137 } 138 } 139 140 val issueQueues = exuConfigs. 141 zipWithIndex. 142 takeRight(exuParameters.LduCnt + exuParameters.StuCnt). 143 map({case (cfg, i) => 144 val wakeUpDateVec = exuConfigs.zip(exeWbReqs).filter(x => needData(cfg, x._1)).map(_._2) 145 val bypassUopVec = reservedStations. 146 filter(r => r.exuCfg.enableBypass && needData(cfg, r.exuCfg)).map(_.io.selectedUop) 147 val bypassDataVec = exuConfigs.zip(exeWbReqs). 148 filter(x => x._1.enableBypass && needData(cfg, x._1)).map(_._2) 149 150 val iq = Module(new IssueQueue( 151 cfg, wakeUpDateVec.length, bypassUopVec.length 152 )) 153 println(s"exu:${cfg.name} wakeupCnt:${wakeUpDateVec.length} bypassCnt:${bypassUopVec.length}") 154 iq.io.redirect <> redirect 155 iq.io.tlbFeedback := io.mem.tlbFeedback(i - exuParameters.ExuCnt + exuParameters.LduCnt + exuParameters.StuCnt) 156 iq.io.enq <> dispatch.io.enqIQCtrl(i) 157 dispatch.io.numExist(i) := iq.io.numExist 158 for( 159 (wakeUpPort, exuOut) <- 160 iq.io.wakeUpPorts.zip(wakeUpDateVec) 161 ){ 162 wakeUpPort.bits := exuOut.bits 163 wakeUpPort.valid := exuOut.fire() // data after arbit 164 } 165 iq.io.bypassUops <> bypassUopVec 166 for(i <- bypassDataVec.indices){ 167 iq.io.bypassData(i).valid := bypassDataVec(i).valid 168 iq.io.bypassData(i).bits := bypassDataVec(i).bits 169 } 170 iq 171 }) 172 173 io.mem.commits <> roq.io.commits 174 io.mem.roqDeqPtr := roq.io.roqDeqPtr 175 io.mem.ldin <> issueQueues.filter(_.exuCfg == Exu.ldExeUnitCfg).map(_.io.deq) 176 io.mem.stin <> issueQueues.filter(_.exuCfg == Exu.stExeUnitCfg).map(_.io.deq) 177 jmpExeUnit.io.csrOnly.exception.valid := roq.io.redirect.valid && roq.io.redirect.bits.isException 178 jmpExeUnit.io.csrOnly.exception.bits := roq.io.exception 179 180 jmpExeUnit.io.csrOnly.memExceptionVAddr := io.mem.exceptionAddr.vaddr 181 jmpExeUnit.fenceToSbuffer <> io.mem.fenceToSbuffer 182 io.mem.sfence <> jmpExeUnit.sfence 183 io.mem.exceptionAddr.lsIdx.lsroqIdx := roq.io.exception.lsroqIdx 184 io.mem.exceptionAddr.lsIdx.lqIdx := roq.io.exception.lqIdx 185 io.mem.exceptionAddr.lsIdx.sqIdx := roq.io.exception.sqIdx 186 io.mem.exceptionAddr.isStore := CommitType.lsInstIsStore(roq.io.exception.ctrl.commitType) 187 188 io.frontend.outOfOrderBrInfo <> brq.io.outOfOrderBrInfo 189 io.frontend.inOrderBrInfo <> brq.io.inOrderBrInfo 190 io.frontend.sfence <> jmpExeUnit.sfence 191 192 io.fencei := jmpExeUnit.fencei 193 194 decode.io.in <> io.frontend.cfVec 195 brq.io.roqRedirect <> roq.io.redirect 196 brq.io.memRedirect <> io.mem.replayAll 197 brq.io.bcommit := roq.io.bcommit 198 brq.io.enqReqs <> decode.io.toBrq 199 for ((x, y) <- brq.io.exuRedirect.zip(exeUnits.filter(_.config.hasRedirect))) { 200 x.bits := y.io.out.bits 201 x.valid := y.io.out.fire() && y.io.out.bits.redirectValid 202 } 203 decode.io.brTags <> brq.io.brTags 204 decBuf.io.isWalking := ParallelOR(roq.io.commits.map(c => c.valid && c.bits.isWalk)) // TODO: opt this 205 decBuf.io.redirect <> redirect 206 decBuf.io.in <> decode.io.out 207 208 rename.io.redirect <> redirect 209 rename.io.roqCommits <> roq.io.commits 210 rename.io.in <> decBuf.io.out 211 rename.io.intRfReadAddr <> dispatch.io.readIntRf.map(_.addr) ++ dispatch.io.intMemRegAddr 212 rename.io.intPregRdy <> dispatch.io.intPregRdy ++ dispatch.io.intMemRegRdy 213 rename.io.fpRfReadAddr <> dispatch.io.readFpRf.map(_.addr) ++ dispatch.io.fpMemRegAddr 214 rename.io.fpPregRdy <> dispatch.io.fpPregRdy ++ dispatch.io.fpMemRegRdy 215 rename.io.replayPregReq <> dispatch.io.replayPregReq 216 dispatch.io.redirect <> redirect 217 dispatch.io.fromRename <> rename.io.out 218 219 roq.io.memRedirect <> io.mem.replayAll 220 roq.io.brqRedirect <> brq.io.redirect 221 roq.io.dp1Req <> dispatch.io.toRoq 222 roq.io.intrBitSet := jmpExeUnit.io.csrOnly.interrupt 223 roq.io.trapTarget := jmpExeUnit.io.csrOnly.trapTarget 224 dispatch.io.roqIdxs <> roq.io.roqIdxs 225 io.mem.dp1Req <> dispatch.io.toLsroq 226 dispatch.io.lsIdxs <> io.mem.lsIdxs 227 dispatch.io.dequeueRoqIndex.valid := roq.io.commitRoqIndex.valid || io.mem.oldestStore.valid 228 // store writeback must be after commit roqIdx 229 dispatch.io.dequeueRoqIndex.bits := Mux(io.mem.oldestStore.valid, io.mem.oldestStore.bits, roq.io.commitRoqIndex.bits) 230 231 232 intRf.io.readPorts <> dispatch.io.readIntRf 233 fpRf.io.readPorts <> dispatch.io.readFpRf ++ issueQueues.flatMap(_.io.readFpRf) 234 memRf.io.readPorts <> issueQueues.flatMap(_.io.readIntRf) 235 236 io.mem.redirect <> redirect 237 238 val wbu = Module(new Wbu(exuConfigs)) 239 wbu.io.in <> exeWbReqs 240 241 val wbIntResults = wbu.io.toIntRf 242 val wbFpResults = wbu.io.toFpRf 243 244 def exuOutToRfWrite(x: Valid[ExuOutput]): RfWritePort = { 245 val rfWrite = Wire(new RfWritePort) 246 rfWrite.wen := x.valid 247 rfWrite.addr := x.bits.uop.pdest 248 rfWrite.data := x.bits.data 249 rfWrite 250 } 251 val intRfWrite = wbIntResults.map(exuOutToRfWrite) 252 intRf.io.writePorts <> intRfWrite 253 memRf.io.writePorts <> intRfWrite 254 fpRf.io.writePorts <> wbFpResults.map(exuOutToRfWrite) 255 256 rename.io.wbIntResults <> wbIntResults 257 rename.io.wbFpResults <> wbFpResults 258 259 roq.io.exeWbResults.take(exeWbReqs.length).zip(wbu.io.toRoq).foreach(x => x._1 := x._2) 260 roq.io.exeWbResults.last := brq.io.out 261 262 263 val debugIntReg, debugFpReg = WireInit(VecInit(Seq.fill(32)(0.U(XLEN.W)))) 264 BoringUtils.addSink(debugIntReg, "DEBUG_INT_ARCH_REG") 265 BoringUtils.addSink(debugFpReg, "DEBUG_FP_ARCH_REG") 266 val debugArchReg = WireInit(VecInit(debugIntReg ++ debugFpReg)) 267 if (!env.FPGAPlatform) { 268 ExcitingUtils.addSource(debugArchReg, "difftestRegs", ExcitingUtils.Debug) 269 } 270 271} 272