xref: /XiangShan/src/main/scala/xiangshan/backend/Backend.scala (revision 16df83adafbc2e25ae14c8c7ccccc5516db96bdd) 
1package xiangshan.backend
2
3import bus.simplebus.SimpleBusUC
4import chisel3._
5import chisel3.util._
6import chisel3.util.experimental.BoringUtils
7import noop.MemMMUIO
8import xiangshan._
9import xiangshan.backend.decode.{DecodeBuffer, DecodeStage}
10import xiangshan.backend.rename.Rename
11import xiangshan.backend.brq.Brq
12import xiangshan.backend.dispatch.Dispatch
13import xiangshan.backend.exu._
14import xiangshan.backend.fu.FunctionUnit
15import xiangshan.backend.issue.{IssueQueue, ReservationStationNew}
16import xiangshan.backend.regfile.{Regfile, RfWritePort}
17import xiangshan.backend.roq.Roq
18import xiangshan.mem._
19import utils.ParallelOR
20
21/** Backend Pipeline:
22  * Decode -> Rename -> Dispatch-1 -> Dispatch-2 -> Issue -> Exe
23  */
24class Backend extends XSModule
25  with NeedImpl {
26  val io = IO(new Bundle {
27    val frontend = Flipped(new FrontendToBackendIO)
28    val mem = Flipped(new MemToBackendIO)
29  })
30
31
32  val aluExeUnits =Array.tabulate(exuParameters.AluCnt)(_ => Module(new AluExeUnit))
33  val jmpExeUnit = Module(new JmpExeUnit)
34  val mulExeUnits = Array.tabulate(exuParameters.MulCnt)(_ => Module(new MulExeUnit))
35  val mduExeUnits = Array.tabulate(exuParameters.MduCnt)(_ => Module(new MulDivExeUnit))
36  // val fmacExeUnits = Array.tabulate(exuParameters.FmacCnt)(_ => Module(new Fmac))
37  // val fmiscExeUnits = Array.tabulate(exuParameters.FmiscCnt)(_ => Module(new Fmisc))
38  // val fmiscDivSqrtExeUnits = Array.tabulate(exuParameters.FmiscDivSqrtCnt)(_ => Module(new FmiscDivSqrt))
39  val exeUnits = jmpExeUnit +: (aluExeUnits ++ mulExeUnits ++ mduExeUnits)
40  exeUnits.foreach(_.io.exception := DontCare)
41  exeUnits.foreach(_.io.dmem := DontCare)
42  exeUnits.foreach(_.io.mcommit := DontCare)
43
44  val decode = Module(new DecodeStage)
45  val brq = Module(new Brq)
46  val decBuf = Module(new DecodeBuffer)
47  val rename = Module(new Rename)
48  val dispatch = Module(new Dispatch)
49  val roq = Module(new Roq)
50  val intRf = Module(new Regfile(
51    numReadPorts = NRIntReadPorts,
52    numWirtePorts = NRIntWritePorts,
53    hasZero = true
54  ))
55  val fpRf = Module(new Regfile(
56    numReadPorts = NRFpReadPorts,
57    numWirtePorts = NRFpWritePorts,
58    hasZero = false
59  ))
60  val memRf = Module(new Regfile(
61    numReadPorts = 2*exuParameters.StuCnt + exuParameters.LduCnt,
62    numWirtePorts = NRIntWritePorts,
63    hasZero = true,
64    isMemRf = true
65  ))
66
67  // backend redirect, flush pipeline
68  val redirect = Mux(
69    roq.io.redirect.valid,
70    roq.io.redirect,
71    Mux(
72      brq.io.redirect.valid,
73      brq.io.redirect,
74      io.mem.replayAll
75    )
76  )
77
78  io.frontend.redirect := redirect
79  io.frontend.redirect.valid := redirect.valid && !redirect.bits.isReplay
80
81  val memConfigs =
82    Seq.fill(exuParameters.LduCnt)(Exu.ldExeUnitCfg) ++
83    Seq.fill(exuParameters.StuCnt)(Exu.stExeUnitCfg)
84
85  val exuConfigs = exeUnits.map(_.config) ++ memConfigs
86
87  val exeWbReqs = exeUnits.map(_.io.out) ++ io.mem.ldout ++ io.mem.stout
88
89  def needWakeup(cfg: ExuConfig): Boolean =
90    (cfg.readIntRf && cfg.writeIntRf) || (cfg.readFpRf && cfg.writeFpRf)
91
92  def needData(a: ExuConfig, b: ExuConfig): Boolean =
93    (a.readIntRf && b.writeIntRf) || (a.readFpRf && b.writeFpRf)
94
95
96  val reservedStations  = exeUnits.zipWithIndex.map({ case (exu, i) =>
97
98    val cfg = exu.config
99    // NOTE: exu could have certern and uncertaion latency
100    // but could not have multiple certern latency
101    var certainLatency = -1
102    if(cfg.hasCertainLatency) { certainLatency = cfg.latency.latencyVal.get }
103
104    val writeBackedData = exuConfigs.zip(exeWbReqs).filter(x => x._1.hasCertainLatency && needData(x._1, cfg)).map(_._2.bits.data)
105    val wakeupCnt = writeBackedData.length
106
107    val extraListenPorts = exuConfigs
108      .zip(exeWbReqs)
109      .filter(x => x._1.hasUncertainlatency && needData(x._1, cfg))
110      .map(_._2)
111    val extraListenPortsCnt = extraListenPorts.length
112
113
114    val rs = Module(new ReservationStationNew(cfg, wakeupCnt, extraListenPortsCnt, fixedDelay = certainLatency))
115
116    println(s"exu:${cfg.name} wakeupCnt: ${wakeupCnt} extraListenPorts: ${extraListenPortsCnt} delay:${certainLatency}")
117
118    rs.io.redirect <> redirect
119    rs.io.numExist <> dispatch.io.numExist(i)
120    rs.io.enqCtrl <> dispatch.io.enqIQCtrl(i)
121    rs.io.enqData <> dispatch.io.enqIQData(i)
122
123
124    rs.io.writeBackedData <> writeBackedData
125    for((x, y) <- rs.io.extraListenPorts.zip(extraListenPorts)){
126      x.valid := y.fire()
127      x.bits := y.bits
128    }
129
130    exu.io.in <> rs.io.deq
131    exu.io.redirect <> redirect
132
133    rs
134  })
135
136  for( rs <- reservedStations){
137
138    rs.io.broadcastedUops <> reservedStations.
139        filter(x => x.exuCfg.hasCertainLatency && needData(rs.exuCfg, x.exuCfg)).
140        map(_.io.selectedUop)
141
142  }
143
144
145  val issueQueues = exuConfigs.
146    zipWithIndex.
147    takeRight(exuParameters.LduCnt + exuParameters.StuCnt).
148    map({case (cfg, i) =>
149      val wakeUpDateVec = exuConfigs.zip(exeWbReqs).filter(x => needData(cfg, x._1)).map(_._2)
150      val bypassUopVec = reservedStations.
151        filter(r => r.exuCfg.enableBypass && needData(cfg, r.exuCfg)).map(_.io.selectedUop)
152      val bypassDataVec = exuConfigs.zip(exeWbReqs).
153        filter(x => x._1.enableBypass && needData(cfg, x._1)).map(_._2)
154
155      val iq = Module(new IssueQueue(
156        cfg, wakeUpDateVec.length, bypassUopVec.length
157      ))
158      println(s"exu:${cfg.name} wakeupCnt:${wakeUpDateVec.length} bypassCnt:${bypassUopVec.length}")
159      iq.io.redirect <> redirect
160      iq.io.tlbFeedback := io.mem.tlbFeedback(i - exuParameters.ExuCnt + exuParameters.LduCnt + exuParameters.StuCnt)
161      iq.io.enq <> dispatch.io.enqIQCtrl(i)
162      dispatch.io.numExist(i) := iq.io.numExist
163      for(
164        (wakeUpPort, exuOut) <-
165        iq.io.wakeUpPorts.zip(wakeUpDateVec)
166      ){
167        wakeUpPort.bits := exuOut.bits
168        wakeUpPort.valid := exuOut.fire() // data after arbit
169      }
170      iq.io.bypassUops <> bypassUopVec
171      for(i <- bypassDataVec.indices){
172        iq.io.bypassData(i).valid := bypassDataVec(i).valid
173        iq.io.bypassData(i).bits := bypassDataVec(i).bits
174      }
175      iq
176    })
177
178  io.mem.commits <> roq.io.commits
179  io.mem.roqDeqPtr := roq.io.roqDeqPtr
180  io.mem.ldin <> issueQueues.filter(_.exuCfg == Exu.ldExeUnitCfg).map(_.io.deq)
181  io.mem.stin <> issueQueues.filter(_.exuCfg == Exu.stExeUnitCfg).map(_.io.deq)
182  jmpExeUnit.io.exception.valid := roq.io.redirect.valid && roq.io.redirect.bits.isException
183  jmpExeUnit.io.exception.bits := roq.io.exception
184
185  io.frontend.outOfOrderBrInfo <> brq.io.outOfOrderBrInfo
186  io.frontend.inOrderBrInfo <> brq.io.inOrderBrInfo
187
188  decode.io.in <> io.frontend.cfVec
189  brq.io.roqRedirect <> roq.io.redirect
190  brq.io.memRedirect <> io.mem.replayAll
191  brq.io.bcommit := roq.io.bcommit
192  brq.io.enqReqs <> decode.io.toBrq
193  for ((x, y) <- brq.io.exuRedirect.zip(exeUnits.filter(_.config.hasRedirect))) {
194    x.bits := y.io.out.bits
195    x.valid := y.io.out.fire() && y.io.out.bits.redirectValid
196  }
197  decode.io.brTags <> brq.io.brTags
198  decBuf.io.isWalking := ParallelOR(roq.io.commits.map(c => c.valid && c.bits.isWalk)) // TODO: opt this
199  decBuf.io.redirect <> redirect
200  decBuf.io.in <> decode.io.out
201
202  rename.io.redirect <> redirect
203  rename.io.roqCommits <> roq.io.commits
204  rename.io.in <> decBuf.io.out
205  rename.io.intRfReadAddr <> dispatch.io.readIntRf.map(_.addr) ++ dispatch.io.intMemRegAddr
206  rename.io.intPregRdy <> dispatch.io.intPregRdy ++ dispatch.io.intMemRegRdy
207  rename.io.fpRfReadAddr <> dispatch.io.readFpRf.map(_.addr) ++ dispatch.io.fpMemRegAddr
208  rename.io.fpPregRdy <> dispatch.io.fpPregRdy ++ dispatch.io.fpMemRegRdy
209  rename.io.replayPregReq <> dispatch.io.replayPregReq
210  dispatch.io.redirect <> redirect
211  dispatch.io.fromRename <> rename.io.out
212
213  roq.io.memRedirect <> io.mem.replayAll
214  roq.io.brqRedirect <> brq.io.redirect
215  roq.io.dp1Req <> dispatch.io.toRoq
216  dispatch.io.roqIdxs <> roq.io.roqIdxs
217  io.mem.dp1Req <> dispatch.io.toLsroq
218  dispatch.io.lsIdxs <> io.mem.lsIdxs
219  dispatch.io.dequeueRoqIndex.valid := roq.io.commitRoqIndex.valid || io.mem.oldestStore.valid
220  // store writeback must be after commit roqIdx
221  dispatch.io.dequeueRoqIndex.bits := Mux(io.mem.oldestStore.valid, io.mem.oldestStore.bits, roq.io.commitRoqIndex.bits)
222
223
224  intRf.io.readPorts <> dispatch.io.readIntRf
225  fpRf.io.readPorts <> dispatch.io.readFpRf ++ issueQueues.flatMap(_.io.readFpRf)
226  memRf.io.readPorts <> issueQueues.flatMap(_.io.readIntRf)
227
228  io.mem.redirect <> redirect
229
230  val wbu = Module(new Wbu(exuConfigs))
231  wbu.io.in <> exeWbReqs
232
233  val wbIntResults = wbu.io.toIntRf
234  val wbFpResults = wbu.io.toFpRf
235
236  def exuOutToRfWrite(x: Valid[ExuOutput]): RfWritePort = {
237    val rfWrite = Wire(new RfWritePort)
238    rfWrite.wen := x.valid
239    rfWrite.addr := x.bits.uop.pdest
240    rfWrite.data := x.bits.data
241    rfWrite
242  }
243  val intRfWrite = wbIntResults.map(exuOutToRfWrite)
244  intRf.io.writePorts <> intRfWrite
245  memRf.io.writePorts <> intRfWrite
246  fpRf.io.writePorts <> wbFpResults.map(exuOutToRfWrite)
247
248  rename.io.wbIntResults <> wbIntResults
249  rename.io.wbFpResults <> wbFpResults
250
251  roq.io.exeWbResults.take(exeWbReqs.length).zip(wbu.io.toRoq).foreach(x => x._1 := x._2)
252  roq.io.exeWbResults.last := brq.io.out
253
254
255  // TODO: Remove sink and source
256  val tmp = WireInit(0.U)
257  val sinks = Array[String](
258    "DTLBFINISH",
259    "DTLBPF",
260    "DTLBENABLE",
261    "perfCntCondMdcacheLoss",
262    "perfCntCondMl2cacheLoss",
263    "perfCntCondMdcacheHit",
264    "lsuMMIO",
265    "perfCntCondMl2cacheHit",
266    "perfCntCondMl2cacheReq",
267    "mtip",
268    "perfCntCondMdcacheReq",
269    "meip"
270  )
271  for (s <- sinks) {
272    BoringUtils.addSink(tmp, s)
273  }
274
275  val debugIntReg, debugFpReg = WireInit(VecInit(Seq.fill(32)(0.U(XLEN.W))))
276  BoringUtils.addSink(debugIntReg, "DEBUG_INT_ARCH_REG")
277  BoringUtils.addSink(debugFpReg, "DEBUG_FP_ARCH_REG")
278  val debugArchReg = WireInit(VecInit(debugIntReg ++ debugFpReg))
279  if (!env.FPGAPlatform) {
280    BoringUtils.addSource(debugArchReg, "difftestRegs")
281  }
282
283}
284