xref: /XiangShan/src/main/scala/xiangshan/backend/Backend.scala (revision 6c4a41925763ce90ef85f967cd1603f976ba2e69) 
1package xiangshan.backend
2
3import bus.simplebus.SimpleBusUC
4import chisel3._
5import chisel3.util._
6import chisel3.util.experimental.BoringUtils
7import noop.MemMMUIO
8import xiangshan._
9import xiangshan.backend.decode.{DecodeBuffer, DecodeStage}
10import xiangshan.backend.rename.Rename
11import xiangshan.backend.brq.Brq
12import xiangshan.backend.dispatch.Dispatch
13import xiangshan.backend.exu._
14import xiangshan.backend.fu.FunctionUnit
15import xiangshan.backend.issue.{IssueQueue, ReservationStation}
16import xiangshan.backend.regfile.{Regfile, RfWritePort}
17import xiangshan.backend.roq.Roq
18import xiangshan.mem._
19import utils.ParallelOR
20
21/** Backend Pipeline:
22  * Decode -> Rename -> Dispatch-1 -> Dispatch-2 -> Issue -> Exe
23  */
24class Backend extends XSModule
25  with NeedImpl {
26  val io = IO(new Bundle {
27    val frontend = Flipped(new FrontendToBackendIO)
28    val mem = Flipped(new MemToBackendIO)
29  })
30
31
32  val aluExeUnits =Array.tabulate(exuParameters.AluCnt)(_ => Module(new AluExeUnit))
33  val jmpExeUnit = Module(new JmpExeUnit)
34  val mulExeUnits = Array.tabulate(exuParameters.MulCnt)(_ => Module(new MulExeUnit))
35  val mduExeUnits = Array.tabulate(exuParameters.MduCnt)(_ => Module(new MulDivExeUnit))
36  // val fmacExeUnits = Array.tabulate(exuParameters.FmacCnt)(_ => Module(new Fmac))
37  // val fmiscExeUnits = Array.tabulate(exuParameters.FmiscCnt)(_ => Module(new Fmisc))
38  // val fmiscDivSqrtExeUnits = Array.tabulate(exuParameters.FmiscDivSqrtCnt)(_ => Module(new FmiscDivSqrt))
39  val exeUnits = jmpExeUnit +: (aluExeUnits ++ mulExeUnits ++ mduExeUnits)
40  exeUnits.foreach(_.io.exception := DontCare)
41  exeUnits.foreach(_.io.dmem := DontCare)
42  exeUnits.foreach(_.io.mcommit := DontCare)
43
44  val decode = Module(new DecodeStage)
45  val brq = Module(new Brq)
46  val decBuf = Module(new DecodeBuffer)
47  val rename = Module(new Rename)
48  val dispatch = Module(new Dispatch)
49  val roq = Module(new Roq)
50  val intRf = Module(new Regfile(
51    numReadPorts = NRIntReadPorts,
52    numWirtePorts = NRIntWritePorts,
53    hasZero = true
54  ))
55  val fpRf = Module(new Regfile(
56    numReadPorts = NRFpReadPorts,
57    numWirtePorts = NRFpWritePorts,
58    hasZero = false
59  ))
60
61  // backend redirect, flush pipeline
62  val redirect = Mux(
63    roq.io.redirect.valid,
64    roq.io.redirect,
65    Mux(
66      brq.io.redirect.valid,
67      brq.io.redirect,
68      io.mem.replayAll
69    )
70  )
71
72  io.frontend.redirect := redirect
73  io.frontend.redirect.valid := redirect.valid && !redirect.bits.isReplay
74
75  val memConfigs =
76    Seq.fill(exuParameters.LduCnt)(Exu.ldExeUnitCfg) ++
77    Seq.fill(exuParameters.StuCnt)(Exu.stExeUnitCfg)
78
79  val exuConfigs = exeUnits.map(_.config) ++ memConfigs
80
81  val exeWbReqs = exeUnits.map(_.io.out) ++ io.mem.ldout ++ io.mem.stout
82
83  def needWakeup(cfg: ExuConfig): Boolean =
84    (cfg.readIntRf && cfg.writeIntRf) || (cfg.readFpRf && cfg.writeFpRf)
85
86  def needData(a: ExuConfig, b: ExuConfig): Boolean =
87    (a.readIntRf && b.writeIntRf) || (a.readFpRf && b.writeFpRf)
88
89
90  val reservedStations = exuConfigs.zipWithIndex.map({ case (cfg, i) =>
91    val wakeUpDateVec = exuConfigs.zip(exeWbReqs).filter(x => needData(cfg, x._1)).map(_._2)
92    val bypassCnt = exuConfigs.count(c => c.enableBypass && needData(cfg, c))
93
94    println(s"exu:${cfg.name} wakeupCnt:${wakeUpDateVec.length} bypassCnt:$bypassCnt")
95
96    val rs = Module(new ReservationStation(
97      cfg, wakeUpDateVec.length, bypassCnt, cfg.enableBypass, fifo = false
98    ))
99    rs.io.redirect <> redirect
100    rs.io.numExist <> dispatch.io.numExist(i)
101    rs.io.enqCtrl <> dispatch.io.enqIQCtrl(i)
102    rs.io.enqData <> dispatch.io.enqIQData(i)
103    for(
104      (wakeUpPort, exuOut) <-
105        rs.io.wakeUpPorts.zip(wakeUpDateVec)
106    ){
107      wakeUpPort.bits := exuOut.bits
108      wakeUpPort.valid := exuOut.valid
109    }
110
111    cfg match {
112      case Exu.ldExeUnitCfg =>
113      case Exu.stExeUnitCfg =>
114      case otherCfg =>
115        exeUnits(i).io.in <> rs.io.deq
116        exeUnits(i).io.redirect <> redirect
117        rs.io.tlbFeedback := DontCare
118    }
119
120    rs
121  })
122
123  for(rs <- reservedStations){
124    rs.io.bypassUops <> reservedStations.
125      filter(x => x.enableBypass && needData(rs.exuCfg, x.exuCfg)).
126      map(_.io.selectedUop)
127
128    val bypassDataVec = exuConfigs.zip(exeWbReqs).
129      filter(x => x._1.enableBypass && needData(rs.exuCfg, x._1)).map(_._2)
130
131    for(i <- bypassDataVec.indices){
132      rs.io.bypassData(i).valid := bypassDataVec(i).valid
133      rs.io.bypassData(i).bits := bypassDataVec(i).bits
134    }
135  }
136
137  io.mem.commits <> roq.io.commits
138  io.mem.roqDeqPtr := roq.io.roqDeqPtr
139  io.mem.ldin <> reservedStations.filter(_.exuCfg == Exu.ldExeUnitCfg).map(_.io.deq)
140  io.mem.stin <> reservedStations.filter(_.exuCfg == Exu.stExeUnitCfg).map(_.io.deq)
141  io.mem.tlbFeedback <> reservedStations.filter(_.exuCfg == Exu.ldExeUnitCfg).map(_.io.tlbFeedback) ++ reservedStations.filter(_.exuCfg == Exu.stExeUnitCfg).map(_.io.tlbFeedback)
142  jmpExeUnit.io.exception.valid := roq.io.redirect.valid && roq.io.redirect.bits.isException
143  jmpExeUnit.io.exception.bits := roq.io.exception
144
145  io.frontend.outOfOrderBrInfo <> brq.io.outOfOrderBrInfo
146  io.frontend.inOrderBrInfo <> brq.io.inOrderBrInfo
147
148  decode.io.in <> io.frontend.cfVec
149  brq.io.roqRedirect <> roq.io.redirect
150  brq.io.memRedirect <> io.mem.replayAll
151  brq.io.bcommit := roq.io.bcommit
152  brq.io.enqReqs <> decode.io.toBrq
153  for ((x, y) <- brq.io.exuRedirect.zip(exeUnits.filter(_.config.hasRedirect))) {
154    x.bits := y.io.out.bits
155    x.valid := y.io.out.fire() && y.io.out.bits.redirectValid
156  }
157  decode.io.brTags <> brq.io.brTags
158  decBuf.io.isWalking := ParallelOR(roq.io.commits.map(c => c.valid && c.bits.isWalk)) // TODO: opt this
159  decBuf.io.redirect <> redirect
160  decBuf.io.in <> decode.io.out
161
162  rename.io.redirect <> redirect
163  rename.io.roqCommits <> roq.io.commits
164  rename.io.in <> decBuf.io.out
165  rename.io.intRfReadAddr <> dispatch.io.readIntRf.map(_.addr) ++ dispatch.io.memIntRf.map(_.addr)
166  rename.io.intPregRdy <> dispatch.io.intPregRdy ++ dispatch.io.intMemRegRdy
167  rename.io.fpRfReadAddr <> dispatch.io.readFpRf.map(_.addr) ++ dispatch.io.memFpRf.map(_.addr)
168  rename.io.fpPregRdy <> dispatch.io.fpPregRdy ++ dispatch.io.fpMemRegRdy
169  rename.io.replayPregReq <> dispatch.io.replayPregReq
170  dispatch.io.redirect <> redirect
171  dispatch.io.fromRename <> rename.io.out
172
173  roq.io.memRedirect <> io.mem.replayAll
174  roq.io.brqRedirect <> brq.io.redirect
175  roq.io.dp1Req <> dispatch.io.toRoq
176  dispatch.io.roqIdxs <> roq.io.roqIdxs
177  io.mem.dp1Req <> dispatch.io.toLsroq
178  dispatch.io.commits <> roq.io.commits
179  dispatch.io.lsIdxs <> io.mem.lsIdxs
180
181  intRf.io.readPorts <> dispatch.io.readIntRf ++ dispatch.io.memIntRf
182  fpRf.io.readPorts <> dispatch.io.readFpRf ++ dispatch.io.memFpRf
183
184  io.mem.redirect <> redirect
185
186  val wbu = Module(new Wbu(exuConfigs))
187  wbu.io.in <> exeWbReqs
188
189  val wbIntResults = wbu.io.toIntRf
190  val wbFpResults = wbu.io.toFpRf
191
192  def exuOutToRfWrite(x: Valid[ExuOutput]): RfWritePort = {
193    val rfWrite = Wire(new RfWritePort)
194    rfWrite.wen := x.valid
195    rfWrite.addr := x.bits.uop.pdest
196    rfWrite.data := x.bits.data
197    rfWrite
198  }
199  intRf.io.writePorts <> wbIntResults.map(exuOutToRfWrite)
200  fpRf.io.writePorts <> wbFpResults.map(exuOutToRfWrite)
201
202  rename.io.wbIntResults <> wbIntResults
203  rename.io.wbFpResults <> wbFpResults
204
205  roq.io.exeWbResults.take(exeWbReqs.length).zip(wbu.io.toRoq).foreach(x => x._1 := x._2)
206  roq.io.exeWbResults.last := brq.io.out
207
208
209  // TODO: Remove sink and source
210  val tmp = WireInit(0.U)
211  val sinks = Array[String](
212    "DTLBFINISH",
213    "DTLBPF",
214    "DTLBENABLE",
215    "perfCntCondMdcacheLoss",
216    "perfCntCondMl2cacheLoss",
217    "perfCntCondMdcacheHit",
218    "lsuMMIO",
219    "perfCntCondMl2cacheHit",
220    "perfCntCondMl2cacheReq",
221    "mtip",
222    "perfCntCondMdcacheReq",
223    "meip"
224  )
225  for (s <- sinks) {
226    BoringUtils.addSink(tmp, s)
227  }
228
229  val debugIntReg, debugFpReg = WireInit(VecInit(Seq.fill(32)(0.U(XLEN.W))))
230  BoringUtils.addSink(debugIntReg, "DEBUG_INT_ARCH_REG")
231  BoringUtils.addSink(debugFpReg, "DEBUG_FP_ARCH_REG")
232  val debugArchReg = WireInit(VecInit(debugIntReg ++ debugFpReg))
233  if (!env.FPGAPlatform) {
234    BoringUtils.addSource(debugArchReg, "difftestRegs")
235  }
236
237}
238