| #
0162f462 |
| 24-Apr-2023 |
czw <[email protected]> |
type(FpWb): delete FpWB & rename VecWB to VfWB
|
| #
60f1a5fe |
| 10-Jun-2023 |
zhanglyGit <[email protected]> |
fix: fix lqdeq and sqdeq width in backend
|
| #
01ceb97c |
| 26-May-2023 |
Ziyue Zhang <[email protected]> |
vxsat: fix the value is always zero
|
| #
4ee69032 |
| 24-May-2023 |
zhanglyGit <[email protected]> |
VldIssue: backend support Vld issue
|
| #
e450f9ec |
| 04-Jun-2023 |
Xuan Hu <[email protected]> |
backend: get lcommit from mem lqDeq
|
| #
7b753beb |
| 04-Jun-2023 |
Xuan Hu <[email protected]> |
backend,mem: split feedback bundle into lda and sta
|
| #
dfb4c5dc |
| 30-May-2023 |
Xuan Hu <[email protected]> |
fix merge error
|
| #
68d13085 |
| 25-May-2023 |
Xuan Hu <[email protected]> |
Merge remote-tracking branch 'upstream/master' into tmp-new-backend-merge-vlsu
# Conflicts:
# .gitmodules
# build.sc
# src/main/scala/top/Configs.scala
# src/main/scala/xiangshan/Bundle.scala
# src/
Merge remote-tracking branch 'upstream/master' into tmp-new-backend-merge-vlsu
# Conflicts:
# .gitmodules
# build.sc
# src/main/scala/top/Configs.scala
# src/main/scala/xiangshan/Bundle.scala
# src/main/scala/xiangshan/Parameters.scala
# src/main/scala/xiangshan/XSCore.scala
# src/main/scala/xiangshan/backend/CtrlBlock.scala
# src/main/scala/xiangshan/backend/MemBlock.scala
# src/main/scala/xiangshan/backend/Scheduler.scala
# src/main/scala/xiangshan/backend/issue/ReservationStation.scala
# src/main/scala/xiangshan/backend/issue/StatusArray.scala
# src/main/scala/xiangshan/backend/rob/Rob.scala
# src/main/scala/xiangshan/mem/MemCommon.scala
# src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala
# src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
# src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
# src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
# src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
show more ...
|
| #
b6b11f60 |
| 22-May-2023 |
Xuan Hu <[email protected]> |
backend: add vector related datapath and configs
|
| #
a8db15d8 |
| 10-May-2023 |
fdy <[email protected]> |
backend: refactor vset and add rab support
|
| #
b52d4755 |
| 26-Apr-2023 |
Xuan Hu <[email protected]> |
isa-riscv,vector: add bundles and convert function
* Add class VType, VConfig
* Add object VSew, VLmul
|
| #
d91483a6 |
| 28-Apr-2023 |
fdy <[email protected]> |
add vset support
Co-authored-by: zhanglyGit <[email protected]>
Co-authored-by: Xuan Hu <[email protected]>
|
| #
d9674a27 |
| 19-Apr-2023 |
fdy <[email protected]> |
Backend: fix the flush signal
|
| #
730cfbc0 |
| 16-Apr-2023 |
Xuan Hu <[email protected]> |
backend: merge v2backend into backend
|
| #
1c2588aa |
| 18-Nov-2020 |
Yinan Xu <[email protected]> |
XSCore: use Blocks
|
| #
4693e1ab |
| 18-Nov-2020 |
Yinan Xu <[email protected]> |
Merge remote-tracking branch 'origin/master' into fix-module-level
|
| #
0412e00d |
| 16-Nov-2020 |
LinJiawei <[email protected]> |
[WIP] backend: connect ctrl block
|
| #
694b0180 |
| 16-Nov-2020 |
LinJiawei <[email protected]> |
[WIP] dispatch: do not need exuConfig form its params
|
| #
52c3f215 |
| 16-Nov-2020 |
LinJiawei <[email protected]> |
[WIP] exu: spilt exuConfig and it's module
|
| #
ccce3504 |
| 16-Nov-2020 |
LinJiawei <[email protected]> |
Merge remote-tracking branch 'origin/fix-module-level' into fp-recodeFN
|
| #
9684eb4f |
| 15-Nov-2020 |
LinJiawei <[email protected]> |
EXU: spilt int data path and float data path
|
| #
0e310298 |
| 13-Nov-2020 |
ZhangZifei <[email protected]> |
Sfence: fix bug: connect sfence from Backend to Ptw
|
| #
28a132d9 |
| 10-Nov-2020 |
Yinan Xu <[email protected]> |
dispatch: don't split int/fp and mem regfile read ports
|
| #
e18c367f |
| 08-Nov-2020 |
LinJiawei <[email protected]> |
[Backend]: Optimize exu and fu
|
| #
7eaf1071 |
| 06-Nov-2020 |
Yinan Xu <[email protected]> |
Merge remote-tracking branch 'origin/fix-dispatch-replay' into xs-fpu
|