1package xiangshan.backend 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import utility.PipelineConnect 8import xiangshan._ 9import xiangshan.backend.Bundles.{DynInst, MemExuInput, MemExuOutput} 10import xiangshan.backend.ctrlblock.CtrlBlock 11import xiangshan.backend.datapath.WbConfig._ 12import xiangshan.backend.datapath.{DataPath, WbDataPath} 13import xiangshan.backend.exu.ExuBlock 14import xiangshan.backend.fu.{FenceIO, FenceToSbuffer, PerfCounterIO} 15import xiangshan.backend.issue.Scheduler 16import xiangshan.backend.rob.RobLsqIO 17import xiangshan.frontend.{FtqPtr, FtqRead} 18import xiangshan.mem.{LqPtr, LsqEnqIO, SqPtr} 19 20class Backend(val params: BackendParams)(implicit p: Parameters) extends LazyModule 21 with HasXSParameter { 22 23 for (exuCfg <- params.allExuParams) { 24 val fuConfigs = exuCfg.fuConfigs 25 val wbPortConfigs = exuCfg.wbPortConfigs 26 val immType = exuCfg.immType 27 println(s"exu: ${fuConfigs.map(_.name)}, wb: ${wbPortConfigs}, imm: ${immType}") 28 require(wbPortConfigs.collectFirst { case x: IntWB => x }.nonEmpty == 29 fuConfigs.map(_.writeIntRf).reduce(_ || _), 30 "int wb port has no priority" ) 31 require(wbPortConfigs.collectFirst { case x: VecWB => x }.nonEmpty == 32 fuConfigs.map(x => x.writeFpRf || x.writeVecRf).reduce(_ || _), 33 "vec wb port has no priority" ) 34 } 35 36 println(s"Function Unit: Alu(${params.AluCnt}), Brh(${params.BrhCnt}), Jmp(${params.JmpCnt}), " + 37 s"Ldu(${params.LduCnt}), Sta(${params.StaCnt}), Std(${params.StdCnt})") 38 39 val ctrlBlock = LazyModule(new CtrlBlock(params)) 40 val intScheduler = params.intSchdParams.map(x => LazyModule(new Scheduler(x))) 41 val vfScheduler = params.vfSchdParams.map(x => LazyModule(new Scheduler(x))) 42 val memScheduler = params.memSchdParams.map(x => LazyModule(new Scheduler(x))) 43 val dataPath = LazyModule(new DataPath(params)) 44 val intExuBlock = params.intSchdParams.map(x => LazyModule(new ExuBlock(x))) 45 val vfExuBlock = params.vfSchdParams.map(x => LazyModule(new ExuBlock(x))) 46 47 lazy val module = new BackendImp(this) 48} 49 50class BackendImp(override val wrapper: Backend)(implicit p: Parameters) extends LazyModuleImp(wrapper) { 51 implicit private val params = wrapper.params 52 val io = IO(new BackendIO()(p, wrapper.params)) 53 54 private val ctrlBlock = wrapper.ctrlBlock.module 55 private val intScheduler = wrapper.intScheduler.get.module 56 private val vfScheduler = wrapper.vfScheduler.get.module 57 private val memScheduler = wrapper.memScheduler.get.module 58 private val dataPath = wrapper.dataPath.module 59 private val intExuBlock = wrapper.intExuBlock.get.module 60 private val vfExuBlock = wrapper.vfExuBlock.get.module 61 private val wbDataPath = Module(new WbDataPath(params)) 62 63 ctrlBlock.io.fromTop.hartId := io.fromTop.hartId 64 ctrlBlock.io.frontend <> io.frontend 65 ctrlBlock.io.fromWB.wbData <> wbDataPath.io.toCtrlBlock.writeback 66 ctrlBlock.io.fromMem.stIn <> io.mem.stIn 67 ctrlBlock.io.fromMem.violation <> io.mem.memoryViolation 68 ctrlBlock.io.csrCtrl <> intExuBlock.io.csrio.get.customCtrl 69 ctrlBlock.io.robio.csr.intrBitSet := intExuBlock.io.csrio.get.interrupt 70 ctrlBlock.io.robio.csr.trapTarget := intExuBlock.io.csrio.get.trapTarget 71 ctrlBlock.io.robio.csr.isXRet := intExuBlock.io.csrio.get.isXRet 72 ctrlBlock.io.robio.csr.wfiEvent := intExuBlock.io.csrio.get.wfi_event 73 ctrlBlock.io.robio.lsq <> io.mem.robLsqIO 74 75 intScheduler.io.fromTop.hartId := io.fromTop.hartId 76 intScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 77 intScheduler.io.fromCtrlBlock.pcVec := ctrlBlock.io.toIssueBlock.pcVec 78 intScheduler.io.fromCtrlBlock.targetVec := ctrlBlock.io.toIssueBlock.targetVec 79 intScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 80 intScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.intUops 81 intScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 82 intScheduler.io.vfWriteBack := 0.U.asTypeOf(intScheduler.io.vfWriteBack) 83 84 memScheduler.io.fromTop.hartId := io.fromTop.hartId 85 memScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 86 memScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 87 memScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.memUops 88 memScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 89 memScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 90 memScheduler.io.fromMem.get.scommit := io.mem.sqDeq 91 memScheduler.io.fromMem.get.lcommit := ctrlBlock.io.robio.lsq.lcommit 92 memScheduler.io.fromMem.get.sqCancelCnt := io.mem.sqCancelCnt 93 memScheduler.io.fromMem.get.lqCancelCnt := io.mem.lqCancelCnt 94 memScheduler.io.fromMem.get.stIssuePtr := io.mem.stIssuePtr 95 memScheduler.io.fromMem.get.memWaitUpdateReq.staIssue.zip(io.mem.stIn).foreach { case (sink, source) => 96 sink.valid := source.valid 97 sink.bits.uop := 0.U.asTypeOf(sink.bits.uop) 98 sink.bits.uop.robIdx := source.bits.robIdx 99 } 100 101 vfScheduler.io.fromTop.hartId := io.fromTop.hartId 102 vfScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 103 vfScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 104 vfScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.vfUops 105 vfScheduler.io.intWriteBack := 0.U.asTypeOf(vfScheduler.io.intWriteBack) 106 vfScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 107 108 dataPath.io.flush := ctrlBlock.io.toDataPath.flush 109 110 for (i <- 0 until dataPath.io.fromIntIQ.length) { 111 for (j <- 0 until dataPath.io.fromIntIQ(i).length) { 112 PipelineConnect(intScheduler.io.toDataPath(i)(j), dataPath.io.fromIntIQ(i)(j), dataPath.io.fromIntIQ(i)(j).valid, 113 intScheduler.io.toDataPath(i)(j).bits.common.robIdx.needFlush(ctrlBlock.io.toDataPath.flush)) 114 intScheduler.io.fromDataPath(i)(j) := dataPath.io.toIntIQ(i)(j) 115 } 116 } 117 118 dataPath.io.fromVfIQ <> vfScheduler.io.toDataPath 119 vfScheduler.io.fromDataPath := dataPath.io.toVfIQ 120 dataPath.io.fromMemIQ <> memScheduler.io.toDataPath 121 memScheduler.io.fromDataPath := dataPath.io.toMemIQ 122 123 println(s"[Backend] wbDataPath.io.toIntPreg: ${wbDataPath.io.toIntPreg.size}, dataPath.io.fromIntWb: ${dataPath.io.fromIntWb.size}") 124 println(s"[Backend] wbDataPath.io.toVfPreg: ${wbDataPath.io.toVfPreg.size}, dataPath.io.fromFpWb: ${dataPath.io.fromVfWb.size}") 125 dataPath.io.fromIntWb := wbDataPath.io.toIntPreg 126 dataPath.io.fromVfWb := wbDataPath.io.toVfPreg 127 dataPath.io.debugIntRat := ctrlBlock.io.debug_int_rat 128 dataPath.io.debugFpRat := ctrlBlock.io.debug_fp_rat 129 dataPath.io.debugVecRat := ctrlBlock.io.debug_vec_rat 130 131 intExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 132 for (i <- 0 until intExuBlock.io.in.length) { 133 for (j <- 0 until intExuBlock.io.in(i).length) { 134 PipelineConnect(dataPath.io.toIntExu(i)(j), intExuBlock.io.in(i)(j), intExuBlock.io.in(i)(j).fire, 135 Mux(dataPath.io.toIntExu(i)(j).fire, 136 dataPath.io.toIntExu(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush), 137 intExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush))) 138 } 139 } 140 141 private val csrio = intExuBlock.io.csrio.get 142 csrio.hartId := io.fromTop.hartId 143 csrio.perf.retiredInstr <> ctrlBlock.io.robio.csr.perfinfo.retiredInstr 144 csrio.perf.ctrlInfo <> ctrlBlock.io.perfInfo.ctrlInfo 145 csrio.perf.perfEventsCtrl <> ctrlBlock.getPerf 146 csrio.fpu.fflags := ctrlBlock.io.robio.csr.fflags 147 csrio.fpu.isIllegal := false.B // Todo: remove it 148 csrio.fpu.dirty_fs := ctrlBlock.io.robio.csr.dirty_fs 149 csrio.vpu <> 0.U.asTypeOf(csrio.vpu) // Todo 150 csrio.exception := ctrlBlock.io.robio.exception 151 csrio.memExceptionVAddr := io.mem.exceptionVAddr 152 csrio.externalInterrupt := io.fromTop.externalInterrupt 153 csrio.distributedUpdate(0) := io.mem.csrDistributedUpdate 154 csrio.distributedUpdate(1) := io.frontendCsrDistributedUpdate 155 csrio.perf <> io.perf 156 private val fenceio = intExuBlock.io.fenceio.get 157 fenceio.disableSfence := csrio.disableSfence 158 io.fenceio <> fenceio 159 160 vfExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 161 for (i <- 0 until vfExuBlock.io.in.size) { 162 for (j <- 0 until vfExuBlock.io.in(i).size) { 163 PipelineConnect(dataPath.io.toFpExu(i)(j), vfExuBlock.io.in(i)(j), vfExuBlock.io.in(i)(j).fire, 164 Mux(dataPath.io.toFpExu(i)(j).fire, 165 dataPath.io.toFpExu(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush), 166 vfExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush))) 167 } 168 } 169 vfExuBlock.io.frm.get := csrio.fpu.frm 170 171 wbDataPath.io.flush := ctrlBlock.io.redirect 172 wbDataPath.io.fromTop.hartId := io.fromTop.hartId 173 wbDataPath.io.fromIntExu <> intExuBlock.io.out 174 wbDataPath.io.fromVfExu <> vfExuBlock.io.out 175 wbDataPath.io.fromMemExu.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 176 sink.valid := source.valid 177 source.ready := sink.ready 178 sink.bits.data := source.bits.data 179 sink.bits.pdest := source.bits.uop.pdest 180 sink.bits.robIdx := source.bits.uop.robIdx 181 sink.bits.intWen.foreach(_ := source.bits.uop.rfWen) 182 sink.bits.fpWen.foreach(_ := source.bits.uop.fpWen) 183 sink.bits.vecWen.foreach(_ := source.bits.uop.vecWen) 184 sink.bits.exceptionVec.foreach(_ := source.bits.uop.exceptionVec) 185 sink.bits.flushPipe.foreach(_ := source.bits.uop.flushPipe) 186 sink.bits.replay.foreach(_ := source.bits.uop.replayInst) 187 sink.bits.debug := source.bits.debug 188 sink.bits.debugInfo := 0.U.asTypeOf(sink.bits.debugInfo) 189 sink.bits.lqIdx.foreach(_ := source.bits.uop.lqIdx) 190 sink.bits.sqIdx.foreach(_ := source.bits.uop.sqIdx) 191 sink.bits.ftqIdx.foreach(_ := source.bits.uop.ftqPtr) 192 sink.bits.ftqOffset.foreach(_ := source.bits.uop.ftqOffset) 193 } 194 195 // to mem 196 io.mem.redirect := ctrlBlock.io.redirect 197 io.mem.issueUops.zip(dataPath.io.toMemExu.flatten).foreach { case (sink, source) => 198 sink.valid := source.valid 199 source.ready := sink.ready 200 sink.bits.iqIdx := source.bits.iqIdx 201 sink.bits.isFirstIssue := source.bits.isFirstIssue 202 sink.bits.uop := 0.U.asTypeOf(sink.bits.uop) 203 sink.bits.src := 0.U.asTypeOf(sink.bits.src) 204 sink.bits.src.zip(source.bits.src).foreach { case (l, r) => l := r} 205 sink.bits.uop.fuType := source.bits.fuType 206 sink.bits.uop.fuOpType := source.bits.fuOpType 207 sink.bits.uop.imm := source.bits.imm 208 sink.bits.uop.robIdx := source.bits.robIdx 209 sink.bits.uop.pdest := source.bits.pdest 210 sink.bits.uop.rfWen := source.bits.rfWen.getOrElse(false.B) 211 sink.bits.uop.fpWen := source.bits.fpWen.getOrElse(false.B) 212 sink.bits.uop.vecWen := source.bits.vecWen.getOrElse(false.B) 213 sink.bits.uop.flushPipe := source.bits.flushPipe.getOrElse(false.B) 214 sink.bits.uop.pc := source.bits.pc.getOrElse(0.U) 215 sink.bits.uop.lqIdx := source.bits.lqIdx.getOrElse(0.U.asTypeOf(new LqPtr)) 216 sink.bits.uop.sqIdx := source.bits.sqIdx.getOrElse(0.U.asTypeOf(new SqPtr)) 217 sink.bits.uop.ftqPtr := source.bits.ftqIdx.getOrElse(0.U.asTypeOf(new FtqPtr)) 218 sink.bits.uop.ftqOffset := source.bits.ftqOffset.getOrElse(0.U) 219 } 220 io.mem.loadFastMatch := memScheduler.io.toMem.get.loadFastMatch.map(_.fastMatch) 221 io.mem.loadFastImm := memScheduler.io.toMem.get.loadFastMatch.map(_.fastImm) 222 io.mem.tlbCsr := csrio.tlb 223 io.mem.csrCtrl := csrio.customCtrl 224 io.mem.sfence := fenceio.sfence 225 io.mem.isStoreException := CommitType.lsInstIsStore(ctrlBlock.io.robio.exception.bits.commitType) 226 require(io.mem.loadPcRead.size == params.LduCnt) 227 io.mem.loadPcRead.zipWithIndex.foreach { case (loadPcRead, i) => 228 loadPcRead.data := ctrlBlock.io.memLdPcRead(i).data 229 ctrlBlock.io.memLdPcRead(i).ptr := loadPcRead.ptr 230 ctrlBlock.io.memLdPcRead(i).offset := loadPcRead.offset 231 } 232 // mem io 233 io.mem.lsqEnqIO <> memScheduler.io.memIO.get.lsqEnqIO 234 io.mem.robLsqIO <> ctrlBlock.io.robio.lsq 235 io.mem.toSbuffer <> fenceio.sbuffer 236 io.mem.rsFeedBack <> memScheduler.io.memIO.get.feedbackIO 237 238 io.frontendSfence := fenceio.sfence 239 io.frontendTlbCsr := csrio.tlb 240 io.frontendCsrCtrl := csrio.customCtrl 241 242 io.tlb <> csrio.tlb 243 244 io.csrCustomCtrl := csrio.customCtrl 245 246 dontTouch(memScheduler.io) 247 dontTouch(io.mem) 248 dontTouch(dataPath.io.toMemExu) 249 dontTouch(wbDataPath.io.fromMemExu) 250} 251 252class BackendMemIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 253 // In/Out // Todo: split it into one-direction bundle 254 val lsqEnqIO = Flipped(new LsqEnqIO) 255 val robLsqIO = new RobLsqIO 256 val toSbuffer = new FenceToSbuffer 257 val rsFeedBack = Vec(params.StaCnt, Flipped(new MemRSFeedbackIO)) 258 val loadPcRead = Vec(params.LduCnt, Flipped(new FtqRead(UInt(VAddrBits.W)))) 259 260 // Input 261 val writeBack = Vec(params.LduCnt + params.StaCnt * 2, Flipped(DecoupledIO(new MemExuOutput()))) 262 263 val s3_delayed_load_error = Input(Vec(LoadPipelineWidth, Bool())) 264 val stIn = Input(Vec(params.StaCnt, ValidIO(new DynInst()))) 265 val memoryViolation = Flipped(ValidIO(new Redirect)) 266 val exceptionVAddr = Input(UInt(VAddrBits.W)) 267 val sqDeq = Input(UInt(params.StaCnt.W)) 268 269 val lqCancelCnt = Input(UInt(log2Up(LoadQueueSize + 1).W)) 270 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 271 272 val otherFastWakeup = Flipped(Vec(params.LduCnt + 2 * params.StaCnt, ValidIO(new DynInst))) 273 val stIssuePtr = Input(new SqPtr()) 274 275 val csrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 276 277 // Output 278 val redirect = ValidIO(new Redirect) // rob flush MemBlock 279 val issueUops = Vec(params.LduCnt + 2 * params.StaCnt, DecoupledIO(new MemExuInput())) 280 val loadFastMatch = Vec(params.LduCnt, Output(UInt(params.LduCnt.W))) 281 val loadFastImm = Vec(params.LduCnt, Output(UInt(12.W))) // Imm_I 282 283 val tlbCsr = Output(new TlbCsrBundle) 284 val csrCtrl = Output(new CustomCSRCtrlIO) 285 val sfence = Output(new SfenceBundle) 286 val isStoreException = Output(Bool()) 287} 288 289class BackendIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 290 val fromTop = new Bundle { 291 val hartId = Input(UInt(8.W)) 292 val externalInterrupt = new ExternalInterruptIO 293 } 294 295 val toTop = new Bundle { 296 val cpuHalted = Output(Bool()) 297 } 298 299 val fenceio = new FenceIO 300 // Todo: merge these bundles into BackendFrontendIO 301 val frontend = Flipped(new FrontendToCtrlIO) 302 val frontendSfence = Output(new SfenceBundle) 303 val frontendCsrCtrl = Output(new CustomCSRCtrlIO) 304 val frontendTlbCsr = Output(new TlbCsrBundle) 305 // distributed csr write 306 val frontendCsrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 307 308 val mem = new BackendMemIO 309 310 val perf = Input(new PerfCounterIO) 311 312 val tlb = Output(new TlbCsrBundle) 313 314 val csrCustomCtrl = Output(new CustomCSRCtrlIO) 315} 316