1package xiangshan.backend 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import utility.{PipelineConnect, ZeroExt} 8import xiangshan._ 9import xiangshan.backend.Bundles.{DynInst, MemExuInput, MemExuOutput} 10import xiangshan.backend.ctrlblock.CtrlBlock 11import xiangshan.backend.datapath.WbConfig._ 12import xiangshan.backend.datapath.{DataPath, WbDataPath} 13import xiangshan.backend.exu.ExuBlock 14import xiangshan.backend.fu.vector.Bundles.{VConfig, VType} 15import xiangshan.backend.fu.{FenceIO, FenceToSbuffer, PerfCounterIO, FuConfig} 16import xiangshan.backend.issue.Scheduler 17import xiangshan.backend.rob.RobLsqIO 18import xiangshan.frontend.{FtqPtr, FtqRead} 19import xiangshan.mem.{LqPtr, LsqEnqIO, SqPtr} 20 21class Backend(val params: BackendParams)(implicit p: Parameters) extends LazyModule 22 with HasXSParameter { 23 24 for (exuCfg <- params.allExuParams) { 25 val fuConfigs = exuCfg.fuConfigs 26 val wbPortConfigs = exuCfg.wbPortConfigs 27 val immType = exuCfg.immType 28 println(s"exu: ${fuConfigs.map(_.name)}, wb: ${wbPortConfigs}, imm: ${immType}") 29 require(wbPortConfigs.collectFirst { case x: IntWB => x }.nonEmpty == 30 fuConfigs.map(_.writeIntRf).reduce(_ || _), 31 "int wb port has no priority" ) 32 require(wbPortConfigs.collectFirst { case x: VecWB => x }.nonEmpty == 33 fuConfigs.map(x => x.writeFpRf || x.writeVecRf).reduce(_ || _), 34 "vec wb port has no priority" ) 35 } 36 37 println(s"Function Unit: Alu(${params.AluCnt}), Brh(${params.BrhCnt}), Jmp(${params.JmpCnt}), " + 38 s"Ldu(${params.LduCnt}), Sta(${params.StaCnt}), Std(${params.StdCnt})") 39 40 for (cfg <- FuConfig.allConfigs) { 41 println(s"[Backend] $cfg") 42 } 43 44 val ctrlBlock = LazyModule(new CtrlBlock(params)) 45 val intScheduler = params.intSchdParams.map(x => LazyModule(new Scheduler(x))) 46 val vfScheduler = params.vfSchdParams.map(x => LazyModule(new Scheduler(x))) 47 val memScheduler = params.memSchdParams.map(x => LazyModule(new Scheduler(x))) 48 val dataPath = LazyModule(new DataPath(params)) 49 val intExuBlock = params.intSchdParams.map(x => LazyModule(new ExuBlock(x))) 50 val vfExuBlock = params.vfSchdParams.map(x => LazyModule(new ExuBlock(x))) 51 52 lazy val module = new BackendImp(this) 53} 54 55class BackendImp(override val wrapper: Backend)(implicit p: Parameters) extends LazyModuleImp(wrapper) 56 with HasXSParameter{ 57 implicit private val params = wrapper.params 58 val io = IO(new BackendIO()(p, wrapper.params)) 59 60 private val ctrlBlock = wrapper.ctrlBlock.module 61 private val intScheduler = wrapper.intScheduler.get.module 62 private val vfScheduler = wrapper.vfScheduler.get.module 63 private val memScheduler = wrapper.memScheduler.get.module 64 private val dataPath = wrapper.dataPath.module 65 private val intExuBlock = wrapper.intExuBlock.get.module 66 private val vfExuBlock = wrapper.vfExuBlock.get.module 67 private val wbDataPath = Module(new WbDataPath(params)) 68 69 ctrlBlock.io.fromTop.hartId := io.fromTop.hartId 70 ctrlBlock.io.frontend <> io.frontend 71 ctrlBlock.io.fromWB.wbData <> wbDataPath.io.toCtrlBlock.writeback 72 ctrlBlock.io.fromMem.stIn <> io.mem.stIn 73 ctrlBlock.io.fromMem.violation <> io.mem.memoryViolation 74 ctrlBlock.io.csrCtrl <> intExuBlock.io.csrio.get.customCtrl 75 ctrlBlock.io.robio.csr.intrBitSet := intExuBlock.io.csrio.get.interrupt 76 ctrlBlock.io.robio.csr.trapTarget := intExuBlock.io.csrio.get.trapTarget 77 ctrlBlock.io.robio.csr.isXRet := intExuBlock.io.csrio.get.isXRet 78 ctrlBlock.io.robio.csr.wfiEvent := intExuBlock.io.csrio.get.wfi_event 79 ctrlBlock.io.robio.lsq <> io.mem.robLsqIO 80 81 intScheduler.io.fromTop.hartId := io.fromTop.hartId 82 intScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 83 intScheduler.io.fromCtrlBlock.pcVec := ctrlBlock.io.toIssueBlock.pcVec 84 intScheduler.io.fromCtrlBlock.targetVec := ctrlBlock.io.toIssueBlock.targetVec 85 intScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 86 intScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.intUops 87 intScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 88 intScheduler.io.vfWriteBack := 0.U.asTypeOf(intScheduler.io.vfWriteBack) 89 90 memScheduler.io.fromTop.hartId := io.fromTop.hartId 91 memScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 92 memScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 93 memScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.memUops 94 memScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 95 memScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 96 memScheduler.io.fromMem.get.scommit := io.mem.sqDeq 97 memScheduler.io.fromMem.get.lcommit := io.mem.lqDeq 98 memScheduler.io.fromMem.get.sqCancelCnt := io.mem.sqCancelCnt 99 memScheduler.io.fromMem.get.lqCancelCnt := io.mem.lqCancelCnt 100 memScheduler.io.fromMem.get.stIssuePtr := io.mem.stIssuePtr 101 memScheduler.io.fromMem.get.memWaitUpdateReq.staIssue.zip(io.mem.stIn).foreach { case (sink, source) => 102 sink.valid := source.valid 103 sink.bits.uop := 0.U.asTypeOf(sink.bits.uop) 104 sink.bits.uop.robIdx := source.bits.robIdx 105 } 106 io.mem.ldaIqFeedback <> memScheduler.io.fromMem.get.ldaFeedback 107 io.mem.staIqFeedback <> memScheduler.io.fromMem.get.staFeedback 108 109 vfScheduler.io.fromTop.hartId := io.fromTop.hartId 110 vfScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 111 vfScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 112 vfScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.vfUops 113 vfScheduler.io.intWriteBack := 0.U.asTypeOf(vfScheduler.io.intWriteBack) 114 vfScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 115 116 dataPath.io.flush := ctrlBlock.io.toDataPath.flush 117 dataPath.io.vconfigReadPort.addr := ctrlBlock.io.toDataPath.vtypeAddr 118 val vconfig = dataPath.io.vconfigReadPort.data 119 ctrlBlock.io.fromDataPath.vtype := vconfig(7, 0).asTypeOf(new VType) 120 for (i <- 0 until dataPath.io.fromIntIQ.length) { 121 for (j <- 0 until dataPath.io.fromIntIQ(i).length) { 122 PipelineConnect(intScheduler.io.toDataPath(i)(j), dataPath.io.fromIntIQ(i)(j), dataPath.io.fromIntIQ(i)(j).valid, 123 intScheduler.io.toDataPath(i)(j).bits.common.robIdx.needFlush(ctrlBlock.io.toDataPath.flush)) 124 intScheduler.io.fromDataPath(i)(j) := dataPath.io.toIntIQ(i)(j) 125 } 126 } 127 128 dataPath.io.fromVfIQ <> vfScheduler.io.toDataPath 129 vfScheduler.io.fromDataPath := dataPath.io.toVfIQ 130 dataPath.io.fromMemIQ <> memScheduler.io.toDataPath 131 memScheduler.io.fromDataPath := dataPath.io.toMemIQ 132 133 println(s"[Backend] wbDataPath.io.toIntPreg: ${wbDataPath.io.toIntPreg.size}, dataPath.io.fromIntWb: ${dataPath.io.fromIntWb.size}") 134 println(s"[Backend] wbDataPath.io.toVfPreg: ${wbDataPath.io.toVfPreg.size}, dataPath.io.fromFpWb: ${dataPath.io.fromVfWb.size}") 135 dataPath.io.fromIntWb := wbDataPath.io.toIntPreg 136 dataPath.io.fromVfWb := wbDataPath.io.toVfPreg 137 dataPath.io.debugIntRat := ctrlBlock.io.debug_int_rat 138 dataPath.io.debugFpRat := ctrlBlock.io.debug_fp_rat 139 dataPath.io.debugVecRat := ctrlBlock.io.debug_vec_rat 140 dataPath.io.debugVconfigRat := ctrlBlock.io.debug_vconfig_rat 141 142 intExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 143 for (i <- 0 until intExuBlock.io.in.length) { 144 for (j <- 0 until intExuBlock.io.in(i).length) { 145 PipelineConnect(dataPath.io.toIntExu(i)(j), intExuBlock.io.in(i)(j), intExuBlock.io.in(i)(j).fire, 146 Mux(dataPath.io.toIntExu(i)(j).fire, 147 dataPath.io.toIntExu(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush), 148 intExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush))) 149 } 150 } 151 152 private val csrio = intExuBlock.io.csrio.get 153 csrio.hartId := io.fromTop.hartId 154 csrio.perf.retiredInstr <> ctrlBlock.io.robio.csr.perfinfo.retiredInstr 155 csrio.perf.ctrlInfo <> ctrlBlock.io.perfInfo.ctrlInfo 156 csrio.perf.perfEventsCtrl <> ctrlBlock.getPerf 157 csrio.fpu.fflags := ctrlBlock.io.robio.csr.fflags 158 csrio.fpu.isIllegal := false.B // Todo: remove it 159 csrio.fpu.dirty_fs := ctrlBlock.io.robio.csr.dirty_fs 160 csrio.vpu <> 0.U.asTypeOf(csrio.vpu) // Todo 161 162 val debugVconfig = dataPath.io.debugVconfig.asTypeOf(new VConfig) 163 val debugVtype = VType.toVtypeStruct(debugVconfig.vtype).asUInt 164 val debugVl = debugVconfig.vl 165 csrio.vpu.set_vstart.valid := ctrlBlock.io.robio.csr.vcsrFlag 166 csrio.vpu.set_vstart.bits := 0.U 167 csrio.vpu.set_vtype.valid := ctrlBlock.io.robio.csr.vcsrFlag 168 csrio.vpu.set_vtype.bits := ZeroExt(debugVtype, XLEN) 169 csrio.vpu.set_vl.valid := ctrlBlock.io.robio.csr.vcsrFlag 170 csrio.vpu.set_vl.bits := ZeroExt(debugVl, XLEN) 171 csrio.exception := ctrlBlock.io.robio.exception 172 csrio.memExceptionVAddr := io.mem.exceptionVAddr 173 csrio.externalInterrupt := io.fromTop.externalInterrupt 174 csrio.distributedUpdate(0) := io.mem.csrDistributedUpdate 175 csrio.distributedUpdate(1) := io.frontendCsrDistributedUpdate 176 csrio.perf <> io.perf 177 private val fenceio = intExuBlock.io.fenceio.get 178 fenceio.disableSfence := csrio.disableSfence 179 io.fenceio <> fenceio 180 181 vfExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 182 for (i <- 0 until vfExuBlock.io.in.size) { 183 for (j <- 0 until vfExuBlock.io.in(i).size) { 184 PipelineConnect(dataPath.io.toFpExu(i)(j), vfExuBlock.io.in(i)(j), vfExuBlock.io.in(i)(j).fire, 185 Mux(dataPath.io.toFpExu(i)(j).fire, 186 dataPath.io.toFpExu(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush), 187 vfExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush))) 188 } 189 } 190 vfExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 191 192 wbDataPath.io.flush := ctrlBlock.io.redirect 193 wbDataPath.io.fromTop.hartId := io.fromTop.hartId 194 wbDataPath.io.fromIntExu <> intExuBlock.io.out 195 wbDataPath.io.fromVfExu <> vfExuBlock.io.out 196 wbDataPath.io.fromMemExu.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 197 sink.valid := source.valid 198 source.ready := sink.ready 199 sink.bits.data := source.bits.data 200 sink.bits.pdest := source.bits.uop.pdest 201 sink.bits.robIdx := source.bits.uop.robIdx 202 sink.bits.intWen.foreach(_ := source.bits.uop.rfWen) 203 sink.bits.fpWen.foreach(_ := source.bits.uop.fpWen) 204 sink.bits.vecWen.foreach(_ := source.bits.uop.vecWen) 205 sink.bits.exceptionVec.foreach(_ := source.bits.uop.exceptionVec) 206 sink.bits.flushPipe.foreach(_ := source.bits.uop.flushPipe) 207 sink.bits.replay.foreach(_ := source.bits.uop.replayInst) 208 sink.bits.debug := source.bits.debug 209 sink.bits.debugInfo := 0.U.asTypeOf(sink.bits.debugInfo) 210 sink.bits.lqIdx.foreach(_ := source.bits.uop.lqIdx) 211 sink.bits.sqIdx.foreach(_ := source.bits.uop.sqIdx) 212 sink.bits.ftqIdx.foreach(_ := source.bits.uop.ftqPtr) 213 sink.bits.ftqOffset.foreach(_ := source.bits.uop.ftqOffset) 214 } 215 216 // to mem 217 io.mem.redirect := ctrlBlock.io.redirect 218 io.mem.issueUops.zip(dataPath.io.toMemExu.flatten).foreach { case (sink, source) => 219 sink.valid := source.valid 220 source.ready := sink.ready 221 sink.bits.iqIdx := source.bits.iqIdx 222 sink.bits.isFirstIssue := source.bits.isFirstIssue 223 sink.bits.uop := 0.U.asTypeOf(sink.bits.uop) 224 sink.bits.src := 0.U.asTypeOf(sink.bits.src) 225 sink.bits.src.zip(source.bits.src).foreach { case (l, r) => l := r} 226 sink.bits.uop.fuType := source.bits.fuType 227 sink.bits.uop.fuOpType := source.bits.fuOpType 228 sink.bits.uop.imm := source.bits.imm 229 sink.bits.uop.robIdx := source.bits.robIdx 230 sink.bits.uop.pdest := source.bits.pdest 231 sink.bits.uop.rfWen := source.bits.rfWen.getOrElse(false.B) 232 sink.bits.uop.fpWen := source.bits.fpWen.getOrElse(false.B) 233 sink.bits.uop.vecWen := source.bits.vecWen.getOrElse(false.B) 234 sink.bits.uop.flushPipe := source.bits.flushPipe.getOrElse(false.B) 235 sink.bits.uop.pc := source.bits.pc.getOrElse(0.U) 236 sink.bits.uop.lqIdx := source.bits.lqIdx.getOrElse(0.U.asTypeOf(new LqPtr)) 237 sink.bits.uop.sqIdx := source.bits.sqIdx.getOrElse(0.U.asTypeOf(new SqPtr)) 238 sink.bits.uop.ftqPtr := source.bits.ftqIdx.getOrElse(0.U.asTypeOf(new FtqPtr)) 239 sink.bits.uop.ftqOffset := source.bits.ftqOffset.getOrElse(0.U) 240 } 241 io.mem.loadFastMatch := memScheduler.io.toMem.get.loadFastMatch.map(_.fastMatch) 242 io.mem.loadFastImm := memScheduler.io.toMem.get.loadFastMatch.map(_.fastImm) 243 io.mem.tlbCsr := csrio.tlb 244 io.mem.csrCtrl := csrio.customCtrl 245 io.mem.sfence := fenceio.sfence 246 io.mem.isStoreException := CommitType.lsInstIsStore(ctrlBlock.io.robio.exception.bits.commitType) 247 require(io.mem.loadPcRead.size == params.LduCnt) 248 io.mem.loadPcRead.zipWithIndex.foreach { case (loadPcRead, i) => 249 loadPcRead.data := ctrlBlock.io.memLdPcRead(i).data 250 ctrlBlock.io.memLdPcRead(i).ptr := loadPcRead.ptr 251 ctrlBlock.io.memLdPcRead(i).offset := loadPcRead.offset 252 } 253 // mem io 254 io.mem.lsqEnqIO <> memScheduler.io.memIO.get.lsqEnqIO 255 io.mem.robLsqIO <> ctrlBlock.io.robio.lsq 256 io.mem.toSbuffer <> fenceio.sbuffer 257 258 io.frontendSfence := fenceio.sfence 259 io.frontendTlbCsr := csrio.tlb 260 io.frontendCsrCtrl := csrio.customCtrl 261 262 io.tlb <> csrio.tlb 263 264 io.csrCustomCtrl := csrio.customCtrl 265 266 dontTouch(memScheduler.io) 267 dontTouch(io.mem) 268 dontTouch(dataPath.io.toMemExu) 269 dontTouch(wbDataPath.io.fromMemExu) 270} 271 272class BackendMemIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 273 // params alias 274 private val LoadQueueSize = VirtualLoadQueueSize 275 // In/Out // Todo: split it into one-direction bundle 276 val lsqEnqIO = Flipped(new LsqEnqIO) 277 val robLsqIO = new RobLsqIO 278 val toSbuffer = new FenceToSbuffer 279 val ldaIqFeedback = Vec(params.LduCnt, Flipped(new MemRSFeedbackIO)) 280 val staIqFeedback = Vec(params.StaCnt, Flipped(new MemRSFeedbackIO)) 281 val loadPcRead = Vec(params.LduCnt, Flipped(new FtqRead(UInt(VAddrBits.W)))) 282 283 // Input 284 val writeBack = MixedVec(Seq.fill(params.LduCnt + params.StaCnt * 2)(Flipped(DecoupledIO(new MemExuOutput()))) ++ Seq.fill(params.VlduCnt)(Flipped(DecoupledIO(new MemExuOutput(true))))) 285 286 val s3_delayed_load_error = Input(Vec(LoadPipelineWidth, Bool())) 287 val stIn = Input(Vec(params.StaCnt, ValidIO(new DynInst()))) 288 val memoryViolation = Flipped(ValidIO(new Redirect)) 289 val exceptionVAddr = Input(UInt(VAddrBits.W)) 290 val sqDeq = Input(UInt(params.StaCnt.W)) 291 val lqDeq = Input(UInt(params.LduCnt.W)) 292 293 val lqCancelCnt = Input(UInt(log2Up(LoadQueueSize + 1).W)) 294 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 295 296 val otherFastWakeup = Flipped(Vec(params.LduCnt + 2 * params.StaCnt, ValidIO(new DynInst))) 297 val stIssuePtr = Input(new SqPtr()) 298 299 val csrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 300 301 // Output 302 val redirect = ValidIO(new Redirect) // rob flush MemBlock 303 val issueUops = MixedVec(Seq.fill(params.LduCnt + params.StaCnt * 2)(DecoupledIO(new MemExuInput())) ++ Seq.fill(params.VlduCnt)(DecoupledIO(new MemExuInput(true)))) 304 val loadFastMatch = Vec(params.LduCnt, Output(UInt(params.LduCnt.W))) 305 val loadFastImm = Vec(params.LduCnt, Output(UInt(12.W))) // Imm_I 306 307 val tlbCsr = Output(new TlbCsrBundle) 308 val csrCtrl = Output(new CustomCSRCtrlIO) 309 val sfence = Output(new SfenceBundle) 310 val isStoreException = Output(Bool()) 311} 312 313class BackendIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 314 val fromTop = new Bundle { 315 val hartId = Input(UInt(8.W)) 316 val externalInterrupt = new ExternalInterruptIO 317 } 318 319 val toTop = new Bundle { 320 val cpuHalted = Output(Bool()) 321 } 322 323 val fenceio = new FenceIO 324 // Todo: merge these bundles into BackendFrontendIO 325 val frontend = Flipped(new FrontendToCtrlIO) 326 val frontendSfence = Output(new SfenceBundle) 327 val frontendCsrCtrl = Output(new CustomCSRCtrlIO) 328 val frontendTlbCsr = Output(new TlbCsrBundle) 329 // distributed csr write 330 val frontendCsrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 331 332 val mem = new BackendMemIO 333 334 val perf = Input(new PerfCounterIO) 335 336 val tlb = Output(new TlbCsrBundle) 337 338 val csrCustomCtrl = Output(new CustomCSRCtrlIO) 339} 340