Backend: limit num of enq no more than 2

params: instant backendParam before its usage

WakeupQueue: pdest copy

backend: change vfSchdParams, add PipelineConnect name

Backend,params: use only one vfma temporarily

rv64v: add vidiv module
* support vdiv, vdivu, vrem and vremu

rv64v: add f2v to remove all fs1 duplicate logic (#2613)

* rv64v: add f2v to remove all fs1 duplicate logic

* rv64v: use IntFPToVec module for i2v and f2v

Parameters: VirtualLoadQueueSize should be equal to LoadQueueReplaySize

mdp: enable LFST by default

Issue: split LDU0 from STA0

Backend,MemBlock,params: expand the width of enq of LSQ

Backend,params: modify the config of VFWB to avoid conflict

MemBlock: enable 3ld3st (#2524)

* enable 3ld3st

* assign enqLsq

* fix IssQueSize

* remove performance regression

* MMU: Fix ptwrepeater when 3ld + 3st

* fix minimal config params

*

MemBlock: enable 3ld3st (#2524)

* enable 3ld3st

* assign enqLsq

* fix IssQueSize

* remove performance regression

* MMU: Fix ptwrepeater when 3ld + 3st

* fix minimal config params

* fix minimal config LoadQueueReplaySize

* add 3ld3st switch

* fix bank conflict valid logic

* fix strict memory ambiguous logic

* fix wakeup logic

* disable 3ld3st by default

* modify minimal config params

---------

Co-authored-by: Lyn <[email protected]>
Co-authored-by: good-circle <[email protected]>

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Frontend: fix connections of ftqIdxAhead

Merge remote-tracking branch 'upstream/master' into backendq

Backend: add VTypeBuffer to deduce size of rob

backend: remove renameOut pipeline

Config: set LoadQueueReplaySize and hytlb.

co-authored-by: Haojin Tang <[email protected]>

Debug Module: cherry-pick debug module from nanhu

Rebase Timing Fix of Memblock from fix-timing branch (#2501)

* fix LQ timing

* l1pf: fix pf queue to ldu timing

* disable ecc path for timing analysis

* TODO: remove this

* fix pipeline

Rebase Timing Fix of Memblock from fix-timing branch (#2501)

* fix LQ timing

* l1pf: fix pf queue to ldu timing

* disable ecc path for timing analysis

* TODO: remove this

* fix pipeline

* memblock: add a Reg between inner/outer reset_vec

* missqueue: make mem_grant always ready

* Enable ECC path again

* remove fast replay reorder logic

* l1pf: use chosen of arbiter to improve timing

* remove reorder remain logic

* mq: use ParallelORR instead of orR

* Strengthen the conditions for load to load path for timing

* fix load to load data select for timing

* refactoring lq replay valid logic

* fix replay port

* fix load unit s0 arbitor logic

* add topdown wiring

* fix ldu ecc path

* remove lateKill

* ecc: physically remove ecc in DataArray

* loadpipe: use ParallelORR and ParallelMux for timing

* mainpipe: use ParallelMux and ParallelorR for timing

* fix fast replay is killed at s1

* fix replay cancel logic

* fix mq nack feedback logic

* sms: fix pf queue tlb req logic for timing

* kill load at s1

* fix loadqueuereplay enq logic

* opt raw rollback arbiter logic

* fix ecc_delayed writeback logic

* train all l1 pf and sms at load s3 for better timing

* disable load to load forward

* Revert "kill load at s1"

This reverts commit 56d47582ad4dd9c83373fb2db2a0709075485d4d.

* fix s0 kill logic

* ITLBRepeater: Add one more buffer when PTW resp

* remove trigger

* fix feedback_slow logic

* add latch in uncachebuffer rollback

* remove trigger in port

* fast replay: use dcache ready

* fix replay logic at s1

* uncache: fix uncache writeback

* fix delay kill logic

* fix clean exception loigc at s3

* fix ldu rollback logic

* fix ldu rollback valid logic

---------

Co-authored-by: sfencevma <[email protected]>
Co-authored-by: XiChen <[email protected]>
Co-authored-by: Lyn <[email protected]>
Co-authored-by: good-circle <[email protected]>

show more ...

fix rebase errors

Parameters: set `FpLogicRegs` to 34

Strided loads/stores need at least 2 temporal fp logic registers
to execute i2f, one for base address and another one for stride.

Set VsFlowSize to 128 to avoid vector store deadlock

backend,param: merge vldu and vstu into one exu

Parameters,FuConfig: vector stores should not write reg files