1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import org.chipsalliance.cde.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import huancun._ 23import system.SoCParamsKey 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.dispatch.DispatchParameters 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.issue.{IntScheduler, IssueBlockParams, MemScheduler, SchdBlockParams, SchedulerType, VfScheduler} 30import xiangshan.backend.regfile.{IntPregParams, PregParams, VfPregParams} 31import xiangshan.backend.BackendParams 32import xiangshan.cache.DCacheParameters 33import xiangshan.cache.prefetch._ 34import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 35import xiangshan.frontend.icache.ICacheParameters 36import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 37import xiangshan.frontend._ 38import xiangshan.frontend.icache.ICacheParameters 39 40import freechips.rocketchip.diplomacy.AddressSet 41import system.SoCParamsKey 42import huancun._ 43import huancun.debug._ 44import xiangshan.cache.wpu.WPUParameters 45import coupledL2._ 46import xiangshan.backend.datapath.WakeUpConfig 47import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 48 49import scala.math.min 50 51case object XSTileKey extends Field[Seq[XSCoreParameters]] 52 53case object XSCoreParamsKey extends Field[XSCoreParameters] 54 55case class XSCoreParameters 56( 57 HasPrefetch: Boolean = false, 58 HartId: Int = 0, 59 XLEN: Int = 64, 60 VLEN: Int = 128, 61 ELEN: Int = 64, 62 HasMExtension: Boolean = true, 63 HasCExtension: Boolean = true, 64 HasDiv: Boolean = true, 65 HasICache: Boolean = true, 66 HasDCache: Boolean = true, 67 AddrBits: Int = 64, 68 VAddrBits: Int = 39, 69 HasFPU: Boolean = true, 70 HasVPU: Boolean = true, 71 HasCustomCSRCacheOp: Boolean = true, 72 FetchWidth: Int = 8, 73 AsidLength: Int = 16, 74 EnableBPU: Boolean = true, 75 EnableBPD: Boolean = true, 76 EnableRAS: Boolean = true, 77 EnableLB: Boolean = false, 78 EnableLoop: Boolean = true, 79 EnableSC: Boolean = true, 80 EnbaleTlbDebug: Boolean = false, 81 EnableJal: Boolean = false, 82 EnableFauFTB: Boolean = true, 83 UbtbGHRLength: Int = 4, 84 // HistoryLength: Int = 512, 85 EnableGHistDiff: Boolean = true, 86 EnableCommitGHistDiff: Boolean = true, 87 UbtbSize: Int = 256, 88 FtbSize: Int = 2048, 89 RasSize: Int = 32, 90 RasSpecSize: Int = 64, 91 RasCtrSize: Int = 8, 92 CacheLineSize: Int = 512, 93 FtbWays: Int = 4, 94 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 95 // Sets Hist Tag 96 // Seq(( 2048, 2, 8), 97 // ( 2048, 9, 8), 98 // ( 2048, 13, 8), 99 // ( 2048, 20, 8), 100 // ( 2048, 26, 8), 101 // ( 2048, 44, 8), 102 // ( 2048, 73, 8), 103 // ( 2048, 256, 8)), 104 Seq(( 4096, 8, 8), 105 ( 4096, 13, 8), 106 ( 4096, 32, 8), 107 ( 4096, 119, 8)), 108 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 109 // Sets Hist Tag 110 Seq(( 256, 4, 9), 111 ( 256, 8, 9), 112 ( 512, 13, 9), 113 ( 512, 16, 9), 114 ( 512, 32, 9)), 115 SCNRows: Int = 512, 116 SCNTables: Int = 4, 117 SCCtrBits: Int = 6, 118 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 119 numBr: Int = 2, 120 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 121 ((resp_in: BranchPredictionResp, p: Parameters) => { 122 val ftb = Module(new FTB()(p)) 123 val ubtb =Module(new FauFTB()(p)) 124 // val bim = Module(new BIM()(p)) 125 val tage = Module(new Tage_SC()(p)) 126 val ras = Module(new RAS()(p)) 127 val ittage = Module(new ITTage()(p)) 128 val preds = Seq(ubtb, tage, ftb, ittage, ras) 129 preds.map(_.io := DontCare) 130 131 // ubtb.io.resp_in(0) := resp_in 132 // bim.io.resp_in(0) := ubtb.io.resp 133 // btb.io.resp_in(0) := bim.io.resp 134 // tage.io.resp_in(0) := btb.io.resp 135 // loop.io.resp_in(0) := tage.io.resp 136 ubtb.io.in.bits.resp_in(0) := resp_in 137 tage.io.in.bits.resp_in(0) := ubtb.io.out 138 ftb.io.in.bits.resp_in(0) := tage.io.out 139 ittage.io.in.bits.resp_in(0) := ftb.io.out 140 ras.io.in.bits.resp_in(0) := ittage.io.out 141 142 (preds, ras.io.out) 143 }), 144 IBufSize: Int = 48, 145 DecodeWidth: Int = 6, 146 RenameWidth: Int = 6, 147 CommitWidth: Int = 6, 148 MaxUopSize: Int = 65, 149 EnableRenameSnapshot: Boolean = true, 150 RenameSnapshotNum: Int = 4, 151 FtqSize: Int = 64, 152 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 153 IntLogicRegs: Int = 32, 154 FpLogicRegs: Int = 33, 155 VecLogicRegs: Int = 32 + 1 + 15, // 15: tmp, 1: vconfig 156 VCONFIG_IDX: Int = 32, 157 NRPhyRegs: Int = 192, 158 VirtualLoadQueueSize: Int = 80, 159 LoadQueueRARSize: Int = 80, 160 LoadQueueRAWSize: Int = 64, // NOTE: make sure that LoadQueueRAWSize is power of 2. 161 RollbackGroupSize: Int = 8, 162 LoadQueueReplaySize: Int = 72, 163 LoadUncacheBufferSize: Int = 20, 164 LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks 165 StoreQueueSize: Int = 64, 166 StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 167 StoreQueueForwardWithMask: Boolean = true, 168 VlsQueueSize: Int = 8, 169 RobSize: Int = 256, 170 RabSize: Int = 256, 171 IssueQueueSize: Int = 32, 172 dpParams: DispatchParameters = DispatchParameters( 173 IntDqSize = 16, 174 FpDqSize = 16, 175 LsDqSize = 18, 176 IntDqDeqWidth = 6, 177 FpDqDeqWidth = 6, 178 LsDqDeqWidth = 6, 179 ), 180 intPreg: PregParams = IntPregParams( 181 numEntries = 224, 182 numRead = None, 183 numWrite = None, 184 ), 185 vfPreg: VfPregParams = VfPregParams( 186 numEntries = 192, 187 numRead = Some(14), 188 numWrite = None, 189 ), 190 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 191 LoadPipelineWidth: Int = 3, 192 StorePipelineWidth: Int = 2, 193 VecLoadPipelineWidth: Int = 2, 194 VecStorePipelineWidth: Int = 2, 195 VecMemSrcInWidth: Int = 2, 196 VecMemInstWbWidth: Int = 1, 197 VecMemDispatchWidth: Int = 1, 198 StoreBufferSize: Int = 16, 199 StoreBufferThreshold: Int = 7, 200 EnsbufferWidth: Int = 2, 201 // ============ VLSU ============ 202 UsQueueSize: Int = 8, 203 VlFlowSize: Int = 32, 204 VlUopSize: Int = 32, 205 VsFlowL1Size: Int = 128, 206 VsFlowL2Size: Int = 32, 207 VsUopSize: Int = 32, 208 // ============================== 209 UncacheBufferSize: Int = 4, 210 EnableLoadToLoadForward: Boolean = true, 211 EnableFastForward: Boolean = true, 212 EnableLdVioCheckAfterReset: Boolean = true, 213 EnableSoftPrefetchAfterReset: Boolean = true, 214 EnableCacheErrorAfterReset: Boolean = true, 215 EnableAccurateLoadError: Boolean = true, 216 EnableUncacheWriteOutstanding: Boolean = false, 217 EnableStorePrefetchAtIssue: Boolean = false, 218 EnableStorePrefetchAtCommit: Boolean = false, 219 EnableAtCommitMissTrigger: Boolean = true, 220 EnableStorePrefetchSMS: Boolean = false, 221 EnableStorePrefetchSPB: Boolean = false, 222 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 223 ReSelectLen: Int = 7, // load replay queue replay select counter len 224 iwpuParameters: WPUParameters = WPUParameters( 225 enWPU = false, 226 algoName = "mmru", 227 isICache = true, 228 ), 229 dwpuParameters: WPUParameters = WPUParameters( 230 enWPU = false, 231 algoName = "mmru", 232 enCfPred = false, 233 isICache = false, 234 ), 235 itlbParameters: TLBParameters = TLBParameters( 236 name = "itlb", 237 fetchi = true, 238 useDmode = false, 239 NWays = 48, 240 ), 241 itlbPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 242 ipmpPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 243 ldtlbParameters: TLBParameters = TLBParameters( 244 name = "ldtlb", 245 NWays = 48, 246 outReplace = false, 247 partialStaticPMP = true, 248 outsideRecvFlush = true, 249 saveLevel = true 250 ), 251 sttlbParameters: TLBParameters = TLBParameters( 252 name = "sttlb", 253 NWays = 48, 254 outReplace = false, 255 partialStaticPMP = true, 256 outsideRecvFlush = true, 257 saveLevel = true 258 ), 259 hytlbParameters: TLBParameters = TLBParameters( 260 name = "hytlb", 261 NWays = 4, 262 partialStaticPMP = true, 263 outsideRecvFlush = true, 264 outReplace = false 265 ), 266 pftlbParameters: TLBParameters = TLBParameters( 267 name = "pftlb", 268 NWays = 48, 269 outReplace = false, 270 partialStaticPMP = true, 271 outsideRecvFlush = true, 272 saveLevel = true 273 ), 274 refillBothTlb: Boolean = false, 275 btlbParameters: TLBParameters = TLBParameters( 276 name = "btlb", 277 NWays = 48, 278 ), 279 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 280 NumPerfCounters: Int = 16, 281 icacheParameters: ICacheParameters = ICacheParameters( 282 tagECC = Some("parity"), 283 dataECC = Some("parity"), 284 replacer = Some("setplru"), 285 nMissEntries = 2, 286 nProbeEntries = 2, 287 nPrefetchEntries = 12, 288 nPrefBufferEntries = 32, 289 ), 290 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 291 tagECC = Some("secded"), 292 dataECC = Some("secded"), 293 replacer = Some("setplru"), 294 nMissEntries = 16, 295 nProbeEntries = 8, 296 nReleaseEntries = 18, 297 nMaxPrefetchEntry = 6, 298 )), 299 L2CacheParamsOpt: Option[L2Param] = Some(L2Param( 300 name = "l2", 301 ways = 8, 302 sets = 1024, // default 512KB L2 303 prefetch = Some(coupledL2.prefetch.PrefetchReceiverParams()) 304 )), 305 L2NBanks: Int = 1, 306 usePTWRepeater: Boolean = false, 307 softTLB: Boolean = false, // dpi-c l1tlb debug only 308 softPTW: Boolean = false, // dpi-c l2tlb debug only 309 softPTWDelay: Int = 1 310){ 311 def vlWidth = log2Up(VLEN) + 1 312 313 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 314 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 315 316 val intSchdParams = { 317 implicit val schdType: SchedulerType = IntScheduler() 318 SchdBlockParams(Seq( 319 IssueBlockParams(Seq( 320 ExeUnitParams("ALU0", Seq(AluCfg), Seq(IntWB(port = 0, 0)), Seq(Seq(IntRD(0, 0)), Seq(IntRD(1, 0)))), 321 ExeUnitParams("ALU1", Seq(AluCfg), Seq(IntWB(port = 1, 0)), Seq(Seq(IntRD(2, 0)), Seq(IntRD(3, 0)))), 322 ), numEntries = IssueQueueSize, numEnq = 2), 323 IssueBlockParams(Seq( 324 ExeUnitParams("MUL0", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 2, 0)), Seq(Seq(IntRD(4, 0)), Seq(IntRD(5, 0)))), 325 ExeUnitParams("MUL1", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 3, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0)))), 326 ), numEntries = IssueQueueSize, numEnq = 2), 327 IssueBlockParams(Seq( 328 ExeUnitParams("BJU0", Seq(BrhCfg), Seq(), Seq(Seq(IntRD(8, 0)), Seq(IntRD(9, 0)))), 329 ExeUnitParams("BJU1", Seq(BrhCfg), Seq(), Seq(Seq(IntRD(10, 0)), Seq(IntRD(12, 1)))), 330 ), numEntries = IssueQueueSize, numEnq = 2), 331 IssueBlockParams(Seq( 332 ExeUnitParams("BJU2", Seq(BrhCfg), Seq(), Seq(Seq(IntRD(11, 0)), Seq(IntRD(7, 1)))), 333 ), numEntries = IssueQueueSize / 2, numEnq = 1), 334 IssueBlockParams(Seq( 335 ExeUnitParams("IMISC0", Seq(VSetRiWiCfg, I2fCfg, I2vCfg, VSetRiWvfCfg, JmpCfg, CsrCfg, FenceCfg), Seq(IntWB(port = 4, 1), VfWB(2, 0)), Seq(Seq(IntRD(5, 1)), Seq(IntRD(3, 1)))), 336 ExeUnitParams("IDIV0", Seq(DivCfg), Seq(IntWB(port = 7, 1)), Seq(Seq(IntRD(1, Int.MaxValue)), Seq(IntRD(9, Int.MaxValue)))), 337 ), numEntries = IssueQueueSize, numEnq = 2), 338 ), 339 numPregs = intPreg.numEntries, 340 numDeqOutside = 0, 341 schdType = schdType, 342 rfDataWidth = intPreg.dataCfg.dataWidth, 343 numUopIn = dpParams.IntDqDeqWidth, 344 ) 345 } 346 val vfSchdParams = { 347 implicit val schdType: SchedulerType = VfScheduler() 348 SchdBlockParams(Seq( 349 IssueBlockParams(Seq( 350 ExeUnitParams("VFEX0", Seq(VfaluCfg, VfmaCfg, VialuCfg, VppuCfg, F2fCfg, F2iCfg, VSetRvfWvfCfg), Seq(VfWB(port = 0, 0), IntWB(port = 4, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))), 351 ExeUnitParams("VFEX1", Seq(VfaluCfg, VfmaCfg, VimacCfg, VipuCfg, VfcvtCfg), Seq(VfWB(port = 1, 0), IntWB(port = 8, 0)), Seq(Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(VfRD(9, 0)), Seq(VfRD(10, 0)), Seq(VfRD(11, 0)))), 352 ), numEntries = IssueQueueSize, numEnq = 2), 353 IssueBlockParams(Seq( 354 ExeUnitParams("VFEX2", Seq(VfdivCfg), Seq(VfWB(port = 5, 0)), Seq(Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(VfRD(9, 0)), Seq(VfRD(10, 0)), Seq(VfRD(11, 0)))), 355 ), numEntries = IssueQueueSize, numEnq = 2), 356 ), 357 numPregs = vfPreg.numEntries, 358 numDeqOutside = 0, 359 schdType = schdType, 360 rfDataWidth = vfPreg.dataCfg.dataWidth, 361 numUopIn = dpParams.FpDqDeqWidth, 362 ) 363 } 364 365 val memSchdParams = { 366 implicit val schdType: SchedulerType = MemScheduler() 367 val rfDataWidth = 64 368 369 SchdBlockParams(Seq( 370 IssueBlockParams(Seq( 371 ExeUnitParams("LDU0", Seq(LduCfg), Seq(IntWB(6, 0), VfWB(3, 0)), Seq(Seq(IntRD(12, 0)))), 372 ExeUnitParams("STA0", Seq(StaCfg), Seq(), Seq(Seq(IntRD(3, 1)))), 373 ), numEntries = IssueQueueSize, numEnq = 2), 374 IssueBlockParams(Seq( 375 ExeUnitParams("HYU0", Seq(HyldaCfg, HystaCfg, MouCfg), Seq(IntWB(5, 0), VfWB(5, 0)), Seq(Seq(IntRD(6, 0)))), 376 ExeUnitParams("HYU1", Seq(FakeHystaCfg), Seq(), Seq()), // fake unit, used to create a new writeback port 377 ), numEntries = IssueQueueSize, numEnq = 2), 378 IssueBlockParams(Seq( 379 ExeUnitParams("LDU1", Seq(LduCfg), Seq(IntWB(7, 0), VfWB(4, 0)), Seq(Seq(IntRD(13, 0)))), 380 ), numEntries = IssueQueueSize, numEnq = 2), 381 IssueBlockParams(Seq( 382 ExeUnitParams("VLSU0", Seq(VlduCfg, VstuCfg), Seq(VfWB(3, 1)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))), 383 ), numEntries = IssueQueueSize, numEnq = 2), 384 IssueBlockParams(Seq( 385 ExeUnitParams("STD0", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(13, 1), VfRD(6, 0)))), 386 ExeUnitParams("STD1", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(5, 1), VfRD(10, Int.MaxValue)))), 387 ), numEntries = IssueQueueSize, numEnq = 2), 388 IssueBlockParams(Seq( 389 ExeUnitParams("VLDU0", Seq(VlduCfg, VstuCfg), Seq(VfWB(5, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))), 390 ), numEntries = IssueQueueSize, numEnq = 2), 391 ), 392 numPregs = intPreg.numEntries max vfPreg.numEntries, 393 numDeqOutside = 0, 394 schdType = schdType, 395 rfDataWidth = rfDataWidth, 396 numUopIn = dpParams.LsDqDeqWidth, 397 ) 398 } 399 400 def PregIdxWidthMax = intPreg.addrWidth max vfPreg.addrWidth 401 402 def iqWakeUpParams = { 403 Seq( 404 WakeUpConfig( 405 Seq("ALU0", "ALU1", "MUL0", "MUL1", "BJU0", "LDU0", "LDU1", "HYU0") -> 406 Seq("ALU0", "ALU1", "MUL0", "MUL1", "BJU0", "BJU1", "BJU2", "LDU0", "LDU1", "STA0", "STD0", "STD1", "HYU0") 407 ), 408 WakeUpConfig(Seq("IMISC0") -> Seq("VFEX0")), 409 ).flatten 410 } 411 412 def backendParams: BackendParams = backend.BackendParams( 413 Map( 414 IntScheduler() -> intSchdParams, 415 VfScheduler() -> vfSchdParams, 416 MemScheduler() -> memSchdParams, 417 ), 418 Seq( 419 intPreg, 420 vfPreg, 421 ), 422 iqWakeUpParams, 423 ) 424} 425 426case object DebugOptionsKey extends Field[DebugOptions] 427 428case class DebugOptions 429( 430 FPGAPlatform: Boolean = false, 431 EnableDifftest: Boolean = false, 432 AlwaysBasicDiff: Boolean = true, 433 EnableDebug: Boolean = false, 434 EnablePerfDebug: Boolean = true, 435 UseDRAMSim: Boolean = false, 436 EnableConstantin: Boolean = false, 437 EnableChiselDB: Boolean = false, 438 AlwaysBasicDB: Boolean = true, 439 EnableTopDown: Boolean = false, 440 EnableRollingDB: Boolean = false 441) 442 443trait HasXSParameter { 444 445 implicit val p: Parameters 446 447 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 448 449 val coreParams = p(XSCoreParamsKey) 450 val env = p(DebugOptionsKey) 451 452 val XLEN = coreParams.XLEN 453 val VLEN = coreParams.VLEN 454 val ELEN = coreParams.ELEN 455 val minFLen = 32 456 val fLen = 64 457 def xLen = XLEN 458 459 val HasMExtension = coreParams.HasMExtension 460 val HasCExtension = coreParams.HasCExtension 461 val HasDiv = coreParams.HasDiv 462 val HasIcache = coreParams.HasICache 463 val HasDcache = coreParams.HasDCache 464 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 465 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 466 val AsidLength = coreParams.AsidLength 467 val ReSelectLen = coreParams.ReSelectLen 468 val AddrBytes = AddrBits / 8 // unused 469 val DataBits = XLEN 470 val DataBytes = DataBits / 8 471 val VDataBytes = VLEN / 8 472 val HasFPU = coreParams.HasFPU 473 val HasVPU = coreParams.HasVPU 474 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 475 val FetchWidth = coreParams.FetchWidth 476 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 477 val EnableBPU = coreParams.EnableBPU 478 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 479 val EnableRAS = coreParams.EnableRAS 480 val EnableLB = coreParams.EnableLB 481 val EnableLoop = coreParams.EnableLoop 482 val EnableSC = coreParams.EnableSC 483 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 484 val HistoryLength = coreParams.HistoryLength 485 val EnableGHistDiff = coreParams.EnableGHistDiff 486 val EnableCommitGHistDiff = coreParams.EnableCommitGHistDiff 487 val UbtbGHRLength = coreParams.UbtbGHRLength 488 val UbtbSize = coreParams.UbtbSize 489 val EnableFauFTB = coreParams.EnableFauFTB 490 val FtbSize = coreParams.FtbSize 491 val FtbWays = coreParams.FtbWays 492 val RasSize = coreParams.RasSize 493 val RasSpecSize = coreParams.RasSpecSize 494 val RasCtrSize = coreParams.RasCtrSize 495 496 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 497 coreParams.branchPredictor(resp_in, p) 498 } 499 val numBr = coreParams.numBr 500 val TageTableInfos = coreParams.TageTableInfos 501 val TageBanks = coreParams.numBr 502 val SCNRows = coreParams.SCNRows 503 val SCCtrBits = coreParams.SCCtrBits 504 val SCHistLens = coreParams.SCHistLens 505 val SCNTables = coreParams.SCNTables 506 507 val SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 508 case ((n, cb), h) => (n, cb, h) 509 } 510 val ITTageTableInfos = coreParams.ITTageTableInfos 511 type FoldedHistoryInfo = Tuple2[Int, Int] 512 val foldedGHistInfos = 513 (TageTableInfos.map{ case (nRows, h, t) => 514 if (h > 0) 515 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 516 else 517 Set[FoldedHistoryInfo]() 518 }.reduce(_++_).toSet ++ 519 SCTableInfos.map{ case (nRows, _, h) => 520 if (h > 0) 521 Set((h, min(log2Ceil(nRows/TageBanks), h))) 522 else 523 Set[FoldedHistoryInfo]() 524 }.reduce(_++_).toSet ++ 525 ITTageTableInfos.map{ case (nRows, h, t) => 526 if (h > 0) 527 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 528 else 529 Set[FoldedHistoryInfo]() 530 }.reduce(_++_) ++ 531 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 532 ).toList 533 534 535 536 val CacheLineSize = coreParams.CacheLineSize 537 val CacheLineHalfWord = CacheLineSize / 16 538 val ExtHistoryLength = HistoryLength + 64 539 val IBufSize = coreParams.IBufSize 540 val DecodeWidth = coreParams.DecodeWidth 541 val RenameWidth = coreParams.RenameWidth 542 val CommitWidth = coreParams.CommitWidth 543 val MaxUopSize = coreParams.MaxUopSize 544 val EnableRenameSnapshot = coreParams.EnableRenameSnapshot 545 val RenameSnapshotNum = coreParams.RenameSnapshotNum 546 val FtqSize = coreParams.FtqSize 547 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 548 val IntLogicRegs = coreParams.IntLogicRegs 549 val FpLogicRegs = coreParams.FpLogicRegs 550 val VecLogicRegs = coreParams.VecLogicRegs 551 val VCONFIG_IDX = coreParams.VCONFIG_IDX 552 val IntPhyRegs = coreParams.intPreg.numEntries 553 val VfPhyRegs = coreParams.vfPreg.numEntries 554 val MaxPhyPregs = IntPhyRegs max VfPhyRegs 555 val PhyRegIdxWidth = log2Up(IntPhyRegs) max log2Up(VfPhyRegs) 556 val RobSize = coreParams.RobSize 557 val RabSize = coreParams.RabSize 558 val IntRefCounterWidth = log2Ceil(RobSize) 559 val LSQEnqWidth = coreParams.dpParams.LsDqDeqWidth 560 val VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize 561 val LoadQueueRARSize = coreParams.LoadQueueRARSize 562 val LoadQueueRAWSize = coreParams.LoadQueueRAWSize 563 val RollbackGroupSize = coreParams.RollbackGroupSize 564 val LoadQueueReplaySize = coreParams.LoadQueueReplaySize 565 val LoadUncacheBufferSize = coreParams.LoadUncacheBufferSize 566 val LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 567 val StoreQueueSize = coreParams.StoreQueueSize 568 val StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 569 val StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask 570 val VlsQueueSize = coreParams.VlsQueueSize 571 val dpParams = coreParams.dpParams 572 573 def backendParams: BackendParams = coreParams.backendParams 574 def MemIQSizeMax = backendParams.memSchdParams.get.issueBlockParams.map(_.numEntries).max 575 def IQSizeMax = backendParams.allSchdParams.map(_.issueBlockParams.map(_.numEntries).max).max 576 577 val NumRedirect = backendParams.numRedirect 578 val BackendRedirectNum = NumRedirect + 2 //2: ldReplay + Exception 579 val LoadPipelineWidth = coreParams.LoadPipelineWidth 580 val StorePipelineWidth = coreParams.StorePipelineWidth 581 val VecLoadPipelineWidth = coreParams.VecLoadPipelineWidth 582 val VecStorePipelineWidth = coreParams.VecStorePipelineWidth 583 val VecMemSrcInWidth = coreParams.VecMemSrcInWidth 584 val VecMemInstWbWidth = coreParams.VecMemInstWbWidth 585 val VecMemDispatchWidth = coreParams.VecMemDispatchWidth 586 val StoreBufferSize = coreParams.StoreBufferSize 587 val StoreBufferThreshold = coreParams.StoreBufferThreshold 588 val EnsbufferWidth = coreParams.EnsbufferWidth 589 val UsQueueSize = coreParams.UsQueueSize 590 val VlFlowSize = coreParams.VlFlowSize 591 val VlUopSize = coreParams.VlUopSize 592 val VsFlowL1Size = coreParams.VsFlowL1Size 593 val VsFlowL2Size = coreParams.VsFlowL2Size 594 val VsUopSize = coreParams.VsUopSize 595 val UncacheBufferSize = coreParams.UncacheBufferSize 596 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 597 val EnableFastForward = coreParams.EnableFastForward 598 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 599 val EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 600 val EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 601 val EnableAccurateLoadError = coreParams.EnableAccurateLoadError 602 val EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 603 val EnableStorePrefetchAtIssue = coreParams.EnableStorePrefetchAtIssue 604 val EnableStorePrefetchAtCommit = coreParams.EnableStorePrefetchAtCommit 605 val EnableAtCommitMissTrigger = coreParams.EnableAtCommitMissTrigger 606 val EnableStorePrefetchSMS = coreParams.EnableStorePrefetchSMS 607 val EnableStorePrefetchSPB = coreParams.EnableStorePrefetchSPB 608 val asidLen = coreParams.MMUAsidLen 609 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 610 val refillBothTlb = coreParams.refillBothTlb 611 val iwpuParam = coreParams.iwpuParameters 612 val dwpuParam = coreParams.dwpuParameters 613 val itlbParams = coreParams.itlbParameters 614 val ldtlbParams = coreParams.ldtlbParameters 615 val sttlbParams = coreParams.sttlbParameters 616 val hytlbParams = coreParams.hytlbParameters 617 val pftlbParams = coreParams.pftlbParameters 618 val btlbParams = coreParams.btlbParameters 619 val l2tlbParams = coreParams.l2tlbParameters 620 val NumPerfCounters = coreParams.NumPerfCounters 621 622 val instBytes = if (HasCExtension) 2 else 4 623 val instOffsetBits = log2Ceil(instBytes) 624 625 val icacheParameters = coreParams.icacheParameters 626 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 627 628 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 629 // for constrained LR/SC loop 630 val LRSCCycles = 64 631 // for lr storm 632 val LRSCBackOff = 8 633 634 // cache hierarchy configurations 635 val l1BusDataWidth = 256 636 637 // load violation predict 638 val ResetTimeMax2Pow = 20 //1078576 639 val ResetTimeMin2Pow = 10 //1024 640 // wait table parameters 641 val WaitTableSize = 1024 642 val MemPredPCWidth = log2Up(WaitTableSize) 643 val LWTUse2BitCounter = true 644 // store set parameters 645 val SSITSize = WaitTableSize 646 val LFSTSize = 32 647 val SSIDWidth = log2Up(LFSTSize) 648 val LFSTWidth = 4 649 val StoreSetEnable = true // LWT will be disabled if SS is enabled 650 val LFSTEnable = false 651 652 val PCntIncrStep: Int = 6 653 val numPCntHc: Int = 25 654 val numPCntPtw: Int = 19 655 656 val numCSRPCntFrontend = 8 657 val numCSRPCntCtrl = 8 658 val numCSRPCntLsu = 8 659 val numCSRPCntHc = 5 660} 661