1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import org.chipsalliance.cde.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import huancun._ 23import system.SoCParamsKey 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.dispatch.DispatchParameters 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.issue.{IntScheduler, IssueBlockParams, MemScheduler, SchdBlockParams, SchedulerType, VfScheduler} 30import xiangshan.backend.regfile.{IntPregParams, PregParams, VfPregParams} 31import xiangshan.backend.BackendParams 32import xiangshan.cache.DCacheParameters 33import xiangshan.cache.prefetch._ 34import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 35import xiangshan.frontend.icache.ICacheParameters 36import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 37import xiangshan.frontend._ 38import xiangshan.frontend.icache.ICacheParameters 39 40import freechips.rocketchip.diplomacy.AddressSet 41import system.SoCParamsKey 42import huancun._ 43import huancun.debug._ 44import xiangshan.cache.wpu.WPUParameters 45import coupledL2._ 46import xiangshan.backend.datapath.WakeUpConfig 47import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 48 49import scala.math.min 50 51case object XSTileKey extends Field[Seq[XSCoreParameters]] 52 53case object XSCoreParamsKey extends Field[XSCoreParameters] 54 55case class XSCoreParameters 56( 57 HasPrefetch: Boolean = false, 58 HartId: Int = 0, 59 XLEN: Int = 64, 60 VLEN: Int = 128, 61 ELEN: Int = 64, 62 HasMExtension: Boolean = true, 63 HasCExtension: Boolean = true, 64 HasDiv: Boolean = true, 65 HasICache: Boolean = true, 66 HasDCache: Boolean = true, 67 AddrBits: Int = 64, 68 VAddrBits: Int = 39, 69 HasFPU: Boolean = true, 70 HasVPU: Boolean = true, 71 HasCustomCSRCacheOp: Boolean = true, 72 FetchWidth: Int = 8, 73 AsidLength: Int = 16, 74 EnableBPU: Boolean = true, 75 EnableBPD: Boolean = true, 76 EnableRAS: Boolean = true, 77 EnableLB: Boolean = false, 78 EnableLoop: Boolean = true, 79 EnableSC: Boolean = true, 80 EnbaleTlbDebug: Boolean = false, 81 EnableJal: Boolean = false, 82 EnableFauFTB: Boolean = true, 83 UbtbGHRLength: Int = 4, 84 // HistoryLength: Int = 512, 85 EnableGHistDiff: Boolean = true, 86 EnableCommitGHistDiff: Boolean = true, 87 UbtbSize: Int = 256, 88 FtbSize: Int = 2048, 89 RasSize: Int = 16, 90 RasSpecSize: Int = 32, 91 RasCtrSize: Int = 3, 92 CacheLineSize: Int = 512, 93 FtbWays: Int = 4, 94 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 95 // Sets Hist Tag 96 // Seq(( 2048, 2, 8), 97 // ( 2048, 9, 8), 98 // ( 2048, 13, 8), 99 // ( 2048, 20, 8), 100 // ( 2048, 26, 8), 101 // ( 2048, 44, 8), 102 // ( 2048, 73, 8), 103 // ( 2048, 256, 8)), 104 Seq(( 4096, 8, 8), 105 ( 4096, 13, 8), 106 ( 4096, 32, 8), 107 ( 4096, 119, 8)), 108 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 109 // Sets Hist Tag 110 Seq(( 256, 4, 9), 111 ( 256, 8, 9), 112 ( 512, 13, 9), 113 ( 512, 16, 9), 114 ( 512, 32, 9)), 115 SCNRows: Int = 512, 116 SCNTables: Int = 4, 117 SCCtrBits: Int = 6, 118 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 119 numBr: Int = 2, 120 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 121 ((resp_in: BranchPredictionResp, p: Parameters) => { 122 val ftb = Module(new FTB()(p)) 123 val ubtb =Module(new FauFTB()(p)) 124 // val bim = Module(new BIM()(p)) 125 val tage = Module(new Tage_SC()(p)) 126 val ras = Module(new RAS()(p)) 127 val ittage = Module(new ITTage()(p)) 128 val preds = Seq(ubtb, tage, ftb, ittage, ras) 129 preds.map(_.io := DontCare) 130 131 // ubtb.io.resp_in(0) := resp_in 132 // bim.io.resp_in(0) := ubtb.io.resp 133 // btb.io.resp_in(0) := bim.io.resp 134 // tage.io.resp_in(0) := btb.io.resp 135 // loop.io.resp_in(0) := tage.io.resp 136 ubtb.io.in.bits.resp_in(0) := resp_in 137 tage.io.in.bits.resp_in(0) := ubtb.io.out 138 ftb.io.in.bits.resp_in(0) := tage.io.out 139 ittage.io.in.bits.resp_in(0) := ftb.io.out 140 ras.io.in.bits.resp_in(0) := ittage.io.out 141 142 (preds, ras.io.out) 143 }), 144 ICacheECCForceError: Boolean = false, 145 IBufSize: Int = 48, 146 IBufNBank: Int = 6, // IBuffer bank amount, should divide IBufSize 147 DecodeWidth: Int = 6, 148 RenameWidth: Int = 6, 149 CommitWidth: Int = 6, 150 MaxUopSize: Int = 65, 151 EnableRenameSnapshot: Boolean = true, 152 RenameSnapshotNum: Int = 4, 153 FtqSize: Int = 64, 154 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 155 IntLogicRegs: Int = 32, 156 FpLogicRegs: Int = 32 + 1 + 1, // 1: I2F, 1: stride 157 VecLogicRegs: Int = 32 + 1 + 15, // 15: tmp, 1: vconfig 158 VCONFIG_IDX: Int = 32, 159 NRPhyRegs: Int = 192, 160 VirtualLoadQueueSize: Int = 72, 161 LoadQueueRARSize: Int = 72, 162 LoadQueueRAWSize: Int = 64, // NOTE: make sure that LoadQueueRAWSize is power of 2. 163 RollbackGroupSize: Int = 8, 164 LoadQueueReplaySize: Int = 72, 165 LoadUncacheBufferSize: Int = 20, 166 LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks 167 StoreQueueSize: Int = 64, 168 StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 169 StoreQueueForwardWithMask: Boolean = true, 170 VlsQueueSize: Int = 8, 171 RobSize: Int = 160, 172 RabSize: Int = 256, 173 VTypeBufferSize: Int = 64, // used to reorder vtype 174 IssueQueueSize: Int = 24, 175 dpParams: DispatchParameters = DispatchParameters( 176 IntDqSize = 16, 177 FpDqSize = 16, 178 LsDqSize = 18, 179 IntDqDeqWidth = 6, 180 FpDqDeqWidth = 6, 181 LsDqDeqWidth = 6, 182 ), 183 intPreg: PregParams = IntPregParams( 184 numEntries = 224, 185 numRead = None, 186 numWrite = None, 187 ), 188 vfPreg: VfPregParams = VfPregParams( 189 numEntries = 192, 190 numRead = Some(14), 191 numWrite = None, 192 ), 193 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 194 LoadPipelineWidth: Int = 3, 195 StorePipelineWidth: Int = 2, 196 VecLoadPipelineWidth: Int = 2, 197 VecStorePipelineWidth: Int = 2, 198 VecMemSrcInWidth: Int = 2, 199 VecMemInstWbWidth: Int = 1, 200 VecMemDispatchWidth: Int = 1, 201 StoreBufferSize: Int = 16, 202 StoreBufferThreshold: Int = 7, 203 EnsbufferWidth: Int = 2, 204 // ============ VLSU ============ 205 UsQueueSize: Int = 8, 206 VlFlowSize: Int = 32, 207 VlUopSize: Int = 32, 208 VsFlowL1Size: Int = 128, 209 VsFlowL2Size: Int = 32, 210 VsUopSize: Int = 32, 211 // ============================== 212 UncacheBufferSize: Int = 4, 213 EnableLoadToLoadForward: Boolean = false, 214 EnableFastForward: Boolean = true, 215 EnableLdVioCheckAfterReset: Boolean = true, 216 EnableSoftPrefetchAfterReset: Boolean = true, 217 EnableCacheErrorAfterReset: Boolean = true, 218 EnableAccurateLoadError: Boolean = true, 219 EnableUncacheWriteOutstanding: Boolean = false, 220 EnableStorePrefetchAtIssue: Boolean = false, 221 EnableStorePrefetchAtCommit: Boolean = false, 222 EnableAtCommitMissTrigger: Boolean = true, 223 EnableStorePrefetchSMS: Boolean = false, 224 EnableStorePrefetchSPB: Boolean = false, 225 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 226 ReSelectLen: Int = 7, // load replay queue replay select counter len 227 iwpuParameters: WPUParameters = WPUParameters( 228 enWPU = false, 229 algoName = "mmru", 230 isICache = true, 231 ), 232 dwpuParameters: WPUParameters = WPUParameters( 233 enWPU = false, 234 algoName = "mmru", 235 enCfPred = false, 236 isICache = false, 237 ), 238 itlbParameters: TLBParameters = TLBParameters( 239 name = "itlb", 240 fetchi = true, 241 useDmode = false, 242 NWays = 48, 243 ), 244 itlbPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 245 ipmpPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 246 ldtlbParameters: TLBParameters = TLBParameters( 247 name = "ldtlb", 248 NWays = 48, 249 outReplace = false, 250 partialStaticPMP = true, 251 outsideRecvFlush = true, 252 saveLevel = true 253 ), 254 sttlbParameters: TLBParameters = TLBParameters( 255 name = "sttlb", 256 NWays = 48, 257 outReplace = false, 258 partialStaticPMP = true, 259 outsideRecvFlush = true, 260 saveLevel = true 261 ), 262 hytlbParameters: TLBParameters = TLBParameters( 263 name = "hytlb", 264 NWays = 48, 265 outReplace = false, 266 partialStaticPMP = true, 267 outsideRecvFlush = true, 268 saveLevel = true 269 ), 270 pftlbParameters: TLBParameters = TLBParameters( 271 name = "pftlb", 272 NWays = 48, 273 outReplace = false, 274 partialStaticPMP = true, 275 outsideRecvFlush = true, 276 saveLevel = true 277 ), 278 refillBothTlb: Boolean = false, 279 btlbParameters: TLBParameters = TLBParameters( 280 name = "btlb", 281 NWays = 48, 282 ), 283 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 284 NumPerfCounters: Int = 16, 285 icacheParameters: ICacheParameters = ICacheParameters( 286 tagECC = Some("parity"), 287 dataECC = Some("parity"), 288 replacer = Some("setplru"), 289 nMissEntries = 2, 290 nProbeEntries = 2, 291 nPrefetchEntries = 12, 292 nPrefBufferEntries = 32, 293 ), 294 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 295 tagECC = Some("secded"), 296 dataECC = Some("secded"), 297 replacer = Some("setplru"), 298 nMissEntries = 16, 299 nProbeEntries = 8, 300 nReleaseEntries = 18, 301 nMaxPrefetchEntry = 6, 302 )), 303 L2CacheParamsOpt: Option[L2Param] = Some(L2Param( 304 name = "l2", 305 ways = 8, 306 sets = 1024, // default 512KB L2 307 prefetch = Some(coupledL2.prefetch.PrefetchReceiverParams()) 308 )), 309 L2NBanks: Int = 1, 310 usePTWRepeater: Boolean = false, 311 softTLB: Boolean = false, // dpi-c l1tlb debug only 312 softPTW: Boolean = false, // dpi-c l2tlb debug only 313 softPTWDelay: Int = 1 314){ 315 def vlWidth = log2Up(VLEN) + 1 316 317 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 318 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 319 320 val intSchdParams = { 321 implicit val schdType: SchedulerType = IntScheduler() 322 SchdBlockParams(Seq( 323 IssueBlockParams(Seq( 324 ExeUnitParams("ALU0", Seq(AluCfg), Seq(IntWB(port = 0, 0)), Seq(Seq(IntRD(0, 0)), Seq(IntRD(1, 0))), true, 1), 325 ExeUnitParams("ALU1", Seq(AluCfg), Seq(IntWB(port = 1, 0)), Seq(Seq(IntRD(2, 0)), Seq(IntRD(3, 0))), true, 1), 326 ), numEntries = IssueQueueSize, numEnq = 2), 327 IssueBlockParams(Seq( 328 ExeUnitParams("MUL0", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 2, 0)), Seq(Seq(IntRD(4, 0)), Seq(IntRD(5, 0))), true, 1), 329 ExeUnitParams("MUL1", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 3, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0))), true, 1), 330 ), numEntries = IssueQueueSize, numEnq = 2), 331 IssueBlockParams(Seq( 332 ExeUnitParams("BJU0", Seq(BrhCfg), Seq(), Seq(Seq(IntRD(8, 0)), Seq(IntRD(9, 0)))), 333 ExeUnitParams("BJU1", Seq(BrhCfg), Seq(), Seq(Seq(IntRD(10, 0)), Seq(IntRD(12, 1)))), 334 ), numEntries = IssueQueueSize, numEnq = 2), 335 IssueBlockParams(Seq( 336 ExeUnitParams("BJU2", Seq(BrhCfg), Seq(), Seq(Seq(IntRD(11, 0)), Seq(IntRD(7, 1)))), 337 ), numEntries = IssueQueueSize / 2, numEnq = 1), 338 IssueBlockParams(Seq( 339 ExeUnitParams("IMISC0", Seq(VSetRiWiCfg, I2fCfg, I2vCfg, VSetRiWvfCfg, JmpCfg, CsrCfg, FenceCfg), Seq(IntWB(port = 4, 1), VfWB(4, 1)), Seq(Seq(IntRD(5, 1)), Seq(IntRD(3, 1)))), 340 ExeUnitParams("IDIV0", Seq(DivCfg), Seq(IntWB(port = 7, 1)), Seq(Seq(IntRD(1, Int.MaxValue)), Seq(IntRD(9, Int.MaxValue)))), 341 ), numEntries = IssueQueueSize, numEnq = 2), 342 ), 343 numPregs = intPreg.numEntries, 344 numDeqOutside = 0, 345 schdType = schdType, 346 rfDataWidth = intPreg.dataCfg.dataWidth, 347 numUopIn = dpParams.IntDqDeqWidth, 348 ) 349 } 350 val vfSchdParams = { 351 implicit val schdType: SchedulerType = VfScheduler() 352 SchdBlockParams(Seq( 353 IssueBlockParams(Seq( 354 ExeUnitParams("VFEX0", Seq(VfaluCfg, VfmaCfg, VialuCfg, VppuCfg, F2fCfg, F2iCfg, VSetRvfWvfCfg), Seq(VfWB(port = 0, 0), IntWB(port = 0, 1)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))), 355 ), numEntries = IssueQueueSize, numEnq = 2), 356 IssueBlockParams(Seq( 357 ExeUnitParams("VFEX1", Seq(VfaluCfg, VfmaCfg, VimacCfg, VipuCfg, F2vCfg, VfcvtCfg), Seq(VfWB(port = 1, 0), IntWB(port = 8, 0)), Seq(Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(VfRD(9, 0)), Seq(VfRD(10, 0)), Seq(VfRD(11, 0)))), 358 ExeUnitParams("VFEX2", Seq(VfdivCfg, VidivCfg), Seq(VfWB(port = 2, 0)), Seq(Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(VfRD(9, 0)), Seq(VfRD(10, 0)), Seq(VfRD(11, 0)))), 359 ), numEntries = IssueQueueSize, numEnq = 2), 360 ), 361 numPregs = vfPreg.numEntries, 362 numDeqOutside = 0, 363 schdType = schdType, 364 rfDataWidth = vfPreg.dataCfg.dataWidth, 365 numUopIn = dpParams.FpDqDeqWidth, 366 ) 367 } 368 369 val memSchdParams = { 370 implicit val schdType: SchedulerType = MemScheduler() 371 val rfDataWidth = 64 372 373 SchdBlockParams(Seq( 374 IssueBlockParams(Seq( 375 ExeUnitParams("STA0", Seq(StaCfg), Seq(), Seq(Seq(IntRD(3, 1)))), 376 ), numEntries = IssueQueueSize, numEnq = 2), 377 IssueBlockParams(Seq( 378 ExeUnitParams("HYU0", Seq(HyldaCfg, HystaCfg, MouCfg), Seq(IntWB(5, 0), VfWB(5, 0)), Seq(Seq(IntRD(6, 0)))), 379 ExeUnitParams("HYU1", Seq(FakeHystaCfg), Seq(), Seq()), // fake unit, used to create a new writeback port 380 ), numEntries = IssueQueueSize, numEnq = 2), 381 IssueBlockParams(Seq( 382 ExeUnitParams("LDU0", Seq(LduCfg), Seq(IntWB(6, 0), VfWB(6, 0)), Seq(Seq(IntRD(12, 0))), true, 1), 383 ), numEntries = IssueQueueSize, numEnq = 2), 384 IssueBlockParams(Seq( 385 ExeUnitParams("LDU1", Seq(LduCfg), Seq(IntWB(7, 0), VfWB(7, 0)), Seq(Seq(IntRD(13, 0))), true, 1), 386 ), numEntries = IssueQueueSize, numEnq = 2), 387 IssueBlockParams(Seq( 388 ExeUnitParams("VLSU0", Seq(VlduCfg, VstuCfg), Seq(VfWB(3, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))), 389 ), numEntries = IssueQueueSize, numEnq = 2), 390 IssueBlockParams(Seq( 391 ExeUnitParams("STD0", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(13, 1), VfRD(6, 0)))), 392 ), numEntries = IssueQueueSize, numEnq = 2), 393 IssueBlockParams(Seq( 394 ExeUnitParams("STD1", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(5, 1), VfRD(10, Int.MaxValue)))), 395 ), numEntries = IssueQueueSize, numEnq = 2), 396 ), 397 numPregs = intPreg.numEntries max vfPreg.numEntries, 398 numDeqOutside = 0, 399 schdType = schdType, 400 rfDataWidth = rfDataWidth, 401 numUopIn = dpParams.LsDqDeqWidth, 402 ) 403 } 404 405 def PregIdxWidthMax = intPreg.addrWidth max vfPreg.addrWidth 406 407 def iqWakeUpParams = { 408 Seq( 409 WakeUpConfig( 410 Seq("ALU0", "ALU1", "MUL0", "MUL1", "LDU0", "LDU1", "HYU0") -> 411 Seq("ALU0", "ALU1", "MUL0", "MUL1", "BJU0", "BJU1", "BJU2", "LDU0", "LDU1", "STA0", "STD0", "STD1", "HYU0") 412 ), 413 WakeUpConfig(Seq("IMISC0") -> Seq("VFEX0","VFEX1")), 414 ).flatten 415 } 416 417 val backendParams: BackendParams = backend.BackendParams( 418 Map( 419 IntScheduler() -> intSchdParams, 420 VfScheduler() -> vfSchdParams, 421 MemScheduler() -> memSchdParams, 422 ), 423 Seq( 424 intPreg, 425 vfPreg, 426 ), 427 iqWakeUpParams, 428 ) 429} 430 431case object DebugOptionsKey extends Field[DebugOptions] 432 433case class DebugOptions 434( 435 FPGAPlatform: Boolean = false, 436 EnableDifftest: Boolean = false, 437 AlwaysBasicDiff: Boolean = true, 438 EnableDebug: Boolean = false, 439 EnablePerfDebug: Boolean = true, 440 UseDRAMSim: Boolean = false, 441 EnableConstantin: Boolean = false, 442 EnableChiselDB: Boolean = false, 443 AlwaysBasicDB: Boolean = true, 444 EnableTopDown: Boolean = false, 445 EnableRollingDB: Boolean = false 446) 447 448trait HasXSParameter { 449 450 implicit val p: Parameters 451 452 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 453 454 val coreParams = p(XSCoreParamsKey) 455 val env = p(DebugOptionsKey) 456 457 val XLEN = coreParams.XLEN 458 val VLEN = coreParams.VLEN 459 val ELEN = coreParams.ELEN 460 val minFLen = 32 461 val fLen = 64 462 def xLen = XLEN 463 464 val HasMExtension = coreParams.HasMExtension 465 val HasCExtension = coreParams.HasCExtension 466 val HasDiv = coreParams.HasDiv 467 val HasIcache = coreParams.HasICache 468 val HasDcache = coreParams.HasDCache 469 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 470 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 471 val AsidLength = coreParams.AsidLength 472 val ReSelectLen = coreParams.ReSelectLen 473 val AddrBytes = AddrBits / 8 // unused 474 val DataBits = XLEN 475 val DataBytes = DataBits / 8 476 val VDataBytes = VLEN / 8 477 val HasFPU = coreParams.HasFPU 478 val HasVPU = coreParams.HasVPU 479 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 480 val FetchWidth = coreParams.FetchWidth 481 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 482 val EnableBPU = coreParams.EnableBPU 483 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 484 val EnableRAS = coreParams.EnableRAS 485 val EnableLB = coreParams.EnableLB 486 val EnableLoop = coreParams.EnableLoop 487 val EnableSC = coreParams.EnableSC 488 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 489 val HistoryLength = coreParams.HistoryLength 490 val EnableGHistDiff = coreParams.EnableGHistDiff 491 val EnableCommitGHistDiff = coreParams.EnableCommitGHistDiff 492 val UbtbGHRLength = coreParams.UbtbGHRLength 493 val UbtbSize = coreParams.UbtbSize 494 val EnableFauFTB = coreParams.EnableFauFTB 495 val FtbSize = coreParams.FtbSize 496 val FtbWays = coreParams.FtbWays 497 val RasSize = coreParams.RasSize 498 val RasSpecSize = coreParams.RasSpecSize 499 val RasCtrSize = coreParams.RasCtrSize 500 501 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 502 coreParams.branchPredictor(resp_in, p) 503 } 504 val numBr = coreParams.numBr 505 val TageTableInfos = coreParams.TageTableInfos 506 val TageBanks = coreParams.numBr 507 val SCNRows = coreParams.SCNRows 508 val SCCtrBits = coreParams.SCCtrBits 509 val SCHistLens = coreParams.SCHistLens 510 val SCNTables = coreParams.SCNTables 511 512 val SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 513 case ((n, cb), h) => (n, cb, h) 514 } 515 val ITTageTableInfos = coreParams.ITTageTableInfos 516 type FoldedHistoryInfo = Tuple2[Int, Int] 517 val foldedGHistInfos = 518 (TageTableInfos.map{ case (nRows, h, t) => 519 if (h > 0) 520 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 521 else 522 Set[FoldedHistoryInfo]() 523 }.reduce(_++_).toSet ++ 524 SCTableInfos.map{ case (nRows, _, h) => 525 if (h > 0) 526 Set((h, min(log2Ceil(nRows/TageBanks), h))) 527 else 528 Set[FoldedHistoryInfo]() 529 }.reduce(_++_).toSet ++ 530 ITTageTableInfos.map{ case (nRows, h, t) => 531 if (h > 0) 532 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 533 else 534 Set[FoldedHistoryInfo]() 535 }.reduce(_++_) ++ 536 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 537 ).toList 538 539 540 541 val CacheLineSize = coreParams.CacheLineSize 542 val CacheLineHalfWord = CacheLineSize / 16 543 val ExtHistoryLength = HistoryLength + 64 544 val ICacheECCForceError = coreParams.ICacheECCForceError 545 val IBufSize = coreParams.IBufSize 546 val IBufNBank = coreParams.IBufNBank 547 val backendParams: BackendParams = coreParams.backendParams 548 val DecodeWidth = coreParams.DecodeWidth 549 val RenameWidth = coreParams.RenameWidth 550 val CommitWidth = coreParams.CommitWidth 551 val MaxUopSize = coreParams.MaxUopSize 552 val EnableRenameSnapshot = coreParams.EnableRenameSnapshot 553 val RenameSnapshotNum = coreParams.RenameSnapshotNum 554 val FtqSize = coreParams.FtqSize 555 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 556 val IntLogicRegs = coreParams.IntLogicRegs 557 val FpLogicRegs = coreParams.FpLogicRegs 558 val VecLogicRegs = coreParams.VecLogicRegs 559 val VCONFIG_IDX = coreParams.VCONFIG_IDX 560 val IntPhyRegs = coreParams.intPreg.numEntries 561 val VfPhyRegs = coreParams.vfPreg.numEntries 562 val MaxPhyPregs = IntPhyRegs max VfPhyRegs 563 val PhyRegIdxWidth = log2Up(IntPhyRegs) max log2Up(VfPhyRegs) 564 val RobSize = coreParams.RobSize 565 val RabSize = coreParams.RabSize 566 val VTypeBufferSize = coreParams.VTypeBufferSize 567 val IntRefCounterWidth = log2Ceil(RobSize) 568 val LSQEnqWidth = coreParams.dpParams.LsDqDeqWidth 569 val LSQLdEnqWidth = LSQEnqWidth min backendParams.numLoadDp 570 val LSQStEnqWidth = LSQEnqWidth min backendParams.numStoreDp 571 val VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize 572 val LoadQueueRARSize = coreParams.LoadQueueRARSize 573 val LoadQueueRAWSize = coreParams.LoadQueueRAWSize 574 val RollbackGroupSize = coreParams.RollbackGroupSize 575 val LoadQueueReplaySize = coreParams.LoadQueueReplaySize 576 val LoadUncacheBufferSize = coreParams.LoadUncacheBufferSize 577 val LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 578 val StoreQueueSize = coreParams.StoreQueueSize 579 val StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 580 val StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask 581 val VlsQueueSize = coreParams.VlsQueueSize 582 val dpParams = coreParams.dpParams 583 584 def MemIQSizeMax = backendParams.memSchdParams.get.issueBlockParams.map(_.numEntries).max 585 def IQSizeMax = backendParams.allSchdParams.map(_.issueBlockParams.map(_.numEntries).max).max 586 587 val NumRedirect = backendParams.numRedirect 588 val BackendRedirectNum = NumRedirect + 2 //2: ldReplay + Exception 589 val FtqRedirectAheadNum = NumRedirect 590 val LoadPipelineWidth = coreParams.LoadPipelineWidth 591 val StorePipelineWidth = coreParams.StorePipelineWidth 592 val VecLoadPipelineWidth = coreParams.VecLoadPipelineWidth 593 val VecStorePipelineWidth = coreParams.VecStorePipelineWidth 594 val VecMemSrcInWidth = coreParams.VecMemSrcInWidth 595 val VecMemInstWbWidth = coreParams.VecMemInstWbWidth 596 val VecMemDispatchWidth = coreParams.VecMemDispatchWidth 597 val StoreBufferSize = coreParams.StoreBufferSize 598 val StoreBufferThreshold = coreParams.StoreBufferThreshold 599 val EnsbufferWidth = coreParams.EnsbufferWidth 600 val UsQueueSize = coreParams.UsQueueSize 601 val VlFlowSize = coreParams.VlFlowSize 602 val VlUopSize = coreParams.VlUopSize 603 val VsFlowL1Size = coreParams.VsFlowL1Size 604 val VsFlowL2Size = coreParams.VsFlowL2Size 605 val VsUopSize = coreParams.VsUopSize 606 val UncacheBufferSize = coreParams.UncacheBufferSize 607 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 608 val EnableFastForward = coreParams.EnableFastForward 609 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 610 val EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 611 val EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 612 val EnableAccurateLoadError = coreParams.EnableAccurateLoadError 613 val EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 614 val EnableStorePrefetchAtIssue = coreParams.EnableStorePrefetchAtIssue 615 val EnableStorePrefetchAtCommit = coreParams.EnableStorePrefetchAtCommit 616 val EnableAtCommitMissTrigger = coreParams.EnableAtCommitMissTrigger 617 val EnableStorePrefetchSMS = coreParams.EnableStorePrefetchSMS 618 val EnableStorePrefetchSPB = coreParams.EnableStorePrefetchSPB 619 val asidLen = coreParams.MMUAsidLen 620 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 621 val refillBothTlb = coreParams.refillBothTlb 622 val iwpuParam = coreParams.iwpuParameters 623 val dwpuParam = coreParams.dwpuParameters 624 val itlbParams = coreParams.itlbParameters 625 val ldtlbParams = coreParams.ldtlbParameters 626 val sttlbParams = coreParams.sttlbParameters 627 val hytlbParams = coreParams.hytlbParameters 628 val pftlbParams = coreParams.pftlbParameters 629 val btlbParams = coreParams.btlbParameters 630 val l2tlbParams = coreParams.l2tlbParameters 631 val NumPerfCounters = coreParams.NumPerfCounters 632 633 val instBytes = if (HasCExtension) 2 else 4 634 val instOffsetBits = log2Ceil(instBytes) 635 636 val icacheParameters = coreParams.icacheParameters 637 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 638 639 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 640 // for constrained LR/SC loop 641 val LRSCCycles = 64 642 // for lr storm 643 val LRSCBackOff = 8 644 645 // cache hierarchy configurations 646 val l1BusDataWidth = 256 647 648 // load violation predict 649 val ResetTimeMax2Pow = 20 //1078576 650 val ResetTimeMin2Pow = 10 //1024 651 // wait table parameters 652 val WaitTableSize = 1024 653 val MemPredPCWidth = log2Up(WaitTableSize) 654 val LWTUse2BitCounter = true 655 // store set parameters 656 val SSITSize = WaitTableSize 657 val LFSTSize = 32 658 val SSIDWidth = log2Up(LFSTSize) 659 val LFSTWidth = 4 660 val StoreSetEnable = true // LWT will be disabled if SS is enabled 661 val LFSTEnable = true 662 663 val PCntIncrStep: Int = 6 664 val numPCntHc: Int = 25 665 val numPCntPtw: Int = 19 666 667 val numCSRPCntFrontend = 8 668 val numCSRPCntCtrl = 8 669 val numCSRPCntLsu = 8 670 val numCSRPCntHc = 5 671 val printEventCoding = true 672 673 // Parameters for Sdtrig extension 674 protected val TriggerNum = 4 675 protected val TriggerChainMaxLength = 2 676} 677