1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import org.chipsalliance.cde.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import huancun._ 23import system.SoCParamsKey 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.dispatch.DispatchParameters 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.issue.{IntScheduler, IssueBlockParams, MemScheduler, SchdBlockParams, SchedulerType, VfScheduler} 30import xiangshan.backend.regfile.{IntPregParams, PregParams, VfPregParams} 31import xiangshan.backend.BackendParams 32import xiangshan.cache.DCacheParameters 33import xiangshan.cache.prefetch._ 34import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 35import xiangshan.frontend.icache.ICacheParameters 36import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 37import xiangshan.frontend._ 38import xiangshan.frontend.icache.ICacheParameters 39 40import freechips.rocketchip.diplomacy.AddressSet 41import system.SoCParamsKey 42import huancun._ 43import huancun.debug._ 44import xiangshan.cache.wpu.WPUParameters 45import coupledL2._ 46import xiangshan.backend.datapath.WakeUpConfig 47import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 48 49import scala.math.min 50 51case object XSTileKey extends Field[Seq[XSCoreParameters]] 52 53case object XSCoreParamsKey extends Field[XSCoreParameters] 54 55case class XSCoreParameters 56( 57 HasPrefetch: Boolean = false, 58 HartId: Int = 0, 59 XLEN: Int = 64, 60 VLEN: Int = 128, 61 ELEN: Int = 64, 62 HasMExtension: Boolean = true, 63 HasCExtension: Boolean = true, 64 HasDiv: Boolean = true, 65 HasICache: Boolean = true, 66 HasDCache: Boolean = true, 67 AddrBits: Int = 64, 68 VAddrBits: Int = 39, 69 HasFPU: Boolean = true, 70 HasVPU: Boolean = true, 71 HasCustomCSRCacheOp: Boolean = true, 72 FetchWidth: Int = 8, 73 AsidLength: Int = 16, 74 EnableBPU: Boolean = true, 75 EnableBPD: Boolean = true, 76 EnableRAS: Boolean = true, 77 EnableLB: Boolean = false, 78 EnableLoop: Boolean = true, 79 EnableSC: Boolean = true, 80 EnbaleTlbDebug: Boolean = false, 81 EnableJal: Boolean = false, 82 EnableFauFTB: Boolean = true, 83 UbtbGHRLength: Int = 4, 84 // HistoryLength: Int = 512, 85 EnableGHistDiff: Boolean = true, 86 EnableCommitGHistDiff: Boolean = true, 87 UbtbSize: Int = 256, 88 FtbSize: Int = 2048, 89 RasSize: Int = 32, 90 RasSpecSize: Int = 64, 91 RasCtrSize: Int = 8, 92 CacheLineSize: Int = 512, 93 FtbWays: Int = 4, 94 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 95 // Sets Hist Tag 96 // Seq(( 2048, 2, 8), 97 // ( 2048, 9, 8), 98 // ( 2048, 13, 8), 99 // ( 2048, 20, 8), 100 // ( 2048, 26, 8), 101 // ( 2048, 44, 8), 102 // ( 2048, 73, 8), 103 // ( 2048, 256, 8)), 104 Seq(( 4096, 8, 8), 105 ( 4096, 13, 8), 106 ( 4096, 32, 8), 107 ( 4096, 119, 8)), 108 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 109 // Sets Hist Tag 110 Seq(( 256, 4, 9), 111 ( 256, 8, 9), 112 ( 512, 13, 9), 113 ( 512, 16, 9), 114 ( 512, 32, 9)), 115 SCNRows: Int = 512, 116 SCNTables: Int = 4, 117 SCCtrBits: Int = 6, 118 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 119 numBr: Int = 2, 120 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 121 ((resp_in: BranchPredictionResp, p: Parameters) => { 122 val ftb = Module(new FTB()(p)) 123 val ubtb =Module(new FauFTB()(p)) 124 // val bim = Module(new BIM()(p)) 125 val tage = Module(new Tage_SC()(p)) 126 val ras = Module(new RAS()(p)) 127 val ittage = Module(new ITTage()(p)) 128 val preds = Seq(ubtb, tage, ftb, ittage, ras) 129 preds.map(_.io := DontCare) 130 131 // ubtb.io.resp_in(0) := resp_in 132 // bim.io.resp_in(0) := ubtb.io.resp 133 // btb.io.resp_in(0) := bim.io.resp 134 // tage.io.resp_in(0) := btb.io.resp 135 // loop.io.resp_in(0) := tage.io.resp 136 ubtb.io.in.bits.resp_in(0) := resp_in 137 tage.io.in.bits.resp_in(0) := ubtb.io.out 138 ftb.io.in.bits.resp_in(0) := tage.io.out 139 ittage.io.in.bits.resp_in(0) := ftb.io.out 140 ras.io.in.bits.resp_in(0) := ittage.io.out 141 142 (preds, ras.io.out) 143 }), 144 IBufSize: Int = 48, 145 DecodeWidth: Int = 6, 146 RenameWidth: Int = 6, 147 CommitWidth: Int = 6, 148 MaxUopSize: Int = 65, 149 EnableRenameSnapshot: Boolean = true, 150 RenameSnapshotNum: Int = 4, 151 FtqSize: Int = 64, 152 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 153 IntLogicRegs: Int = 32, 154 FpLogicRegs: Int = 32 + 1 + 1, // 1: I2F, 1: stride 155 VecLogicRegs: Int = 32 + 1 + 15, // 15: tmp, 1: vconfig 156 VCONFIG_IDX: Int = 32, 157 NRPhyRegs: Int = 192, 158 VirtualLoadQueueSize: Int = 80, 159 LoadQueueRARSize: Int = 80, 160 LoadQueueRAWSize: Int = 64, // NOTE: make sure that LoadQueueRAWSize is power of 2. 161 RollbackGroupSize: Int = 8, 162 LoadQueueReplaySize: Int = 72, 163 LoadUncacheBufferSize: Int = 20, 164 LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks 165 StoreQueueSize: Int = 64, 166 StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 167 StoreQueueForwardWithMask: Boolean = true, 168 VlsQueueSize: Int = 8, 169 RobSize: Int = 256, 170 RabSize: Int = 256, 171 VTypeBufferSize: Int = 64, // used to reorder vtype 172 IssueQueueSize: Int = 32, 173 dpParams: DispatchParameters = DispatchParameters( 174 IntDqSize = 16, 175 FpDqSize = 16, 176 LsDqSize = 18, 177 IntDqDeqWidth = 6, 178 FpDqDeqWidth = 6, 179 LsDqDeqWidth = 6, 180 ), 181 intPreg: PregParams = IntPregParams( 182 numEntries = 224, 183 numRead = None, 184 numWrite = None, 185 ), 186 vfPreg: VfPregParams = VfPregParams( 187 numEntries = 192, 188 numRead = Some(14), 189 numWrite = None, 190 ), 191 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 192 LoadPipelineWidth: Int = 3, 193 StorePipelineWidth: Int = 2, 194 VecLoadPipelineWidth: Int = 2, 195 VecStorePipelineWidth: Int = 2, 196 VecMemSrcInWidth: Int = 2, 197 VecMemInstWbWidth: Int = 1, 198 VecMemDispatchWidth: Int = 1, 199 StoreBufferSize: Int = 16, 200 StoreBufferThreshold: Int = 7, 201 EnsbufferWidth: Int = 2, 202 // ============ VLSU ============ 203 UsQueueSize: Int = 8, 204 VlFlowSize: Int = 32, 205 VlUopSize: Int = 32, 206 VsFlowL1Size: Int = 128, 207 VsFlowL2Size: Int = 32, 208 VsUopSize: Int = 32, 209 // ============================== 210 UncacheBufferSize: Int = 4, 211 EnableLoadToLoadForward: Boolean = true, 212 EnableFastForward: Boolean = true, 213 EnableLdVioCheckAfterReset: Boolean = true, 214 EnableSoftPrefetchAfterReset: Boolean = true, 215 EnableCacheErrorAfterReset: Boolean = true, 216 EnableAccurateLoadError: Boolean = true, 217 EnableUncacheWriteOutstanding: Boolean = false, 218 EnableStorePrefetchAtIssue: Boolean = false, 219 EnableStorePrefetchAtCommit: Boolean = false, 220 EnableAtCommitMissTrigger: Boolean = true, 221 EnableStorePrefetchSMS: Boolean = false, 222 EnableStorePrefetchSPB: Boolean = false, 223 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 224 ReSelectLen: Int = 7, // load replay queue replay select counter len 225 iwpuParameters: WPUParameters = WPUParameters( 226 enWPU = false, 227 algoName = "mmru", 228 isICache = true, 229 ), 230 dwpuParameters: WPUParameters = WPUParameters( 231 enWPU = false, 232 algoName = "mmru", 233 enCfPred = false, 234 isICache = false, 235 ), 236 itlbParameters: TLBParameters = TLBParameters( 237 name = "itlb", 238 fetchi = true, 239 useDmode = false, 240 NWays = 48, 241 ), 242 itlbPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 243 ipmpPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 244 ldtlbParameters: TLBParameters = TLBParameters( 245 name = "ldtlb", 246 NWays = 48, 247 outReplace = false, 248 partialStaticPMP = true, 249 outsideRecvFlush = true, 250 saveLevel = true 251 ), 252 sttlbParameters: TLBParameters = TLBParameters( 253 name = "sttlb", 254 NWays = 48, 255 outReplace = false, 256 partialStaticPMP = true, 257 outsideRecvFlush = true, 258 saveLevel = true 259 ), 260 hytlbParameters: TLBParameters = TLBParameters( 261 name = "hytlb", 262 NWays = 48, 263 outReplace = false, 264 partialStaticPMP = true, 265 outsideRecvFlush = true, 266 saveLevel = true 267 ), 268 pftlbParameters: TLBParameters = TLBParameters( 269 name = "pftlb", 270 NWays = 48, 271 outReplace = false, 272 partialStaticPMP = true, 273 outsideRecvFlush = true, 274 saveLevel = true 275 ), 276 refillBothTlb: Boolean = false, 277 btlbParameters: TLBParameters = TLBParameters( 278 name = "btlb", 279 NWays = 48, 280 ), 281 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 282 NumPerfCounters: Int = 16, 283 icacheParameters: ICacheParameters = ICacheParameters( 284 tagECC = Some("parity"), 285 dataECC = Some("parity"), 286 replacer = Some("setplru"), 287 nMissEntries = 2, 288 nProbeEntries = 2, 289 nPrefetchEntries = 12, 290 nPrefBufferEntries = 32, 291 ), 292 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 293 tagECC = Some("secded"), 294 dataECC = Some("secded"), 295 replacer = Some("setplru"), 296 nMissEntries = 16, 297 nProbeEntries = 8, 298 nReleaseEntries = 18, 299 nMaxPrefetchEntry = 6, 300 )), 301 L2CacheParamsOpt: Option[L2Param] = Some(L2Param( 302 name = "l2", 303 ways = 8, 304 sets = 1024, // default 512KB L2 305 prefetch = Some(coupledL2.prefetch.PrefetchReceiverParams()) 306 )), 307 L2NBanks: Int = 1, 308 usePTWRepeater: Boolean = false, 309 softTLB: Boolean = false, // dpi-c l1tlb debug only 310 softPTW: Boolean = false, // dpi-c l2tlb debug only 311 softPTWDelay: Int = 1 312){ 313 def vlWidth = log2Up(VLEN) + 1 314 315 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 316 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 317 318 val intSchdParams = { 319 implicit val schdType: SchedulerType = IntScheduler() 320 SchdBlockParams(Seq( 321 IssueBlockParams(Seq( 322 ExeUnitParams("ALU0", Seq(AluCfg), Seq(IntWB(port = 0, 0)), Seq(Seq(IntRD(0, 0)), Seq(IntRD(1, 0)))), 323 ExeUnitParams("ALU1", Seq(AluCfg), Seq(IntWB(port = 1, 0)), Seq(Seq(IntRD(2, 0)), Seq(IntRD(3, 0)))), 324 ), numEntries = IssueQueueSize, numEnq = 2), 325 IssueBlockParams(Seq( 326 ExeUnitParams("MUL0", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 2, 0)), Seq(Seq(IntRD(4, 0)), Seq(IntRD(5, 0)))), 327 ExeUnitParams("MUL1", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 3, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0)))), 328 ), numEntries = IssueQueueSize, numEnq = 2), 329 IssueBlockParams(Seq( 330 ExeUnitParams("BJU0", Seq(BrhCfg), Seq(), Seq(Seq(IntRD(8, 0)), Seq(IntRD(9, 0)))), 331 ExeUnitParams("BJU1", Seq(BrhCfg), Seq(), Seq(Seq(IntRD(10, 0)), Seq(IntRD(12, 1)))), 332 ), numEntries = IssueQueueSize, numEnq = 2), 333 IssueBlockParams(Seq( 334 ExeUnitParams("BJU2", Seq(BrhCfg), Seq(), Seq(Seq(IntRD(11, 0)), Seq(IntRD(7, 1)))), 335 ), numEntries = IssueQueueSize / 2, numEnq = 1), 336 IssueBlockParams(Seq( 337 ExeUnitParams("IMISC0", Seq(VSetRiWiCfg, I2fCfg, I2vCfg, VSetRiWvfCfg, JmpCfg, CsrCfg, FenceCfg), Seq(IntWB(port = 4, 1), VfWB(2, 0)), Seq(Seq(IntRD(5, 1)), Seq(IntRD(3, 1)))), 338 ExeUnitParams("IDIV0", Seq(DivCfg), Seq(IntWB(port = 7, 1)), Seq(Seq(IntRD(1, Int.MaxValue)), Seq(IntRD(9, Int.MaxValue)))), 339 ), numEntries = IssueQueueSize, numEnq = 2), 340 ), 341 numPregs = intPreg.numEntries, 342 numDeqOutside = 0, 343 schdType = schdType, 344 rfDataWidth = intPreg.dataCfg.dataWidth, 345 numUopIn = dpParams.IntDqDeqWidth, 346 ) 347 } 348 val vfSchdParams = { 349 implicit val schdType: SchedulerType = VfScheduler() 350 SchdBlockParams(Seq( 351 IssueBlockParams(Seq( 352 ExeUnitParams("VFEX0", Seq(VfaluCfg, VfmaCfg, VialuCfg, VppuCfg, F2fCfg, F2iCfg, VSetRvfWvfCfg), Seq(VfWB(port = 0, 0), IntWB(port = 4, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))), 353 ExeUnitParams("VFEX1", Seq(VfaluCfg, VfmaCfg, VimacCfg, VipuCfg, VfcvtCfg), Seq(VfWB(port = 1, 0), IntWB(port = 8, 0)), Seq(Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(VfRD(9, 0)), Seq(VfRD(10, 0)), Seq(VfRD(11, 0)))), 354 ), numEntries = IssueQueueSize, numEnq = 2), 355 IssueBlockParams(Seq( 356 ExeUnitParams("VFEX2", Seq(VfdivCfg), Seq(VfWB(port = 5, 0)), Seq(Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(VfRD(9, 0)), Seq(VfRD(10, 0)), Seq(VfRD(11, 0)))), 357 ), numEntries = IssueQueueSize, numEnq = 2), 358 ), 359 numPregs = vfPreg.numEntries, 360 numDeqOutside = 0, 361 schdType = schdType, 362 rfDataWidth = vfPreg.dataCfg.dataWidth, 363 numUopIn = dpParams.FpDqDeqWidth, 364 ) 365 } 366 367 val memSchdParams = { 368 implicit val schdType: SchedulerType = MemScheduler() 369 val rfDataWidth = 64 370 371 SchdBlockParams(Seq( 372 IssueBlockParams(Seq( 373 ExeUnitParams("LDU0", Seq(LduCfg), Seq(IntWB(6, 0), VfWB(3, 0)), Seq(Seq(IntRD(12, 0)))), 374 ExeUnitParams("STA0", Seq(StaCfg), Seq(), Seq(Seq(IntRD(3, 1)))), 375 ), numEntries = IssueQueueSize, numEnq = 2), 376 IssueBlockParams(Seq( 377 ExeUnitParams("HYU0", Seq(HyldaCfg, HystaCfg, MouCfg), Seq(IntWB(5, 0), VfWB(5, 0)), Seq(Seq(IntRD(6, 0)))), 378 ExeUnitParams("HYU1", Seq(FakeHystaCfg), Seq(), Seq()), // fake unit, used to create a new writeback port 379 ), numEntries = IssueQueueSize, numEnq = 2), 380 IssueBlockParams(Seq( 381 ExeUnitParams("LDU1", Seq(LduCfg), Seq(IntWB(7, 0), VfWB(4, 0)), Seq(Seq(IntRD(13, 0)))), 382 ), numEntries = IssueQueueSize, numEnq = 2), 383 IssueBlockParams(Seq( 384 ExeUnitParams("VLSU0", Seq(VlduCfg, VstuCfg), Seq(VfWB(3, 1)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))), 385 ), numEntries = IssueQueueSize, numEnq = 2), 386 IssueBlockParams(Seq( 387 ExeUnitParams("STD0", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(13, 1), VfRD(6, 0)))), 388 ExeUnitParams("STD1", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(5, 1), VfRD(10, Int.MaxValue)))), 389 ), numEntries = IssueQueueSize, numEnq = 4), 390 ), 391 numPregs = intPreg.numEntries max vfPreg.numEntries, 392 numDeqOutside = 0, 393 schdType = schdType, 394 rfDataWidth = rfDataWidth, 395 numUopIn = dpParams.LsDqDeqWidth, 396 ) 397 } 398 399 def PregIdxWidthMax = intPreg.addrWidth max vfPreg.addrWidth 400 401 def iqWakeUpParams = { 402 Seq( 403 WakeUpConfig( 404 Seq("ALU0", "ALU1", "MUL0", "MUL1", "LDU0", "LDU1", "HYU0") -> 405 Seq("ALU0", "ALU1", "MUL0", "MUL1", "BJU0", "BJU1", "BJU2", "LDU0", "LDU1", "STA0", "STD0", "STD1", "HYU0") 406 ), 407 WakeUpConfig(Seq("IMISC0") -> Seq("VFEX0")), 408 ).flatten 409 } 410 411 def backendParams: BackendParams = backend.BackendParams( 412 Map( 413 IntScheduler() -> intSchdParams, 414 VfScheduler() -> vfSchdParams, 415 MemScheduler() -> memSchdParams, 416 ), 417 Seq( 418 intPreg, 419 vfPreg, 420 ), 421 iqWakeUpParams, 422 ) 423} 424 425case object DebugOptionsKey extends Field[DebugOptions] 426 427case class DebugOptions 428( 429 FPGAPlatform: Boolean = false, 430 EnableDifftest: Boolean = false, 431 AlwaysBasicDiff: Boolean = true, 432 EnableDebug: Boolean = false, 433 EnablePerfDebug: Boolean = true, 434 UseDRAMSim: Boolean = false, 435 EnableConstantin: Boolean = false, 436 EnableChiselDB: Boolean = false, 437 AlwaysBasicDB: Boolean = true, 438 EnableTopDown: Boolean = false, 439 EnableRollingDB: Boolean = false 440) 441 442trait HasXSParameter { 443 444 implicit val p: Parameters 445 446 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 447 448 val coreParams = p(XSCoreParamsKey) 449 val env = p(DebugOptionsKey) 450 451 val XLEN = coreParams.XLEN 452 val VLEN = coreParams.VLEN 453 val ELEN = coreParams.ELEN 454 val minFLen = 32 455 val fLen = 64 456 def xLen = XLEN 457 458 val HasMExtension = coreParams.HasMExtension 459 val HasCExtension = coreParams.HasCExtension 460 val HasDiv = coreParams.HasDiv 461 val HasIcache = coreParams.HasICache 462 val HasDcache = coreParams.HasDCache 463 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 464 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 465 val AsidLength = coreParams.AsidLength 466 val ReSelectLen = coreParams.ReSelectLen 467 val AddrBytes = AddrBits / 8 // unused 468 val DataBits = XLEN 469 val DataBytes = DataBits / 8 470 val VDataBytes = VLEN / 8 471 val HasFPU = coreParams.HasFPU 472 val HasVPU = coreParams.HasVPU 473 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 474 val FetchWidth = coreParams.FetchWidth 475 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 476 val EnableBPU = coreParams.EnableBPU 477 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 478 val EnableRAS = coreParams.EnableRAS 479 val EnableLB = coreParams.EnableLB 480 val EnableLoop = coreParams.EnableLoop 481 val EnableSC = coreParams.EnableSC 482 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 483 val HistoryLength = coreParams.HistoryLength 484 val EnableGHistDiff = coreParams.EnableGHistDiff 485 val EnableCommitGHistDiff = coreParams.EnableCommitGHistDiff 486 val UbtbGHRLength = coreParams.UbtbGHRLength 487 val UbtbSize = coreParams.UbtbSize 488 val EnableFauFTB = coreParams.EnableFauFTB 489 val FtbSize = coreParams.FtbSize 490 val FtbWays = coreParams.FtbWays 491 val RasSize = coreParams.RasSize 492 val RasSpecSize = coreParams.RasSpecSize 493 val RasCtrSize = coreParams.RasCtrSize 494 495 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 496 coreParams.branchPredictor(resp_in, p) 497 } 498 val numBr = coreParams.numBr 499 val TageTableInfos = coreParams.TageTableInfos 500 val TageBanks = coreParams.numBr 501 val SCNRows = coreParams.SCNRows 502 val SCCtrBits = coreParams.SCCtrBits 503 val SCHistLens = coreParams.SCHistLens 504 val SCNTables = coreParams.SCNTables 505 506 val SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 507 case ((n, cb), h) => (n, cb, h) 508 } 509 val ITTageTableInfos = coreParams.ITTageTableInfos 510 type FoldedHistoryInfo = Tuple2[Int, Int] 511 val foldedGHistInfos = 512 (TageTableInfos.map{ case (nRows, h, t) => 513 if (h > 0) 514 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 515 else 516 Set[FoldedHistoryInfo]() 517 }.reduce(_++_).toSet ++ 518 SCTableInfos.map{ case (nRows, _, h) => 519 if (h > 0) 520 Set((h, min(log2Ceil(nRows/TageBanks), h))) 521 else 522 Set[FoldedHistoryInfo]() 523 }.reduce(_++_).toSet ++ 524 ITTageTableInfos.map{ case (nRows, h, t) => 525 if (h > 0) 526 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 527 else 528 Set[FoldedHistoryInfo]() 529 }.reduce(_++_) ++ 530 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 531 ).toList 532 533 534 535 val CacheLineSize = coreParams.CacheLineSize 536 val CacheLineHalfWord = CacheLineSize / 16 537 val ExtHistoryLength = HistoryLength + 64 538 val IBufSize = coreParams.IBufSize 539 val DecodeWidth = coreParams.DecodeWidth 540 val RenameWidth = coreParams.RenameWidth 541 val CommitWidth = coreParams.CommitWidth 542 val MaxUopSize = coreParams.MaxUopSize 543 val EnableRenameSnapshot = coreParams.EnableRenameSnapshot 544 val RenameSnapshotNum = coreParams.RenameSnapshotNum 545 val FtqSize = coreParams.FtqSize 546 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 547 val IntLogicRegs = coreParams.IntLogicRegs 548 val FpLogicRegs = coreParams.FpLogicRegs 549 val VecLogicRegs = coreParams.VecLogicRegs 550 val VCONFIG_IDX = coreParams.VCONFIG_IDX 551 val IntPhyRegs = coreParams.intPreg.numEntries 552 val VfPhyRegs = coreParams.vfPreg.numEntries 553 val MaxPhyPregs = IntPhyRegs max VfPhyRegs 554 val PhyRegIdxWidth = log2Up(IntPhyRegs) max log2Up(VfPhyRegs) 555 val RobSize = coreParams.RobSize 556 val RabSize = coreParams.RabSize 557 val VTypeBufferSize = coreParams.VTypeBufferSize 558 val IntRefCounterWidth = log2Ceil(RobSize) 559 val LSQEnqWidth = coreParams.dpParams.LsDqDeqWidth 560 val VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize 561 val LoadQueueRARSize = coreParams.LoadQueueRARSize 562 val LoadQueueRAWSize = coreParams.LoadQueueRAWSize 563 val RollbackGroupSize = coreParams.RollbackGroupSize 564 val LoadQueueReplaySize = coreParams.LoadQueueReplaySize 565 val LoadUncacheBufferSize = coreParams.LoadUncacheBufferSize 566 val LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 567 val StoreQueueSize = coreParams.StoreQueueSize 568 val StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 569 val StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask 570 val VlsQueueSize = coreParams.VlsQueueSize 571 val dpParams = coreParams.dpParams 572 573 def backendParams: BackendParams = coreParams.backendParams 574 def MemIQSizeMax = backendParams.memSchdParams.get.issueBlockParams.map(_.numEntries).max 575 def IQSizeMax = backendParams.allSchdParams.map(_.issueBlockParams.map(_.numEntries).max).max 576 577 val NumRedirect = backendParams.numRedirect 578 val BackendRedirectNum = NumRedirect + 2 //2: ldReplay + Exception 579 val LoadPipelineWidth = coreParams.LoadPipelineWidth 580 val StorePipelineWidth = coreParams.StorePipelineWidth 581 val VecLoadPipelineWidth = coreParams.VecLoadPipelineWidth 582 val VecStorePipelineWidth = coreParams.VecStorePipelineWidth 583 val VecMemSrcInWidth = coreParams.VecMemSrcInWidth 584 val VecMemInstWbWidth = coreParams.VecMemInstWbWidth 585 val VecMemDispatchWidth = coreParams.VecMemDispatchWidth 586 val StoreBufferSize = coreParams.StoreBufferSize 587 val StoreBufferThreshold = coreParams.StoreBufferThreshold 588 val EnsbufferWidth = coreParams.EnsbufferWidth 589 val UsQueueSize = coreParams.UsQueueSize 590 val VlFlowSize = coreParams.VlFlowSize 591 val VlUopSize = coreParams.VlUopSize 592 val VsFlowL1Size = coreParams.VsFlowL1Size 593 val VsFlowL2Size = coreParams.VsFlowL2Size 594 val VsUopSize = coreParams.VsUopSize 595 val UncacheBufferSize = coreParams.UncacheBufferSize 596 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 597 val EnableFastForward = coreParams.EnableFastForward 598 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 599 val EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 600 val EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 601 val EnableAccurateLoadError = coreParams.EnableAccurateLoadError 602 val EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 603 val EnableStorePrefetchAtIssue = coreParams.EnableStorePrefetchAtIssue 604 val EnableStorePrefetchAtCommit = coreParams.EnableStorePrefetchAtCommit 605 val EnableAtCommitMissTrigger = coreParams.EnableAtCommitMissTrigger 606 val EnableStorePrefetchSMS = coreParams.EnableStorePrefetchSMS 607 val EnableStorePrefetchSPB = coreParams.EnableStorePrefetchSPB 608 val asidLen = coreParams.MMUAsidLen 609 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 610 val refillBothTlb = coreParams.refillBothTlb 611 val iwpuParam = coreParams.iwpuParameters 612 val dwpuParam = coreParams.dwpuParameters 613 val itlbParams = coreParams.itlbParameters 614 val ldtlbParams = coreParams.ldtlbParameters 615 val sttlbParams = coreParams.sttlbParameters 616 val hytlbParams = coreParams.hytlbParameters 617 val pftlbParams = coreParams.pftlbParameters 618 val btlbParams = coreParams.btlbParameters 619 val l2tlbParams = coreParams.l2tlbParameters 620 val NumPerfCounters = coreParams.NumPerfCounters 621 622 val instBytes = if (HasCExtension) 2 else 4 623 val instOffsetBits = log2Ceil(instBytes) 624 625 val icacheParameters = coreParams.icacheParameters 626 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 627 628 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 629 // for constrained LR/SC loop 630 val LRSCCycles = 64 631 // for lr storm 632 val LRSCBackOff = 8 633 634 // cache hierarchy configurations 635 val l1BusDataWidth = 256 636 637 // load violation predict 638 val ResetTimeMax2Pow = 20 //1078576 639 val ResetTimeMin2Pow = 10 //1024 640 // wait table parameters 641 val WaitTableSize = 1024 642 val MemPredPCWidth = log2Up(WaitTableSize) 643 val LWTUse2BitCounter = true 644 // store set parameters 645 val SSITSize = WaitTableSize 646 val LFSTSize = 32 647 val SSIDWidth = log2Up(LFSTSize) 648 val LFSTWidth = 4 649 val StoreSetEnable = true // LWT will be disabled if SS is enabled 650 val LFSTEnable = false 651 652 val PCntIncrStep: Int = 6 653 val numPCntHc: Int = 25 654 val numPCntPtw: Int = 19 655 656 val numCSRPCntFrontend = 8 657 val numCSRPCntCtrl = 8 658 val numCSRPCntLsu = 8 659 val numCSRPCntHc = 5 660 661 // Parameters for Sdtrig extension 662 protected val TriggerNum = 4 663 protected val TriggerChainMaxLength = 2 664} 665