| #
fda42022 |
| 01-Jul-2020 |
zhanglinjuan <[email protected]> |
add bpu update signals in redirect bundle
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| #
97cfa7f8 |
| 30-Jun-2020 |
LinJiawei <[email protected]> |
Brq: connect to roq
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| #
08cfb13c |
| 28-Jun-2020 |
Yinan Xu <[email protected]> |
Merge pull request #63 from RISCVERS/dev-temp-lsu
Lsu: add sbuffer to naive Lsu
|
| #
4e1a70f6 |
| 28-Jun-2020 |
William Wang <[email protected]> |
Lsu: add sbuffer to naive Lsu
|
| #
e4698824 |
| 28-Jun-2020 |
zoujr <[email protected]> |
Ibuffer: Fixed PC address error
|
| #
f04ed0d5 |
| 27-Jun-2020 |
ljw <[email protected]> |
Revert "Ibuf"
|
| #
16e27c9a |
| 27-Jun-2020 |
William Wang <[email protected]> |
Merge pull request #53 from RISCVERS/fix-rename-bug
Fix rename bug
|
| #
0851457f |
| 27-Jun-2020 |
LinJiawei <[email protected]> |
Rename: map arch reg to phy reg 0-31 initially
|
| #
95f23fe5 |
| 26-Jun-2020 |
Your Name <[email protected]> |
Ibuffer.scala
Add some XSDebug
Modified mask interface and enqueue
|
| #
72235fa4 |
| 24-Jun-2020 |
William Wang <[email protected]> |
difftest: set up nemu difftest framework
|
| #
e402d94e |
| 23-Jun-2020 |
William Wang <[email protected]> |
Lsu: insert naive Lsu into pipeline
|
| #
5b821d1c |
| 23-Jun-2020 |
William Wang <[email protected]> |
Merge branch 'master' into dev-xs-execution
|
| #
056d0086 |
| 22-Jun-2020 |
LinJiawei <[email protected]> |
FreeList: use an additional bit to check freelist empty
|
| #
dc5a3a16 |
| 22-Jun-2020 |
William Wang <[email protected]> |
Merge branch 'master' into dev-xs-execution
|
| #
c898bc97 |
| 22-Jun-2020 |
William Wang <[email protected]> |
Roq: add a "just enough" Roq
|
| #
7bc1a6e4 |
| 21-Jun-2020 |
ZhangZifei <[email protected]> |
Merge branch 'master' into alu
|
| #
cc4cad5e |
| 21-Jun-2020 |
ZhangZifei <[email protected]> |
Exu/Alu: add ALU && pass ALU/BRU.bjRes to Brq through exuRedirect
1. add ALU(almost copy from Noop.ALU)
remove jal/jalr/ret/call from ALU
remove predictWrong from ALU(judged by brq now)
rem
Exu/Alu: add ALU && pass ALU/BRU.bjRes to Brq through exuRedirect
1. add ALU(almost copy from Noop.ALU)
remove jal/jalr/ret/call from ALU
remove predictWrong from ALU(judged by brq now)
remove bpuUpdateReq from ALU
2. add Redirect to ExuOutput
it is connected to brq
show more ...
|
| #
c3174e61 |
| 21-Jun-2020 |
ZhangZifei <[email protected]> |
fix(EXUIO.redirect): remove ExuInput.redirect to ExuIO.redirect
1. remove ExuInput.redirect to ExuIO.redirect for input redirect
don't need waiting for function unit's in.valid.
2. remove ExuOutput.
fix(EXUIO.redirect): remove ExuInput.redirect to ExuIO.redirect
1. remove ExuInput.redirect to ExuIO.redirect for input redirect
don't need waiting for function unit's in.valid.
2. remove ExuOutput.redirect for redirect is only generate by brq
and roq. ALU/BRU.bj instr only need generate target and send to
brq.
show more ...
|
| #
57c4f8d6 |
| 20-Jun-2020 |
LinJiawei <[email protected]> |
Rename: send phy-reg status(rdy/busy) to dispatch-2
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| #
c2430064 |
| 20-Jun-2020 |
ZhangZifei <[email protected]> |
Bundle/ExuIO: add redirect to ExuInput and ExuOutput
ExuInput is used to flush the function unit itself.
ExuOutput is used to flush other function units.
Just ROB, bru(can exec jal/jalr/csr in
Bundle/ExuIO: add redirect to ExuInput and ExuOutput
ExuInput is used to flush the function unit itself.
ExuOutput is used to flush other function units.
Just ROB, bru(can exec jal/jalr/csr instrs) and alu(can exec
branch instrs) can generate redirect.
show more ...
|
| #
54658d36 |
| 20-Jun-2020 |
LinJiawei <[email protected]> |
xiangshan/Bundle: add freelist alloc ptr in MicroOp
|
| #
db34a189 |
| 20-Jun-2020 |
LinJiawei <[email protected]> |
xiangshan/Bundle: update exu io
|
| #
37fcf7fb |
| 20-Jun-2020 |
LinJiawei <[email protected]> |
Bundle: Add 'isException' in Redirect
|
| #
296e7422 |
| 19-Jun-2020 |
LinJiawei <[email protected]> |
Add roq walk signal. Fix issue queue bypass logic.
|
| #
9a2e6b8a |
| 18-Jun-2020 |
LinJiawei <[email protected]> |
Adjust pipeline, refactor EXU, IssueQueue
|