xref: /XiangShan/src/main/scala/xiangshan/Bundle.scala (revision 57c4f8d6c40b210d99a6e8c1f324345547eb16db) 
1package xiangshan
2
3import chisel3._
4import chisel3.util._
5
6// Fetch FetchWidth x 32-bit insts from Icache
7class FetchPacket extends XSBundle {
8  val instrs = Vec(FetchWidth, UInt(32.W))
9  val mask = UInt(FetchWidth.W)
10  val pc = UInt(VAddrBits.W) // the pc of first inst in the fetch group
11}
12
13// Dequeue DecodeWidth insts from Ibuffer
14class CtrlFlow extends XSBundle {
15  val instr = UInt(32.W)
16  val pc = UInt(VAddrBits.W)
17  val exceptionVec = Vec(16, Bool())
18  val intrVec = Vec(12, Bool())
19  val isRVC = Bool()
20  val isBr = Bool()
21}
22
23// Decode DecodeWidth insts at Decode Stage
24class CtrlSignals extends XSBundle {
25  val src1Type, src2Type, src3Type = SrcType()
26  val lsrc1, lsrc2, lsrc3 = UInt(5.W)
27  val ldest = UInt(5.W)
28  val fuType = FuType()
29  val fuOpType = FuOpType()
30  val rfWen = Bool()
31  val fpWen = Bool()
32  val isXSTrap = Bool()
33  val noSpecExec = Bool()  // This inst can not be speculated
34  val isBlocked  = Bool()  // This inst requires pipeline to be blocked
35  val isRVF = Bool()
36  val imm = UInt(XLEN.W)
37}
38
39class CfCtrl extends XSBundle {
40  val cf = new CtrlFlow
41  val ctrl = new CtrlSignals
42  val brMask = UInt(BrqSize.W)
43  val brTag = UInt(BrTagWidth.W)
44}
45
46// CfCtrl -> MicroOp at Rename Stage
47class MicroOp extends CfCtrl {
48
49  val psrc1, psrc2, psrc3, pdest, old_pdest = UInt(PhyRegIdxWidth.W)
50  val src1State, src2State, src3State = SrcState()
51  val freelistAllocPtr = UInt(PhyRegIdxWidth.W)
52  val roqIdx = UInt(RoqIdxWidth.W)
53}
54
55class Redirect extends XSBundle {
56  val target = UInt(VAddrBits.W)
57  val brTag = UInt(BrTagWidth.W)
58  val isException = Bool()
59  val roqIdx = UInt(RoqIdxWidth.W)
60  val freelistAllocPtr = UInt(PhyRegIdxWidth.W)
61}
62
63class Dp1ToDp2IO extends XSBundle {
64  val intDqToDp2 = Vec(IntDqDeqWidth, DecoupledIO(new MicroOp))
65  val fpDqToDp2 = Vec(FpDqDeqWidth, DecoupledIO(new MicroOp))
66  val lsDqToDp2 = Vec(LsDqDeqWidth, DecoupledIO(new MicroOp))
67}
68
69
70class ExuInput extends XSBundle {
71  val uop = new MicroOp
72  val redirect = new Redirect
73  val src1, src2, src3 = UInt(XLEN.W)
74}
75
76class ExuOutput extends XSBundle {
77  val uop = new MicroOp
78  val redirect = new Redirect
79  val data = UInt(XLEN.W)
80}
81
82class ExuIO extends XSBundle {
83  val in = Flipped(DecoupledIO(new ExuInput))
84  val out = DecoupledIO(new ExuOutput)
85}
86
87class RoqCommit extends XSBundle {
88  val uop = new MicroOp
89  val isWalk = Bool()
90}
91
92class FrontendToBackendIO extends XSBundle {
93  // to backend end
94  val cfVec = Vec(DecodeWidth, DecoupledIO(new CtrlFlow))
95  // from backend
96  val redirect = Flipped(ValidIO(new Redirect))
97  val commits = Vec(CommitWidth, Flipped(ValidIO(new RoqCommit))) // update branch pred
98}