xref: /XiangShan/src/main/scala/xiangshan/Bundle.scala (revision 9a2e6b8ae06ed24bb317fa76e397982fa714877b) 
1package xiangshan
2
3import chisel3._
4import chisel3.util._
5
6// Fetch FetchWidth x 32-bit insts from Icache
7class FetchPacket extends XSBundle {
8  val instrs = Vec(FetchWidth, UInt(32.W))
9  val mask = UInt(FetchWidth.W)
10  val pc = UInt(VAddrBits.W) // the pc of first inst in the fetch group
11}
12
13// Dequeue DecodeWidth insts from Ibuffer
14class CtrlFlow extends XSBundle {
15  val instr = UInt(32.W)
16  val pc = UInt(VAddrBits.W)
17  val exceptionVec = Vec(16, Bool())
18  val intrVec = Vec(12, Bool())
19  val isRVC = Bool()
20  val isBr = Bool()
21}
22
23// Decode DecodeWidth insts at Decode Stage
24class CtrlSignals extends XSBundle {
25  val src1Type, src2Type, src3Type = SrcType()
26  val lsrc1, lsrc2, lsrc3 = UInt(5.W)
27  val ldest = UInt(5.W)
28  val fuType = FuType()
29  val fuOpType = FuOpType()
30  val rfWen = Bool()
31  val fpWen = Bool()
32  val isXSTrap = Bool()
33  val noSpecExec = Bool()  // This inst can not be speculated
34  val isBlocked  = Bool()  // This inst requires pipeline to be blocked
35}
36
37class CfCtrl extends XSBundle {
38  val cf = new CtrlFlow
39  val ctrl = new CtrlSignals
40  val brMask = UInt(BrqSize.W)
41  val brTag = UInt(BrTagWidth.W)
42}
43
44// CfCtrl -> MicroOp at Rename Stage
45class MicroOp extends CfCtrl {
46
47  val psrc1, psrc2, psrc3, pdest, old_pdest = UInt(PhyRegIdxWidth.W)
48  val src1State, src2State, src3State = SrcState()
49
50  val roqIdx = UInt(RoqIdxWidth.W)
51}
52
53class Redirect extends XSBundle {
54  val target = UInt(VAddrBits.W)
55  val brTag = UInt(BrTagWidth.W)
56}
57
58class Dp1ToDp2IO extends XSBundle {
59  val intDqToDp2 = Vec(IntDqDeqWidth, DecoupledIO(new MicroOp))
60  val fpDqToDp2 = Vec(FpDqDeqWidth, DecoupledIO(new MicroOp))
61  val lsDqToDp2 = Vec(LsDqDeqWidth, DecoupledIO(new MicroOp))
62}
63
64
65class ExuInput extends XSBundle {
66  val uop = new MicroOp
67  val src1, src2, src3 = UInt(XLEN.W)
68  val isRVF = Bool()
69}
70
71class ExuOutput extends XSBundle {
72  val uop = new MicroOp
73  val data = UInt(XLEN.W)
74}
75
76class ExuIO extends XSBundle {
77  val in = Flipped(DecoupledIO(new ExuInput))
78  val out = DecoupledIO(new ExuOutput)
79}
80
81class RoqCommit extends XSBundle {
82  val uop = new MicroOp
83}
84
85class FrontendToBackendIO extends XSBundle {
86  // to backend end
87  val cfVec = Vec(DecodeWidth, DecoupledIO(new CtrlFlow))
88  // from backend
89  val redirect = Flipped(ValidIO(new Redirect))
90  val commits = Vec(CommitWidth, Flipped(ValidIO(new RoqCommit))) // update branch pred
91}