1package xiangshan 2 3import chisel3._ 4import chisel3.util._ 5import bus.simplebus._ 6import xiangshan.backend.rename.FreeListPtr 7 8// Fetch FetchWidth x 32-bit insts from Icache 9class FetchPacket extends XSBundle { 10 val instrs = Vec(FetchWidth, UInt(32.W)) 11 val mask = UInt((FetchWidth*2).W) 12 val pc = UInt(VAddrBits.W) // the pc of first inst in the fetch group 13 val pnpc = Vec(FetchWidth, UInt(VAddrBits.W)) 14} 15 16// Dequeue DecodeWidth insts from Ibuffer 17class CtrlFlow extends XSBundle { 18 val instr = UInt(32.W) 19 val pc = UInt(VAddrBits.W) 20 val pnpc = UInt(VAddrBits.W) 21 val exceptionVec = Vec(16, Bool()) 22 val intrVec = Vec(12, Bool()) 23 val isRVC = Bool() 24 val isBr = Bool() 25} 26 27// Decode DecodeWidth insts at Decode Stage 28class CtrlSignals extends XSBundle { 29 val src1Type, src2Type, src3Type = SrcType() 30 val lsrc1, lsrc2, lsrc3 = UInt(5.W) 31 val ldest = UInt(5.W) 32 val fuType = FuType() 33 val fuOpType = FuOpType() 34 val rfWen = Bool() 35 val fpWen = Bool() 36 val isXSTrap = Bool() 37 val noSpecExec = Bool() // This inst can not be speculated 38 val isBlocked = Bool() // This inst requires pipeline to be blocked 39 val isRVF = Bool() 40 val imm = UInt(XLEN.W) 41} 42 43class CfCtrl extends XSBundle { 44 val cf = new CtrlFlow 45 val ctrl = new CtrlSignals 46 val brMask = UInt(BrqSize.W) 47 val brTag = UInt(BrTagWidth.W) 48} 49 50// CfCtrl -> MicroOp at Rename Stage 51class MicroOp extends CfCtrl { 52 53 val psrc1, psrc2, psrc3, pdest, old_pdest = UInt(PhyRegIdxWidth.W) 54 val src1State, src2State, src3State = SrcState() 55 val freelistAllocPtr = new FreeListPtr 56 val roqIdx = UInt(RoqIdxWidth.W) 57} 58 59class Redirect extends XSBundle { 60 val pc = UInt(VAddrBits.W) // wrongly predicted pc 61 val target = UInt(VAddrBits.W) 62 val brTag = UInt(BrTagWidth.W) 63 val _type = UInt(2.W) 64 val taken = Bool() 65 val isException = Bool() 66 val roqIdx = UInt(ExtendedRoqIdxWidth.W) 67 val freelistAllocPtr = new FreeListPtr 68} 69 70// class BpuUpdateReq extends XSBundle { 71 // val pc = UInt(VAddrBits.W) 72 // val isMissPred = Bool() 73 // val _type = UInt(2.W) 74 // val actualTarget = UInt(VAddrBits.W) 75 // val actualTaken = Bool() 76 // val redirect = new Redirect 77 // TODO: 78 // val isRVC = Bool() 79//} 80 81class Dp1ToDp2IO extends XSBundle { 82 val intDqToDp2 = Vec(IntDqDeqWidth, DecoupledIO(new MicroOp)) 83 val fpDqToDp2 = Vec(FpDqDeqWidth, DecoupledIO(new MicroOp)) 84 val lsDqToDp2 = Vec(LsDqDeqWidth, DecoupledIO(new MicroOp)) 85} 86 87class DebugBundle extends XSBundle{ 88 val isMMIO = Bool() 89} 90 91class ExuInput extends XSBundle { 92 val uop = new MicroOp 93 val src1, src2, src3 = UInt(XLEN.W) 94} 95 96class ExuOutput extends XSBundle { 97 val uop = new MicroOp 98 val data = UInt(XLEN.W) 99 val redirect = Valid(new Redirect) 100 val debug = new DebugBundle 101} 102 103class ExuIO extends XSBundle { 104 val in = Flipped(DecoupledIO(new ExuInput)) 105 val redirect = Flipped(ValidIO(new Redirect)) 106 val out = DecoupledIO(new ExuOutput) 107 108 // for Lsu 109 val dmem = new SimpleBusUC 110 val scommit = Input(UInt(3.W)) 111} 112 113class RoqCommit extends XSBundle { 114 val uop = new MicroOp 115 val isWalk = Bool() 116} 117 118class FrontendToBackendIO extends XSBundle { 119 // to backend end 120 val cfVec = Vec(DecodeWidth, DecoupledIO(new CtrlFlow)) 121 // from backend 122 val redirect = Flipped(ValidIO(new Redirect)) 123 val commits = Vec(CommitWidth, Flipped(ValidIO(new RoqCommit))) // update branch pred 124} 125