| /linux-6.14.4/drivers/clk/ |
| D | clk_test.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Kunit tests for clk framework
5 #include <linux/clk.h>
6 #include <linux/clk-provider.h>
7 #include <linux/clk/clk-conf.h>
12 #include "clk.h"
14 #include <kunit/clk.h>
39 return ctx->rate; in clk_dummy_recalc_rate()
56 if (req->max_rate < ULONG_MAX) in clk_dummy_maximize_rate()
57 req->rate = req->max_rate; in clk_dummy_maximize_rate()
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| D | clk-gate_test.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Kunit tests for clk gate
5 #include <linux/clk.h>
6 #include <linux/clk-provider.h>
16 pdev = platform_device_register_simple("test_gate_device", -1, NULL, 0); in clk_gate_register_test_dev()
19 ret = clk_hw_register_gate(&pdev->dev, "test_gate", NULL, 0, NULL, in clk_gate_register_test_dev()
31 struct clk_hw *parent; in clk_gate_register_test_parent_names() local
34 parent = clk_hw_register_fixed_rate(NULL, "test_parent", NULL, 0, in clk_gate_register_test_parent_names()
36 KUNIT_ASSERT_NOT_ERR_OR_NULL(test, parent); in clk_gate_register_test_parent_names()
41 KUNIT_EXPECT_PTR_EQ(test, parent, clk_hw_get_parent(ret)); in clk_gate_register_test_parent_names()
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| D | clk.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2010-2011 Canonical Ltd <[email protected]>
4 * Copyright (C) 2011-2012 Linaro Ltd <[email protected]>
6 * Standard functionality for the common clock API. See Documentation/driver-api/clk.rst
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
11 #include <linux/clk/clk-conf.h>
25 #include "clk.h"
68 struct clk_core *parent; member
100 #include <trace/events/clk.h>
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| D | clk-fixed-rate_test.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * KUnit test for clk fixed rate basic type
5 #include <linux/clk.h>
6 #include <linux/clk-provider.h>
11 #include <kunit/clk.h>
17 #include "clk-fixed-rate_test.h"
20 * struct clk_hw_fixed_rate_kunit_params - Parameters to pass to __clk_hw_register_fixed_rate()
21 * @dev: device registering clk
22 * @np: device_node of device registering clk
23 * @name: name of clk
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| D | clk-gpio.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2013 - 2014 Texas Instruments Incorporated - https://www.ti.com
12 #include <linux/clk-provider.h>
26 * prepare - clk_(un)prepare are functional and control a gpio that can sleep
27 * enable - clk_enable and clk_disable are functional & control
28 * non-sleeping gpio
29 * rate - inherits rate from parent. No clk_set_rate support
30 * parent - fixed parent. No clk_set_parent support
34 * struct clk_gpio - gpio gated clock
36 * @hw: handle between common and hardware-specific interfaces
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| /linux-6.14.4/drivers/sh/clk/ |
| D | core.c | 4 * Copyright (C) 2005 - 2010 Paul Mundt
8 * Copyright (C) 2004 - 2008 Nokia Corporation
29 #include <linux/clk.h>
39 void clk_rate_table_build(struct clk *clk, in clk_rate_table_build() argument
49 clk->nr_freqs = nr_freqs; in clk_rate_table_build()
55 if (src_table->divisors && i < src_table->nr_divisors) in clk_rate_table_build()
56 div = src_table->divisors[i]; in clk_rate_table_build()
58 if (src_table->multipliers && i < src_table->nr_multipliers) in clk_rate_table_build()
59 mult = src_table->multipliers[i]; in clk_rate_table_build()
64 freq = clk->parent->rate * mult / div; in clk_rate_table_build()
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| D | cpg.c | 5 * Copyright (C) 2010 - 2012 Paul Mundt
11 #include <linux/clk.h>
19 static unsigned int sh_clk_read(struct clk *clk) in sh_clk_read() argument
21 if (clk->flags & CLK_ENABLE_REG_8BIT) in sh_clk_read()
22 return ioread8(clk->mapped_reg); in sh_clk_read()
23 else if (clk->flags & CLK_ENABLE_REG_16BIT) in sh_clk_read()
24 return ioread16(clk->mapped_reg); in sh_clk_read()
26 return ioread32(clk->mapped_reg); in sh_clk_read()
29 static void sh_clk_write(int value, struct clk *clk) in sh_clk_write() argument
31 if (clk->flags & CLK_ENABLE_REG_8BIT) in sh_clk_write()
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| /linux-6.14.4/drivers/clk/tegra/ |
| D | clk-tegra210-emc.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved.
7 #include <linux/clk.h>
8 #include <linux/clk-provider.h>
9 #include <linux/clk/tegra.h>
15 #include "clk.h"
37 struct clk *parents[8];
57 value = readl_relaxed(emc->regs + CLK_SOURCE_EMC); in tegra210_clk_emc_get_parent()
70 * CCF assumes that neither the parent nor its rate will change during in tegra210_clk_emc_recalc_rate()
71 * ->set_rate(), so the parent rate passed in here was cached from the in tegra210_clk_emc_recalc_rate()
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| D | clk-tegra124-emc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/clk/tegra/clk-emc.c
11 #include <linux/clk-provider.h>
12 #include <linux/clk.h>
14 #include <linux/clk/tegra.h>
27 #include "clk.h"
48 * When we change the timing to a timing with a parent that has the same
49 * clock source as the current parent, we must first change to a backup
68 struct clk *parent; member
75 struct clk *prev_parent;
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| /linux-6.14.4/drivers/clk/imx/ |
| D | clk-scu.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2021 NXP
7 #include <dt-bindings/firmware/imx/rsrc.h>
8 #include <linux/arm-smccc.h>
10 #include <linux/clk-provider.h>
20 #include "clk-scu.h"
44 * struct clk_scu - Description of one SCU clock
55 struct clk_hw *parent; member
62 * struct clk_gpr_scu - Description of one SCU GPR clock
78 * struct imx_sc_msg_req_set_clock_rate - clock set rate protocol
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| /linux-6.14.4/drivers/clk/ti/ |
| D | dpll3xxx.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * OMAP3/4 - specific DPLL control functions
5 * Copyright (C) 2009-2010 Texas Instruments, Inc.
6 * Copyright (C) 2009-2010 Nokia Corporation
23 #include <linux/clk.h>
27 #include <linux/clk/ti.h>
40 static u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk);
41 static void omap3_dpll_deny_idle(struct clk_hw_omap *clk);
42 static void omap3_dpll_allow_idle(struct clk_hw_omap *clk);
46 /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
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| D | gate.c | 1 // SPDX-License-Identifier: GPL-2.0-only
7 * Tero Kristo <t-[email protected]>
10 #include <linux/clk-provider.h>
15 #include <linux/clk/ti.h>
22 static int omap36xx_gate_clk_enable_with_hsdiv_restore(struct clk_hw *clk);
48 * omap36xx_gate_clk_enable_with_hsdiv_restore - enable clocks suffering
60 struct clk_omap_divider *parent; in omap36xx_gate_clk_enable_with_hsdiv_restore() local
68 /* Parent is the x2 node, get parent of parent for the m2 div */ in omap36xx_gate_clk_enable_with_hsdiv_restore()
70 parent = to_clk_omap_divider(parent_hw); in omap36xx_gate_clk_enable_with_hsdiv_restore()
74 orig_v = ti_clk_ll_ops->clk_readl(&parent->reg); in omap36xx_gate_clk_enable_with_hsdiv_restore()
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| D | clk.c | 1 // SPDX-License-Identifier: GPL-2.0-only
7 * Tero Kristo <t-[email protected]>
11 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
14 #include <linux/clk/ti.h>
45 struct clk_iomap *io = clk_memmaps[reg->index]; in clk_memmap_writel()
47 if (reg->ptr) in clk_memmap_writel()
48 writel_relaxed(val, reg->ptr); in clk_memmap_writel()
49 else if (io->regmap) in clk_memmap_writel()
50 regmap_write(io->regmap, reg->offset, val); in clk_memmap_writel()
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| /linux-6.14.4/drivers/clk/sunxi/ |
| D | clk-sun9i-cpus.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2015 Chen-Yu Tsai
5 * Chen-Yu Tsai <[email protected]>
11 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
57 reg = readl(cpus->reg); in sun9i_a80_cpus_clk_recalc_rate()
59 /* apply pre-divider first if parent is pll4 */ in sun9i_a80_cpus_clk_recalc_rate()
63 /* clk divider */ in sun9i_a80_cpus_clk_recalc_rate()
70 u8 parent, unsigned long parent_rate) in sun9i_a80_cpus_clk_round() argument
76 * frequencies higher than the parent frequency in sun9i_a80_cpus_clk_round()
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| /linux-6.14.4/drivers/clk/renesas/ |
| D | rcar-gen3-cpg.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car Gen3 Clock Pulse Generator
5 * Copyright (C) 2015-2018 Glider bvba
8 * Based on clk-rcar-gen3.c
15 #include <linux/clk.h>
16 #include <linux/clk-provider.h>
25 #include "renesas-cpg-mssr.h"
26 #include "rcar-cpg-lib.h"
27 #include "rcar-gen3-cpg.h"
59 val = readl(pll_clk->pllcr_reg) & CPG_PLLnCR_STC_MASK; in cpg_pll_clk_recalc_rate()
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| D | rzg2l-cpg.c | 1 // SPDX-License-Identifier: GPL-2.0
7 * Based on renesas-cpg-mssr.c
15 #include <linux/clk.h>
16 #include <linux/clk-provider.h>
17 #include <linux/clk/renesas.h>
28 #include <linux/reset-controller.h>
32 #include <dt-bindings/clock/renesas-cpg-mssr.h>
34 #include "rzg2l-cpg.h"
71 * struct clk_hw_data - clock hardware data
87 * struct sd_mux_hw_data - SD MUX clock hardware data
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| D | rzv2h-cpg.c | 1 // SPDX-License-Identifier: GPL-2.0
7 * Based on rzg2l-cpg.c
15 #include <linux/clk.h>
16 #include <linux/clk-provider.h>
27 #include <linux/reset-controller.h>
29 #include <dt-bindings/clock/renesas-cpg-mssr.h>
31 #include "rzv2h-cpg.h"
45 #define CPG_BUS_MSTOP(m) (CPG_BUS_1_MSTOP + ((m) - 1) * 4)
60 * struct rzv2h_cpg_priv - Clock Pulse Generator Private Data
69 * @num_resets: Number of Module Resets in info->resets[]
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| /linux-6.14.4/include/linux/ |
| D | sh_clk.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
10 #include <linux/clk.h>
13 struct clk;
24 void (*init)(struct clk *clk);
26 int (*enable)(struct clk *clk);
27 void (*disable)(struct clk *clk);
28 unsigned long (*recalc)(struct clk *clk);
29 int (*set_rate)(struct clk *clk, unsigned long rate);
30 int (*set_parent)(struct clk *clk, struct clk *parent);
31 long (*round_rate)(struct clk *clk, unsigned long rate);
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| D | clk-provider.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2010-2011 Jeremy Kerr <[email protected]>
4 * Copyright (C) 2011-2012 Linaro Ltd <[email protected]>
13 * flags used across common struct clk. these flags should only affect the
14 * top-level framework. custom flags for dealing with hardware specifics
17 * Please update clk_flags[] in drivers/clk/clk.c when making changes here!
20 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
25 #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */
26 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
27 #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
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| /linux-6.14.4/drivers/clk/davinci/ |
| D | da8xx-cfgchip.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Clock driver for DA8xx/AM17xx/AM18xx/OMAP-L13x CFGCHIP
8 #include <linux/clk-provider.h>
9 #include <linux/clk.h>
12 #include <linux/mfd/da8xx-cfgchip.h>
15 #include <linux/platform_data/clk-da8xx-cfgchip.h>
21 /* --- Gate clocks --- */
44 struct da8xx_cfgchip_gate_clk *clk = to_da8xx_cfgchip_gate_clk(hw); in da8xx_cfgchip_gate_clk_enable() local
46 return regmap_write_bits(clk->regmap, clk->reg, clk->mask, clk->mask); in da8xx_cfgchip_gate_clk_enable()
51 struct da8xx_cfgchip_gate_clk *clk = to_da8xx_cfgchip_gate_clk(hw); in da8xx_cfgchip_gate_clk_disable() local
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| /linux-6.14.4/drivers/clk/starfive/ |
| D | clk-starfive-jh71x0.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2021-2022 Emil Renner Berthing <[email protected]>
8 #include <linux/clk-provider.h>
13 #include "clk-starfive-jh71x0.h"
20 static struct jh71x0_clk_priv *jh71x0_priv_from(struct jh71x0_clk *clk) in jh71x0_priv_from() argument
22 return container_of(clk, struct jh71x0_clk_priv, reg[clk->idx]); in jh71x0_priv_from()
25 static u32 jh71x0_clk_reg_get(struct jh71x0_clk *clk) in jh71x0_clk_reg_get() argument
27 struct jh71x0_clk_priv *priv = jh71x0_priv_from(clk); in jh71x0_clk_reg_get()
28 void __iomem *reg = priv->base + 4 * clk->idx; in jh71x0_clk_reg_get()
33 static void jh71x0_clk_reg_rmw(struct jh71x0_clk *clk, u32 mask, u32 value) in jh71x0_clk_reg_rmw() argument
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| /linux-6.14.4/arch/sh/kernel/cpu/sh4a/ |
| D | clock-sh7780.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * arch/sh/kernel/cpu/sh4a/clock-sh7780.c
22 static void master_clk_init(struct clk *clk) in master_clk_init() argument
24 clk->rate *= pfc_divisors[__raw_readl(FRQCR) & 0x0003]; in master_clk_init()
31 static unsigned long module_clk_recalc(struct clk *clk) in module_clk_recalc() argument
34 return clk->parent->rate / pfc_divisors[idx]; in module_clk_recalc()
41 static unsigned long bus_clk_recalc(struct clk *clk) in bus_clk_recalc() argument
44 return clk->parent->rate / bfc_divisors[idx]; in bus_clk_recalc()
51 static unsigned long cpu_clk_recalc(struct clk *clk) in cpu_clk_recalc() argument
54 return clk->parent->rate / ifc_divisors[idx]; in cpu_clk_recalc()
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| /linux-6.14.4/drivers/clk/keystone/ |
| D | sci-clk.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/
6 * Tero Kristo <t-[email protected]>
8 #include <linux/clk-provider.h>
24 * struct sci_clk_provider - TI SCI clock provider representation
40 * struct sci_clk - TI SCI clock representation
66 * sci_clk_prepare - Prepare (enable) a TI SCI clock
73 struct sci_clk *clk = to_sci_clk(hw); in sci_clk_prepare() local
74 bool enable_ssc = clk->flags & SCI_CLK_SSC_ENABLE; in sci_clk_prepare()
75 bool allow_freq_change = clk->flags & SCI_CLK_ALLOW_FREQ_CHANGE; in sci_clk_prepare()
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| /linux-6.14.4/arch/arm/boot/dts/nxp/lpc/ |
| D | lpc32xx.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2015-2019 Vladimir Zapolskiy <[email protected]>
9 #include <dt-bindings/clock/lpc32xx-clock.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
13 #address-cells = <1>;
14 #size-cells = <1>;
16 interrupt-parent = <&mic>;
19 #address-cells = <1>;
20 #size-cells = <0>;
23 compatible = "arm,arm926ej-s";
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| /linux-6.14.4/drivers/clk/zynq/ |
| D | pll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk/zynq.h>
10 #include <linux/clk-provider.h>
15 * struct zynq_pll - pll clock
16 * @hw: Handle between common and hardware-specific interfaces
45 * zynq_pll_round_rate() - Round a clock frequency
46 * @hw: Handle between common and hardware-specific interfaces
48 * @prate: Clock frequency of parent clock
66 * zynq_pll_recalc_rate() - Recalculate clock frequency
67 * @hw: Handle between common and hardware-specific interfaces
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