1 // SPDX-License-Identifier: GPL-2.0-only
7  * Tero Kristo <t-[email protected]>
10 #include <linux/clk-provider.h>
15 #include <linux/clk/ti.h>
22 static int omap36xx_gate_clk_enable_with_hsdiv_restore(struct clk_hw *clk);
48  * omap36xx_gate_clk_enable_with_hsdiv_restore - enable clocks suffering
60 	struct clk_omap_divider *parent;  in omap36xx_gate_clk_enable_with_hsdiv_restore()  local
68 	/* Parent is the x2 node, get parent of parent for the m2 div */  in omap36xx_gate_clk_enable_with_hsdiv_restore()
70 	parent = to_clk_omap_divider(parent_hw);  in omap36xx_gate_clk_enable_with_hsdiv_restore()
74 		orig_v = ti_clk_ll_ops->clk_readl(&parent->reg);  in omap36xx_gate_clk_enable_with_hsdiv_restore()
78 		dummy_v ^= (1 << parent->shift);  in omap36xx_gate_clk_enable_with_hsdiv_restore()
79 		ti_clk_ll_ops->clk_writel(dummy_v, &parent->reg);  in omap36xx_gate_clk_enable_with_hsdiv_restore()
82 		ti_clk_ll_ops->clk_writel(orig_v, &parent->reg);  in omap36xx_gate_clk_enable_with_hsdiv_restore()
88 static struct clk *_register_gate(struct device_node *node, const char *name,  in _register_gate()
96 	struct clk *clk;  in _register_gate()  local
100 		return ERR_PTR(-ENOMEM);  in _register_gate()
102 	clk_hw->hw.init = &init;  in _register_gate()
107 	memcpy(&clk_hw->enable_reg, reg, sizeof(*reg));  in _register_gate()
108 	clk_hw->enable_bit = bit_idx;  in _register_gate()
109 	clk_hw->ops = hw_ops;  in _register_gate()
111 	clk_hw->flags = clk_gate_flags;  in _register_gate()
118 	clk = of_ti_clk_register_omap_hw(node, &clk_hw->hw, name);  in _register_gate()
120 	if (IS_ERR(clk))  in _register_gate()
123 	return clk;  in _register_gate()
130 	struct clk *clk;  in _of_ti_gate_clk_setup()  local
146 		pr_err("%pOFn must have 1 parent\n", node);  in _of_ti_gate_clk_setup()
152 	if (of_property_read_bool(node, "ti,set-rate-parent"))  in _of_ti_gate_clk_setup()
155 	if (of_property_read_bool(node, "ti,set-bit-to-disable"))  in _of_ti_gate_clk_setup()
159 	clk = _register_gate(node, name, parent_name, flags, &reg,  in _of_ti_gate_clk_setup()
162 	if (!IS_ERR(clk))  in _of_ti_gate_clk_setup()
163 		of_clk_add_provider(node, of_clk_src_simple_get, clk);  in _of_ti_gate_clk_setup()
176 	if (ti_clk_get_reg_addr(node, 0, &gate->enable_reg))  in _of_ti_composite_gate_clk_setup()
179 	gate->enable_bit = gate->enable_reg.bit;  in _of_ti_composite_gate_clk_setup()
180 	gate->ops = hw_ops;  in _of_ti_composite_gate_clk_setup()
182 	if (!ti_clk_add_component(node, &gate->hw, CLK_COMPONENT_TYPE_GATE))  in _of_ti_composite_gate_clk_setup()
194 CLK_OF_DECLARE(ti_composite_no_wait_gate_clk, "ti,composite-no-wait-gate-clock",
202 CLK_OF_DECLARE(ti_composite_interface_clk, "ti,composite-interface-clock",
210 CLK_OF_DECLARE(ti_composite_gate_clk, "ti,composite-gate-clock",
218 CLK_OF_DECLARE(ti_clkdm_gate_clk, "ti,clkdm-gate-clock",
226 CLK_OF_DECLARE(ti_hsdiv_gate_clk, "ti,hsdiv-gate-clock",
233 CLK_OF_DECLARE(ti_gate_clk, "ti,gate-clock", of_ti_gate_clk_setup);
239 CLK_OF_DECLARE(ti_wait_gate_clk, "ti,wait-gate-clock",
248 CLK_OF_DECLARE(ti_am35xx_gate_clk, "ti,am35xx-gate-clock",
256 CLK_OF_DECLARE(ti_dss_gate_clk, "ti,dss-gate-clock",