1 // SPDX-License-Identifier: GPL-2.0
7  * Based on rzg2l-cpg.c
15 #include <linux/clk.h>
16 #include <linux/clk-provider.h>
27 #include <linux/reset-controller.h>
29 #include <dt-bindings/clock/renesas-cpg-mssr.h>
31 #include "rzv2h-cpg.h"
45 #define CPG_BUS_MSTOP(m)	(CPG_BUS_1_MSTOP + ((m) - 1) * 4)
60  * struct rzv2h_cpg_priv - Clock Pulse Generator Private Data
69  * @num_resets: Number of Module Resets in info->resets[]
79 	struct clk **clks;
104  * struct mod_clock - Module clock
108  * @hw: handle between common and hardware-specific interfaces
129  * struct ddiv_clk - DDIV clock
132  * @div: divider clk
147 	struct rzv2h_cpg_priv *priv = pll_clk->priv;  in rzv2h_cpg_pll_clk_recalc_rate()
151 	if (!PLL_CLK_ACCESS(pll_clk->conf))  in rzv2h_cpg_pll_clk_recalc_rate()
154 	clk1 = readl(priv->base + PLL_CLK1_OFFSET(pll_clk->conf));  in rzv2h_cpg_pll_clk_recalc_rate()
155 	clk2 = readl(priv->base + PLL_CLK2_OFFSET(pll_clk->conf));  in rzv2h_cpg_pll_clk_recalc_rate()
167 static struct clk * __init
172 	void __iomem *base = priv->base;  in rzv2h_cpg_pll_clk_register()
173 	struct device *dev = priv->dev;  in rzv2h_cpg_pll_clk_register()
175 	const struct clk *parent;  in rzv2h_cpg_pll_clk_register()  local
180 	parent = priv->clks[core->parent];  in rzv2h_cpg_pll_clk_register()
181 	if (IS_ERR(parent))  in rzv2h_cpg_pll_clk_register()
182 		return ERR_CAST(parent);  in rzv2h_cpg_pll_clk_register()
186 		return ERR_PTR(-ENOMEM);  in rzv2h_cpg_pll_clk_register()
188 	parent_name = __clk_get_name(parent);  in rzv2h_cpg_pll_clk_register()
189 	init.name = core->name;  in rzv2h_cpg_pll_clk_register()
195 	pll_clk->hw.init = &init;  in rzv2h_cpg_pll_clk_register()
196 	pll_clk->conf = core->cfg.conf;  in rzv2h_cpg_pll_clk_register()
197 	pll_clk->base = base;  in rzv2h_cpg_pll_clk_register()
198 	pll_clk->priv = priv;  in rzv2h_cpg_pll_clk_register()
199 	pll_clk->type = core->type;  in rzv2h_cpg_pll_clk_register()
201 	ret = devm_clk_hw_register(dev, &pll_clk->hw);  in rzv2h_cpg_pll_clk_register()
205 	return pll_clk->hw.clk;  in rzv2h_cpg_pll_clk_register()
214 	val = readl(divider->reg) >> divider->shift;  in rzv2h_ddiv_recalc_rate()
215 	val &= clk_div_mask(divider->width);  in rzv2h_ddiv_recalc_rate()
217 	return divider_recalc_rate(hw, parent_rate, val, divider->table,  in rzv2h_ddiv_recalc_rate()
218 				   divider->flags, divider->width);  in rzv2h_ddiv_recalc_rate()
226 	return divider_round_rate(hw, rate, prate, divider->table,  in rzv2h_ddiv_round_rate()
227 				  divider->width, divider->flags);  in rzv2h_ddiv_round_rate()
235 	return divider_determine_rate(hw, req, divider->table, divider->width,  in rzv2h_ddiv_determine_rate()
236 				      divider->flags);  in rzv2h_ddiv_determine_rate()
252 	struct rzv2h_cpg_priv *priv = ddiv->priv;  in rzv2h_ddiv_set_rate()
258 	value = divider_get_val(rate, parent_rate, divider->table,  in rzv2h_ddiv_set_rate()
259 				divider->width, divider->flags);  in rzv2h_ddiv_set_rate()
263 	spin_lock_irqsave(divider->lock, flags);  in rzv2h_ddiv_set_rate()
265 	ret = rzv2h_cpg_wait_ddiv_clk_update_done(priv->base, ddiv->mon);  in rzv2h_ddiv_set_rate()
269 	val = readl(divider->reg) | DDIV_DIVCTL_WEN(divider->shift);  in rzv2h_ddiv_set_rate()
270 	val &= ~(clk_div_mask(divider->width) << divider->shift);  in rzv2h_ddiv_set_rate()
271 	val |= (u32)value << divider->shift;  in rzv2h_ddiv_set_rate()
272 	writel(val, divider->reg);  in rzv2h_ddiv_set_rate()
274 	ret = rzv2h_cpg_wait_ddiv_clk_update_done(priv->base, ddiv->mon);  in rzv2h_ddiv_set_rate()
278 	spin_unlock_irqrestore(divider->lock, flags);  in rzv2h_ddiv_set_rate()
283 	spin_unlock_irqrestore(divider->lock, flags);  in rzv2h_ddiv_set_rate()
294 static struct clk * __init
298 	struct ddiv cfg_ddiv = core->cfg.ddiv;  in rzv2h_cpg_ddiv_clk_register()
300 	struct device *dev = priv->dev;  in rzv2h_cpg_ddiv_clk_register()
303 	const struct clk *parent;  in rzv2h_cpg_ddiv_clk_register()  local
309 	parent = priv->clks[core->parent];  in rzv2h_cpg_ddiv_clk_register()
310 	if (IS_ERR(parent))  in rzv2h_cpg_ddiv_clk_register()
311 		return ERR_CAST(parent);  in rzv2h_cpg_ddiv_clk_register()
313 	parent_name = __clk_get_name(parent);  in rzv2h_cpg_ddiv_clk_register()
316 		return ERR_PTR(-EINVAL);  in rzv2h_cpg_ddiv_clk_register()
318 	ddiv = devm_kzalloc(priv->dev, sizeof(*ddiv), GFP_KERNEL);  in rzv2h_cpg_ddiv_clk_register()
320 		return ERR_PTR(-ENOMEM);  in rzv2h_cpg_ddiv_clk_register()
322 	init.name = core->name;  in rzv2h_cpg_ddiv_clk_register()
327 	ddiv->priv = priv;  in rzv2h_cpg_ddiv_clk_register()
328 	ddiv->mon = cfg_ddiv.monbit;  in rzv2h_cpg_ddiv_clk_register()
329 	div = &ddiv->div;  in rzv2h_cpg_ddiv_clk_register()
330 	div->reg = priv->base + cfg_ddiv.offset;  in rzv2h_cpg_ddiv_clk_register()
331 	div->shift = shift;  in rzv2h_cpg_ddiv_clk_register()
332 	div->width = width;  in rzv2h_cpg_ddiv_clk_register()
333 	div->flags = core->flag;  in rzv2h_cpg_ddiv_clk_register()
334 	div->lock = &priv->rmw_lock;  in rzv2h_cpg_ddiv_clk_register()
335 	div->hw.init = &init;  in rzv2h_cpg_ddiv_clk_register()
336 	div->table = core->dtable;  in rzv2h_cpg_ddiv_clk_register()
338 	ret = devm_clk_hw_register(dev, &div->hw);  in rzv2h_cpg_ddiv_clk_register()
342 	return div->hw.clk;  in rzv2h_cpg_ddiv_clk_register()
345 static struct clk
349 	unsigned int clkidx = clkspec->args[1];  in rzv2h_cpg_clk_src_twocell_get()
351 	struct device *dev = priv->dev;  in rzv2h_cpg_clk_src_twocell_get()
353 	struct clk *clk;  in rzv2h_cpg_clk_src_twocell_get()  local
355 	switch (clkspec->args[0]) {  in rzv2h_cpg_clk_src_twocell_get()
358 		if (clkidx > priv->last_dt_core_clk) {  in rzv2h_cpg_clk_src_twocell_get()
360 			return ERR_PTR(-EINVAL);  in rzv2h_cpg_clk_src_twocell_get()
362 		clk = priv->clks[clkidx];  in rzv2h_cpg_clk_src_twocell_get()
367 		if (clkidx >= priv->num_mod_clks) {  in rzv2h_cpg_clk_src_twocell_get()
369 			return ERR_PTR(-EINVAL);  in rzv2h_cpg_clk_src_twocell_get()
371 		clk = priv->clks[priv->num_core_clks + clkidx];  in rzv2h_cpg_clk_src_twocell_get()
375 		dev_err(dev, "Invalid CPG clock type %u\n", clkspec->args[0]);  in rzv2h_cpg_clk_src_twocell_get()
376 		return ERR_PTR(-EINVAL);  in rzv2h_cpg_clk_src_twocell_get()
379 	if (IS_ERR(clk))  in rzv2h_cpg_clk_src_twocell_get()
381 			PTR_ERR(clk));  in rzv2h_cpg_clk_src_twocell_get()
384 			clkspec->args[0], clkspec->args[1], clk,  in rzv2h_cpg_clk_src_twocell_get()
385 			clk_get_rate(clk));  in rzv2h_cpg_clk_src_twocell_get()
386 	return clk;  in rzv2h_cpg_clk_src_twocell_get()
393 	struct clk *clk = ERR_PTR(-EOPNOTSUPP), *parent;  in rzv2h_cpg_register_core_clk()  local
394 	unsigned int id = core->id, div = core->div;  in rzv2h_cpg_register_core_clk()
395 	struct device *dev = priv->dev;  in rzv2h_cpg_register_core_clk()
399 	WARN_DEBUG(id >= priv->num_core_clks);  in rzv2h_cpg_register_core_clk()
400 	WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);  in rzv2h_cpg_register_core_clk()
402 	switch (core->type) {  in rzv2h_cpg_register_core_clk()
404 		clk = of_clk_get_by_name(priv->dev->of_node, core->name);  in rzv2h_cpg_register_core_clk()
407 		WARN_DEBUG(core->parent >= priv->num_core_clks);  in rzv2h_cpg_register_core_clk()
408 		parent = priv->clks[core->parent];  in rzv2h_cpg_register_core_clk()
409 		if (IS_ERR(parent)) {  in rzv2h_cpg_register_core_clk()
410 			clk = parent;  in rzv2h_cpg_register_core_clk()
414 		parent_name = __clk_get_name(parent);  in rzv2h_cpg_register_core_clk()
415 		clk_hw = devm_clk_hw_register_fixed_factor(dev, core->name,  in rzv2h_cpg_register_core_clk()
417 							   core->mult, div);  in rzv2h_cpg_register_core_clk()
419 			clk = ERR_CAST(clk_hw);  in rzv2h_cpg_register_core_clk()
421 			clk = clk_hw->clk;  in rzv2h_cpg_register_core_clk()
424 		clk = rzv2h_cpg_pll_clk_register(core, priv, &rzv2h_cpg_pll_ops);  in rzv2h_cpg_register_core_clk()
427 		clk = rzv2h_cpg_ddiv_clk_register(core, priv);  in rzv2h_cpg_register_core_clk()
433 	if (IS_ERR_OR_NULL(clk))  in rzv2h_cpg_register_core_clk()
436 	dev_dbg(dev, "Core clock %pC at %lu Hz\n", clk, clk_get_rate(clk));  in rzv2h_cpg_register_core_clk()
437 	priv->clks[id] = clk;  in rzv2h_cpg_register_core_clk()
442 		core->name, PTR_ERR(clk));  in rzv2h_cpg_register_core_clk()
450 	unsigned int index = (mstop_index - 1) * 16;  in rzv2h_mod_clock_mstop_enable()
451 	atomic_t *mstop = &priv->mstop_count[index];  in rzv2h_mod_clock_mstop_enable()
456 	spin_lock_irqsave(&priv->rmw_lock, flags);  in rzv2h_mod_clock_mstop_enable()
463 		writel(val, priv->base + CPG_BUS_MSTOP(mstop_index));  in rzv2h_mod_clock_mstop_enable()
464 	spin_unlock_irqrestore(&priv->rmw_lock, flags);  in rzv2h_mod_clock_mstop_enable()
472 	unsigned int index = (mstop_index - 1) * 16;  in rzv2h_mod_clock_mstop_disable()
473 	atomic_t *mstop = &priv->mstop_count[index];  in rzv2h_mod_clock_mstop_disable()
478 	spin_lock_irqsave(&priv->rmw_lock, flags);  in rzv2h_mod_clock_mstop_disable()
485 		writel(val, priv->base + CPG_BUS_MSTOP(mstop_index));  in rzv2h_mod_clock_mstop_disable()
486 	spin_unlock_irqrestore(&priv->rmw_lock, flags);  in rzv2h_mod_clock_mstop_disable()
492 	struct rzv2h_cpg_priv *priv = clock->priv;  in rzv2h_mod_clock_is_enabled()
496 	if (clock->mon_index >= 0) {  in rzv2h_mod_clock_is_enabled()
497 		offset = GET_CLK_MON_OFFSET(clock->mon_index);  in rzv2h_mod_clock_is_enabled()
498 		bitmask = BIT(clock->mon_bit);  in rzv2h_mod_clock_is_enabled()
500 		offset = GET_CLK_ON_OFFSET(clock->on_index);  in rzv2h_mod_clock_is_enabled()
501 		bitmask = BIT(clock->on_bit);  in rzv2h_mod_clock_is_enabled()
504 	return readl(priv->base + offset) & bitmask;  in rzv2h_mod_clock_is_enabled()
511 	unsigned int reg = GET_CLK_ON_OFFSET(clock->on_index);  in rzv2h_mod_clock_endisable()
512 	struct rzv2h_cpg_priv *priv = clock->priv;  in rzv2h_mod_clock_endisable()
513 	u32 bitmask = BIT(clock->on_bit);  in rzv2h_mod_clock_endisable()
514 	struct device *dev = priv->dev;  in rzv2h_mod_clock_endisable()
518 	dev_dbg(dev, "CLK_ON 0x%x/%pC %s\n", reg, hw->clk,  in rzv2h_mod_clock_endisable()
527 		writel(value, priv->base + reg);  in rzv2h_mod_clock_endisable()
528 		if (clock->mstop_data != BUS_MSTOP_NONE)  in rzv2h_mod_clock_endisable()
529 			rzv2h_mod_clock_mstop_enable(priv, clock->mstop_data);  in rzv2h_mod_clock_endisable()
531 		if (clock->mstop_data != BUS_MSTOP_NONE)  in rzv2h_mod_clock_endisable()
532 			rzv2h_mod_clock_mstop_disable(priv, clock->mstop_data);  in rzv2h_mod_clock_endisable()
533 		writel(value, priv->base + reg);  in rzv2h_mod_clock_endisable()
536 	if (!enable || clock->mon_index < 0)  in rzv2h_mod_clock_endisable()
539 	reg = GET_CLK_MON_OFFSET(clock->mon_index);  in rzv2h_mod_clock_endisable()
540 	bitmask = BIT(clock->mon_bit);  in rzv2h_mod_clock_endisable()
541 	error = readl_poll_timeout_atomic(priv->base + reg, value,  in rzv2h_mod_clock_endisable()
545 			priv->base + reg);  in rzv2h_mod_clock_endisable()
571 	struct device *dev = priv->dev;  in rzv2h_cpg_register_mod_clk()
573 	struct clk *parent, *clk;  in rzv2h_cpg_register_mod_clk()  local
578 	id = GET_MOD_CLK_ID(priv->num_core_clks, mod->on_index, mod->on_bit);  in rzv2h_cpg_register_mod_clk()
579 	WARN_DEBUG(id >= priv->num_core_clks + priv->num_mod_clks);  in rzv2h_cpg_register_mod_clk()
580 	WARN_DEBUG(mod->parent >= priv->num_core_clks + priv->num_mod_clks);  in rzv2h_cpg_register_mod_clk()
581 	WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);  in rzv2h_cpg_register_mod_clk()
583 	parent = priv->clks[mod->parent];  in rzv2h_cpg_register_mod_clk()
584 	if (IS_ERR(parent)) {  in rzv2h_cpg_register_mod_clk()
585 		clk = parent;  in rzv2h_cpg_register_mod_clk()
591 		clk = ERR_PTR(-ENOMEM);  in rzv2h_cpg_register_mod_clk()
595 	init.name = mod->name;  in rzv2h_cpg_register_mod_clk()
598 	if (mod->critical)  in rzv2h_cpg_register_mod_clk()
601 	parent_name = __clk_get_name(parent);  in rzv2h_cpg_register_mod_clk()
605 	clock->on_index = mod->on_index;  in rzv2h_cpg_register_mod_clk()
606 	clock->on_bit = mod->on_bit;  in rzv2h_cpg_register_mod_clk()
607 	clock->mon_index = mod->mon_index;  in rzv2h_cpg_register_mod_clk()
608 	clock->mon_bit = mod->mon_bit;  in rzv2h_cpg_register_mod_clk()
609 	clock->no_pm = mod->no_pm;  in rzv2h_cpg_register_mod_clk()
610 	clock->priv = priv;  in rzv2h_cpg_register_mod_clk()
611 	clock->hw.init = &init;  in rzv2h_cpg_register_mod_clk()
612 	clock->mstop_data = mod->mstop_data;  in rzv2h_cpg_register_mod_clk()
614 	ret = devm_clk_hw_register(dev, &clock->hw);  in rzv2h_cpg_register_mod_clk()
616 		clk = ERR_PTR(ret);  in rzv2h_cpg_register_mod_clk()
620 	priv->clks[id] = clock->hw.clk;  in rzv2h_cpg_register_mod_clk()
627 	if (clock->mstop_data != BUS_MSTOP_NONE &&  in rzv2h_cpg_register_mod_clk()
628 	    !mod->critical && rzv2h_mod_clock_is_enabled(&clock->hw)) {  in rzv2h_cpg_register_mod_clk()
629 		rzv2h_mod_clock_mstop_enable(priv, clock->mstop_data);  in rzv2h_cpg_register_mod_clk()
630 	} else if (clock->mstop_data != BUS_MSTOP_NONE && mod->critical) {  in rzv2h_cpg_register_mod_clk()
631 		unsigned long mstop_mask = FIELD_GET(BUS_MSTOP_BITS_MASK, clock->mstop_data);  in rzv2h_cpg_register_mod_clk()
632 		u16 mstop_index = FIELD_GET(BUS_MSTOP_IDX_MASK, clock->mstop_data);  in rzv2h_cpg_register_mod_clk()
633 		unsigned int index = (mstop_index - 1) * 16;  in rzv2h_cpg_register_mod_clk()
634 		atomic_t *mstop = &priv->mstop_count[index];  in rzv2h_cpg_register_mod_clk()
645 		spin_lock_irqsave(&priv->rmw_lock, flags);  in rzv2h_cpg_register_mod_clk()
653 			writel(val, priv->base + CPG_BUS_MSTOP(mstop_index));  in rzv2h_cpg_register_mod_clk()
654 		spin_unlock_irqrestore(&priv->rmw_lock, flags);  in rzv2h_cpg_register_mod_clk()
661 		mod->name, PTR_ERR(clk));  in rzv2h_cpg_register_mod_clk()
668 	unsigned int reg = GET_RST_OFFSET(priv->resets[id].reset_index);  in rzv2h_cpg_assert()
669 	u32 mask = BIT(priv->resets[id].reset_bit);  in rzv2h_cpg_assert()
670 	u8 monbit = priv->resets[id].mon_bit;  in rzv2h_cpg_assert()
673 	dev_dbg(rcdev->dev, "assert id:%ld offset:0x%x\n", id, reg);  in rzv2h_cpg_assert()
675 	writel(value, priv->base + reg);  in rzv2h_cpg_assert()
677 	reg = GET_RST_MON_OFFSET(priv->resets[id].mon_index);  in rzv2h_cpg_assert()
680 	return readl_poll_timeout_atomic(priv->base + reg, value,  in rzv2h_cpg_assert()
688 	unsigned int reg = GET_RST_OFFSET(priv->resets[id].reset_index);  in rzv2h_cpg_deassert()
689 	u32 mask = BIT(priv->resets[id].reset_bit);  in rzv2h_cpg_deassert()
690 	u8 monbit = priv->resets[id].mon_bit;  in rzv2h_cpg_deassert()
693 	dev_dbg(rcdev->dev, "deassert id:%ld offset:0x%x\n", id, reg);  in rzv2h_cpg_deassert()
695 	writel(value, priv->base + reg);  in rzv2h_cpg_deassert()
697 	reg = GET_RST_MON_OFFSET(priv->resets[id].mon_index);  in rzv2h_cpg_deassert()
700 	return readl_poll_timeout_atomic(priv->base + reg, value,  in rzv2h_cpg_deassert()
720 	unsigned int reg = GET_RST_MON_OFFSET(priv->resets[id].mon_index);  in rzv2h_cpg_status()
721 	u8 monbit = priv->resets[id].mon_bit;  in rzv2h_cpg_status()
723 	return !!(readl(priv->base + reg) & BIT(monbit));  in rzv2h_cpg_status()
737 	unsigned int id = reset_spec->args[0];  in rzv2h_cpg_reset_xlate()
742 	for (i = 0; i < rcdev->nr_resets; i++) {  in rzv2h_cpg_reset_xlate()
743 		if (rst_index == priv->resets[i].reset_index &&  in rzv2h_cpg_reset_xlate()
744 		    rst_bit == priv->resets[i].reset_bit)  in rzv2h_cpg_reset_xlate()
748 	return -EINVAL;  in rzv2h_cpg_reset_xlate()
753 	priv->rcdev.ops = &rzv2h_cpg_reset_ops;  in rzv2h_cpg_reset_controller_register()
754 	priv->rcdev.of_node = priv->dev->of_node;  in rzv2h_cpg_reset_controller_register()
755 	priv->rcdev.dev = priv->dev;  in rzv2h_cpg_reset_controller_register()
756 	priv->rcdev.of_reset_n_cells = 1;  in rzv2h_cpg_reset_controller_register()
757 	priv->rcdev.of_xlate = rzv2h_cpg_reset_xlate;  in rzv2h_cpg_reset_controller_register()
758 	priv->rcdev.nr_resets = priv->num_resets;  in rzv2h_cpg_reset_controller_register()
760 	return devm_reset_controller_register(priv->dev, &priv->rcdev);  in rzv2h_cpg_reset_controller_register()
764  * struct rzv2h_cpg_pd - RZ/V2H power domain data structure
776 	if (clkspec->np != pd->genpd.dev.of_node || clkspec->args_count != 2)  in rzv2h_cpg_is_pm_clk()
779 	switch (clkspec->args[0]) {  in rzv2h_cpg_is_pm_clk()
781 		struct rzv2h_cpg_priv *priv = pd->priv;  in rzv2h_cpg_is_pm_clk()
782 		unsigned int id = clkspec->args[1];  in rzv2h_cpg_is_pm_clk()
785 		if (id >= priv->num_mod_clks)  in rzv2h_cpg_is_pm_clk()
788 		if (priv->clks[priv->num_core_clks + id] == ERR_PTR(-ENOENT))  in rzv2h_cpg_is_pm_clk()
791 		clock = to_mod_clock(__clk_get_hw(priv->clks[priv->num_core_clks + id]));  in rzv2h_cpg_is_pm_clk()
793 		return !clock->no_pm;  in rzv2h_cpg_is_pm_clk()
805 	struct device_node *np = dev->of_node;  in rzv2h_cpg_attach_dev()
808 	struct clk *clk;  in rzv2h_cpg_attach_dev()  local
812 	for (i = 0; !of_parse_phandle_with_args(np, "clocks", "#clock-cells", i, &clkspec); i++) {  in rzv2h_cpg_attach_dev()
826 		clk = of_clk_get_from_provider(&clkspec);  in rzv2h_cpg_attach_dev()
828 		if (IS_ERR(clk)) {  in rzv2h_cpg_attach_dev()
829 			error = PTR_ERR(clk);  in rzv2h_cpg_attach_dev()
833 		error = pm_clk_add_clk(dev, clk);  in rzv2h_cpg_attach_dev()
844 	clk_put(clk);  in rzv2h_cpg_attach_dev()
865 	struct device *dev = priv->dev;  in rzv2h_cpg_add_pm_domains()
866 	struct device_node *np = dev->of_node;  in rzv2h_cpg_add_pm_domains()
872 		return -ENOMEM;  in rzv2h_cpg_add_pm_domains()
874 	pd->genpd.name = np->name;  in rzv2h_cpg_add_pm_domains()
875 	pd->priv = priv;  in rzv2h_cpg_add_pm_domains()
876 	pd->genpd.flags |= GENPD_FLAG_ALWAYS_ON | GENPD_FLAG_PM_CLK | GENPD_FLAG_ACTIVE_WAKEUP;  in rzv2h_cpg_add_pm_domains()
877 	pd->genpd.attach_dev = rzv2h_cpg_attach_dev;  in rzv2h_cpg_add_pm_domains()
878 	pd->genpd.detach_dev = rzv2h_cpg_detach_dev;  in rzv2h_cpg_add_pm_domains()
879 	ret = pm_genpd_init(&pd->genpd, &pm_domain_always_on_gov, false);  in rzv2h_cpg_add_pm_domains()
883 	ret = devm_add_action_or_reset(dev, rzv2h_cpg_genpd_remove_simple, &pd->genpd);  in rzv2h_cpg_add_pm_domains()
887 	return of_genpd_add_provider_simple(np, &pd->genpd);  in rzv2h_cpg_add_pm_domains()
897 	struct device *dev = &pdev->dev;  in rzv2h_cpg_probe()
898 	struct device_node *np = dev->of_node;  in rzv2h_cpg_probe()
902 	struct clk **clks;  in rzv2h_cpg_probe()
909 		return -ENOMEM;  in rzv2h_cpg_probe()
911 	spin_lock_init(&priv->rmw_lock);  in rzv2h_cpg_probe()
913 	priv->dev = dev;  in rzv2h_cpg_probe()
915 	priv->base = devm_platform_ioremap_resource(pdev, 0);  in rzv2h_cpg_probe()
916 	if (IS_ERR(priv->base))  in rzv2h_cpg_probe()
917 		return PTR_ERR(priv->base);  in rzv2h_cpg_probe()
919 	nclks = info->num_total_core_clks + info->num_hw_mod_clks;  in rzv2h_cpg_probe()
922 		return -ENOMEM;  in rzv2h_cpg_probe()
924 	priv->mstop_count = devm_kcalloc(dev, info->num_mstop_bits,  in rzv2h_cpg_probe()
925 					 sizeof(*priv->mstop_count), GFP_KERNEL);  in rzv2h_cpg_probe()
926 	if (!priv->mstop_count)  in rzv2h_cpg_probe()
927 		return -ENOMEM;  in rzv2h_cpg_probe()
929 	priv->resets = devm_kmemdup(dev, info->resets, sizeof(*info->resets) *  in rzv2h_cpg_probe()
930 				    info->num_resets, GFP_KERNEL);  in rzv2h_cpg_probe()
931 	if (!priv->resets)  in rzv2h_cpg_probe()
932 		return -ENOMEM;  in rzv2h_cpg_probe()
935 	priv->clks = clks;  in rzv2h_cpg_probe()
936 	priv->num_core_clks = info->num_total_core_clks;  in rzv2h_cpg_probe()
937 	priv->num_mod_clks = info->num_hw_mod_clks;  in rzv2h_cpg_probe()
938 	priv->last_dt_core_clk = info->last_dt_core_clk;  in rzv2h_cpg_probe()
939 	priv->num_resets = info->num_resets;  in rzv2h_cpg_probe()
942 		clks[i] = ERR_PTR(-ENOENT);  in rzv2h_cpg_probe()
944 	for (i = 0; i < info->num_core_clks; i++)  in rzv2h_cpg_probe()
945 		rzv2h_cpg_register_core_clk(&info->core_clks[i], priv);  in rzv2h_cpg_probe()
947 	for (i = 0; i < info->num_mod_clks; i++)  in rzv2h_cpg_probe()
948 		rzv2h_cpg_register_mod_clk(&info->mod_clks[i], priv);  in rzv2h_cpg_probe()
972 		.compatible = "renesas,r9a09g057-cpg",
978 		.compatible = "renesas,r9a09g047-cpg",
987 		.name	= "rzv2h-cpg",