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Searched refs:SCB_CPUID_REVISION_Pos (Results 1 – 13 of 13) sorted by relevance

/nrf52832-nimble/rt-thread/components/CMSIS/Include/
H A Dcore_cm0.h331 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB … macro
332 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB …
H A Dcore_cm0plus.h346 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB … macro
347 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB …
H A Dcore_sc000.h339 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB … macro
340 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB …
H A Dcore_cm3.h366 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB … macro
367 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB …
H A Dcore_sc300.h357 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB … macro
358 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB …
H A Dcore_cm4.h406 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB … macro
407 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB …
/nrf52832-nimble/nordic/cmsis/include/
H A Dcore_cm0.h415 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB … macro
H A Dcore_cm0plus.h433 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB … macro
H A Dcore_sc000.h423 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB … macro
H A Dcore_cm3.h455 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB … macro
H A Dcore_sc300.h457 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB … macro
H A Dcore_cm4.h523 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB … macro
H A Dcore_cm7.h567 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB … macro