| /btstack/port/stm32-f4discovery-usb/Drivers/STM32F4xx_HAL_Driver/Inc/ |
| H A D | stm32f4xx_ll_dma.h | 54 (uint8_t)(DMA1_Stream5_BASE - DMA1_BASE),
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| /btstack/port/stm32-f4discovery-usb/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ |
| H A D | stm32f410rx.h | 625 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL) macro
693 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
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| H A D | stm32f410tx.h | 618 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL) macro
683 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
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| H A D | stm32f410cx.h | 625 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL) macro
693 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
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| H A D | stm32f401xe.h | 707 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL) macro
795 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
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| H A D | stm32f401xc.h | 707 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL) macro
795 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
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| H A D | stm32f411xe.h | 709 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL) macro
798 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
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| H A D | stm32f412cx.h | 881 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL) macro
987 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
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| H A D | stm32f405xx.h | 904 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL) macro
1019 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
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| H A D | stm32f415xx.h | 972 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL) macro
1090 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
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| H A D | stm32f412zx.h | 930 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL) macro
1044 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
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| H A D | stm32f407xx.h | 1000 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL) macro
1121 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
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| H A D | stm32f412vx.h | 930 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL) macro
1042 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
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| H A D | stm32f413xx.h | 1034 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL) macro
1173 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
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| H A D | stm32f423xx.h | 1068 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL) macro
1208 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
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| H A D | stm32f412rx.h | 927 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL) macro
1038 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
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| H A D | stm32f417xx.h | 1068 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL) macro
1192 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
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| H A D | stm32f446xx.h | 1017 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL) macro
1139 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
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| H A D | stm32f427xx.h | 1080 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL) macro
1213 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
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| H A D | stm32f437xx.h | 1152 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL) macro
1288 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
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| H A D | stm32f429xx.h | 1133 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL) macro
1269 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
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| H A D | stm32f439xx.h | 1203 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL) macro
1342 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
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| H A D | stm32f469xx.h | 1224 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL) macro
1360 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
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| H A D | stm32f479xx.h | 1294 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL) macro
1433 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
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| /btstack/port/stm32-f4discovery-cc256x/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ |
| H A D | stm32f407xx.h | 1016 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL) macro
1137 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
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