xref: /btstack/port/stm32-f4discovery-usb/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f469xx.h (revision a8f7f3fcbcd51f8d2e92aca076b6a9f812db358c) 
1 /**
2   ******************************************************************************
3   * @file    stm32f469xx.h
4   * @author  MCD Application Team
5   * @brief   CMSIS STM32F469xx Device Peripheral Access Layer Header File.
6   *
7   *          This file contains:
8   *           - Data structures and the address mapping for all peripherals
9   *           - peripherals registers declarations and bits definition
10   *           - Macros to access peripheral’s registers hardware
11   *
12   ******************************************************************************
13   * @attention
14   *
15   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
16   * All rights reserved.</center></h2>
17   *
18   * This software component is licensed by ST under BSD 3-Clause license,
19   * the "License"; You may not use this file except in compliance with the
20   * License. You may obtain a copy of the License at:
21   *                        opensource.org/licenses/BSD-3-Clause
22   *
23   ******************************************************************************
24   */
25 
26 /** @addtogroup CMSIS_Device
27   * @{
28   */
29 
30 /** @addtogroup stm32f469xx
31   * @{
32   */
33 
34 #ifndef __STM32F469xx_H
35 #define __STM32F469xx_H
36 
37 #ifdef __cplusplus
38  extern "C" {
39 #endif /* __cplusplus */
40 
41 /** @addtogroup Configuration_section_for_CMSIS
42   * @{
43   */
44 
45 /**
46   * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
47   */
48 #define __CM4_REV                 0x0001U  /*!< Core revision r0p1                            */
49 #define __MPU_PRESENT             1U       /*!< STM32F4XX provides an MPU                     */
50 #define __NVIC_PRIO_BITS          4U       /*!< STM32F4XX uses 4 Bits for the Priority Levels */
51 #define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
52 #define __FPU_PRESENT             1U       /*!< FPU present                                   */
53 
54 /**
55   * @}
56   */
57 
58 /** @addtogroup Peripheral_interrupt_number_definition
59   * @{
60   */
61 
62 /**
63  * @brief STM32F4XX Interrupt Number Definition, according to the selected device
64  *        in @ref Library_configuration_section
65  */
66 typedef enum
67 {
68 /******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/
69   NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
70   MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                           */
71   BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */
72   UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */
73   SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                    */
74   DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */
75   PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                    */
76   SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                */
77 /******  STM32 specific Interrupt Numbers **********************************************************************/
78   WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */
79   PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt                         */
80   TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */
81   RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */
82   FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
83   RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
84   EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
85   EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
86   EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */
87   EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
88   EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
89   DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */
90   DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */
91   DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */
92   DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */
93   DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */
94   DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */
95   DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */
96   ADC_IRQn                    = 18,     /*!< ADC1, ADC2 and ADC3 global Interrupts                             */
97   CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */
98   CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */
99   CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */
100   CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */
101   EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
102   TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */
103   TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */
104   TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
105   TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
106   TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
107   TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
108   TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
109   I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
110   I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
111   I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
112   I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */
113   SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
114   SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
115   USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
116   USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
117   USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
118   EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
119   RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
120   OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */
121   TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */
122   TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */
123   TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
124   TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare global interrupt                             */
125   DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
126   FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */
127   SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                             */
128   TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
129   SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
130   UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */
131   UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */
132   TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */
133   TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */
134   DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */
135   DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */
136   DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */
137   DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */
138   DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */
139   ETH_IRQn                    = 61,     /*!< Ethernet global Interrupt                                         */
140   ETH_WKUP_IRQn               = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt                       */
141   CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                                 */
142   CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                                */
143   CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                                */
144   CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                                */
145   OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */
146   DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */
147   DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */
148   DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */
149   USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */
150   I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
151   I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
152   OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */
153   OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */
154   OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */
155   OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */
156   DCMI_IRQn                   = 78,     /*!< DCMI global interrupt                                             */
157   HASH_RNG_IRQn               = 80,     /*!< Hash and Rng global interrupt                                     */
158   FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */
159   UART7_IRQn                  = 82,     /*!< UART7 global interrupt                                            */
160   UART8_IRQn                  = 83,     /*!< UART8 global interrupt                                            */
161   SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */
162   SPI5_IRQn                   = 85,     /*!< SPI5 global Interrupt                                             */
163   SPI6_IRQn                   = 86,     /*!< SPI6 global Interrupt                                             */
164   SAI1_IRQn                   = 87,     /*!< SAI1 global Interrupt                                             */
165   LTDC_IRQn                   = 88,     /*!< LTDC global Interrupt                                              */
166   LTDC_ER_IRQn                = 89,     /*!< LTDC Error global Interrupt                                        */
167   DMA2D_IRQn                  = 90,     /*!< DMA2D global Interrupt                                            */
168   QUADSPI_IRQn                = 91,     /*!< QUADSPI global Interrupt                                          */
169   DSI_IRQn                    = 92      /*!< DSI global Interrupt                                              */
170 } IRQn_Type;
171 
172 /**
173   * @}
174   */
175 
176 #include "core_cm4.h"             /* Cortex-M4 processor and core peripherals */
177 #include "system_stm32f4xx.h"
178 #include <stdint.h>
179 
180 /** @addtogroup Peripheral_registers_structures
181   * @{
182   */
183 
184 /**
185   * @brief Analog to Digital Converter
186   */
187 
188 typedef struct
189 {
190   __IO uint32_t SR;     /*!< ADC status register,                         Address offset: 0x00 */
191   __IO uint32_t CR1;    /*!< ADC control register 1,                      Address offset: 0x04 */
192   __IO uint32_t CR2;    /*!< ADC control register 2,                      Address offset: 0x08 */
193   __IO uint32_t SMPR1;  /*!< ADC sample time register 1,                  Address offset: 0x0C */
194   __IO uint32_t SMPR2;  /*!< ADC sample time register 2,                  Address offset: 0x10 */
195   __IO uint32_t JOFR1;  /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
196   __IO uint32_t JOFR2;  /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
197   __IO uint32_t JOFR3;  /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
198   __IO uint32_t JOFR4;  /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
199   __IO uint32_t HTR;    /*!< ADC watchdog higher threshold register,      Address offset: 0x24 */
200   __IO uint32_t LTR;    /*!< ADC watchdog lower threshold register,       Address offset: 0x28 */
201   __IO uint32_t SQR1;   /*!< ADC regular sequence register 1,             Address offset: 0x2C */
202   __IO uint32_t SQR2;   /*!< ADC regular sequence register 2,             Address offset: 0x30 */
203   __IO uint32_t SQR3;   /*!< ADC regular sequence register 3,             Address offset: 0x34 */
204   __IO uint32_t JSQR;   /*!< ADC injected sequence register,              Address offset: 0x38*/
205   __IO uint32_t JDR1;   /*!< ADC injected data register 1,                Address offset: 0x3C */
206   __IO uint32_t JDR2;   /*!< ADC injected data register 2,                Address offset: 0x40 */
207   __IO uint32_t JDR3;   /*!< ADC injected data register 3,                Address offset: 0x44 */
208   __IO uint32_t JDR4;   /*!< ADC injected data register 4,                Address offset: 0x48 */
209   __IO uint32_t DR;     /*!< ADC regular data register,                   Address offset: 0x4C */
210 } ADC_TypeDef;
211 
212 typedef struct
213 {
214   __IO uint32_t CSR;    /*!< ADC Common status register,                  Address offset: ADC1 base address + 0x300 */
215   __IO uint32_t CCR;    /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
216   __IO uint32_t CDR;    /*!< ADC common regular data register for dual
217                              AND triple modes,                            Address offset: ADC1 base address + 0x308 */
218 } ADC_Common_TypeDef;
219 
220 
221 /**
222   * @brief Controller Area Network TxMailBox
223   */
224 
225 typedef struct
226 {
227   __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */
228   __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
229   __IO uint32_t TDLR; /*!< CAN mailbox data low register */
230   __IO uint32_t TDHR; /*!< CAN mailbox data high register */
231 } CAN_TxMailBox_TypeDef;
232 
233 /**
234   * @brief Controller Area Network FIFOMailBox
235   */
236 
237 typedef struct
238 {
239   __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */
240   __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
241   __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
242   __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
243 } CAN_FIFOMailBox_TypeDef;
244 
245 /**
246   * @brief Controller Area Network FilterRegister
247   */
248 
249 typedef struct
250 {
251   __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
252   __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
253 } CAN_FilterRegister_TypeDef;
254 
255 /**
256   * @brief Controller Area Network
257   */
258 
259 typedef struct
260 {
261   __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */
262   __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */
263   __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */
264   __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */
265   __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */
266   __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */
267   __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */
268   __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */
269   uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */
270   CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */
271   CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */
272   uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */
273   __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */
274   __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */
275   uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */
276   __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */
277   uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */
278   __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */
279   uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */
280   __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */
281   uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */
282   CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */
283 } CAN_TypeDef;
284 
285 /**
286   * @brief CRC calculation unit
287   */
288 
289 typedef struct
290 {
291   __IO uint32_t DR;         /*!< CRC Data register,             Address offset: 0x00 */
292   __IO uint8_t  IDR;        /*!< CRC Independent data register, Address offset: 0x04 */
293   uint8_t       RESERVED0;  /*!< Reserved, 0x05                                      */
294   uint16_t      RESERVED1;  /*!< Reserved, 0x06                                      */
295   __IO uint32_t CR;         /*!< CRC Control register,          Address offset: 0x08 */
296 } CRC_TypeDef;
297 
298 /**
299   * @brief Digital to Analog Converter
300   */
301 
302 typedef struct
303 {
304   __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */
305   __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */
306   __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
307   __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
308   __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
309   __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
310   __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
311   __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
312   __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
313   __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
314   __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
315   __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */
316   __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */
317   __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */
318 } DAC_TypeDef;
319 
320 /**
321   * @brief Debug MCU
322   */
323 
324 typedef struct
325 {
326   __IO uint32_t IDCODE;  /*!< MCU device ID code,               Address offset: 0x00 */
327   __IO uint32_t CR;      /*!< Debug MCU configuration register, Address offset: 0x04 */
328   __IO uint32_t APB1FZ;  /*!< Debug MCU APB1 freeze register,   Address offset: 0x08 */
329   __IO uint32_t APB2FZ;  /*!< Debug MCU APB2 freeze register,   Address offset: 0x0C */
330 }DBGMCU_TypeDef;
331 
332 /**
333   * @brief DCMI
334   */
335 
336 typedef struct
337 {
338   __IO uint32_t CR;       /*!< DCMI control register 1,                       Address offset: 0x00 */
339   __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */
340   __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */
341   __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */
342   __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */
343   __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */
344   __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */
345   __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
346   __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */
347   __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */
348   __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */
349 } DCMI_TypeDef;
350 
351 /**
352   * @brief DMA Controller
353   */
354 
355 typedef struct
356 {
357   __IO uint32_t CR;     /*!< DMA stream x configuration register      */
358   __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */
359   __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */
360   __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */
361   __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */
362   __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */
363 } DMA_Stream_TypeDef;
364 
365 typedef struct
366 {
367   __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */
368   __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */
369   __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */
370   __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
371 } DMA_TypeDef;
372 
373 /**
374   * @brief DMA2D Controller
375   */
376 
377 typedef struct
378 {
379   __IO uint32_t CR;            /*!< DMA2D Control Register,                         Address offset: 0x00 */
380   __IO uint32_t ISR;           /*!< DMA2D Interrupt Status Register,                Address offset: 0x04 */
381   __IO uint32_t IFCR;          /*!< DMA2D Interrupt Flag Clear Register,            Address offset: 0x08 */
382   __IO uint32_t FGMAR;         /*!< DMA2D Foreground Memory Address Register,       Address offset: 0x0C */
383   __IO uint32_t FGOR;          /*!< DMA2D Foreground Offset Register,               Address offset: 0x10 */
384   __IO uint32_t BGMAR;         /*!< DMA2D Background Memory Address Register,       Address offset: 0x14 */
385   __IO uint32_t BGOR;          /*!< DMA2D Background Offset Register,               Address offset: 0x18 */
386   __IO uint32_t FGPFCCR;       /*!< DMA2D Foreground PFC Control Register,          Address offset: 0x1C */
387   __IO uint32_t FGCOLR;        /*!< DMA2D Foreground Color Register,                Address offset: 0x20 */
388   __IO uint32_t BGPFCCR;       /*!< DMA2D Background PFC Control Register,          Address offset: 0x24 */
389   __IO uint32_t BGCOLR;        /*!< DMA2D Background Color Register,                Address offset: 0x28 */
390   __IO uint32_t FGCMAR;        /*!< DMA2D Foreground CLUT Memory Address Register,  Address offset: 0x2C */
391   __IO uint32_t BGCMAR;        /*!< DMA2D Background CLUT Memory Address Register,  Address offset: 0x30 */
392   __IO uint32_t OPFCCR;        /*!< DMA2D Output PFC Control Register,              Address offset: 0x34 */
393   __IO uint32_t OCOLR;         /*!< DMA2D Output Color Register,                    Address offset: 0x38 */
394   __IO uint32_t OMAR;          /*!< DMA2D Output Memory Address Register,           Address offset: 0x3C */
395   __IO uint32_t OOR;           /*!< DMA2D Output Offset Register,                   Address offset: 0x40 */
396   __IO uint32_t NLR;           /*!< DMA2D Number of Line Register,                  Address offset: 0x44 */
397   __IO uint32_t LWR;           /*!< DMA2D Line Watermark Register,                  Address offset: 0x48 */
398   __IO uint32_t AMTCR;         /*!< DMA2D AHB Master Timer Configuration Register,  Address offset: 0x4C */
399   uint32_t      RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
400   __IO uint32_t FGCLUT[256];   /*!< DMA2D Foreground CLUT,                          Address offset:400-7FF */
401   __IO uint32_t BGCLUT[256];   /*!< DMA2D Background CLUT,                          Address offset:800-BFF */
402 } DMA2D_TypeDef;
403 
404 /**
405   * @brief DSI Controller
406   */
407 
408 typedef struct
409 {
410   __IO uint32_t VR;            /*!< DSI Host Version Register,                                 Address offset: 0x00        */
411   __IO uint32_t CR;            /*!< DSI Host Control Register,                                 Address offset: 0x04        */
412   __IO uint32_t CCR;           /*!< DSI HOST Clock Control Register,                           Address offset: 0x08        */
413   __IO uint32_t LVCIDR;        /*!< DSI Host LTDC VCID Register,                               Address offset: 0x0C        */
414   __IO uint32_t LCOLCR;        /*!< DSI Host LTDC Color Coding Register,                       Address offset: 0x10        */
415   __IO uint32_t LPCR;          /*!< DSI Host LTDC Polarity Configuration Register,             Address offset: 0x14        */
416   __IO uint32_t LPMCR;         /*!< DSI Host Low-Power Mode Configuration Register,            Address offset: 0x18        */
417   uint32_t      RESERVED0[4];  /*!< Reserved, 0x1C - 0x2B                                                                  */
418   __IO uint32_t PCR;           /*!< DSI Host Protocol Configuration Register,                  Address offset: 0x2C        */
419   __IO uint32_t GVCIDR;        /*!< DSI Host Generic VCID Register,                            Address offset: 0x30        */
420   __IO uint32_t MCR;           /*!< DSI Host Mode Configuration Register,                      Address offset: 0x34        */
421   __IO uint32_t VMCR;          /*!< DSI Host Video Mode Configuration Register,                Address offset: 0x38        */
422   __IO uint32_t VPCR;          /*!< DSI Host Video Packet Configuration Register,              Address offset: 0x3C        */
423   __IO uint32_t VCCR;          /*!< DSI Host Video Chunks Configuration Register,              Address offset: 0x40        */
424   __IO uint32_t VNPCR;         /*!< DSI Host Video Null Packet Configuration Register,         Address offset: 0x44        */
425   __IO uint32_t VHSACR;        /*!< DSI Host Video HSA Configuration Register,                 Address offset: 0x48        */
426   __IO uint32_t VHBPCR;        /*!< DSI Host Video HBP Configuration Register,                 Address offset: 0x4C        */
427   __IO uint32_t VLCR;          /*!< DSI Host Video Line Configuration Register,                Address offset: 0x50        */
428   __IO uint32_t VVSACR;        /*!< DSI Host Video VSA Configuration Register,                 Address offset: 0x54        */
429   __IO uint32_t VVBPCR;        /*!< DSI Host Video VBP Configuration Register,                 Address offset: 0x58        */
430   __IO uint32_t VVFPCR;        /*!< DSI Host Video VFP Configuration Register,                 Address offset: 0x5C        */
431   __IO uint32_t VVACR;         /*!< DSI Host Video VA Configuration Register,                  Address offset: 0x60        */
432   __IO uint32_t LCCR;          /*!< DSI Host LTDC Command Configuration Register,              Address offset: 0x64        */
433   __IO uint32_t CMCR;          /*!< DSI Host Command Mode Configuration Register,              Address offset: 0x68        */
434   __IO uint32_t GHCR;          /*!< DSI Host Generic Header Configuration Register,            Address offset: 0x6C        */
435   __IO uint32_t GPDR;          /*!< DSI Host Generic Payload Data Register,                    Address offset: 0x70        */
436   __IO uint32_t GPSR;          /*!< DSI Host Generic Packet Status Register,                   Address offset: 0x74        */
437   __IO uint32_t TCCR[6];       /*!< DSI Host Timeout Counter Configuration Register,           Address offset: 0x78-0x8F   */
438   __IO uint32_t TDCR;          /*!< DSI Host 3D Configuration Register,                        Address offset: 0x90        */
439   __IO uint32_t CLCR;          /*!< DSI Host Clock Lane Configuration Register,                Address offset: 0x94        */
440   __IO uint32_t CLTCR;         /*!< DSI Host Clock Lane Timer Configuration Register,          Address offset: 0x98        */
441   __IO uint32_t DLTCR;         /*!< DSI Host Data Lane Timer Configuration Register,           Address offset: 0x9C        */
442   __IO uint32_t PCTLR;         /*!< DSI Host PHY Control Register,                             Address offset: 0xA0        */
443   __IO uint32_t PCONFR;        /*!< DSI Host PHY Configuration Register,                       Address offset: 0xA4        */
444   __IO uint32_t PUCR;          /*!< DSI Host PHY ULPS Control Register,                        Address offset: 0xA8        */
445   __IO uint32_t PTTCR;         /*!< DSI Host PHY TX Triggers Configuration Register,           Address offset: 0xAC        */
446   __IO uint32_t PSR;           /*!< DSI Host PHY Status Register,                              Address offset: 0xB0        */
447   uint32_t      RESERVED1[2];  /*!< Reserved, 0xB4 - 0xBB                                                                  */
448   __IO uint32_t ISR[2];        /*!< DSI Host Interrupt & Status Register,                      Address offset: 0xBC-0xC3   */
449   __IO uint32_t IER[2];        /*!< DSI Host Interrupt Enable Register,                        Address offset: 0xC4-0xCB   */
450   uint32_t      RESERVED2[3];  /*!< Reserved, 0xD0 - 0xD7                                                                  */
451   __IO uint32_t FIR[2];        /*!< DSI Host Force Interrupt Register,                         Address offset: 0xD8-0xDF   */
452   uint32_t      RESERVED3[8];  /*!< Reserved, 0xE0 - 0xFF                                                                  */
453   __IO uint32_t VSCR;          /*!< DSI Host Video Shadow Control Register,                    Address offset: 0x100       */
454   uint32_t      RESERVED4[2];  /*!< Reserved, 0x104 - 0x10B                                                                */
455   __IO uint32_t LCVCIDR;       /*!< DSI Host LTDC Current VCID Register,                       Address offset: 0x10C       */
456   __IO uint32_t LCCCR;         /*!< DSI Host LTDC Current Color Coding Register,               Address offset: 0x110       */
457   uint32_t      RESERVED5;     /*!< Reserved, 0x114                                                                        */
458   __IO uint32_t LPMCCR;        /*!< DSI Host Low-power Mode Current Configuration Register,    Address offset: 0x118       */
459   uint32_t      RESERVED6[7];  /*!< Reserved, 0x11C - 0x137                                                                */
460   __IO uint32_t VMCCR;         /*!< DSI Host Video Mode Current Configuration Register,        Address offset: 0x138       */
461   __IO uint32_t VPCCR;         /*!< DSI Host Video Packet Current Configuration Register,      Address offset: 0x13C       */
462   __IO uint32_t VCCCR;         /*!< DSI Host Video Chuncks Current Configuration Register,     Address offset: 0x140       */
463   __IO uint32_t VNPCCR;        /*!< DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144       */
464   __IO uint32_t VHSACCR;       /*!< DSI Host Video HSA Current Configuration Register,         Address offset: 0x148       */
465   __IO uint32_t VHBPCCR;       /*!< DSI Host Video HBP Current Configuration Register,         Address offset: 0x14C       */
466   __IO uint32_t VLCCR;         /*!< DSI Host Video Line Current Configuration Register,        Address offset: 0x150       */
467   __IO uint32_t VVSACCR;       /*!< DSI Host Video VSA Current Configuration Register,         Address offset: 0x154       */
468   __IO uint32_t VVBPCCR;       /*!< DSI Host Video VBP Current Configuration Register,         Address offset: 0x158       */
469   __IO uint32_t VVFPCCR;       /*!< DSI Host Video VFP Current Configuration Register,         Address offset: 0x15C       */
470   __IO uint32_t VVACCR;        /*!< DSI Host Video VA Current Configuration Register,          Address offset: 0x160       */
471   uint32_t      RESERVED7[11]; /*!< Reserved, 0x164 - 0x18F                                                                */
472   __IO uint32_t TDCCR;         /*!< DSI Host 3D Current Configuration Register,                Address offset: 0x190       */
473   uint32_t      RESERVED8[155]; /*!< Reserved, 0x194 - 0x3FF                                                               */
474   __IO uint32_t WCFGR;          /*!< DSI Wrapper Configuration Register,                       Address offset: 0x400       */
475   __IO uint32_t WCR;            /*!< DSI Wrapper Control Register,                             Address offset: 0x404       */
476   __IO uint32_t WIER;           /*!< DSI Wrapper Interrupt Enable Register,                    Address offset: 0x408       */
477   __IO uint32_t WISR;           /*!< DSI Wrapper Interrupt and Status Register,                Address offset: 0x40C       */
478   __IO uint32_t WIFCR;          /*!< DSI Wrapper Interrupt Flag Clear Register,                Address offset: 0x410       */
479   uint32_t      RESERVED9;      /*!< Reserved, 0x414                                                                       */
480   __IO uint32_t WPCR[5];        /*!< DSI Wrapper PHY Configuration Register,                   Address offset: 0x418-0x42B */
481   uint32_t      RESERVED10;     /*!< Reserved, 0x42C                                                                       */
482   __IO uint32_t WRPCR;          /*!< DSI Wrapper Regulator and PLL Control Register, Address offset: 0x430                 */
483 } DSI_TypeDef;
484 
485 /**
486   * @brief Ethernet MAC
487   */
488 
489 typedef struct
490 {
491   __IO uint32_t MACCR;
492   __IO uint32_t MACFFR;
493   __IO uint32_t MACHTHR;
494   __IO uint32_t MACHTLR;
495   __IO uint32_t MACMIIAR;
496   __IO uint32_t MACMIIDR;
497   __IO uint32_t MACFCR;
498   __IO uint32_t MACVLANTR;             /*    8 */
499   uint32_t      RESERVED0[2];
500   __IO uint32_t MACRWUFFR;             /*   11 */
501   __IO uint32_t MACPMTCSR;
502   uint32_t      RESERVED1;
503   __IO uint32_t MACDBGR;
504   __IO uint32_t MACSR;                 /*   15 */
505   __IO uint32_t MACIMR;
506   __IO uint32_t MACA0HR;
507   __IO uint32_t MACA0LR;
508   __IO uint32_t MACA1HR;
509   __IO uint32_t MACA1LR;
510   __IO uint32_t MACA2HR;
511   __IO uint32_t MACA2LR;
512   __IO uint32_t MACA3HR;
513   __IO uint32_t MACA3LR;               /*   24 */
514   uint32_t      RESERVED2[40];
515   __IO uint32_t MMCCR;                 /*   65 */
516   __IO uint32_t MMCRIR;
517   __IO uint32_t MMCTIR;
518   __IO uint32_t MMCRIMR;
519   __IO uint32_t MMCTIMR;               /*   69 */
520   uint32_t      RESERVED3[14];
521   __IO uint32_t MMCTGFSCCR;            /*   84 */
522   __IO uint32_t MMCTGFMSCCR;
523   uint32_t      RESERVED4[5];
524   __IO uint32_t MMCTGFCR;
525   uint32_t      RESERVED5[10];
526   __IO uint32_t MMCRFCECR;
527   __IO uint32_t MMCRFAECR;
528   uint32_t      RESERVED6[10];
529   __IO uint32_t MMCRGUFCR;
530   uint32_t      RESERVED7[334];
531   __IO uint32_t PTPTSCR;
532   __IO uint32_t PTPSSIR;
533   __IO uint32_t PTPTSHR;
534   __IO uint32_t PTPTSLR;
535   __IO uint32_t PTPTSHUR;
536   __IO uint32_t PTPTSLUR;
537   __IO uint32_t PTPTSAR;
538   __IO uint32_t PTPTTHR;
539   __IO uint32_t PTPTTLR;
540   __IO uint32_t RESERVED8;
541   __IO uint32_t PTPTSSR;
542   uint32_t      RESERVED9[565];
543   __IO uint32_t DMABMR;
544   __IO uint32_t DMATPDR;
545   __IO uint32_t DMARPDR;
546   __IO uint32_t DMARDLAR;
547   __IO uint32_t DMATDLAR;
548   __IO uint32_t DMASR;
549   __IO uint32_t DMAOMR;
550   __IO uint32_t DMAIER;
551   __IO uint32_t DMAMFBOCR;
552   __IO uint32_t DMARSWTR;
553   uint32_t      RESERVED10[8];
554   __IO uint32_t DMACHTDR;
555   __IO uint32_t DMACHRDR;
556   __IO uint32_t DMACHTBAR;
557   __IO uint32_t DMACHRBAR;
558 } ETH_TypeDef;
559 
560 /**
561   * @brief External Interrupt/Event Controller
562   */
563 
564 typedef struct
565 {
566   __IO uint32_t IMR;    /*!< EXTI Interrupt mask register,            Address offset: 0x00 */
567   __IO uint32_t EMR;    /*!< EXTI Event mask register,                Address offset: 0x04 */
568   __IO uint32_t RTSR;   /*!< EXTI Rising trigger selection register,  Address offset: 0x08 */
569   __IO uint32_t FTSR;   /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
570   __IO uint32_t SWIER;  /*!< EXTI Software interrupt event register,  Address offset: 0x10 */
571   __IO uint32_t PR;     /*!< EXTI Pending register,                   Address offset: 0x14 */
572 } EXTI_TypeDef;
573 
574 /**
575   * @brief FLASH Registers
576   */
577 
578 typedef struct
579 {
580   __IO uint32_t ACR;      /*!< FLASH access control register,   Address offset: 0x00 */
581   __IO uint32_t KEYR;     /*!< FLASH key register,              Address offset: 0x04 */
582   __IO uint32_t OPTKEYR;  /*!< FLASH option key register,       Address offset: 0x08 */
583   __IO uint32_t SR;       /*!< FLASH status register,           Address offset: 0x0C */
584   __IO uint32_t CR;       /*!< FLASH control register,          Address offset: 0x10 */
585   __IO uint32_t OPTCR;    /*!< FLASH option control register ,  Address offset: 0x14 */
586   __IO uint32_t OPTCR1;   /*!< FLASH option control register 1, Address offset: 0x18 */
587 } FLASH_TypeDef;
588 
589 /**
590   * @brief Flexible Memory Controller
591   */
592 
593 typedef struct
594 {
595   __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
596 } FMC_Bank1_TypeDef;
597 
598 /**
599   * @brief Flexible Memory Controller Bank1E
600   */
601 
602 typedef struct
603 {
604   __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
605 } FMC_Bank1E_TypeDef;
606 
607 /**
608   * @brief Flexible Memory Controller Bank3
609   */
610 
611 typedef struct
612 {
613   __IO uint32_t PCR;       /*!< NAND Flash control register,                       Address offset: 0x80 */
614   __IO uint32_t SR;        /*!< NAND Flash FIFO status and interrupt register,     Address offset: 0x84 */
615   __IO uint32_t PMEM;      /*!< NAND Flash Common memory space timing register,    Address offset: 0x88 */
616   __IO uint32_t PATT;      /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
617   uint32_t      RESERVED;  /*!< Reserved, 0x90                                                          */
618   __IO uint32_t ECCR;      /*!< NAND Flash ECC result registers,                   Address offset: 0x94 */
619 } FMC_Bank3_TypeDef;
620 
621 /**
622   * @brief Flexible Memory Controller Bank5_6
623   */
624 
625 typedef struct
626 {
627   __IO uint32_t SDCR[2];        /*!< SDRAM Control registers ,      Address offset: 0x140-0x144  */
628   __IO uint32_t SDTR[2];        /*!< SDRAM Timing registers ,       Address offset: 0x148-0x14C  */
629   __IO uint32_t SDCMR;          /*!< SDRAM Command Mode register,   Address offset: 0x150        */
630   __IO uint32_t SDRTR;          /*!< SDRAM Refresh Timer register,  Address offset: 0x154        */
631   __IO uint32_t SDSR;           /*!< SDRAM Status register,         Address offset: 0x158        */
632 } FMC_Bank5_6_TypeDef;
633 
634 /**
635   * @brief General Purpose I/O
636   */
637 
638 typedef struct
639 {
640   __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */
641   __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */
642   __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */
643   __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
644   __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */
645   __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */
646   __IO uint32_t BSRR;     /*!< GPIO port bit set/reset register,      Address offset: 0x18      */
647   __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */
648   __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
649 } GPIO_TypeDef;
650 
651 /**
652   * @brief System configuration controller
653   */
654 
655 typedef struct
656 {
657   __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
658   __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
659   __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
660   uint32_t      RESERVED[2];  /*!< Reserved, 0x18-0x1C                                                          */
661   __IO uint32_t CMPCR;        /*!< SYSCFG Compensation cell control register,         Address offset: 0x20      */
662 } SYSCFG_TypeDef;
663 
664 /**
665   * @brief Inter-integrated Circuit Interface
666   */
667 
668 typedef struct
669 {
670   __IO uint32_t CR1;        /*!< I2C Control register 1,     Address offset: 0x00 */
671   __IO uint32_t CR2;        /*!< I2C Control register 2,     Address offset: 0x04 */
672   __IO uint32_t OAR1;       /*!< I2C Own address register 1, Address offset: 0x08 */
673   __IO uint32_t OAR2;       /*!< I2C Own address register 2, Address offset: 0x0C */
674   __IO uint32_t DR;         /*!< I2C Data register,          Address offset: 0x10 */
675   __IO uint32_t SR1;        /*!< I2C Status register 1,      Address offset: 0x14 */
676   __IO uint32_t SR2;        /*!< I2C Status register 2,      Address offset: 0x18 */
677   __IO uint32_t CCR;        /*!< I2C Clock control register, Address offset: 0x1C */
678   __IO uint32_t TRISE;      /*!< I2C TRISE register,         Address offset: 0x20 */
679   __IO uint32_t FLTR;       /*!< I2C FLTR register,          Address offset: 0x24 */
680 } I2C_TypeDef;
681 
682 /**
683   * @brief Independent WATCHDOG
684   */
685 
686 typedef struct
687 {
688   __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
689   __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
690   __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
691   __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
692 } IWDG_TypeDef;
693 
694 /**
695   * @brief LCD-TFT Display Controller
696   */
697 
698 typedef struct
699 {
700   uint32_t      RESERVED0[2];  /*!< Reserved, 0x00-0x04                                                       */
701   __IO uint32_t SSCR;          /*!< LTDC Synchronization Size Configuration Register,    Address offset: 0x08 */
702   __IO uint32_t BPCR;          /*!< LTDC Back Porch Configuration Register,              Address offset: 0x0C */
703   __IO uint32_t AWCR;          /*!< LTDC Active Width Configuration Register,            Address offset: 0x10 */
704   __IO uint32_t TWCR;          /*!< LTDC Total Width Configuration Register,             Address offset: 0x14 */
705   __IO uint32_t GCR;           /*!< LTDC Global Control Register,                        Address offset: 0x18 */
706   uint32_t      RESERVED1[2];  /*!< Reserved, 0x1C-0x20                                                       */
707   __IO uint32_t SRCR;          /*!< LTDC Shadow Reload Configuration Register,           Address offset: 0x24 */
708   uint32_t      RESERVED2[1];  /*!< Reserved, 0x28                                                            */
709   __IO uint32_t BCCR;          /*!< LTDC Background Color Configuration Register,        Address offset: 0x2C */
710   uint32_t      RESERVED3[1];  /*!< Reserved, 0x30                                                            */
711   __IO uint32_t IER;           /*!< LTDC Interrupt Enable Register,                      Address offset: 0x34 */
712   __IO uint32_t ISR;           /*!< LTDC Interrupt Status Register,                      Address offset: 0x38 */
713   __IO uint32_t ICR;           /*!< LTDC Interrupt Clear Register,                       Address offset: 0x3C */
714   __IO uint32_t LIPCR;         /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
715   __IO uint32_t CPSR;          /*!< LTDC Current Position Status Register,               Address offset: 0x44 */
716   __IO uint32_t CDSR;          /*!< LTDC Current Display Status Register,                Address offset: 0x48 */
717 } LTDC_TypeDef;
718 
719 /**
720   * @brief LCD-TFT Display layer x Controller
721   */
722 
723 typedef struct
724 {
725   __IO uint32_t CR;            /*!< LTDC Layerx Control Register                                  Address offset: 0x84 */
726   __IO uint32_t WHPCR;         /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
727   __IO uint32_t WVPCR;         /*!< LTDC Layerx Window Vertical Position Configuration Register   Address offset: 0x8C */
728   __IO uint32_t CKCR;          /*!< LTDC Layerx Color Keying Configuration Register               Address offset: 0x90 */
729   __IO uint32_t PFCR;          /*!< LTDC Layerx Pixel Format Configuration Register               Address offset: 0x94 */
730   __IO uint32_t CACR;          /*!< LTDC Layerx Constant Alpha Configuration Register             Address offset: 0x98 */
731   __IO uint32_t DCCR;          /*!< LTDC Layerx Default Color Configuration Register              Address offset: 0x9C */
732   __IO uint32_t BFCR;          /*!< LTDC Layerx Blending Factors Configuration Register           Address offset: 0xA0 */
733   uint32_t      RESERVED0[2];  /*!< Reserved                                                                           */
734   __IO uint32_t CFBAR;         /*!< LTDC Layerx Color Frame Buffer Address Register               Address offset: 0xAC */
735   __IO uint32_t CFBLR;         /*!< LTDC Layerx Color Frame Buffer Length Register                Address offset: 0xB0 */
736   __IO uint32_t CFBLNR;        /*!< LTDC Layerx ColorFrame Buffer Line Number Register            Address offset: 0xB4 */
737   uint32_t      RESERVED1[3];  /*!< Reserved                                                                           */
738   __IO uint32_t CLUTWR;        /*!< LTDC Layerx CLUT Write Register                               Address offset: 0x144*/
739 } LTDC_Layer_TypeDef;
740 
741 /**
742   * @brief Power Control
743   */
744 
745 typedef struct
746 {
747   __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
748   __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
749 } PWR_TypeDef;
750 
751 /**
752   * @brief Reset and Clock Control
753   */
754 
755 typedef struct
756 {
757   __IO uint32_t CR;            /*!< RCC clock control register,                                  Address offset: 0x00 */
758   __IO uint32_t PLLCFGR;       /*!< RCC PLL configuration register,                              Address offset: 0x04 */
759   __IO uint32_t CFGR;          /*!< RCC clock configuration register,                            Address offset: 0x08 */
760   __IO uint32_t CIR;           /*!< RCC clock interrupt register,                                Address offset: 0x0C */
761   __IO uint32_t AHB1RSTR;      /*!< RCC AHB1 peripheral reset register,                          Address offset: 0x10 */
762   __IO uint32_t AHB2RSTR;      /*!< RCC AHB2 peripheral reset register,                          Address offset: 0x14 */
763   __IO uint32_t AHB3RSTR;      /*!< RCC AHB3 peripheral reset register,                          Address offset: 0x18 */
764   uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                                    */
765   __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                          Address offset: 0x20 */
766   __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                          Address offset: 0x24 */
767   uint32_t      RESERVED1[2];  /*!< Reserved, 0x28-0x2C                                                               */
768   __IO uint32_t AHB1ENR;       /*!< RCC AHB1 peripheral clock register,                          Address offset: 0x30 */
769   __IO uint32_t AHB2ENR;       /*!< RCC AHB2 peripheral clock register,                          Address offset: 0x34 */
770   __IO uint32_t AHB3ENR;       /*!< RCC AHB3 peripheral clock register,                          Address offset: 0x38 */
771   uint32_t      RESERVED2;     /*!< Reserved, 0x3C                                                                    */
772   __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x40 */
773   __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x44 */
774   uint32_t      RESERVED3[2];  /*!< Reserved, 0x48-0x4C                                                               */
775   __IO uint32_t AHB1LPENR;     /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
776   __IO uint32_t AHB2LPENR;     /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
777   __IO uint32_t AHB3LPENR;     /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
778   uint32_t      RESERVED4;     /*!< Reserved, 0x5C                                                                    */
779   __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
780   __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
781   uint32_t      RESERVED5[2];  /*!< Reserved, 0x68-0x6C                                                               */
782   __IO uint32_t BDCR;          /*!< RCC Backup domain control register,                          Address offset: 0x70 */
783   __IO uint32_t CSR;           /*!< RCC clock control & status register,                         Address offset: 0x74 */
784   uint32_t      RESERVED6[2];  /*!< Reserved, 0x78-0x7C                                                               */
785   __IO uint32_t SSCGR;         /*!< RCC spread spectrum clock generation register,               Address offset: 0x80 */
786   __IO uint32_t PLLI2SCFGR;    /*!< RCC PLLI2S configuration register,                           Address offset: 0x84 */
787   __IO uint32_t PLLSAICFGR;    /*!< RCC PLLSAI configuration register,                           Address offset: 0x88 */
788   __IO uint32_t DCKCFGR;       /*!< RCC Dedicated Clocks configuration register,                 Address offset: 0x8C */
789 } RCC_TypeDef;
790 
791 /**
792   * @brief Real-Time Clock
793   */
794 
795 typedef struct
796 {
797   __IO uint32_t TR;      /*!< RTC time register,                                        Address offset: 0x00 */
798   __IO uint32_t DR;      /*!< RTC date register,                                        Address offset: 0x04 */
799   __IO uint32_t CR;      /*!< RTC control register,                                     Address offset: 0x08 */
800   __IO uint32_t ISR;     /*!< RTC initialization and status register,                   Address offset: 0x0C */
801   __IO uint32_t PRER;    /*!< RTC prescaler register,                                   Address offset: 0x10 */
802   __IO uint32_t WUTR;    /*!< RTC wakeup timer register,                                Address offset: 0x14 */
803   __IO uint32_t CALIBR;  /*!< RTC calibration register,                                 Address offset: 0x18 */
804   __IO uint32_t ALRMAR;  /*!< RTC alarm A register,                                     Address offset: 0x1C */
805   __IO uint32_t ALRMBR;  /*!< RTC alarm B register,                                     Address offset: 0x20 */
806   __IO uint32_t WPR;     /*!< RTC write protection register,                            Address offset: 0x24 */
807   __IO uint32_t SSR;     /*!< RTC sub second register,                                  Address offset: 0x28 */
808   __IO uint32_t SHIFTR;  /*!< RTC shift control register,                               Address offset: 0x2C */
809   __IO uint32_t TSTR;    /*!< RTC time stamp time register,                             Address offset: 0x30 */
810   __IO uint32_t TSDR;    /*!< RTC time stamp date register,                             Address offset: 0x34 */
811   __IO uint32_t TSSSR;   /*!< RTC time-stamp sub second register,                       Address offset: 0x38 */
812   __IO uint32_t CALR;    /*!< RTC calibration register,                                 Address offset: 0x3C */
813   __IO uint32_t TAFCR;   /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
814   __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register,                          Address offset: 0x44 */
815   __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register,                          Address offset: 0x48 */
816   uint32_t RESERVED7;    /*!< Reserved, 0x4C                                                                 */
817   __IO uint32_t BKP0R;   /*!< RTC backup register 1,                                    Address offset: 0x50 */
818   __IO uint32_t BKP1R;   /*!< RTC backup register 1,                                    Address offset: 0x54 */
819   __IO uint32_t BKP2R;   /*!< RTC backup register 2,                                    Address offset: 0x58 */
820   __IO uint32_t BKP3R;   /*!< RTC backup register 3,                                    Address offset: 0x5C */
821   __IO uint32_t BKP4R;   /*!< RTC backup register 4,                                    Address offset: 0x60 */
822   __IO uint32_t BKP5R;   /*!< RTC backup register 5,                                    Address offset: 0x64 */
823   __IO uint32_t BKP6R;   /*!< RTC backup register 6,                                    Address offset: 0x68 */
824   __IO uint32_t BKP7R;   /*!< RTC backup register 7,                                    Address offset: 0x6C */
825   __IO uint32_t BKP8R;   /*!< RTC backup register 8,                                    Address offset: 0x70 */
826   __IO uint32_t BKP9R;   /*!< RTC backup register 9,                                    Address offset: 0x74 */
827   __IO uint32_t BKP10R;  /*!< RTC backup register 10,                                   Address offset: 0x78 */
828   __IO uint32_t BKP11R;  /*!< RTC backup register 11,                                   Address offset: 0x7C */
829   __IO uint32_t BKP12R;  /*!< RTC backup register 12,                                   Address offset: 0x80 */
830   __IO uint32_t BKP13R;  /*!< RTC backup register 13,                                   Address offset: 0x84 */
831   __IO uint32_t BKP14R;  /*!< RTC backup register 14,                                   Address offset: 0x88 */
832   __IO uint32_t BKP15R;  /*!< RTC backup register 15,                                   Address offset: 0x8C */
833   __IO uint32_t BKP16R;  /*!< RTC backup register 16,                                   Address offset: 0x90 */
834   __IO uint32_t BKP17R;  /*!< RTC backup register 17,                                   Address offset: 0x94 */
835   __IO uint32_t BKP18R;  /*!< RTC backup register 18,                                   Address offset: 0x98 */
836   __IO uint32_t BKP19R;  /*!< RTC backup register 19,                                   Address offset: 0x9C */
837 } RTC_TypeDef;
838 
839 /**
840   * @brief Serial Audio Interface
841   */
842 
843 typedef struct
844 {
845   __IO uint32_t GCR;      /*!< SAI global configuration register,        Address offset: 0x00 */
846 } SAI_TypeDef;
847 
848 typedef struct
849 {
850   __IO uint32_t CR1;      /*!< SAI block x configuration register 1,     Address offset: 0x04 */
851   __IO uint32_t CR2;      /*!< SAI block x configuration register 2,     Address offset: 0x08 */
852   __IO uint32_t FRCR;     /*!< SAI block x frame configuration register, Address offset: 0x0C */
853   __IO uint32_t SLOTR;    /*!< SAI block x slot register,                Address offset: 0x10 */
854   __IO uint32_t IMR;      /*!< SAI block x interrupt mask register,      Address offset: 0x14 */
855   __IO uint32_t SR;       /*!< SAI block x status register,              Address offset: 0x18 */
856   __IO uint32_t CLRFR;    /*!< SAI block x clear flag register,          Address offset: 0x1C */
857   __IO uint32_t DR;       /*!< SAI block x data register,                Address offset: 0x20 */
858 } SAI_Block_TypeDef;
859 
860 /**
861   * @brief SD host Interface
862   */
863 
864 typedef struct
865 {
866   __IO uint32_t POWER;                 /*!< SDIO power control register,    Address offset: 0x00 */
867   __IO uint32_t CLKCR;                 /*!< SDI clock control register,     Address offset: 0x04 */
868   __IO uint32_t ARG;                   /*!< SDIO argument register,         Address offset: 0x08 */
869   __IO uint32_t CMD;                   /*!< SDIO command register,          Address offset: 0x0C */
870   __IO const uint32_t  RESPCMD;        /*!< SDIO command response register, Address offset: 0x10 */
871   __IO const uint32_t  RESP1;          /*!< SDIO response 1 register,       Address offset: 0x14 */
872   __IO const uint32_t  RESP2;          /*!< SDIO response 2 register,       Address offset: 0x18 */
873   __IO const uint32_t  RESP3;          /*!< SDIO response 3 register,       Address offset: 0x1C */
874   __IO const uint32_t  RESP4;          /*!< SDIO response 4 register,       Address offset: 0x20 */
875   __IO uint32_t DTIMER;                /*!< SDIO data timer register,       Address offset: 0x24 */
876   __IO uint32_t DLEN;                  /*!< SDIO data length register,      Address offset: 0x28 */
877   __IO uint32_t DCTRL;                 /*!< SDIO data control register,     Address offset: 0x2C */
878   __IO const uint32_t  DCOUNT;         /*!< SDIO data counter register,     Address offset: 0x30 */
879   __IO const uint32_t  STA;            /*!< SDIO status register,           Address offset: 0x34 */
880   __IO uint32_t ICR;                   /*!< SDIO interrupt clear register,  Address offset: 0x38 */
881   __IO uint32_t MASK;                  /*!< SDIO mask register,             Address offset: 0x3C */
882   uint32_t      RESERVED0[2];          /*!< Reserved, 0x40-0x44                                  */
883   __IO const uint32_t  FIFOCNT;        /*!< SDIO FIFO counter register,     Address offset: 0x48 */
884   uint32_t      RESERVED1[13];         /*!< Reserved, 0x4C-0x7C                                  */
885   __IO uint32_t FIFO;                  /*!< SDIO data FIFO register,        Address offset: 0x80 */
886 } SDIO_TypeDef;
887 
888 /**
889   * @brief Serial Peripheral Interface
890   */
891 
892 typedef struct
893 {
894   __IO uint32_t CR1;        /*!< SPI control register 1 (not used in I2S mode),      Address offset: 0x00 */
895   __IO uint32_t CR2;        /*!< SPI control register 2,                             Address offset: 0x04 */
896   __IO uint32_t SR;         /*!< SPI status register,                                Address offset: 0x08 */
897   __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
898   __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
899   __IO uint32_t RXCRCR;     /*!< SPI RX CRC register (not used in I2S mode),         Address offset: 0x14 */
900   __IO uint32_t TXCRCR;     /*!< SPI TX CRC register (not used in I2S mode),         Address offset: 0x18 */
901   __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
902   __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
903 } SPI_TypeDef;
904 
905 /**
906   * @brief QUAD Serial Peripheral Interface
907   */
908 
909 typedef struct
910 {
911   __IO uint32_t CR;       /*!< QUADSPI Control register,                           Address offset: 0x00 */
912   __IO uint32_t DCR;      /*!< QUADSPI Device Configuration register,              Address offset: 0x04 */
913   __IO uint32_t SR;       /*!< QUADSPI Status register,                            Address offset: 0x08 */
914   __IO uint32_t FCR;      /*!< QUADSPI Flag Clear register,                        Address offset: 0x0C */
915   __IO uint32_t DLR;      /*!< QUADSPI Data Length register,                       Address offset: 0x10 */
916   __IO uint32_t CCR;      /*!< QUADSPI Communication Configuration register,       Address offset: 0x14 */
917   __IO uint32_t AR;       /*!< QUADSPI Address register,                           Address offset: 0x18 */
918   __IO uint32_t ABR;      /*!< QUADSPI Alternate Bytes register,                   Address offset: 0x1C */
919   __IO uint32_t DR;       /*!< QUADSPI Data register,                              Address offset: 0x20 */
920   __IO uint32_t PSMKR;    /*!< QUADSPI Polling Status Mask register,               Address offset: 0x24 */
921   __IO uint32_t PSMAR;    /*!< QUADSPI Polling Status Match register,              Address offset: 0x28 */
922   __IO uint32_t PIR;      /*!< QUADSPI Polling Interval register,                  Address offset: 0x2C */
923   __IO uint32_t LPTR;     /*!< QUADSPI Low Power Timeout register,                 Address offset: 0x30 */
924 } QUADSPI_TypeDef;
925 
926 /**
927   * @brief TIM
928   */
929 
930 typedef struct
931 {
932   __IO uint32_t CR1;         /*!< TIM control register 1,              Address offset: 0x00 */
933   __IO uint32_t CR2;         /*!< TIM control register 2,              Address offset: 0x04 */
934   __IO uint32_t SMCR;        /*!< TIM slave mode control register,     Address offset: 0x08 */
935   __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
936   __IO uint32_t SR;          /*!< TIM status register,                 Address offset: 0x10 */
937   __IO uint32_t EGR;         /*!< TIM event generation register,       Address offset: 0x14 */
938   __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
939   __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
940   __IO uint32_t CCER;        /*!< TIM capture/compare enable register, Address offset: 0x20 */
941   __IO uint32_t CNT;         /*!< TIM counter register,                Address offset: 0x24 */
942   __IO uint32_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */
943   __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */
944   __IO uint32_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */
945   __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */
946   __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */
947   __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */
948   __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */
949   __IO uint32_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */
950   __IO uint32_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */
951   __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
952   __IO uint32_t OR;          /*!< TIM option register,                 Address offset: 0x50 */
953 } TIM_TypeDef;
954 
955 /**
956   * @brief Universal Synchronous Asynchronous Receiver Transmitter
957   */
958 
959 typedef struct
960 {
961   __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
962   __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
963   __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
964   __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
965   __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
966   __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
967   __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
968 } USART_TypeDef;
969 
970 /**
971   * @brief Window WATCHDOG
972   */
973 
974 typedef struct
975 {
976   __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
977   __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
978   __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
979 } WWDG_TypeDef;
980 
981 /**
982   * @brief RNG
983   */
984 
985 typedef struct
986 {
987   __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
988   __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
989   __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
990 } RNG_TypeDef;
991 
992 /**
993   * @brief USB_OTG_Core_Registers
994   */
995 typedef struct
996 {
997   __IO uint32_t GOTGCTL;              /*!< USB_OTG Control and Status Register          000h */
998   __IO uint32_t GOTGINT;              /*!< USB_OTG Interrupt Register                   004h */
999   __IO uint32_t GAHBCFG;              /*!< Core AHB Configuration Register              008h */
1000   __IO uint32_t GUSBCFG;              /*!< Core USB Configuration Register              00Ch */
1001   __IO uint32_t GRSTCTL;              /*!< Core Reset Register                          010h */
1002   __IO uint32_t GINTSTS;              /*!< Core Interrupt Register                      014h */
1003   __IO uint32_t GINTMSK;              /*!< Core Interrupt Mask Register                 018h */
1004   __IO uint32_t GRXSTSR;              /*!< Receive Sts Q Read Register                  01Ch */
1005   __IO uint32_t GRXSTSP;              /*!< Receive Sts Q Read & POP Register            020h */
1006   __IO uint32_t GRXFSIZ;              /*!< Receive FIFO Size Register                   024h */
1007   __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!< EP0 / Non Periodic Tx FIFO Size Register     028h */
1008   __IO uint32_t HNPTXSTS;             /*!< Non Periodic Tx FIFO/Queue Sts reg           02Ch */
1009   uint32_t Reserved30[2];             /*!< Reserved                                     030h */
1010   __IO uint32_t GCCFG;                /*!< General Purpose IO Register                  038h */
1011   __IO uint32_t CID;                  /*!< User ID Register                             03Ch */
1012   uint32_t  Reserved5[3];             /*!< Reserved                                040h-048h */
1013   __IO uint32_t GHWCFG3;              /*!< User HW config3                              04Ch */
1014   uint32_t  Reserved6;                /*!< Reserved                                     050h */
1015   __IO uint32_t GLPMCFG;              /*!< LPM Register                                 054h */
1016   uint32_t  Reserved;                 /*!< Reserved                                     058h */
1017   __IO uint32_t GDFIFOCFG;            /*!< DFIFO Software Config Register               05Ch */
1018   uint32_t  Reserved43[40];           /*!< Reserved                                058h-0FFh */
1019   __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg               100h */
1020   __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO                        */
1021 } USB_OTG_GlobalTypeDef;
1022 
1023 /**
1024   * @brief USB_OTG_device_Registers
1025   */
1026 typedef struct
1027 {
1028   __IO uint32_t DCFG;            /*!< dev Configuration Register   800h */
1029   __IO uint32_t DCTL;            /*!< dev Control Register         804h */
1030   __IO uint32_t DSTS;            /*!< dev Status Register (RO)     808h */
1031   uint32_t Reserved0C;           /*!< Reserved                     80Ch */
1032   __IO uint32_t DIEPMSK;         /*!< dev IN Endpoint Mask         810h */
1033   __IO uint32_t DOEPMSK;         /*!< dev OUT Endpoint Mask        814h */
1034   __IO uint32_t DAINT;           /*!< dev All Endpoints Itr Reg    818h */
1035   __IO uint32_t DAINTMSK;        /*!< dev All Endpoints Itr Mask   81Ch */
1036   uint32_t  Reserved20;          /*!< Reserved                     820h */
1037   uint32_t Reserved9;            /*!< Reserved                     824h */
1038   __IO uint32_t DVBUSDIS;        /*!< dev VBUS discharge Register  828h */
1039   __IO uint32_t DVBUSPULSE;      /*!< dev VBUS Pulse Register      82Ch */
1040   __IO uint32_t DTHRCTL;         /*!< dev threshold                830h */
1041   __IO uint32_t DIEPEMPMSK;      /*!< dev empty msk                834h */
1042   __IO uint32_t DEACHINT;        /*!< dedicated EP interrupt       838h */
1043   __IO uint32_t DEACHMSK;        /*!< dedicated EP msk             83Ch */
1044   uint32_t Reserved40;           /*!< dedicated EP mask            840h */
1045   __IO uint32_t DINEP1MSK;       /*!< dedicated EP mask            844h */
1046   uint32_t  Reserved44[15];      /*!< Reserved                 844-87Ch */
1047   __IO uint32_t DOUTEP1MSK;      /*!< dedicated EP msk             884h */
1048 } USB_OTG_DeviceTypeDef;
1049 
1050 /**
1051   * @brief USB_OTG_IN_Endpoint-Specific_Register
1052   */
1053 typedef struct
1054 {
1055   __IO uint32_t DIEPCTL;           /*!< dev IN Endpoint Control Reg    900h + (ep_num * 20h) + 00h */
1056   uint32_t Reserved04;             /*!< Reserved                       900h + (ep_num * 20h) + 04h */
1057   __IO uint32_t DIEPINT;           /*!< dev IN Endpoint Itr Reg        900h + (ep_num * 20h) + 08h */
1058   uint32_t Reserved0C;             /*!< Reserved                       900h + (ep_num * 20h) + 0Ch */
1059   __IO uint32_t DIEPTSIZ;          /*!< IN Endpoint Txfer Size         900h + (ep_num * 20h) + 10h */
1060   __IO uint32_t DIEPDMA;           /*!< IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h */
1061   __IO uint32_t DTXFSTS;           /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
1062   uint32_t Reserved18;             /*!< Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
1063 } USB_OTG_INEndpointTypeDef;
1064 
1065 /**
1066   * @brief USB_OTG_OUT_Endpoint-Specific_Registers
1067   */
1068 typedef struct
1069 {
1070   __IO uint32_t DOEPCTL;       /*!< dev OUT Endpoint Control Reg           B00h + (ep_num * 20h) + 00h */
1071   uint32_t Reserved04;         /*!< Reserved                               B00h + (ep_num * 20h) + 04h */
1072   __IO uint32_t DOEPINT;       /*!< dev OUT Endpoint Itr Reg               B00h + (ep_num * 20h) + 08h */
1073   uint32_t Reserved0C;         /*!< Reserved                               B00h + (ep_num * 20h) + 0Ch */
1074   __IO uint32_t DOEPTSIZ;      /*!< dev OUT Endpoint Txfer Size            B00h + (ep_num * 20h) + 10h */
1075   __IO uint32_t DOEPDMA;       /*!< dev OUT Endpoint DMA Address           B00h + (ep_num * 20h) + 14h */
1076   uint32_t Reserved18[2];      /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
1077 } USB_OTG_OUTEndpointTypeDef;
1078 
1079 /**
1080   * @brief USB_OTG_Host_Mode_Register_Structures
1081   */
1082 typedef struct
1083 {
1084   __IO uint32_t HCFG;             /*!< Host Configuration Register          400h */
1085   __IO uint32_t HFIR;             /*!< Host Frame Interval Register         404h */
1086   __IO uint32_t HFNUM;            /*!< Host Frame Nbr/Frame Remaining       408h */
1087   uint32_t Reserved40C;           /*!< Reserved                             40Ch */
1088   __IO uint32_t HPTXSTS;          /*!< Host Periodic Tx FIFO/ Queue Status  410h */
1089   __IO uint32_t HAINT;            /*!< Host All Channels Interrupt Register 414h */
1090   __IO uint32_t HAINTMSK;         /*!< Host All Channels Interrupt Mask     418h */
1091 } USB_OTG_HostTypeDef;
1092 
1093 /**
1094   * @brief USB_OTG_Host_Channel_Specific_Registers
1095   */
1096 typedef struct
1097 {
1098   __IO uint32_t HCCHAR;           /*!< Host Channel Characteristics Register    500h */
1099   __IO uint32_t HCSPLT;           /*!< Host Channel Split Control Register      504h */
1100   __IO uint32_t HCINT;            /*!< Host Channel Interrupt Register          508h */
1101   __IO uint32_t HCINTMSK;         /*!< Host Channel Interrupt Mask Register     50Ch */
1102   __IO uint32_t HCTSIZ;           /*!< Host Channel Transfer Size Register      510h */
1103   __IO uint32_t HCDMA;            /*!< Host Channel DMA Address Register        514h */
1104   uint32_t Reserved[2];           /*!< Reserved                                      */
1105 } USB_OTG_HostChannelTypeDef;
1106 
1107 /**
1108   * @}
1109   */
1110 
1111 /** @addtogroup Peripheral_memory_map
1112   * @{
1113   */
1114 #define FLASH_BASE            0x08000000UL /*!< FLASH(up to 1 MB) base address in the alias region                         */
1115 #define CCMDATARAM_BASE       0x10000000UL /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region  */
1116 #define SRAM1_BASE            0x20000000UL /*!< SRAM1(160 KB) base address in the alias region                             */
1117 #define SRAM2_BASE            0x20028000UL /*!< SRAM2(32 KB) base address in the alias region                              */
1118 #define SRAM3_BASE            0x20030000UL /*!< SRAM3(128 KB) base address in the alias region                              */
1119 #define PERIPH_BASE           0x40000000UL /*!< Peripheral base address in the alias region                                */
1120 #define BKPSRAM_BASE          0x40024000UL /*!< Backup SRAM(4 KB) base address in the alias region                         */
1121 #define FMC_R_BASE            0xA0000000UL /*!< FMC registers base address                                                 */
1122 #define QSPI_R_BASE           0xA0001000UL /*!< QuadSPI registers base address                                             */
1123 #define SRAM1_BB_BASE         0x22000000UL /*!< SRAM1(112 KB) base address in the bit-band region                          */
1124 #define SRAM2_BB_BASE         0x22500000UL /*!< SRAM2(16 KB) base address in the bit-band region                           */
1125 #define SRAM3_BB_BASE         0x22600000UL /*!< SRAM3(64 KB) base address in the bit-band region                           */
1126 #define PERIPH_BB_BASE        0x42000000UL /*!< Peripheral base address in the bit-band region                             */
1127 #define BKPSRAM_BB_BASE       0x42480000UL /*!< Backup SRAM(4 KB) base address in the bit-band region                      */
1128 #define FLASH_END             0x081FFFFFUL /*!< FLASH end address                                                          */
1129 #define FLASH_OTP_BASE        0x1FFF7800UL /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area                */
1130 #define FLASH_OTP_END         0x1FFF7A0FUL /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area                 */
1131 #define CCMDATARAM_END        0x1000FFFFUL /*!< CCM data RAM end address                                                   */
1132 
1133 /* Legacy defines */
1134 #define SRAM_BASE             SRAM1_BASE
1135 #define SRAM_BB_BASE          SRAM1_BB_BASE
1136 
1137 /*!< Peripheral memory map */
1138 #define APB1PERIPH_BASE       PERIPH_BASE
1139 #define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)
1140 #define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)
1141 #define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000UL)
1142 
1143 /*!< APB1 peripherals */
1144 #define TIM2_BASE             (APB1PERIPH_BASE + 0x0000UL)
1145 #define TIM3_BASE             (APB1PERIPH_BASE + 0x0400UL)
1146 #define TIM4_BASE             (APB1PERIPH_BASE + 0x0800UL)
1147 #define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00UL)
1148 #define TIM6_BASE             (APB1PERIPH_BASE + 0x1000UL)
1149 #define TIM7_BASE             (APB1PERIPH_BASE + 0x1400UL)
1150 #define TIM12_BASE            (APB1PERIPH_BASE + 0x1800UL)
1151 #define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00UL)
1152 #define TIM14_BASE            (APB1PERIPH_BASE + 0x2000UL)
1153 #define RTC_BASE              (APB1PERIPH_BASE + 0x2800UL)
1154 #define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00UL)
1155 #define IWDG_BASE             (APB1PERIPH_BASE + 0x3000UL)
1156 #define I2S2ext_BASE          (APB1PERIPH_BASE + 0x3400UL)
1157 #define SPI2_BASE             (APB1PERIPH_BASE + 0x3800UL)
1158 #define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00UL)
1159 #define I2S3ext_BASE          (APB1PERIPH_BASE + 0x4000UL)
1160 #define USART2_BASE           (APB1PERIPH_BASE + 0x4400UL)
1161 #define USART3_BASE           (APB1PERIPH_BASE + 0x4800UL)
1162 #define UART4_BASE            (APB1PERIPH_BASE + 0x4C00UL)
1163 #define UART5_BASE            (APB1PERIPH_BASE + 0x5000UL)
1164 #define I2C1_BASE             (APB1PERIPH_BASE + 0x5400UL)
1165 #define I2C2_BASE             (APB1PERIPH_BASE + 0x5800UL)
1166 #define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00UL)
1167 #define CAN1_BASE             (APB1PERIPH_BASE + 0x6400UL)
1168 #define CAN2_BASE             (APB1PERIPH_BASE + 0x6800UL)
1169 #define PWR_BASE              (APB1PERIPH_BASE + 0x7000UL)
1170 #define DAC_BASE              (APB1PERIPH_BASE + 0x7400UL)
1171 #define UART7_BASE            (APB1PERIPH_BASE + 0x7800UL)
1172 #define UART8_BASE            (APB1PERIPH_BASE + 0x7C00UL)
1173 
1174 /*!< APB2 peripherals */
1175 #define TIM1_BASE             (APB2PERIPH_BASE + 0x0000UL)
1176 #define TIM8_BASE             (APB2PERIPH_BASE + 0x0400UL)
1177 #define USART1_BASE           (APB2PERIPH_BASE + 0x1000UL)
1178 #define USART6_BASE           (APB2PERIPH_BASE + 0x1400UL)
1179 #define ADC1_BASE             (APB2PERIPH_BASE + 0x2000UL)
1180 #define ADC2_BASE             (APB2PERIPH_BASE + 0x2100UL)
1181 #define ADC3_BASE             (APB2PERIPH_BASE + 0x2200UL)
1182 #define ADC123_COMMON_BASE    (APB2PERIPH_BASE + 0x2300UL)
1183 /* Legacy define */
1184 #define ADC_BASE               ADC123_COMMON_BASE
1185 #define SDIO_BASE             (APB2PERIPH_BASE + 0x2C00UL)
1186 #define SPI1_BASE             (APB2PERIPH_BASE + 0x3000UL)
1187 #define SPI4_BASE             (APB2PERIPH_BASE + 0x3400UL)
1188 #define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800UL)
1189 #define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00UL)
1190 #define TIM9_BASE             (APB2PERIPH_BASE + 0x4000UL)
1191 #define TIM10_BASE            (APB2PERIPH_BASE + 0x4400UL)
1192 #define TIM11_BASE            (APB2PERIPH_BASE + 0x4800UL)
1193 #define SPI5_BASE             (APB2PERIPH_BASE + 0x5000UL)
1194 #define SPI6_BASE             (APB2PERIPH_BASE + 0x5400UL)
1195 #define SAI1_BASE             (APB2PERIPH_BASE + 0x5800UL)
1196 #define SAI1_Block_A_BASE     (SAI1_BASE + 0x004UL)
1197 #define SAI1_Block_B_BASE     (SAI1_BASE + 0x024UL)
1198 #define LTDC_BASE             (APB2PERIPH_BASE + 0x6800UL)
1199 #define LTDC_Layer1_BASE      (LTDC_BASE + 0x84UL)
1200 #define LTDC_Layer2_BASE      (LTDC_BASE + 0x104UL)
1201 #define DSI_BASE              (APB2PERIPH_BASE + 0x6C00UL)
1202 
1203 /*!< AHB1 peripherals */
1204 #define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000UL)
1205 #define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400UL)
1206 #define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800UL)
1207 #define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00UL)
1208 #define GPIOE_BASE            (AHB1PERIPH_BASE + 0x1000UL)
1209 #define GPIOF_BASE            (AHB1PERIPH_BASE + 0x1400UL)
1210 #define GPIOG_BASE            (AHB1PERIPH_BASE + 0x1800UL)
1211 #define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00UL)
1212 #define GPIOI_BASE            (AHB1PERIPH_BASE + 0x2000UL)
1213 #define GPIOJ_BASE            (AHB1PERIPH_BASE + 0x2400UL)
1214 #define GPIOK_BASE            (AHB1PERIPH_BASE + 0x2800UL)
1215 #define CRC_BASE              (AHB1PERIPH_BASE + 0x3000UL)
1216 #define RCC_BASE              (AHB1PERIPH_BASE + 0x3800UL)
1217 #define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00UL)
1218 #define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000UL)
1219 #define DMA1_Stream0_BASE     (DMA1_BASE + 0x010UL)
1220 #define DMA1_Stream1_BASE     (DMA1_BASE + 0x028UL)
1221 #define DMA1_Stream2_BASE     (DMA1_BASE + 0x040UL)
1222 #define DMA1_Stream3_BASE     (DMA1_BASE + 0x058UL)
1223 #define DMA1_Stream4_BASE     (DMA1_BASE + 0x070UL)
1224 #define DMA1_Stream5_BASE     (DMA1_BASE + 0x088UL)
1225 #define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0UL)
1226 #define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8UL)
1227 #define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400UL)
1228 #define DMA2_Stream0_BASE     (DMA2_BASE + 0x010UL)
1229 #define DMA2_Stream1_BASE     (DMA2_BASE + 0x028UL)
1230 #define DMA2_Stream2_BASE     (DMA2_BASE + 0x040UL)
1231 #define DMA2_Stream3_BASE     (DMA2_BASE + 0x058UL)
1232 #define DMA2_Stream4_BASE     (DMA2_BASE + 0x070UL)
1233 #define DMA2_Stream5_BASE     (DMA2_BASE + 0x088UL)
1234 #define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0UL)
1235 #define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8UL)
1236 #define ETH_BASE              (AHB1PERIPH_BASE + 0x8000UL)
1237 #define ETH_MAC_BASE          (ETH_BASE)
1238 #define ETH_MMC_BASE          (ETH_BASE + 0x0100UL)
1239 #define ETH_PTP_BASE          (ETH_BASE + 0x0700UL)
1240 #define ETH_DMA_BASE          (ETH_BASE + 0x1000UL)
1241 #define DMA2D_BASE            (AHB1PERIPH_BASE + 0xB000UL)
1242 
1243 /*!< AHB2 peripherals */
1244 #define DCMI_BASE             (AHB2PERIPH_BASE + 0x50000UL)
1245 #define RNG_BASE              (AHB2PERIPH_BASE + 0x60800UL)
1246 
1247 /*!< FMC Bankx registers base address */
1248 #define FMC_Bank1_R_BASE      (FMC_R_BASE + 0x0000UL)
1249 #define FMC_Bank1E_R_BASE     (FMC_R_BASE + 0x0104UL)
1250 #define FMC_Bank3_R_BASE      (FMC_R_BASE + 0x0080UL)
1251 #define FMC_Bank5_6_R_BASE    (FMC_R_BASE + 0x0140UL)
1252 
1253 
1254 /*!< Debug MCU registers base address */
1255 #define DBGMCU_BASE           0xE0042000UL
1256 /*!< USB registers base address */
1257 #define USB_OTG_HS_PERIPH_BASE               0x40040000UL
1258 #define USB_OTG_FS_PERIPH_BASE               0x50000000UL
1259 
1260 #define USB_OTG_GLOBAL_BASE                  0x000UL
1261 #define USB_OTG_DEVICE_BASE                  0x800UL
1262 #define USB_OTG_IN_ENDPOINT_BASE             0x900UL
1263 #define USB_OTG_OUT_ENDPOINT_BASE            0xB00UL
1264 #define USB_OTG_EP_REG_SIZE                  0x20UL
1265 #define USB_OTG_HOST_BASE                    0x400UL
1266 #define USB_OTG_HOST_PORT_BASE               0x440UL
1267 #define USB_OTG_HOST_CHANNEL_BASE            0x500UL
1268 #define USB_OTG_HOST_CHANNEL_SIZE            0x20UL
1269 #define USB_OTG_PCGCCTL_BASE                 0xE00UL
1270 #define USB_OTG_FIFO_BASE                    0x1000UL
1271 #define USB_OTG_FIFO_SIZE                    0x1000UL
1272 
1273 #define UID_BASE                     0x1FFF7A10UL           /*!< Unique device ID register base address */
1274 #define FLASHSIZE_BASE               0x1FFF7A22UL           /*!< FLASH Size register base address       */
1275 #define PACKAGE_BASE                 0x1FFF7BF0UL           /*!< Package size register base address     */
1276 /**
1277   * @}
1278   */
1279 
1280 /** @addtogroup Peripheral_declaration
1281   * @{
1282   */
1283 #define TIM2                ((TIM_TypeDef *) TIM2_BASE)
1284 #define TIM3                ((TIM_TypeDef *) TIM3_BASE)
1285 #define TIM4                ((TIM_TypeDef *) TIM4_BASE)
1286 #define TIM5                ((TIM_TypeDef *) TIM5_BASE)
1287 #define TIM6                ((TIM_TypeDef *) TIM6_BASE)
1288 #define TIM7                ((TIM_TypeDef *) TIM7_BASE)
1289 #define TIM12               ((TIM_TypeDef *) TIM12_BASE)
1290 #define TIM13               ((TIM_TypeDef *) TIM13_BASE)
1291 #define TIM14               ((TIM_TypeDef *) TIM14_BASE)
1292 #define RTC                 ((RTC_TypeDef *) RTC_BASE)
1293 #define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
1294 #define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
1295 #define I2S2ext             ((SPI_TypeDef *) I2S2ext_BASE)
1296 #define SPI2                ((SPI_TypeDef *) SPI2_BASE)
1297 #define SPI3                ((SPI_TypeDef *) SPI3_BASE)
1298 #define I2S3ext             ((SPI_TypeDef *) I2S3ext_BASE)
1299 #define USART2              ((USART_TypeDef *) USART2_BASE)
1300 #define USART3              ((USART_TypeDef *) USART3_BASE)
1301 #define UART4               ((USART_TypeDef *) UART4_BASE)
1302 #define UART5               ((USART_TypeDef *) UART5_BASE)
1303 #define I2C1                ((I2C_TypeDef *) I2C1_BASE)
1304 #define I2C2                ((I2C_TypeDef *) I2C2_BASE)
1305 #define I2C3                ((I2C_TypeDef *) I2C3_BASE)
1306 #define CAN1                ((CAN_TypeDef *) CAN1_BASE)
1307 #define CAN2                ((CAN_TypeDef *) CAN2_BASE)
1308 #define PWR                 ((PWR_TypeDef *) PWR_BASE)
1309 #define DAC1                ((DAC_TypeDef *) DAC_BASE)
1310 #define DAC                 ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
1311 #define UART7               ((USART_TypeDef *) UART7_BASE)
1312 #define UART8               ((USART_TypeDef *) UART8_BASE)
1313 #define TIM1                ((TIM_TypeDef *) TIM1_BASE)
1314 #define TIM8                ((TIM_TypeDef *) TIM8_BASE)
1315 #define USART1              ((USART_TypeDef *) USART1_BASE)
1316 #define USART6              ((USART_TypeDef *) USART6_BASE)
1317 #define ADC1                ((ADC_TypeDef *) ADC1_BASE)
1318 #define ADC2                ((ADC_TypeDef *) ADC2_BASE)
1319 #define ADC3                ((ADC_TypeDef *) ADC3_BASE)
1320 #define ADC123_COMMON       ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)
1321 /* Legacy define */
1322 #define ADC                  ADC123_COMMON
1323 #define SDIO                ((SDIO_TypeDef *) SDIO_BASE)
1324 #define SPI1                ((SPI_TypeDef *) SPI1_BASE)
1325 #define SPI4                ((SPI_TypeDef *) SPI4_BASE)
1326 #define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
1327 #define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
1328 #define TIM9                ((TIM_TypeDef *) TIM9_BASE)
1329 #define TIM10               ((TIM_TypeDef *) TIM10_BASE)
1330 #define TIM11               ((TIM_TypeDef *) TIM11_BASE)
1331 #define SPI5                ((SPI_TypeDef *) SPI5_BASE)
1332 #define SPI6                ((SPI_TypeDef *) SPI6_BASE)
1333 #define SAI1                ((SAI_TypeDef *) SAI1_BASE)
1334 #define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
1335 #define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
1336 #define LTDC                ((LTDC_TypeDef *)LTDC_BASE)
1337 #define LTDC_Layer1         ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
1338 #define LTDC_Layer2         ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
1339 #define DSI                 ((DSI_TypeDef *)DSI_BASE)
1340 #define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
1341 #define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
1342 #define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
1343 #define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
1344 #define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
1345 #define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
1346 #define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
1347 #define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
1348 #define GPIOI               ((GPIO_TypeDef *) GPIOI_BASE)
1349 #define GPIOJ               ((GPIO_TypeDef *) GPIOJ_BASE)
1350 #define GPIOK               ((GPIO_TypeDef *) GPIOK_BASE)
1351 #define CRC                 ((CRC_TypeDef *) CRC_BASE)
1352 #define RCC                 ((RCC_TypeDef *) RCC_BASE)
1353 #define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
1354 #define DMA1                ((DMA_TypeDef *) DMA1_BASE)
1355 #define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
1356 #define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
1357 #define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
1358 #define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
1359 #define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
1360 #define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
1361 #define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
1362 #define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
1363 #define DMA2                ((DMA_TypeDef *) DMA2_BASE)
1364 #define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
1365 #define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
1366 #define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
1367 #define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
1368 #define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
1369 #define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
1370 #define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
1371 #define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
1372 #define ETH                 ((ETH_TypeDef *) ETH_BASE)
1373 #define DMA2D               ((DMA2D_TypeDef *)DMA2D_BASE)
1374 #define DCMI                ((DCMI_TypeDef *) DCMI_BASE)
1375 #define RNG                 ((RNG_TypeDef *) RNG_BASE)
1376 #define FMC_Bank1           ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
1377 #define FMC_Bank1E          ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
1378 #define FMC_Bank3           ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
1379 #define FMC_Bank5_6         ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
1380 #define QUADSPI             ((QUADSPI_TypeDef *) QSPI_R_BASE)
1381 #define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
1382 #define USB_OTG_FS          ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
1383 #define USB_OTG_HS          ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
1384 
1385 /**
1386   * @}
1387   */
1388 
1389 /** @addtogroup Exported_constants
1390   * @{
1391   */
1392 
1393   /** @addtogroup Peripheral_Registers_Bits_Definition
1394   * @{
1395   */
1396 
1397 /******************************************************************************/
1398 /*                         Peripheral Registers_Bits_Definition               */
1399 /******************************************************************************/
1400 
1401 /******************************************************************************/
1402 /*                                                                            */
1403 /*                        Analog to Digital Converter                         */
1404 /*                                                                            */
1405 /******************************************************************************/
1406 /*
1407  * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
1408  */
1409 #define ADC_MULTIMODE_SUPPORT                                                  /*!<ADC Multimode feature available on specific devices */
1410 
1411 /********************  Bit definition for ADC_SR register  ********************/
1412 #define ADC_SR_AWD_Pos            (0U)
1413 #define ADC_SR_AWD_Msk            (0x1UL << ADC_SR_AWD_Pos)                     /*!< 0x00000001 */
1414 #define ADC_SR_AWD                ADC_SR_AWD_Msk                               /*!<Analog watchdog flag */
1415 #define ADC_SR_EOC_Pos            (1U)
1416 #define ADC_SR_EOC_Msk            (0x1UL << ADC_SR_EOC_Pos)                     /*!< 0x00000002 */
1417 #define ADC_SR_EOC                ADC_SR_EOC_Msk                               /*!<End of conversion */
1418 #define ADC_SR_JEOC_Pos           (2U)
1419 #define ADC_SR_JEOC_Msk           (0x1UL << ADC_SR_JEOC_Pos)                    /*!< 0x00000004 */
1420 #define ADC_SR_JEOC               ADC_SR_JEOC_Msk                              /*!<Injected channel end of conversion */
1421 #define ADC_SR_JSTRT_Pos          (3U)
1422 #define ADC_SR_JSTRT_Msk          (0x1UL << ADC_SR_JSTRT_Pos)                   /*!< 0x00000008 */
1423 #define ADC_SR_JSTRT              ADC_SR_JSTRT_Msk                             /*!<Injected channel Start flag */
1424 #define ADC_SR_STRT_Pos           (4U)
1425 #define ADC_SR_STRT_Msk           (0x1UL << ADC_SR_STRT_Pos)                    /*!< 0x00000010 */
1426 #define ADC_SR_STRT               ADC_SR_STRT_Msk                              /*!<Regular channel Start flag */
1427 #define ADC_SR_OVR_Pos            (5U)
1428 #define ADC_SR_OVR_Msk            (0x1UL << ADC_SR_OVR_Pos)                     /*!< 0x00000020 */
1429 #define ADC_SR_OVR                ADC_SR_OVR_Msk                               /*!<Overrun flag */
1430 
1431 /*******************  Bit definition for ADC_CR1 register  ********************/
1432 #define ADC_CR1_AWDCH_Pos         (0U)
1433 #define ADC_CR1_AWDCH_Msk         (0x1FUL << ADC_CR1_AWDCH_Pos)                 /*!< 0x0000001F */
1434 #define ADC_CR1_AWDCH             ADC_CR1_AWDCH_Msk                            /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
1435 #define ADC_CR1_AWDCH_0           (0x01UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000001 */
1436 #define ADC_CR1_AWDCH_1           (0x02UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000002 */
1437 #define ADC_CR1_AWDCH_2           (0x04UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000004 */
1438 #define ADC_CR1_AWDCH_3           (0x08UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000008 */
1439 #define ADC_CR1_AWDCH_4           (0x10UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000010 */
1440 #define ADC_CR1_EOCIE_Pos         (5U)
1441 #define ADC_CR1_EOCIE_Msk         (0x1UL << ADC_CR1_EOCIE_Pos)                  /*!< 0x00000020 */
1442 #define ADC_CR1_EOCIE             ADC_CR1_EOCIE_Msk                            /*!<Interrupt enable for EOC */
1443 #define ADC_CR1_AWDIE_Pos         (6U)
1444 #define ADC_CR1_AWDIE_Msk         (0x1UL << ADC_CR1_AWDIE_Pos)                  /*!< 0x00000040 */
1445 #define ADC_CR1_AWDIE             ADC_CR1_AWDIE_Msk                            /*!<AAnalog Watchdog interrupt enable */
1446 #define ADC_CR1_JEOCIE_Pos        (7U)
1447 #define ADC_CR1_JEOCIE_Msk        (0x1UL << ADC_CR1_JEOCIE_Pos)                 /*!< 0x00000080 */
1448 #define ADC_CR1_JEOCIE            ADC_CR1_JEOCIE_Msk                           /*!<Interrupt enable for injected channels */
1449 #define ADC_CR1_SCAN_Pos          (8U)
1450 #define ADC_CR1_SCAN_Msk          (0x1UL << ADC_CR1_SCAN_Pos)                   /*!< 0x00000100 */
1451 #define ADC_CR1_SCAN              ADC_CR1_SCAN_Msk                             /*!<Scan mode */
1452 #define ADC_CR1_AWDSGL_Pos        (9U)
1453 #define ADC_CR1_AWDSGL_Msk        (0x1UL << ADC_CR1_AWDSGL_Pos)                 /*!< 0x00000200 */
1454 #define ADC_CR1_AWDSGL            ADC_CR1_AWDSGL_Msk                           /*!<Enable the watchdog on a single channel in scan mode */
1455 #define ADC_CR1_JAUTO_Pos         (10U)
1456 #define ADC_CR1_JAUTO_Msk         (0x1UL << ADC_CR1_JAUTO_Pos)                  /*!< 0x00000400 */
1457 #define ADC_CR1_JAUTO             ADC_CR1_JAUTO_Msk                            /*!<Automatic injected group conversion */
1458 #define ADC_CR1_DISCEN_Pos        (11U)
1459 #define ADC_CR1_DISCEN_Msk        (0x1UL << ADC_CR1_DISCEN_Pos)                 /*!< 0x00000800 */
1460 #define ADC_CR1_DISCEN            ADC_CR1_DISCEN_Msk                           /*!<Discontinuous mode on regular channels */
1461 #define ADC_CR1_JDISCEN_Pos       (12U)
1462 #define ADC_CR1_JDISCEN_Msk       (0x1UL << ADC_CR1_JDISCEN_Pos)                /*!< 0x00001000 */
1463 #define ADC_CR1_JDISCEN           ADC_CR1_JDISCEN_Msk                          /*!<Discontinuous mode on injected channels */
1464 #define ADC_CR1_DISCNUM_Pos       (13U)
1465 #define ADC_CR1_DISCNUM_Msk       (0x7UL << ADC_CR1_DISCNUM_Pos)                /*!< 0x0000E000 */
1466 #define ADC_CR1_DISCNUM           ADC_CR1_DISCNUM_Msk                          /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
1467 #define ADC_CR1_DISCNUM_0         (0x1UL << ADC_CR1_DISCNUM_Pos)                /*!< 0x00002000 */
1468 #define ADC_CR1_DISCNUM_1         (0x2UL << ADC_CR1_DISCNUM_Pos)                /*!< 0x00004000 */
1469 #define ADC_CR1_DISCNUM_2         (0x4UL << ADC_CR1_DISCNUM_Pos)                /*!< 0x00008000 */
1470 #define ADC_CR1_JAWDEN_Pos        (22U)
1471 #define ADC_CR1_JAWDEN_Msk        (0x1UL << ADC_CR1_JAWDEN_Pos)                 /*!< 0x00400000 */
1472 #define ADC_CR1_JAWDEN            ADC_CR1_JAWDEN_Msk                           /*!<Analog watchdog enable on injected channels */
1473 #define ADC_CR1_AWDEN_Pos         (23U)
1474 #define ADC_CR1_AWDEN_Msk         (0x1UL << ADC_CR1_AWDEN_Pos)                  /*!< 0x00800000 */
1475 #define ADC_CR1_AWDEN             ADC_CR1_AWDEN_Msk                            /*!<Analog watchdog enable on regular channels */
1476 #define ADC_CR1_RES_Pos           (24U)
1477 #define ADC_CR1_RES_Msk           (0x3UL << ADC_CR1_RES_Pos)                    /*!< 0x03000000 */
1478 #define ADC_CR1_RES               ADC_CR1_RES_Msk                              /*!<RES[2:0] bits (Resolution) */
1479 #define ADC_CR1_RES_0             (0x1UL << ADC_CR1_RES_Pos)                    /*!< 0x01000000 */
1480 #define ADC_CR1_RES_1             (0x2UL << ADC_CR1_RES_Pos)                    /*!< 0x02000000 */
1481 #define ADC_CR1_OVRIE_Pos         (26U)
1482 #define ADC_CR1_OVRIE_Msk         (0x1UL << ADC_CR1_OVRIE_Pos)                  /*!< 0x04000000 */
1483 #define ADC_CR1_OVRIE             ADC_CR1_OVRIE_Msk                            /*!<overrun interrupt enable */
1484 
1485 /*******************  Bit definition for ADC_CR2 register  ********************/
1486 #define ADC_CR2_ADON_Pos          (0U)
1487 #define ADC_CR2_ADON_Msk          (0x1UL << ADC_CR2_ADON_Pos)                   /*!< 0x00000001 */
1488 #define ADC_CR2_ADON              ADC_CR2_ADON_Msk                             /*!<A/D Converter ON / OFF */
1489 #define ADC_CR2_CONT_Pos          (1U)
1490 #define ADC_CR2_CONT_Msk          (0x1UL << ADC_CR2_CONT_Pos)                   /*!< 0x00000002 */
1491 #define ADC_CR2_CONT              ADC_CR2_CONT_Msk                             /*!<Continuous Conversion */
1492 #define ADC_CR2_DMA_Pos           (8U)
1493 #define ADC_CR2_DMA_Msk           (0x1UL << ADC_CR2_DMA_Pos)                    /*!< 0x00000100 */
1494 #define ADC_CR2_DMA               ADC_CR2_DMA_Msk                              /*!<Direct Memory access mode */
1495 #define ADC_CR2_DDS_Pos           (9U)
1496 #define ADC_CR2_DDS_Msk           (0x1UL << ADC_CR2_DDS_Pos)                    /*!< 0x00000200 */
1497 #define ADC_CR2_DDS               ADC_CR2_DDS_Msk                              /*!<DMA disable selection (Single ADC) */
1498 #define ADC_CR2_EOCS_Pos          (10U)
1499 #define ADC_CR2_EOCS_Msk          (0x1UL << ADC_CR2_EOCS_Pos)                   /*!< 0x00000400 */
1500 #define ADC_CR2_EOCS              ADC_CR2_EOCS_Msk                             /*!<End of conversion selection */
1501 #define ADC_CR2_ALIGN_Pos         (11U)
1502 #define ADC_CR2_ALIGN_Msk         (0x1UL << ADC_CR2_ALIGN_Pos)                  /*!< 0x00000800 */
1503 #define ADC_CR2_ALIGN             ADC_CR2_ALIGN_Msk                            /*!<Data Alignment */
1504 #define ADC_CR2_JEXTSEL_Pos       (16U)
1505 #define ADC_CR2_JEXTSEL_Msk       (0xFUL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x000F0000 */
1506 #define ADC_CR2_JEXTSEL           ADC_CR2_JEXTSEL_Msk                          /*!<JEXTSEL[3:0] bits (External event select for injected group) */
1507 #define ADC_CR2_JEXTSEL_0         (0x1UL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00010000 */
1508 #define ADC_CR2_JEXTSEL_1         (0x2UL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00020000 */
1509 #define ADC_CR2_JEXTSEL_2         (0x4UL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00040000 */
1510 #define ADC_CR2_JEXTSEL_3         (0x8UL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00080000 */
1511 #define ADC_CR2_JEXTEN_Pos        (20U)
1512 #define ADC_CR2_JEXTEN_Msk        (0x3UL << ADC_CR2_JEXTEN_Pos)                 /*!< 0x00300000 */
1513 #define ADC_CR2_JEXTEN            ADC_CR2_JEXTEN_Msk                           /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
1514 #define ADC_CR2_JEXTEN_0          (0x1UL << ADC_CR2_JEXTEN_Pos)                 /*!< 0x00100000 */
1515 #define ADC_CR2_JEXTEN_1          (0x2UL << ADC_CR2_JEXTEN_Pos)                 /*!< 0x00200000 */
1516 #define ADC_CR2_JSWSTART_Pos      (22U)
1517 #define ADC_CR2_JSWSTART_Msk      (0x1UL << ADC_CR2_JSWSTART_Pos)               /*!< 0x00400000 */
1518 #define ADC_CR2_JSWSTART          ADC_CR2_JSWSTART_Msk                         /*!<Start Conversion of injected channels */
1519 #define ADC_CR2_EXTSEL_Pos        (24U)
1520 #define ADC_CR2_EXTSEL_Msk        (0xFUL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x0F000000 */
1521 #define ADC_CR2_EXTSEL            ADC_CR2_EXTSEL_Msk                           /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
1522 #define ADC_CR2_EXTSEL_0          (0x1UL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x01000000 */
1523 #define ADC_CR2_EXTSEL_1          (0x2UL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x02000000 */
1524 #define ADC_CR2_EXTSEL_2          (0x4UL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x04000000 */
1525 #define ADC_CR2_EXTSEL_3          (0x8UL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x08000000 */
1526 #define ADC_CR2_EXTEN_Pos         (28U)
1527 #define ADC_CR2_EXTEN_Msk         (0x3UL << ADC_CR2_EXTEN_Pos)                  /*!< 0x30000000 */
1528 #define ADC_CR2_EXTEN             ADC_CR2_EXTEN_Msk                            /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
1529 #define ADC_CR2_EXTEN_0           (0x1UL << ADC_CR2_EXTEN_Pos)                  /*!< 0x10000000 */
1530 #define ADC_CR2_EXTEN_1           (0x2UL << ADC_CR2_EXTEN_Pos)                  /*!< 0x20000000 */
1531 #define ADC_CR2_SWSTART_Pos       (30U)
1532 #define ADC_CR2_SWSTART_Msk       (0x1UL << ADC_CR2_SWSTART_Pos)                /*!< 0x40000000 */
1533 #define ADC_CR2_SWSTART           ADC_CR2_SWSTART_Msk                          /*!<Start Conversion of regular channels */
1534 
1535 /******************  Bit definition for ADC_SMPR1 register  *******************/
1536 #define ADC_SMPR1_SMP10_Pos       (0U)
1537 #define ADC_SMPR1_SMP10_Msk       (0x7UL << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000007 */
1538 #define ADC_SMPR1_SMP10           ADC_SMPR1_SMP10_Msk                          /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
1539 #define ADC_SMPR1_SMP10_0         (0x1UL << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000001 */
1540 #define ADC_SMPR1_SMP10_1         (0x2UL << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000002 */
1541 #define ADC_SMPR1_SMP10_2         (0x4UL << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000004 */
1542 #define ADC_SMPR1_SMP11_Pos       (3U)
1543 #define ADC_SMPR1_SMP11_Msk       (0x7UL << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000038 */
1544 #define ADC_SMPR1_SMP11           ADC_SMPR1_SMP11_Msk                          /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
1545 #define ADC_SMPR1_SMP11_0         (0x1UL << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000008 */
1546 #define ADC_SMPR1_SMP11_1         (0x2UL << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000010 */
1547 #define ADC_SMPR1_SMP11_2         (0x4UL << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000020 */
1548 #define ADC_SMPR1_SMP12_Pos       (6U)
1549 #define ADC_SMPR1_SMP12_Msk       (0x7UL << ADC_SMPR1_SMP12_Pos)                /*!< 0x000001C0 */
1550 #define ADC_SMPR1_SMP12           ADC_SMPR1_SMP12_Msk                          /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
1551 #define ADC_SMPR1_SMP12_0         (0x1UL << ADC_SMPR1_SMP12_Pos)                /*!< 0x00000040 */
1552 #define ADC_SMPR1_SMP12_1         (0x2UL << ADC_SMPR1_SMP12_Pos)                /*!< 0x00000080 */
1553 #define ADC_SMPR1_SMP12_2         (0x4UL << ADC_SMPR1_SMP12_Pos)                /*!< 0x00000100 */
1554 #define ADC_SMPR1_SMP13_Pos       (9U)
1555 #define ADC_SMPR1_SMP13_Msk       (0x7UL << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000E00 */
1556 #define ADC_SMPR1_SMP13           ADC_SMPR1_SMP13_Msk                          /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
1557 #define ADC_SMPR1_SMP13_0         (0x1UL << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000200 */
1558 #define ADC_SMPR1_SMP13_1         (0x2UL << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000400 */
1559 #define ADC_SMPR1_SMP13_2         (0x4UL << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000800 */
1560 #define ADC_SMPR1_SMP14_Pos       (12U)
1561 #define ADC_SMPR1_SMP14_Msk       (0x7UL << ADC_SMPR1_SMP14_Pos)                /*!< 0x00007000 */
1562 #define ADC_SMPR1_SMP14           ADC_SMPR1_SMP14_Msk                          /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
1563 #define ADC_SMPR1_SMP14_0         (0x1UL << ADC_SMPR1_SMP14_Pos)                /*!< 0x00001000 */
1564 #define ADC_SMPR1_SMP14_1         (0x2UL << ADC_SMPR1_SMP14_Pos)                /*!< 0x00002000 */
1565 #define ADC_SMPR1_SMP14_2         (0x4UL << ADC_SMPR1_SMP14_Pos)                /*!< 0x00004000 */
1566 #define ADC_SMPR1_SMP15_Pos       (15U)
1567 #define ADC_SMPR1_SMP15_Msk       (0x7UL << ADC_SMPR1_SMP15_Pos)                /*!< 0x00038000 */
1568 #define ADC_SMPR1_SMP15           ADC_SMPR1_SMP15_Msk                          /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
1569 #define ADC_SMPR1_SMP15_0         (0x1UL << ADC_SMPR1_SMP15_Pos)                /*!< 0x00008000 */
1570 #define ADC_SMPR1_SMP15_1         (0x2UL << ADC_SMPR1_SMP15_Pos)                /*!< 0x00010000 */
1571 #define ADC_SMPR1_SMP15_2         (0x4UL << ADC_SMPR1_SMP15_Pos)                /*!< 0x00020000 */
1572 #define ADC_SMPR1_SMP16_Pos       (18U)
1573 #define ADC_SMPR1_SMP16_Msk       (0x7UL << ADC_SMPR1_SMP16_Pos)                /*!< 0x001C0000 */
1574 #define ADC_SMPR1_SMP16           ADC_SMPR1_SMP16_Msk                          /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
1575 #define ADC_SMPR1_SMP16_0         (0x1UL << ADC_SMPR1_SMP16_Pos)                /*!< 0x00040000 */
1576 #define ADC_SMPR1_SMP16_1         (0x2UL << ADC_SMPR1_SMP16_Pos)                /*!< 0x00080000 */
1577 #define ADC_SMPR1_SMP16_2         (0x4UL << ADC_SMPR1_SMP16_Pos)                /*!< 0x00100000 */
1578 #define ADC_SMPR1_SMP17_Pos       (21U)
1579 #define ADC_SMPR1_SMP17_Msk       (0x7UL << ADC_SMPR1_SMP17_Pos)                /*!< 0x00E00000 */
1580 #define ADC_SMPR1_SMP17           ADC_SMPR1_SMP17_Msk                          /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
1581 #define ADC_SMPR1_SMP17_0         (0x1UL << ADC_SMPR1_SMP17_Pos)                /*!< 0x00200000 */
1582 #define ADC_SMPR1_SMP17_1         (0x2UL << ADC_SMPR1_SMP17_Pos)                /*!< 0x00400000 */
1583 #define ADC_SMPR1_SMP17_2         (0x4UL << ADC_SMPR1_SMP17_Pos)                /*!< 0x00800000 */
1584 #define ADC_SMPR1_SMP18_Pos       (24U)
1585 #define ADC_SMPR1_SMP18_Msk       (0x7UL << ADC_SMPR1_SMP18_Pos)                /*!< 0x07000000 */
1586 #define ADC_SMPR1_SMP18           ADC_SMPR1_SMP18_Msk                          /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
1587 #define ADC_SMPR1_SMP18_0         (0x1UL << ADC_SMPR1_SMP18_Pos)                /*!< 0x01000000 */
1588 #define ADC_SMPR1_SMP18_1         (0x2UL << ADC_SMPR1_SMP18_Pos)                /*!< 0x02000000 */
1589 #define ADC_SMPR1_SMP18_2         (0x4UL << ADC_SMPR1_SMP18_Pos)                /*!< 0x04000000 */
1590 
1591 /******************  Bit definition for ADC_SMPR2 register  *******************/
1592 #define ADC_SMPR2_SMP0_Pos        (0U)
1593 #define ADC_SMPR2_SMP0_Msk        (0x7UL << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000007 */
1594 #define ADC_SMPR2_SMP0            ADC_SMPR2_SMP0_Msk                           /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
1595 #define ADC_SMPR2_SMP0_0          (0x1UL << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000001 */
1596 #define ADC_SMPR2_SMP0_1          (0x2UL << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000002 */
1597 #define ADC_SMPR2_SMP0_2          (0x4UL << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000004 */
1598 #define ADC_SMPR2_SMP1_Pos        (3U)
1599 #define ADC_SMPR2_SMP1_Msk        (0x7UL << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000038 */
1600 #define ADC_SMPR2_SMP1            ADC_SMPR2_SMP1_Msk                           /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
1601 #define ADC_SMPR2_SMP1_0          (0x1UL << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000008 */
1602 #define ADC_SMPR2_SMP1_1          (0x2UL << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000010 */
1603 #define ADC_SMPR2_SMP1_2          (0x4UL << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000020 */
1604 #define ADC_SMPR2_SMP2_Pos        (6U)
1605 #define ADC_SMPR2_SMP2_Msk        (0x7UL << ADC_SMPR2_SMP2_Pos)                 /*!< 0x000001C0 */
1606 #define ADC_SMPR2_SMP2            ADC_SMPR2_SMP2_Msk                           /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
1607 #define ADC_SMPR2_SMP2_0          (0x1UL << ADC_SMPR2_SMP2_Pos)                 /*!< 0x00000040 */
1608 #define ADC_SMPR2_SMP2_1          (0x2UL << ADC_SMPR2_SMP2_Pos)                 /*!< 0x00000080 */
1609 #define ADC_SMPR2_SMP2_2          (0x4UL << ADC_SMPR2_SMP2_Pos)                 /*!< 0x00000100 */
1610 #define ADC_SMPR2_SMP3_Pos        (9U)
1611 #define ADC_SMPR2_SMP3_Msk        (0x7UL << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000E00 */
1612 #define ADC_SMPR2_SMP3            ADC_SMPR2_SMP3_Msk                           /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
1613 #define ADC_SMPR2_SMP3_0          (0x1UL << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000200 */
1614 #define ADC_SMPR2_SMP3_1          (0x2UL << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000400 */
1615 #define ADC_SMPR2_SMP3_2          (0x4UL << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000800 */
1616 #define ADC_SMPR2_SMP4_Pos        (12U)
1617 #define ADC_SMPR2_SMP4_Msk        (0x7UL << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00007000 */
1618 #define ADC_SMPR2_SMP4            ADC_SMPR2_SMP4_Msk                           /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
1619 #define ADC_SMPR2_SMP4_0          (0x1UL << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00001000 */
1620 #define ADC_SMPR2_SMP4_1          (0x2UL << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00002000 */
1621 #define ADC_SMPR2_SMP4_2          (0x4UL << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00004000 */
1622 #define ADC_SMPR2_SMP5_Pos        (15U)
1623 #define ADC_SMPR2_SMP5_Msk        (0x7UL << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00038000 */
1624 #define ADC_SMPR2_SMP5            ADC_SMPR2_SMP5_Msk                           /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
1625 #define ADC_SMPR2_SMP5_0          (0x1UL << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00008000 */
1626 #define ADC_SMPR2_SMP5_1          (0x2UL << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00010000 */
1627 #define ADC_SMPR2_SMP5_2          (0x4UL << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00020000 */
1628 #define ADC_SMPR2_SMP6_Pos        (18U)
1629 #define ADC_SMPR2_SMP6_Msk        (0x7UL << ADC_SMPR2_SMP6_Pos)                 /*!< 0x001C0000 */
1630 #define ADC_SMPR2_SMP6            ADC_SMPR2_SMP6_Msk                           /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
1631 #define ADC_SMPR2_SMP6_0          (0x1UL << ADC_SMPR2_SMP6_Pos)                 /*!< 0x00040000 */
1632 #define ADC_SMPR2_SMP6_1          (0x2UL << ADC_SMPR2_SMP6_Pos)                 /*!< 0x00080000 */
1633 #define ADC_SMPR2_SMP6_2          (0x4UL << ADC_SMPR2_SMP6_Pos)                 /*!< 0x00100000 */
1634 #define ADC_SMPR2_SMP7_Pos        (21U)
1635 #define ADC_SMPR2_SMP7_Msk        (0x7UL << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00E00000 */
1636 #define ADC_SMPR2_SMP7            ADC_SMPR2_SMP7_Msk                           /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
1637 #define ADC_SMPR2_SMP7_0          (0x1UL << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00200000 */
1638 #define ADC_SMPR2_SMP7_1          (0x2UL << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00400000 */
1639 #define ADC_SMPR2_SMP7_2          (0x4UL << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00800000 */
1640 #define ADC_SMPR2_SMP8_Pos        (24U)
1641 #define ADC_SMPR2_SMP8_Msk        (0x7UL << ADC_SMPR2_SMP8_Pos)                 /*!< 0x07000000 */
1642 #define ADC_SMPR2_SMP8            ADC_SMPR2_SMP8_Msk                           /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
1643 #define ADC_SMPR2_SMP8_0          (0x1UL << ADC_SMPR2_SMP8_Pos)                 /*!< 0x01000000 */
1644 #define ADC_SMPR2_SMP8_1          (0x2UL << ADC_SMPR2_SMP8_Pos)                 /*!< 0x02000000 */
1645 #define ADC_SMPR2_SMP8_2          (0x4UL << ADC_SMPR2_SMP8_Pos)                 /*!< 0x04000000 */
1646 #define ADC_SMPR2_SMP9_Pos        (27U)
1647 #define ADC_SMPR2_SMP9_Msk        (0x7UL << ADC_SMPR2_SMP9_Pos)                 /*!< 0x38000000 */
1648 #define ADC_SMPR2_SMP9            ADC_SMPR2_SMP9_Msk                           /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
1649 #define ADC_SMPR2_SMP9_0          (0x1UL << ADC_SMPR2_SMP9_Pos)                 /*!< 0x08000000 */
1650 #define ADC_SMPR2_SMP9_1          (0x2UL << ADC_SMPR2_SMP9_Pos)                 /*!< 0x10000000 */
1651 #define ADC_SMPR2_SMP9_2          (0x4UL << ADC_SMPR2_SMP9_Pos)                 /*!< 0x20000000 */
1652 
1653 /******************  Bit definition for ADC_JOFR1 register  *******************/
1654 #define ADC_JOFR1_JOFFSET1_Pos    (0U)
1655 #define ADC_JOFR1_JOFFSET1_Msk    (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos)           /*!< 0x00000FFF */
1656 #define ADC_JOFR1_JOFFSET1        ADC_JOFR1_JOFFSET1_Msk                       /*!<Data offset for injected channel 1 */
1657 
1658 /******************  Bit definition for ADC_JOFR2 register  *******************/
1659 #define ADC_JOFR2_JOFFSET2_Pos    (0U)
1660 #define ADC_JOFR2_JOFFSET2_Msk    (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos)           /*!< 0x00000FFF */
1661 #define ADC_JOFR2_JOFFSET2        ADC_JOFR2_JOFFSET2_Msk                       /*!<Data offset for injected channel 2 */
1662 
1663 /******************  Bit definition for ADC_JOFR3 register  *******************/
1664 #define ADC_JOFR3_JOFFSET3_Pos    (0U)
1665 #define ADC_JOFR3_JOFFSET3_Msk    (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos)           /*!< 0x00000FFF */
1666 #define ADC_JOFR3_JOFFSET3        ADC_JOFR3_JOFFSET3_Msk                       /*!<Data offset for injected channel 3 */
1667 
1668 /******************  Bit definition for ADC_JOFR4 register  *******************/
1669 #define ADC_JOFR4_JOFFSET4_Pos    (0U)
1670 #define ADC_JOFR4_JOFFSET4_Msk    (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos)           /*!< 0x00000FFF */
1671 #define ADC_JOFR4_JOFFSET4        ADC_JOFR4_JOFFSET4_Msk                       /*!<Data offset for injected channel 4 */
1672 
1673 /*******************  Bit definition for ADC_HTR register  ********************/
1674 #define ADC_HTR_HT_Pos            (0U)
1675 #define ADC_HTR_HT_Msk            (0xFFFUL << ADC_HTR_HT_Pos)                   /*!< 0x00000FFF */
1676 #define ADC_HTR_HT                ADC_HTR_HT_Msk                               /*!<Analog watchdog high threshold */
1677 
1678 /*******************  Bit definition for ADC_LTR register  ********************/
1679 #define ADC_LTR_LT_Pos            (0U)
1680 #define ADC_LTR_LT_Msk            (0xFFFUL << ADC_LTR_LT_Pos)                   /*!< 0x00000FFF */
1681 #define ADC_LTR_LT                ADC_LTR_LT_Msk                               /*!<Analog watchdog low threshold */
1682 
1683 /*******************  Bit definition for ADC_SQR1 register  *******************/
1684 #define ADC_SQR1_SQ13_Pos         (0U)
1685 #define ADC_SQR1_SQ13_Msk         (0x1FUL << ADC_SQR1_SQ13_Pos)                 /*!< 0x0000001F */
1686 #define ADC_SQR1_SQ13             ADC_SQR1_SQ13_Msk                            /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
1687 #define ADC_SQR1_SQ13_0           (0x01UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000001 */
1688 #define ADC_SQR1_SQ13_1           (0x02UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000002 */
1689 #define ADC_SQR1_SQ13_2           (0x04UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000004 */
1690 #define ADC_SQR1_SQ13_3           (0x08UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000008 */
1691 #define ADC_SQR1_SQ13_4           (0x10UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000010 */
1692 #define ADC_SQR1_SQ14_Pos         (5U)
1693 #define ADC_SQR1_SQ14_Msk         (0x1FUL << ADC_SQR1_SQ14_Pos)                 /*!< 0x000003E0 */
1694 #define ADC_SQR1_SQ14             ADC_SQR1_SQ14_Msk                            /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
1695 #define ADC_SQR1_SQ14_0           (0x01UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000020 */
1696 #define ADC_SQR1_SQ14_1           (0x02UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000040 */
1697 #define ADC_SQR1_SQ14_2           (0x04UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000080 */
1698 #define ADC_SQR1_SQ14_3           (0x08UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000100 */
1699 #define ADC_SQR1_SQ14_4           (0x10UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000200 */
1700 #define ADC_SQR1_SQ15_Pos         (10U)
1701 #define ADC_SQR1_SQ15_Msk         (0x1FUL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00007C00 */
1702 #define ADC_SQR1_SQ15             ADC_SQR1_SQ15_Msk                            /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
1703 #define ADC_SQR1_SQ15_0           (0x01UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00000400 */
1704 #define ADC_SQR1_SQ15_1           (0x02UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00000800 */
1705 #define ADC_SQR1_SQ15_2           (0x04UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00001000 */
1706 #define ADC_SQR1_SQ15_3           (0x08UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00002000 */
1707 #define ADC_SQR1_SQ15_4           (0x10UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00004000 */
1708 #define ADC_SQR1_SQ16_Pos         (15U)
1709 #define ADC_SQR1_SQ16_Msk         (0x1FUL << ADC_SQR1_SQ16_Pos)                 /*!< 0x000F8000 */
1710 #define ADC_SQR1_SQ16             ADC_SQR1_SQ16_Msk                            /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
1711 #define ADC_SQR1_SQ16_0           (0x01UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00008000 */
1712 #define ADC_SQR1_SQ16_1           (0x02UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00010000 */
1713 #define ADC_SQR1_SQ16_2           (0x04UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00020000 */
1714 #define ADC_SQR1_SQ16_3           (0x08UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00040000 */
1715 #define ADC_SQR1_SQ16_4           (0x10UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00080000 */
1716 #define ADC_SQR1_L_Pos            (20U)
1717 #define ADC_SQR1_L_Msk            (0xFUL << ADC_SQR1_L_Pos)                     /*!< 0x00F00000 */
1718 #define ADC_SQR1_L                ADC_SQR1_L_Msk                               /*!<L[3:0] bits (Regular channel sequence length) */
1719 #define ADC_SQR1_L_0              (0x1UL << ADC_SQR1_L_Pos)                     /*!< 0x00100000 */
1720 #define ADC_SQR1_L_1              (0x2UL << ADC_SQR1_L_Pos)                     /*!< 0x00200000 */
1721 #define ADC_SQR1_L_2              (0x4UL << ADC_SQR1_L_Pos)                     /*!< 0x00400000 */
1722 #define ADC_SQR1_L_3              (0x8UL << ADC_SQR1_L_Pos)                     /*!< 0x00800000 */
1723 
1724 /*******************  Bit definition for ADC_SQR2 register  *******************/
1725 #define ADC_SQR2_SQ7_Pos          (0U)
1726 #define ADC_SQR2_SQ7_Msk          (0x1FUL << ADC_SQR2_SQ7_Pos)                  /*!< 0x0000001F */
1727 #define ADC_SQR2_SQ7              ADC_SQR2_SQ7_Msk                             /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
1728 #define ADC_SQR2_SQ7_0            (0x01UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000001 */
1729 #define ADC_SQR2_SQ7_1            (0x02UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000002 */
1730 #define ADC_SQR2_SQ7_2            (0x04UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000004 */
1731 #define ADC_SQR2_SQ7_3            (0x08UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000008 */
1732 #define ADC_SQR2_SQ7_4            (0x10UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000010 */
1733 #define ADC_SQR2_SQ8_Pos          (5U)
1734 #define ADC_SQR2_SQ8_Msk          (0x1FUL << ADC_SQR2_SQ8_Pos)                  /*!< 0x000003E0 */
1735 #define ADC_SQR2_SQ8              ADC_SQR2_SQ8_Msk                             /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
1736 #define ADC_SQR2_SQ8_0            (0x01UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000020 */
1737 #define ADC_SQR2_SQ8_1            (0x02UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000040 */
1738 #define ADC_SQR2_SQ8_2            (0x04UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000080 */
1739 #define ADC_SQR2_SQ8_3            (0x08UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000100 */
1740 #define ADC_SQR2_SQ8_4            (0x10UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000200 */
1741 #define ADC_SQR2_SQ9_Pos          (10U)
1742 #define ADC_SQR2_SQ9_Msk          (0x1FUL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00007C00 */
1743 #define ADC_SQR2_SQ9              ADC_SQR2_SQ9_Msk                             /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
1744 #define ADC_SQR2_SQ9_0            (0x01UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00000400 */
1745 #define ADC_SQR2_SQ9_1            (0x02UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00000800 */
1746 #define ADC_SQR2_SQ9_2            (0x04UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00001000 */
1747 #define ADC_SQR2_SQ9_3            (0x08UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00002000 */
1748 #define ADC_SQR2_SQ9_4            (0x10UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00004000 */
1749 #define ADC_SQR2_SQ10_Pos         (15U)
1750 #define ADC_SQR2_SQ10_Msk         (0x1FUL << ADC_SQR2_SQ10_Pos)                 /*!< 0x000F8000 */
1751 #define ADC_SQR2_SQ10             ADC_SQR2_SQ10_Msk                            /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
1752 #define ADC_SQR2_SQ10_0           (0x01UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00008000 */
1753 #define ADC_SQR2_SQ10_1           (0x02UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00010000 */
1754 #define ADC_SQR2_SQ10_2           (0x04UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00020000 */
1755 #define ADC_SQR2_SQ10_3           (0x08UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00040000 */
1756 #define ADC_SQR2_SQ10_4           (0x10UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00080000 */
1757 #define ADC_SQR2_SQ11_Pos         (20U)
1758 #define ADC_SQR2_SQ11_Msk         (0x1FUL << ADC_SQR2_SQ11_Pos)                 /*!< 0x01F00000 */
1759 #define ADC_SQR2_SQ11             ADC_SQR2_SQ11_Msk                            /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
1760 #define ADC_SQR2_SQ11_0           (0x01UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x00100000 */
1761 #define ADC_SQR2_SQ11_1           (0x02UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x00200000 */
1762 #define ADC_SQR2_SQ11_2           (0x04UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x00400000 */
1763 #define ADC_SQR2_SQ11_3           (0x08UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x00800000 */
1764 #define ADC_SQR2_SQ11_4           (0x10UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x01000000 */
1765 #define ADC_SQR2_SQ12_Pos         (25U)
1766 #define ADC_SQR2_SQ12_Msk         (0x1FUL << ADC_SQR2_SQ12_Pos)                 /*!< 0x3E000000 */
1767 #define ADC_SQR2_SQ12             ADC_SQR2_SQ12_Msk                            /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
1768 #define ADC_SQR2_SQ12_0           (0x01UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x02000000 */
1769 #define ADC_SQR2_SQ12_1           (0x02UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x04000000 */
1770 #define ADC_SQR2_SQ12_2           (0x04UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x08000000 */
1771 #define ADC_SQR2_SQ12_3           (0x08UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x10000000 */
1772 #define ADC_SQR2_SQ12_4           (0x10UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x20000000 */
1773 
1774 /*******************  Bit definition for ADC_SQR3 register  *******************/
1775 #define ADC_SQR3_SQ1_Pos          (0U)
1776 #define ADC_SQR3_SQ1_Msk          (0x1FUL << ADC_SQR3_SQ1_Pos)                  /*!< 0x0000001F */
1777 #define ADC_SQR3_SQ1              ADC_SQR3_SQ1_Msk                             /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
1778 #define ADC_SQR3_SQ1_0            (0x01UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000001 */
1779 #define ADC_SQR3_SQ1_1            (0x02UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000002 */
1780 #define ADC_SQR3_SQ1_2            (0x04UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000004 */
1781 #define ADC_SQR3_SQ1_3            (0x08UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000008 */
1782 #define ADC_SQR3_SQ1_4            (0x10UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000010 */
1783 #define ADC_SQR3_SQ2_Pos          (5U)
1784 #define ADC_SQR3_SQ2_Msk          (0x1FUL << ADC_SQR3_SQ2_Pos)                  /*!< 0x000003E0 */
1785 #define ADC_SQR3_SQ2              ADC_SQR3_SQ2_Msk                             /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
1786 #define ADC_SQR3_SQ2_0            (0x01UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000020 */
1787 #define ADC_SQR3_SQ2_1            (0x02UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000040 */
1788 #define ADC_SQR3_SQ2_2            (0x04UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000080 */
1789 #define ADC_SQR3_SQ2_3            (0x08UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000100 */
1790 #define ADC_SQR3_SQ2_4            (0x10UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000200 */
1791 #define ADC_SQR3_SQ3_Pos          (10U)
1792 #define ADC_SQR3_SQ3_Msk          (0x1FUL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00007C00 */
1793 #define ADC_SQR3_SQ3              ADC_SQR3_SQ3_Msk                             /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
1794 #define ADC_SQR3_SQ3_0            (0x01UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00000400 */
1795 #define ADC_SQR3_SQ3_1            (0x02UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00000800 */
1796 #define ADC_SQR3_SQ3_2            (0x04UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00001000 */
1797 #define ADC_SQR3_SQ3_3            (0x08UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00002000 */
1798 #define ADC_SQR3_SQ3_4            (0x10UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00004000 */
1799 #define ADC_SQR3_SQ4_Pos          (15U)
1800 #define ADC_SQR3_SQ4_Msk          (0x1FUL << ADC_SQR3_SQ4_Pos)                  /*!< 0x000F8000 */
1801 #define ADC_SQR3_SQ4              ADC_SQR3_SQ4_Msk                             /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
1802 #define ADC_SQR3_SQ4_0            (0x01UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00008000 */
1803 #define ADC_SQR3_SQ4_1            (0x02UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00010000 */
1804 #define ADC_SQR3_SQ4_2            (0x04UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00020000 */
1805 #define ADC_SQR3_SQ4_3            (0x08UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00040000 */
1806 #define ADC_SQR3_SQ4_4            (0x10UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00080000 */
1807 #define ADC_SQR3_SQ5_Pos          (20U)
1808 #define ADC_SQR3_SQ5_Msk          (0x1FUL << ADC_SQR3_SQ5_Pos)                  /*!< 0x01F00000 */
1809 #define ADC_SQR3_SQ5              ADC_SQR3_SQ5_Msk                             /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
1810 #define ADC_SQR3_SQ5_0            (0x01UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x00100000 */
1811 #define ADC_SQR3_SQ5_1            (0x02UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x00200000 */
1812 #define ADC_SQR3_SQ5_2            (0x04UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x00400000 */
1813 #define ADC_SQR3_SQ5_3            (0x08UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x00800000 */
1814 #define ADC_SQR3_SQ5_4            (0x10UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x01000000 */
1815 #define ADC_SQR3_SQ6_Pos          (25U)
1816 #define ADC_SQR3_SQ6_Msk          (0x1FUL << ADC_SQR3_SQ6_Pos)                  /*!< 0x3E000000 */
1817 #define ADC_SQR3_SQ6              ADC_SQR3_SQ6_Msk                             /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
1818 #define ADC_SQR3_SQ6_0            (0x01UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x02000000 */
1819 #define ADC_SQR3_SQ6_1            (0x02UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x04000000 */
1820 #define ADC_SQR3_SQ6_2            (0x04UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x08000000 */
1821 #define ADC_SQR3_SQ6_3            (0x08UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x10000000 */
1822 #define ADC_SQR3_SQ6_4            (0x10UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x20000000 */
1823 
1824 /*******************  Bit definition for ADC_JSQR register  *******************/
1825 #define ADC_JSQR_JSQ1_Pos         (0U)
1826 #define ADC_JSQR_JSQ1_Msk         (0x1FUL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x0000001F */
1827 #define ADC_JSQR_JSQ1             ADC_JSQR_JSQ1_Msk                            /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
1828 #define ADC_JSQR_JSQ1_0           (0x01UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000001 */
1829 #define ADC_JSQR_JSQ1_1           (0x02UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000002 */
1830 #define ADC_JSQR_JSQ1_2           (0x04UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000004 */
1831 #define ADC_JSQR_JSQ1_3           (0x08UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000008 */
1832 #define ADC_JSQR_JSQ1_4           (0x10UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000010 */
1833 #define ADC_JSQR_JSQ2_Pos         (5U)
1834 #define ADC_JSQR_JSQ2_Msk         (0x1FUL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x000003E0 */
1835 #define ADC_JSQR_JSQ2             ADC_JSQR_JSQ2_Msk                            /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
1836 #define ADC_JSQR_JSQ2_0           (0x01UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000020 */
1837 #define ADC_JSQR_JSQ2_1           (0x02UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000040 */
1838 #define ADC_JSQR_JSQ2_2           (0x04UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000080 */
1839 #define ADC_JSQR_JSQ2_3           (0x08UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000100 */
1840 #define ADC_JSQR_JSQ2_4           (0x10UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000200 */
1841 #define ADC_JSQR_JSQ3_Pos         (10U)
1842 #define ADC_JSQR_JSQ3_Msk         (0x1FUL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00007C00 */
1843 #define ADC_JSQR_JSQ3             ADC_JSQR_JSQ3_Msk                            /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
1844 #define ADC_JSQR_JSQ3_0           (0x01UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00000400 */
1845 #define ADC_JSQR_JSQ3_1           (0x02UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00000800 */
1846 #define ADC_JSQR_JSQ3_2           (0x04UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00001000 */
1847 #define ADC_JSQR_JSQ3_3           (0x08UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00002000 */
1848 #define ADC_JSQR_JSQ3_4           (0x10UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00004000 */
1849 #define ADC_JSQR_JSQ4_Pos         (15U)
1850 #define ADC_JSQR_JSQ4_Msk         (0x1FUL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x000F8000 */
1851 #define ADC_JSQR_JSQ4             ADC_JSQR_JSQ4_Msk                            /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
1852 #define ADC_JSQR_JSQ4_0           (0x01UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00008000 */
1853 #define ADC_JSQR_JSQ4_1           (0x02UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00010000 */
1854 #define ADC_JSQR_JSQ4_2           (0x04UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00020000 */
1855 #define ADC_JSQR_JSQ4_3           (0x08UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00040000 */
1856 #define ADC_JSQR_JSQ4_4           (0x10UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00080000 */
1857 #define ADC_JSQR_JL_Pos           (20U)
1858 #define ADC_JSQR_JL_Msk           (0x3UL << ADC_JSQR_JL_Pos)                    /*!< 0x00300000 */
1859 #define ADC_JSQR_JL               ADC_JSQR_JL_Msk                              /*!<JL[1:0] bits (Injected Sequence length) */
1860 #define ADC_JSQR_JL_0             (0x1UL << ADC_JSQR_JL_Pos)                    /*!< 0x00100000 */
1861 #define ADC_JSQR_JL_1             (0x2UL << ADC_JSQR_JL_Pos)                    /*!< 0x00200000 */
1862 
1863 /*******************  Bit definition for ADC_JDR1 register  *******************/
1864 #define ADC_JDR1_JDATA_Pos        (0U)
1865 #define ADC_JDR1_JDATA_Msk        (0xFFFFUL << ADC_JDR1_JDATA_Pos)              /*!< 0x0000FFFF */
1866 #define ADC_JDR1_JDATA            ADC_JDR1_JDATA_Msk                           /*!<Injected data */
1867 
1868 /*******************  Bit definition for ADC_JDR2 register  *******************/
1869 #define ADC_JDR2_JDATA_Pos        (0U)
1870 #define ADC_JDR2_JDATA_Msk        (0xFFFFUL << ADC_JDR2_JDATA_Pos)              /*!< 0x0000FFFF */
1871 #define ADC_JDR2_JDATA            ADC_JDR2_JDATA_Msk                           /*!<Injected data */
1872 
1873 /*******************  Bit definition for ADC_JDR3 register  *******************/
1874 #define ADC_JDR3_JDATA_Pos        (0U)
1875 #define ADC_JDR3_JDATA_Msk        (0xFFFFUL << ADC_JDR3_JDATA_Pos)              /*!< 0x0000FFFF */
1876 #define ADC_JDR3_JDATA            ADC_JDR3_JDATA_Msk                           /*!<Injected data */
1877 
1878 /*******************  Bit definition for ADC_JDR4 register  *******************/
1879 #define ADC_JDR4_JDATA_Pos        (0U)
1880 #define ADC_JDR4_JDATA_Msk        (0xFFFFUL << ADC_JDR4_JDATA_Pos)              /*!< 0x0000FFFF */
1881 #define ADC_JDR4_JDATA            ADC_JDR4_JDATA_Msk                           /*!<Injected data */
1882 
1883 /********************  Bit definition for ADC_DR register  ********************/
1884 #define ADC_DR_DATA_Pos           (0U)
1885 #define ADC_DR_DATA_Msk           (0xFFFFUL << ADC_DR_DATA_Pos)                 /*!< 0x0000FFFF */
1886 #define ADC_DR_DATA               ADC_DR_DATA_Msk                              /*!<Regular data */
1887 #define ADC_DR_ADC2DATA_Pos       (16U)
1888 #define ADC_DR_ADC2DATA_Msk       (0xFFFFUL << ADC_DR_ADC2DATA_Pos)             /*!< 0xFFFF0000 */
1889 #define ADC_DR_ADC2DATA           ADC_DR_ADC2DATA_Msk                          /*!<ADC2 data */
1890 
1891 /*******************  Bit definition for ADC_CSR register  ********************/
1892 #define ADC_CSR_AWD1_Pos          (0U)
1893 #define ADC_CSR_AWD1_Msk          (0x1UL << ADC_CSR_AWD1_Pos)                   /*!< 0x00000001 */
1894 #define ADC_CSR_AWD1              ADC_CSR_AWD1_Msk                             /*!<ADC1 Analog watchdog flag */
1895 #define ADC_CSR_EOC1_Pos          (1U)
1896 #define ADC_CSR_EOC1_Msk          (0x1UL << ADC_CSR_EOC1_Pos)                   /*!< 0x00000002 */
1897 #define ADC_CSR_EOC1              ADC_CSR_EOC1_Msk                             /*!<ADC1 End of conversion */
1898 #define ADC_CSR_JEOC1_Pos         (2U)
1899 #define ADC_CSR_JEOC1_Msk         (0x1UL << ADC_CSR_JEOC1_Pos)                  /*!< 0x00000004 */
1900 #define ADC_CSR_JEOC1             ADC_CSR_JEOC1_Msk                            /*!<ADC1 Injected channel end of conversion */
1901 #define ADC_CSR_JSTRT1_Pos        (3U)
1902 #define ADC_CSR_JSTRT1_Msk        (0x1UL << ADC_CSR_JSTRT1_Pos)                 /*!< 0x00000008 */
1903 #define ADC_CSR_JSTRT1            ADC_CSR_JSTRT1_Msk                           /*!<ADC1 Injected channel Start flag */
1904 #define ADC_CSR_STRT1_Pos         (4U)
1905 #define ADC_CSR_STRT1_Msk         (0x1UL << ADC_CSR_STRT1_Pos)                  /*!< 0x00000010 */
1906 #define ADC_CSR_STRT1             ADC_CSR_STRT1_Msk                            /*!<ADC1 Regular channel Start flag */
1907 #define ADC_CSR_OVR1_Pos          (5U)
1908 #define ADC_CSR_OVR1_Msk          (0x1UL << ADC_CSR_OVR1_Pos)                   /*!< 0x00000020 */
1909 #define ADC_CSR_OVR1              ADC_CSR_OVR1_Msk                             /*!<ADC1 DMA overrun  flag */
1910 #define ADC_CSR_AWD2_Pos          (8U)
1911 #define ADC_CSR_AWD2_Msk          (0x1UL << ADC_CSR_AWD2_Pos)                   /*!< 0x00000100 */
1912 #define ADC_CSR_AWD2              ADC_CSR_AWD2_Msk                             /*!<ADC2 Analog watchdog flag */
1913 #define ADC_CSR_EOC2_Pos          (9U)
1914 #define ADC_CSR_EOC2_Msk          (0x1UL << ADC_CSR_EOC2_Pos)                   /*!< 0x00000200 */
1915 #define ADC_CSR_EOC2              ADC_CSR_EOC2_Msk                             /*!<ADC2 End of conversion */
1916 #define ADC_CSR_JEOC2_Pos         (10U)
1917 #define ADC_CSR_JEOC2_Msk         (0x1UL << ADC_CSR_JEOC2_Pos)                  /*!< 0x00000400 */
1918 #define ADC_CSR_JEOC2             ADC_CSR_JEOC2_Msk                            /*!<ADC2 Injected channel end of conversion */
1919 #define ADC_CSR_JSTRT2_Pos        (11U)
1920 #define ADC_CSR_JSTRT2_Msk        (0x1UL << ADC_CSR_JSTRT2_Pos)                 /*!< 0x00000800 */
1921 #define ADC_CSR_JSTRT2            ADC_CSR_JSTRT2_Msk                           /*!<ADC2 Injected channel Start flag */
1922 #define ADC_CSR_STRT2_Pos         (12U)
1923 #define ADC_CSR_STRT2_Msk         (0x1UL << ADC_CSR_STRT2_Pos)                  /*!< 0x00001000 */
1924 #define ADC_CSR_STRT2             ADC_CSR_STRT2_Msk                            /*!<ADC2 Regular channel Start flag */
1925 #define ADC_CSR_OVR2_Pos          (13U)
1926 #define ADC_CSR_OVR2_Msk          (0x1UL << ADC_CSR_OVR2_Pos)                   /*!< 0x00002000 */
1927 #define ADC_CSR_OVR2              ADC_CSR_OVR2_Msk                             /*!<ADC2 DMA overrun  flag */
1928 #define ADC_CSR_AWD3_Pos          (16U)
1929 #define ADC_CSR_AWD3_Msk          (0x1UL << ADC_CSR_AWD3_Pos)                   /*!< 0x00010000 */
1930 #define ADC_CSR_AWD3              ADC_CSR_AWD3_Msk                             /*!<ADC3 Analog watchdog flag */
1931 #define ADC_CSR_EOC3_Pos          (17U)
1932 #define ADC_CSR_EOC3_Msk          (0x1UL << ADC_CSR_EOC3_Pos)                   /*!< 0x00020000 */
1933 #define ADC_CSR_EOC3              ADC_CSR_EOC3_Msk                             /*!<ADC3 End of conversion */
1934 #define ADC_CSR_JEOC3_Pos         (18U)
1935 #define ADC_CSR_JEOC3_Msk         (0x1UL << ADC_CSR_JEOC3_Pos)                  /*!< 0x00040000 */
1936 #define ADC_CSR_JEOC3             ADC_CSR_JEOC3_Msk                            /*!<ADC3 Injected channel end of conversion */
1937 #define ADC_CSR_JSTRT3_Pos        (19U)
1938 #define ADC_CSR_JSTRT3_Msk        (0x1UL << ADC_CSR_JSTRT3_Pos)                 /*!< 0x00080000 */
1939 #define ADC_CSR_JSTRT3            ADC_CSR_JSTRT3_Msk                           /*!<ADC3 Injected channel Start flag */
1940 #define ADC_CSR_STRT3_Pos         (20U)
1941 #define ADC_CSR_STRT3_Msk         (0x1UL << ADC_CSR_STRT3_Pos)                  /*!< 0x00100000 */
1942 #define ADC_CSR_STRT3             ADC_CSR_STRT3_Msk                            /*!<ADC3 Regular channel Start flag */
1943 #define ADC_CSR_OVR3_Pos          (21U)
1944 #define ADC_CSR_OVR3_Msk          (0x1UL << ADC_CSR_OVR3_Pos)                   /*!< 0x00200000 */
1945 #define ADC_CSR_OVR3              ADC_CSR_OVR3_Msk                             /*!<ADC3 DMA overrun  flag */
1946 
1947 /* Legacy defines */
1948 #define  ADC_CSR_DOVR1                        ADC_CSR_OVR1
1949 #define  ADC_CSR_DOVR2                        ADC_CSR_OVR2
1950 #define  ADC_CSR_DOVR3                        ADC_CSR_OVR3
1951 
1952 /*******************  Bit definition for ADC_CCR register  ********************/
1953 #define ADC_CCR_MULTI_Pos         (0U)
1954 #define ADC_CCR_MULTI_Msk         (0x1FUL << ADC_CCR_MULTI_Pos)                 /*!< 0x0000001F */
1955 #define ADC_CCR_MULTI             ADC_CCR_MULTI_Msk                            /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
1956 #define ADC_CCR_MULTI_0           (0x01UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000001 */
1957 #define ADC_CCR_MULTI_1           (0x02UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000002 */
1958 #define ADC_CCR_MULTI_2           (0x04UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000004 */
1959 #define ADC_CCR_MULTI_3           (0x08UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000008 */
1960 #define ADC_CCR_MULTI_4           (0x10UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000010 */
1961 #define ADC_CCR_DELAY_Pos         (8U)
1962 #define ADC_CCR_DELAY_Msk         (0xFUL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000F00 */
1963 #define ADC_CCR_DELAY             ADC_CCR_DELAY_Msk                            /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
1964 #define ADC_CCR_DELAY_0           (0x1UL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000100 */
1965 #define ADC_CCR_DELAY_1           (0x2UL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000200 */
1966 #define ADC_CCR_DELAY_2           (0x4UL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000400 */
1967 #define ADC_CCR_DELAY_3           (0x8UL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000800 */
1968 #define ADC_CCR_DDS_Pos           (13U)
1969 #define ADC_CCR_DDS_Msk           (0x1UL << ADC_CCR_DDS_Pos)                    /*!< 0x00002000 */
1970 #define ADC_CCR_DDS               ADC_CCR_DDS_Msk                              /*!<DMA disable selection (Multi-ADC mode) */
1971 #define ADC_CCR_DMA_Pos           (14U)
1972 #define ADC_CCR_DMA_Msk           (0x3UL << ADC_CCR_DMA_Pos)                    /*!< 0x0000C000 */
1973 #define ADC_CCR_DMA               ADC_CCR_DMA_Msk                              /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
1974 #define ADC_CCR_DMA_0             (0x1UL << ADC_CCR_DMA_Pos)                    /*!< 0x00004000 */
1975 #define ADC_CCR_DMA_1             (0x2UL << ADC_CCR_DMA_Pos)                    /*!< 0x00008000 */
1976 #define ADC_CCR_ADCPRE_Pos        (16U)
1977 #define ADC_CCR_ADCPRE_Msk        (0x3UL << ADC_CCR_ADCPRE_Pos)                 /*!< 0x00030000 */
1978 #define ADC_CCR_ADCPRE            ADC_CCR_ADCPRE_Msk                           /*!<ADCPRE[1:0] bits (ADC prescaler) */
1979 #define ADC_CCR_ADCPRE_0          (0x1UL << ADC_CCR_ADCPRE_Pos)                 /*!< 0x00010000 */
1980 #define ADC_CCR_ADCPRE_1          (0x2UL << ADC_CCR_ADCPRE_Pos)                 /*!< 0x00020000 */
1981 #define ADC_CCR_VBATE_Pos         (22U)
1982 #define ADC_CCR_VBATE_Msk         (0x1UL << ADC_CCR_VBATE_Pos)                  /*!< 0x00400000 */
1983 #define ADC_CCR_VBATE             ADC_CCR_VBATE_Msk                            /*!<VBAT Enable */
1984 #define ADC_CCR_TSVREFE_Pos       (23U)
1985 #define ADC_CCR_TSVREFE_Msk       (0x1UL << ADC_CCR_TSVREFE_Pos)                /*!< 0x00800000 */
1986 #define ADC_CCR_TSVREFE           ADC_CCR_TSVREFE_Msk                          /*!<Temperature Sensor and VREFINT Enable */
1987 
1988 /*******************  Bit definition for ADC_CDR register  ********************/
1989 #define ADC_CDR_DATA1_Pos         (0U)
1990 #define ADC_CDR_DATA1_Msk         (0xFFFFUL << ADC_CDR_DATA1_Pos)               /*!< 0x0000FFFF */
1991 #define ADC_CDR_DATA1             ADC_CDR_DATA1_Msk                            /*!<1st data of a pair of regular conversions */
1992 #define ADC_CDR_DATA2_Pos         (16U)
1993 #define ADC_CDR_DATA2_Msk         (0xFFFFUL << ADC_CDR_DATA2_Pos)               /*!< 0xFFFF0000 */
1994 #define ADC_CDR_DATA2             ADC_CDR_DATA2_Msk                            /*!<2nd data of a pair of regular conversions */
1995 
1996 /* Legacy defines */
1997 #define ADC_CDR_RDATA_MST         ADC_CDR_DATA1
1998 #define ADC_CDR_RDATA_SLV         ADC_CDR_DATA2
1999 
2000 /******************************************************************************/
2001 /*                                                                            */
2002 /*                         Controller Area Network                            */
2003 /*                                                                            */
2004 /******************************************************************************/
2005 /*!<CAN control and status registers */
2006 /*******************  Bit definition for CAN_MCR register  ********************/
2007 #define CAN_MCR_INRQ_Pos       (0U)
2008 #define CAN_MCR_INRQ_Msk       (0x1UL << CAN_MCR_INRQ_Pos)                      /*!< 0x00000001 */
2009 #define CAN_MCR_INRQ           CAN_MCR_INRQ_Msk                                /*!<Initialization Request */
2010 #define CAN_MCR_SLEEP_Pos      (1U)
2011 #define CAN_MCR_SLEEP_Msk      (0x1UL << CAN_MCR_SLEEP_Pos)                     /*!< 0x00000002 */
2012 #define CAN_MCR_SLEEP          CAN_MCR_SLEEP_Msk                               /*!<Sleep Mode Request */
2013 #define CAN_MCR_TXFP_Pos       (2U)
2014 #define CAN_MCR_TXFP_Msk       (0x1UL << CAN_MCR_TXFP_Pos)                      /*!< 0x00000004 */
2015 #define CAN_MCR_TXFP           CAN_MCR_TXFP_Msk                                /*!<Transmit FIFO Priority */
2016 #define CAN_MCR_RFLM_Pos       (3U)
2017 #define CAN_MCR_RFLM_Msk       (0x1UL << CAN_MCR_RFLM_Pos)                      /*!< 0x00000008 */
2018 #define CAN_MCR_RFLM           CAN_MCR_RFLM_Msk                                /*!<Receive FIFO Locked Mode */
2019 #define CAN_MCR_NART_Pos       (4U)
2020 #define CAN_MCR_NART_Msk       (0x1UL << CAN_MCR_NART_Pos)                      /*!< 0x00000010 */
2021 #define CAN_MCR_NART           CAN_MCR_NART_Msk                                /*!<No Automatic Retransmission */
2022 #define CAN_MCR_AWUM_Pos       (5U)
2023 #define CAN_MCR_AWUM_Msk       (0x1UL << CAN_MCR_AWUM_Pos)                      /*!< 0x00000020 */
2024 #define CAN_MCR_AWUM           CAN_MCR_AWUM_Msk                                /*!<Automatic Wakeup Mode */
2025 #define CAN_MCR_ABOM_Pos       (6U)
2026 #define CAN_MCR_ABOM_Msk       (0x1UL << CAN_MCR_ABOM_Pos)                      /*!< 0x00000040 */
2027 #define CAN_MCR_ABOM           CAN_MCR_ABOM_Msk                                /*!<Automatic Bus-Off Management */
2028 #define CAN_MCR_TTCM_Pos       (7U)
2029 #define CAN_MCR_TTCM_Msk       (0x1UL << CAN_MCR_TTCM_Pos)                      /*!< 0x00000080 */
2030 #define CAN_MCR_TTCM           CAN_MCR_TTCM_Msk                                /*!<Time Triggered Communication Mode */
2031 #define CAN_MCR_RESET_Pos      (15U)
2032 #define CAN_MCR_RESET_Msk      (0x1UL << CAN_MCR_RESET_Pos)                     /*!< 0x00008000 */
2033 #define CAN_MCR_RESET          CAN_MCR_RESET_Msk                               /*!<bxCAN software master reset */
2034 #define CAN_MCR_DBF_Pos        (16U)
2035 #define CAN_MCR_DBF_Msk        (0x1UL << CAN_MCR_DBF_Pos)                       /*!< 0x00010000 */
2036 #define CAN_MCR_DBF            CAN_MCR_DBF_Msk                                 /*!<bxCAN Debug freeze */
2037 /*******************  Bit definition for CAN_MSR register  ********************/
2038 #define CAN_MSR_INAK_Pos       (0U)
2039 #define CAN_MSR_INAK_Msk       (0x1UL << CAN_MSR_INAK_Pos)                      /*!< 0x00000001 */
2040 #define CAN_MSR_INAK           CAN_MSR_INAK_Msk                                /*!<Initialization Acknowledge */
2041 #define CAN_MSR_SLAK_Pos       (1U)
2042 #define CAN_MSR_SLAK_Msk       (0x1UL << CAN_MSR_SLAK_Pos)                      /*!< 0x00000002 */
2043 #define CAN_MSR_SLAK           CAN_MSR_SLAK_Msk                                /*!<Sleep Acknowledge */
2044 #define CAN_MSR_ERRI_Pos       (2U)
2045 #define CAN_MSR_ERRI_Msk       (0x1UL << CAN_MSR_ERRI_Pos)                      /*!< 0x00000004 */
2046 #define CAN_MSR_ERRI           CAN_MSR_ERRI_Msk                                /*!<Error Interrupt */
2047 #define CAN_MSR_WKUI_Pos       (3U)
2048 #define CAN_MSR_WKUI_Msk       (0x1UL << CAN_MSR_WKUI_Pos)                      /*!< 0x00000008 */
2049 #define CAN_MSR_WKUI           CAN_MSR_WKUI_Msk                                /*!<Wakeup Interrupt */
2050 #define CAN_MSR_SLAKI_Pos      (4U)
2051 #define CAN_MSR_SLAKI_Msk      (0x1UL << CAN_MSR_SLAKI_Pos)                     /*!< 0x00000010 */
2052 #define CAN_MSR_SLAKI          CAN_MSR_SLAKI_Msk                               /*!<Sleep Acknowledge Interrupt */
2053 #define CAN_MSR_TXM_Pos        (8U)
2054 #define CAN_MSR_TXM_Msk        (0x1UL << CAN_MSR_TXM_Pos)                       /*!< 0x00000100 */
2055 #define CAN_MSR_TXM            CAN_MSR_TXM_Msk                                 /*!<Transmit Mode */
2056 #define CAN_MSR_RXM_Pos        (9U)
2057 #define CAN_MSR_RXM_Msk        (0x1UL << CAN_MSR_RXM_Pos)                       /*!< 0x00000200 */
2058 #define CAN_MSR_RXM            CAN_MSR_RXM_Msk                                 /*!<Receive Mode */
2059 #define CAN_MSR_SAMP_Pos       (10U)
2060 #define CAN_MSR_SAMP_Msk       (0x1UL << CAN_MSR_SAMP_Pos)                      /*!< 0x00000400 */
2061 #define CAN_MSR_SAMP           CAN_MSR_SAMP_Msk                                /*!<Last Sample Point */
2062 #define CAN_MSR_RX_Pos         (11U)
2063 #define CAN_MSR_RX_Msk         (0x1UL << CAN_MSR_RX_Pos)                        /*!< 0x00000800 */
2064 #define CAN_MSR_RX             CAN_MSR_RX_Msk                                  /*!<CAN Rx Signal */
2065 
2066 /*******************  Bit definition for CAN_TSR register  ********************/
2067 #define CAN_TSR_RQCP0_Pos      (0U)
2068 #define CAN_TSR_RQCP0_Msk      (0x1UL << CAN_TSR_RQCP0_Pos)                     /*!< 0x00000001 */
2069 #define CAN_TSR_RQCP0          CAN_TSR_RQCP0_Msk                               /*!<Request Completed Mailbox0 */
2070 #define CAN_TSR_TXOK0_Pos      (1U)
2071 #define CAN_TSR_TXOK0_Msk      (0x1UL << CAN_TSR_TXOK0_Pos)                     /*!< 0x00000002 */
2072 #define CAN_TSR_TXOK0          CAN_TSR_TXOK0_Msk                               /*!<Transmission OK of Mailbox0 */
2073 #define CAN_TSR_ALST0_Pos      (2U)
2074 #define CAN_TSR_ALST0_Msk      (0x1UL << CAN_TSR_ALST0_Pos)                     /*!< 0x00000004 */
2075 #define CAN_TSR_ALST0          CAN_TSR_ALST0_Msk                               /*!<Arbitration Lost for Mailbox0 */
2076 #define CAN_TSR_TERR0_Pos      (3U)
2077 #define CAN_TSR_TERR0_Msk      (0x1UL << CAN_TSR_TERR0_Pos)                     /*!< 0x00000008 */
2078 #define CAN_TSR_TERR0          CAN_TSR_TERR0_Msk                               /*!<Transmission Error of Mailbox0 */
2079 #define CAN_TSR_ABRQ0_Pos      (7U)
2080 #define CAN_TSR_ABRQ0_Msk      (0x1UL << CAN_TSR_ABRQ0_Pos)                     /*!< 0x00000080 */
2081 #define CAN_TSR_ABRQ0          CAN_TSR_ABRQ0_Msk                               /*!<Abort Request for Mailbox0 */
2082 #define CAN_TSR_RQCP1_Pos      (8U)
2083 #define CAN_TSR_RQCP1_Msk      (0x1UL << CAN_TSR_RQCP1_Pos)                     /*!< 0x00000100 */
2084 #define CAN_TSR_RQCP1          CAN_TSR_RQCP1_Msk                               /*!<Request Completed Mailbox1 */
2085 #define CAN_TSR_TXOK1_Pos      (9U)
2086 #define CAN_TSR_TXOK1_Msk      (0x1UL << CAN_TSR_TXOK1_Pos)                     /*!< 0x00000200 */
2087 #define CAN_TSR_TXOK1          CAN_TSR_TXOK1_Msk                               /*!<Transmission OK of Mailbox1 */
2088 #define CAN_TSR_ALST1_Pos      (10U)
2089 #define CAN_TSR_ALST1_Msk      (0x1UL << CAN_TSR_ALST1_Pos)                     /*!< 0x00000400 */
2090 #define CAN_TSR_ALST1          CAN_TSR_ALST1_Msk                               /*!<Arbitration Lost for Mailbox1 */
2091 #define CAN_TSR_TERR1_Pos      (11U)
2092 #define CAN_TSR_TERR1_Msk      (0x1UL << CAN_TSR_TERR1_Pos)                     /*!< 0x00000800 */
2093 #define CAN_TSR_TERR1          CAN_TSR_TERR1_Msk                               /*!<Transmission Error of Mailbox1 */
2094 #define CAN_TSR_ABRQ1_Pos      (15U)
2095 #define CAN_TSR_ABRQ1_Msk      (0x1UL << CAN_TSR_ABRQ1_Pos)                     /*!< 0x00008000 */
2096 #define CAN_TSR_ABRQ1          CAN_TSR_ABRQ1_Msk                               /*!<Abort Request for Mailbox 1 */
2097 #define CAN_TSR_RQCP2_Pos      (16U)
2098 #define CAN_TSR_RQCP2_Msk      (0x1UL << CAN_TSR_RQCP2_Pos)                     /*!< 0x00010000 */
2099 #define CAN_TSR_RQCP2          CAN_TSR_RQCP2_Msk                               /*!<Request Completed Mailbox2 */
2100 #define CAN_TSR_TXOK2_Pos      (17U)
2101 #define CAN_TSR_TXOK2_Msk      (0x1UL << CAN_TSR_TXOK2_Pos)                     /*!< 0x00020000 */
2102 #define CAN_TSR_TXOK2          CAN_TSR_TXOK2_Msk                               /*!<Transmission OK of Mailbox 2 */
2103 #define CAN_TSR_ALST2_Pos      (18U)
2104 #define CAN_TSR_ALST2_Msk      (0x1UL << CAN_TSR_ALST2_Pos)                     /*!< 0x00040000 */
2105 #define CAN_TSR_ALST2          CAN_TSR_ALST2_Msk                               /*!<Arbitration Lost for mailbox 2 */
2106 #define CAN_TSR_TERR2_Pos      (19U)
2107 #define CAN_TSR_TERR2_Msk      (0x1UL << CAN_TSR_TERR2_Pos)                     /*!< 0x00080000 */
2108 #define CAN_TSR_TERR2          CAN_TSR_TERR2_Msk                               /*!<Transmission Error of Mailbox 2 */
2109 #define CAN_TSR_ABRQ2_Pos      (23U)
2110 #define CAN_TSR_ABRQ2_Msk      (0x1UL << CAN_TSR_ABRQ2_Pos)                     /*!< 0x00800000 */
2111 #define CAN_TSR_ABRQ2          CAN_TSR_ABRQ2_Msk                               /*!<Abort Request for Mailbox 2 */
2112 #define CAN_TSR_CODE_Pos       (24U)
2113 #define CAN_TSR_CODE_Msk       (0x3UL << CAN_TSR_CODE_Pos)                      /*!< 0x03000000 */
2114 #define CAN_TSR_CODE           CAN_TSR_CODE_Msk                                /*!<Mailbox Code */
2115 
2116 #define CAN_TSR_TME_Pos        (26U)
2117 #define CAN_TSR_TME_Msk        (0x7UL << CAN_TSR_TME_Pos)                       /*!< 0x1C000000 */
2118 #define CAN_TSR_TME            CAN_TSR_TME_Msk                                 /*!<TME[2:0] bits */
2119 #define CAN_TSR_TME0_Pos       (26U)
2120 #define CAN_TSR_TME0_Msk       (0x1UL << CAN_TSR_TME0_Pos)                      /*!< 0x04000000 */
2121 #define CAN_TSR_TME0           CAN_TSR_TME0_Msk                                /*!<Transmit Mailbox 0 Empty */
2122 #define CAN_TSR_TME1_Pos       (27U)
2123 #define CAN_TSR_TME1_Msk       (0x1UL << CAN_TSR_TME1_Pos)                      /*!< 0x08000000 */
2124 #define CAN_TSR_TME1           CAN_TSR_TME1_Msk                                /*!<Transmit Mailbox 1 Empty */
2125 #define CAN_TSR_TME2_Pos       (28U)
2126 #define CAN_TSR_TME2_Msk       (0x1UL << CAN_TSR_TME2_Pos)                      /*!< 0x10000000 */
2127 #define CAN_TSR_TME2           CAN_TSR_TME2_Msk                                /*!<Transmit Mailbox 2 Empty */
2128 
2129 #define CAN_TSR_LOW_Pos        (29U)
2130 #define CAN_TSR_LOW_Msk        (0x7UL << CAN_TSR_LOW_Pos)                       /*!< 0xE0000000 */
2131 #define CAN_TSR_LOW            CAN_TSR_LOW_Msk                                 /*!<LOW[2:0] bits */
2132 #define CAN_TSR_LOW0_Pos       (29U)
2133 #define CAN_TSR_LOW0_Msk       (0x1UL << CAN_TSR_LOW0_Pos)                      /*!< 0x20000000 */
2134 #define CAN_TSR_LOW0           CAN_TSR_LOW0_Msk                                /*!<Lowest Priority Flag for Mailbox 0 */
2135 #define CAN_TSR_LOW1_Pos       (30U)
2136 #define CAN_TSR_LOW1_Msk       (0x1UL << CAN_TSR_LOW1_Pos)                      /*!< 0x40000000 */
2137 #define CAN_TSR_LOW1           CAN_TSR_LOW1_Msk                                /*!<Lowest Priority Flag for Mailbox 1 */
2138 #define CAN_TSR_LOW2_Pos       (31U)
2139 #define CAN_TSR_LOW2_Msk       (0x1UL << CAN_TSR_LOW2_Pos)                      /*!< 0x80000000 */
2140 #define CAN_TSR_LOW2           CAN_TSR_LOW2_Msk                                /*!<Lowest Priority Flag for Mailbox 2 */
2141 
2142 /*******************  Bit definition for CAN_RF0R register  *******************/
2143 #define CAN_RF0R_FMP0_Pos      (0U)
2144 #define CAN_RF0R_FMP0_Msk      (0x3UL << CAN_RF0R_FMP0_Pos)                     /*!< 0x00000003 */
2145 #define CAN_RF0R_FMP0          CAN_RF0R_FMP0_Msk                               /*!<FIFO 0 Message Pending */
2146 #define CAN_RF0R_FULL0_Pos     (3U)
2147 #define CAN_RF0R_FULL0_Msk     (0x1UL << CAN_RF0R_FULL0_Pos)                    /*!< 0x00000008 */
2148 #define CAN_RF0R_FULL0         CAN_RF0R_FULL0_Msk                              /*!<FIFO 0 Full */
2149 #define CAN_RF0R_FOVR0_Pos     (4U)
2150 #define CAN_RF0R_FOVR0_Msk     (0x1UL << CAN_RF0R_FOVR0_Pos)                    /*!< 0x00000010 */
2151 #define CAN_RF0R_FOVR0         CAN_RF0R_FOVR0_Msk                              /*!<FIFO 0 Overrun */
2152 #define CAN_RF0R_RFOM0_Pos     (5U)
2153 #define CAN_RF0R_RFOM0_Msk     (0x1UL << CAN_RF0R_RFOM0_Pos)                    /*!< 0x00000020 */
2154 #define CAN_RF0R_RFOM0         CAN_RF0R_RFOM0_Msk                              /*!<Release FIFO 0 Output Mailbox */
2155 
2156 /*******************  Bit definition for CAN_RF1R register  *******************/
2157 #define CAN_RF1R_FMP1_Pos      (0U)
2158 #define CAN_RF1R_FMP1_Msk      (0x3UL << CAN_RF1R_FMP1_Pos)                     /*!< 0x00000003 */
2159 #define CAN_RF1R_FMP1          CAN_RF1R_FMP1_Msk                               /*!<FIFO 1 Message Pending */
2160 #define CAN_RF1R_FULL1_Pos     (3U)
2161 #define CAN_RF1R_FULL1_Msk     (0x1UL << CAN_RF1R_FULL1_Pos)                    /*!< 0x00000008 */
2162 #define CAN_RF1R_FULL1         CAN_RF1R_FULL1_Msk                              /*!<FIFO 1 Full */
2163 #define CAN_RF1R_FOVR1_Pos     (4U)
2164 #define CAN_RF1R_FOVR1_Msk     (0x1UL << CAN_RF1R_FOVR1_Pos)                    /*!< 0x00000010 */
2165 #define CAN_RF1R_FOVR1         CAN_RF1R_FOVR1_Msk                              /*!<FIFO 1 Overrun */
2166 #define CAN_RF1R_RFOM1_Pos     (5U)
2167 #define CAN_RF1R_RFOM1_Msk     (0x1UL << CAN_RF1R_RFOM1_Pos)                    /*!< 0x00000020 */
2168 #define CAN_RF1R_RFOM1         CAN_RF1R_RFOM1_Msk                              /*!<Release FIFO 1 Output Mailbox */
2169 
2170 /********************  Bit definition for CAN_IER register  *******************/
2171 #define CAN_IER_TMEIE_Pos      (0U)
2172 #define CAN_IER_TMEIE_Msk      (0x1UL << CAN_IER_TMEIE_Pos)                     /*!< 0x00000001 */
2173 #define CAN_IER_TMEIE          CAN_IER_TMEIE_Msk                               /*!<Transmit Mailbox Empty Interrupt Enable */
2174 #define CAN_IER_FMPIE0_Pos     (1U)
2175 #define CAN_IER_FMPIE0_Msk     (0x1UL << CAN_IER_FMPIE0_Pos)                    /*!< 0x00000002 */
2176 #define CAN_IER_FMPIE0         CAN_IER_FMPIE0_Msk                              /*!<FIFO Message Pending Interrupt Enable */
2177 #define CAN_IER_FFIE0_Pos      (2U)
2178 #define CAN_IER_FFIE0_Msk      (0x1UL << CAN_IER_FFIE0_Pos)                     /*!< 0x00000004 */
2179 #define CAN_IER_FFIE0          CAN_IER_FFIE0_Msk                               /*!<FIFO Full Interrupt Enable */
2180 #define CAN_IER_FOVIE0_Pos     (3U)
2181 #define CAN_IER_FOVIE0_Msk     (0x1UL << CAN_IER_FOVIE0_Pos)                    /*!< 0x00000008 */
2182 #define CAN_IER_FOVIE0         CAN_IER_FOVIE0_Msk                              /*!<FIFO Overrun Interrupt Enable */
2183 #define CAN_IER_FMPIE1_Pos     (4U)
2184 #define CAN_IER_FMPIE1_Msk     (0x1UL << CAN_IER_FMPIE1_Pos)                    /*!< 0x00000010 */
2185 #define CAN_IER_FMPIE1         CAN_IER_FMPIE1_Msk                              /*!<FIFO Message Pending Interrupt Enable */
2186 #define CAN_IER_FFIE1_Pos      (5U)
2187 #define CAN_IER_FFIE1_Msk      (0x1UL << CAN_IER_FFIE1_Pos)                     /*!< 0x00000020 */
2188 #define CAN_IER_FFIE1          CAN_IER_FFIE1_Msk                               /*!<FIFO Full Interrupt Enable */
2189 #define CAN_IER_FOVIE1_Pos     (6U)
2190 #define CAN_IER_FOVIE1_Msk     (0x1UL << CAN_IER_FOVIE1_Pos)                    /*!< 0x00000040 */
2191 #define CAN_IER_FOVIE1         CAN_IER_FOVIE1_Msk                              /*!<FIFO Overrun Interrupt Enable */
2192 #define CAN_IER_EWGIE_Pos      (8U)
2193 #define CAN_IER_EWGIE_Msk      (0x1UL << CAN_IER_EWGIE_Pos)                     /*!< 0x00000100 */
2194 #define CAN_IER_EWGIE          CAN_IER_EWGIE_Msk                               /*!<Error Warning Interrupt Enable */
2195 #define CAN_IER_EPVIE_Pos      (9U)
2196 #define CAN_IER_EPVIE_Msk      (0x1UL << CAN_IER_EPVIE_Pos)                     /*!< 0x00000200 */
2197 #define CAN_IER_EPVIE          CAN_IER_EPVIE_Msk                               /*!<Error Passive Interrupt Enable */
2198 #define CAN_IER_BOFIE_Pos      (10U)
2199 #define CAN_IER_BOFIE_Msk      (0x1UL << CAN_IER_BOFIE_Pos)                     /*!< 0x00000400 */
2200 #define CAN_IER_BOFIE          CAN_IER_BOFIE_Msk                               /*!<Bus-Off Interrupt Enable */
2201 #define CAN_IER_LECIE_Pos      (11U)
2202 #define CAN_IER_LECIE_Msk      (0x1UL << CAN_IER_LECIE_Pos)                     /*!< 0x00000800 */
2203 #define CAN_IER_LECIE          CAN_IER_LECIE_Msk                               /*!<Last Error Code Interrupt Enable */
2204 #define CAN_IER_ERRIE_Pos      (15U)
2205 #define CAN_IER_ERRIE_Msk      (0x1UL << CAN_IER_ERRIE_Pos)                     /*!< 0x00008000 */
2206 #define CAN_IER_ERRIE          CAN_IER_ERRIE_Msk                               /*!<Error Interrupt Enable */
2207 #define CAN_IER_WKUIE_Pos      (16U)
2208 #define CAN_IER_WKUIE_Msk      (0x1UL << CAN_IER_WKUIE_Pos)                     /*!< 0x00010000 */
2209 #define CAN_IER_WKUIE          CAN_IER_WKUIE_Msk                               /*!<Wakeup Interrupt Enable */
2210 #define CAN_IER_SLKIE_Pos      (17U)
2211 #define CAN_IER_SLKIE_Msk      (0x1UL << CAN_IER_SLKIE_Pos)                     /*!< 0x00020000 */
2212 #define CAN_IER_SLKIE          CAN_IER_SLKIE_Msk                               /*!<Sleep Interrupt Enable */
2213 #define CAN_IER_EWGIE_Pos      (8U)
2214 
2215 /********************  Bit definition for CAN_ESR register  *******************/
2216 #define CAN_ESR_EWGF_Pos       (0U)
2217 #define CAN_ESR_EWGF_Msk       (0x1UL << CAN_ESR_EWGF_Pos)                      /*!< 0x00000001 */
2218 #define CAN_ESR_EWGF           CAN_ESR_EWGF_Msk                                /*!<Error Warning Flag */
2219 #define CAN_ESR_EPVF_Pos       (1U)
2220 #define CAN_ESR_EPVF_Msk       (0x1UL << CAN_ESR_EPVF_Pos)                      /*!< 0x00000002 */
2221 #define CAN_ESR_EPVF           CAN_ESR_EPVF_Msk                                /*!<Error Passive Flag */
2222 #define CAN_ESR_BOFF_Pos       (2U)
2223 #define CAN_ESR_BOFF_Msk       (0x1UL << CAN_ESR_BOFF_Pos)                      /*!< 0x00000004 */
2224 #define CAN_ESR_BOFF           CAN_ESR_BOFF_Msk                                /*!<Bus-Off Flag */
2225 
2226 #define CAN_ESR_LEC_Pos        (4U)
2227 #define CAN_ESR_LEC_Msk        (0x7UL << CAN_ESR_LEC_Pos)                       /*!< 0x00000070 */
2228 #define CAN_ESR_LEC            CAN_ESR_LEC_Msk                                 /*!<LEC[2:0] bits (Last Error Code) */
2229 #define CAN_ESR_LEC_0          (0x1UL << CAN_ESR_LEC_Pos)                       /*!< 0x00000010 */
2230 #define CAN_ESR_LEC_1          (0x2UL << CAN_ESR_LEC_Pos)                       /*!< 0x00000020 */
2231 #define CAN_ESR_LEC_2          (0x4UL << CAN_ESR_LEC_Pos)                       /*!< 0x00000040 */
2232 
2233 #define CAN_ESR_TEC_Pos        (16U)
2234 #define CAN_ESR_TEC_Msk        (0xFFUL << CAN_ESR_TEC_Pos)                      /*!< 0x00FF0000 */
2235 #define CAN_ESR_TEC            CAN_ESR_TEC_Msk                                 /*!<Least significant byte of the 9-bit Transmit Error Counter */
2236 #define CAN_ESR_REC_Pos        (24U)
2237 #define CAN_ESR_REC_Msk        (0xFFUL << CAN_ESR_REC_Pos)                      /*!< 0xFF000000 */
2238 #define CAN_ESR_REC            CAN_ESR_REC_Msk                                 /*!<Receive Error Counter */
2239 
2240 /*******************  Bit definition for CAN_BTR register  ********************/
2241 #define CAN_BTR_BRP_Pos        (0U)
2242 #define CAN_BTR_BRP_Msk        (0x3FFUL << CAN_BTR_BRP_Pos)                     /*!< 0x000003FF */
2243 #define CAN_BTR_BRP            CAN_BTR_BRP_Msk                                 /*!<Baud Rate Prescaler */
2244 #define CAN_BTR_TS1_Pos        (16U)
2245 #define CAN_BTR_TS1_Msk        (0xFUL << CAN_BTR_TS1_Pos)                       /*!< 0x000F0000 */
2246 #define CAN_BTR_TS1            CAN_BTR_TS1_Msk                                 /*!<Time Segment 1 */
2247 #define CAN_BTR_TS1_0          (0x1UL << CAN_BTR_TS1_Pos)                       /*!< 0x00010000 */
2248 #define CAN_BTR_TS1_1          (0x2UL << CAN_BTR_TS1_Pos)                       /*!< 0x00020000 */
2249 #define CAN_BTR_TS1_2          (0x4UL << CAN_BTR_TS1_Pos)                       /*!< 0x00040000 */
2250 #define CAN_BTR_TS1_3          (0x8UL << CAN_BTR_TS1_Pos)                       /*!< 0x00080000 */
2251 #define CAN_BTR_TS2_Pos        (20U)
2252 #define CAN_BTR_TS2_Msk        (0x7UL << CAN_BTR_TS2_Pos)                       /*!< 0x00700000 */
2253 #define CAN_BTR_TS2            CAN_BTR_TS2_Msk                                 /*!<Time Segment 2 */
2254 #define CAN_BTR_TS2_0          (0x1UL << CAN_BTR_TS2_Pos)                       /*!< 0x00100000 */
2255 #define CAN_BTR_TS2_1          (0x2UL << CAN_BTR_TS2_Pos)                       /*!< 0x00200000 */
2256 #define CAN_BTR_TS2_2          (0x4UL << CAN_BTR_TS2_Pos)                       /*!< 0x00400000 */
2257 #define CAN_BTR_SJW_Pos        (24U)
2258 #define CAN_BTR_SJW_Msk        (0x3UL << CAN_BTR_SJW_Pos)                       /*!< 0x03000000 */
2259 #define CAN_BTR_SJW            CAN_BTR_SJW_Msk                                 /*!<Resynchronization Jump Width */
2260 #define CAN_BTR_SJW_0          (0x1UL << CAN_BTR_SJW_Pos)                       /*!< 0x01000000 */
2261 #define CAN_BTR_SJW_1          (0x2UL << CAN_BTR_SJW_Pos)                       /*!< 0x02000000 */
2262 #define CAN_BTR_LBKM_Pos       (30U)
2263 #define CAN_BTR_LBKM_Msk       (0x1UL << CAN_BTR_LBKM_Pos)                      /*!< 0x40000000 */
2264 #define CAN_BTR_LBKM           CAN_BTR_LBKM_Msk                                /*!<Loop Back Mode (Debug) */
2265 #define CAN_BTR_SILM_Pos       (31U)
2266 #define CAN_BTR_SILM_Msk       (0x1UL << CAN_BTR_SILM_Pos)                      /*!< 0x80000000 */
2267 #define CAN_BTR_SILM           CAN_BTR_SILM_Msk                                /*!<Silent Mode */
2268 
2269 
2270 /*!<Mailbox registers */
2271 /******************  Bit definition for CAN_TI0R register  ********************/
2272 #define CAN_TI0R_TXRQ_Pos      (0U)
2273 #define CAN_TI0R_TXRQ_Msk      (0x1UL << CAN_TI0R_TXRQ_Pos)                     /*!< 0x00000001 */
2274 #define CAN_TI0R_TXRQ          CAN_TI0R_TXRQ_Msk                               /*!<Transmit Mailbox Request */
2275 #define CAN_TI0R_RTR_Pos       (1U)
2276 #define CAN_TI0R_RTR_Msk       (0x1UL << CAN_TI0R_RTR_Pos)                      /*!< 0x00000002 */
2277 #define CAN_TI0R_RTR           CAN_TI0R_RTR_Msk                                /*!<Remote Transmission Request */
2278 #define CAN_TI0R_IDE_Pos       (2U)
2279 #define CAN_TI0R_IDE_Msk       (0x1UL << CAN_TI0R_IDE_Pos)                      /*!< 0x00000004 */
2280 #define CAN_TI0R_IDE           CAN_TI0R_IDE_Msk                                /*!<Identifier Extension */
2281 #define CAN_TI0R_EXID_Pos      (3U)
2282 #define CAN_TI0R_EXID_Msk      (0x3FFFFUL << CAN_TI0R_EXID_Pos)                 /*!< 0x001FFFF8 */
2283 #define CAN_TI0R_EXID          CAN_TI0R_EXID_Msk                               /*!<Extended Identifier */
2284 #define CAN_TI0R_STID_Pos      (21U)
2285 #define CAN_TI0R_STID_Msk      (0x7FFUL << CAN_TI0R_STID_Pos)                   /*!< 0xFFE00000 */
2286 #define CAN_TI0R_STID          CAN_TI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
2287 
2288 /******************  Bit definition for CAN_TDT0R register  *******************/
2289 #define CAN_TDT0R_DLC_Pos      (0U)
2290 #define CAN_TDT0R_DLC_Msk      (0xFUL << CAN_TDT0R_DLC_Pos)                     /*!< 0x0000000F */
2291 #define CAN_TDT0R_DLC          CAN_TDT0R_DLC_Msk                               /*!<Data Length Code */
2292 #define CAN_TDT0R_TGT_Pos      (8U)
2293 #define CAN_TDT0R_TGT_Msk      (0x1UL << CAN_TDT0R_TGT_Pos)                     /*!< 0x00000100 */
2294 #define CAN_TDT0R_TGT          CAN_TDT0R_TGT_Msk                               /*!<Transmit Global Time */
2295 #define CAN_TDT0R_TIME_Pos     (16U)
2296 #define CAN_TDT0R_TIME_Msk     (0xFFFFUL << CAN_TDT0R_TIME_Pos)                 /*!< 0xFFFF0000 */
2297 #define CAN_TDT0R_TIME         CAN_TDT0R_TIME_Msk                              /*!<Message Time Stamp */
2298 
2299 /******************  Bit definition for CAN_TDL0R register  *******************/
2300 #define CAN_TDL0R_DATA0_Pos    (0U)
2301 #define CAN_TDL0R_DATA0_Msk    (0xFFUL << CAN_TDL0R_DATA0_Pos)                  /*!< 0x000000FF */
2302 #define CAN_TDL0R_DATA0        CAN_TDL0R_DATA0_Msk                             /*!<Data byte 0 */
2303 #define CAN_TDL0R_DATA1_Pos    (8U)
2304 #define CAN_TDL0R_DATA1_Msk    (0xFFUL << CAN_TDL0R_DATA1_Pos)                  /*!< 0x0000FF00 */
2305 #define CAN_TDL0R_DATA1        CAN_TDL0R_DATA1_Msk                             /*!<Data byte 1 */
2306 #define CAN_TDL0R_DATA2_Pos    (16U)
2307 #define CAN_TDL0R_DATA2_Msk    (0xFFUL << CAN_TDL0R_DATA2_Pos)                  /*!< 0x00FF0000 */
2308 #define CAN_TDL0R_DATA2        CAN_TDL0R_DATA2_Msk                             /*!<Data byte 2 */
2309 #define CAN_TDL0R_DATA3_Pos    (24U)
2310 #define CAN_TDL0R_DATA3_Msk    (0xFFUL << CAN_TDL0R_DATA3_Pos)                  /*!< 0xFF000000 */
2311 #define CAN_TDL0R_DATA3        CAN_TDL0R_DATA3_Msk                             /*!<Data byte 3 */
2312 
2313 /******************  Bit definition for CAN_TDH0R register  *******************/
2314 #define CAN_TDH0R_DATA4_Pos    (0U)
2315 #define CAN_TDH0R_DATA4_Msk    (0xFFUL << CAN_TDH0R_DATA4_Pos)                  /*!< 0x000000FF */
2316 #define CAN_TDH0R_DATA4        CAN_TDH0R_DATA4_Msk                             /*!<Data byte 4 */
2317 #define CAN_TDH0R_DATA5_Pos    (8U)
2318 #define CAN_TDH0R_DATA5_Msk    (0xFFUL << CAN_TDH0R_DATA5_Pos)                  /*!< 0x0000FF00 */
2319 #define CAN_TDH0R_DATA5        CAN_TDH0R_DATA5_Msk                             /*!<Data byte 5 */
2320 #define CAN_TDH0R_DATA6_Pos    (16U)
2321 #define CAN_TDH0R_DATA6_Msk    (0xFFUL << CAN_TDH0R_DATA6_Pos)                  /*!< 0x00FF0000 */
2322 #define CAN_TDH0R_DATA6        CAN_TDH0R_DATA6_Msk                             /*!<Data byte 6 */
2323 #define CAN_TDH0R_DATA7_Pos    (24U)
2324 #define CAN_TDH0R_DATA7_Msk    (0xFFUL << CAN_TDH0R_DATA7_Pos)                  /*!< 0xFF000000 */
2325 #define CAN_TDH0R_DATA7        CAN_TDH0R_DATA7_Msk                             /*!<Data byte 7 */
2326 
2327 /*******************  Bit definition for CAN_TI1R register  *******************/
2328 #define CAN_TI1R_TXRQ_Pos      (0U)
2329 #define CAN_TI1R_TXRQ_Msk      (0x1UL << CAN_TI1R_TXRQ_Pos)                     /*!< 0x00000001 */
2330 #define CAN_TI1R_TXRQ          CAN_TI1R_TXRQ_Msk                               /*!<Transmit Mailbox Request */
2331 #define CAN_TI1R_RTR_Pos       (1U)
2332 #define CAN_TI1R_RTR_Msk       (0x1UL << CAN_TI1R_RTR_Pos)                      /*!< 0x00000002 */
2333 #define CAN_TI1R_RTR           CAN_TI1R_RTR_Msk                                /*!<Remote Transmission Request */
2334 #define CAN_TI1R_IDE_Pos       (2U)
2335 #define CAN_TI1R_IDE_Msk       (0x1UL << CAN_TI1R_IDE_Pos)                      /*!< 0x00000004 */
2336 #define CAN_TI1R_IDE           CAN_TI1R_IDE_Msk                                /*!<Identifier Extension */
2337 #define CAN_TI1R_EXID_Pos      (3U)
2338 #define CAN_TI1R_EXID_Msk      (0x3FFFFUL << CAN_TI1R_EXID_Pos)                 /*!< 0x001FFFF8 */
2339 #define CAN_TI1R_EXID          CAN_TI1R_EXID_Msk                               /*!<Extended Identifier */
2340 #define CAN_TI1R_STID_Pos      (21U)
2341 #define CAN_TI1R_STID_Msk      (0x7FFUL << CAN_TI1R_STID_Pos)                   /*!< 0xFFE00000 */
2342 #define CAN_TI1R_STID          CAN_TI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
2343 
2344 /*******************  Bit definition for CAN_TDT1R register  ******************/
2345 #define CAN_TDT1R_DLC_Pos      (0U)
2346 #define CAN_TDT1R_DLC_Msk      (0xFUL << CAN_TDT1R_DLC_Pos)                     /*!< 0x0000000F */
2347 #define CAN_TDT1R_DLC          CAN_TDT1R_DLC_Msk                               /*!<Data Length Code */
2348 #define CAN_TDT1R_TGT_Pos      (8U)
2349 #define CAN_TDT1R_TGT_Msk      (0x1UL << CAN_TDT1R_TGT_Pos)                     /*!< 0x00000100 */
2350 #define CAN_TDT1R_TGT          CAN_TDT1R_TGT_Msk                               /*!<Transmit Global Time */
2351 #define CAN_TDT1R_TIME_Pos     (16U)
2352 #define CAN_TDT1R_TIME_Msk     (0xFFFFUL << CAN_TDT1R_TIME_Pos)                 /*!< 0xFFFF0000 */
2353 #define CAN_TDT1R_TIME         CAN_TDT1R_TIME_Msk                              /*!<Message Time Stamp */
2354 
2355 /*******************  Bit definition for CAN_TDL1R register  ******************/
2356 #define CAN_TDL1R_DATA0_Pos    (0U)
2357 #define CAN_TDL1R_DATA0_Msk    (0xFFUL << CAN_TDL1R_DATA0_Pos)                  /*!< 0x000000FF */
2358 #define CAN_TDL1R_DATA0        CAN_TDL1R_DATA0_Msk                             /*!<Data byte 0 */
2359 #define CAN_TDL1R_DATA1_Pos    (8U)
2360 #define CAN_TDL1R_DATA1_Msk    (0xFFUL << CAN_TDL1R_DATA1_Pos)                  /*!< 0x0000FF00 */
2361 #define CAN_TDL1R_DATA1        CAN_TDL1R_DATA1_Msk                             /*!<Data byte 1 */
2362 #define CAN_TDL1R_DATA2_Pos    (16U)
2363 #define CAN_TDL1R_DATA2_Msk    (0xFFUL << CAN_TDL1R_DATA2_Pos)                  /*!< 0x00FF0000 */
2364 #define CAN_TDL1R_DATA2        CAN_TDL1R_DATA2_Msk                             /*!<Data byte 2 */
2365 #define CAN_TDL1R_DATA3_Pos    (24U)
2366 #define CAN_TDL1R_DATA3_Msk    (0xFFUL << CAN_TDL1R_DATA3_Pos)                  /*!< 0xFF000000 */
2367 #define CAN_TDL1R_DATA3        CAN_TDL1R_DATA3_Msk                             /*!<Data byte 3 */
2368 
2369 /*******************  Bit definition for CAN_TDH1R register  ******************/
2370 #define CAN_TDH1R_DATA4_Pos    (0U)
2371 #define CAN_TDH1R_DATA4_Msk    (0xFFUL << CAN_TDH1R_DATA4_Pos)                  /*!< 0x000000FF */
2372 #define CAN_TDH1R_DATA4        CAN_TDH1R_DATA4_Msk                             /*!<Data byte 4 */
2373 #define CAN_TDH1R_DATA5_Pos    (8U)
2374 #define CAN_TDH1R_DATA5_Msk    (0xFFUL << CAN_TDH1R_DATA5_Pos)                  /*!< 0x0000FF00 */
2375 #define CAN_TDH1R_DATA5        CAN_TDH1R_DATA5_Msk                             /*!<Data byte 5 */
2376 #define CAN_TDH1R_DATA6_Pos    (16U)
2377 #define CAN_TDH1R_DATA6_Msk    (0xFFUL << CAN_TDH1R_DATA6_Pos)                  /*!< 0x00FF0000 */
2378 #define CAN_TDH1R_DATA6        CAN_TDH1R_DATA6_Msk                             /*!<Data byte 6 */
2379 #define CAN_TDH1R_DATA7_Pos    (24U)
2380 #define CAN_TDH1R_DATA7_Msk    (0xFFUL << CAN_TDH1R_DATA7_Pos)                  /*!< 0xFF000000 */
2381 #define CAN_TDH1R_DATA7        CAN_TDH1R_DATA7_Msk                             /*!<Data byte 7 */
2382 
2383 /*******************  Bit definition for CAN_TI2R register  *******************/
2384 #define CAN_TI2R_TXRQ_Pos      (0U)
2385 #define CAN_TI2R_TXRQ_Msk      (0x1UL << CAN_TI2R_TXRQ_Pos)                     /*!< 0x00000001 */
2386 #define CAN_TI2R_TXRQ          CAN_TI2R_TXRQ_Msk                               /*!<Transmit Mailbox Request */
2387 #define CAN_TI2R_RTR_Pos       (1U)
2388 #define CAN_TI2R_RTR_Msk       (0x1UL << CAN_TI2R_RTR_Pos)                      /*!< 0x00000002 */
2389 #define CAN_TI2R_RTR           CAN_TI2R_RTR_Msk                                /*!<Remote Transmission Request */
2390 #define CAN_TI2R_IDE_Pos       (2U)
2391 #define CAN_TI2R_IDE_Msk       (0x1UL << CAN_TI2R_IDE_Pos)                      /*!< 0x00000004 */
2392 #define CAN_TI2R_IDE           CAN_TI2R_IDE_Msk                                /*!<Identifier Extension */
2393 #define CAN_TI2R_EXID_Pos      (3U)
2394 #define CAN_TI2R_EXID_Msk      (0x3FFFFUL << CAN_TI2R_EXID_Pos)                 /*!< 0x001FFFF8 */
2395 #define CAN_TI2R_EXID          CAN_TI2R_EXID_Msk                               /*!<Extended identifier */
2396 #define CAN_TI2R_STID_Pos      (21U)
2397 #define CAN_TI2R_STID_Msk      (0x7FFUL << CAN_TI2R_STID_Pos)                   /*!< 0xFFE00000 */
2398 #define CAN_TI2R_STID          CAN_TI2R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
2399 
2400 /*******************  Bit definition for CAN_TDT2R register  ******************/
2401 #define CAN_TDT2R_DLC_Pos      (0U)
2402 #define CAN_TDT2R_DLC_Msk      (0xFUL << CAN_TDT2R_DLC_Pos)                     /*!< 0x0000000F */
2403 #define CAN_TDT2R_DLC          CAN_TDT2R_DLC_Msk                               /*!<Data Length Code */
2404 #define CAN_TDT2R_TGT_Pos      (8U)
2405 #define CAN_TDT2R_TGT_Msk      (0x1UL << CAN_TDT2R_TGT_Pos)                     /*!< 0x00000100 */
2406 #define CAN_TDT2R_TGT          CAN_TDT2R_TGT_Msk                               /*!<Transmit Global Time */
2407 #define CAN_TDT2R_TIME_Pos     (16U)
2408 #define CAN_TDT2R_TIME_Msk     (0xFFFFUL << CAN_TDT2R_TIME_Pos)                 /*!< 0xFFFF0000 */
2409 #define CAN_TDT2R_TIME         CAN_TDT2R_TIME_Msk                              /*!<Message Time Stamp */
2410 
2411 /*******************  Bit definition for CAN_TDL2R register  ******************/
2412 #define CAN_TDL2R_DATA0_Pos    (0U)
2413 #define CAN_TDL2R_DATA0_Msk    (0xFFUL << CAN_TDL2R_DATA0_Pos)                  /*!< 0x000000FF */
2414 #define CAN_TDL2R_DATA0        CAN_TDL2R_DATA0_Msk                             /*!<Data byte 0 */
2415 #define CAN_TDL2R_DATA1_Pos    (8U)
2416 #define CAN_TDL2R_DATA1_Msk    (0xFFUL << CAN_TDL2R_DATA1_Pos)                  /*!< 0x0000FF00 */
2417 #define CAN_TDL2R_DATA1        CAN_TDL2R_DATA1_Msk                             /*!<Data byte 1 */
2418 #define CAN_TDL2R_DATA2_Pos    (16U)
2419 #define CAN_TDL2R_DATA2_Msk    (0xFFUL << CAN_TDL2R_DATA2_Pos)                  /*!< 0x00FF0000 */
2420 #define CAN_TDL2R_DATA2        CAN_TDL2R_DATA2_Msk                             /*!<Data byte 2 */
2421 #define CAN_TDL2R_DATA3_Pos    (24U)
2422 #define CAN_TDL2R_DATA3_Msk    (0xFFUL << CAN_TDL2R_DATA3_Pos)                  /*!< 0xFF000000 */
2423 #define CAN_TDL2R_DATA3        CAN_TDL2R_DATA3_Msk                             /*!<Data byte 3 */
2424 
2425 /*******************  Bit definition for CAN_TDH2R register  ******************/
2426 #define CAN_TDH2R_DATA4_Pos    (0U)
2427 #define CAN_TDH2R_DATA4_Msk    (0xFFUL << CAN_TDH2R_DATA4_Pos)                  /*!< 0x000000FF */
2428 #define CAN_TDH2R_DATA4        CAN_TDH2R_DATA4_Msk                             /*!<Data byte 4 */
2429 #define CAN_TDH2R_DATA5_Pos    (8U)
2430 #define CAN_TDH2R_DATA5_Msk    (0xFFUL << CAN_TDH2R_DATA5_Pos)                  /*!< 0x0000FF00 */
2431 #define CAN_TDH2R_DATA5        CAN_TDH2R_DATA5_Msk                             /*!<Data byte 5 */
2432 #define CAN_TDH2R_DATA6_Pos    (16U)
2433 #define CAN_TDH2R_DATA6_Msk    (0xFFUL << CAN_TDH2R_DATA6_Pos)                  /*!< 0x00FF0000 */
2434 #define CAN_TDH2R_DATA6        CAN_TDH2R_DATA6_Msk                             /*!<Data byte 6 */
2435 #define CAN_TDH2R_DATA7_Pos    (24U)
2436 #define CAN_TDH2R_DATA7_Msk    (0xFFUL << CAN_TDH2R_DATA7_Pos)                  /*!< 0xFF000000 */
2437 #define CAN_TDH2R_DATA7        CAN_TDH2R_DATA7_Msk                             /*!<Data byte 7 */
2438 
2439 /*******************  Bit definition for CAN_RI0R register  *******************/
2440 #define CAN_RI0R_RTR_Pos       (1U)
2441 #define CAN_RI0R_RTR_Msk       (0x1UL << CAN_RI0R_RTR_Pos)                      /*!< 0x00000002 */
2442 #define CAN_RI0R_RTR           CAN_RI0R_RTR_Msk                                /*!<Remote Transmission Request */
2443 #define CAN_RI0R_IDE_Pos       (2U)
2444 #define CAN_RI0R_IDE_Msk       (0x1UL << CAN_RI0R_IDE_Pos)                      /*!< 0x00000004 */
2445 #define CAN_RI0R_IDE           CAN_RI0R_IDE_Msk                                /*!<Identifier Extension */
2446 #define CAN_RI0R_EXID_Pos      (3U)
2447 #define CAN_RI0R_EXID_Msk      (0x3FFFFUL << CAN_RI0R_EXID_Pos)                 /*!< 0x001FFFF8 */
2448 #define CAN_RI0R_EXID          CAN_RI0R_EXID_Msk                               /*!<Extended Identifier */
2449 #define CAN_RI0R_STID_Pos      (21U)
2450 #define CAN_RI0R_STID_Msk      (0x7FFUL << CAN_RI0R_STID_Pos)                   /*!< 0xFFE00000 */
2451 #define CAN_RI0R_STID          CAN_RI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
2452 
2453 /*******************  Bit definition for CAN_RDT0R register  ******************/
2454 #define CAN_RDT0R_DLC_Pos      (0U)
2455 #define CAN_RDT0R_DLC_Msk      (0xFUL << CAN_RDT0R_DLC_Pos)                     /*!< 0x0000000F */
2456 #define CAN_RDT0R_DLC          CAN_RDT0R_DLC_Msk                               /*!<Data Length Code */
2457 #define CAN_RDT0R_FMI_Pos      (8U)
2458 #define CAN_RDT0R_FMI_Msk      (0xFFUL << CAN_RDT0R_FMI_Pos)                    /*!< 0x0000FF00 */
2459 #define CAN_RDT0R_FMI          CAN_RDT0R_FMI_Msk                               /*!<Filter Match Index */
2460 #define CAN_RDT0R_TIME_Pos     (16U)
2461 #define CAN_RDT0R_TIME_Msk     (0xFFFFUL << CAN_RDT0R_TIME_Pos)                 /*!< 0xFFFF0000 */
2462 #define CAN_RDT0R_TIME         CAN_RDT0R_TIME_Msk                              /*!<Message Time Stamp */
2463 
2464 /*******************  Bit definition for CAN_RDL0R register  ******************/
2465 #define CAN_RDL0R_DATA0_Pos    (0U)
2466 #define CAN_RDL0R_DATA0_Msk    (0xFFUL << CAN_RDL0R_DATA0_Pos)                  /*!< 0x000000FF */
2467 #define CAN_RDL0R_DATA0        CAN_RDL0R_DATA0_Msk                             /*!<Data byte 0 */
2468 #define CAN_RDL0R_DATA1_Pos    (8U)
2469 #define CAN_RDL0R_DATA1_Msk    (0xFFUL << CAN_RDL0R_DATA1_Pos)                  /*!< 0x0000FF00 */
2470 #define CAN_RDL0R_DATA1        CAN_RDL0R_DATA1_Msk                             /*!<Data byte 1 */
2471 #define CAN_RDL0R_DATA2_Pos    (16U)
2472 #define CAN_RDL0R_DATA2_Msk    (0xFFUL << CAN_RDL0R_DATA2_Pos)                  /*!< 0x00FF0000 */
2473 #define CAN_RDL0R_DATA2        CAN_RDL0R_DATA2_Msk                             /*!<Data byte 2 */
2474 #define CAN_RDL0R_DATA3_Pos    (24U)
2475 #define CAN_RDL0R_DATA3_Msk    (0xFFUL << CAN_RDL0R_DATA3_Pos)                  /*!< 0xFF000000 */
2476 #define CAN_RDL0R_DATA3        CAN_RDL0R_DATA3_Msk                             /*!<Data byte 3 */
2477 
2478 /*******************  Bit definition for CAN_RDH0R register  ******************/
2479 #define CAN_RDH0R_DATA4_Pos    (0U)
2480 #define CAN_RDH0R_DATA4_Msk    (0xFFUL << CAN_RDH0R_DATA4_Pos)                  /*!< 0x000000FF */
2481 #define CAN_RDH0R_DATA4        CAN_RDH0R_DATA4_Msk                             /*!<Data byte 4 */
2482 #define CAN_RDH0R_DATA5_Pos    (8U)
2483 #define CAN_RDH0R_DATA5_Msk    (0xFFUL << CAN_RDH0R_DATA5_Pos)                  /*!< 0x0000FF00 */
2484 #define CAN_RDH0R_DATA5        CAN_RDH0R_DATA5_Msk                             /*!<Data byte 5 */
2485 #define CAN_RDH0R_DATA6_Pos    (16U)
2486 #define CAN_RDH0R_DATA6_Msk    (0xFFUL << CAN_RDH0R_DATA6_Pos)                  /*!< 0x00FF0000 */
2487 #define CAN_RDH0R_DATA6        CAN_RDH0R_DATA6_Msk                             /*!<Data byte 6 */
2488 #define CAN_RDH0R_DATA7_Pos    (24U)
2489 #define CAN_RDH0R_DATA7_Msk    (0xFFUL << CAN_RDH0R_DATA7_Pos)                  /*!< 0xFF000000 */
2490 #define CAN_RDH0R_DATA7        CAN_RDH0R_DATA7_Msk                             /*!<Data byte 7 */
2491 
2492 /*******************  Bit definition for CAN_RI1R register  *******************/
2493 #define CAN_RI1R_RTR_Pos       (1U)
2494 #define CAN_RI1R_RTR_Msk       (0x1UL << CAN_RI1R_RTR_Pos)                      /*!< 0x00000002 */
2495 #define CAN_RI1R_RTR           CAN_RI1R_RTR_Msk                                /*!<Remote Transmission Request */
2496 #define CAN_RI1R_IDE_Pos       (2U)
2497 #define CAN_RI1R_IDE_Msk       (0x1UL << CAN_RI1R_IDE_Pos)                      /*!< 0x00000004 */
2498 #define CAN_RI1R_IDE           CAN_RI1R_IDE_Msk                                /*!<Identifier Extension */
2499 #define CAN_RI1R_EXID_Pos      (3U)
2500 #define CAN_RI1R_EXID_Msk      (0x3FFFFUL << CAN_RI1R_EXID_Pos)                 /*!< 0x001FFFF8 */
2501 #define CAN_RI1R_EXID          CAN_RI1R_EXID_Msk                               /*!<Extended identifier */
2502 #define CAN_RI1R_STID_Pos      (21U)
2503 #define CAN_RI1R_STID_Msk      (0x7FFUL << CAN_RI1R_STID_Pos)                   /*!< 0xFFE00000 */
2504 #define CAN_RI1R_STID          CAN_RI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
2505 
2506 /*******************  Bit definition for CAN_RDT1R register  ******************/
2507 #define CAN_RDT1R_DLC_Pos      (0U)
2508 #define CAN_RDT1R_DLC_Msk      (0xFUL << CAN_RDT1R_DLC_Pos)                     /*!< 0x0000000F */
2509 #define CAN_RDT1R_DLC          CAN_RDT1R_DLC_Msk                               /*!<Data Length Code */
2510 #define CAN_RDT1R_FMI_Pos      (8U)
2511 #define CAN_RDT1R_FMI_Msk      (0xFFUL << CAN_RDT1R_FMI_Pos)                    /*!< 0x0000FF00 */
2512 #define CAN_RDT1R_FMI          CAN_RDT1R_FMI_Msk                               /*!<Filter Match Index */
2513 #define CAN_RDT1R_TIME_Pos     (16U)
2514 #define CAN_RDT1R_TIME_Msk     (0xFFFFUL << CAN_RDT1R_TIME_Pos)                 /*!< 0xFFFF0000 */
2515 #define CAN_RDT1R_TIME         CAN_RDT1R_TIME_Msk                              /*!<Message Time Stamp */
2516 
2517 /*******************  Bit definition for CAN_RDL1R register  ******************/
2518 #define CAN_RDL1R_DATA0_Pos    (0U)
2519 #define CAN_RDL1R_DATA0_Msk    (0xFFUL << CAN_RDL1R_DATA0_Pos)                  /*!< 0x000000FF */
2520 #define CAN_RDL1R_DATA0        CAN_RDL1R_DATA0_Msk                             /*!<Data byte 0 */
2521 #define CAN_RDL1R_DATA1_Pos    (8U)
2522 #define CAN_RDL1R_DATA1_Msk    (0xFFUL << CAN_RDL1R_DATA1_Pos)                  /*!< 0x0000FF00 */
2523 #define CAN_RDL1R_DATA1        CAN_RDL1R_DATA1_Msk                             /*!<Data byte 1 */
2524 #define CAN_RDL1R_DATA2_Pos    (16U)
2525 #define CAN_RDL1R_DATA2_Msk    (0xFFUL << CAN_RDL1R_DATA2_Pos)                  /*!< 0x00FF0000 */
2526 #define CAN_RDL1R_DATA2        CAN_RDL1R_DATA2_Msk                             /*!<Data byte 2 */
2527 #define CAN_RDL1R_DATA3_Pos    (24U)
2528 #define CAN_RDL1R_DATA3_Msk    (0xFFUL << CAN_RDL1R_DATA3_Pos)                  /*!< 0xFF000000 */
2529 #define CAN_RDL1R_DATA3        CAN_RDL1R_DATA3_Msk                             /*!<Data byte 3 */
2530 
2531 /*******************  Bit definition for CAN_RDH1R register  ******************/
2532 #define CAN_RDH1R_DATA4_Pos    (0U)
2533 #define CAN_RDH1R_DATA4_Msk    (0xFFUL << CAN_RDH1R_DATA4_Pos)                  /*!< 0x000000FF */
2534 #define CAN_RDH1R_DATA4        CAN_RDH1R_DATA4_Msk                             /*!<Data byte 4 */
2535 #define CAN_RDH1R_DATA5_Pos    (8U)
2536 #define CAN_RDH1R_DATA5_Msk    (0xFFUL << CAN_RDH1R_DATA5_Pos)                  /*!< 0x0000FF00 */
2537 #define CAN_RDH1R_DATA5        CAN_RDH1R_DATA5_Msk                             /*!<Data byte 5 */
2538 #define CAN_RDH1R_DATA6_Pos    (16U)
2539 #define CAN_RDH1R_DATA6_Msk    (0xFFUL << CAN_RDH1R_DATA6_Pos)                  /*!< 0x00FF0000 */
2540 #define CAN_RDH1R_DATA6        CAN_RDH1R_DATA6_Msk                             /*!<Data byte 6 */
2541 #define CAN_RDH1R_DATA7_Pos    (24U)
2542 #define CAN_RDH1R_DATA7_Msk    (0xFFUL << CAN_RDH1R_DATA7_Pos)                  /*!< 0xFF000000 */
2543 #define CAN_RDH1R_DATA7        CAN_RDH1R_DATA7_Msk                             /*!<Data byte 7 */
2544 
2545 /*!<CAN filter registers */
2546 /*******************  Bit definition for CAN_FMR register  ********************/
2547 #define CAN_FMR_FINIT_Pos      (0U)
2548 #define CAN_FMR_FINIT_Msk      (0x1UL << CAN_FMR_FINIT_Pos)                     /*!< 0x00000001 */
2549 #define CAN_FMR_FINIT          CAN_FMR_FINIT_Msk                               /*!<Filter Init Mode */
2550 #define CAN_FMR_CAN2SB_Pos     (8U)
2551 #define CAN_FMR_CAN2SB_Msk     (0x3FUL << CAN_FMR_CAN2SB_Pos)                   /*!< 0x00003F00 */
2552 #define CAN_FMR_CAN2SB         CAN_FMR_CAN2SB_Msk                              /*!<CAN2 start bank */
2553 
2554 /*******************  Bit definition for CAN_FM1R register  *******************/
2555 #define CAN_FM1R_FBM_Pos       (0U)
2556 #define CAN_FM1R_FBM_Msk       (0xFFFFFFFUL << CAN_FM1R_FBM_Pos)                /*!< 0x0FFFFFFF */
2557 #define CAN_FM1R_FBM           CAN_FM1R_FBM_Msk                                /*!<Filter Mode */
2558 #define CAN_FM1R_FBM0_Pos      (0U)
2559 #define CAN_FM1R_FBM0_Msk      (0x1UL << CAN_FM1R_FBM0_Pos)                     /*!< 0x00000001 */
2560 #define CAN_FM1R_FBM0          CAN_FM1R_FBM0_Msk                               /*!<Filter Init Mode bit 0 */
2561 #define CAN_FM1R_FBM1_Pos      (1U)
2562 #define CAN_FM1R_FBM1_Msk      (0x1UL << CAN_FM1R_FBM1_Pos)                     /*!< 0x00000002 */
2563 #define CAN_FM1R_FBM1          CAN_FM1R_FBM1_Msk                               /*!<Filter Init Mode bit 1 */
2564 #define CAN_FM1R_FBM2_Pos      (2U)
2565 #define CAN_FM1R_FBM2_Msk      (0x1UL << CAN_FM1R_FBM2_Pos)                     /*!< 0x00000004 */
2566 #define CAN_FM1R_FBM2          CAN_FM1R_FBM2_Msk                               /*!<Filter Init Mode bit 2 */
2567 #define CAN_FM1R_FBM3_Pos      (3U)
2568 #define CAN_FM1R_FBM3_Msk      (0x1UL << CAN_FM1R_FBM3_Pos)                     /*!< 0x00000008 */
2569 #define CAN_FM1R_FBM3          CAN_FM1R_FBM3_Msk                               /*!<Filter Init Mode bit 3 */
2570 #define CAN_FM1R_FBM4_Pos      (4U)
2571 #define CAN_FM1R_FBM4_Msk      (0x1UL << CAN_FM1R_FBM4_Pos)                     /*!< 0x00000010 */
2572 #define CAN_FM1R_FBM4          CAN_FM1R_FBM4_Msk                               /*!<Filter Init Mode bit 4 */
2573 #define CAN_FM1R_FBM5_Pos      (5U)
2574 #define CAN_FM1R_FBM5_Msk      (0x1UL << CAN_FM1R_FBM5_Pos)                     /*!< 0x00000020 */
2575 #define CAN_FM1R_FBM5          CAN_FM1R_FBM5_Msk                               /*!<Filter Init Mode bit 5 */
2576 #define CAN_FM1R_FBM6_Pos      (6U)
2577 #define CAN_FM1R_FBM6_Msk      (0x1UL << CAN_FM1R_FBM6_Pos)                     /*!< 0x00000040 */
2578 #define CAN_FM1R_FBM6          CAN_FM1R_FBM6_Msk                               /*!<Filter Init Mode bit 6 */
2579 #define CAN_FM1R_FBM7_Pos      (7U)
2580 #define CAN_FM1R_FBM7_Msk      (0x1UL << CAN_FM1R_FBM7_Pos)                     /*!< 0x00000080 */
2581 #define CAN_FM1R_FBM7          CAN_FM1R_FBM7_Msk                               /*!<Filter Init Mode bit 7 */
2582 #define CAN_FM1R_FBM8_Pos      (8U)
2583 #define CAN_FM1R_FBM8_Msk      (0x1UL << CAN_FM1R_FBM8_Pos)                     /*!< 0x00000100 */
2584 #define CAN_FM1R_FBM8          CAN_FM1R_FBM8_Msk                               /*!<Filter Init Mode bit 8 */
2585 #define CAN_FM1R_FBM9_Pos      (9U)
2586 #define CAN_FM1R_FBM9_Msk      (0x1UL << CAN_FM1R_FBM9_Pos)                     /*!< 0x00000200 */
2587 #define CAN_FM1R_FBM9          CAN_FM1R_FBM9_Msk                               /*!<Filter Init Mode bit 9 */
2588 #define CAN_FM1R_FBM10_Pos     (10U)
2589 #define CAN_FM1R_FBM10_Msk     (0x1UL << CAN_FM1R_FBM10_Pos)                    /*!< 0x00000400 */
2590 #define CAN_FM1R_FBM10         CAN_FM1R_FBM10_Msk                              /*!<Filter Init Mode bit 10 */
2591 #define CAN_FM1R_FBM11_Pos     (11U)
2592 #define CAN_FM1R_FBM11_Msk     (0x1UL << CAN_FM1R_FBM11_Pos)                    /*!< 0x00000800 */
2593 #define CAN_FM1R_FBM11         CAN_FM1R_FBM11_Msk                              /*!<Filter Init Mode bit 11 */
2594 #define CAN_FM1R_FBM12_Pos     (12U)
2595 #define CAN_FM1R_FBM12_Msk     (0x1UL << CAN_FM1R_FBM12_Pos)                    /*!< 0x00001000 */
2596 #define CAN_FM1R_FBM12         CAN_FM1R_FBM12_Msk                              /*!<Filter Init Mode bit 12 */
2597 #define CAN_FM1R_FBM13_Pos     (13U)
2598 #define CAN_FM1R_FBM13_Msk     (0x1UL << CAN_FM1R_FBM13_Pos)                    /*!< 0x00002000 */
2599 #define CAN_FM1R_FBM13         CAN_FM1R_FBM13_Msk                              /*!<Filter Init Mode bit 13 */
2600 #define CAN_FM1R_FBM14_Pos     (14U)
2601 #define CAN_FM1R_FBM14_Msk     (0x1UL << CAN_FM1R_FBM14_Pos)                    /*!< 0x00004000 */
2602 #define CAN_FM1R_FBM14         CAN_FM1R_FBM14_Msk                              /*!<Filter Init Mode bit 14 */
2603 #define CAN_FM1R_FBM15_Pos     (15U)
2604 #define CAN_FM1R_FBM15_Msk     (0x1UL << CAN_FM1R_FBM15_Pos)                    /*!< 0x00008000 */
2605 #define CAN_FM1R_FBM15         CAN_FM1R_FBM15_Msk                              /*!<Filter Init Mode bit 15 */
2606 #define CAN_FM1R_FBM16_Pos     (16U)
2607 #define CAN_FM1R_FBM16_Msk     (0x1UL << CAN_FM1R_FBM16_Pos)                    /*!< 0x00010000 */
2608 #define CAN_FM1R_FBM16         CAN_FM1R_FBM16_Msk                              /*!<Filter Init Mode bit 16 */
2609 #define CAN_FM1R_FBM17_Pos     (17U)
2610 #define CAN_FM1R_FBM17_Msk     (0x1UL << CAN_FM1R_FBM17_Pos)                    /*!< 0x00020000 */
2611 #define CAN_FM1R_FBM17         CAN_FM1R_FBM17_Msk                              /*!<Filter Init Mode bit 17 */
2612 #define CAN_FM1R_FBM18_Pos     (18U)
2613 #define CAN_FM1R_FBM18_Msk     (0x1UL << CAN_FM1R_FBM18_Pos)                    /*!< 0x00040000 */
2614 #define CAN_FM1R_FBM18         CAN_FM1R_FBM18_Msk                              /*!<Filter Init Mode bit 18 */
2615 #define CAN_FM1R_FBM19_Pos     (19U)
2616 #define CAN_FM1R_FBM19_Msk     (0x1UL << CAN_FM1R_FBM19_Pos)                    /*!< 0x00080000 */
2617 #define CAN_FM1R_FBM19         CAN_FM1R_FBM19_Msk                              /*!<Filter Init Mode bit 19 */
2618 #define CAN_FM1R_FBM20_Pos     (20U)
2619 #define CAN_FM1R_FBM20_Msk     (0x1UL << CAN_FM1R_FBM20_Pos)                    /*!< 0x00100000 */
2620 #define CAN_FM1R_FBM20         CAN_FM1R_FBM20_Msk                              /*!<Filter Init Mode bit 20 */
2621 #define CAN_FM1R_FBM21_Pos     (21U)
2622 #define CAN_FM1R_FBM21_Msk     (0x1UL << CAN_FM1R_FBM21_Pos)                    /*!< 0x00200000 */
2623 #define CAN_FM1R_FBM21         CAN_FM1R_FBM21_Msk                              /*!<Filter Init Mode bit 21 */
2624 #define CAN_FM1R_FBM22_Pos     (22U)
2625 #define CAN_FM1R_FBM22_Msk     (0x1UL << CAN_FM1R_FBM22_Pos)                    /*!< 0x00400000 */
2626 #define CAN_FM1R_FBM22         CAN_FM1R_FBM22_Msk                              /*!<Filter Init Mode bit 22 */
2627 #define CAN_FM1R_FBM23_Pos     (23U)
2628 #define CAN_FM1R_FBM23_Msk     (0x1UL << CAN_FM1R_FBM23_Pos)                    /*!< 0x00800000 */
2629 #define CAN_FM1R_FBM23         CAN_FM1R_FBM23_Msk                              /*!<Filter Init Mode bit 23 */
2630 #define CAN_FM1R_FBM24_Pos     (24U)
2631 #define CAN_FM1R_FBM24_Msk     (0x1UL << CAN_FM1R_FBM24_Pos)                    /*!< 0x01000000 */
2632 #define CAN_FM1R_FBM24         CAN_FM1R_FBM24_Msk                              /*!<Filter Init Mode bit 24 */
2633 #define CAN_FM1R_FBM25_Pos     (25U)
2634 #define CAN_FM1R_FBM25_Msk     (0x1UL << CAN_FM1R_FBM25_Pos)                    /*!< 0x02000000 */
2635 #define CAN_FM1R_FBM25         CAN_FM1R_FBM25_Msk                              /*!<Filter Init Mode bit 25 */
2636 #define CAN_FM1R_FBM26_Pos     (26U)
2637 #define CAN_FM1R_FBM26_Msk     (0x1UL << CAN_FM1R_FBM26_Pos)                    /*!< 0x04000000 */
2638 #define CAN_FM1R_FBM26         CAN_FM1R_FBM26_Msk                              /*!<Filter Init Mode bit 26 */
2639 #define CAN_FM1R_FBM27_Pos     (27U)
2640 #define CAN_FM1R_FBM27_Msk     (0x1UL << CAN_FM1R_FBM27_Pos)                    /*!< 0x08000000 */
2641 #define CAN_FM1R_FBM27         CAN_FM1R_FBM27_Msk                              /*!<Filter Init Mode bit 27 */
2642 
2643 /*******************  Bit definition for CAN_FS1R register  *******************/
2644 #define CAN_FS1R_FSC_Pos       (0U)
2645 #define CAN_FS1R_FSC_Msk       (0xFFFFFFFUL << CAN_FS1R_FSC_Pos)                /*!< 0x0FFFFFFF */
2646 #define CAN_FS1R_FSC           CAN_FS1R_FSC_Msk                                /*!<Filter Scale Configuration */
2647 #define CAN_FS1R_FSC0_Pos      (0U)
2648 #define CAN_FS1R_FSC0_Msk      (0x1UL << CAN_FS1R_FSC0_Pos)                     /*!< 0x00000001 */
2649 #define CAN_FS1R_FSC0          CAN_FS1R_FSC0_Msk                               /*!<Filter Scale Configuration bit 0 */
2650 #define CAN_FS1R_FSC1_Pos      (1U)
2651 #define CAN_FS1R_FSC1_Msk      (0x1UL << CAN_FS1R_FSC1_Pos)                     /*!< 0x00000002 */
2652 #define CAN_FS1R_FSC1          CAN_FS1R_FSC1_Msk                               /*!<Filter Scale Configuration bit 1 */
2653 #define CAN_FS1R_FSC2_Pos      (2U)
2654 #define CAN_FS1R_FSC2_Msk      (0x1UL << CAN_FS1R_FSC2_Pos)                     /*!< 0x00000004 */
2655 #define CAN_FS1R_FSC2          CAN_FS1R_FSC2_Msk                               /*!<Filter Scale Configuration bit 2 */
2656 #define CAN_FS1R_FSC3_Pos      (3U)
2657 #define CAN_FS1R_FSC3_Msk      (0x1UL << CAN_FS1R_FSC3_Pos)                     /*!< 0x00000008 */
2658 #define CAN_FS1R_FSC3          CAN_FS1R_FSC3_Msk                               /*!<Filter Scale Configuration bit 3 */
2659 #define CAN_FS1R_FSC4_Pos      (4U)
2660 #define CAN_FS1R_FSC4_Msk      (0x1UL << CAN_FS1R_FSC4_Pos)                     /*!< 0x00000010 */
2661 #define CAN_FS1R_FSC4          CAN_FS1R_FSC4_Msk                               /*!<Filter Scale Configuration bit 4 */
2662 #define CAN_FS1R_FSC5_Pos      (5U)
2663 #define CAN_FS1R_FSC5_Msk      (0x1UL << CAN_FS1R_FSC5_Pos)                     /*!< 0x00000020 */
2664 #define CAN_FS1R_FSC5          CAN_FS1R_FSC5_Msk                               /*!<Filter Scale Configuration bit 5 */
2665 #define CAN_FS1R_FSC6_Pos      (6U)
2666 #define CAN_FS1R_FSC6_Msk      (0x1UL << CAN_FS1R_FSC6_Pos)                     /*!< 0x00000040 */
2667 #define CAN_FS1R_FSC6          CAN_FS1R_FSC6_Msk                               /*!<Filter Scale Configuration bit 6 */
2668 #define CAN_FS1R_FSC7_Pos      (7U)
2669 #define CAN_FS1R_FSC7_Msk      (0x1UL << CAN_FS1R_FSC7_Pos)                     /*!< 0x00000080 */
2670 #define CAN_FS1R_FSC7          CAN_FS1R_FSC7_Msk                               /*!<Filter Scale Configuration bit 7 */
2671 #define CAN_FS1R_FSC8_Pos      (8U)
2672 #define CAN_FS1R_FSC8_Msk      (0x1UL << CAN_FS1R_FSC8_Pos)                     /*!< 0x00000100 */
2673 #define CAN_FS1R_FSC8          CAN_FS1R_FSC8_Msk                               /*!<Filter Scale Configuration bit 8 */
2674 #define CAN_FS1R_FSC9_Pos      (9U)
2675 #define CAN_FS1R_FSC9_Msk      (0x1UL << CAN_FS1R_FSC9_Pos)                     /*!< 0x00000200 */
2676 #define CAN_FS1R_FSC9          CAN_FS1R_FSC9_Msk                               /*!<Filter Scale Configuration bit 9 */
2677 #define CAN_FS1R_FSC10_Pos     (10U)
2678 #define CAN_FS1R_FSC10_Msk     (0x1UL << CAN_FS1R_FSC10_Pos)                    /*!< 0x00000400 */
2679 #define CAN_FS1R_FSC10         CAN_FS1R_FSC10_Msk                              /*!<Filter Scale Configuration bit 10 */
2680 #define CAN_FS1R_FSC11_Pos     (11U)
2681 #define CAN_FS1R_FSC11_Msk     (0x1UL << CAN_FS1R_FSC11_Pos)                    /*!< 0x00000800 */
2682 #define CAN_FS1R_FSC11         CAN_FS1R_FSC11_Msk                              /*!<Filter Scale Configuration bit 11 */
2683 #define CAN_FS1R_FSC12_Pos     (12U)
2684 #define CAN_FS1R_FSC12_Msk     (0x1UL << CAN_FS1R_FSC12_Pos)                    /*!< 0x00001000 */
2685 #define CAN_FS1R_FSC12         CAN_FS1R_FSC12_Msk                              /*!<Filter Scale Configuration bit 12 */
2686 #define CAN_FS1R_FSC13_Pos     (13U)
2687 #define CAN_FS1R_FSC13_Msk     (0x1UL << CAN_FS1R_FSC13_Pos)                    /*!< 0x00002000 */
2688 #define CAN_FS1R_FSC13         CAN_FS1R_FSC13_Msk                              /*!<Filter Scale Configuration bit 13 */
2689 #define CAN_FS1R_FSC14_Pos     (14U)
2690 #define CAN_FS1R_FSC14_Msk     (0x1UL << CAN_FS1R_FSC14_Pos)                    /*!< 0x00004000 */
2691 #define CAN_FS1R_FSC14         CAN_FS1R_FSC14_Msk                              /*!<Filter Scale Configuration bit 14 */
2692 #define CAN_FS1R_FSC15_Pos     (15U)
2693 #define CAN_FS1R_FSC15_Msk     (0x1UL << CAN_FS1R_FSC15_Pos)                    /*!< 0x00008000 */
2694 #define CAN_FS1R_FSC15         CAN_FS1R_FSC15_Msk                              /*!<Filter Scale Configuration bit 15 */
2695 #define CAN_FS1R_FSC16_Pos     (16U)
2696 #define CAN_FS1R_FSC16_Msk     (0x1UL << CAN_FS1R_FSC16_Pos)                    /*!< 0x00010000 */
2697 #define CAN_FS1R_FSC16         CAN_FS1R_FSC16_Msk                              /*!<Filter Scale Configuration bit 16 */
2698 #define CAN_FS1R_FSC17_Pos     (17U)
2699 #define CAN_FS1R_FSC17_Msk     (0x1UL << CAN_FS1R_FSC17_Pos)                    /*!< 0x00020000 */
2700 #define CAN_FS1R_FSC17         CAN_FS1R_FSC17_Msk                              /*!<Filter Scale Configuration bit 17 */
2701 #define CAN_FS1R_FSC18_Pos     (18U)
2702 #define CAN_FS1R_FSC18_Msk     (0x1UL << CAN_FS1R_FSC18_Pos)                    /*!< 0x00040000 */
2703 #define CAN_FS1R_FSC18         CAN_FS1R_FSC18_Msk                              /*!<Filter Scale Configuration bit 18 */
2704 #define CAN_FS1R_FSC19_Pos     (19U)
2705 #define CAN_FS1R_FSC19_Msk     (0x1UL << CAN_FS1R_FSC19_Pos)                    /*!< 0x00080000 */
2706 #define CAN_FS1R_FSC19         CAN_FS1R_FSC19_Msk                              /*!<Filter Scale Configuration bit 19 */
2707 #define CAN_FS1R_FSC20_Pos     (20U)
2708 #define CAN_FS1R_FSC20_Msk     (0x1UL << CAN_FS1R_FSC20_Pos)                    /*!< 0x00100000 */
2709 #define CAN_FS1R_FSC20         CAN_FS1R_FSC20_Msk                              /*!<Filter Scale Configuration bit 20 */
2710 #define CAN_FS1R_FSC21_Pos     (21U)
2711 #define CAN_FS1R_FSC21_Msk     (0x1UL << CAN_FS1R_FSC21_Pos)                    /*!< 0x00200000 */
2712 #define CAN_FS1R_FSC21         CAN_FS1R_FSC21_Msk                              /*!<Filter Scale Configuration bit 21 */
2713 #define CAN_FS1R_FSC22_Pos     (22U)
2714 #define CAN_FS1R_FSC22_Msk     (0x1UL << CAN_FS1R_FSC22_Pos)                    /*!< 0x00400000 */
2715 #define CAN_FS1R_FSC22         CAN_FS1R_FSC22_Msk                              /*!<Filter Scale Configuration bit 22 */
2716 #define CAN_FS1R_FSC23_Pos     (23U)
2717 #define CAN_FS1R_FSC23_Msk     (0x1UL << CAN_FS1R_FSC23_Pos)                    /*!< 0x00800000 */
2718 #define CAN_FS1R_FSC23         CAN_FS1R_FSC23_Msk                              /*!<Filter Scale Configuration bit 23 */
2719 #define CAN_FS1R_FSC24_Pos     (24U)
2720 #define CAN_FS1R_FSC24_Msk     (0x1UL << CAN_FS1R_FSC24_Pos)                    /*!< 0x01000000 */
2721 #define CAN_FS1R_FSC24         CAN_FS1R_FSC24_Msk                              /*!<Filter Scale Configuration bit 24 */
2722 #define CAN_FS1R_FSC25_Pos     (25U)
2723 #define CAN_FS1R_FSC25_Msk     (0x1UL << CAN_FS1R_FSC25_Pos)                    /*!< 0x02000000 */
2724 #define CAN_FS1R_FSC25         CAN_FS1R_FSC25_Msk                              /*!<Filter Scale Configuration bit 25 */
2725 #define CAN_FS1R_FSC26_Pos     (26U)
2726 #define CAN_FS1R_FSC26_Msk     (0x1UL << CAN_FS1R_FSC26_Pos)                    /*!< 0x04000000 */
2727 #define CAN_FS1R_FSC26         CAN_FS1R_FSC26_Msk                              /*!<Filter Scale Configuration bit 26 */
2728 #define CAN_FS1R_FSC27_Pos     (27U)
2729 #define CAN_FS1R_FSC27_Msk     (0x1UL << CAN_FS1R_FSC27_Pos)                    /*!< 0x08000000 */
2730 #define CAN_FS1R_FSC27         CAN_FS1R_FSC27_Msk                              /*!<Filter Scale Configuration bit 27 */
2731 
2732 /******************  Bit definition for CAN_FFA1R register  *******************/
2733 #define CAN_FFA1R_FFA_Pos      (0U)
2734 #define CAN_FFA1R_FFA_Msk      (0xFFFFFFFUL << CAN_FFA1R_FFA_Pos)               /*!< 0x0FFFFFFF */
2735 #define CAN_FFA1R_FFA          CAN_FFA1R_FFA_Msk                               /*!<Filter FIFO Assignment */
2736 #define CAN_FFA1R_FFA0_Pos     (0U)
2737 #define CAN_FFA1R_FFA0_Msk     (0x1UL << CAN_FFA1R_FFA0_Pos)                    /*!< 0x00000001 */
2738 #define CAN_FFA1R_FFA0         CAN_FFA1R_FFA0_Msk                              /*!<Filter FIFO Assignment bit 0 */
2739 #define CAN_FFA1R_FFA1_Pos     (1U)
2740 #define CAN_FFA1R_FFA1_Msk     (0x1UL << CAN_FFA1R_FFA1_Pos)                    /*!< 0x00000002 */
2741 #define CAN_FFA1R_FFA1         CAN_FFA1R_FFA1_Msk                              /*!<Filter FIFO Assignment bit 1 */
2742 #define CAN_FFA1R_FFA2_Pos     (2U)
2743 #define CAN_FFA1R_FFA2_Msk     (0x1UL << CAN_FFA1R_FFA2_Pos)                    /*!< 0x00000004 */
2744 #define CAN_FFA1R_FFA2         CAN_FFA1R_FFA2_Msk                              /*!<Filter FIFO Assignment bit 2 */
2745 #define CAN_FFA1R_FFA3_Pos     (3U)
2746 #define CAN_FFA1R_FFA3_Msk     (0x1UL << CAN_FFA1R_FFA3_Pos)                    /*!< 0x00000008 */
2747 #define CAN_FFA1R_FFA3         CAN_FFA1R_FFA3_Msk                              /*!<Filter FIFO Assignment bit 3 */
2748 #define CAN_FFA1R_FFA4_Pos     (4U)
2749 #define CAN_FFA1R_FFA4_Msk     (0x1UL << CAN_FFA1R_FFA4_Pos)                    /*!< 0x00000010 */
2750 #define CAN_FFA1R_FFA4         CAN_FFA1R_FFA4_Msk                              /*!<Filter FIFO Assignment bit 4 */
2751 #define CAN_FFA1R_FFA5_Pos     (5U)
2752 #define CAN_FFA1R_FFA5_Msk     (0x1UL << CAN_FFA1R_FFA5_Pos)                    /*!< 0x00000020 */
2753 #define CAN_FFA1R_FFA5         CAN_FFA1R_FFA5_Msk                              /*!<Filter FIFO Assignment bit 5 */
2754 #define CAN_FFA1R_FFA6_Pos     (6U)
2755 #define CAN_FFA1R_FFA6_Msk     (0x1UL << CAN_FFA1R_FFA6_Pos)                    /*!< 0x00000040 */
2756 #define CAN_FFA1R_FFA6         CAN_FFA1R_FFA6_Msk                              /*!<Filter FIFO Assignment bit 6 */
2757 #define CAN_FFA1R_FFA7_Pos     (7U)
2758 #define CAN_FFA1R_FFA7_Msk     (0x1UL << CAN_FFA1R_FFA7_Pos)                    /*!< 0x00000080 */
2759 #define CAN_FFA1R_FFA7         CAN_FFA1R_FFA7_Msk                              /*!<Filter FIFO Assignment bit 7 */
2760 #define CAN_FFA1R_FFA8_Pos     (8U)
2761 #define CAN_FFA1R_FFA8_Msk     (0x1UL << CAN_FFA1R_FFA8_Pos)                    /*!< 0x00000100 */
2762 #define CAN_FFA1R_FFA8         CAN_FFA1R_FFA8_Msk                              /*!<Filter FIFO Assignment bit 8 */
2763 #define CAN_FFA1R_FFA9_Pos     (9U)
2764 #define CAN_FFA1R_FFA9_Msk     (0x1UL << CAN_FFA1R_FFA9_Pos)                    /*!< 0x00000200 */
2765 #define CAN_FFA1R_FFA9         CAN_FFA1R_FFA9_Msk                              /*!<Filter FIFO Assignment bit 9 */
2766 #define CAN_FFA1R_FFA10_Pos    (10U)
2767 #define CAN_FFA1R_FFA10_Msk    (0x1UL << CAN_FFA1R_FFA10_Pos)                   /*!< 0x00000400 */
2768 #define CAN_FFA1R_FFA10        CAN_FFA1R_FFA10_Msk                             /*!<Filter FIFO Assignment bit 10 */
2769 #define CAN_FFA1R_FFA11_Pos    (11U)
2770 #define CAN_FFA1R_FFA11_Msk    (0x1UL << CAN_FFA1R_FFA11_Pos)                   /*!< 0x00000800 */
2771 #define CAN_FFA1R_FFA11        CAN_FFA1R_FFA11_Msk                             /*!<Filter FIFO Assignment bit 11 */
2772 #define CAN_FFA1R_FFA12_Pos    (12U)
2773 #define CAN_FFA1R_FFA12_Msk    (0x1UL << CAN_FFA1R_FFA12_Pos)                   /*!< 0x00001000 */
2774 #define CAN_FFA1R_FFA12        CAN_FFA1R_FFA12_Msk                             /*!<Filter FIFO Assignment bit 12 */
2775 #define CAN_FFA1R_FFA13_Pos    (13U)
2776 #define CAN_FFA1R_FFA13_Msk    (0x1UL << CAN_FFA1R_FFA13_Pos)                   /*!< 0x00002000 */
2777 #define CAN_FFA1R_FFA13        CAN_FFA1R_FFA13_Msk                             /*!<Filter FIFO Assignment bit 13 */
2778 #define CAN_FFA1R_FFA14_Pos    (14U)
2779 #define CAN_FFA1R_FFA14_Msk    (0x1UL << CAN_FFA1R_FFA14_Pos)                   /*!< 0x00004000 */
2780 #define CAN_FFA1R_FFA14        CAN_FFA1R_FFA14_Msk                             /*!<Filter FIFO Assignment bit 14 */
2781 #define CAN_FFA1R_FFA15_Pos    (15U)
2782 #define CAN_FFA1R_FFA15_Msk    (0x1UL << CAN_FFA1R_FFA15_Pos)                   /*!< 0x00008000 */
2783 #define CAN_FFA1R_FFA15        CAN_FFA1R_FFA15_Msk                             /*!<Filter FIFO Assignment bit 15 */
2784 #define CAN_FFA1R_FFA16_Pos    (16U)
2785 #define CAN_FFA1R_FFA16_Msk    (0x1UL << CAN_FFA1R_FFA16_Pos)                   /*!< 0x00010000 */
2786 #define CAN_FFA1R_FFA16        CAN_FFA1R_FFA16_Msk                             /*!<Filter FIFO Assignment bit 16 */
2787 #define CAN_FFA1R_FFA17_Pos    (17U)
2788 #define CAN_FFA1R_FFA17_Msk    (0x1UL << CAN_FFA1R_FFA17_Pos)                   /*!< 0x00020000 */
2789 #define CAN_FFA1R_FFA17        CAN_FFA1R_FFA17_Msk                             /*!<Filter FIFO Assignment bit 17 */
2790 #define CAN_FFA1R_FFA18_Pos    (18U)
2791 #define CAN_FFA1R_FFA18_Msk    (0x1UL << CAN_FFA1R_FFA18_Pos)                   /*!< 0x00040000 */
2792 #define CAN_FFA1R_FFA18        CAN_FFA1R_FFA18_Msk                             /*!<Filter FIFO Assignment bit 18 */
2793 #define CAN_FFA1R_FFA19_Pos    (19U)
2794 #define CAN_FFA1R_FFA19_Msk    (0x1UL << CAN_FFA1R_FFA19_Pos)                   /*!< 0x00080000 */
2795 #define CAN_FFA1R_FFA19        CAN_FFA1R_FFA19_Msk                             /*!<Filter FIFO Assignment bit 19 */
2796 #define CAN_FFA1R_FFA20_Pos    (20U)
2797 #define CAN_FFA1R_FFA20_Msk    (0x1UL << CAN_FFA1R_FFA20_Pos)                   /*!< 0x00100000 */
2798 #define CAN_FFA1R_FFA20        CAN_FFA1R_FFA20_Msk                             /*!<Filter FIFO Assignment bit 20 */
2799 #define CAN_FFA1R_FFA21_Pos    (21U)
2800 #define CAN_FFA1R_FFA21_Msk    (0x1UL << CAN_FFA1R_FFA21_Pos)                   /*!< 0x00200000 */
2801 #define CAN_FFA1R_FFA21        CAN_FFA1R_FFA21_Msk                             /*!<Filter FIFO Assignment bit 21 */
2802 #define CAN_FFA1R_FFA22_Pos    (22U)
2803 #define CAN_FFA1R_FFA22_Msk    (0x1UL << CAN_FFA1R_FFA22_Pos)                   /*!< 0x00400000 */
2804 #define CAN_FFA1R_FFA22        CAN_FFA1R_FFA22_Msk                             /*!<Filter FIFO Assignment bit 22 */
2805 #define CAN_FFA1R_FFA23_Pos    (23U)
2806 #define CAN_FFA1R_FFA23_Msk    (0x1UL << CAN_FFA1R_FFA23_Pos)                   /*!< 0x00800000 */
2807 #define CAN_FFA1R_FFA23        CAN_FFA1R_FFA23_Msk                             /*!<Filter FIFO Assignment bit 23 */
2808 #define CAN_FFA1R_FFA24_Pos    (24U)
2809 #define CAN_FFA1R_FFA24_Msk    (0x1UL << CAN_FFA1R_FFA24_Pos)                   /*!< 0x01000000 */
2810 #define CAN_FFA1R_FFA24        CAN_FFA1R_FFA24_Msk                             /*!<Filter FIFO Assignment bit 24 */
2811 #define CAN_FFA1R_FFA25_Pos    (25U)
2812 #define CAN_FFA1R_FFA25_Msk    (0x1UL << CAN_FFA1R_FFA25_Pos)                   /*!< 0x02000000 */
2813 #define CAN_FFA1R_FFA25        CAN_FFA1R_FFA25_Msk                             /*!<Filter FIFO Assignment bit 25 */
2814 #define CAN_FFA1R_FFA26_Pos    (26U)
2815 #define CAN_FFA1R_FFA26_Msk    (0x1UL << CAN_FFA1R_FFA26_Pos)                   /*!< 0x04000000 */
2816 #define CAN_FFA1R_FFA26        CAN_FFA1R_FFA26_Msk                             /*!<Filter FIFO Assignment bit 26 */
2817 #define CAN_FFA1R_FFA27_Pos    (27U)
2818 #define CAN_FFA1R_FFA27_Msk    (0x1UL << CAN_FFA1R_FFA27_Pos)                   /*!< 0x08000000 */
2819 #define CAN_FFA1R_FFA27        CAN_FFA1R_FFA27_Msk                             /*!<Filter FIFO Assignment bit 27 */
2820 
2821 /*******************  Bit definition for CAN_FA1R register  *******************/
2822 #define CAN_FA1R_FACT_Pos      (0U)
2823 #define CAN_FA1R_FACT_Msk      (0xFFFFFFFUL << CAN_FA1R_FACT_Pos)               /*!< 0x0FFFFFFF */
2824 #define CAN_FA1R_FACT          CAN_FA1R_FACT_Msk                               /*!<Filter Active */
2825 #define CAN_FA1R_FACT0_Pos     (0U)
2826 #define CAN_FA1R_FACT0_Msk     (0x1UL << CAN_FA1R_FACT0_Pos)                    /*!< 0x00000001 */
2827 #define CAN_FA1R_FACT0         CAN_FA1R_FACT0_Msk                              /*!<Filter Active bit 0 */
2828 #define CAN_FA1R_FACT1_Pos     (1U)
2829 #define CAN_FA1R_FACT1_Msk     (0x1UL << CAN_FA1R_FACT1_Pos)                    /*!< 0x00000002 */
2830 #define CAN_FA1R_FACT1         CAN_FA1R_FACT1_Msk                              /*!<Filter Active bit 1 */
2831 #define CAN_FA1R_FACT2_Pos     (2U)
2832 #define CAN_FA1R_FACT2_Msk     (0x1UL << CAN_FA1R_FACT2_Pos)                    /*!< 0x00000004 */
2833 #define CAN_FA1R_FACT2         CAN_FA1R_FACT2_Msk                              /*!<Filter Active bit 2 */
2834 #define CAN_FA1R_FACT3_Pos     (3U)
2835 #define CAN_FA1R_FACT3_Msk     (0x1UL << CAN_FA1R_FACT3_Pos)                    /*!< 0x00000008 */
2836 #define CAN_FA1R_FACT3         CAN_FA1R_FACT3_Msk                              /*!<Filter Active bit 3 */
2837 #define CAN_FA1R_FACT4_Pos     (4U)
2838 #define CAN_FA1R_FACT4_Msk     (0x1UL << CAN_FA1R_FACT4_Pos)                    /*!< 0x00000010 */
2839 #define CAN_FA1R_FACT4         CAN_FA1R_FACT4_Msk                              /*!<Filter Active bit 4 */
2840 #define CAN_FA1R_FACT5_Pos     (5U)
2841 #define CAN_FA1R_FACT5_Msk     (0x1UL << CAN_FA1R_FACT5_Pos)                    /*!< 0x00000020 */
2842 #define CAN_FA1R_FACT5         CAN_FA1R_FACT5_Msk                              /*!<Filter Active bit 5 */
2843 #define CAN_FA1R_FACT6_Pos     (6U)
2844 #define CAN_FA1R_FACT6_Msk     (0x1UL << CAN_FA1R_FACT6_Pos)                    /*!< 0x00000040 */
2845 #define CAN_FA1R_FACT6         CAN_FA1R_FACT6_Msk                              /*!<Filter Active bit 6 */
2846 #define CAN_FA1R_FACT7_Pos     (7U)
2847 #define CAN_FA1R_FACT7_Msk     (0x1UL << CAN_FA1R_FACT7_Pos)                    /*!< 0x00000080 */
2848 #define CAN_FA1R_FACT7         CAN_FA1R_FACT7_Msk                              /*!<Filter Active bit 7 */
2849 #define CAN_FA1R_FACT8_Pos     (8U)
2850 #define CAN_FA1R_FACT8_Msk     (0x1UL << CAN_FA1R_FACT8_Pos)                    /*!< 0x00000100 */
2851 #define CAN_FA1R_FACT8         CAN_FA1R_FACT8_Msk                              /*!<Filter Active bit 8 */
2852 #define CAN_FA1R_FACT9_Pos     (9U)
2853 #define CAN_FA1R_FACT9_Msk     (0x1UL << CAN_FA1R_FACT9_Pos)                    /*!< 0x00000200 */
2854 #define CAN_FA1R_FACT9         CAN_FA1R_FACT9_Msk                              /*!<Filter Active bit 9 */
2855 #define CAN_FA1R_FACT10_Pos    (10U)
2856 #define CAN_FA1R_FACT10_Msk    (0x1UL << CAN_FA1R_FACT10_Pos)                   /*!< 0x00000400 */
2857 #define CAN_FA1R_FACT10        CAN_FA1R_FACT10_Msk                             /*!<Filter Active bit 10 */
2858 #define CAN_FA1R_FACT11_Pos    (11U)
2859 #define CAN_FA1R_FACT11_Msk    (0x1UL << CAN_FA1R_FACT11_Pos)                   /*!< 0x00000800 */
2860 #define CAN_FA1R_FACT11        CAN_FA1R_FACT11_Msk                             /*!<Filter Active bit 11 */
2861 #define CAN_FA1R_FACT12_Pos    (12U)
2862 #define CAN_FA1R_FACT12_Msk    (0x1UL << CAN_FA1R_FACT12_Pos)                   /*!< 0x00001000 */
2863 #define CAN_FA1R_FACT12        CAN_FA1R_FACT12_Msk                             /*!<Filter Active bit 12 */
2864 #define CAN_FA1R_FACT13_Pos    (13U)
2865 #define CAN_FA1R_FACT13_Msk    (0x1UL << CAN_FA1R_FACT13_Pos)                   /*!< 0x00002000 */
2866 #define CAN_FA1R_FACT13        CAN_FA1R_FACT13_Msk                             /*!<Filter Active bit 13 */
2867 #define CAN_FA1R_FACT14_Pos    (14U)
2868 #define CAN_FA1R_FACT14_Msk    (0x1UL << CAN_FA1R_FACT14_Pos)                   /*!< 0x00004000 */
2869 #define CAN_FA1R_FACT14        CAN_FA1R_FACT14_Msk                             /*!<Filter Active bit 14 */
2870 #define CAN_FA1R_FACT15_Pos    (15U)
2871 #define CAN_FA1R_FACT15_Msk    (0x1UL << CAN_FA1R_FACT15_Pos)                   /*!< 0x00008000 */
2872 #define CAN_FA1R_FACT15        CAN_FA1R_FACT15_Msk                             /*!<Filter Active bit 15 */
2873 #define CAN_FA1R_FACT16_Pos    (16U)
2874 #define CAN_FA1R_FACT16_Msk    (0x1UL << CAN_FA1R_FACT16_Pos)                   /*!< 0x00010000 */
2875 #define CAN_FA1R_FACT16        CAN_FA1R_FACT16_Msk                             /*!<Filter Active bit 16 */
2876 #define CAN_FA1R_FACT17_Pos    (17U)
2877 #define CAN_FA1R_FACT17_Msk    (0x1UL << CAN_FA1R_FACT17_Pos)                   /*!< 0x00020000 */
2878 #define CAN_FA1R_FACT17        CAN_FA1R_FACT17_Msk                             /*!<Filter Active bit 17 */
2879 #define CAN_FA1R_FACT18_Pos    (18U)
2880 #define CAN_FA1R_FACT18_Msk    (0x1UL << CAN_FA1R_FACT18_Pos)                   /*!< 0x00040000 */
2881 #define CAN_FA1R_FACT18        CAN_FA1R_FACT18_Msk                             /*!<Filter Active bit 18 */
2882 #define CAN_FA1R_FACT19_Pos    (19U)
2883 #define CAN_FA1R_FACT19_Msk    (0x1UL << CAN_FA1R_FACT19_Pos)                   /*!< 0x00080000 */
2884 #define CAN_FA1R_FACT19        CAN_FA1R_FACT19_Msk                             /*!<Filter Active bit 19 */
2885 #define CAN_FA1R_FACT20_Pos    (20U)
2886 #define CAN_FA1R_FACT20_Msk    (0x1UL << CAN_FA1R_FACT20_Pos)                   /*!< 0x00100000 */
2887 #define CAN_FA1R_FACT20        CAN_FA1R_FACT20_Msk                             /*!<Filter Active bit 20 */
2888 #define CAN_FA1R_FACT21_Pos    (21U)
2889 #define CAN_FA1R_FACT21_Msk    (0x1UL << CAN_FA1R_FACT21_Pos)                   /*!< 0x00200000 */
2890 #define CAN_FA1R_FACT21        CAN_FA1R_FACT21_Msk                             /*!<Filter Active bit 21 */
2891 #define CAN_FA1R_FACT22_Pos    (22U)
2892 #define CAN_FA1R_FACT22_Msk    (0x1UL << CAN_FA1R_FACT22_Pos)                   /*!< 0x00400000 */
2893 #define CAN_FA1R_FACT22        CAN_FA1R_FACT22_Msk                             /*!<Filter Active bit 22 */
2894 #define CAN_FA1R_FACT23_Pos    (23U)
2895 #define CAN_FA1R_FACT23_Msk    (0x1UL << CAN_FA1R_FACT23_Pos)                   /*!< 0x00800000 */
2896 #define CAN_FA1R_FACT23        CAN_FA1R_FACT23_Msk                             /*!<Filter Active bit 23 */
2897 #define CAN_FA1R_FACT24_Pos    (24U)
2898 #define CAN_FA1R_FACT24_Msk    (0x1UL << CAN_FA1R_FACT24_Pos)                   /*!< 0x01000000 */
2899 #define CAN_FA1R_FACT24        CAN_FA1R_FACT24_Msk                             /*!<Filter Active bit 24 */
2900 #define CAN_FA1R_FACT25_Pos    (25U)
2901 #define CAN_FA1R_FACT25_Msk    (0x1UL << CAN_FA1R_FACT25_Pos)                   /*!< 0x02000000 */
2902 #define CAN_FA1R_FACT25        CAN_FA1R_FACT25_Msk                             /*!<Filter Active bit 25 */
2903 #define CAN_FA1R_FACT26_Pos    (26U)
2904 #define CAN_FA1R_FACT26_Msk    (0x1UL << CAN_FA1R_FACT26_Pos)                   /*!< 0x04000000 */
2905 #define CAN_FA1R_FACT26        CAN_FA1R_FACT26_Msk                             /*!<Filter Active bit 26 */
2906 #define CAN_FA1R_FACT27_Pos    (27U)
2907 #define CAN_FA1R_FACT27_Msk    (0x1UL << CAN_FA1R_FACT27_Pos)                   /*!< 0x08000000 */
2908 #define CAN_FA1R_FACT27        CAN_FA1R_FACT27_Msk                             /*!<Filter Active bit 27 */
2909 
2910 
2911 /*******************  Bit definition for CAN_F0R1 register  *******************/
2912 #define CAN_F0R1_FB0_Pos       (0U)
2913 #define CAN_F0R1_FB0_Msk       (0x1UL << CAN_F0R1_FB0_Pos)                      /*!< 0x00000001 */
2914 #define CAN_F0R1_FB0           CAN_F0R1_FB0_Msk                                /*!<Filter bit 0 */
2915 #define CAN_F0R1_FB1_Pos       (1U)
2916 #define CAN_F0R1_FB1_Msk       (0x1UL << CAN_F0R1_FB1_Pos)                      /*!< 0x00000002 */
2917 #define CAN_F0R1_FB1           CAN_F0R1_FB1_Msk                                /*!<Filter bit 1 */
2918 #define CAN_F0R1_FB2_Pos       (2U)
2919 #define CAN_F0R1_FB2_Msk       (0x1UL << CAN_F0R1_FB2_Pos)                      /*!< 0x00000004 */
2920 #define CAN_F0R1_FB2           CAN_F0R1_FB2_Msk                                /*!<Filter bit 2 */
2921 #define CAN_F0R1_FB3_Pos       (3U)
2922 #define CAN_F0R1_FB3_Msk       (0x1UL << CAN_F0R1_FB3_Pos)                      /*!< 0x00000008 */
2923 #define CAN_F0R1_FB3           CAN_F0R1_FB3_Msk                                /*!<Filter bit 3 */
2924 #define CAN_F0R1_FB4_Pos       (4U)
2925 #define CAN_F0R1_FB4_Msk       (0x1UL << CAN_F0R1_FB4_Pos)                      /*!< 0x00000010 */
2926 #define CAN_F0R1_FB4           CAN_F0R1_FB4_Msk                                /*!<Filter bit 4 */
2927 #define CAN_F0R1_FB5_Pos       (5U)
2928 #define CAN_F0R1_FB5_Msk       (0x1UL << CAN_F0R1_FB5_Pos)                      /*!< 0x00000020 */
2929 #define CAN_F0R1_FB5           CAN_F0R1_FB5_Msk                                /*!<Filter bit 5 */
2930 #define CAN_F0R1_FB6_Pos       (6U)
2931 #define CAN_F0R1_FB6_Msk       (0x1UL << CAN_F0R1_FB6_Pos)                      /*!< 0x00000040 */
2932 #define CAN_F0R1_FB6           CAN_F0R1_FB6_Msk                                /*!<Filter bit 6 */
2933 #define CAN_F0R1_FB7_Pos       (7U)
2934 #define CAN_F0R1_FB7_Msk       (0x1UL << CAN_F0R1_FB7_Pos)                      /*!< 0x00000080 */
2935 #define CAN_F0R1_FB7           CAN_F0R1_FB7_Msk                                /*!<Filter bit 7 */
2936 #define CAN_F0R1_FB8_Pos       (8U)
2937 #define CAN_F0R1_FB8_Msk       (0x1UL << CAN_F0R1_FB8_Pos)                      /*!< 0x00000100 */
2938 #define CAN_F0R1_FB8           CAN_F0R1_FB8_Msk                                /*!<Filter bit 8 */
2939 #define CAN_F0R1_FB9_Pos       (9U)
2940 #define CAN_F0R1_FB9_Msk       (0x1UL << CAN_F0R1_FB9_Pos)                      /*!< 0x00000200 */
2941 #define CAN_F0R1_FB9           CAN_F0R1_FB9_Msk                                /*!<Filter bit 9 */
2942 #define CAN_F0R1_FB10_Pos      (10U)
2943 #define CAN_F0R1_FB10_Msk      (0x1UL << CAN_F0R1_FB10_Pos)                     /*!< 0x00000400 */
2944 #define CAN_F0R1_FB10          CAN_F0R1_FB10_Msk                               /*!<Filter bit 10 */
2945 #define CAN_F0R1_FB11_Pos      (11U)
2946 #define CAN_F0R1_FB11_Msk      (0x1UL << CAN_F0R1_FB11_Pos)                     /*!< 0x00000800 */
2947 #define CAN_F0R1_FB11          CAN_F0R1_FB11_Msk                               /*!<Filter bit 11 */
2948 #define CAN_F0R1_FB12_Pos      (12U)
2949 #define CAN_F0R1_FB12_Msk      (0x1UL << CAN_F0R1_FB12_Pos)                     /*!< 0x00001000 */
2950 #define CAN_F0R1_FB12          CAN_F0R1_FB12_Msk                               /*!<Filter bit 12 */
2951 #define CAN_F0R1_FB13_Pos      (13U)
2952 #define CAN_F0R1_FB13_Msk      (0x1UL << CAN_F0R1_FB13_Pos)                     /*!< 0x00002000 */
2953 #define CAN_F0R1_FB13          CAN_F0R1_FB13_Msk                               /*!<Filter bit 13 */
2954 #define CAN_F0R1_FB14_Pos      (14U)
2955 #define CAN_F0R1_FB14_Msk      (0x1UL << CAN_F0R1_FB14_Pos)                     /*!< 0x00004000 */
2956 #define CAN_F0R1_FB14          CAN_F0R1_FB14_Msk                               /*!<Filter bit 14 */
2957 #define CAN_F0R1_FB15_Pos      (15U)
2958 #define CAN_F0R1_FB15_Msk      (0x1UL << CAN_F0R1_FB15_Pos)                     /*!< 0x00008000 */
2959 #define CAN_F0R1_FB15          CAN_F0R1_FB15_Msk                               /*!<Filter bit 15 */
2960 #define CAN_F0R1_FB16_Pos      (16U)
2961 #define CAN_F0R1_FB16_Msk      (0x1UL << CAN_F0R1_FB16_Pos)                     /*!< 0x00010000 */
2962 #define CAN_F0R1_FB16          CAN_F0R1_FB16_Msk                               /*!<Filter bit 16 */
2963 #define CAN_F0R1_FB17_Pos      (17U)
2964 #define CAN_F0R1_FB17_Msk      (0x1UL << CAN_F0R1_FB17_Pos)                     /*!< 0x00020000 */
2965 #define CAN_F0R1_FB17          CAN_F0R1_FB17_Msk                               /*!<Filter bit 17 */
2966 #define CAN_F0R1_FB18_Pos      (18U)
2967 #define CAN_F0R1_FB18_Msk      (0x1UL << CAN_F0R1_FB18_Pos)                     /*!< 0x00040000 */
2968 #define CAN_F0R1_FB18          CAN_F0R1_FB18_Msk                               /*!<Filter bit 18 */
2969 #define CAN_F0R1_FB19_Pos      (19U)
2970 #define CAN_F0R1_FB19_Msk      (0x1UL << CAN_F0R1_FB19_Pos)                     /*!< 0x00080000 */
2971 #define CAN_F0R1_FB19          CAN_F0R1_FB19_Msk                               /*!<Filter bit 19 */
2972 #define CAN_F0R1_FB20_Pos      (20U)
2973 #define CAN_F0R1_FB20_Msk      (0x1UL << CAN_F0R1_FB20_Pos)                     /*!< 0x00100000 */
2974 #define CAN_F0R1_FB20          CAN_F0R1_FB20_Msk                               /*!<Filter bit 20 */
2975 #define CAN_F0R1_FB21_Pos      (21U)
2976 #define CAN_F0R1_FB21_Msk      (0x1UL << CAN_F0R1_FB21_Pos)                     /*!< 0x00200000 */
2977 #define CAN_F0R1_FB21          CAN_F0R1_FB21_Msk                               /*!<Filter bit 21 */
2978 #define CAN_F0R1_FB22_Pos      (22U)
2979 #define CAN_F0R1_FB22_Msk      (0x1UL << CAN_F0R1_FB22_Pos)                     /*!< 0x00400000 */
2980 #define CAN_F0R1_FB22          CAN_F0R1_FB22_Msk                               /*!<Filter bit 22 */
2981 #define CAN_F0R1_FB23_Pos      (23U)
2982 #define CAN_F0R1_FB23_Msk      (0x1UL << CAN_F0R1_FB23_Pos)                     /*!< 0x00800000 */
2983 #define CAN_F0R1_FB23          CAN_F0R1_FB23_Msk                               /*!<Filter bit 23 */
2984 #define CAN_F0R1_FB24_Pos      (24U)
2985 #define CAN_F0R1_FB24_Msk      (0x1UL << CAN_F0R1_FB24_Pos)                     /*!< 0x01000000 */
2986 #define CAN_F0R1_FB24          CAN_F0R1_FB24_Msk                               /*!<Filter bit 24 */
2987 #define CAN_F0R1_FB25_Pos      (25U)
2988 #define CAN_F0R1_FB25_Msk      (0x1UL << CAN_F0R1_FB25_Pos)                     /*!< 0x02000000 */
2989 #define CAN_F0R1_FB25          CAN_F0R1_FB25_Msk                               /*!<Filter bit 25 */
2990 #define CAN_F0R1_FB26_Pos      (26U)
2991 #define CAN_F0R1_FB26_Msk      (0x1UL << CAN_F0R1_FB26_Pos)                     /*!< 0x04000000 */
2992 #define CAN_F0R1_FB26          CAN_F0R1_FB26_Msk                               /*!<Filter bit 26 */
2993 #define CAN_F0R1_FB27_Pos      (27U)
2994 #define CAN_F0R1_FB27_Msk      (0x1UL << CAN_F0R1_FB27_Pos)                     /*!< 0x08000000 */
2995 #define CAN_F0R1_FB27          CAN_F0R1_FB27_Msk                               /*!<Filter bit 27 */
2996 #define CAN_F0R1_FB28_Pos      (28U)
2997 #define CAN_F0R1_FB28_Msk      (0x1UL << CAN_F0R1_FB28_Pos)                     /*!< 0x10000000 */
2998 #define CAN_F0R1_FB28          CAN_F0R1_FB28_Msk                               /*!<Filter bit 28 */
2999 #define CAN_F0R1_FB29_Pos      (29U)
3000 #define CAN_F0R1_FB29_Msk      (0x1UL << CAN_F0R1_FB29_Pos)                     /*!< 0x20000000 */
3001 #define CAN_F0R1_FB29          CAN_F0R1_FB29_Msk                               /*!<Filter bit 29 */
3002 #define CAN_F0R1_FB30_Pos      (30U)
3003 #define CAN_F0R1_FB30_Msk      (0x1UL << CAN_F0R1_FB30_Pos)                     /*!< 0x40000000 */
3004 #define CAN_F0R1_FB30          CAN_F0R1_FB30_Msk                               /*!<Filter bit 30 */
3005 #define CAN_F0R1_FB31_Pos      (31U)
3006 #define CAN_F0R1_FB31_Msk      (0x1UL << CAN_F0R1_FB31_Pos)                     /*!< 0x80000000 */
3007 #define CAN_F0R1_FB31          CAN_F0R1_FB31_Msk                               /*!<Filter bit 31 */
3008 
3009 /*******************  Bit definition for CAN_F1R1 register  *******************/
3010 #define CAN_F1R1_FB0_Pos       (0U)
3011 #define CAN_F1R1_FB0_Msk       (0x1UL << CAN_F1R1_FB0_Pos)                      /*!< 0x00000001 */
3012 #define CAN_F1R1_FB0           CAN_F1R1_FB0_Msk                                /*!<Filter bit 0 */
3013 #define CAN_F1R1_FB1_Pos       (1U)
3014 #define CAN_F1R1_FB1_Msk       (0x1UL << CAN_F1R1_FB1_Pos)                      /*!< 0x00000002 */
3015 #define CAN_F1R1_FB1           CAN_F1R1_FB1_Msk                                /*!<Filter bit 1 */
3016 #define CAN_F1R1_FB2_Pos       (2U)
3017 #define CAN_F1R1_FB2_Msk       (0x1UL << CAN_F1R1_FB2_Pos)                      /*!< 0x00000004 */
3018 #define CAN_F1R1_FB2           CAN_F1R1_FB2_Msk                                /*!<Filter bit 2 */
3019 #define CAN_F1R1_FB3_Pos       (3U)
3020 #define CAN_F1R1_FB3_Msk       (0x1UL << CAN_F1R1_FB3_Pos)                      /*!< 0x00000008 */
3021 #define CAN_F1R1_FB3           CAN_F1R1_FB3_Msk                                /*!<Filter bit 3 */
3022 #define CAN_F1R1_FB4_Pos       (4U)
3023 #define CAN_F1R1_FB4_Msk       (0x1UL << CAN_F1R1_FB4_Pos)                      /*!< 0x00000010 */
3024 #define CAN_F1R1_FB4           CAN_F1R1_FB4_Msk                                /*!<Filter bit 4 */
3025 #define CAN_F1R1_FB5_Pos       (5U)
3026 #define CAN_F1R1_FB5_Msk       (0x1UL << CAN_F1R1_FB5_Pos)                      /*!< 0x00000020 */
3027 #define CAN_F1R1_FB5           CAN_F1R1_FB5_Msk                                /*!<Filter bit 5 */
3028 #define CAN_F1R1_FB6_Pos       (6U)
3029 #define CAN_F1R1_FB6_Msk       (0x1UL << CAN_F1R1_FB6_Pos)                      /*!< 0x00000040 */
3030 #define CAN_F1R1_FB6           CAN_F1R1_FB6_Msk                                /*!<Filter bit 6 */
3031 #define CAN_F1R1_FB7_Pos       (7U)
3032 #define CAN_F1R1_FB7_Msk       (0x1UL << CAN_F1R1_FB7_Pos)                      /*!< 0x00000080 */
3033 #define CAN_F1R1_FB7           CAN_F1R1_FB7_Msk                                /*!<Filter bit 7 */
3034 #define CAN_F1R1_FB8_Pos       (8U)
3035 #define CAN_F1R1_FB8_Msk       (0x1UL << CAN_F1R1_FB8_Pos)                      /*!< 0x00000100 */
3036 #define CAN_F1R1_FB8           CAN_F1R1_FB8_Msk                                /*!<Filter bit 8 */
3037 #define CAN_F1R1_FB9_Pos       (9U)
3038 #define CAN_F1R1_FB9_Msk       (0x1UL << CAN_F1R1_FB9_Pos)                      /*!< 0x00000200 */
3039 #define CAN_F1R1_FB9           CAN_F1R1_FB9_Msk                                /*!<Filter bit 9 */
3040 #define CAN_F1R1_FB10_Pos      (10U)
3041 #define CAN_F1R1_FB10_Msk      (0x1UL << CAN_F1R1_FB10_Pos)                     /*!< 0x00000400 */
3042 #define CAN_F1R1_FB10          CAN_F1R1_FB10_Msk                               /*!<Filter bit 10 */
3043 #define CAN_F1R1_FB11_Pos      (11U)
3044 #define CAN_F1R1_FB11_Msk      (0x1UL << CAN_F1R1_FB11_Pos)                     /*!< 0x00000800 */
3045 #define CAN_F1R1_FB11          CAN_F1R1_FB11_Msk                               /*!<Filter bit 11 */
3046 #define CAN_F1R1_FB12_Pos      (12U)
3047 #define CAN_F1R1_FB12_Msk      (0x1UL << CAN_F1R1_FB12_Pos)                     /*!< 0x00001000 */
3048 #define CAN_F1R1_FB12          CAN_F1R1_FB12_Msk                               /*!<Filter bit 12 */
3049 #define CAN_F1R1_FB13_Pos      (13U)
3050 #define CAN_F1R1_FB13_Msk      (0x1UL << CAN_F1R1_FB13_Pos)                     /*!< 0x00002000 */
3051 #define CAN_F1R1_FB13          CAN_F1R1_FB13_Msk                               /*!<Filter bit 13 */
3052 #define CAN_F1R1_FB14_Pos      (14U)
3053 #define CAN_F1R1_FB14_Msk      (0x1UL << CAN_F1R1_FB14_Pos)                     /*!< 0x00004000 */
3054 #define CAN_F1R1_FB14          CAN_F1R1_FB14_Msk                               /*!<Filter bit 14 */
3055 #define CAN_F1R1_FB15_Pos      (15U)
3056 #define CAN_F1R1_FB15_Msk      (0x1UL << CAN_F1R1_FB15_Pos)                     /*!< 0x00008000 */
3057 #define CAN_F1R1_FB15          CAN_F1R1_FB15_Msk                               /*!<Filter bit 15 */
3058 #define CAN_F1R1_FB16_Pos      (16U)
3059 #define CAN_F1R1_FB16_Msk      (0x1UL << CAN_F1R1_FB16_Pos)                     /*!< 0x00010000 */
3060 #define CAN_F1R1_FB16          CAN_F1R1_FB16_Msk                               /*!<Filter bit 16 */
3061 #define CAN_F1R1_FB17_Pos      (17U)
3062 #define CAN_F1R1_FB17_Msk      (0x1UL << CAN_F1R1_FB17_Pos)                     /*!< 0x00020000 */
3063 #define CAN_F1R1_FB17          CAN_F1R1_FB17_Msk                               /*!<Filter bit 17 */
3064 #define CAN_F1R1_FB18_Pos      (18U)
3065 #define CAN_F1R1_FB18_Msk      (0x1UL << CAN_F1R1_FB18_Pos)                     /*!< 0x00040000 */
3066 #define CAN_F1R1_FB18          CAN_F1R1_FB18_Msk                               /*!<Filter bit 18 */
3067 #define CAN_F1R1_FB19_Pos      (19U)
3068 #define CAN_F1R1_FB19_Msk      (0x1UL << CAN_F1R1_FB19_Pos)                     /*!< 0x00080000 */
3069 #define CAN_F1R1_FB19          CAN_F1R1_FB19_Msk                               /*!<Filter bit 19 */
3070 #define CAN_F1R1_FB20_Pos      (20U)
3071 #define CAN_F1R1_FB20_Msk      (0x1UL << CAN_F1R1_FB20_Pos)                     /*!< 0x00100000 */
3072 #define CAN_F1R1_FB20          CAN_F1R1_FB20_Msk                               /*!<Filter bit 20 */
3073 #define CAN_F1R1_FB21_Pos      (21U)
3074 #define CAN_F1R1_FB21_Msk      (0x1UL << CAN_F1R1_FB21_Pos)                     /*!< 0x00200000 */
3075 #define CAN_F1R1_FB21          CAN_F1R1_FB21_Msk                               /*!<Filter bit 21 */
3076 #define CAN_F1R1_FB22_Pos      (22U)
3077 #define CAN_F1R1_FB22_Msk      (0x1UL << CAN_F1R1_FB22_Pos)                     /*!< 0x00400000 */
3078 #define CAN_F1R1_FB22          CAN_F1R1_FB22_Msk                               /*!<Filter bit 22 */
3079 #define CAN_F1R1_FB23_Pos      (23U)
3080 #define CAN_F1R1_FB23_Msk      (0x1UL << CAN_F1R1_FB23_Pos)                     /*!< 0x00800000 */
3081 #define CAN_F1R1_FB23          CAN_F1R1_FB23_Msk                               /*!<Filter bit 23 */
3082 #define CAN_F1R1_FB24_Pos      (24U)
3083 #define CAN_F1R1_FB24_Msk      (0x1UL << CAN_F1R1_FB24_Pos)                     /*!< 0x01000000 */
3084 #define CAN_F1R1_FB24          CAN_F1R1_FB24_Msk                               /*!<Filter bit 24 */
3085 #define CAN_F1R1_FB25_Pos      (25U)
3086 #define CAN_F1R1_FB25_Msk      (0x1UL << CAN_F1R1_FB25_Pos)                     /*!< 0x02000000 */
3087 #define CAN_F1R1_FB25          CAN_F1R1_FB25_Msk                               /*!<Filter bit 25 */
3088 #define CAN_F1R1_FB26_Pos      (26U)
3089 #define CAN_F1R1_FB26_Msk      (0x1UL << CAN_F1R1_FB26_Pos)                     /*!< 0x04000000 */
3090 #define CAN_F1R1_FB26          CAN_F1R1_FB26_Msk                               /*!<Filter bit 26 */
3091 #define CAN_F1R1_FB27_Pos      (27U)
3092 #define CAN_F1R1_FB27_Msk      (0x1UL << CAN_F1R1_FB27_Pos)                     /*!< 0x08000000 */
3093 #define CAN_F1R1_FB27          CAN_F1R1_FB27_Msk                               /*!<Filter bit 27 */
3094 #define CAN_F1R1_FB28_Pos      (28U)
3095 #define CAN_F1R1_FB28_Msk      (0x1UL << CAN_F1R1_FB28_Pos)                     /*!< 0x10000000 */
3096 #define CAN_F1R1_FB28          CAN_F1R1_FB28_Msk                               /*!<Filter bit 28 */
3097 #define CAN_F1R1_FB29_Pos      (29U)
3098 #define CAN_F1R1_FB29_Msk      (0x1UL << CAN_F1R1_FB29_Pos)                     /*!< 0x20000000 */
3099 #define CAN_F1R1_FB29          CAN_F1R1_FB29_Msk                               /*!<Filter bit 29 */
3100 #define CAN_F1R1_FB30_Pos      (30U)
3101 #define CAN_F1R1_FB30_Msk      (0x1UL << CAN_F1R1_FB30_Pos)                     /*!< 0x40000000 */
3102 #define CAN_F1R1_FB30          CAN_F1R1_FB30_Msk                               /*!<Filter bit 30 */
3103 #define CAN_F1R1_FB31_Pos      (31U)
3104 #define CAN_F1R1_FB31_Msk      (0x1UL << CAN_F1R1_FB31_Pos)                     /*!< 0x80000000 */
3105 #define CAN_F1R1_FB31          CAN_F1R1_FB31_Msk                               /*!<Filter bit 31 */
3106 
3107 /*******************  Bit definition for CAN_F2R1 register  *******************/
3108 #define CAN_F2R1_FB0_Pos       (0U)
3109 #define CAN_F2R1_FB0_Msk       (0x1UL << CAN_F2R1_FB0_Pos)                      /*!< 0x00000001 */
3110 #define CAN_F2R1_FB0           CAN_F2R1_FB0_Msk                                /*!<Filter bit 0 */
3111 #define CAN_F2R1_FB1_Pos       (1U)
3112 #define CAN_F2R1_FB1_Msk       (0x1UL << CAN_F2R1_FB1_Pos)                      /*!< 0x00000002 */
3113 #define CAN_F2R1_FB1           CAN_F2R1_FB1_Msk                                /*!<Filter bit 1 */
3114 #define CAN_F2R1_FB2_Pos       (2U)
3115 #define CAN_F2R1_FB2_Msk       (0x1UL << CAN_F2R1_FB2_Pos)                      /*!< 0x00000004 */
3116 #define CAN_F2R1_FB2           CAN_F2R1_FB2_Msk                                /*!<Filter bit 2 */
3117 #define CAN_F2R1_FB3_Pos       (3U)
3118 #define CAN_F2R1_FB3_Msk       (0x1UL << CAN_F2R1_FB3_Pos)                      /*!< 0x00000008 */
3119 #define CAN_F2R1_FB3           CAN_F2R1_FB3_Msk                                /*!<Filter bit 3 */
3120 #define CAN_F2R1_FB4_Pos       (4U)
3121 #define CAN_F2R1_FB4_Msk       (0x1UL << CAN_F2R1_FB4_Pos)                      /*!< 0x00000010 */
3122 #define CAN_F2R1_FB4           CAN_F2R1_FB4_Msk                                /*!<Filter bit 4 */
3123 #define CAN_F2R1_FB5_Pos       (5U)
3124 #define CAN_F2R1_FB5_Msk       (0x1UL << CAN_F2R1_FB5_Pos)                      /*!< 0x00000020 */
3125 #define CAN_F2R1_FB5           CAN_F2R1_FB5_Msk                                /*!<Filter bit 5 */
3126 #define CAN_F2R1_FB6_Pos       (6U)
3127 #define CAN_F2R1_FB6_Msk       (0x1UL << CAN_F2R1_FB6_Pos)                      /*!< 0x00000040 */
3128 #define CAN_F2R1_FB6           CAN_F2R1_FB6_Msk                                /*!<Filter bit 6 */
3129 #define CAN_F2R1_FB7_Pos       (7U)
3130 #define CAN_F2R1_FB7_Msk       (0x1UL << CAN_F2R1_FB7_Pos)                      /*!< 0x00000080 */
3131 #define CAN_F2R1_FB7           CAN_F2R1_FB7_Msk                                /*!<Filter bit 7 */
3132 #define CAN_F2R1_FB8_Pos       (8U)
3133 #define CAN_F2R1_FB8_Msk       (0x1UL << CAN_F2R1_FB8_Pos)                      /*!< 0x00000100 */
3134 #define CAN_F2R1_FB8           CAN_F2R1_FB8_Msk                                /*!<Filter bit 8 */
3135 #define CAN_F2R1_FB9_Pos       (9U)
3136 #define CAN_F2R1_FB9_Msk       (0x1UL << CAN_F2R1_FB9_Pos)                      /*!< 0x00000200 */
3137 #define CAN_F2R1_FB9           CAN_F2R1_FB9_Msk                                /*!<Filter bit 9 */
3138 #define CAN_F2R1_FB10_Pos      (10U)
3139 #define CAN_F2R1_FB10_Msk      (0x1UL << CAN_F2R1_FB10_Pos)                     /*!< 0x00000400 */
3140 #define CAN_F2R1_FB10          CAN_F2R1_FB10_Msk                               /*!<Filter bit 10 */
3141 #define CAN_F2R1_FB11_Pos      (11U)
3142 #define CAN_F2R1_FB11_Msk      (0x1UL << CAN_F2R1_FB11_Pos)                     /*!< 0x00000800 */
3143 #define CAN_F2R1_FB11          CAN_F2R1_FB11_Msk                               /*!<Filter bit 11 */
3144 #define CAN_F2R1_FB12_Pos      (12U)
3145 #define CAN_F2R1_FB12_Msk      (0x1UL << CAN_F2R1_FB12_Pos)                     /*!< 0x00001000 */
3146 #define CAN_F2R1_FB12          CAN_F2R1_FB12_Msk                               /*!<Filter bit 12 */
3147 #define CAN_F2R1_FB13_Pos      (13U)
3148 #define CAN_F2R1_FB13_Msk      (0x1UL << CAN_F2R1_FB13_Pos)                     /*!< 0x00002000 */
3149 #define CAN_F2R1_FB13          CAN_F2R1_FB13_Msk                               /*!<Filter bit 13 */
3150 #define CAN_F2R1_FB14_Pos      (14U)
3151 #define CAN_F2R1_FB14_Msk      (0x1UL << CAN_F2R1_FB14_Pos)                     /*!< 0x00004000 */
3152 #define CAN_F2R1_FB14          CAN_F2R1_FB14_Msk                               /*!<Filter bit 14 */
3153 #define CAN_F2R1_FB15_Pos      (15U)
3154 #define CAN_F2R1_FB15_Msk      (0x1UL << CAN_F2R1_FB15_Pos)                     /*!< 0x00008000 */
3155 #define CAN_F2R1_FB15          CAN_F2R1_FB15_Msk                               /*!<Filter bit 15 */
3156 #define CAN_F2R1_FB16_Pos      (16U)
3157 #define CAN_F2R1_FB16_Msk      (0x1UL << CAN_F2R1_FB16_Pos)                     /*!< 0x00010000 */
3158 #define CAN_F2R1_FB16          CAN_F2R1_FB16_Msk                               /*!<Filter bit 16 */
3159 #define CAN_F2R1_FB17_Pos      (17U)
3160 #define CAN_F2R1_FB17_Msk      (0x1UL << CAN_F2R1_FB17_Pos)                     /*!< 0x00020000 */
3161 #define CAN_F2R1_FB17          CAN_F2R1_FB17_Msk                               /*!<Filter bit 17 */
3162 #define CAN_F2R1_FB18_Pos      (18U)
3163 #define CAN_F2R1_FB18_Msk      (0x1UL << CAN_F2R1_FB18_Pos)                     /*!< 0x00040000 */
3164 #define CAN_F2R1_FB18          CAN_F2R1_FB18_Msk                               /*!<Filter bit 18 */
3165 #define CAN_F2R1_FB19_Pos      (19U)
3166 #define CAN_F2R1_FB19_Msk      (0x1UL << CAN_F2R1_FB19_Pos)                     /*!< 0x00080000 */
3167 #define CAN_F2R1_FB19          CAN_F2R1_FB19_Msk                               /*!<Filter bit 19 */
3168 #define CAN_F2R1_FB20_Pos      (20U)
3169 #define CAN_F2R1_FB20_Msk      (0x1UL << CAN_F2R1_FB20_Pos)                     /*!< 0x00100000 */
3170 #define CAN_F2R1_FB20          CAN_F2R1_FB20_Msk                               /*!<Filter bit 20 */
3171 #define CAN_F2R1_FB21_Pos      (21U)
3172 #define CAN_F2R1_FB21_Msk      (0x1UL << CAN_F2R1_FB21_Pos)                     /*!< 0x00200000 */
3173 #define CAN_F2R1_FB21          CAN_F2R1_FB21_Msk                               /*!<Filter bit 21 */
3174 #define CAN_F2R1_FB22_Pos      (22U)
3175 #define CAN_F2R1_FB22_Msk      (0x1UL << CAN_F2R1_FB22_Pos)                     /*!< 0x00400000 */
3176 #define CAN_F2R1_FB22          CAN_F2R1_FB22_Msk                               /*!<Filter bit 22 */
3177 #define CAN_F2R1_FB23_Pos      (23U)
3178 #define CAN_F2R1_FB23_Msk      (0x1UL << CAN_F2R1_FB23_Pos)                     /*!< 0x00800000 */
3179 #define CAN_F2R1_FB23          CAN_F2R1_FB23_Msk                               /*!<Filter bit 23 */
3180 #define CAN_F2R1_FB24_Pos      (24U)
3181 #define CAN_F2R1_FB24_Msk      (0x1UL << CAN_F2R1_FB24_Pos)                     /*!< 0x01000000 */
3182 #define CAN_F2R1_FB24          CAN_F2R1_FB24_Msk                               /*!<Filter bit 24 */
3183 #define CAN_F2R1_FB25_Pos      (25U)
3184 #define CAN_F2R1_FB25_Msk      (0x1UL << CAN_F2R1_FB25_Pos)                     /*!< 0x02000000 */
3185 #define CAN_F2R1_FB25          CAN_F2R1_FB25_Msk                               /*!<Filter bit 25 */
3186 #define CAN_F2R1_FB26_Pos      (26U)
3187 #define CAN_F2R1_FB26_Msk      (0x1UL << CAN_F2R1_FB26_Pos)                     /*!< 0x04000000 */
3188 #define CAN_F2R1_FB26          CAN_F2R1_FB26_Msk                               /*!<Filter bit 26 */
3189 #define CAN_F2R1_FB27_Pos      (27U)
3190 #define CAN_F2R1_FB27_Msk      (0x1UL << CAN_F2R1_FB27_Pos)                     /*!< 0x08000000 */
3191 #define CAN_F2R1_FB27          CAN_F2R1_FB27_Msk                               /*!<Filter bit 27 */
3192 #define CAN_F2R1_FB28_Pos      (28U)
3193 #define CAN_F2R1_FB28_Msk      (0x1UL << CAN_F2R1_FB28_Pos)                     /*!< 0x10000000 */
3194 #define CAN_F2R1_FB28          CAN_F2R1_FB28_Msk                               /*!<Filter bit 28 */
3195 #define CAN_F2R1_FB29_Pos      (29U)
3196 #define CAN_F2R1_FB29_Msk      (0x1UL << CAN_F2R1_FB29_Pos)                     /*!< 0x20000000 */
3197 #define CAN_F2R1_FB29          CAN_F2R1_FB29_Msk                               /*!<Filter bit 29 */
3198 #define CAN_F2R1_FB30_Pos      (30U)
3199 #define CAN_F2R1_FB30_Msk      (0x1UL << CAN_F2R1_FB30_Pos)                     /*!< 0x40000000 */
3200 #define CAN_F2R1_FB30          CAN_F2R1_FB30_Msk                               /*!<Filter bit 30 */
3201 #define CAN_F2R1_FB31_Pos      (31U)
3202 #define CAN_F2R1_FB31_Msk      (0x1UL << CAN_F2R1_FB31_Pos)                     /*!< 0x80000000 */
3203 #define CAN_F2R1_FB31          CAN_F2R1_FB31_Msk                               /*!<Filter bit 31 */
3204 
3205 /*******************  Bit definition for CAN_F3R1 register  *******************/
3206 #define CAN_F3R1_FB0_Pos       (0U)
3207 #define CAN_F3R1_FB0_Msk       (0x1UL << CAN_F3R1_FB0_Pos)                      /*!< 0x00000001 */
3208 #define CAN_F3R1_FB0           CAN_F3R1_FB0_Msk                                /*!<Filter bit 0 */
3209 #define CAN_F3R1_FB1_Pos       (1U)
3210 #define CAN_F3R1_FB1_Msk       (0x1UL << CAN_F3R1_FB1_Pos)                      /*!< 0x00000002 */
3211 #define CAN_F3R1_FB1           CAN_F3R1_FB1_Msk                                /*!<Filter bit 1 */
3212 #define CAN_F3R1_FB2_Pos       (2U)
3213 #define CAN_F3R1_FB2_Msk       (0x1UL << CAN_F3R1_FB2_Pos)                      /*!< 0x00000004 */
3214 #define CAN_F3R1_FB2           CAN_F3R1_FB2_Msk                                /*!<Filter bit 2 */
3215 #define CAN_F3R1_FB3_Pos       (3U)
3216 #define CAN_F3R1_FB3_Msk       (0x1UL << CAN_F3R1_FB3_Pos)                      /*!< 0x00000008 */
3217 #define CAN_F3R1_FB3           CAN_F3R1_FB3_Msk                                /*!<Filter bit 3 */
3218 #define CAN_F3R1_FB4_Pos       (4U)
3219 #define CAN_F3R1_FB4_Msk       (0x1UL << CAN_F3R1_FB4_Pos)                      /*!< 0x00000010 */
3220 #define CAN_F3R1_FB4           CAN_F3R1_FB4_Msk                                /*!<Filter bit 4 */
3221 #define CAN_F3R1_FB5_Pos       (5U)
3222 #define CAN_F3R1_FB5_Msk       (0x1UL << CAN_F3R1_FB5_Pos)                      /*!< 0x00000020 */
3223 #define CAN_F3R1_FB5           CAN_F3R1_FB5_Msk                                /*!<Filter bit 5 */
3224 #define CAN_F3R1_FB6_Pos       (6U)
3225 #define CAN_F3R1_FB6_Msk       (0x1UL << CAN_F3R1_FB6_Pos)                      /*!< 0x00000040 */
3226 #define CAN_F3R1_FB6           CAN_F3R1_FB6_Msk                                /*!<Filter bit 6 */
3227 #define CAN_F3R1_FB7_Pos       (7U)
3228 #define CAN_F3R1_FB7_Msk       (0x1UL << CAN_F3R1_FB7_Pos)                      /*!< 0x00000080 */
3229 #define CAN_F3R1_FB7           CAN_F3R1_FB7_Msk                                /*!<Filter bit 7 */
3230 #define CAN_F3R1_FB8_Pos       (8U)
3231 #define CAN_F3R1_FB8_Msk       (0x1UL << CAN_F3R1_FB8_Pos)                      /*!< 0x00000100 */
3232 #define CAN_F3R1_FB8           CAN_F3R1_FB8_Msk                                /*!<Filter bit 8 */
3233 #define CAN_F3R1_FB9_Pos       (9U)
3234 #define CAN_F3R1_FB9_Msk       (0x1UL << CAN_F3R1_FB9_Pos)                      /*!< 0x00000200 */
3235 #define CAN_F3R1_FB9           CAN_F3R1_FB9_Msk                                /*!<Filter bit 9 */
3236 #define CAN_F3R1_FB10_Pos      (10U)
3237 #define CAN_F3R1_FB10_Msk      (0x1UL << CAN_F3R1_FB10_Pos)                     /*!< 0x00000400 */
3238 #define CAN_F3R1_FB10          CAN_F3R1_FB10_Msk                               /*!<Filter bit 10 */
3239 #define CAN_F3R1_FB11_Pos      (11U)
3240 #define CAN_F3R1_FB11_Msk      (0x1UL << CAN_F3R1_FB11_Pos)                     /*!< 0x00000800 */
3241 #define CAN_F3R1_FB11          CAN_F3R1_FB11_Msk                               /*!<Filter bit 11 */
3242 #define CAN_F3R1_FB12_Pos      (12U)
3243 #define CAN_F3R1_FB12_Msk      (0x1UL << CAN_F3R1_FB12_Pos)                     /*!< 0x00001000 */
3244 #define CAN_F3R1_FB12          CAN_F3R1_FB12_Msk                               /*!<Filter bit 12 */
3245 #define CAN_F3R1_FB13_Pos      (13U)
3246 #define CAN_F3R1_FB13_Msk      (0x1UL << CAN_F3R1_FB13_Pos)                     /*!< 0x00002000 */
3247 #define CAN_F3R1_FB13          CAN_F3R1_FB13_Msk                               /*!<Filter bit 13 */
3248 #define CAN_F3R1_FB14_Pos      (14U)
3249 #define CAN_F3R1_FB14_Msk      (0x1UL << CAN_F3R1_FB14_Pos)                     /*!< 0x00004000 */
3250 #define CAN_F3R1_FB14          CAN_F3R1_FB14_Msk                               /*!<Filter bit 14 */
3251 #define CAN_F3R1_FB15_Pos      (15U)
3252 #define CAN_F3R1_FB15_Msk      (0x1UL << CAN_F3R1_FB15_Pos)                     /*!< 0x00008000 */
3253 #define CAN_F3R1_FB15          CAN_F3R1_FB15_Msk                               /*!<Filter bit 15 */
3254 #define CAN_F3R1_FB16_Pos      (16U)
3255 #define CAN_F3R1_FB16_Msk      (0x1UL << CAN_F3R1_FB16_Pos)                     /*!< 0x00010000 */
3256 #define CAN_F3R1_FB16          CAN_F3R1_FB16_Msk                               /*!<Filter bit 16 */
3257 #define CAN_F3R1_FB17_Pos      (17U)
3258 #define CAN_F3R1_FB17_Msk      (0x1UL << CAN_F3R1_FB17_Pos)                     /*!< 0x00020000 */
3259 #define CAN_F3R1_FB17          CAN_F3R1_FB17_Msk                               /*!<Filter bit 17 */
3260 #define CAN_F3R1_FB18_Pos      (18U)
3261 #define CAN_F3R1_FB18_Msk      (0x1UL << CAN_F3R1_FB18_Pos)                     /*!< 0x00040000 */
3262 #define CAN_F3R1_FB18          CAN_F3R1_FB18_Msk                               /*!<Filter bit 18 */
3263 #define CAN_F3R1_FB19_Pos      (19U)
3264 #define CAN_F3R1_FB19_Msk      (0x1UL << CAN_F3R1_FB19_Pos)                     /*!< 0x00080000 */
3265 #define CAN_F3R1_FB19          CAN_F3R1_FB19_Msk                               /*!<Filter bit 19 */
3266 #define CAN_F3R1_FB20_Pos      (20U)
3267 #define CAN_F3R1_FB20_Msk      (0x1UL << CAN_F3R1_FB20_Pos)                     /*!< 0x00100000 */
3268 #define CAN_F3R1_FB20          CAN_F3R1_FB20_Msk                               /*!<Filter bit 20 */
3269 #define CAN_F3R1_FB21_Pos      (21U)
3270 #define CAN_F3R1_FB21_Msk      (0x1UL << CAN_F3R1_FB21_Pos)                     /*!< 0x00200000 */
3271 #define CAN_F3R1_FB21          CAN_F3R1_FB21_Msk                               /*!<Filter bit 21 */
3272 #define CAN_F3R1_FB22_Pos      (22U)
3273 #define CAN_F3R1_FB22_Msk      (0x1UL << CAN_F3R1_FB22_Pos)                     /*!< 0x00400000 */
3274 #define CAN_F3R1_FB22          CAN_F3R1_FB22_Msk                               /*!<Filter bit 22 */
3275 #define CAN_F3R1_FB23_Pos      (23U)
3276 #define CAN_F3R1_FB23_Msk      (0x1UL << CAN_F3R1_FB23_Pos)                     /*!< 0x00800000 */
3277 #define CAN_F3R1_FB23          CAN_F3R1_FB23_Msk                               /*!<Filter bit 23 */
3278 #define CAN_F3R1_FB24_Pos      (24U)
3279 #define CAN_F3R1_FB24_Msk      (0x1UL << CAN_F3R1_FB24_Pos)                     /*!< 0x01000000 */
3280 #define CAN_F3R1_FB24          CAN_F3R1_FB24_Msk                               /*!<Filter bit 24 */
3281 #define CAN_F3R1_FB25_Pos      (25U)
3282 #define CAN_F3R1_FB25_Msk      (0x1UL << CAN_F3R1_FB25_Pos)                     /*!< 0x02000000 */
3283 #define CAN_F3R1_FB25          CAN_F3R1_FB25_Msk                               /*!<Filter bit 25 */
3284 #define CAN_F3R1_FB26_Pos      (26U)
3285 #define CAN_F3R1_FB26_Msk      (0x1UL << CAN_F3R1_FB26_Pos)                     /*!< 0x04000000 */
3286 #define CAN_F3R1_FB26          CAN_F3R1_FB26_Msk                               /*!<Filter bit 26 */
3287 #define CAN_F3R1_FB27_Pos      (27U)
3288 #define CAN_F3R1_FB27_Msk      (0x1UL << CAN_F3R1_FB27_Pos)                     /*!< 0x08000000 */
3289 #define CAN_F3R1_FB27          CAN_F3R1_FB27_Msk                               /*!<Filter bit 27 */
3290 #define CAN_F3R1_FB28_Pos      (28U)
3291 #define CAN_F3R1_FB28_Msk      (0x1UL << CAN_F3R1_FB28_Pos)                     /*!< 0x10000000 */
3292 #define CAN_F3R1_FB28          CAN_F3R1_FB28_Msk                               /*!<Filter bit 28 */
3293 #define CAN_F3R1_FB29_Pos      (29U)
3294 #define CAN_F3R1_FB29_Msk      (0x1UL << CAN_F3R1_FB29_Pos)                     /*!< 0x20000000 */
3295 #define CAN_F3R1_FB29          CAN_F3R1_FB29_Msk                               /*!<Filter bit 29 */
3296 #define CAN_F3R1_FB30_Pos      (30U)
3297 #define CAN_F3R1_FB30_Msk      (0x1UL << CAN_F3R1_FB30_Pos)                     /*!< 0x40000000 */
3298 #define CAN_F3R1_FB30          CAN_F3R1_FB30_Msk                               /*!<Filter bit 30 */
3299 #define CAN_F3R1_FB31_Pos      (31U)
3300 #define CAN_F3R1_FB31_Msk      (0x1UL << CAN_F3R1_FB31_Pos)                     /*!< 0x80000000 */
3301 #define CAN_F3R1_FB31          CAN_F3R1_FB31_Msk                               /*!<Filter bit 31 */
3302 
3303 /*******************  Bit definition for CAN_F4R1 register  *******************/
3304 #define CAN_F4R1_FB0_Pos       (0U)
3305 #define CAN_F4R1_FB0_Msk       (0x1UL << CAN_F4R1_FB0_Pos)                      /*!< 0x00000001 */
3306 #define CAN_F4R1_FB0           CAN_F4R1_FB0_Msk                                /*!<Filter bit 0 */
3307 #define CAN_F4R1_FB1_Pos       (1U)
3308 #define CAN_F4R1_FB1_Msk       (0x1UL << CAN_F4R1_FB1_Pos)                      /*!< 0x00000002 */
3309 #define CAN_F4R1_FB1           CAN_F4R1_FB1_Msk                                /*!<Filter bit 1 */
3310 #define CAN_F4R1_FB2_Pos       (2U)
3311 #define CAN_F4R1_FB2_Msk       (0x1UL << CAN_F4R1_FB2_Pos)                      /*!< 0x00000004 */
3312 #define CAN_F4R1_FB2           CAN_F4R1_FB2_Msk                                /*!<Filter bit 2 */
3313 #define CAN_F4R1_FB3_Pos       (3U)
3314 #define CAN_F4R1_FB3_Msk       (0x1UL << CAN_F4R1_FB3_Pos)                      /*!< 0x00000008 */
3315 #define CAN_F4R1_FB3           CAN_F4R1_FB3_Msk                                /*!<Filter bit 3 */
3316 #define CAN_F4R1_FB4_Pos       (4U)
3317 #define CAN_F4R1_FB4_Msk       (0x1UL << CAN_F4R1_FB4_Pos)                      /*!< 0x00000010 */
3318 #define CAN_F4R1_FB4           CAN_F4R1_FB4_Msk                                /*!<Filter bit 4 */
3319 #define CAN_F4R1_FB5_Pos       (5U)
3320 #define CAN_F4R1_FB5_Msk       (0x1UL << CAN_F4R1_FB5_Pos)                      /*!< 0x00000020 */
3321 #define CAN_F4R1_FB5           CAN_F4R1_FB5_Msk                                /*!<Filter bit 5 */
3322 #define CAN_F4R1_FB6_Pos       (6U)
3323 #define CAN_F4R1_FB6_Msk       (0x1UL << CAN_F4R1_FB6_Pos)                      /*!< 0x00000040 */
3324 #define CAN_F4R1_FB6           CAN_F4R1_FB6_Msk                                /*!<Filter bit 6 */
3325 #define CAN_F4R1_FB7_Pos       (7U)
3326 #define CAN_F4R1_FB7_Msk       (0x1UL << CAN_F4R1_FB7_Pos)                      /*!< 0x00000080 */
3327 #define CAN_F4R1_FB7           CAN_F4R1_FB7_Msk                                /*!<Filter bit 7 */
3328 #define CAN_F4R1_FB8_Pos       (8U)
3329 #define CAN_F4R1_FB8_Msk       (0x1UL << CAN_F4R1_FB8_Pos)                      /*!< 0x00000100 */
3330 #define CAN_F4R1_FB8           CAN_F4R1_FB8_Msk                                /*!<Filter bit 8 */
3331 #define CAN_F4R1_FB9_Pos       (9U)
3332 #define CAN_F4R1_FB9_Msk       (0x1UL << CAN_F4R1_FB9_Pos)                      /*!< 0x00000200 */
3333 #define CAN_F4R1_FB9           CAN_F4R1_FB9_Msk                                /*!<Filter bit 9 */
3334 #define CAN_F4R1_FB10_Pos      (10U)
3335 #define CAN_F4R1_FB10_Msk      (0x1UL << CAN_F4R1_FB10_Pos)                     /*!< 0x00000400 */
3336 #define CAN_F4R1_FB10          CAN_F4R1_FB10_Msk                               /*!<Filter bit 10 */
3337 #define CAN_F4R1_FB11_Pos      (11U)
3338 #define CAN_F4R1_FB11_Msk      (0x1UL << CAN_F4R1_FB11_Pos)                     /*!< 0x00000800 */
3339 #define CAN_F4R1_FB11          CAN_F4R1_FB11_Msk                               /*!<Filter bit 11 */
3340 #define CAN_F4R1_FB12_Pos      (12U)
3341 #define CAN_F4R1_FB12_Msk      (0x1UL << CAN_F4R1_FB12_Pos)                     /*!< 0x00001000 */
3342 #define CAN_F4R1_FB12          CAN_F4R1_FB12_Msk                               /*!<Filter bit 12 */
3343 #define CAN_F4R1_FB13_Pos      (13U)
3344 #define CAN_F4R1_FB13_Msk      (0x1UL << CAN_F4R1_FB13_Pos)                     /*!< 0x00002000 */
3345 #define CAN_F4R1_FB13          CAN_F4R1_FB13_Msk                               /*!<Filter bit 13 */
3346 #define CAN_F4R1_FB14_Pos      (14U)
3347 #define CAN_F4R1_FB14_Msk      (0x1UL << CAN_F4R1_FB14_Pos)                     /*!< 0x00004000 */
3348 #define CAN_F4R1_FB14          CAN_F4R1_FB14_Msk                               /*!<Filter bit 14 */
3349 #define CAN_F4R1_FB15_Pos      (15U)
3350 #define CAN_F4R1_FB15_Msk      (0x1UL << CAN_F4R1_FB15_Pos)                     /*!< 0x00008000 */
3351 #define CAN_F4R1_FB15          CAN_F4R1_FB15_Msk                               /*!<Filter bit 15 */
3352 #define CAN_F4R1_FB16_Pos      (16U)
3353 #define CAN_F4R1_FB16_Msk      (0x1UL << CAN_F4R1_FB16_Pos)                     /*!< 0x00010000 */
3354 #define CAN_F4R1_FB16          CAN_F4R1_FB16_Msk                               /*!<Filter bit 16 */
3355 #define CAN_F4R1_FB17_Pos      (17U)
3356 #define CAN_F4R1_FB17_Msk      (0x1UL << CAN_F4R1_FB17_Pos)                     /*!< 0x00020000 */
3357 #define CAN_F4R1_FB17          CAN_F4R1_FB17_Msk                               /*!<Filter bit 17 */
3358 #define CAN_F4R1_FB18_Pos      (18U)
3359 #define CAN_F4R1_FB18_Msk      (0x1UL << CAN_F4R1_FB18_Pos)                     /*!< 0x00040000 */
3360 #define CAN_F4R1_FB18          CAN_F4R1_FB18_Msk                               /*!<Filter bit 18 */
3361 #define CAN_F4R1_FB19_Pos      (19U)
3362 #define CAN_F4R1_FB19_Msk      (0x1UL << CAN_F4R1_FB19_Pos)                     /*!< 0x00080000 */
3363 #define CAN_F4R1_FB19          CAN_F4R1_FB19_Msk                               /*!<Filter bit 19 */
3364 #define CAN_F4R1_FB20_Pos      (20U)
3365 #define CAN_F4R1_FB20_Msk      (0x1UL << CAN_F4R1_FB20_Pos)                     /*!< 0x00100000 */
3366 #define CAN_F4R1_FB20          CAN_F4R1_FB20_Msk                               /*!<Filter bit 20 */
3367 #define CAN_F4R1_FB21_Pos      (21U)
3368 #define CAN_F4R1_FB21_Msk      (0x1UL << CAN_F4R1_FB21_Pos)                     /*!< 0x00200000 */
3369 #define CAN_F4R1_FB21          CAN_F4R1_FB21_Msk                               /*!<Filter bit 21 */
3370 #define CAN_F4R1_FB22_Pos      (22U)
3371 #define CAN_F4R1_FB22_Msk      (0x1UL << CAN_F4R1_FB22_Pos)                     /*!< 0x00400000 */
3372 #define CAN_F4R1_FB22          CAN_F4R1_FB22_Msk                               /*!<Filter bit 22 */
3373 #define CAN_F4R1_FB23_Pos      (23U)
3374 #define CAN_F4R1_FB23_Msk      (0x1UL << CAN_F4R1_FB23_Pos)                     /*!< 0x00800000 */
3375 #define CAN_F4R1_FB23          CAN_F4R1_FB23_Msk                               /*!<Filter bit 23 */
3376 #define CAN_F4R1_FB24_Pos      (24U)
3377 #define CAN_F4R1_FB24_Msk      (0x1UL << CAN_F4R1_FB24_Pos)                     /*!< 0x01000000 */
3378 #define CAN_F4R1_FB24          CAN_F4R1_FB24_Msk                               /*!<Filter bit 24 */
3379 #define CAN_F4R1_FB25_Pos      (25U)
3380 #define CAN_F4R1_FB25_Msk      (0x1UL << CAN_F4R1_FB25_Pos)                     /*!< 0x02000000 */
3381 #define CAN_F4R1_FB25          CAN_F4R1_FB25_Msk                               /*!<Filter bit 25 */
3382 #define CAN_F4R1_FB26_Pos      (26U)
3383 #define CAN_F4R1_FB26_Msk      (0x1UL << CAN_F4R1_FB26_Pos)                     /*!< 0x04000000 */
3384 #define CAN_F4R1_FB26          CAN_F4R1_FB26_Msk                               /*!<Filter bit 26 */
3385 #define CAN_F4R1_FB27_Pos      (27U)
3386 #define CAN_F4R1_FB27_Msk      (0x1UL << CAN_F4R1_FB27_Pos)                     /*!< 0x08000000 */
3387 #define CAN_F4R1_FB27          CAN_F4R1_FB27_Msk                               /*!<Filter bit 27 */
3388 #define CAN_F4R1_FB28_Pos      (28U)
3389 #define CAN_F4R1_FB28_Msk      (0x1UL << CAN_F4R1_FB28_Pos)                     /*!< 0x10000000 */
3390 #define CAN_F4R1_FB28          CAN_F4R1_FB28_Msk                               /*!<Filter bit 28 */
3391 #define CAN_F4R1_FB29_Pos      (29U)
3392 #define CAN_F4R1_FB29_Msk      (0x1UL << CAN_F4R1_FB29_Pos)                     /*!< 0x20000000 */
3393 #define CAN_F4R1_FB29          CAN_F4R1_FB29_Msk                               /*!<Filter bit 29 */
3394 #define CAN_F4R1_FB30_Pos      (30U)
3395 #define CAN_F4R1_FB30_Msk      (0x1UL << CAN_F4R1_FB30_Pos)                     /*!< 0x40000000 */
3396 #define CAN_F4R1_FB30          CAN_F4R1_FB30_Msk                               /*!<Filter bit 30 */
3397 #define CAN_F4R1_FB31_Pos      (31U)
3398 #define CAN_F4R1_FB31_Msk      (0x1UL << CAN_F4R1_FB31_Pos)                     /*!< 0x80000000 */
3399 #define CAN_F4R1_FB31          CAN_F4R1_FB31_Msk                               /*!<Filter bit 31 */
3400 
3401 /*******************  Bit definition for CAN_F5R1 register  *******************/
3402 #define CAN_F5R1_FB0_Pos       (0U)
3403 #define CAN_F5R1_FB0_Msk       (0x1UL << CAN_F5R1_FB0_Pos)                      /*!< 0x00000001 */
3404 #define CAN_F5R1_FB0           CAN_F5R1_FB0_Msk                                /*!<Filter bit 0 */
3405 #define CAN_F5R1_FB1_Pos       (1U)
3406 #define CAN_F5R1_FB1_Msk       (0x1UL << CAN_F5R1_FB1_Pos)                      /*!< 0x00000002 */
3407 #define CAN_F5R1_FB1           CAN_F5R1_FB1_Msk                                /*!<Filter bit 1 */
3408 #define CAN_F5R1_FB2_Pos       (2U)
3409 #define CAN_F5R1_FB2_Msk       (0x1UL << CAN_F5R1_FB2_Pos)                      /*!< 0x00000004 */
3410 #define CAN_F5R1_FB2           CAN_F5R1_FB2_Msk                                /*!<Filter bit 2 */
3411 #define CAN_F5R1_FB3_Pos       (3U)
3412 #define CAN_F5R1_FB3_Msk       (0x1UL << CAN_F5R1_FB3_Pos)                      /*!< 0x00000008 */
3413 #define CAN_F5R1_FB3           CAN_F5R1_FB3_Msk                                /*!<Filter bit 3 */
3414 #define CAN_F5R1_FB4_Pos       (4U)
3415 #define CAN_F5R1_FB4_Msk       (0x1UL << CAN_F5R1_FB4_Pos)                      /*!< 0x00000010 */
3416 #define CAN_F5R1_FB4           CAN_F5R1_FB4_Msk                                /*!<Filter bit 4 */
3417 #define CAN_F5R1_FB5_Pos       (5U)
3418 #define CAN_F5R1_FB5_Msk       (0x1UL << CAN_F5R1_FB5_Pos)                      /*!< 0x00000020 */
3419 #define CAN_F5R1_FB5           CAN_F5R1_FB5_Msk                                /*!<Filter bit 5 */
3420 #define CAN_F5R1_FB6_Pos       (6U)
3421 #define CAN_F5R1_FB6_Msk       (0x1UL << CAN_F5R1_FB6_Pos)                      /*!< 0x00000040 */
3422 #define CAN_F5R1_FB6           CAN_F5R1_FB6_Msk                                /*!<Filter bit 6 */
3423 #define CAN_F5R1_FB7_Pos       (7U)
3424 #define CAN_F5R1_FB7_Msk       (0x1UL << CAN_F5R1_FB7_Pos)                      /*!< 0x00000080 */
3425 #define CAN_F5R1_FB7           CAN_F5R1_FB7_Msk                                /*!<Filter bit 7 */
3426 #define CAN_F5R1_FB8_Pos       (8U)
3427 #define CAN_F5R1_FB8_Msk       (0x1UL << CAN_F5R1_FB8_Pos)                      /*!< 0x00000100 */
3428 #define CAN_F5R1_FB8           CAN_F5R1_FB8_Msk                                /*!<Filter bit 8 */
3429 #define CAN_F5R1_FB9_Pos       (9U)
3430 #define CAN_F5R1_FB9_Msk       (0x1UL << CAN_F5R1_FB9_Pos)                      /*!< 0x00000200 */
3431 #define CAN_F5R1_FB9           CAN_F5R1_FB9_Msk                                /*!<Filter bit 9 */
3432 #define CAN_F5R1_FB10_Pos      (10U)
3433 #define CAN_F5R1_FB10_Msk      (0x1UL << CAN_F5R1_FB10_Pos)                     /*!< 0x00000400 */
3434 #define CAN_F5R1_FB10          CAN_F5R1_FB10_Msk                               /*!<Filter bit 10 */
3435 #define CAN_F5R1_FB11_Pos      (11U)
3436 #define CAN_F5R1_FB11_Msk      (0x1UL << CAN_F5R1_FB11_Pos)                     /*!< 0x00000800 */
3437 #define CAN_F5R1_FB11          CAN_F5R1_FB11_Msk                               /*!<Filter bit 11 */
3438 #define CAN_F5R1_FB12_Pos      (12U)
3439 #define CAN_F5R1_FB12_Msk      (0x1UL << CAN_F5R1_FB12_Pos)                     /*!< 0x00001000 */
3440 #define CAN_F5R1_FB12          CAN_F5R1_FB12_Msk                               /*!<Filter bit 12 */
3441 #define CAN_F5R1_FB13_Pos      (13U)
3442 #define CAN_F5R1_FB13_Msk      (0x1UL << CAN_F5R1_FB13_Pos)                     /*!< 0x00002000 */
3443 #define CAN_F5R1_FB13          CAN_F5R1_FB13_Msk                               /*!<Filter bit 13 */
3444 #define CAN_F5R1_FB14_Pos      (14U)
3445 #define CAN_F5R1_FB14_Msk      (0x1UL << CAN_F5R1_FB14_Pos)                     /*!< 0x00004000 */
3446 #define CAN_F5R1_FB14          CAN_F5R1_FB14_Msk                               /*!<Filter bit 14 */
3447 #define CAN_F5R1_FB15_Pos      (15U)
3448 #define CAN_F5R1_FB15_Msk      (0x1UL << CAN_F5R1_FB15_Pos)                     /*!< 0x00008000 */
3449 #define CAN_F5R1_FB15          CAN_F5R1_FB15_Msk                               /*!<Filter bit 15 */
3450 #define CAN_F5R1_FB16_Pos      (16U)
3451 #define CAN_F5R1_FB16_Msk      (0x1UL << CAN_F5R1_FB16_Pos)                     /*!< 0x00010000 */
3452 #define CAN_F5R1_FB16          CAN_F5R1_FB16_Msk                               /*!<Filter bit 16 */
3453 #define CAN_F5R1_FB17_Pos      (17U)
3454 #define CAN_F5R1_FB17_Msk      (0x1UL << CAN_F5R1_FB17_Pos)                     /*!< 0x00020000 */
3455 #define CAN_F5R1_FB17          CAN_F5R1_FB17_Msk                               /*!<Filter bit 17 */
3456 #define CAN_F5R1_FB18_Pos      (18U)
3457 #define CAN_F5R1_FB18_Msk      (0x1UL << CAN_F5R1_FB18_Pos)                     /*!< 0x00040000 */
3458 #define CAN_F5R1_FB18          CAN_F5R1_FB18_Msk                               /*!<Filter bit 18 */
3459 #define CAN_F5R1_FB19_Pos      (19U)
3460 #define CAN_F5R1_FB19_Msk      (0x1UL << CAN_F5R1_FB19_Pos)                     /*!< 0x00080000 */
3461 #define CAN_F5R1_FB19          CAN_F5R1_FB19_Msk                               /*!<Filter bit 19 */
3462 #define CAN_F5R1_FB20_Pos      (20U)
3463 #define CAN_F5R1_FB20_Msk      (0x1UL << CAN_F5R1_FB20_Pos)                     /*!< 0x00100000 */
3464 #define CAN_F5R1_FB20          CAN_F5R1_FB20_Msk                               /*!<Filter bit 20 */
3465 #define CAN_F5R1_FB21_Pos      (21U)
3466 #define CAN_F5R1_FB21_Msk      (0x1UL << CAN_F5R1_FB21_Pos)                     /*!< 0x00200000 */
3467 #define CAN_F5R1_FB21          CAN_F5R1_FB21_Msk                               /*!<Filter bit 21 */
3468 #define CAN_F5R1_FB22_Pos      (22U)
3469 #define CAN_F5R1_FB22_Msk      (0x1UL << CAN_F5R1_FB22_Pos)                     /*!< 0x00400000 */
3470 #define CAN_F5R1_FB22          CAN_F5R1_FB22_Msk                               /*!<Filter bit 22 */
3471 #define CAN_F5R1_FB23_Pos      (23U)
3472 #define CAN_F5R1_FB23_Msk      (0x1UL << CAN_F5R1_FB23_Pos)                     /*!< 0x00800000 */
3473 #define CAN_F5R1_FB23          CAN_F5R1_FB23_Msk                               /*!<Filter bit 23 */
3474 #define CAN_F5R1_FB24_Pos      (24U)
3475 #define CAN_F5R1_FB24_Msk      (0x1UL << CAN_F5R1_FB24_Pos)                     /*!< 0x01000000 */
3476 #define CAN_F5R1_FB24          CAN_F5R1_FB24_Msk                               /*!<Filter bit 24 */
3477 #define CAN_F5R1_FB25_Pos      (25U)
3478 #define CAN_F5R1_FB25_Msk      (0x1UL << CAN_F5R1_FB25_Pos)                     /*!< 0x02000000 */
3479 #define CAN_F5R1_FB25          CAN_F5R1_FB25_Msk                               /*!<Filter bit 25 */
3480 #define CAN_F5R1_FB26_Pos      (26U)
3481 #define CAN_F5R1_FB26_Msk      (0x1UL << CAN_F5R1_FB26_Pos)                     /*!< 0x04000000 */
3482 #define CAN_F5R1_FB26          CAN_F5R1_FB26_Msk                               /*!<Filter bit 26 */
3483 #define CAN_F5R1_FB27_Pos      (27U)
3484 #define CAN_F5R1_FB27_Msk      (0x1UL << CAN_F5R1_FB27_Pos)                     /*!< 0x08000000 */
3485 #define CAN_F5R1_FB27          CAN_F5R1_FB27_Msk                               /*!<Filter bit 27 */
3486 #define CAN_F5R1_FB28_Pos      (28U)
3487 #define CAN_F5R1_FB28_Msk      (0x1UL << CAN_F5R1_FB28_Pos)                     /*!< 0x10000000 */
3488 #define CAN_F5R1_FB28          CAN_F5R1_FB28_Msk                               /*!<Filter bit 28 */
3489 #define CAN_F5R1_FB29_Pos      (29U)
3490 #define CAN_F5R1_FB29_Msk      (0x1UL << CAN_F5R1_FB29_Pos)                     /*!< 0x20000000 */
3491 #define CAN_F5R1_FB29          CAN_F5R1_FB29_Msk                               /*!<Filter bit 29 */
3492 #define CAN_F5R1_FB30_Pos      (30U)
3493 #define CAN_F5R1_FB30_Msk      (0x1UL << CAN_F5R1_FB30_Pos)                     /*!< 0x40000000 */
3494 #define CAN_F5R1_FB30          CAN_F5R1_FB30_Msk                               /*!<Filter bit 30 */
3495 #define CAN_F5R1_FB31_Pos      (31U)
3496 #define CAN_F5R1_FB31_Msk      (0x1UL << CAN_F5R1_FB31_Pos)                     /*!< 0x80000000 */
3497 #define CAN_F5R1_FB31          CAN_F5R1_FB31_Msk                               /*!<Filter bit 31 */
3498 
3499 /*******************  Bit definition for CAN_F6R1 register  *******************/
3500 #define CAN_F6R1_FB0_Pos       (0U)
3501 #define CAN_F6R1_FB0_Msk       (0x1UL << CAN_F6R1_FB0_Pos)                      /*!< 0x00000001 */
3502 #define CAN_F6R1_FB0           CAN_F6R1_FB0_Msk                                /*!<Filter bit 0 */
3503 #define CAN_F6R1_FB1_Pos       (1U)
3504 #define CAN_F6R1_FB1_Msk       (0x1UL << CAN_F6R1_FB1_Pos)                      /*!< 0x00000002 */
3505 #define CAN_F6R1_FB1           CAN_F6R1_FB1_Msk                                /*!<Filter bit 1 */
3506 #define CAN_F6R1_FB2_Pos       (2U)
3507 #define CAN_F6R1_FB2_Msk       (0x1UL << CAN_F6R1_FB2_Pos)                      /*!< 0x00000004 */
3508 #define CAN_F6R1_FB2           CAN_F6R1_FB2_Msk                                /*!<Filter bit 2 */
3509 #define CAN_F6R1_FB3_Pos       (3U)
3510 #define CAN_F6R1_FB3_Msk       (0x1UL << CAN_F6R1_FB3_Pos)                      /*!< 0x00000008 */
3511 #define CAN_F6R1_FB3           CAN_F6R1_FB3_Msk                                /*!<Filter bit 3 */
3512 #define CAN_F6R1_FB4_Pos       (4U)
3513 #define CAN_F6R1_FB4_Msk       (0x1UL << CAN_F6R1_FB4_Pos)                      /*!< 0x00000010 */
3514 #define CAN_F6R1_FB4           CAN_F6R1_FB4_Msk                                /*!<Filter bit 4 */
3515 #define CAN_F6R1_FB5_Pos       (5U)
3516 #define CAN_F6R1_FB5_Msk       (0x1UL << CAN_F6R1_FB5_Pos)                      /*!< 0x00000020 */
3517 #define CAN_F6R1_FB5           CAN_F6R1_FB5_Msk                                /*!<Filter bit 5 */
3518 #define CAN_F6R1_FB6_Pos       (6U)
3519 #define CAN_F6R1_FB6_Msk       (0x1UL << CAN_F6R1_FB6_Pos)                      /*!< 0x00000040 */
3520 #define CAN_F6R1_FB6           CAN_F6R1_FB6_Msk                                /*!<Filter bit 6 */
3521 #define CAN_F6R1_FB7_Pos       (7U)
3522 #define CAN_F6R1_FB7_Msk       (0x1UL << CAN_F6R1_FB7_Pos)                      /*!< 0x00000080 */
3523 #define CAN_F6R1_FB7           CAN_F6R1_FB7_Msk                                /*!<Filter bit 7 */
3524 #define CAN_F6R1_FB8_Pos       (8U)
3525 #define CAN_F6R1_FB8_Msk       (0x1UL << CAN_F6R1_FB8_Pos)                      /*!< 0x00000100 */
3526 #define CAN_F6R1_FB8           CAN_F6R1_FB8_Msk                                /*!<Filter bit 8 */
3527 #define CAN_F6R1_FB9_Pos       (9U)
3528 #define CAN_F6R1_FB9_Msk       (0x1UL << CAN_F6R1_FB9_Pos)                      /*!< 0x00000200 */
3529 #define CAN_F6R1_FB9           CAN_F6R1_FB9_Msk                                /*!<Filter bit 9 */
3530 #define CAN_F6R1_FB10_Pos      (10U)
3531 #define CAN_F6R1_FB10_Msk      (0x1UL << CAN_F6R1_FB10_Pos)                     /*!< 0x00000400 */
3532 #define CAN_F6R1_FB10          CAN_F6R1_FB10_Msk                               /*!<Filter bit 10 */
3533 #define CAN_F6R1_FB11_Pos      (11U)
3534 #define CAN_F6R1_FB11_Msk      (0x1UL << CAN_F6R1_FB11_Pos)                     /*!< 0x00000800 */
3535 #define CAN_F6R1_FB11          CAN_F6R1_FB11_Msk                               /*!<Filter bit 11 */
3536 #define CAN_F6R1_FB12_Pos      (12U)
3537 #define CAN_F6R1_FB12_Msk      (0x1UL << CAN_F6R1_FB12_Pos)                     /*!< 0x00001000 */
3538 #define CAN_F6R1_FB12          CAN_F6R1_FB12_Msk                               /*!<Filter bit 12 */
3539 #define CAN_F6R1_FB13_Pos      (13U)
3540 #define CAN_F6R1_FB13_Msk      (0x1UL << CAN_F6R1_FB13_Pos)                     /*!< 0x00002000 */
3541 #define CAN_F6R1_FB13          CAN_F6R1_FB13_Msk                               /*!<Filter bit 13 */
3542 #define CAN_F6R1_FB14_Pos      (14U)
3543 #define CAN_F6R1_FB14_Msk      (0x1UL << CAN_F6R1_FB14_Pos)                     /*!< 0x00004000 */
3544 #define CAN_F6R1_FB14          CAN_F6R1_FB14_Msk                               /*!<Filter bit 14 */
3545 #define CAN_F6R1_FB15_Pos      (15U)
3546 #define CAN_F6R1_FB15_Msk      (0x1UL << CAN_F6R1_FB15_Pos)                     /*!< 0x00008000 */
3547 #define CAN_F6R1_FB15          CAN_F6R1_FB15_Msk                               /*!<Filter bit 15 */
3548 #define CAN_F6R1_FB16_Pos      (16U)
3549 #define CAN_F6R1_FB16_Msk      (0x1UL << CAN_F6R1_FB16_Pos)                     /*!< 0x00010000 */
3550 #define CAN_F6R1_FB16          CAN_F6R1_FB16_Msk                               /*!<Filter bit 16 */
3551 #define CAN_F6R1_FB17_Pos      (17U)
3552 #define CAN_F6R1_FB17_Msk      (0x1UL << CAN_F6R1_FB17_Pos)                     /*!< 0x00020000 */
3553 #define CAN_F6R1_FB17          CAN_F6R1_FB17_Msk                               /*!<Filter bit 17 */
3554 #define CAN_F6R1_FB18_Pos      (18U)
3555 #define CAN_F6R1_FB18_Msk      (0x1UL << CAN_F6R1_FB18_Pos)                     /*!< 0x00040000 */
3556 #define CAN_F6R1_FB18          CAN_F6R1_FB18_Msk                               /*!<Filter bit 18 */
3557 #define CAN_F6R1_FB19_Pos      (19U)
3558 #define CAN_F6R1_FB19_Msk      (0x1UL << CAN_F6R1_FB19_Pos)                     /*!< 0x00080000 */
3559 #define CAN_F6R1_FB19          CAN_F6R1_FB19_Msk                               /*!<Filter bit 19 */
3560 #define CAN_F6R1_FB20_Pos      (20U)
3561 #define CAN_F6R1_FB20_Msk      (0x1UL << CAN_F6R1_FB20_Pos)                     /*!< 0x00100000 */
3562 #define CAN_F6R1_FB20          CAN_F6R1_FB20_Msk                               /*!<Filter bit 20 */
3563 #define CAN_F6R1_FB21_Pos      (21U)
3564 #define CAN_F6R1_FB21_Msk      (0x1UL << CAN_F6R1_FB21_Pos)                     /*!< 0x00200000 */
3565 #define CAN_F6R1_FB21          CAN_F6R1_FB21_Msk                               /*!<Filter bit 21 */
3566 #define CAN_F6R1_FB22_Pos      (22U)
3567 #define CAN_F6R1_FB22_Msk      (0x1UL << CAN_F6R1_FB22_Pos)                     /*!< 0x00400000 */
3568 #define CAN_F6R1_FB22          CAN_F6R1_FB22_Msk                               /*!<Filter bit 22 */
3569 #define CAN_F6R1_FB23_Pos      (23U)
3570 #define CAN_F6R1_FB23_Msk      (0x1UL << CAN_F6R1_FB23_Pos)                     /*!< 0x00800000 */
3571 #define CAN_F6R1_FB23          CAN_F6R1_FB23_Msk                               /*!<Filter bit 23 */
3572 #define CAN_F6R1_FB24_Pos      (24U)
3573 #define CAN_F6R1_FB24_Msk      (0x1UL << CAN_F6R1_FB24_Pos)                     /*!< 0x01000000 */
3574 #define CAN_F6R1_FB24          CAN_F6R1_FB24_Msk                               /*!<Filter bit 24 */
3575 #define CAN_F6R1_FB25_Pos      (25U)
3576 #define CAN_F6R1_FB25_Msk      (0x1UL << CAN_F6R1_FB25_Pos)                     /*!< 0x02000000 */
3577 #define CAN_F6R1_FB25          CAN_F6R1_FB25_Msk                               /*!<Filter bit 25 */
3578 #define CAN_F6R1_FB26_Pos      (26U)
3579 #define CAN_F6R1_FB26_Msk      (0x1UL << CAN_F6R1_FB26_Pos)                     /*!< 0x04000000 */
3580 #define CAN_F6R1_FB26          CAN_F6R1_FB26_Msk                               /*!<Filter bit 26 */
3581 #define CAN_F6R1_FB27_Pos      (27U)
3582 #define CAN_F6R1_FB27_Msk      (0x1UL << CAN_F6R1_FB27_Pos)                     /*!< 0x08000000 */
3583 #define CAN_F6R1_FB27          CAN_F6R1_FB27_Msk                               /*!<Filter bit 27 */
3584 #define CAN_F6R1_FB28_Pos      (28U)
3585 #define CAN_F6R1_FB28_Msk      (0x1UL << CAN_F6R1_FB28_Pos)                     /*!< 0x10000000 */
3586 #define CAN_F6R1_FB28          CAN_F6R1_FB28_Msk                               /*!<Filter bit 28 */
3587 #define CAN_F6R1_FB29_Pos      (29U)
3588 #define CAN_F6R1_FB29_Msk      (0x1UL << CAN_F6R1_FB29_Pos)                     /*!< 0x20000000 */
3589 #define CAN_F6R1_FB29          CAN_F6R1_FB29_Msk                               /*!<Filter bit 29 */
3590 #define CAN_F6R1_FB30_Pos      (30U)
3591 #define CAN_F6R1_FB30_Msk      (0x1UL << CAN_F6R1_FB30_Pos)                     /*!< 0x40000000 */
3592 #define CAN_F6R1_FB30          CAN_F6R1_FB30_Msk                               /*!<Filter bit 30 */
3593 #define CAN_F6R1_FB31_Pos      (31U)
3594 #define CAN_F6R1_FB31_Msk      (0x1UL << CAN_F6R1_FB31_Pos)                     /*!< 0x80000000 */
3595 #define CAN_F6R1_FB31          CAN_F6R1_FB31_Msk                               /*!<Filter bit 31 */
3596 
3597 /*******************  Bit definition for CAN_F7R1 register  *******************/
3598 #define CAN_F7R1_FB0_Pos       (0U)
3599 #define CAN_F7R1_FB0_Msk       (0x1UL << CAN_F7R1_FB0_Pos)                      /*!< 0x00000001 */
3600 #define CAN_F7R1_FB0           CAN_F7R1_FB0_Msk                                /*!<Filter bit 0 */
3601 #define CAN_F7R1_FB1_Pos       (1U)
3602 #define CAN_F7R1_FB1_Msk       (0x1UL << CAN_F7R1_FB1_Pos)                      /*!< 0x00000002 */
3603 #define CAN_F7R1_FB1           CAN_F7R1_FB1_Msk                                /*!<Filter bit 1 */
3604 #define CAN_F7R1_FB2_Pos       (2U)
3605 #define CAN_F7R1_FB2_Msk       (0x1UL << CAN_F7R1_FB2_Pos)                      /*!< 0x00000004 */
3606 #define CAN_F7R1_FB2           CAN_F7R1_FB2_Msk                                /*!<Filter bit 2 */
3607 #define CAN_F7R1_FB3_Pos       (3U)
3608 #define CAN_F7R1_FB3_Msk       (0x1UL << CAN_F7R1_FB3_Pos)                      /*!< 0x00000008 */
3609 #define CAN_F7R1_FB3           CAN_F7R1_FB3_Msk                                /*!<Filter bit 3 */
3610 #define CAN_F7R1_FB4_Pos       (4U)
3611 #define CAN_F7R1_FB4_Msk       (0x1UL << CAN_F7R1_FB4_Pos)                      /*!< 0x00000010 */
3612 #define CAN_F7R1_FB4           CAN_F7R1_FB4_Msk                                /*!<Filter bit 4 */
3613 #define CAN_F7R1_FB5_Pos       (5U)
3614 #define CAN_F7R1_FB5_Msk       (0x1UL << CAN_F7R1_FB5_Pos)                      /*!< 0x00000020 */
3615 #define CAN_F7R1_FB5           CAN_F7R1_FB5_Msk                                /*!<Filter bit 5 */
3616 #define CAN_F7R1_FB6_Pos       (6U)
3617 #define CAN_F7R1_FB6_Msk       (0x1UL << CAN_F7R1_FB6_Pos)                      /*!< 0x00000040 */
3618 #define CAN_F7R1_FB6           CAN_F7R1_FB6_Msk                                /*!<Filter bit 6 */
3619 #define CAN_F7R1_FB7_Pos       (7U)
3620 #define CAN_F7R1_FB7_Msk       (0x1UL << CAN_F7R1_FB7_Pos)                      /*!< 0x00000080 */
3621 #define CAN_F7R1_FB7           CAN_F7R1_FB7_Msk                                /*!<Filter bit 7 */
3622 #define CAN_F7R1_FB8_Pos       (8U)
3623 #define CAN_F7R1_FB8_Msk       (0x1UL << CAN_F7R1_FB8_Pos)                      /*!< 0x00000100 */
3624 #define CAN_F7R1_FB8           CAN_F7R1_FB8_Msk                                /*!<Filter bit 8 */
3625 #define CAN_F7R1_FB9_Pos       (9U)
3626 #define CAN_F7R1_FB9_Msk       (0x1UL << CAN_F7R1_FB9_Pos)                      /*!< 0x00000200 */
3627 #define CAN_F7R1_FB9           CAN_F7R1_FB9_Msk                                /*!<Filter bit 9 */
3628 #define CAN_F7R1_FB10_Pos      (10U)
3629 #define CAN_F7R1_FB10_Msk      (0x1UL << CAN_F7R1_FB10_Pos)                     /*!< 0x00000400 */
3630 #define CAN_F7R1_FB10          CAN_F7R1_FB10_Msk                               /*!<Filter bit 10 */
3631 #define CAN_F7R1_FB11_Pos      (11U)
3632 #define CAN_F7R1_FB11_Msk      (0x1UL << CAN_F7R1_FB11_Pos)                     /*!< 0x00000800 */
3633 #define CAN_F7R1_FB11          CAN_F7R1_FB11_Msk                               /*!<Filter bit 11 */
3634 #define CAN_F7R1_FB12_Pos      (12U)
3635 #define CAN_F7R1_FB12_Msk      (0x1UL << CAN_F7R1_FB12_Pos)                     /*!< 0x00001000 */
3636 #define CAN_F7R1_FB12          CAN_F7R1_FB12_Msk                               /*!<Filter bit 12 */
3637 #define CAN_F7R1_FB13_Pos      (13U)
3638 #define CAN_F7R1_FB13_Msk      (0x1UL << CAN_F7R1_FB13_Pos)                     /*!< 0x00002000 */
3639 #define CAN_F7R1_FB13          CAN_F7R1_FB13_Msk                               /*!<Filter bit 13 */
3640 #define CAN_F7R1_FB14_Pos      (14U)
3641 #define CAN_F7R1_FB14_Msk      (0x1UL << CAN_F7R1_FB14_Pos)                     /*!< 0x00004000 */
3642 #define CAN_F7R1_FB14          CAN_F7R1_FB14_Msk                               /*!<Filter bit 14 */
3643 #define CAN_F7R1_FB15_Pos      (15U)
3644 #define CAN_F7R1_FB15_Msk      (0x1UL << CAN_F7R1_FB15_Pos)                     /*!< 0x00008000 */
3645 #define CAN_F7R1_FB15          CAN_F7R1_FB15_Msk                               /*!<Filter bit 15 */
3646 #define CAN_F7R1_FB16_Pos      (16U)
3647 #define CAN_F7R1_FB16_Msk      (0x1UL << CAN_F7R1_FB16_Pos)                     /*!< 0x00010000 */
3648 #define CAN_F7R1_FB16          CAN_F7R1_FB16_Msk                               /*!<Filter bit 16 */
3649 #define CAN_F7R1_FB17_Pos      (17U)
3650 #define CAN_F7R1_FB17_Msk      (0x1UL << CAN_F7R1_FB17_Pos)                     /*!< 0x00020000 */
3651 #define CAN_F7R1_FB17          CAN_F7R1_FB17_Msk                               /*!<Filter bit 17 */
3652 #define CAN_F7R1_FB18_Pos      (18U)
3653 #define CAN_F7R1_FB18_Msk      (0x1UL << CAN_F7R1_FB18_Pos)                     /*!< 0x00040000 */
3654 #define CAN_F7R1_FB18          CAN_F7R1_FB18_Msk                               /*!<Filter bit 18 */
3655 #define CAN_F7R1_FB19_Pos      (19U)
3656 #define CAN_F7R1_FB19_Msk      (0x1UL << CAN_F7R1_FB19_Pos)                     /*!< 0x00080000 */
3657 #define CAN_F7R1_FB19          CAN_F7R1_FB19_Msk                               /*!<Filter bit 19 */
3658 #define CAN_F7R1_FB20_Pos      (20U)
3659 #define CAN_F7R1_FB20_Msk      (0x1UL << CAN_F7R1_FB20_Pos)                     /*!< 0x00100000 */
3660 #define CAN_F7R1_FB20          CAN_F7R1_FB20_Msk                               /*!<Filter bit 20 */
3661 #define CAN_F7R1_FB21_Pos      (21U)
3662 #define CAN_F7R1_FB21_Msk      (0x1UL << CAN_F7R1_FB21_Pos)                     /*!< 0x00200000 */
3663 #define CAN_F7R1_FB21          CAN_F7R1_FB21_Msk                               /*!<Filter bit 21 */
3664 #define CAN_F7R1_FB22_Pos      (22U)
3665 #define CAN_F7R1_FB22_Msk      (0x1UL << CAN_F7R1_FB22_Pos)                     /*!< 0x00400000 */
3666 #define CAN_F7R1_FB22          CAN_F7R1_FB22_Msk                               /*!<Filter bit 22 */
3667 #define CAN_F7R1_FB23_Pos      (23U)
3668 #define CAN_F7R1_FB23_Msk      (0x1UL << CAN_F7R1_FB23_Pos)                     /*!< 0x00800000 */
3669 #define CAN_F7R1_FB23          CAN_F7R1_FB23_Msk                               /*!<Filter bit 23 */
3670 #define CAN_F7R1_FB24_Pos      (24U)
3671 #define CAN_F7R1_FB24_Msk      (0x1UL << CAN_F7R1_FB24_Pos)                     /*!< 0x01000000 */
3672 #define CAN_F7R1_FB24          CAN_F7R1_FB24_Msk                               /*!<Filter bit 24 */
3673 #define CAN_F7R1_FB25_Pos      (25U)
3674 #define CAN_F7R1_FB25_Msk      (0x1UL << CAN_F7R1_FB25_Pos)                     /*!< 0x02000000 */
3675 #define CAN_F7R1_FB25          CAN_F7R1_FB25_Msk                               /*!<Filter bit 25 */
3676 #define CAN_F7R1_FB26_Pos      (26U)
3677 #define CAN_F7R1_FB26_Msk      (0x1UL << CAN_F7R1_FB26_Pos)                     /*!< 0x04000000 */
3678 #define CAN_F7R1_FB26          CAN_F7R1_FB26_Msk                               /*!<Filter bit 26 */
3679 #define CAN_F7R1_FB27_Pos      (27U)
3680 #define CAN_F7R1_FB27_Msk      (0x1UL << CAN_F7R1_FB27_Pos)                     /*!< 0x08000000 */
3681 #define CAN_F7R1_FB27          CAN_F7R1_FB27_Msk                               /*!<Filter bit 27 */
3682 #define CAN_F7R1_FB28_Pos      (28U)
3683 #define CAN_F7R1_FB28_Msk      (0x1UL << CAN_F7R1_FB28_Pos)                     /*!< 0x10000000 */
3684 #define CAN_F7R1_FB28          CAN_F7R1_FB28_Msk                               /*!<Filter bit 28 */
3685 #define CAN_F7R1_FB29_Pos      (29U)
3686 #define CAN_F7R1_FB29_Msk      (0x1UL << CAN_F7R1_FB29_Pos)                     /*!< 0x20000000 */
3687 #define CAN_F7R1_FB29          CAN_F7R1_FB29_Msk                               /*!<Filter bit 29 */
3688 #define CAN_F7R1_FB30_Pos      (30U)
3689 #define CAN_F7R1_FB30_Msk      (0x1UL << CAN_F7R1_FB30_Pos)                     /*!< 0x40000000 */
3690 #define CAN_F7R1_FB30          CAN_F7R1_FB30_Msk                               /*!<Filter bit 30 */
3691 #define CAN_F7R1_FB31_Pos      (31U)
3692 #define CAN_F7R1_FB31_Msk      (0x1UL << CAN_F7R1_FB31_Pos)                     /*!< 0x80000000 */
3693 #define CAN_F7R1_FB31          CAN_F7R1_FB31_Msk                               /*!<Filter bit 31 */
3694 
3695 /*******************  Bit definition for CAN_F8R1 register  *******************/
3696 #define CAN_F8R1_FB0_Pos       (0U)
3697 #define CAN_F8R1_FB0_Msk       (0x1UL << CAN_F8R1_FB0_Pos)                      /*!< 0x00000001 */
3698 #define CAN_F8R1_FB0           CAN_F8R1_FB0_Msk                                /*!<Filter bit 0 */
3699 #define CAN_F8R1_FB1_Pos       (1U)
3700 #define CAN_F8R1_FB1_Msk       (0x1UL << CAN_F8R1_FB1_Pos)                      /*!< 0x00000002 */
3701 #define CAN_F8R1_FB1           CAN_F8R1_FB1_Msk                                /*!<Filter bit 1 */
3702 #define CAN_F8R1_FB2_Pos       (2U)
3703 #define CAN_F8R1_FB2_Msk       (0x1UL << CAN_F8R1_FB2_Pos)                      /*!< 0x00000004 */
3704 #define CAN_F8R1_FB2           CAN_F8R1_FB2_Msk                                /*!<Filter bit 2 */
3705 #define CAN_F8R1_FB3_Pos       (3U)
3706 #define CAN_F8R1_FB3_Msk       (0x1UL << CAN_F8R1_FB3_Pos)                      /*!< 0x00000008 */
3707 #define CAN_F8R1_FB3           CAN_F8R1_FB3_Msk                                /*!<Filter bit 3 */
3708 #define CAN_F8R1_FB4_Pos       (4U)
3709 #define CAN_F8R1_FB4_Msk       (0x1UL << CAN_F8R1_FB4_Pos)                      /*!< 0x00000010 */
3710 #define CAN_F8R1_FB4           CAN_F8R1_FB4_Msk                                /*!<Filter bit 4 */
3711 #define CAN_F8R1_FB5_Pos       (5U)
3712 #define CAN_F8R1_FB5_Msk       (0x1UL << CAN_F8R1_FB5_Pos)                      /*!< 0x00000020 */
3713 #define CAN_F8R1_FB5           CAN_F8R1_FB5_Msk                                /*!<Filter bit 5 */
3714 #define CAN_F8R1_FB6_Pos       (6U)
3715 #define CAN_F8R1_FB6_Msk       (0x1UL << CAN_F8R1_FB6_Pos)                      /*!< 0x00000040 */
3716 #define CAN_F8R1_FB6           CAN_F8R1_FB6_Msk                                /*!<Filter bit 6 */
3717 #define CAN_F8R1_FB7_Pos       (7U)
3718 #define CAN_F8R1_FB7_Msk       (0x1UL << CAN_F8R1_FB7_Pos)                      /*!< 0x00000080 */
3719 #define CAN_F8R1_FB7           CAN_F8R1_FB7_Msk                                /*!<Filter bit 7 */
3720 #define CAN_F8R1_FB8_Pos       (8U)
3721 #define CAN_F8R1_FB8_Msk       (0x1UL << CAN_F8R1_FB8_Pos)                      /*!< 0x00000100 */
3722 #define CAN_F8R1_FB8           CAN_F8R1_FB8_Msk                                /*!<Filter bit 8 */
3723 #define CAN_F8R1_FB9_Pos       (9U)
3724 #define CAN_F8R1_FB9_Msk       (0x1UL << CAN_F8R1_FB9_Pos)                      /*!< 0x00000200 */
3725 #define CAN_F8R1_FB9           CAN_F8R1_FB9_Msk                                /*!<Filter bit 9 */
3726 #define CAN_F8R1_FB10_Pos      (10U)
3727 #define CAN_F8R1_FB10_Msk      (0x1UL << CAN_F8R1_FB10_Pos)                     /*!< 0x00000400 */
3728 #define CAN_F8R1_FB10          CAN_F8R1_FB10_Msk                               /*!<Filter bit 10 */
3729 #define CAN_F8R1_FB11_Pos      (11U)
3730 #define CAN_F8R1_FB11_Msk      (0x1UL << CAN_F8R1_FB11_Pos)                     /*!< 0x00000800 */
3731 #define CAN_F8R1_FB11          CAN_F8R1_FB11_Msk                               /*!<Filter bit 11 */
3732 #define CAN_F8R1_FB12_Pos      (12U)
3733 #define CAN_F8R1_FB12_Msk      (0x1UL << CAN_F8R1_FB12_Pos)                     /*!< 0x00001000 */
3734 #define CAN_F8R1_FB12          CAN_F8R1_FB12_Msk                               /*!<Filter bit 12 */
3735 #define CAN_F8R1_FB13_Pos      (13U)
3736 #define CAN_F8R1_FB13_Msk      (0x1UL << CAN_F8R1_FB13_Pos)                     /*!< 0x00002000 */
3737 #define CAN_F8R1_FB13          CAN_F8R1_FB13_Msk                               /*!<Filter bit 13 */
3738 #define CAN_F8R1_FB14_Pos      (14U)
3739 #define CAN_F8R1_FB14_Msk      (0x1UL << CAN_F8R1_FB14_Pos)                     /*!< 0x00004000 */
3740 #define CAN_F8R1_FB14          CAN_F8R1_FB14_Msk                               /*!<Filter bit 14 */
3741 #define CAN_F8R1_FB15_Pos      (15U)
3742 #define CAN_F8R1_FB15_Msk      (0x1UL << CAN_F8R1_FB15_Pos)                     /*!< 0x00008000 */
3743 #define CAN_F8R1_FB15          CAN_F8R1_FB15_Msk                               /*!<Filter bit 15 */
3744 #define CAN_F8R1_FB16_Pos      (16U)
3745 #define CAN_F8R1_FB16_Msk      (0x1UL << CAN_F8R1_FB16_Pos)                     /*!< 0x00010000 */
3746 #define CAN_F8R1_FB16          CAN_F8R1_FB16_Msk                               /*!<Filter bit 16 */
3747 #define CAN_F8R1_FB17_Pos      (17U)
3748 #define CAN_F8R1_FB17_Msk      (0x1UL << CAN_F8R1_FB17_Pos)                     /*!< 0x00020000 */
3749 #define CAN_F8R1_FB17          CAN_F8R1_FB17_Msk                               /*!<Filter bit 17 */
3750 #define CAN_F8R1_FB18_Pos      (18U)
3751 #define CAN_F8R1_FB18_Msk      (0x1UL << CAN_F8R1_FB18_Pos)                     /*!< 0x00040000 */
3752 #define CAN_F8R1_FB18          CAN_F8R1_FB18_Msk                               /*!<Filter bit 18 */
3753 #define CAN_F8R1_FB19_Pos      (19U)
3754 #define CAN_F8R1_FB19_Msk      (0x1UL << CAN_F8R1_FB19_Pos)                     /*!< 0x00080000 */
3755 #define CAN_F8R1_FB19          CAN_F8R1_FB19_Msk                               /*!<Filter bit 19 */
3756 #define CAN_F8R1_FB20_Pos      (20U)
3757 #define CAN_F8R1_FB20_Msk      (0x1UL << CAN_F8R1_FB20_Pos)                     /*!< 0x00100000 */
3758 #define CAN_F8R1_FB20          CAN_F8R1_FB20_Msk                               /*!<Filter bit 20 */
3759 #define CAN_F8R1_FB21_Pos      (21U)
3760 #define CAN_F8R1_FB21_Msk      (0x1UL << CAN_F8R1_FB21_Pos)                     /*!< 0x00200000 */
3761 #define CAN_F8R1_FB21          CAN_F8R1_FB21_Msk                               /*!<Filter bit 21 */
3762 #define CAN_F8R1_FB22_Pos      (22U)
3763 #define CAN_F8R1_FB22_Msk      (0x1UL << CAN_F8R1_FB22_Pos)                     /*!< 0x00400000 */
3764 #define CAN_F8R1_FB22          CAN_F8R1_FB22_Msk                               /*!<Filter bit 22 */
3765 #define CAN_F8R1_FB23_Pos      (23U)
3766 #define CAN_F8R1_FB23_Msk      (0x1UL << CAN_F8R1_FB23_Pos)                     /*!< 0x00800000 */
3767 #define CAN_F8R1_FB23          CAN_F8R1_FB23_Msk                               /*!<Filter bit 23 */
3768 #define CAN_F8R1_FB24_Pos      (24U)
3769 #define CAN_F8R1_FB24_Msk      (0x1UL << CAN_F8R1_FB24_Pos)                     /*!< 0x01000000 */
3770 #define CAN_F8R1_FB24          CAN_F8R1_FB24_Msk                               /*!<Filter bit 24 */
3771 #define CAN_F8R1_FB25_Pos      (25U)
3772 #define CAN_F8R1_FB25_Msk      (0x1UL << CAN_F8R1_FB25_Pos)                     /*!< 0x02000000 */
3773 #define CAN_F8R1_FB25          CAN_F8R1_FB25_Msk                               /*!<Filter bit 25 */
3774 #define CAN_F8R1_FB26_Pos      (26U)
3775 #define CAN_F8R1_FB26_Msk      (0x1UL << CAN_F8R1_FB26_Pos)                     /*!< 0x04000000 */
3776 #define CAN_F8R1_FB26          CAN_F8R1_FB26_Msk                               /*!<Filter bit 26 */
3777 #define CAN_F8R1_FB27_Pos      (27U)
3778 #define CAN_F8R1_FB27_Msk      (0x1UL << CAN_F8R1_FB27_Pos)                     /*!< 0x08000000 */
3779 #define CAN_F8R1_FB27          CAN_F8R1_FB27_Msk                               /*!<Filter bit 27 */
3780 #define CAN_F8R1_FB28_Pos      (28U)
3781 #define CAN_F8R1_FB28_Msk      (0x1UL << CAN_F8R1_FB28_Pos)                     /*!< 0x10000000 */
3782 #define CAN_F8R1_FB28          CAN_F8R1_FB28_Msk                               /*!<Filter bit 28 */
3783 #define CAN_F8R1_FB29_Pos      (29U)
3784 #define CAN_F8R1_FB29_Msk      (0x1UL << CAN_F8R1_FB29_Pos)                     /*!< 0x20000000 */
3785 #define CAN_F8R1_FB29          CAN_F8R1_FB29_Msk                               /*!<Filter bit 29 */
3786 #define CAN_F8R1_FB30_Pos      (30U)
3787 #define CAN_F8R1_FB30_Msk      (0x1UL << CAN_F8R1_FB30_Pos)                     /*!< 0x40000000 */
3788 #define CAN_F8R1_FB30          CAN_F8R1_FB30_Msk                               /*!<Filter bit 30 */
3789 #define CAN_F8R1_FB31_Pos      (31U)
3790 #define CAN_F8R1_FB31_Msk      (0x1UL << CAN_F8R1_FB31_Pos)                     /*!< 0x80000000 */
3791 #define CAN_F8R1_FB31          CAN_F8R1_FB31_Msk                               /*!<Filter bit 31 */
3792 
3793 /*******************  Bit definition for CAN_F9R1 register  *******************/
3794 #define CAN_F9R1_FB0_Pos       (0U)
3795 #define CAN_F9R1_FB0_Msk       (0x1UL << CAN_F9R1_FB0_Pos)                      /*!< 0x00000001 */
3796 #define CAN_F9R1_FB0           CAN_F9R1_FB0_Msk                                /*!<Filter bit 0 */
3797 #define CAN_F9R1_FB1_Pos       (1U)
3798 #define CAN_F9R1_FB1_Msk       (0x1UL << CAN_F9R1_FB1_Pos)                      /*!< 0x00000002 */
3799 #define CAN_F9R1_FB1           CAN_F9R1_FB1_Msk                                /*!<Filter bit 1 */
3800 #define CAN_F9R1_FB2_Pos       (2U)
3801 #define CAN_F9R1_FB2_Msk       (0x1UL << CAN_F9R1_FB2_Pos)                      /*!< 0x00000004 */
3802 #define CAN_F9R1_FB2           CAN_F9R1_FB2_Msk                                /*!<Filter bit 2 */
3803 #define CAN_F9R1_FB3_Pos       (3U)
3804 #define CAN_F9R1_FB3_Msk       (0x1UL << CAN_F9R1_FB3_Pos)                      /*!< 0x00000008 */
3805 #define CAN_F9R1_FB3           CAN_F9R1_FB3_Msk                                /*!<Filter bit 3 */
3806 #define CAN_F9R1_FB4_Pos       (4U)
3807 #define CAN_F9R1_FB4_Msk       (0x1UL << CAN_F9R1_FB4_Pos)                      /*!< 0x00000010 */
3808 #define CAN_F9R1_FB4           CAN_F9R1_FB4_Msk                                /*!<Filter bit 4 */
3809 #define CAN_F9R1_FB5_Pos       (5U)
3810 #define CAN_F9R1_FB5_Msk       (0x1UL << CAN_F9R1_FB5_Pos)                      /*!< 0x00000020 */
3811 #define CAN_F9R1_FB5           CAN_F9R1_FB5_Msk                                /*!<Filter bit 5 */
3812 #define CAN_F9R1_FB6_Pos       (6U)
3813 #define CAN_F9R1_FB6_Msk       (0x1UL << CAN_F9R1_FB6_Pos)                      /*!< 0x00000040 */
3814 #define CAN_F9R1_FB6           CAN_F9R1_FB6_Msk                                /*!<Filter bit 6 */
3815 #define CAN_F9R1_FB7_Pos       (7U)
3816 #define CAN_F9R1_FB7_Msk       (0x1UL << CAN_F9R1_FB7_Pos)                      /*!< 0x00000080 */
3817 #define CAN_F9R1_FB7           CAN_F9R1_FB7_Msk                                /*!<Filter bit 7 */
3818 #define CAN_F9R1_FB8_Pos       (8U)
3819 #define CAN_F9R1_FB8_Msk       (0x1UL << CAN_F9R1_FB8_Pos)                      /*!< 0x00000100 */
3820 #define CAN_F9R1_FB8           CAN_F9R1_FB8_Msk                                /*!<Filter bit 8 */
3821 #define CAN_F9R1_FB9_Pos       (9U)
3822 #define CAN_F9R1_FB9_Msk       (0x1UL << CAN_F9R1_FB9_Pos)                      /*!< 0x00000200 */
3823 #define CAN_F9R1_FB9           CAN_F9R1_FB9_Msk                                /*!<Filter bit 9 */
3824 #define CAN_F9R1_FB10_Pos      (10U)
3825 #define CAN_F9R1_FB10_Msk      (0x1UL << CAN_F9R1_FB10_Pos)                     /*!< 0x00000400 */
3826 #define CAN_F9R1_FB10          CAN_F9R1_FB10_Msk                               /*!<Filter bit 10 */
3827 #define CAN_F9R1_FB11_Pos      (11U)
3828 #define CAN_F9R1_FB11_Msk      (0x1UL << CAN_F9R1_FB11_Pos)                     /*!< 0x00000800 */
3829 #define CAN_F9R1_FB11          CAN_F9R1_FB11_Msk                               /*!<Filter bit 11 */
3830 #define CAN_F9R1_FB12_Pos      (12U)
3831 #define CAN_F9R1_FB12_Msk      (0x1UL << CAN_F9R1_FB12_Pos)                     /*!< 0x00001000 */
3832 #define CAN_F9R1_FB12          CAN_F9R1_FB12_Msk                               /*!<Filter bit 12 */
3833 #define CAN_F9R1_FB13_Pos      (13U)
3834 #define CAN_F9R1_FB13_Msk      (0x1UL << CAN_F9R1_FB13_Pos)                     /*!< 0x00002000 */
3835 #define CAN_F9R1_FB13          CAN_F9R1_FB13_Msk                               /*!<Filter bit 13 */
3836 #define CAN_F9R1_FB14_Pos      (14U)
3837 #define CAN_F9R1_FB14_Msk      (0x1UL << CAN_F9R1_FB14_Pos)                     /*!< 0x00004000 */
3838 #define CAN_F9R1_FB14          CAN_F9R1_FB14_Msk                               /*!<Filter bit 14 */
3839 #define CAN_F9R1_FB15_Pos      (15U)
3840 #define CAN_F9R1_FB15_Msk      (0x1UL << CAN_F9R1_FB15_Pos)                     /*!< 0x00008000 */
3841 #define CAN_F9R1_FB15          CAN_F9R1_FB15_Msk                               /*!<Filter bit 15 */
3842 #define CAN_F9R1_FB16_Pos      (16U)
3843 #define CAN_F9R1_FB16_Msk      (0x1UL << CAN_F9R1_FB16_Pos)                     /*!< 0x00010000 */
3844 #define CAN_F9R1_FB16          CAN_F9R1_FB16_Msk                               /*!<Filter bit 16 */
3845 #define CAN_F9R1_FB17_Pos      (17U)
3846 #define CAN_F9R1_FB17_Msk      (0x1UL << CAN_F9R1_FB17_Pos)                     /*!< 0x00020000 */
3847 #define CAN_F9R1_FB17          CAN_F9R1_FB17_Msk                               /*!<Filter bit 17 */
3848 #define CAN_F9R1_FB18_Pos      (18U)
3849 #define CAN_F9R1_FB18_Msk      (0x1UL << CAN_F9R1_FB18_Pos)                     /*!< 0x00040000 */
3850 #define CAN_F9R1_FB18          CAN_F9R1_FB18_Msk                               /*!<Filter bit 18 */
3851 #define CAN_F9R1_FB19_Pos      (19U)
3852 #define CAN_F9R1_FB19_Msk      (0x1UL << CAN_F9R1_FB19_Pos)                     /*!< 0x00080000 */
3853 #define CAN_F9R1_FB19          CAN_F9R1_FB19_Msk                               /*!<Filter bit 19 */
3854 #define CAN_F9R1_FB20_Pos      (20U)
3855 #define CAN_F9R1_FB20_Msk      (0x1UL << CAN_F9R1_FB20_Pos)                     /*!< 0x00100000 */
3856 #define CAN_F9R1_FB20          CAN_F9R1_FB20_Msk                               /*!<Filter bit 20 */
3857 #define CAN_F9R1_FB21_Pos      (21U)
3858 #define CAN_F9R1_FB21_Msk      (0x1UL << CAN_F9R1_FB21_Pos)                     /*!< 0x00200000 */
3859 #define CAN_F9R1_FB21          CAN_F9R1_FB21_Msk                               /*!<Filter bit 21 */
3860 #define CAN_F9R1_FB22_Pos      (22U)
3861 #define CAN_F9R1_FB22_Msk      (0x1UL << CAN_F9R1_FB22_Pos)                     /*!< 0x00400000 */
3862 #define CAN_F9R1_FB22          CAN_F9R1_FB22_Msk                               /*!<Filter bit 22 */
3863 #define CAN_F9R1_FB23_Pos      (23U)
3864 #define CAN_F9R1_FB23_Msk      (0x1UL << CAN_F9R1_FB23_Pos)                     /*!< 0x00800000 */
3865 #define CAN_F9R1_FB23          CAN_F9R1_FB23_Msk                               /*!<Filter bit 23 */
3866 #define CAN_F9R1_FB24_Pos      (24U)
3867 #define CAN_F9R1_FB24_Msk      (0x1UL << CAN_F9R1_FB24_Pos)                     /*!< 0x01000000 */
3868 #define CAN_F9R1_FB24          CAN_F9R1_FB24_Msk                               /*!<Filter bit 24 */
3869 #define CAN_F9R1_FB25_Pos      (25U)
3870 #define CAN_F9R1_FB25_Msk      (0x1UL << CAN_F9R1_FB25_Pos)                     /*!< 0x02000000 */
3871 #define CAN_F9R1_FB25          CAN_F9R1_FB25_Msk                               /*!<Filter bit 25 */
3872 #define CAN_F9R1_FB26_Pos      (26U)
3873 #define CAN_F9R1_FB26_Msk      (0x1UL << CAN_F9R1_FB26_Pos)                     /*!< 0x04000000 */
3874 #define CAN_F9R1_FB26          CAN_F9R1_FB26_Msk                               /*!<Filter bit 26 */
3875 #define CAN_F9R1_FB27_Pos      (27U)
3876 #define CAN_F9R1_FB27_Msk      (0x1UL << CAN_F9R1_FB27_Pos)                     /*!< 0x08000000 */
3877 #define CAN_F9R1_FB27          CAN_F9R1_FB27_Msk                               /*!<Filter bit 27 */
3878 #define CAN_F9R1_FB28_Pos      (28U)
3879 #define CAN_F9R1_FB28_Msk      (0x1UL << CAN_F9R1_FB28_Pos)                     /*!< 0x10000000 */
3880 #define CAN_F9R1_FB28          CAN_F9R1_FB28_Msk                               /*!<Filter bit 28 */
3881 #define CAN_F9R1_FB29_Pos      (29U)
3882 #define CAN_F9R1_FB29_Msk      (0x1UL << CAN_F9R1_FB29_Pos)                     /*!< 0x20000000 */
3883 #define CAN_F9R1_FB29          CAN_F9R1_FB29_Msk                               /*!<Filter bit 29 */
3884 #define CAN_F9R1_FB30_Pos      (30U)
3885 #define CAN_F9R1_FB30_Msk      (0x1UL << CAN_F9R1_FB30_Pos)                     /*!< 0x40000000 */
3886 #define CAN_F9R1_FB30          CAN_F9R1_FB30_Msk                               /*!<Filter bit 30 */
3887 #define CAN_F9R1_FB31_Pos      (31U)
3888 #define CAN_F9R1_FB31_Msk      (0x1UL << CAN_F9R1_FB31_Pos)                     /*!< 0x80000000 */
3889 #define CAN_F9R1_FB31          CAN_F9R1_FB31_Msk                               /*!<Filter bit 31 */
3890 
3891 /*******************  Bit definition for CAN_F10R1 register  ******************/
3892 #define CAN_F10R1_FB0_Pos      (0U)
3893 #define CAN_F10R1_FB0_Msk      (0x1UL << CAN_F10R1_FB0_Pos)                     /*!< 0x00000001 */
3894 #define CAN_F10R1_FB0          CAN_F10R1_FB0_Msk                               /*!<Filter bit 0 */
3895 #define CAN_F10R1_FB1_Pos      (1U)
3896 #define CAN_F10R1_FB1_Msk      (0x1UL << CAN_F10R1_FB1_Pos)                     /*!< 0x00000002 */
3897 #define CAN_F10R1_FB1          CAN_F10R1_FB1_Msk                               /*!<Filter bit 1 */
3898 #define CAN_F10R1_FB2_Pos      (2U)
3899 #define CAN_F10R1_FB2_Msk      (0x1UL << CAN_F10R1_FB2_Pos)                     /*!< 0x00000004 */
3900 #define CAN_F10R1_FB2          CAN_F10R1_FB2_Msk                               /*!<Filter bit 2 */
3901 #define CAN_F10R1_FB3_Pos      (3U)
3902 #define CAN_F10R1_FB3_Msk      (0x1UL << CAN_F10R1_FB3_Pos)                     /*!< 0x00000008 */
3903 #define CAN_F10R1_FB3          CAN_F10R1_FB3_Msk                               /*!<Filter bit 3 */
3904 #define CAN_F10R1_FB4_Pos      (4U)
3905 #define CAN_F10R1_FB4_Msk      (0x1UL << CAN_F10R1_FB4_Pos)                     /*!< 0x00000010 */
3906 #define CAN_F10R1_FB4          CAN_F10R1_FB4_Msk                               /*!<Filter bit 4 */
3907 #define CAN_F10R1_FB5_Pos      (5U)
3908 #define CAN_F10R1_FB5_Msk      (0x1UL << CAN_F10R1_FB5_Pos)                     /*!< 0x00000020 */
3909 #define CAN_F10R1_FB5          CAN_F10R1_FB5_Msk                               /*!<Filter bit 5 */
3910 #define CAN_F10R1_FB6_Pos      (6U)
3911 #define CAN_F10R1_FB6_Msk      (0x1UL << CAN_F10R1_FB6_Pos)                     /*!< 0x00000040 */
3912 #define CAN_F10R1_FB6          CAN_F10R1_FB6_Msk                               /*!<Filter bit 6 */
3913 #define CAN_F10R1_FB7_Pos      (7U)
3914 #define CAN_F10R1_FB7_Msk      (0x1UL << CAN_F10R1_FB7_Pos)                     /*!< 0x00000080 */
3915 #define CAN_F10R1_FB7          CAN_F10R1_FB7_Msk                               /*!<Filter bit 7 */
3916 #define CAN_F10R1_FB8_Pos      (8U)
3917 #define CAN_F10R1_FB8_Msk      (0x1UL << CAN_F10R1_FB8_Pos)                     /*!< 0x00000100 */
3918 #define CAN_F10R1_FB8          CAN_F10R1_FB8_Msk                               /*!<Filter bit 8 */
3919 #define CAN_F10R1_FB9_Pos      (9U)
3920 #define CAN_F10R1_FB9_Msk      (0x1UL << CAN_F10R1_FB9_Pos)                     /*!< 0x00000200 */
3921 #define CAN_F10R1_FB9          CAN_F10R1_FB9_Msk                               /*!<Filter bit 9 */
3922 #define CAN_F10R1_FB10_Pos     (10U)
3923 #define CAN_F10R1_FB10_Msk     (0x1UL << CAN_F10R1_FB10_Pos)                    /*!< 0x00000400 */
3924 #define CAN_F10R1_FB10         CAN_F10R1_FB10_Msk                              /*!<Filter bit 10 */
3925 #define CAN_F10R1_FB11_Pos     (11U)
3926 #define CAN_F10R1_FB11_Msk     (0x1UL << CAN_F10R1_FB11_Pos)                    /*!< 0x00000800 */
3927 #define CAN_F10R1_FB11         CAN_F10R1_FB11_Msk                              /*!<Filter bit 11 */
3928 #define CAN_F10R1_FB12_Pos     (12U)
3929 #define CAN_F10R1_FB12_Msk     (0x1UL << CAN_F10R1_FB12_Pos)                    /*!< 0x00001000 */
3930 #define CAN_F10R1_FB12         CAN_F10R1_FB12_Msk                              /*!<Filter bit 12 */
3931 #define CAN_F10R1_FB13_Pos     (13U)
3932 #define CAN_F10R1_FB13_Msk     (0x1UL << CAN_F10R1_FB13_Pos)                    /*!< 0x00002000 */
3933 #define CAN_F10R1_FB13         CAN_F10R1_FB13_Msk                              /*!<Filter bit 13 */
3934 #define CAN_F10R1_FB14_Pos     (14U)
3935 #define CAN_F10R1_FB14_Msk     (0x1UL << CAN_F10R1_FB14_Pos)                    /*!< 0x00004000 */
3936 #define CAN_F10R1_FB14         CAN_F10R1_FB14_Msk                              /*!<Filter bit 14 */
3937 #define CAN_F10R1_FB15_Pos     (15U)
3938 #define CAN_F10R1_FB15_Msk     (0x1UL << CAN_F10R1_FB15_Pos)                    /*!< 0x00008000 */
3939 #define CAN_F10R1_FB15         CAN_F10R1_FB15_Msk                              /*!<Filter bit 15 */
3940 #define CAN_F10R1_FB16_Pos     (16U)
3941 #define CAN_F10R1_FB16_Msk     (0x1UL << CAN_F10R1_FB16_Pos)                    /*!< 0x00010000 */
3942 #define CAN_F10R1_FB16         CAN_F10R1_FB16_Msk                              /*!<Filter bit 16 */
3943 #define CAN_F10R1_FB17_Pos     (17U)
3944 #define CAN_F10R1_FB17_Msk     (0x1UL << CAN_F10R1_FB17_Pos)                    /*!< 0x00020000 */
3945 #define CAN_F10R1_FB17         CAN_F10R1_FB17_Msk                              /*!<Filter bit 17 */
3946 #define CAN_F10R1_FB18_Pos     (18U)
3947 #define CAN_F10R1_FB18_Msk     (0x1UL << CAN_F10R1_FB18_Pos)                    /*!< 0x00040000 */
3948 #define CAN_F10R1_FB18         CAN_F10R1_FB18_Msk                              /*!<Filter bit 18 */
3949 #define CAN_F10R1_FB19_Pos     (19U)
3950 #define CAN_F10R1_FB19_Msk     (0x1UL << CAN_F10R1_FB19_Pos)                    /*!< 0x00080000 */
3951 #define CAN_F10R1_FB19         CAN_F10R1_FB19_Msk                              /*!<Filter bit 19 */
3952 #define CAN_F10R1_FB20_Pos     (20U)
3953 #define CAN_F10R1_FB20_Msk     (0x1UL << CAN_F10R1_FB20_Pos)                    /*!< 0x00100000 */
3954 #define CAN_F10R1_FB20         CAN_F10R1_FB20_Msk                              /*!<Filter bit 20 */
3955 #define CAN_F10R1_FB21_Pos     (21U)
3956 #define CAN_F10R1_FB21_Msk     (0x1UL << CAN_F10R1_FB21_Pos)                    /*!< 0x00200000 */
3957 #define CAN_F10R1_FB21         CAN_F10R1_FB21_Msk                              /*!<Filter bit 21 */
3958 #define CAN_F10R1_FB22_Pos     (22U)
3959 #define CAN_F10R1_FB22_Msk     (0x1UL << CAN_F10R1_FB22_Pos)                    /*!< 0x00400000 */
3960 #define CAN_F10R1_FB22         CAN_F10R1_FB22_Msk                              /*!<Filter bit 22 */
3961 #define CAN_F10R1_FB23_Pos     (23U)
3962 #define CAN_F10R1_FB23_Msk     (0x1UL << CAN_F10R1_FB23_Pos)                    /*!< 0x00800000 */
3963 #define CAN_F10R1_FB23         CAN_F10R1_FB23_Msk                              /*!<Filter bit 23 */
3964 #define CAN_F10R1_FB24_Pos     (24U)
3965 #define CAN_F10R1_FB24_Msk     (0x1UL << CAN_F10R1_FB24_Pos)                    /*!< 0x01000000 */
3966 #define CAN_F10R1_FB24         CAN_F10R1_FB24_Msk                              /*!<Filter bit 24 */
3967 #define CAN_F10R1_FB25_Pos     (25U)
3968 #define CAN_F10R1_FB25_Msk     (0x1UL << CAN_F10R1_FB25_Pos)                    /*!< 0x02000000 */
3969 #define CAN_F10R1_FB25         CAN_F10R1_FB25_Msk                              /*!<Filter bit 25 */
3970 #define CAN_F10R1_FB26_Pos     (26U)
3971 #define CAN_F10R1_FB26_Msk     (0x1UL << CAN_F10R1_FB26_Pos)                    /*!< 0x04000000 */
3972 #define CAN_F10R1_FB26         CAN_F10R1_FB26_Msk                              /*!<Filter bit 26 */
3973 #define CAN_F10R1_FB27_Pos     (27U)
3974 #define CAN_F10R1_FB27_Msk     (0x1UL << CAN_F10R1_FB27_Pos)                    /*!< 0x08000000 */
3975 #define CAN_F10R1_FB27         CAN_F10R1_FB27_Msk                              /*!<Filter bit 27 */
3976 #define CAN_F10R1_FB28_Pos     (28U)
3977 #define CAN_F10R1_FB28_Msk     (0x1UL << CAN_F10R1_FB28_Pos)                    /*!< 0x10000000 */
3978 #define CAN_F10R1_FB28         CAN_F10R1_FB28_Msk                              /*!<Filter bit 28 */
3979 #define CAN_F10R1_FB29_Pos     (29U)
3980 #define CAN_F10R1_FB29_Msk     (0x1UL << CAN_F10R1_FB29_Pos)                    /*!< 0x20000000 */
3981 #define CAN_F10R1_FB29         CAN_F10R1_FB29_Msk                              /*!<Filter bit 29 */
3982 #define CAN_F10R1_FB30_Pos     (30U)
3983 #define CAN_F10R1_FB30_Msk     (0x1UL << CAN_F10R1_FB30_Pos)                    /*!< 0x40000000 */
3984 #define CAN_F10R1_FB30         CAN_F10R1_FB30_Msk                              /*!<Filter bit 30 */
3985 #define CAN_F10R1_FB31_Pos     (31U)
3986 #define CAN_F10R1_FB31_Msk     (0x1UL << CAN_F10R1_FB31_Pos)                    /*!< 0x80000000 */
3987 #define CAN_F10R1_FB31         CAN_F10R1_FB31_Msk                              /*!<Filter bit 31 */
3988 
3989 /*******************  Bit definition for CAN_F11R1 register  ******************/
3990 #define CAN_F11R1_FB0_Pos      (0U)
3991 #define CAN_F11R1_FB0_Msk      (0x1UL << CAN_F11R1_FB0_Pos)                     /*!< 0x00000001 */
3992 #define CAN_F11R1_FB0          CAN_F11R1_FB0_Msk                               /*!<Filter bit 0 */
3993 #define CAN_F11R1_FB1_Pos      (1U)
3994 #define CAN_F11R1_FB1_Msk      (0x1UL << CAN_F11R1_FB1_Pos)                     /*!< 0x00000002 */
3995 #define CAN_F11R1_FB1          CAN_F11R1_FB1_Msk                               /*!<Filter bit 1 */
3996 #define CAN_F11R1_FB2_Pos      (2U)
3997 #define CAN_F11R1_FB2_Msk      (0x1UL << CAN_F11R1_FB2_Pos)                     /*!< 0x00000004 */
3998 #define CAN_F11R1_FB2          CAN_F11R1_FB2_Msk                               /*!<Filter bit 2 */
3999 #define CAN_F11R1_FB3_Pos      (3U)
4000 #define CAN_F11R1_FB3_Msk      (0x1UL << CAN_F11R1_FB3_Pos)                     /*!< 0x00000008 */
4001 #define CAN_F11R1_FB3          CAN_F11R1_FB3_Msk                               /*!<Filter bit 3 */
4002 #define CAN_F11R1_FB4_Pos      (4U)
4003 #define CAN_F11R1_FB4_Msk      (0x1UL << CAN_F11R1_FB4_Pos)                     /*!< 0x00000010 */
4004 #define CAN_F11R1_FB4          CAN_F11R1_FB4_Msk                               /*!<Filter bit 4 */
4005 #define CAN_F11R1_FB5_Pos      (5U)
4006 #define CAN_F11R1_FB5_Msk      (0x1UL << CAN_F11R1_FB5_Pos)                     /*!< 0x00000020 */
4007 #define CAN_F11R1_FB5          CAN_F11R1_FB5_Msk                               /*!<Filter bit 5 */
4008 #define CAN_F11R1_FB6_Pos      (6U)
4009 #define CAN_F11R1_FB6_Msk      (0x1UL << CAN_F11R1_FB6_Pos)                     /*!< 0x00000040 */
4010 #define CAN_F11R1_FB6          CAN_F11R1_FB6_Msk                               /*!<Filter bit 6 */
4011 #define CAN_F11R1_FB7_Pos      (7U)
4012 #define CAN_F11R1_FB7_Msk      (0x1UL << CAN_F11R1_FB7_Pos)                     /*!< 0x00000080 */
4013 #define CAN_F11R1_FB7          CAN_F11R1_FB7_Msk                               /*!<Filter bit 7 */
4014 #define CAN_F11R1_FB8_Pos      (8U)
4015 #define CAN_F11R1_FB8_Msk      (0x1UL << CAN_F11R1_FB8_Pos)                     /*!< 0x00000100 */
4016 #define CAN_F11R1_FB8          CAN_F11R1_FB8_Msk                               /*!<Filter bit 8 */
4017 #define CAN_F11R1_FB9_Pos      (9U)
4018 #define CAN_F11R1_FB9_Msk      (0x1UL << CAN_F11R1_FB9_Pos)                     /*!< 0x00000200 */
4019 #define CAN_F11R1_FB9          CAN_F11R1_FB9_Msk                               /*!<Filter bit 9 */
4020 #define CAN_F11R1_FB10_Pos     (10U)
4021 #define CAN_F11R1_FB10_Msk     (0x1UL << CAN_F11R1_FB10_Pos)                    /*!< 0x00000400 */
4022 #define CAN_F11R1_FB10         CAN_F11R1_FB10_Msk                              /*!<Filter bit 10 */
4023 #define CAN_F11R1_FB11_Pos     (11U)
4024 #define CAN_F11R1_FB11_Msk     (0x1UL << CAN_F11R1_FB11_Pos)                    /*!< 0x00000800 */
4025 #define CAN_F11R1_FB11         CAN_F11R1_FB11_Msk                              /*!<Filter bit 11 */
4026 #define CAN_F11R1_FB12_Pos     (12U)
4027 #define CAN_F11R1_FB12_Msk     (0x1UL << CAN_F11R1_FB12_Pos)                    /*!< 0x00001000 */
4028 #define CAN_F11R1_FB12         CAN_F11R1_FB12_Msk                              /*!<Filter bit 12 */
4029 #define CAN_F11R1_FB13_Pos     (13U)
4030 #define CAN_F11R1_FB13_Msk     (0x1UL << CAN_F11R1_FB13_Pos)                    /*!< 0x00002000 */
4031 #define CAN_F11R1_FB13         CAN_F11R1_FB13_Msk                              /*!<Filter bit 13 */
4032 #define CAN_F11R1_FB14_Pos     (14U)
4033 #define CAN_F11R1_FB14_Msk     (0x1UL << CAN_F11R1_FB14_Pos)                    /*!< 0x00004000 */
4034 #define CAN_F11R1_FB14         CAN_F11R1_FB14_Msk                              /*!<Filter bit 14 */
4035 #define CAN_F11R1_FB15_Pos     (15U)
4036 #define CAN_F11R1_FB15_Msk     (0x1UL << CAN_F11R1_FB15_Pos)                    /*!< 0x00008000 */
4037 #define CAN_F11R1_FB15         CAN_F11R1_FB15_Msk                              /*!<Filter bit 15 */
4038 #define CAN_F11R1_FB16_Pos     (16U)
4039 #define CAN_F11R1_FB16_Msk     (0x1UL << CAN_F11R1_FB16_Pos)                    /*!< 0x00010000 */
4040 #define CAN_F11R1_FB16         CAN_F11R1_FB16_Msk                              /*!<Filter bit 16 */
4041 #define CAN_F11R1_FB17_Pos     (17U)
4042 #define CAN_F11R1_FB17_Msk     (0x1UL << CAN_F11R1_FB17_Pos)                    /*!< 0x00020000 */
4043 #define CAN_F11R1_FB17         CAN_F11R1_FB17_Msk                              /*!<Filter bit 17 */
4044 #define CAN_F11R1_FB18_Pos     (18U)
4045 #define CAN_F11R1_FB18_Msk     (0x1UL << CAN_F11R1_FB18_Pos)                    /*!< 0x00040000 */
4046 #define CAN_F11R1_FB18         CAN_F11R1_FB18_Msk                              /*!<Filter bit 18 */
4047 #define CAN_F11R1_FB19_Pos     (19U)
4048 #define CAN_F11R1_FB19_Msk     (0x1UL << CAN_F11R1_FB19_Pos)                    /*!< 0x00080000 */
4049 #define CAN_F11R1_FB19         CAN_F11R1_FB19_Msk                              /*!<Filter bit 19 */
4050 #define CAN_F11R1_FB20_Pos     (20U)
4051 #define CAN_F11R1_FB20_Msk     (0x1UL << CAN_F11R1_FB20_Pos)                    /*!< 0x00100000 */
4052 #define CAN_F11R1_FB20         CAN_F11R1_FB20_Msk                              /*!<Filter bit 20 */
4053 #define CAN_F11R1_FB21_Pos     (21U)
4054 #define CAN_F11R1_FB21_Msk     (0x1UL << CAN_F11R1_FB21_Pos)                    /*!< 0x00200000 */
4055 #define CAN_F11R1_FB21         CAN_F11R1_FB21_Msk                              /*!<Filter bit 21 */
4056 #define CAN_F11R1_FB22_Pos     (22U)
4057 #define CAN_F11R1_FB22_Msk     (0x1UL << CAN_F11R1_FB22_Pos)                    /*!< 0x00400000 */
4058 #define CAN_F11R1_FB22         CAN_F11R1_FB22_Msk                              /*!<Filter bit 22 */
4059 #define CAN_F11R1_FB23_Pos     (23U)
4060 #define CAN_F11R1_FB23_Msk     (0x1UL << CAN_F11R1_FB23_Pos)                    /*!< 0x00800000 */
4061 #define CAN_F11R1_FB23         CAN_F11R1_FB23_Msk                              /*!<Filter bit 23 */
4062 #define CAN_F11R1_FB24_Pos     (24U)
4063 #define CAN_F11R1_FB24_Msk     (0x1UL << CAN_F11R1_FB24_Pos)                    /*!< 0x01000000 */
4064 #define CAN_F11R1_FB24         CAN_F11R1_FB24_Msk                              /*!<Filter bit 24 */
4065 #define CAN_F11R1_FB25_Pos     (25U)
4066 #define CAN_F11R1_FB25_Msk     (0x1UL << CAN_F11R1_FB25_Pos)                    /*!< 0x02000000 */
4067 #define CAN_F11R1_FB25         CAN_F11R1_FB25_Msk                              /*!<Filter bit 25 */
4068 #define CAN_F11R1_FB26_Pos     (26U)
4069 #define CAN_F11R1_FB26_Msk     (0x1UL << CAN_F11R1_FB26_Pos)                    /*!< 0x04000000 */
4070 #define CAN_F11R1_FB26         CAN_F11R1_FB26_Msk                              /*!<Filter bit 26 */
4071 #define CAN_F11R1_FB27_Pos     (27U)
4072 #define CAN_F11R1_FB27_Msk     (0x1UL << CAN_F11R1_FB27_Pos)                    /*!< 0x08000000 */
4073 #define CAN_F11R1_FB27         CAN_F11R1_FB27_Msk                              /*!<Filter bit 27 */
4074 #define CAN_F11R1_FB28_Pos     (28U)
4075 #define CAN_F11R1_FB28_Msk     (0x1UL << CAN_F11R1_FB28_Pos)                    /*!< 0x10000000 */
4076 #define CAN_F11R1_FB28         CAN_F11R1_FB28_Msk                              /*!<Filter bit 28 */
4077 #define CAN_F11R1_FB29_Pos     (29U)
4078 #define CAN_F11R1_FB29_Msk     (0x1UL << CAN_F11R1_FB29_Pos)                    /*!< 0x20000000 */
4079 #define CAN_F11R1_FB29         CAN_F11R1_FB29_Msk                              /*!<Filter bit 29 */
4080 #define CAN_F11R1_FB30_Pos     (30U)
4081 #define CAN_F11R1_FB30_Msk     (0x1UL << CAN_F11R1_FB30_Pos)                    /*!< 0x40000000 */
4082 #define CAN_F11R1_FB30         CAN_F11R1_FB30_Msk                              /*!<Filter bit 30 */
4083 #define CAN_F11R1_FB31_Pos     (31U)
4084 #define CAN_F11R1_FB31_Msk     (0x1UL << CAN_F11R1_FB31_Pos)                    /*!< 0x80000000 */
4085 #define CAN_F11R1_FB31         CAN_F11R1_FB31_Msk                              /*!<Filter bit 31 */
4086 
4087 /*******************  Bit definition for CAN_F12R1 register  ******************/
4088 #define CAN_F12R1_FB0_Pos      (0U)
4089 #define CAN_F12R1_FB0_Msk      (0x1UL << CAN_F12R1_FB0_Pos)                     /*!< 0x00000001 */
4090 #define CAN_F12R1_FB0          CAN_F12R1_FB0_Msk                               /*!<Filter bit 0 */
4091 #define CAN_F12R1_FB1_Pos      (1U)
4092 #define CAN_F12R1_FB1_Msk      (0x1UL << CAN_F12R1_FB1_Pos)                     /*!< 0x00000002 */
4093 #define CAN_F12R1_FB1          CAN_F12R1_FB1_Msk                               /*!<Filter bit 1 */
4094 #define CAN_F12R1_FB2_Pos      (2U)
4095 #define CAN_F12R1_FB2_Msk      (0x1UL << CAN_F12R1_FB2_Pos)                     /*!< 0x00000004 */
4096 #define CAN_F12R1_FB2          CAN_F12R1_FB2_Msk                               /*!<Filter bit 2 */
4097 #define CAN_F12R1_FB3_Pos      (3U)
4098 #define CAN_F12R1_FB3_Msk      (0x1UL << CAN_F12R1_FB3_Pos)                     /*!< 0x00000008 */
4099 #define CAN_F12R1_FB3          CAN_F12R1_FB3_Msk                               /*!<Filter bit 3 */
4100 #define CAN_F12R1_FB4_Pos      (4U)
4101 #define CAN_F12R1_FB4_Msk      (0x1UL << CAN_F12R1_FB4_Pos)                     /*!< 0x00000010 */
4102 #define CAN_F12R1_FB4          CAN_F12R1_FB4_Msk                               /*!<Filter bit 4 */
4103 #define CAN_F12R1_FB5_Pos      (5U)
4104 #define CAN_F12R1_FB5_Msk      (0x1UL << CAN_F12R1_FB5_Pos)                     /*!< 0x00000020 */
4105 #define CAN_F12R1_FB5          CAN_F12R1_FB5_Msk                               /*!<Filter bit 5 */
4106 #define CAN_F12R1_FB6_Pos      (6U)
4107 #define CAN_F12R1_FB6_Msk      (0x1UL << CAN_F12R1_FB6_Pos)                     /*!< 0x00000040 */
4108 #define CAN_F12R1_FB6          CAN_F12R1_FB6_Msk                               /*!<Filter bit 6 */
4109 #define CAN_F12R1_FB7_Pos      (7U)
4110 #define CAN_F12R1_FB7_Msk      (0x1UL << CAN_F12R1_FB7_Pos)                     /*!< 0x00000080 */
4111 #define CAN_F12R1_FB7          CAN_F12R1_FB7_Msk                               /*!<Filter bit 7 */
4112 #define CAN_F12R1_FB8_Pos      (8U)
4113 #define CAN_F12R1_FB8_Msk      (0x1UL << CAN_F12R1_FB8_Pos)                     /*!< 0x00000100 */
4114 #define CAN_F12R1_FB8          CAN_F12R1_FB8_Msk                               /*!<Filter bit 8 */
4115 #define CAN_F12R1_FB9_Pos      (9U)
4116 #define CAN_F12R1_FB9_Msk      (0x1UL << CAN_F12R1_FB9_Pos)                     /*!< 0x00000200 */
4117 #define CAN_F12R1_FB9          CAN_F12R1_FB9_Msk                               /*!<Filter bit 9 */
4118 #define CAN_F12R1_FB10_Pos     (10U)
4119 #define CAN_F12R1_FB10_Msk     (0x1UL << CAN_F12R1_FB10_Pos)                    /*!< 0x00000400 */
4120 #define CAN_F12R1_FB10         CAN_F12R1_FB10_Msk                              /*!<Filter bit 10 */
4121 #define CAN_F12R1_FB11_Pos     (11U)
4122 #define CAN_F12R1_FB11_Msk     (0x1UL << CAN_F12R1_FB11_Pos)                    /*!< 0x00000800 */
4123 #define CAN_F12R1_FB11         CAN_F12R1_FB11_Msk                              /*!<Filter bit 11 */
4124 #define CAN_F12R1_FB12_Pos     (12U)
4125 #define CAN_F12R1_FB12_Msk     (0x1UL << CAN_F12R1_FB12_Pos)                    /*!< 0x00001000 */
4126 #define CAN_F12R1_FB12         CAN_F12R1_FB12_Msk                              /*!<Filter bit 12 */
4127 #define CAN_F12R1_FB13_Pos     (13U)
4128 #define CAN_F12R1_FB13_Msk     (0x1UL << CAN_F12R1_FB13_Pos)                    /*!< 0x00002000 */
4129 #define CAN_F12R1_FB13         CAN_F12R1_FB13_Msk                              /*!<Filter bit 13 */
4130 #define CAN_F12R1_FB14_Pos     (14U)
4131 #define CAN_F12R1_FB14_Msk     (0x1UL << CAN_F12R1_FB14_Pos)                    /*!< 0x00004000 */
4132 #define CAN_F12R1_FB14         CAN_F12R1_FB14_Msk                              /*!<Filter bit 14 */
4133 #define CAN_F12R1_FB15_Pos     (15U)
4134 #define CAN_F12R1_FB15_Msk     (0x1UL << CAN_F12R1_FB15_Pos)                    /*!< 0x00008000 */
4135 #define CAN_F12R1_FB15         CAN_F12R1_FB15_Msk                              /*!<Filter bit 15 */
4136 #define CAN_F12R1_FB16_Pos     (16U)
4137 #define CAN_F12R1_FB16_Msk     (0x1UL << CAN_F12R1_FB16_Pos)                    /*!< 0x00010000 */
4138 #define CAN_F12R1_FB16         CAN_F12R1_FB16_Msk                              /*!<Filter bit 16 */
4139 #define CAN_F12R1_FB17_Pos     (17U)
4140 #define CAN_F12R1_FB17_Msk     (0x1UL << CAN_F12R1_FB17_Pos)                    /*!< 0x00020000 */
4141 #define CAN_F12R1_FB17         CAN_F12R1_FB17_Msk                              /*!<Filter bit 17 */
4142 #define CAN_F12R1_FB18_Pos     (18U)
4143 #define CAN_F12R1_FB18_Msk     (0x1UL << CAN_F12R1_FB18_Pos)                    /*!< 0x00040000 */
4144 #define CAN_F12R1_FB18         CAN_F12R1_FB18_Msk                              /*!<Filter bit 18 */
4145 #define CAN_F12R1_FB19_Pos     (19U)
4146 #define CAN_F12R1_FB19_Msk     (0x1UL << CAN_F12R1_FB19_Pos)                    /*!< 0x00080000 */
4147 #define CAN_F12R1_FB19         CAN_F12R1_FB19_Msk                              /*!<Filter bit 19 */
4148 #define CAN_F12R1_FB20_Pos     (20U)
4149 #define CAN_F12R1_FB20_Msk     (0x1UL << CAN_F12R1_FB20_Pos)                    /*!< 0x00100000 */
4150 #define CAN_F12R1_FB20         CAN_F12R1_FB20_Msk                              /*!<Filter bit 20 */
4151 #define CAN_F12R1_FB21_Pos     (21U)
4152 #define CAN_F12R1_FB21_Msk     (0x1UL << CAN_F12R1_FB21_Pos)                    /*!< 0x00200000 */
4153 #define CAN_F12R1_FB21         CAN_F12R1_FB21_Msk                              /*!<Filter bit 21 */
4154 #define CAN_F12R1_FB22_Pos     (22U)
4155 #define CAN_F12R1_FB22_Msk     (0x1UL << CAN_F12R1_FB22_Pos)                    /*!< 0x00400000 */
4156 #define CAN_F12R1_FB22         CAN_F12R1_FB22_Msk                              /*!<Filter bit 22 */
4157 #define CAN_F12R1_FB23_Pos     (23U)
4158 #define CAN_F12R1_FB23_Msk     (0x1UL << CAN_F12R1_FB23_Pos)                    /*!< 0x00800000 */
4159 #define CAN_F12R1_FB23         CAN_F12R1_FB23_Msk                              /*!<Filter bit 23 */
4160 #define CAN_F12R1_FB24_Pos     (24U)
4161 #define CAN_F12R1_FB24_Msk     (0x1UL << CAN_F12R1_FB24_Pos)                    /*!< 0x01000000 */
4162 #define CAN_F12R1_FB24         CAN_F12R1_FB24_Msk                              /*!<Filter bit 24 */
4163 #define CAN_F12R1_FB25_Pos     (25U)
4164 #define CAN_F12R1_FB25_Msk     (0x1UL << CAN_F12R1_FB25_Pos)                    /*!< 0x02000000 */
4165 #define CAN_F12R1_FB25         CAN_F12R1_FB25_Msk                              /*!<Filter bit 25 */
4166 #define CAN_F12R1_FB26_Pos     (26U)
4167 #define CAN_F12R1_FB26_Msk     (0x1UL << CAN_F12R1_FB26_Pos)                    /*!< 0x04000000 */
4168 #define CAN_F12R1_FB26         CAN_F12R1_FB26_Msk                              /*!<Filter bit 26 */
4169 #define CAN_F12R1_FB27_Pos     (27U)
4170 #define CAN_F12R1_FB27_Msk     (0x1UL << CAN_F12R1_FB27_Pos)                    /*!< 0x08000000 */
4171 #define CAN_F12R1_FB27         CAN_F12R1_FB27_Msk                              /*!<Filter bit 27 */
4172 #define CAN_F12R1_FB28_Pos     (28U)
4173 #define CAN_F12R1_FB28_Msk     (0x1UL << CAN_F12R1_FB28_Pos)                    /*!< 0x10000000 */
4174 #define CAN_F12R1_FB28         CAN_F12R1_FB28_Msk                              /*!<Filter bit 28 */
4175 #define CAN_F12R1_FB29_Pos     (29U)
4176 #define CAN_F12R1_FB29_Msk     (0x1UL << CAN_F12R1_FB29_Pos)                    /*!< 0x20000000 */
4177 #define CAN_F12R1_FB29         CAN_F12R1_FB29_Msk                              /*!<Filter bit 29 */
4178 #define CAN_F12R1_FB30_Pos     (30U)
4179 #define CAN_F12R1_FB30_Msk     (0x1UL << CAN_F12R1_FB30_Pos)                    /*!< 0x40000000 */
4180 #define CAN_F12R1_FB30         CAN_F12R1_FB30_Msk                              /*!<Filter bit 30 */
4181 #define CAN_F12R1_FB31_Pos     (31U)
4182 #define CAN_F12R1_FB31_Msk     (0x1UL << CAN_F12R1_FB31_Pos)                    /*!< 0x80000000 */
4183 #define CAN_F12R1_FB31         CAN_F12R1_FB31_Msk                              /*!<Filter bit 31 */
4184 
4185 /*******************  Bit definition for CAN_F13R1 register  ******************/
4186 #define CAN_F13R1_FB0_Pos      (0U)
4187 #define CAN_F13R1_FB0_Msk      (0x1UL << CAN_F13R1_FB0_Pos)                     /*!< 0x00000001 */
4188 #define CAN_F13R1_FB0          CAN_F13R1_FB0_Msk                               /*!<Filter bit 0 */
4189 #define CAN_F13R1_FB1_Pos      (1U)
4190 #define CAN_F13R1_FB1_Msk      (0x1UL << CAN_F13R1_FB1_Pos)                     /*!< 0x00000002 */
4191 #define CAN_F13R1_FB1          CAN_F13R1_FB1_Msk                               /*!<Filter bit 1 */
4192 #define CAN_F13R1_FB2_Pos      (2U)
4193 #define CAN_F13R1_FB2_Msk      (0x1UL << CAN_F13R1_FB2_Pos)                     /*!< 0x00000004 */
4194 #define CAN_F13R1_FB2          CAN_F13R1_FB2_Msk                               /*!<Filter bit 2 */
4195 #define CAN_F13R1_FB3_Pos      (3U)
4196 #define CAN_F13R1_FB3_Msk      (0x1UL << CAN_F13R1_FB3_Pos)                     /*!< 0x00000008 */
4197 #define CAN_F13R1_FB3          CAN_F13R1_FB3_Msk                               /*!<Filter bit 3 */
4198 #define CAN_F13R1_FB4_Pos      (4U)
4199 #define CAN_F13R1_FB4_Msk      (0x1UL << CAN_F13R1_FB4_Pos)                     /*!< 0x00000010 */
4200 #define CAN_F13R1_FB4          CAN_F13R1_FB4_Msk                               /*!<Filter bit 4 */
4201 #define CAN_F13R1_FB5_Pos      (5U)
4202 #define CAN_F13R1_FB5_Msk      (0x1UL << CAN_F13R1_FB5_Pos)                     /*!< 0x00000020 */
4203 #define CAN_F13R1_FB5          CAN_F13R1_FB5_Msk                               /*!<Filter bit 5 */
4204 #define CAN_F13R1_FB6_Pos      (6U)
4205 #define CAN_F13R1_FB6_Msk      (0x1UL << CAN_F13R1_FB6_Pos)                     /*!< 0x00000040 */
4206 #define CAN_F13R1_FB6          CAN_F13R1_FB6_Msk                               /*!<Filter bit 6 */
4207 #define CAN_F13R1_FB7_Pos      (7U)
4208 #define CAN_F13R1_FB7_Msk      (0x1UL << CAN_F13R1_FB7_Pos)                     /*!< 0x00000080 */
4209 #define CAN_F13R1_FB7          CAN_F13R1_FB7_Msk                               /*!<Filter bit 7 */
4210 #define CAN_F13R1_FB8_Pos      (8U)
4211 #define CAN_F13R1_FB8_Msk      (0x1UL << CAN_F13R1_FB8_Pos)                     /*!< 0x00000100 */
4212 #define CAN_F13R1_FB8          CAN_F13R1_FB8_Msk                               /*!<Filter bit 8 */
4213 #define CAN_F13R1_FB9_Pos      (9U)
4214 #define CAN_F13R1_FB9_Msk      (0x1UL << CAN_F13R1_FB9_Pos)                     /*!< 0x00000200 */
4215 #define CAN_F13R1_FB9          CAN_F13R1_FB9_Msk                               /*!<Filter bit 9 */
4216 #define CAN_F13R1_FB10_Pos     (10U)
4217 #define CAN_F13R1_FB10_Msk     (0x1UL << CAN_F13R1_FB10_Pos)                    /*!< 0x00000400 */
4218 #define CAN_F13R1_FB10         CAN_F13R1_FB10_Msk                              /*!<Filter bit 10 */
4219 #define CAN_F13R1_FB11_Pos     (11U)
4220 #define CAN_F13R1_FB11_Msk     (0x1UL << CAN_F13R1_FB11_Pos)                    /*!< 0x00000800 */
4221 #define CAN_F13R1_FB11         CAN_F13R1_FB11_Msk                              /*!<Filter bit 11 */
4222 #define CAN_F13R1_FB12_Pos     (12U)
4223 #define CAN_F13R1_FB12_Msk     (0x1UL << CAN_F13R1_FB12_Pos)                    /*!< 0x00001000 */
4224 #define CAN_F13R1_FB12         CAN_F13R1_FB12_Msk                              /*!<Filter bit 12 */
4225 #define CAN_F13R1_FB13_Pos     (13U)
4226 #define CAN_F13R1_FB13_Msk     (0x1UL << CAN_F13R1_FB13_Pos)                    /*!< 0x00002000 */
4227 #define CAN_F13R1_FB13         CAN_F13R1_FB13_Msk                              /*!<Filter bit 13 */
4228 #define CAN_F13R1_FB14_Pos     (14U)
4229 #define CAN_F13R1_FB14_Msk     (0x1UL << CAN_F13R1_FB14_Pos)                    /*!< 0x00004000 */
4230 #define CAN_F13R1_FB14         CAN_F13R1_FB14_Msk                              /*!<Filter bit 14 */
4231 #define CAN_F13R1_FB15_Pos     (15U)
4232 #define CAN_F13R1_FB15_Msk     (0x1UL << CAN_F13R1_FB15_Pos)                    /*!< 0x00008000 */
4233 #define CAN_F13R1_FB15         CAN_F13R1_FB15_Msk                              /*!<Filter bit 15 */
4234 #define CAN_F13R1_FB16_Pos     (16U)
4235 #define CAN_F13R1_FB16_Msk     (0x1UL << CAN_F13R1_FB16_Pos)                    /*!< 0x00010000 */
4236 #define CAN_F13R1_FB16         CAN_F13R1_FB16_Msk                              /*!<Filter bit 16 */
4237 #define CAN_F13R1_FB17_Pos     (17U)
4238 #define CAN_F13R1_FB17_Msk     (0x1UL << CAN_F13R1_FB17_Pos)                    /*!< 0x00020000 */
4239 #define CAN_F13R1_FB17         CAN_F13R1_FB17_Msk                              /*!<Filter bit 17 */
4240 #define CAN_F13R1_FB18_Pos     (18U)
4241 #define CAN_F13R1_FB18_Msk     (0x1UL << CAN_F13R1_FB18_Pos)                    /*!< 0x00040000 */
4242 #define CAN_F13R1_FB18         CAN_F13R1_FB18_Msk                              /*!<Filter bit 18 */
4243 #define CAN_F13R1_FB19_Pos     (19U)
4244 #define CAN_F13R1_FB19_Msk     (0x1UL << CAN_F13R1_FB19_Pos)                    /*!< 0x00080000 */
4245 #define CAN_F13R1_FB19         CAN_F13R1_FB19_Msk                              /*!<Filter bit 19 */
4246 #define CAN_F13R1_FB20_Pos     (20U)
4247 #define CAN_F13R1_FB20_Msk     (0x1UL << CAN_F13R1_FB20_Pos)                    /*!< 0x00100000 */
4248 #define CAN_F13R1_FB20         CAN_F13R1_FB20_Msk                              /*!<Filter bit 20 */
4249 #define CAN_F13R1_FB21_Pos     (21U)
4250 #define CAN_F13R1_FB21_Msk     (0x1UL << CAN_F13R1_FB21_Pos)                    /*!< 0x00200000 */
4251 #define CAN_F13R1_FB21         CAN_F13R1_FB21_Msk                              /*!<Filter bit 21 */
4252 #define CAN_F13R1_FB22_Pos     (22U)
4253 #define CAN_F13R1_FB22_Msk     (0x1UL << CAN_F13R1_FB22_Pos)                    /*!< 0x00400000 */
4254 #define CAN_F13R1_FB22         CAN_F13R1_FB22_Msk                              /*!<Filter bit 22 */
4255 #define CAN_F13R1_FB23_Pos     (23U)
4256 #define CAN_F13R1_FB23_Msk     (0x1UL << CAN_F13R1_FB23_Pos)                    /*!< 0x00800000 */
4257 #define CAN_F13R1_FB23         CAN_F13R1_FB23_Msk                              /*!<Filter bit 23 */
4258 #define CAN_F13R1_FB24_Pos     (24U)
4259 #define CAN_F13R1_FB24_Msk     (0x1UL << CAN_F13R1_FB24_Pos)                    /*!< 0x01000000 */
4260 #define CAN_F13R1_FB24         CAN_F13R1_FB24_Msk                              /*!<Filter bit 24 */
4261 #define CAN_F13R1_FB25_Pos     (25U)
4262 #define CAN_F13R1_FB25_Msk     (0x1UL << CAN_F13R1_FB25_Pos)                    /*!< 0x02000000 */
4263 #define CAN_F13R1_FB25         CAN_F13R1_FB25_Msk                              /*!<Filter bit 25 */
4264 #define CAN_F13R1_FB26_Pos     (26U)
4265 #define CAN_F13R1_FB26_Msk     (0x1UL << CAN_F13R1_FB26_Pos)                    /*!< 0x04000000 */
4266 #define CAN_F13R1_FB26         CAN_F13R1_FB26_Msk                              /*!<Filter bit 26 */
4267 #define CAN_F13R1_FB27_Pos     (27U)
4268 #define CAN_F13R1_FB27_Msk     (0x1UL << CAN_F13R1_FB27_Pos)                    /*!< 0x08000000 */
4269 #define CAN_F13R1_FB27         CAN_F13R1_FB27_Msk                              /*!<Filter bit 27 */
4270 #define CAN_F13R1_FB28_Pos     (28U)
4271 #define CAN_F13R1_FB28_Msk     (0x1UL << CAN_F13R1_FB28_Pos)                    /*!< 0x10000000 */
4272 #define CAN_F13R1_FB28         CAN_F13R1_FB28_Msk                              /*!<Filter bit 28 */
4273 #define CAN_F13R1_FB29_Pos     (29U)
4274 #define CAN_F13R1_FB29_Msk     (0x1UL << CAN_F13R1_FB29_Pos)                    /*!< 0x20000000 */
4275 #define CAN_F13R1_FB29         CAN_F13R1_FB29_Msk                              /*!<Filter bit 29 */
4276 #define CAN_F13R1_FB30_Pos     (30U)
4277 #define CAN_F13R1_FB30_Msk     (0x1UL << CAN_F13R1_FB30_Pos)                    /*!< 0x40000000 */
4278 #define CAN_F13R1_FB30         CAN_F13R1_FB30_Msk                              /*!<Filter bit 30 */
4279 #define CAN_F13R1_FB31_Pos     (31U)
4280 #define CAN_F13R1_FB31_Msk     (0x1UL << CAN_F13R1_FB31_Pos)                    /*!< 0x80000000 */
4281 #define CAN_F13R1_FB31         CAN_F13R1_FB31_Msk                              /*!<Filter bit 31 */
4282 
4283 /*******************  Bit definition for CAN_F0R2 register  *******************/
4284 #define CAN_F0R2_FB0_Pos       (0U)
4285 #define CAN_F0R2_FB0_Msk       (0x1UL << CAN_F0R2_FB0_Pos)                      /*!< 0x00000001 */
4286 #define CAN_F0R2_FB0           CAN_F0R2_FB0_Msk                                /*!<Filter bit 0 */
4287 #define CAN_F0R2_FB1_Pos       (1U)
4288 #define CAN_F0R2_FB1_Msk       (0x1UL << CAN_F0R2_FB1_Pos)                      /*!< 0x00000002 */
4289 #define CAN_F0R2_FB1           CAN_F0R2_FB1_Msk                                /*!<Filter bit 1 */
4290 #define CAN_F0R2_FB2_Pos       (2U)
4291 #define CAN_F0R2_FB2_Msk       (0x1UL << CAN_F0R2_FB2_Pos)                      /*!< 0x00000004 */
4292 #define CAN_F0R2_FB2           CAN_F0R2_FB2_Msk                                /*!<Filter bit 2 */
4293 #define CAN_F0R2_FB3_Pos       (3U)
4294 #define CAN_F0R2_FB3_Msk       (0x1UL << CAN_F0R2_FB3_Pos)                      /*!< 0x00000008 */
4295 #define CAN_F0R2_FB3           CAN_F0R2_FB3_Msk                                /*!<Filter bit 3 */
4296 #define CAN_F0R2_FB4_Pos       (4U)
4297 #define CAN_F0R2_FB4_Msk       (0x1UL << CAN_F0R2_FB4_Pos)                      /*!< 0x00000010 */
4298 #define CAN_F0R2_FB4           CAN_F0R2_FB4_Msk                                /*!<Filter bit 4 */
4299 #define CAN_F0R2_FB5_Pos       (5U)
4300 #define CAN_F0R2_FB5_Msk       (0x1UL << CAN_F0R2_FB5_Pos)                      /*!< 0x00000020 */
4301 #define CAN_F0R2_FB5           CAN_F0R2_FB5_Msk                                /*!<Filter bit 5 */
4302 #define CAN_F0R2_FB6_Pos       (6U)
4303 #define CAN_F0R2_FB6_Msk       (0x1UL << CAN_F0R2_FB6_Pos)                      /*!< 0x00000040 */
4304 #define CAN_F0R2_FB6           CAN_F0R2_FB6_Msk                                /*!<Filter bit 6 */
4305 #define CAN_F0R2_FB7_Pos       (7U)
4306 #define CAN_F0R2_FB7_Msk       (0x1UL << CAN_F0R2_FB7_Pos)                      /*!< 0x00000080 */
4307 #define CAN_F0R2_FB7           CAN_F0R2_FB7_Msk                                /*!<Filter bit 7 */
4308 #define CAN_F0R2_FB8_Pos       (8U)
4309 #define CAN_F0R2_FB8_Msk       (0x1UL << CAN_F0R2_FB8_Pos)                      /*!< 0x00000100 */
4310 #define CAN_F0R2_FB8           CAN_F0R2_FB8_Msk                                /*!<Filter bit 8 */
4311 #define CAN_F0R2_FB9_Pos       (9U)
4312 #define CAN_F0R2_FB9_Msk       (0x1UL << CAN_F0R2_FB9_Pos)                      /*!< 0x00000200 */
4313 #define CAN_F0R2_FB9           CAN_F0R2_FB9_Msk                                /*!<Filter bit 9 */
4314 #define CAN_F0R2_FB10_Pos      (10U)
4315 #define CAN_F0R2_FB10_Msk      (0x1UL << CAN_F0R2_FB10_Pos)                     /*!< 0x00000400 */
4316 #define CAN_F0R2_FB10          CAN_F0R2_FB10_Msk                               /*!<Filter bit 10 */
4317 #define CAN_F0R2_FB11_Pos      (11U)
4318 #define CAN_F0R2_FB11_Msk      (0x1UL << CAN_F0R2_FB11_Pos)                     /*!< 0x00000800 */
4319 #define CAN_F0R2_FB11          CAN_F0R2_FB11_Msk                               /*!<Filter bit 11 */
4320 #define CAN_F0R2_FB12_Pos      (12U)
4321 #define CAN_F0R2_FB12_Msk      (0x1UL << CAN_F0R2_FB12_Pos)                     /*!< 0x00001000 */
4322 #define CAN_F0R2_FB12          CAN_F0R2_FB12_Msk                               /*!<Filter bit 12 */
4323 #define CAN_F0R2_FB13_Pos      (13U)
4324 #define CAN_F0R2_FB13_Msk      (0x1UL << CAN_F0R2_FB13_Pos)                     /*!< 0x00002000 */
4325 #define CAN_F0R2_FB13          CAN_F0R2_FB13_Msk                               /*!<Filter bit 13 */
4326 #define CAN_F0R2_FB14_Pos      (14U)
4327 #define CAN_F0R2_FB14_Msk      (0x1UL << CAN_F0R2_FB14_Pos)                     /*!< 0x00004000 */
4328 #define CAN_F0R2_FB14          CAN_F0R2_FB14_Msk                               /*!<Filter bit 14 */
4329 #define CAN_F0R2_FB15_Pos      (15U)
4330 #define CAN_F0R2_FB15_Msk      (0x1UL << CAN_F0R2_FB15_Pos)                     /*!< 0x00008000 */
4331 #define CAN_F0R2_FB15          CAN_F0R2_FB15_Msk                               /*!<Filter bit 15 */
4332 #define CAN_F0R2_FB16_Pos      (16U)
4333 #define CAN_F0R2_FB16_Msk      (0x1UL << CAN_F0R2_FB16_Pos)                     /*!< 0x00010000 */
4334 #define CAN_F0R2_FB16          CAN_F0R2_FB16_Msk                               /*!<Filter bit 16 */
4335 #define CAN_F0R2_FB17_Pos      (17U)
4336 #define CAN_F0R2_FB17_Msk      (0x1UL << CAN_F0R2_FB17_Pos)                     /*!< 0x00020000 */
4337 #define CAN_F0R2_FB17          CAN_F0R2_FB17_Msk                               /*!<Filter bit 17 */
4338 #define CAN_F0R2_FB18_Pos      (18U)
4339 #define CAN_F0R2_FB18_Msk      (0x1UL << CAN_F0R2_FB18_Pos)                     /*!< 0x00040000 */
4340 #define CAN_F0R2_FB18          CAN_F0R2_FB18_Msk                               /*!<Filter bit 18 */
4341 #define CAN_F0R2_FB19_Pos      (19U)
4342 #define CAN_F0R2_FB19_Msk      (0x1UL << CAN_F0R2_FB19_Pos)                     /*!< 0x00080000 */
4343 #define CAN_F0R2_FB19          CAN_F0R2_FB19_Msk                               /*!<Filter bit 19 */
4344 #define CAN_F0R2_FB20_Pos      (20U)
4345 #define CAN_F0R2_FB20_Msk      (0x1UL << CAN_F0R2_FB20_Pos)                     /*!< 0x00100000 */
4346 #define CAN_F0R2_FB20          CAN_F0R2_FB20_Msk                               /*!<Filter bit 20 */
4347 #define CAN_F0R2_FB21_Pos      (21U)
4348 #define CAN_F0R2_FB21_Msk      (0x1UL << CAN_F0R2_FB21_Pos)                     /*!< 0x00200000 */
4349 #define CAN_F0R2_FB21          CAN_F0R2_FB21_Msk                               /*!<Filter bit 21 */
4350 #define CAN_F0R2_FB22_Pos      (22U)
4351 #define CAN_F0R2_FB22_Msk      (0x1UL << CAN_F0R2_FB22_Pos)                     /*!< 0x00400000 */
4352 #define CAN_F0R2_FB22          CAN_F0R2_FB22_Msk                               /*!<Filter bit 22 */
4353 #define CAN_F0R2_FB23_Pos      (23U)
4354 #define CAN_F0R2_FB23_Msk      (0x1UL << CAN_F0R2_FB23_Pos)                     /*!< 0x00800000 */
4355 #define CAN_F0R2_FB23          CAN_F0R2_FB23_Msk                               /*!<Filter bit 23 */
4356 #define CAN_F0R2_FB24_Pos      (24U)
4357 #define CAN_F0R2_FB24_Msk      (0x1UL << CAN_F0R2_FB24_Pos)                     /*!< 0x01000000 */
4358 #define CAN_F0R2_FB24          CAN_F0R2_FB24_Msk                               /*!<Filter bit 24 */
4359 #define CAN_F0R2_FB25_Pos      (25U)
4360 #define CAN_F0R2_FB25_Msk      (0x1UL << CAN_F0R2_FB25_Pos)                     /*!< 0x02000000 */
4361 #define CAN_F0R2_FB25          CAN_F0R2_FB25_Msk                               /*!<Filter bit 25 */
4362 #define CAN_F0R2_FB26_Pos      (26U)
4363 #define CAN_F0R2_FB26_Msk      (0x1UL << CAN_F0R2_FB26_Pos)                     /*!< 0x04000000 */
4364 #define CAN_F0R2_FB26          CAN_F0R2_FB26_Msk                               /*!<Filter bit 26 */
4365 #define CAN_F0R2_FB27_Pos      (27U)
4366 #define CAN_F0R2_FB27_Msk      (0x1UL << CAN_F0R2_FB27_Pos)                     /*!< 0x08000000 */
4367 #define CAN_F0R2_FB27          CAN_F0R2_FB27_Msk                               /*!<Filter bit 27 */
4368 #define CAN_F0R2_FB28_Pos      (28U)
4369 #define CAN_F0R2_FB28_Msk      (0x1UL << CAN_F0R2_FB28_Pos)                     /*!< 0x10000000 */
4370 #define CAN_F0R2_FB28          CAN_F0R2_FB28_Msk                               /*!<Filter bit 28 */
4371 #define CAN_F0R2_FB29_Pos      (29U)
4372 #define CAN_F0R2_FB29_Msk      (0x1UL << CAN_F0R2_FB29_Pos)                     /*!< 0x20000000 */
4373 #define CAN_F0R2_FB29          CAN_F0R2_FB29_Msk                               /*!<Filter bit 29 */
4374 #define CAN_F0R2_FB30_Pos      (30U)
4375 #define CAN_F0R2_FB30_Msk      (0x1UL << CAN_F0R2_FB30_Pos)                     /*!< 0x40000000 */
4376 #define CAN_F0R2_FB30          CAN_F0R2_FB30_Msk                               /*!<Filter bit 30 */
4377 #define CAN_F0R2_FB31_Pos      (31U)
4378 #define CAN_F0R2_FB31_Msk      (0x1UL << CAN_F0R2_FB31_Pos)                     /*!< 0x80000000 */
4379 #define CAN_F0R2_FB31          CAN_F0R2_FB31_Msk                               /*!<Filter bit 31 */
4380 
4381 /*******************  Bit definition for CAN_F1R2 register  *******************/
4382 #define CAN_F1R2_FB0_Pos       (0U)
4383 #define CAN_F1R2_FB0_Msk       (0x1UL << CAN_F1R2_FB0_Pos)                      /*!< 0x00000001 */
4384 #define CAN_F1R2_FB0           CAN_F1R2_FB0_Msk                                /*!<Filter bit 0 */
4385 #define CAN_F1R2_FB1_Pos       (1U)
4386 #define CAN_F1R2_FB1_Msk       (0x1UL << CAN_F1R2_FB1_Pos)                      /*!< 0x00000002 */
4387 #define CAN_F1R2_FB1           CAN_F1R2_FB1_Msk                                /*!<Filter bit 1 */
4388 #define CAN_F1R2_FB2_Pos       (2U)
4389 #define CAN_F1R2_FB2_Msk       (0x1UL << CAN_F1R2_FB2_Pos)                      /*!< 0x00000004 */
4390 #define CAN_F1R2_FB2           CAN_F1R2_FB2_Msk                                /*!<Filter bit 2 */
4391 #define CAN_F1R2_FB3_Pos       (3U)
4392 #define CAN_F1R2_FB3_Msk       (0x1UL << CAN_F1R2_FB3_Pos)                      /*!< 0x00000008 */
4393 #define CAN_F1R2_FB3           CAN_F1R2_FB3_Msk                                /*!<Filter bit 3 */
4394 #define CAN_F1R2_FB4_Pos       (4U)
4395 #define CAN_F1R2_FB4_Msk       (0x1UL << CAN_F1R2_FB4_Pos)                      /*!< 0x00000010 */
4396 #define CAN_F1R2_FB4           CAN_F1R2_FB4_Msk                                /*!<Filter bit 4 */
4397 #define CAN_F1R2_FB5_Pos       (5U)
4398 #define CAN_F1R2_FB5_Msk       (0x1UL << CAN_F1R2_FB5_Pos)                      /*!< 0x00000020 */
4399 #define CAN_F1R2_FB5           CAN_F1R2_FB5_Msk                                /*!<Filter bit 5 */
4400 #define CAN_F1R2_FB6_Pos       (6U)
4401 #define CAN_F1R2_FB6_Msk       (0x1UL << CAN_F1R2_FB6_Pos)                      /*!< 0x00000040 */
4402 #define CAN_F1R2_FB6           CAN_F1R2_FB6_Msk                                /*!<Filter bit 6 */
4403 #define CAN_F1R2_FB7_Pos       (7U)
4404 #define CAN_F1R2_FB7_Msk       (0x1UL << CAN_F1R2_FB7_Pos)                      /*!< 0x00000080 */
4405 #define CAN_F1R2_FB7           CAN_F1R2_FB7_Msk                                /*!<Filter bit 7 */
4406 #define CAN_F1R2_FB8_Pos       (8U)
4407 #define CAN_F1R2_FB8_Msk       (0x1UL << CAN_F1R2_FB8_Pos)                      /*!< 0x00000100 */
4408 #define CAN_F1R2_FB8           CAN_F1R2_FB8_Msk                                /*!<Filter bit 8 */
4409 #define CAN_F1R2_FB9_Pos       (9U)
4410 #define CAN_F1R2_FB9_Msk       (0x1UL << CAN_F1R2_FB9_Pos)                      /*!< 0x00000200 */
4411 #define CAN_F1R2_FB9           CAN_F1R2_FB9_Msk                                /*!<Filter bit 9 */
4412 #define CAN_F1R2_FB10_Pos      (10U)
4413 #define CAN_F1R2_FB10_Msk      (0x1UL << CAN_F1R2_FB10_Pos)                     /*!< 0x00000400 */
4414 #define CAN_F1R2_FB10          CAN_F1R2_FB10_Msk                               /*!<Filter bit 10 */
4415 #define CAN_F1R2_FB11_Pos      (11U)
4416 #define CAN_F1R2_FB11_Msk      (0x1UL << CAN_F1R2_FB11_Pos)                     /*!< 0x00000800 */
4417 #define CAN_F1R2_FB11          CAN_F1R2_FB11_Msk                               /*!<Filter bit 11 */
4418 #define CAN_F1R2_FB12_Pos      (12U)
4419 #define CAN_F1R2_FB12_Msk      (0x1UL << CAN_F1R2_FB12_Pos)                     /*!< 0x00001000 */
4420 #define CAN_F1R2_FB12          CAN_F1R2_FB12_Msk                               /*!<Filter bit 12 */
4421 #define CAN_F1R2_FB13_Pos      (13U)
4422 #define CAN_F1R2_FB13_Msk      (0x1UL << CAN_F1R2_FB13_Pos)                     /*!< 0x00002000 */
4423 #define CAN_F1R2_FB13          CAN_F1R2_FB13_Msk                               /*!<Filter bit 13 */
4424 #define CAN_F1R2_FB14_Pos      (14U)
4425 #define CAN_F1R2_FB14_Msk      (0x1UL << CAN_F1R2_FB14_Pos)                     /*!< 0x00004000 */
4426 #define CAN_F1R2_FB14          CAN_F1R2_FB14_Msk                               /*!<Filter bit 14 */
4427 #define CAN_F1R2_FB15_Pos      (15U)
4428 #define CAN_F1R2_FB15_Msk      (0x1UL << CAN_F1R2_FB15_Pos)                     /*!< 0x00008000 */
4429 #define CAN_F1R2_FB15          CAN_F1R2_FB15_Msk                               /*!<Filter bit 15 */
4430 #define CAN_F1R2_FB16_Pos      (16U)
4431 #define CAN_F1R2_FB16_Msk      (0x1UL << CAN_F1R2_FB16_Pos)                     /*!< 0x00010000 */
4432 #define CAN_F1R2_FB16          CAN_F1R2_FB16_Msk                               /*!<Filter bit 16 */
4433 #define CAN_F1R2_FB17_Pos      (17U)
4434 #define CAN_F1R2_FB17_Msk      (0x1UL << CAN_F1R2_FB17_Pos)                     /*!< 0x00020000 */
4435 #define CAN_F1R2_FB17          CAN_F1R2_FB17_Msk                               /*!<Filter bit 17 */
4436 #define CAN_F1R2_FB18_Pos      (18U)
4437 #define CAN_F1R2_FB18_Msk      (0x1UL << CAN_F1R2_FB18_Pos)                     /*!< 0x00040000 */
4438 #define CAN_F1R2_FB18          CAN_F1R2_FB18_Msk                               /*!<Filter bit 18 */
4439 #define CAN_F1R2_FB19_Pos      (19U)
4440 #define CAN_F1R2_FB19_Msk      (0x1UL << CAN_F1R2_FB19_Pos)                     /*!< 0x00080000 */
4441 #define CAN_F1R2_FB19          CAN_F1R2_FB19_Msk                               /*!<Filter bit 19 */
4442 #define CAN_F1R2_FB20_Pos      (20U)
4443 #define CAN_F1R2_FB20_Msk      (0x1UL << CAN_F1R2_FB20_Pos)                     /*!< 0x00100000 */
4444 #define CAN_F1R2_FB20          CAN_F1R2_FB20_Msk                               /*!<Filter bit 20 */
4445 #define CAN_F1R2_FB21_Pos      (21U)
4446 #define CAN_F1R2_FB21_Msk      (0x1UL << CAN_F1R2_FB21_Pos)                     /*!< 0x00200000 */
4447 #define CAN_F1R2_FB21          CAN_F1R2_FB21_Msk                               /*!<Filter bit 21 */
4448 #define CAN_F1R2_FB22_Pos      (22U)
4449 #define CAN_F1R2_FB22_Msk      (0x1UL << CAN_F1R2_FB22_Pos)                     /*!< 0x00400000 */
4450 #define CAN_F1R2_FB22          CAN_F1R2_FB22_Msk                               /*!<Filter bit 22 */
4451 #define CAN_F1R2_FB23_Pos      (23U)
4452 #define CAN_F1R2_FB23_Msk      (0x1UL << CAN_F1R2_FB23_Pos)                     /*!< 0x00800000 */
4453 #define CAN_F1R2_FB23          CAN_F1R2_FB23_Msk                               /*!<Filter bit 23 */
4454 #define CAN_F1R2_FB24_Pos      (24U)
4455 #define CAN_F1R2_FB24_Msk      (0x1UL << CAN_F1R2_FB24_Pos)                     /*!< 0x01000000 */
4456 #define CAN_F1R2_FB24          CAN_F1R2_FB24_Msk                               /*!<Filter bit 24 */
4457 #define CAN_F1R2_FB25_Pos      (25U)
4458 #define CAN_F1R2_FB25_Msk      (0x1UL << CAN_F1R2_FB25_Pos)                     /*!< 0x02000000 */
4459 #define CAN_F1R2_FB25          CAN_F1R2_FB25_Msk                               /*!<Filter bit 25 */
4460 #define CAN_F1R2_FB26_Pos      (26U)
4461 #define CAN_F1R2_FB26_Msk      (0x1UL << CAN_F1R2_FB26_Pos)                     /*!< 0x04000000 */
4462 #define CAN_F1R2_FB26          CAN_F1R2_FB26_Msk                               /*!<Filter bit 26 */
4463 #define CAN_F1R2_FB27_Pos      (27U)
4464 #define CAN_F1R2_FB27_Msk      (0x1UL << CAN_F1R2_FB27_Pos)                     /*!< 0x08000000 */
4465 #define CAN_F1R2_FB27          CAN_F1R2_FB27_Msk                               /*!<Filter bit 27 */
4466 #define CAN_F1R2_FB28_Pos      (28U)
4467 #define CAN_F1R2_FB28_Msk      (0x1UL << CAN_F1R2_FB28_Pos)                     /*!< 0x10000000 */
4468 #define CAN_F1R2_FB28          CAN_F1R2_FB28_Msk                               /*!<Filter bit 28 */
4469 #define CAN_F1R2_FB29_Pos      (29U)
4470 #define CAN_F1R2_FB29_Msk      (0x1UL << CAN_F1R2_FB29_Pos)                     /*!< 0x20000000 */
4471 #define CAN_F1R2_FB29          CAN_F1R2_FB29_Msk                               /*!<Filter bit 29 */
4472 #define CAN_F1R2_FB30_Pos      (30U)
4473 #define CAN_F1R2_FB30_Msk      (0x1UL << CAN_F1R2_FB30_Pos)                     /*!< 0x40000000 */
4474 #define CAN_F1R2_FB30          CAN_F1R2_FB30_Msk                               /*!<Filter bit 30 */
4475 #define CAN_F1R2_FB31_Pos      (31U)
4476 #define CAN_F1R2_FB31_Msk      (0x1UL << CAN_F1R2_FB31_Pos)                     /*!< 0x80000000 */
4477 #define CAN_F1R2_FB31          CAN_F1R2_FB31_Msk                               /*!<Filter bit 31 */
4478 
4479 /*******************  Bit definition for CAN_F2R2 register  *******************/
4480 #define CAN_F2R2_FB0_Pos       (0U)
4481 #define CAN_F2R2_FB0_Msk       (0x1UL << CAN_F2R2_FB0_Pos)                      /*!< 0x00000001 */
4482 #define CAN_F2R2_FB0           CAN_F2R2_FB0_Msk                                /*!<Filter bit 0 */
4483 #define CAN_F2R2_FB1_Pos       (1U)
4484 #define CAN_F2R2_FB1_Msk       (0x1UL << CAN_F2R2_FB1_Pos)                      /*!< 0x00000002 */
4485 #define CAN_F2R2_FB1           CAN_F2R2_FB1_Msk                                /*!<Filter bit 1 */
4486 #define CAN_F2R2_FB2_Pos       (2U)
4487 #define CAN_F2R2_FB2_Msk       (0x1UL << CAN_F2R2_FB2_Pos)                      /*!< 0x00000004 */
4488 #define CAN_F2R2_FB2           CAN_F2R2_FB2_Msk                                /*!<Filter bit 2 */
4489 #define CAN_F2R2_FB3_Pos       (3U)
4490 #define CAN_F2R2_FB3_Msk       (0x1UL << CAN_F2R2_FB3_Pos)                      /*!< 0x00000008 */
4491 #define CAN_F2R2_FB3           CAN_F2R2_FB3_Msk                                /*!<Filter bit 3 */
4492 #define CAN_F2R2_FB4_Pos       (4U)
4493 #define CAN_F2R2_FB4_Msk       (0x1UL << CAN_F2R2_FB4_Pos)                      /*!< 0x00000010 */
4494 #define CAN_F2R2_FB4           CAN_F2R2_FB4_Msk                                /*!<Filter bit 4 */
4495 #define CAN_F2R2_FB5_Pos       (5U)
4496 #define CAN_F2R2_FB5_Msk       (0x1UL << CAN_F2R2_FB5_Pos)                      /*!< 0x00000020 */
4497 #define CAN_F2R2_FB5           CAN_F2R2_FB5_Msk                                /*!<Filter bit 5 */
4498 #define CAN_F2R2_FB6_Pos       (6U)
4499 #define CAN_F2R2_FB6_Msk       (0x1UL << CAN_F2R2_FB6_Pos)                      /*!< 0x00000040 */
4500 #define CAN_F2R2_FB6           CAN_F2R2_FB6_Msk                                /*!<Filter bit 6 */
4501 #define CAN_F2R2_FB7_Pos       (7U)
4502 #define CAN_F2R2_FB7_Msk       (0x1UL << CAN_F2R2_FB7_Pos)                      /*!< 0x00000080 */
4503 #define CAN_F2R2_FB7           CAN_F2R2_FB7_Msk                                /*!<Filter bit 7 */
4504 #define CAN_F2R2_FB8_Pos       (8U)
4505 #define CAN_F2R2_FB8_Msk       (0x1UL << CAN_F2R2_FB8_Pos)                      /*!< 0x00000100 */
4506 #define CAN_F2R2_FB8           CAN_F2R2_FB8_Msk                                /*!<Filter bit 8 */
4507 #define CAN_F2R2_FB9_Pos       (9U)
4508 #define CAN_F2R2_FB9_Msk       (0x1UL << CAN_F2R2_FB9_Pos)                      /*!< 0x00000200 */
4509 #define CAN_F2R2_FB9           CAN_F2R2_FB9_Msk                                /*!<Filter bit 9 */
4510 #define CAN_F2R2_FB10_Pos      (10U)
4511 #define CAN_F2R2_FB10_Msk      (0x1UL << CAN_F2R2_FB10_Pos)                     /*!< 0x00000400 */
4512 #define CAN_F2R2_FB10          CAN_F2R2_FB10_Msk                               /*!<Filter bit 10 */
4513 #define CAN_F2R2_FB11_Pos      (11U)
4514 #define CAN_F2R2_FB11_Msk      (0x1UL << CAN_F2R2_FB11_Pos)                     /*!< 0x00000800 */
4515 #define CAN_F2R2_FB11          CAN_F2R2_FB11_Msk                               /*!<Filter bit 11 */
4516 #define CAN_F2R2_FB12_Pos      (12U)
4517 #define CAN_F2R2_FB12_Msk      (0x1UL << CAN_F2R2_FB12_Pos)                     /*!< 0x00001000 */
4518 #define CAN_F2R2_FB12          CAN_F2R2_FB12_Msk                               /*!<Filter bit 12 */
4519 #define CAN_F2R2_FB13_Pos      (13U)
4520 #define CAN_F2R2_FB13_Msk      (0x1UL << CAN_F2R2_FB13_Pos)                     /*!< 0x00002000 */
4521 #define CAN_F2R2_FB13          CAN_F2R2_FB13_Msk                               /*!<Filter bit 13 */
4522 #define CAN_F2R2_FB14_Pos      (14U)
4523 #define CAN_F2R2_FB14_Msk      (0x1UL << CAN_F2R2_FB14_Pos)                     /*!< 0x00004000 */
4524 #define CAN_F2R2_FB14          CAN_F2R2_FB14_Msk                               /*!<Filter bit 14 */
4525 #define CAN_F2R2_FB15_Pos      (15U)
4526 #define CAN_F2R2_FB15_Msk      (0x1UL << CAN_F2R2_FB15_Pos)                     /*!< 0x00008000 */
4527 #define CAN_F2R2_FB15          CAN_F2R2_FB15_Msk                               /*!<Filter bit 15 */
4528 #define CAN_F2R2_FB16_Pos      (16U)
4529 #define CAN_F2R2_FB16_Msk      (0x1UL << CAN_F2R2_FB16_Pos)                     /*!< 0x00010000 */
4530 #define CAN_F2R2_FB16          CAN_F2R2_FB16_Msk                               /*!<Filter bit 16 */
4531 #define CAN_F2R2_FB17_Pos      (17U)
4532 #define CAN_F2R2_FB17_Msk      (0x1UL << CAN_F2R2_FB17_Pos)                     /*!< 0x00020000 */
4533 #define CAN_F2R2_FB17          CAN_F2R2_FB17_Msk                               /*!<Filter bit 17 */
4534 #define CAN_F2R2_FB18_Pos      (18U)
4535 #define CAN_F2R2_FB18_Msk      (0x1UL << CAN_F2R2_FB18_Pos)                     /*!< 0x00040000 */
4536 #define CAN_F2R2_FB18          CAN_F2R2_FB18_Msk                               /*!<Filter bit 18 */
4537 #define CAN_F2R2_FB19_Pos      (19U)
4538 #define CAN_F2R2_FB19_Msk      (0x1UL << CAN_F2R2_FB19_Pos)                     /*!< 0x00080000 */
4539 #define CAN_F2R2_FB19          CAN_F2R2_FB19_Msk                               /*!<Filter bit 19 */
4540 #define CAN_F2R2_FB20_Pos      (20U)
4541 #define CAN_F2R2_FB20_Msk      (0x1UL << CAN_F2R2_FB20_Pos)                     /*!< 0x00100000 */
4542 #define CAN_F2R2_FB20          CAN_F2R2_FB20_Msk                               /*!<Filter bit 20 */
4543 #define CAN_F2R2_FB21_Pos      (21U)
4544 #define CAN_F2R2_FB21_Msk      (0x1UL << CAN_F2R2_FB21_Pos)                     /*!< 0x00200000 */
4545 #define CAN_F2R2_FB21          CAN_F2R2_FB21_Msk                               /*!<Filter bit 21 */
4546 #define CAN_F2R2_FB22_Pos      (22U)
4547 #define CAN_F2R2_FB22_Msk      (0x1UL << CAN_F2R2_FB22_Pos)                     /*!< 0x00400000 */
4548 #define CAN_F2R2_FB22          CAN_F2R2_FB22_Msk                               /*!<Filter bit 22 */
4549 #define CAN_F2R2_FB23_Pos      (23U)
4550 #define CAN_F2R2_FB23_Msk      (0x1UL << CAN_F2R2_FB23_Pos)                     /*!< 0x00800000 */
4551 #define CAN_F2R2_FB23          CAN_F2R2_FB23_Msk                               /*!<Filter bit 23 */
4552 #define CAN_F2R2_FB24_Pos      (24U)
4553 #define CAN_F2R2_FB24_Msk      (0x1UL << CAN_F2R2_FB24_Pos)                     /*!< 0x01000000 */
4554 #define CAN_F2R2_FB24          CAN_F2R2_FB24_Msk                               /*!<Filter bit 24 */
4555 #define CAN_F2R2_FB25_Pos      (25U)
4556 #define CAN_F2R2_FB25_Msk      (0x1UL << CAN_F2R2_FB25_Pos)                     /*!< 0x02000000 */
4557 #define CAN_F2R2_FB25          CAN_F2R2_FB25_Msk                               /*!<Filter bit 25 */
4558 #define CAN_F2R2_FB26_Pos      (26U)
4559 #define CAN_F2R2_FB26_Msk      (0x1UL << CAN_F2R2_FB26_Pos)                     /*!< 0x04000000 */
4560 #define CAN_F2R2_FB26          CAN_F2R2_FB26_Msk                               /*!<Filter bit 26 */
4561 #define CAN_F2R2_FB27_Pos      (27U)
4562 #define CAN_F2R2_FB27_Msk      (0x1UL << CAN_F2R2_FB27_Pos)                     /*!< 0x08000000 */
4563 #define CAN_F2R2_FB27          CAN_F2R2_FB27_Msk                               /*!<Filter bit 27 */
4564 #define CAN_F2R2_FB28_Pos      (28U)
4565 #define CAN_F2R2_FB28_Msk      (0x1UL << CAN_F2R2_FB28_Pos)                     /*!< 0x10000000 */
4566 #define CAN_F2R2_FB28          CAN_F2R2_FB28_Msk                               /*!<Filter bit 28 */
4567 #define CAN_F2R2_FB29_Pos      (29U)
4568 #define CAN_F2R2_FB29_Msk      (0x1UL << CAN_F2R2_FB29_Pos)                     /*!< 0x20000000 */
4569 #define CAN_F2R2_FB29          CAN_F2R2_FB29_Msk                               /*!<Filter bit 29 */
4570 #define CAN_F2R2_FB30_Pos      (30U)
4571 #define CAN_F2R2_FB30_Msk      (0x1UL << CAN_F2R2_FB30_Pos)                     /*!< 0x40000000 */
4572 #define CAN_F2R2_FB30          CAN_F2R2_FB30_Msk                               /*!<Filter bit 30 */
4573 #define CAN_F2R2_FB31_Pos      (31U)
4574 #define CAN_F2R2_FB31_Msk      (0x1UL << CAN_F2R2_FB31_Pos)                     /*!< 0x80000000 */
4575 #define CAN_F2R2_FB31          CAN_F2R2_FB31_Msk                               /*!<Filter bit 31 */
4576 
4577 /*******************  Bit definition for CAN_F3R2 register  *******************/
4578 #define CAN_F3R2_FB0_Pos       (0U)
4579 #define CAN_F3R2_FB0_Msk       (0x1UL << CAN_F3R2_FB0_Pos)                      /*!< 0x00000001 */
4580 #define CAN_F3R2_FB0           CAN_F3R2_FB0_Msk                                /*!<Filter bit 0 */
4581 #define CAN_F3R2_FB1_Pos       (1U)
4582 #define CAN_F3R2_FB1_Msk       (0x1UL << CAN_F3R2_FB1_Pos)                      /*!< 0x00000002 */
4583 #define CAN_F3R2_FB1           CAN_F3R2_FB1_Msk                                /*!<Filter bit 1 */
4584 #define CAN_F3R2_FB2_Pos       (2U)
4585 #define CAN_F3R2_FB2_Msk       (0x1UL << CAN_F3R2_FB2_Pos)                      /*!< 0x00000004 */
4586 #define CAN_F3R2_FB2           CAN_F3R2_FB2_Msk                                /*!<Filter bit 2 */
4587 #define CAN_F3R2_FB3_Pos       (3U)
4588 #define CAN_F3R2_FB3_Msk       (0x1UL << CAN_F3R2_FB3_Pos)                      /*!< 0x00000008 */
4589 #define CAN_F3R2_FB3           CAN_F3R2_FB3_Msk                                /*!<Filter bit 3 */
4590 #define CAN_F3R2_FB4_Pos       (4U)
4591 #define CAN_F3R2_FB4_Msk       (0x1UL << CAN_F3R2_FB4_Pos)                      /*!< 0x00000010 */
4592 #define CAN_F3R2_FB4           CAN_F3R2_FB4_Msk                                /*!<Filter bit 4 */
4593 #define CAN_F3R2_FB5_Pos       (5U)
4594 #define CAN_F3R2_FB5_Msk       (0x1UL << CAN_F3R2_FB5_Pos)                      /*!< 0x00000020 */
4595 #define CAN_F3R2_FB5           CAN_F3R2_FB5_Msk                                /*!<Filter bit 5 */
4596 #define CAN_F3R2_FB6_Pos       (6U)
4597 #define CAN_F3R2_FB6_Msk       (0x1UL << CAN_F3R2_FB6_Pos)                      /*!< 0x00000040 */
4598 #define CAN_F3R2_FB6           CAN_F3R2_FB6_Msk                                /*!<Filter bit 6 */
4599 #define CAN_F3R2_FB7_Pos       (7U)
4600 #define CAN_F3R2_FB7_Msk       (0x1UL << CAN_F3R2_FB7_Pos)                      /*!< 0x00000080 */
4601 #define CAN_F3R2_FB7           CAN_F3R2_FB7_Msk                                /*!<Filter bit 7 */
4602 #define CAN_F3R2_FB8_Pos       (8U)
4603 #define CAN_F3R2_FB8_Msk       (0x1UL << CAN_F3R2_FB8_Pos)                      /*!< 0x00000100 */
4604 #define CAN_F3R2_FB8           CAN_F3R2_FB8_Msk                                /*!<Filter bit 8 */
4605 #define CAN_F3R2_FB9_Pos       (9U)
4606 #define CAN_F3R2_FB9_Msk       (0x1UL << CAN_F3R2_FB9_Pos)                      /*!< 0x00000200 */
4607 #define CAN_F3R2_FB9           CAN_F3R2_FB9_Msk                                /*!<Filter bit 9 */
4608 #define CAN_F3R2_FB10_Pos      (10U)
4609 #define CAN_F3R2_FB10_Msk      (0x1UL << CAN_F3R2_FB10_Pos)                     /*!< 0x00000400 */
4610 #define CAN_F3R2_FB10          CAN_F3R2_FB10_Msk                               /*!<Filter bit 10 */
4611 #define CAN_F3R2_FB11_Pos      (11U)
4612 #define CAN_F3R2_FB11_Msk      (0x1UL << CAN_F3R2_FB11_Pos)                     /*!< 0x00000800 */
4613 #define CAN_F3R2_FB11          CAN_F3R2_FB11_Msk                               /*!<Filter bit 11 */
4614 #define CAN_F3R2_FB12_Pos      (12U)
4615 #define CAN_F3R2_FB12_Msk      (0x1UL << CAN_F3R2_FB12_Pos)                     /*!< 0x00001000 */
4616 #define CAN_F3R2_FB12          CAN_F3R2_FB12_Msk                               /*!<Filter bit 12 */
4617 #define CAN_F3R2_FB13_Pos      (13U)
4618 #define CAN_F3R2_FB13_Msk      (0x1UL << CAN_F3R2_FB13_Pos)                     /*!< 0x00002000 */
4619 #define CAN_F3R2_FB13          CAN_F3R2_FB13_Msk                               /*!<Filter bit 13 */
4620 #define CAN_F3R2_FB14_Pos      (14U)
4621 #define CAN_F3R2_FB14_Msk      (0x1UL << CAN_F3R2_FB14_Pos)                     /*!< 0x00004000 */
4622 #define CAN_F3R2_FB14          CAN_F3R2_FB14_Msk                               /*!<Filter bit 14 */
4623 #define CAN_F3R2_FB15_Pos      (15U)
4624 #define CAN_F3R2_FB15_Msk      (0x1UL << CAN_F3R2_FB15_Pos)                     /*!< 0x00008000 */
4625 #define CAN_F3R2_FB15          CAN_F3R2_FB15_Msk                               /*!<Filter bit 15 */
4626 #define CAN_F3R2_FB16_Pos      (16U)
4627 #define CAN_F3R2_FB16_Msk      (0x1UL << CAN_F3R2_FB16_Pos)                     /*!< 0x00010000 */
4628 #define CAN_F3R2_FB16          CAN_F3R2_FB16_Msk                               /*!<Filter bit 16 */
4629 #define CAN_F3R2_FB17_Pos      (17U)
4630 #define CAN_F3R2_FB17_Msk      (0x1UL << CAN_F3R2_FB17_Pos)                     /*!< 0x00020000 */
4631 #define CAN_F3R2_FB17          CAN_F3R2_FB17_Msk                               /*!<Filter bit 17 */
4632 #define CAN_F3R2_FB18_Pos      (18U)
4633 #define CAN_F3R2_FB18_Msk      (0x1UL << CAN_F3R2_FB18_Pos)                     /*!< 0x00040000 */
4634 #define CAN_F3R2_FB18          CAN_F3R2_FB18_Msk                               /*!<Filter bit 18 */
4635 #define CAN_F3R2_FB19_Pos      (19U)
4636 #define CAN_F3R2_FB19_Msk      (0x1UL << CAN_F3R2_FB19_Pos)                     /*!< 0x00080000 */
4637 #define CAN_F3R2_FB19          CAN_F3R2_FB19_Msk                               /*!<Filter bit 19 */
4638 #define CAN_F3R2_FB20_Pos      (20U)
4639 #define CAN_F3R2_FB20_Msk      (0x1UL << CAN_F3R2_FB20_Pos)                     /*!< 0x00100000 */
4640 #define CAN_F3R2_FB20          CAN_F3R2_FB20_Msk                               /*!<Filter bit 20 */
4641 #define CAN_F3R2_FB21_Pos      (21U)
4642 #define CAN_F3R2_FB21_Msk      (0x1UL << CAN_F3R2_FB21_Pos)                     /*!< 0x00200000 */
4643 #define CAN_F3R2_FB21          CAN_F3R2_FB21_Msk                               /*!<Filter bit 21 */
4644 #define CAN_F3R2_FB22_Pos      (22U)
4645 #define CAN_F3R2_FB22_Msk      (0x1UL << CAN_F3R2_FB22_Pos)                     /*!< 0x00400000 */
4646 #define CAN_F3R2_FB22          CAN_F3R2_FB22_Msk                               /*!<Filter bit 22 */
4647 #define CAN_F3R2_FB23_Pos      (23U)
4648 #define CAN_F3R2_FB23_Msk      (0x1UL << CAN_F3R2_FB23_Pos)                     /*!< 0x00800000 */
4649 #define CAN_F3R2_FB23          CAN_F3R2_FB23_Msk                               /*!<Filter bit 23 */
4650 #define CAN_F3R2_FB24_Pos      (24U)
4651 #define CAN_F3R2_FB24_Msk      (0x1UL << CAN_F3R2_FB24_Pos)                     /*!< 0x01000000 */
4652 #define CAN_F3R2_FB24          CAN_F3R2_FB24_Msk                               /*!<Filter bit 24 */
4653 #define CAN_F3R2_FB25_Pos      (25U)
4654 #define CAN_F3R2_FB25_Msk      (0x1UL << CAN_F3R2_FB25_Pos)                     /*!< 0x02000000 */
4655 #define CAN_F3R2_FB25          CAN_F3R2_FB25_Msk                               /*!<Filter bit 25 */
4656 #define CAN_F3R2_FB26_Pos      (26U)
4657 #define CAN_F3R2_FB26_Msk      (0x1UL << CAN_F3R2_FB26_Pos)                     /*!< 0x04000000 */
4658 #define CAN_F3R2_FB26          CAN_F3R2_FB26_Msk                               /*!<Filter bit 26 */
4659 #define CAN_F3R2_FB27_Pos      (27U)
4660 #define CAN_F3R2_FB27_Msk      (0x1UL << CAN_F3R2_FB27_Pos)                     /*!< 0x08000000 */
4661 #define CAN_F3R2_FB27          CAN_F3R2_FB27_Msk                               /*!<Filter bit 27 */
4662 #define CAN_F3R2_FB28_Pos      (28U)
4663 #define CAN_F3R2_FB28_Msk      (0x1UL << CAN_F3R2_FB28_Pos)                     /*!< 0x10000000 */
4664 #define CAN_F3R2_FB28          CAN_F3R2_FB28_Msk                               /*!<Filter bit 28 */
4665 #define CAN_F3R2_FB29_Pos      (29U)
4666 #define CAN_F3R2_FB29_Msk      (0x1UL << CAN_F3R2_FB29_Pos)                     /*!< 0x20000000 */
4667 #define CAN_F3R2_FB29          CAN_F3R2_FB29_Msk                               /*!<Filter bit 29 */
4668 #define CAN_F3R2_FB30_Pos      (30U)
4669 #define CAN_F3R2_FB30_Msk      (0x1UL << CAN_F3R2_FB30_Pos)                     /*!< 0x40000000 */
4670 #define CAN_F3R2_FB30          CAN_F3R2_FB30_Msk                               /*!<Filter bit 30 */
4671 #define CAN_F3R2_FB31_Pos      (31U)
4672 #define CAN_F3R2_FB31_Msk      (0x1UL << CAN_F3R2_FB31_Pos)                     /*!< 0x80000000 */
4673 #define CAN_F3R2_FB31          CAN_F3R2_FB31_Msk                               /*!<Filter bit 31 */
4674 
4675 /*******************  Bit definition for CAN_F4R2 register  *******************/
4676 #define CAN_F4R2_FB0_Pos       (0U)
4677 #define CAN_F4R2_FB0_Msk       (0x1UL << CAN_F4R2_FB0_Pos)                      /*!< 0x00000001 */
4678 #define CAN_F4R2_FB0           CAN_F4R2_FB0_Msk                                /*!<Filter bit 0 */
4679 #define CAN_F4R2_FB1_Pos       (1U)
4680 #define CAN_F4R2_FB1_Msk       (0x1UL << CAN_F4R2_FB1_Pos)                      /*!< 0x00000002 */
4681 #define CAN_F4R2_FB1           CAN_F4R2_FB1_Msk                                /*!<Filter bit 1 */
4682 #define CAN_F4R2_FB2_Pos       (2U)
4683 #define CAN_F4R2_FB2_Msk       (0x1UL << CAN_F4R2_FB2_Pos)                      /*!< 0x00000004 */
4684 #define CAN_F4R2_FB2           CAN_F4R2_FB2_Msk                                /*!<Filter bit 2 */
4685 #define CAN_F4R2_FB3_Pos       (3U)
4686 #define CAN_F4R2_FB3_Msk       (0x1UL << CAN_F4R2_FB3_Pos)                      /*!< 0x00000008 */
4687 #define CAN_F4R2_FB3           CAN_F4R2_FB3_Msk                                /*!<Filter bit 3 */
4688 #define CAN_F4R2_FB4_Pos       (4U)
4689 #define CAN_F4R2_FB4_Msk       (0x1UL << CAN_F4R2_FB4_Pos)                      /*!< 0x00000010 */
4690 #define CAN_F4R2_FB4           CAN_F4R2_FB4_Msk                                /*!<Filter bit 4 */
4691 #define CAN_F4R2_FB5_Pos       (5U)
4692 #define CAN_F4R2_FB5_Msk       (0x1UL << CAN_F4R2_FB5_Pos)                      /*!< 0x00000020 */
4693 #define CAN_F4R2_FB5           CAN_F4R2_FB5_Msk                                /*!<Filter bit 5 */
4694 #define CAN_F4R2_FB6_Pos       (6U)
4695 #define CAN_F4R2_FB6_Msk       (0x1UL << CAN_F4R2_FB6_Pos)                      /*!< 0x00000040 */
4696 #define CAN_F4R2_FB6           CAN_F4R2_FB6_Msk                                /*!<Filter bit 6 */
4697 #define CAN_F4R2_FB7_Pos       (7U)
4698 #define CAN_F4R2_FB7_Msk       (0x1UL << CAN_F4R2_FB7_Pos)                      /*!< 0x00000080 */
4699 #define CAN_F4R2_FB7           CAN_F4R2_FB7_Msk                                /*!<Filter bit 7 */
4700 #define CAN_F4R2_FB8_Pos       (8U)
4701 #define CAN_F4R2_FB8_Msk       (0x1UL << CAN_F4R2_FB8_Pos)                      /*!< 0x00000100 */
4702 #define CAN_F4R2_FB8           CAN_F4R2_FB8_Msk                                /*!<Filter bit 8 */
4703 #define CAN_F4R2_FB9_Pos       (9U)
4704 #define CAN_F4R2_FB9_Msk       (0x1UL << CAN_F4R2_FB9_Pos)                      /*!< 0x00000200 */
4705 #define CAN_F4R2_FB9           CAN_F4R2_FB9_Msk                                /*!<Filter bit 9 */
4706 #define CAN_F4R2_FB10_Pos      (10U)
4707 #define CAN_F4R2_FB10_Msk      (0x1UL << CAN_F4R2_FB10_Pos)                     /*!< 0x00000400 */
4708 #define CAN_F4R2_FB10          CAN_F4R2_FB10_Msk                               /*!<Filter bit 10 */
4709 #define CAN_F4R2_FB11_Pos      (11U)
4710 #define CAN_F4R2_FB11_Msk      (0x1UL << CAN_F4R2_FB11_Pos)                     /*!< 0x00000800 */
4711 #define CAN_F4R2_FB11          CAN_F4R2_FB11_Msk                               /*!<Filter bit 11 */
4712 #define CAN_F4R2_FB12_Pos      (12U)
4713 #define CAN_F4R2_FB12_Msk      (0x1UL << CAN_F4R2_FB12_Pos)                     /*!< 0x00001000 */
4714 #define CAN_F4R2_FB12          CAN_F4R2_FB12_Msk                               /*!<Filter bit 12 */
4715 #define CAN_F4R2_FB13_Pos      (13U)
4716 #define CAN_F4R2_FB13_Msk      (0x1UL << CAN_F4R2_FB13_Pos)                     /*!< 0x00002000 */
4717 #define CAN_F4R2_FB13          CAN_F4R2_FB13_Msk                               /*!<Filter bit 13 */
4718 #define CAN_F4R2_FB14_Pos      (14U)
4719 #define CAN_F4R2_FB14_Msk      (0x1UL << CAN_F4R2_FB14_Pos)                     /*!< 0x00004000 */
4720 #define CAN_F4R2_FB14          CAN_F4R2_FB14_Msk                               /*!<Filter bit 14 */
4721 #define CAN_F4R2_FB15_Pos      (15U)
4722 #define CAN_F4R2_FB15_Msk      (0x1UL << CAN_F4R2_FB15_Pos)                     /*!< 0x00008000 */
4723 #define CAN_F4R2_FB15          CAN_F4R2_FB15_Msk                               /*!<Filter bit 15 */
4724 #define CAN_F4R2_FB16_Pos      (16U)
4725 #define CAN_F4R2_FB16_Msk      (0x1UL << CAN_F4R2_FB16_Pos)                     /*!< 0x00010000 */
4726 #define CAN_F4R2_FB16          CAN_F4R2_FB16_Msk                               /*!<Filter bit 16 */
4727 #define CAN_F4R2_FB17_Pos      (17U)
4728 #define CAN_F4R2_FB17_Msk      (0x1UL << CAN_F4R2_FB17_Pos)                     /*!< 0x00020000 */
4729 #define CAN_F4R2_FB17          CAN_F4R2_FB17_Msk                               /*!<Filter bit 17 */
4730 #define CAN_F4R2_FB18_Pos      (18U)
4731 #define CAN_F4R2_FB18_Msk      (0x1UL << CAN_F4R2_FB18_Pos)                     /*!< 0x00040000 */
4732 #define CAN_F4R2_FB18          CAN_F4R2_FB18_Msk                               /*!<Filter bit 18 */
4733 #define CAN_F4R2_FB19_Pos      (19U)
4734 #define CAN_F4R2_FB19_Msk      (0x1UL << CAN_F4R2_FB19_Pos)                     /*!< 0x00080000 */
4735 #define CAN_F4R2_FB19          CAN_F4R2_FB19_Msk                               /*!<Filter bit 19 */
4736 #define CAN_F4R2_FB20_Pos      (20U)
4737 #define CAN_F4R2_FB20_Msk      (0x1UL << CAN_F4R2_FB20_Pos)                     /*!< 0x00100000 */
4738 #define CAN_F4R2_FB20          CAN_F4R2_FB20_Msk                               /*!<Filter bit 20 */
4739 #define CAN_F4R2_FB21_Pos      (21U)
4740 #define CAN_F4R2_FB21_Msk      (0x1UL << CAN_F4R2_FB21_Pos)                     /*!< 0x00200000 */
4741 #define CAN_F4R2_FB21          CAN_F4R2_FB21_Msk                               /*!<Filter bit 21 */
4742 #define CAN_F4R2_FB22_Pos      (22U)
4743 #define CAN_F4R2_FB22_Msk      (0x1UL << CAN_F4R2_FB22_Pos)                     /*!< 0x00400000 */
4744 #define CAN_F4R2_FB22          CAN_F4R2_FB22_Msk                               /*!<Filter bit 22 */
4745 #define CAN_F4R2_FB23_Pos      (23U)
4746 #define CAN_F4R2_FB23_Msk      (0x1UL << CAN_F4R2_FB23_Pos)                     /*!< 0x00800000 */
4747 #define CAN_F4R2_FB23          CAN_F4R2_FB23_Msk                               /*!<Filter bit 23 */
4748 #define CAN_F4R2_FB24_Pos      (24U)
4749 #define CAN_F4R2_FB24_Msk      (0x1UL << CAN_F4R2_FB24_Pos)                     /*!< 0x01000000 */
4750 #define CAN_F4R2_FB24          CAN_F4R2_FB24_Msk                               /*!<Filter bit 24 */
4751 #define CAN_F4R2_FB25_Pos      (25U)
4752 #define CAN_F4R2_FB25_Msk      (0x1UL << CAN_F4R2_FB25_Pos)                     /*!< 0x02000000 */
4753 #define CAN_F4R2_FB25          CAN_F4R2_FB25_Msk                               /*!<Filter bit 25 */
4754 #define CAN_F4R2_FB26_Pos      (26U)
4755 #define CAN_F4R2_FB26_Msk      (0x1UL << CAN_F4R2_FB26_Pos)                     /*!< 0x04000000 */
4756 #define CAN_F4R2_FB26          CAN_F4R2_FB26_Msk                               /*!<Filter bit 26 */
4757 #define CAN_F4R2_FB27_Pos      (27U)
4758 #define CAN_F4R2_FB27_Msk      (0x1UL << CAN_F4R2_FB27_Pos)                     /*!< 0x08000000 */
4759 #define CAN_F4R2_FB27          CAN_F4R2_FB27_Msk                               /*!<Filter bit 27 */
4760 #define CAN_F4R2_FB28_Pos      (28U)
4761 #define CAN_F4R2_FB28_Msk      (0x1UL << CAN_F4R2_FB28_Pos)                     /*!< 0x10000000 */
4762 #define CAN_F4R2_FB28          CAN_F4R2_FB28_Msk                               /*!<Filter bit 28 */
4763 #define CAN_F4R2_FB29_Pos      (29U)
4764 #define CAN_F4R2_FB29_Msk      (0x1UL << CAN_F4R2_FB29_Pos)                     /*!< 0x20000000 */
4765 #define CAN_F4R2_FB29          CAN_F4R2_FB29_Msk                               /*!<Filter bit 29 */
4766 #define CAN_F4R2_FB30_Pos      (30U)
4767 #define CAN_F4R2_FB30_Msk      (0x1UL << CAN_F4R2_FB30_Pos)                     /*!< 0x40000000 */
4768 #define CAN_F4R2_FB30          CAN_F4R2_FB30_Msk                               /*!<Filter bit 30 */
4769 #define CAN_F4R2_FB31_Pos      (31U)
4770 #define CAN_F4R2_FB31_Msk      (0x1UL << CAN_F4R2_FB31_Pos)                     /*!< 0x80000000 */
4771 #define CAN_F4R2_FB31          CAN_F4R2_FB31_Msk                               /*!<Filter bit 31 */
4772 
4773 /*******************  Bit definition for CAN_F5R2 register  *******************/
4774 #define CAN_F5R2_FB0_Pos       (0U)
4775 #define CAN_F5R2_FB0_Msk       (0x1UL << CAN_F5R2_FB0_Pos)                      /*!< 0x00000001 */
4776 #define CAN_F5R2_FB0           CAN_F5R2_FB0_Msk                                /*!<Filter bit 0 */
4777 #define CAN_F5R2_FB1_Pos       (1U)
4778 #define CAN_F5R2_FB1_Msk       (0x1UL << CAN_F5R2_FB1_Pos)                      /*!< 0x00000002 */
4779 #define CAN_F5R2_FB1           CAN_F5R2_FB1_Msk                                /*!<Filter bit 1 */
4780 #define CAN_F5R2_FB2_Pos       (2U)
4781 #define CAN_F5R2_FB2_Msk       (0x1UL << CAN_F5R2_FB2_Pos)                      /*!< 0x00000004 */
4782 #define CAN_F5R2_FB2           CAN_F5R2_FB2_Msk                                /*!<Filter bit 2 */
4783 #define CAN_F5R2_FB3_Pos       (3U)
4784 #define CAN_F5R2_FB3_Msk       (0x1UL << CAN_F5R2_FB3_Pos)                      /*!< 0x00000008 */
4785 #define CAN_F5R2_FB3           CAN_F5R2_FB3_Msk                                /*!<Filter bit 3 */
4786 #define CAN_F5R2_FB4_Pos       (4U)
4787 #define CAN_F5R2_FB4_Msk       (0x1UL << CAN_F5R2_FB4_Pos)                      /*!< 0x00000010 */
4788 #define CAN_F5R2_FB4           CAN_F5R2_FB4_Msk                                /*!<Filter bit 4 */
4789 #define CAN_F5R2_FB5_Pos       (5U)
4790 #define CAN_F5R2_FB5_Msk       (0x1UL << CAN_F5R2_FB5_Pos)                      /*!< 0x00000020 */
4791 #define CAN_F5R2_FB5           CAN_F5R2_FB5_Msk                                /*!<Filter bit 5 */
4792 #define CAN_F5R2_FB6_Pos       (6U)
4793 #define CAN_F5R2_FB6_Msk       (0x1UL << CAN_F5R2_FB6_Pos)                      /*!< 0x00000040 */
4794 #define CAN_F5R2_FB6           CAN_F5R2_FB6_Msk                                /*!<Filter bit 6 */
4795 #define CAN_F5R2_FB7_Pos       (7U)
4796 #define CAN_F5R2_FB7_Msk       (0x1UL << CAN_F5R2_FB7_Pos)                      /*!< 0x00000080 */
4797 #define CAN_F5R2_FB7           CAN_F5R2_FB7_Msk                                /*!<Filter bit 7 */
4798 #define CAN_F5R2_FB8_Pos       (8U)
4799 #define CAN_F5R2_FB8_Msk       (0x1UL << CAN_F5R2_FB8_Pos)                      /*!< 0x00000100 */
4800 #define CAN_F5R2_FB8           CAN_F5R2_FB8_Msk                                /*!<Filter bit 8 */
4801 #define CAN_F5R2_FB9_Pos       (9U)
4802 #define CAN_F5R2_FB9_Msk       (0x1UL << CAN_F5R2_FB9_Pos)                      /*!< 0x00000200 */
4803 #define CAN_F5R2_FB9           CAN_F5R2_FB9_Msk                                /*!<Filter bit 9 */
4804 #define CAN_F5R2_FB10_Pos      (10U)
4805 #define CAN_F5R2_FB10_Msk      (0x1UL << CAN_F5R2_FB10_Pos)                     /*!< 0x00000400 */
4806 #define CAN_F5R2_FB10          CAN_F5R2_FB10_Msk                               /*!<Filter bit 10 */
4807 #define CAN_F5R2_FB11_Pos      (11U)
4808 #define CAN_F5R2_FB11_Msk      (0x1UL << CAN_F5R2_FB11_Pos)                     /*!< 0x00000800 */
4809 #define CAN_F5R2_FB11          CAN_F5R2_FB11_Msk                               /*!<Filter bit 11 */
4810 #define CAN_F5R2_FB12_Pos      (12U)
4811 #define CAN_F5R2_FB12_Msk      (0x1UL << CAN_F5R2_FB12_Pos)                     /*!< 0x00001000 */
4812 #define CAN_F5R2_FB12          CAN_F5R2_FB12_Msk                               /*!<Filter bit 12 */
4813 #define CAN_F5R2_FB13_Pos      (13U)
4814 #define CAN_F5R2_FB13_Msk      (0x1UL << CAN_F5R2_FB13_Pos)                     /*!< 0x00002000 */
4815 #define CAN_F5R2_FB13          CAN_F5R2_FB13_Msk                               /*!<Filter bit 13 */
4816 #define CAN_F5R2_FB14_Pos      (14U)
4817 #define CAN_F5R2_FB14_Msk      (0x1UL << CAN_F5R2_FB14_Pos)                     /*!< 0x00004000 */
4818 #define CAN_F5R2_FB14          CAN_F5R2_FB14_Msk                               /*!<Filter bit 14 */
4819 #define CAN_F5R2_FB15_Pos      (15U)
4820 #define CAN_F5R2_FB15_Msk      (0x1UL << CAN_F5R2_FB15_Pos)                     /*!< 0x00008000 */
4821 #define CAN_F5R2_FB15          CAN_F5R2_FB15_Msk                               /*!<Filter bit 15 */
4822 #define CAN_F5R2_FB16_Pos      (16U)
4823 #define CAN_F5R2_FB16_Msk      (0x1UL << CAN_F5R2_FB16_Pos)                     /*!< 0x00010000 */
4824 #define CAN_F5R2_FB16          CAN_F5R2_FB16_Msk                               /*!<Filter bit 16 */
4825 #define CAN_F5R2_FB17_Pos      (17U)
4826 #define CAN_F5R2_FB17_Msk      (0x1UL << CAN_F5R2_FB17_Pos)                     /*!< 0x00020000 */
4827 #define CAN_F5R2_FB17          CAN_F5R2_FB17_Msk                               /*!<Filter bit 17 */
4828 #define CAN_F5R2_FB18_Pos      (18U)
4829 #define CAN_F5R2_FB18_Msk      (0x1UL << CAN_F5R2_FB18_Pos)                     /*!< 0x00040000 */
4830 #define CAN_F5R2_FB18          CAN_F5R2_FB18_Msk                               /*!<Filter bit 18 */
4831 #define CAN_F5R2_FB19_Pos      (19U)
4832 #define CAN_F5R2_FB19_Msk      (0x1UL << CAN_F5R2_FB19_Pos)                     /*!< 0x00080000 */
4833 #define CAN_F5R2_FB19          CAN_F5R2_FB19_Msk                               /*!<Filter bit 19 */
4834 #define CAN_F5R2_FB20_Pos      (20U)
4835 #define CAN_F5R2_FB20_Msk      (0x1UL << CAN_F5R2_FB20_Pos)                     /*!< 0x00100000 */
4836 #define CAN_F5R2_FB20          CAN_F5R2_FB20_Msk                               /*!<Filter bit 20 */
4837 #define CAN_F5R2_FB21_Pos      (21U)
4838 #define CAN_F5R2_FB21_Msk      (0x1UL << CAN_F5R2_FB21_Pos)                     /*!< 0x00200000 */
4839 #define CAN_F5R2_FB21          CAN_F5R2_FB21_Msk                               /*!<Filter bit 21 */
4840 #define CAN_F5R2_FB22_Pos      (22U)
4841 #define CAN_F5R2_FB22_Msk      (0x1UL << CAN_F5R2_FB22_Pos)                     /*!< 0x00400000 */
4842 #define CAN_F5R2_FB22          CAN_F5R2_FB22_Msk                               /*!<Filter bit 22 */
4843 #define CAN_F5R2_FB23_Pos      (23U)
4844 #define CAN_F5R2_FB23_Msk      (0x1UL << CAN_F5R2_FB23_Pos)                     /*!< 0x00800000 */
4845 #define CAN_F5R2_FB23          CAN_F5R2_FB23_Msk                               /*!<Filter bit 23 */
4846 #define CAN_F5R2_FB24_Pos      (24U)
4847 #define CAN_F5R2_FB24_Msk      (0x1UL << CAN_F5R2_FB24_Pos)                     /*!< 0x01000000 */
4848 #define CAN_F5R2_FB24          CAN_F5R2_FB24_Msk                               /*!<Filter bit 24 */
4849 #define CAN_F5R2_FB25_Pos      (25U)
4850 #define CAN_F5R2_FB25_Msk      (0x1UL << CAN_F5R2_FB25_Pos)                     /*!< 0x02000000 */
4851 #define CAN_F5R2_FB25          CAN_F5R2_FB25_Msk                               /*!<Filter bit 25 */
4852 #define CAN_F5R2_FB26_Pos      (26U)
4853 #define CAN_F5R2_FB26_Msk      (0x1UL << CAN_F5R2_FB26_Pos)                     /*!< 0x04000000 */
4854 #define CAN_F5R2_FB26          CAN_F5R2_FB26_Msk                               /*!<Filter bit 26 */
4855 #define CAN_F5R2_FB27_Pos      (27U)
4856 #define CAN_F5R2_FB27_Msk      (0x1UL << CAN_F5R2_FB27_Pos)                     /*!< 0x08000000 */
4857 #define CAN_F5R2_FB27          CAN_F5R2_FB27_Msk                               /*!<Filter bit 27 */
4858 #define CAN_F5R2_FB28_Pos      (28U)
4859 #define CAN_F5R2_FB28_Msk      (0x1UL << CAN_F5R2_FB28_Pos)                     /*!< 0x10000000 */
4860 #define CAN_F5R2_FB28          CAN_F5R2_FB28_Msk                               /*!<Filter bit 28 */
4861 #define CAN_F5R2_FB29_Pos      (29U)
4862 #define CAN_F5R2_FB29_Msk      (0x1UL << CAN_F5R2_FB29_Pos)                     /*!< 0x20000000 */
4863 #define CAN_F5R2_FB29          CAN_F5R2_FB29_Msk                               /*!<Filter bit 29 */
4864 #define CAN_F5R2_FB30_Pos      (30U)
4865 #define CAN_F5R2_FB30_Msk      (0x1UL << CAN_F5R2_FB30_Pos)                     /*!< 0x40000000 */
4866 #define CAN_F5R2_FB30          CAN_F5R2_FB30_Msk                               /*!<Filter bit 30 */
4867 #define CAN_F5R2_FB31_Pos      (31U)
4868 #define CAN_F5R2_FB31_Msk      (0x1UL << CAN_F5R2_FB31_Pos)                     /*!< 0x80000000 */
4869 #define CAN_F5R2_FB31          CAN_F5R2_FB31_Msk                               /*!<Filter bit 31 */
4870 
4871 /*******************  Bit definition for CAN_F6R2 register  *******************/
4872 #define CAN_F6R2_FB0_Pos       (0U)
4873 #define CAN_F6R2_FB0_Msk       (0x1UL << CAN_F6R2_FB0_Pos)                      /*!< 0x00000001 */
4874 #define CAN_F6R2_FB0           CAN_F6R2_FB0_Msk                                /*!<Filter bit 0 */
4875 #define CAN_F6R2_FB1_Pos       (1U)
4876 #define CAN_F6R2_FB1_Msk       (0x1UL << CAN_F6R2_FB1_Pos)                      /*!< 0x00000002 */
4877 #define CAN_F6R2_FB1           CAN_F6R2_FB1_Msk                                /*!<Filter bit 1 */
4878 #define CAN_F6R2_FB2_Pos       (2U)
4879 #define CAN_F6R2_FB2_Msk       (0x1UL << CAN_F6R2_FB2_Pos)                      /*!< 0x00000004 */
4880 #define CAN_F6R2_FB2           CAN_F6R2_FB2_Msk                                /*!<Filter bit 2 */
4881 #define CAN_F6R2_FB3_Pos       (3U)
4882 #define CAN_F6R2_FB3_Msk       (0x1UL << CAN_F6R2_FB3_Pos)                      /*!< 0x00000008 */
4883 #define CAN_F6R2_FB3           CAN_F6R2_FB3_Msk                                /*!<Filter bit 3 */
4884 #define CAN_F6R2_FB4_Pos       (4U)
4885 #define CAN_F6R2_FB4_Msk       (0x1UL << CAN_F6R2_FB4_Pos)                      /*!< 0x00000010 */
4886 #define CAN_F6R2_FB4           CAN_F6R2_FB4_Msk                                /*!<Filter bit 4 */
4887 #define CAN_F6R2_FB5_Pos       (5U)
4888 #define CAN_F6R2_FB5_Msk       (0x1UL << CAN_F6R2_FB5_Pos)                      /*!< 0x00000020 */
4889 #define CAN_F6R2_FB5           CAN_F6R2_FB5_Msk                                /*!<Filter bit 5 */
4890 #define CAN_F6R2_FB6_Pos       (6U)
4891 #define CAN_F6R2_FB6_Msk       (0x1UL << CAN_F6R2_FB6_Pos)                      /*!< 0x00000040 */
4892 #define CAN_F6R2_FB6           CAN_F6R2_FB6_Msk                                /*!<Filter bit 6 */
4893 #define CAN_F6R2_FB7_Pos       (7U)
4894 #define CAN_F6R2_FB7_Msk       (0x1UL << CAN_F6R2_FB7_Pos)                      /*!< 0x00000080 */
4895 #define CAN_F6R2_FB7           CAN_F6R2_FB7_Msk                                /*!<Filter bit 7 */
4896 #define CAN_F6R2_FB8_Pos       (8U)
4897 #define CAN_F6R2_FB8_Msk       (0x1UL << CAN_F6R2_FB8_Pos)                      /*!< 0x00000100 */
4898 #define CAN_F6R2_FB8           CAN_F6R2_FB8_Msk                                /*!<Filter bit 8 */
4899 #define CAN_F6R2_FB9_Pos       (9U)
4900 #define CAN_F6R2_FB9_Msk       (0x1UL << CAN_F6R2_FB9_Pos)                      /*!< 0x00000200 */
4901 #define CAN_F6R2_FB9           CAN_F6R2_FB9_Msk                                /*!<Filter bit 9 */
4902 #define CAN_F6R2_FB10_Pos      (10U)
4903 #define CAN_F6R2_FB10_Msk      (0x1UL << CAN_F6R2_FB10_Pos)                     /*!< 0x00000400 */
4904 #define CAN_F6R2_FB10          CAN_F6R2_FB10_Msk                               /*!<Filter bit 10 */
4905 #define CAN_F6R2_FB11_Pos      (11U)
4906 #define CAN_F6R2_FB11_Msk      (0x1UL << CAN_F6R2_FB11_Pos)                     /*!< 0x00000800 */
4907 #define CAN_F6R2_FB11          CAN_F6R2_FB11_Msk                               /*!<Filter bit 11 */
4908 #define CAN_F6R2_FB12_Pos      (12U)
4909 #define CAN_F6R2_FB12_Msk      (0x1UL << CAN_F6R2_FB12_Pos)                     /*!< 0x00001000 */
4910 #define CAN_F6R2_FB12          CAN_F6R2_FB12_Msk                               /*!<Filter bit 12 */
4911 #define CAN_F6R2_FB13_Pos      (13U)
4912 #define CAN_F6R2_FB13_Msk      (0x1UL << CAN_F6R2_FB13_Pos)                     /*!< 0x00002000 */
4913 #define CAN_F6R2_FB13          CAN_F6R2_FB13_Msk                               /*!<Filter bit 13 */
4914 #define CAN_F6R2_FB14_Pos      (14U)
4915 #define CAN_F6R2_FB14_Msk      (0x1UL << CAN_F6R2_FB14_Pos)                     /*!< 0x00004000 */
4916 #define CAN_F6R2_FB14          CAN_F6R2_FB14_Msk                               /*!<Filter bit 14 */
4917 #define CAN_F6R2_FB15_Pos      (15U)
4918 #define CAN_F6R2_FB15_Msk      (0x1UL << CAN_F6R2_FB15_Pos)                     /*!< 0x00008000 */
4919 #define CAN_F6R2_FB15          CAN_F6R2_FB15_Msk                               /*!<Filter bit 15 */
4920 #define CAN_F6R2_FB16_Pos      (16U)
4921 #define CAN_F6R2_FB16_Msk      (0x1UL << CAN_F6R2_FB16_Pos)                     /*!< 0x00010000 */
4922 #define CAN_F6R2_FB16          CAN_F6R2_FB16_Msk                               /*!<Filter bit 16 */
4923 #define CAN_F6R2_FB17_Pos      (17U)
4924 #define CAN_F6R2_FB17_Msk      (0x1UL << CAN_F6R2_FB17_Pos)                     /*!< 0x00020000 */
4925 #define CAN_F6R2_FB17          CAN_F6R2_FB17_Msk                               /*!<Filter bit 17 */
4926 #define CAN_F6R2_FB18_Pos      (18U)
4927 #define CAN_F6R2_FB18_Msk      (0x1UL << CAN_F6R2_FB18_Pos)                     /*!< 0x00040000 */
4928 #define CAN_F6R2_FB18          CAN_F6R2_FB18_Msk                               /*!<Filter bit 18 */
4929 #define CAN_F6R2_FB19_Pos      (19U)
4930 #define CAN_F6R2_FB19_Msk      (0x1UL << CAN_F6R2_FB19_Pos)                     /*!< 0x00080000 */
4931 #define CAN_F6R2_FB19          CAN_F6R2_FB19_Msk                               /*!<Filter bit 19 */
4932 #define CAN_F6R2_FB20_Pos      (20U)
4933 #define CAN_F6R2_FB20_Msk      (0x1UL << CAN_F6R2_FB20_Pos)                     /*!< 0x00100000 */
4934 #define CAN_F6R2_FB20          CAN_F6R2_FB20_Msk                               /*!<Filter bit 20 */
4935 #define CAN_F6R2_FB21_Pos      (21U)
4936 #define CAN_F6R2_FB21_Msk      (0x1UL << CAN_F6R2_FB21_Pos)                     /*!< 0x00200000 */
4937 #define CAN_F6R2_FB21          CAN_F6R2_FB21_Msk                               /*!<Filter bit 21 */
4938 #define CAN_F6R2_FB22_Pos      (22U)
4939 #define CAN_F6R2_FB22_Msk      (0x1UL << CAN_F6R2_FB22_Pos)                     /*!< 0x00400000 */
4940 #define CAN_F6R2_FB22          CAN_F6R2_FB22_Msk                               /*!<Filter bit 22 */
4941 #define CAN_F6R2_FB23_Pos      (23U)
4942 #define CAN_F6R2_FB23_Msk      (0x1UL << CAN_F6R2_FB23_Pos)                     /*!< 0x00800000 */
4943 #define CAN_F6R2_FB23          CAN_F6R2_FB23_Msk                               /*!<Filter bit 23 */
4944 #define CAN_F6R2_FB24_Pos      (24U)
4945 #define CAN_F6R2_FB24_Msk      (0x1UL << CAN_F6R2_FB24_Pos)                     /*!< 0x01000000 */
4946 #define CAN_F6R2_FB24          CAN_F6R2_FB24_Msk                               /*!<Filter bit 24 */
4947 #define CAN_F6R2_FB25_Pos      (25U)
4948 #define CAN_F6R2_FB25_Msk      (0x1UL << CAN_F6R2_FB25_Pos)                     /*!< 0x02000000 */
4949 #define CAN_F6R2_FB25          CAN_F6R2_FB25_Msk                               /*!<Filter bit 25 */
4950 #define CAN_F6R2_FB26_Pos      (26U)
4951 #define CAN_F6R2_FB26_Msk      (0x1UL << CAN_F6R2_FB26_Pos)                     /*!< 0x04000000 */
4952 #define CAN_F6R2_FB26          CAN_F6R2_FB26_Msk                               /*!<Filter bit 26 */
4953 #define CAN_F6R2_FB27_Pos      (27U)
4954 #define CAN_F6R2_FB27_Msk      (0x1UL << CAN_F6R2_FB27_Pos)                     /*!< 0x08000000 */
4955 #define CAN_F6R2_FB27          CAN_F6R2_FB27_Msk                               /*!<Filter bit 27 */
4956 #define CAN_F6R2_FB28_Pos      (28U)
4957 #define CAN_F6R2_FB28_Msk      (0x1UL << CAN_F6R2_FB28_Pos)                     /*!< 0x10000000 */
4958 #define CAN_F6R2_FB28          CAN_F6R2_FB28_Msk                               /*!<Filter bit 28 */
4959 #define CAN_F6R2_FB29_Pos      (29U)
4960 #define CAN_F6R2_FB29_Msk      (0x1UL << CAN_F6R2_FB29_Pos)                     /*!< 0x20000000 */
4961 #define CAN_F6R2_FB29          CAN_F6R2_FB29_Msk                               /*!<Filter bit 29 */
4962 #define CAN_F6R2_FB30_Pos      (30U)
4963 #define CAN_F6R2_FB30_Msk      (0x1UL << CAN_F6R2_FB30_Pos)                     /*!< 0x40000000 */
4964 #define CAN_F6R2_FB30          CAN_F6R2_FB30_Msk                               /*!<Filter bit 30 */
4965 #define CAN_F6R2_FB31_Pos      (31U)
4966 #define CAN_F6R2_FB31_Msk      (0x1UL << CAN_F6R2_FB31_Pos)                     /*!< 0x80000000 */
4967 #define CAN_F6R2_FB31          CAN_F6R2_FB31_Msk                               /*!<Filter bit 31 */
4968 
4969 /*******************  Bit definition for CAN_F7R2 register  *******************/
4970 #define CAN_F7R2_FB0_Pos       (0U)
4971 #define CAN_F7R2_FB0_Msk       (0x1UL << CAN_F7R2_FB0_Pos)                      /*!< 0x00000001 */
4972 #define CAN_F7R2_FB0           CAN_F7R2_FB0_Msk                                /*!<Filter bit 0 */
4973 #define CAN_F7R2_FB1_Pos       (1U)
4974 #define CAN_F7R2_FB1_Msk       (0x1UL << CAN_F7R2_FB1_Pos)                      /*!< 0x00000002 */
4975 #define CAN_F7R2_FB1           CAN_F7R2_FB1_Msk                                /*!<Filter bit 1 */
4976 #define CAN_F7R2_FB2_Pos       (2U)
4977 #define CAN_F7R2_FB2_Msk       (0x1UL << CAN_F7R2_FB2_Pos)                      /*!< 0x00000004 */
4978 #define CAN_F7R2_FB2           CAN_F7R2_FB2_Msk                                /*!<Filter bit 2 */
4979 #define CAN_F7R2_FB3_Pos       (3U)
4980 #define CAN_F7R2_FB3_Msk       (0x1UL << CAN_F7R2_FB3_Pos)                      /*!< 0x00000008 */
4981 #define CAN_F7R2_FB3           CAN_F7R2_FB3_Msk                                /*!<Filter bit 3 */
4982 #define CAN_F7R2_FB4_Pos       (4U)
4983 #define CAN_F7R2_FB4_Msk       (0x1UL << CAN_F7R2_FB4_Pos)                      /*!< 0x00000010 */
4984 #define CAN_F7R2_FB4           CAN_F7R2_FB4_Msk                                /*!<Filter bit 4 */
4985 #define CAN_F7R2_FB5_Pos       (5U)
4986 #define CAN_F7R2_FB5_Msk       (0x1UL << CAN_F7R2_FB5_Pos)                      /*!< 0x00000020 */
4987 #define CAN_F7R2_FB5           CAN_F7R2_FB5_Msk                                /*!<Filter bit 5 */
4988 #define CAN_F7R2_FB6_Pos       (6U)
4989 #define CAN_F7R2_FB6_Msk       (0x1UL << CAN_F7R2_FB6_Pos)                      /*!< 0x00000040 */
4990 #define CAN_F7R2_FB6           CAN_F7R2_FB6_Msk                                /*!<Filter bit 6 */
4991 #define CAN_F7R2_FB7_Pos       (7U)
4992 #define CAN_F7R2_FB7_Msk       (0x1UL << CAN_F7R2_FB7_Pos)                      /*!< 0x00000080 */
4993 #define CAN_F7R2_FB7           CAN_F7R2_FB7_Msk                                /*!<Filter bit 7 */
4994 #define CAN_F7R2_FB8_Pos       (8U)
4995 #define CAN_F7R2_FB8_Msk       (0x1UL << CAN_F7R2_FB8_Pos)                      /*!< 0x00000100 */
4996 #define CAN_F7R2_FB8           CAN_F7R2_FB8_Msk                                /*!<Filter bit 8 */
4997 #define CAN_F7R2_FB9_Pos       (9U)
4998 #define CAN_F7R2_FB9_Msk       (0x1UL << CAN_F7R2_FB9_Pos)                      /*!< 0x00000200 */
4999 #define CAN_F7R2_FB9           CAN_F7R2_FB9_Msk                                /*!<Filter bit 9 */
5000 #define CAN_F7R2_FB10_Pos      (10U)
5001 #define CAN_F7R2_FB10_Msk      (0x1UL << CAN_F7R2_FB10_Pos)                     /*!< 0x00000400 */
5002 #define CAN_F7R2_FB10          CAN_F7R2_FB10_Msk                               /*!<Filter bit 10 */
5003 #define CAN_F7R2_FB11_Pos      (11U)
5004 #define CAN_F7R2_FB11_Msk      (0x1UL << CAN_F7R2_FB11_Pos)                     /*!< 0x00000800 */
5005 #define CAN_F7R2_FB11          CAN_F7R2_FB11_Msk                               /*!<Filter bit 11 */
5006 #define CAN_F7R2_FB12_Pos      (12U)
5007 #define CAN_F7R2_FB12_Msk      (0x1UL << CAN_F7R2_FB12_Pos)                     /*!< 0x00001000 */
5008 #define CAN_F7R2_FB12          CAN_F7R2_FB12_Msk                               /*!<Filter bit 12 */
5009 #define CAN_F7R2_FB13_Pos      (13U)
5010 #define CAN_F7R2_FB13_Msk      (0x1UL << CAN_F7R2_FB13_Pos)                     /*!< 0x00002000 */
5011 #define CAN_F7R2_FB13          CAN_F7R2_FB13_Msk                               /*!<Filter bit 13 */
5012 #define CAN_F7R2_FB14_Pos      (14U)
5013 #define CAN_F7R2_FB14_Msk      (0x1UL << CAN_F7R2_FB14_Pos)                     /*!< 0x00004000 */
5014 #define CAN_F7R2_FB14          CAN_F7R2_FB14_Msk                               /*!<Filter bit 14 */
5015 #define CAN_F7R2_FB15_Pos      (15U)
5016 #define CAN_F7R2_FB15_Msk      (0x1UL << CAN_F7R2_FB15_Pos)                     /*!< 0x00008000 */
5017 #define CAN_F7R2_FB15          CAN_F7R2_FB15_Msk                               /*!<Filter bit 15 */
5018 #define CAN_F7R2_FB16_Pos      (16U)
5019 #define CAN_F7R2_FB16_Msk      (0x1UL << CAN_F7R2_FB16_Pos)                     /*!< 0x00010000 */
5020 #define CAN_F7R2_FB16          CAN_F7R2_FB16_Msk                               /*!<Filter bit 16 */
5021 #define CAN_F7R2_FB17_Pos      (17U)
5022 #define CAN_F7R2_FB17_Msk      (0x1UL << CAN_F7R2_FB17_Pos)                     /*!< 0x00020000 */
5023 #define CAN_F7R2_FB17          CAN_F7R2_FB17_Msk                               /*!<Filter bit 17 */
5024 #define CAN_F7R2_FB18_Pos      (18U)
5025 #define CAN_F7R2_FB18_Msk      (0x1UL << CAN_F7R2_FB18_Pos)                     /*!< 0x00040000 */
5026 #define CAN_F7R2_FB18          CAN_F7R2_FB18_Msk                               /*!<Filter bit 18 */
5027 #define CAN_F7R2_FB19_Pos      (19U)
5028 #define CAN_F7R2_FB19_Msk      (0x1UL << CAN_F7R2_FB19_Pos)                     /*!< 0x00080000 */
5029 #define CAN_F7R2_FB19          CAN_F7R2_FB19_Msk                               /*!<Filter bit 19 */
5030 #define CAN_F7R2_FB20_Pos      (20U)
5031 #define CAN_F7R2_FB20_Msk      (0x1UL << CAN_F7R2_FB20_Pos)                     /*!< 0x00100000 */
5032 #define CAN_F7R2_FB20          CAN_F7R2_FB20_Msk                               /*!<Filter bit 20 */
5033 #define CAN_F7R2_FB21_Pos      (21U)
5034 #define CAN_F7R2_FB21_Msk      (0x1UL << CAN_F7R2_FB21_Pos)                     /*!< 0x00200000 */
5035 #define CAN_F7R2_FB21          CAN_F7R2_FB21_Msk                               /*!<Filter bit 21 */
5036 #define CAN_F7R2_FB22_Pos      (22U)
5037 #define CAN_F7R2_FB22_Msk      (0x1UL << CAN_F7R2_FB22_Pos)                     /*!< 0x00400000 */
5038 #define CAN_F7R2_FB22          CAN_F7R2_FB22_Msk                               /*!<Filter bit 22 */
5039 #define CAN_F7R2_FB23_Pos      (23U)
5040 #define CAN_F7R2_FB23_Msk      (0x1UL << CAN_F7R2_FB23_Pos)                     /*!< 0x00800000 */
5041 #define CAN_F7R2_FB23          CAN_F7R2_FB23_Msk                               /*!<Filter bit 23 */
5042 #define CAN_F7R2_FB24_Pos      (24U)
5043 #define CAN_F7R2_FB24_Msk      (0x1UL << CAN_F7R2_FB24_Pos)                     /*!< 0x01000000 */
5044 #define CAN_F7R2_FB24          CAN_F7R2_FB24_Msk                               /*!<Filter bit 24 */
5045 #define CAN_F7R2_FB25_Pos      (25U)
5046 #define CAN_F7R2_FB25_Msk      (0x1UL << CAN_F7R2_FB25_Pos)                     /*!< 0x02000000 */
5047 #define CAN_F7R2_FB25          CAN_F7R2_FB25_Msk                               /*!<Filter bit 25 */
5048 #define CAN_F7R2_FB26_Pos      (26U)
5049 #define CAN_F7R2_FB26_Msk      (0x1UL << CAN_F7R2_FB26_Pos)                     /*!< 0x04000000 */
5050 #define CAN_F7R2_FB26          CAN_F7R2_FB26_Msk                               /*!<Filter bit 26 */
5051 #define CAN_F7R2_FB27_Pos      (27U)
5052 #define CAN_F7R2_FB27_Msk      (0x1UL << CAN_F7R2_FB27_Pos)                     /*!< 0x08000000 */
5053 #define CAN_F7R2_FB27          CAN_F7R2_FB27_Msk                               /*!<Filter bit 27 */
5054 #define CAN_F7R2_FB28_Pos      (28U)
5055 #define CAN_F7R2_FB28_Msk      (0x1UL << CAN_F7R2_FB28_Pos)                     /*!< 0x10000000 */
5056 #define CAN_F7R2_FB28          CAN_F7R2_FB28_Msk                               /*!<Filter bit 28 */
5057 #define CAN_F7R2_FB29_Pos      (29U)
5058 #define CAN_F7R2_FB29_Msk      (0x1UL << CAN_F7R2_FB29_Pos)                     /*!< 0x20000000 */
5059 #define CAN_F7R2_FB29          CAN_F7R2_FB29_Msk                               /*!<Filter bit 29 */
5060 #define CAN_F7R2_FB30_Pos      (30U)
5061 #define CAN_F7R2_FB30_Msk      (0x1UL << CAN_F7R2_FB30_Pos)                     /*!< 0x40000000 */
5062 #define CAN_F7R2_FB30          CAN_F7R2_FB30_Msk                               /*!<Filter bit 30 */
5063 #define CAN_F7R2_FB31_Pos      (31U)
5064 #define CAN_F7R2_FB31_Msk      (0x1UL << CAN_F7R2_FB31_Pos)                     /*!< 0x80000000 */
5065 #define CAN_F7R2_FB31          CAN_F7R2_FB31_Msk                               /*!<Filter bit 31 */
5066 
5067 /*******************  Bit definition for CAN_F8R2 register  *******************/
5068 #define CAN_F8R2_FB0_Pos       (0U)
5069 #define CAN_F8R2_FB0_Msk       (0x1UL << CAN_F8R2_FB0_Pos)                      /*!< 0x00000001 */
5070 #define CAN_F8R2_FB0           CAN_F8R2_FB0_Msk                                /*!<Filter bit 0 */
5071 #define CAN_F8R2_FB1_Pos       (1U)
5072 #define CAN_F8R2_FB1_Msk       (0x1UL << CAN_F8R2_FB1_Pos)                      /*!< 0x00000002 */
5073 #define CAN_F8R2_FB1           CAN_F8R2_FB1_Msk                                /*!<Filter bit 1 */
5074 #define CAN_F8R2_FB2_Pos       (2U)
5075 #define CAN_F8R2_FB2_Msk       (0x1UL << CAN_F8R2_FB2_Pos)                      /*!< 0x00000004 */
5076 #define CAN_F8R2_FB2           CAN_F8R2_FB2_Msk                                /*!<Filter bit 2 */
5077 #define CAN_F8R2_FB3_Pos       (3U)
5078 #define CAN_F8R2_FB3_Msk       (0x1UL << CAN_F8R2_FB3_Pos)                      /*!< 0x00000008 */
5079 #define CAN_F8R2_FB3           CAN_F8R2_FB3_Msk                                /*!<Filter bit 3 */
5080 #define CAN_F8R2_FB4_Pos       (4U)
5081 #define CAN_F8R2_FB4_Msk       (0x1UL << CAN_F8R2_FB4_Pos)                      /*!< 0x00000010 */
5082 #define CAN_F8R2_FB4           CAN_F8R2_FB4_Msk                                /*!<Filter bit 4 */
5083 #define CAN_F8R2_FB5_Pos       (5U)
5084 #define CAN_F8R2_FB5_Msk       (0x1UL << CAN_F8R2_FB5_Pos)                      /*!< 0x00000020 */
5085 #define CAN_F8R2_FB5           CAN_F8R2_FB5_Msk                                /*!<Filter bit 5 */
5086 #define CAN_F8R2_FB6_Pos       (6U)
5087 #define CAN_F8R2_FB6_Msk       (0x1UL << CAN_F8R2_FB6_Pos)                      /*!< 0x00000040 */
5088 #define CAN_F8R2_FB6           CAN_F8R2_FB6_Msk                                /*!<Filter bit 6 */
5089 #define CAN_F8R2_FB7_Pos       (7U)
5090 #define CAN_F8R2_FB7_Msk       (0x1UL << CAN_F8R2_FB7_Pos)                      /*!< 0x00000080 */
5091 #define CAN_F8R2_FB7           CAN_F8R2_FB7_Msk                                /*!<Filter bit 7 */
5092 #define CAN_F8R2_FB8_Pos       (8U)
5093 #define CAN_F8R2_FB8_Msk       (0x1UL << CAN_F8R2_FB8_Pos)                      /*!< 0x00000100 */
5094 #define CAN_F8R2_FB8           CAN_F8R2_FB8_Msk                                /*!<Filter bit 8 */
5095 #define CAN_F8R2_FB9_Pos       (9U)
5096 #define CAN_F8R2_FB9_Msk       (0x1UL << CAN_F8R2_FB9_Pos)                      /*!< 0x00000200 */
5097 #define CAN_F8R2_FB9           CAN_F8R2_FB9_Msk                                /*!<Filter bit 9 */
5098 #define CAN_F8R2_FB10_Pos      (10U)
5099 #define CAN_F8R2_FB10_Msk      (0x1UL << CAN_F8R2_FB10_Pos)                     /*!< 0x00000400 */
5100 #define CAN_F8R2_FB10          CAN_F8R2_FB10_Msk                               /*!<Filter bit 10 */
5101 #define CAN_F8R2_FB11_Pos      (11U)
5102 #define CAN_F8R2_FB11_Msk      (0x1UL << CAN_F8R2_FB11_Pos)                     /*!< 0x00000800 */
5103 #define CAN_F8R2_FB11          CAN_F8R2_FB11_Msk                               /*!<Filter bit 11 */
5104 #define CAN_F8R2_FB12_Pos      (12U)
5105 #define CAN_F8R2_FB12_Msk      (0x1UL << CAN_F8R2_FB12_Pos)                     /*!< 0x00001000 */
5106 #define CAN_F8R2_FB12          CAN_F8R2_FB12_Msk                               /*!<Filter bit 12 */
5107 #define CAN_F8R2_FB13_Pos      (13U)
5108 #define CAN_F8R2_FB13_Msk      (0x1UL << CAN_F8R2_FB13_Pos)                     /*!< 0x00002000 */
5109 #define CAN_F8R2_FB13          CAN_F8R2_FB13_Msk                               /*!<Filter bit 13 */
5110 #define CAN_F8R2_FB14_Pos      (14U)
5111 #define CAN_F8R2_FB14_Msk      (0x1UL << CAN_F8R2_FB14_Pos)                     /*!< 0x00004000 */
5112 #define CAN_F8R2_FB14          CAN_F8R2_FB14_Msk                               /*!<Filter bit 14 */
5113 #define CAN_F8R2_FB15_Pos      (15U)
5114 #define CAN_F8R2_FB15_Msk      (0x1UL << CAN_F8R2_FB15_Pos)                     /*!< 0x00008000 */
5115 #define CAN_F8R2_FB15          CAN_F8R2_FB15_Msk                               /*!<Filter bit 15 */
5116 #define CAN_F8R2_FB16_Pos      (16U)
5117 #define CAN_F8R2_FB16_Msk      (0x1UL << CAN_F8R2_FB16_Pos)                     /*!< 0x00010000 */
5118 #define CAN_F8R2_FB16          CAN_F8R2_FB16_Msk                               /*!<Filter bit 16 */
5119 #define CAN_F8R2_FB17_Pos      (17U)
5120 #define CAN_F8R2_FB17_Msk      (0x1UL << CAN_F8R2_FB17_Pos)                     /*!< 0x00020000 */
5121 #define CAN_F8R2_FB17          CAN_F8R2_FB17_Msk                               /*!<Filter bit 17 */
5122 #define CAN_F8R2_FB18_Pos      (18U)
5123 #define CAN_F8R2_FB18_Msk      (0x1UL << CAN_F8R2_FB18_Pos)                     /*!< 0x00040000 */
5124 #define CAN_F8R2_FB18          CAN_F8R2_FB18_Msk                               /*!<Filter bit 18 */
5125 #define CAN_F8R2_FB19_Pos      (19U)
5126 #define CAN_F8R2_FB19_Msk      (0x1UL << CAN_F8R2_FB19_Pos)                     /*!< 0x00080000 */
5127 #define CAN_F8R2_FB19          CAN_F8R2_FB19_Msk                               /*!<Filter bit 19 */
5128 #define CAN_F8R2_FB20_Pos      (20U)
5129 #define CAN_F8R2_FB20_Msk      (0x1UL << CAN_F8R2_FB20_Pos)                     /*!< 0x00100000 */
5130 #define CAN_F8R2_FB20          CAN_F8R2_FB20_Msk                               /*!<Filter bit 20 */
5131 #define CAN_F8R2_FB21_Pos      (21U)
5132 #define CAN_F8R2_FB21_Msk      (0x1UL << CAN_F8R2_FB21_Pos)                     /*!< 0x00200000 */
5133 #define CAN_F8R2_FB21          CAN_F8R2_FB21_Msk                               /*!<Filter bit 21 */
5134 #define CAN_F8R2_FB22_Pos      (22U)
5135 #define CAN_F8R2_FB22_Msk      (0x1UL << CAN_F8R2_FB22_Pos)                     /*!< 0x00400000 */
5136 #define CAN_F8R2_FB22          CAN_F8R2_FB22_Msk                               /*!<Filter bit 22 */
5137 #define CAN_F8R2_FB23_Pos      (23U)
5138 #define CAN_F8R2_FB23_Msk      (0x1UL << CAN_F8R2_FB23_Pos)                     /*!< 0x00800000 */
5139 #define CAN_F8R2_FB23          CAN_F8R2_FB23_Msk                               /*!<Filter bit 23 */
5140 #define CAN_F8R2_FB24_Pos      (24U)
5141 #define CAN_F8R2_FB24_Msk      (0x1UL << CAN_F8R2_FB24_Pos)                     /*!< 0x01000000 */
5142 #define CAN_F8R2_FB24          CAN_F8R2_FB24_Msk                               /*!<Filter bit 24 */
5143 #define CAN_F8R2_FB25_Pos      (25U)
5144 #define CAN_F8R2_FB25_Msk      (0x1UL << CAN_F8R2_FB25_Pos)                     /*!< 0x02000000 */
5145 #define CAN_F8R2_FB25          CAN_F8R2_FB25_Msk                               /*!<Filter bit 25 */
5146 #define CAN_F8R2_FB26_Pos      (26U)
5147 #define CAN_F8R2_FB26_Msk      (0x1UL << CAN_F8R2_FB26_Pos)                     /*!< 0x04000000 */
5148 #define CAN_F8R2_FB26          CAN_F8R2_FB26_Msk                               /*!<Filter bit 26 */
5149 #define CAN_F8R2_FB27_Pos      (27U)
5150 #define CAN_F8R2_FB27_Msk      (0x1UL << CAN_F8R2_FB27_Pos)                     /*!< 0x08000000 */
5151 #define CAN_F8R2_FB27          CAN_F8R2_FB27_Msk                               /*!<Filter bit 27 */
5152 #define CAN_F8R2_FB28_Pos      (28U)
5153 #define CAN_F8R2_FB28_Msk      (0x1UL << CAN_F8R2_FB28_Pos)                     /*!< 0x10000000 */
5154 #define CAN_F8R2_FB28          CAN_F8R2_FB28_Msk                               /*!<Filter bit 28 */
5155 #define CAN_F8R2_FB29_Pos      (29U)
5156 #define CAN_F8R2_FB29_Msk      (0x1UL << CAN_F8R2_FB29_Pos)                     /*!< 0x20000000 */
5157 #define CAN_F8R2_FB29          CAN_F8R2_FB29_Msk                               /*!<Filter bit 29 */
5158 #define CAN_F8R2_FB30_Pos      (30U)
5159 #define CAN_F8R2_FB30_Msk      (0x1UL << CAN_F8R2_FB30_Pos)                     /*!< 0x40000000 */
5160 #define CAN_F8R2_FB30          CAN_F8R2_FB30_Msk                               /*!<Filter bit 30 */
5161 #define CAN_F8R2_FB31_Pos      (31U)
5162 #define CAN_F8R2_FB31_Msk      (0x1UL << CAN_F8R2_FB31_Pos)                     /*!< 0x80000000 */
5163 #define CAN_F8R2_FB31          CAN_F8R2_FB31_Msk                               /*!<Filter bit 31 */
5164 
5165 /*******************  Bit definition for CAN_F9R2 register  *******************/
5166 #define CAN_F9R2_FB0_Pos       (0U)
5167 #define CAN_F9R2_FB0_Msk       (0x1UL << CAN_F9R2_FB0_Pos)                      /*!< 0x00000001 */
5168 #define CAN_F9R2_FB0           CAN_F9R2_FB0_Msk                                /*!<Filter bit 0 */
5169 #define CAN_F9R2_FB1_Pos       (1U)
5170 #define CAN_F9R2_FB1_Msk       (0x1UL << CAN_F9R2_FB1_Pos)                      /*!< 0x00000002 */
5171 #define CAN_F9R2_FB1           CAN_F9R2_FB1_Msk                                /*!<Filter bit 1 */
5172 #define CAN_F9R2_FB2_Pos       (2U)
5173 #define CAN_F9R2_FB2_Msk       (0x1UL << CAN_F9R2_FB2_Pos)                      /*!< 0x00000004 */
5174 #define CAN_F9R2_FB2           CAN_F9R2_FB2_Msk                                /*!<Filter bit 2 */
5175 #define CAN_F9R2_FB3_Pos       (3U)
5176 #define CAN_F9R2_FB3_Msk       (0x1UL << CAN_F9R2_FB3_Pos)                      /*!< 0x00000008 */
5177 #define CAN_F9R2_FB3           CAN_F9R2_FB3_Msk                                /*!<Filter bit 3 */
5178 #define CAN_F9R2_FB4_Pos       (4U)
5179 #define CAN_F9R2_FB4_Msk       (0x1UL << CAN_F9R2_FB4_Pos)                      /*!< 0x00000010 */
5180 #define CAN_F9R2_FB4           CAN_F9R2_FB4_Msk                                /*!<Filter bit 4 */
5181 #define CAN_F9R2_FB5_Pos       (5U)
5182 #define CAN_F9R2_FB5_Msk       (0x1UL << CAN_F9R2_FB5_Pos)                      /*!< 0x00000020 */
5183 #define CAN_F9R2_FB5           CAN_F9R2_FB5_Msk                                /*!<Filter bit 5 */
5184 #define CAN_F9R2_FB6_Pos       (6U)
5185 #define CAN_F9R2_FB6_Msk       (0x1UL << CAN_F9R2_FB6_Pos)                      /*!< 0x00000040 */
5186 #define CAN_F9R2_FB6           CAN_F9R2_FB6_Msk                                /*!<Filter bit 6 */
5187 #define CAN_F9R2_FB7_Pos       (7U)
5188 #define CAN_F9R2_FB7_Msk       (0x1UL << CAN_F9R2_FB7_Pos)                      /*!< 0x00000080 */
5189 #define CAN_F9R2_FB7           CAN_F9R2_FB7_Msk                                /*!<Filter bit 7 */
5190 #define CAN_F9R2_FB8_Pos       (8U)
5191 #define CAN_F9R2_FB8_Msk       (0x1UL << CAN_F9R2_FB8_Pos)                      /*!< 0x00000100 */
5192 #define CAN_F9R2_FB8           CAN_F9R2_FB8_Msk                                /*!<Filter bit 8 */
5193 #define CAN_F9R2_FB9_Pos       (9U)
5194 #define CAN_F9R2_FB9_Msk       (0x1UL << CAN_F9R2_FB9_Pos)                      /*!< 0x00000200 */
5195 #define CAN_F9R2_FB9           CAN_F9R2_FB9_Msk                                /*!<Filter bit 9 */
5196 #define CAN_F9R2_FB10_Pos      (10U)
5197 #define CAN_F9R2_FB10_Msk      (0x1UL << CAN_F9R2_FB10_Pos)                     /*!< 0x00000400 */
5198 #define CAN_F9R2_FB10          CAN_F9R2_FB10_Msk                               /*!<Filter bit 10 */
5199 #define CAN_F9R2_FB11_Pos      (11U)
5200 #define CAN_F9R2_FB11_Msk      (0x1UL << CAN_F9R2_FB11_Pos)                     /*!< 0x00000800 */
5201 #define CAN_F9R2_FB11          CAN_F9R2_FB11_Msk                               /*!<Filter bit 11 */
5202 #define CAN_F9R2_FB12_Pos      (12U)
5203 #define CAN_F9R2_FB12_Msk      (0x1UL << CAN_F9R2_FB12_Pos)                     /*!< 0x00001000 */
5204 #define CAN_F9R2_FB12          CAN_F9R2_FB12_Msk                               /*!<Filter bit 12 */
5205 #define CAN_F9R2_FB13_Pos      (13U)
5206 #define CAN_F9R2_FB13_Msk      (0x1UL << CAN_F9R2_FB13_Pos)                     /*!< 0x00002000 */
5207 #define CAN_F9R2_FB13          CAN_F9R2_FB13_Msk                               /*!<Filter bit 13 */
5208 #define CAN_F9R2_FB14_Pos      (14U)
5209 #define CAN_F9R2_FB14_Msk      (0x1UL << CAN_F9R2_FB14_Pos)                     /*!< 0x00004000 */
5210 #define CAN_F9R2_FB14          CAN_F9R2_FB14_Msk                               /*!<Filter bit 14 */
5211 #define CAN_F9R2_FB15_Pos      (15U)
5212 #define CAN_F9R2_FB15_Msk      (0x1UL << CAN_F9R2_FB15_Pos)                     /*!< 0x00008000 */
5213 #define CAN_F9R2_FB15          CAN_F9R2_FB15_Msk                               /*!<Filter bit 15 */
5214 #define CAN_F9R2_FB16_Pos      (16U)
5215 #define CAN_F9R2_FB16_Msk      (0x1UL << CAN_F9R2_FB16_Pos)                     /*!< 0x00010000 */
5216 #define CAN_F9R2_FB16          CAN_F9R2_FB16_Msk                               /*!<Filter bit 16 */
5217 #define CAN_F9R2_FB17_Pos      (17U)
5218 #define CAN_F9R2_FB17_Msk      (0x1UL << CAN_F9R2_FB17_Pos)                     /*!< 0x00020000 */
5219 #define CAN_F9R2_FB17          CAN_F9R2_FB17_Msk                               /*!<Filter bit 17 */
5220 #define CAN_F9R2_FB18_Pos      (18U)
5221 #define CAN_F9R2_FB18_Msk      (0x1UL << CAN_F9R2_FB18_Pos)                     /*!< 0x00040000 */
5222 #define CAN_F9R2_FB18          CAN_F9R2_FB18_Msk                               /*!<Filter bit 18 */
5223 #define CAN_F9R2_FB19_Pos      (19U)
5224 #define CAN_F9R2_FB19_Msk      (0x1UL << CAN_F9R2_FB19_Pos)                     /*!< 0x00080000 */
5225 #define CAN_F9R2_FB19          CAN_F9R2_FB19_Msk                               /*!<Filter bit 19 */
5226 #define CAN_F9R2_FB20_Pos      (20U)
5227 #define CAN_F9R2_FB20_Msk      (0x1UL << CAN_F9R2_FB20_Pos)                     /*!< 0x00100000 */
5228 #define CAN_F9R2_FB20          CAN_F9R2_FB20_Msk                               /*!<Filter bit 20 */
5229 #define CAN_F9R2_FB21_Pos      (21U)
5230 #define CAN_F9R2_FB21_Msk      (0x1UL << CAN_F9R2_FB21_Pos)                     /*!< 0x00200000 */
5231 #define CAN_F9R2_FB21          CAN_F9R2_FB21_Msk                               /*!<Filter bit 21 */
5232 #define CAN_F9R2_FB22_Pos      (22U)
5233 #define CAN_F9R2_FB22_Msk      (0x1UL << CAN_F9R2_FB22_Pos)                     /*!< 0x00400000 */
5234 #define CAN_F9R2_FB22          CAN_F9R2_FB22_Msk                               /*!<Filter bit 22 */
5235 #define CAN_F9R2_FB23_Pos      (23U)
5236 #define CAN_F9R2_FB23_Msk      (0x1UL << CAN_F9R2_FB23_Pos)                     /*!< 0x00800000 */
5237 #define CAN_F9R2_FB23          CAN_F9R2_FB23_Msk                               /*!<Filter bit 23 */
5238 #define CAN_F9R2_FB24_Pos      (24U)
5239 #define CAN_F9R2_FB24_Msk      (0x1UL << CAN_F9R2_FB24_Pos)                     /*!< 0x01000000 */
5240 #define CAN_F9R2_FB24          CAN_F9R2_FB24_Msk                               /*!<Filter bit 24 */
5241 #define CAN_F9R2_FB25_Pos      (25U)
5242 #define CAN_F9R2_FB25_Msk      (0x1UL << CAN_F9R2_FB25_Pos)                     /*!< 0x02000000 */
5243 #define CAN_F9R2_FB25          CAN_F9R2_FB25_Msk                               /*!<Filter bit 25 */
5244 #define CAN_F9R2_FB26_Pos      (26U)
5245 #define CAN_F9R2_FB26_Msk      (0x1UL << CAN_F9R2_FB26_Pos)                     /*!< 0x04000000 */
5246 #define CAN_F9R2_FB26          CAN_F9R2_FB26_Msk                               /*!<Filter bit 26 */
5247 #define CAN_F9R2_FB27_Pos      (27U)
5248 #define CAN_F9R2_FB27_Msk      (0x1UL << CAN_F9R2_FB27_Pos)                     /*!< 0x08000000 */
5249 #define CAN_F9R2_FB27          CAN_F9R2_FB27_Msk                               /*!<Filter bit 27 */
5250 #define CAN_F9R2_FB28_Pos      (28U)
5251 #define CAN_F9R2_FB28_Msk      (0x1UL << CAN_F9R2_FB28_Pos)                     /*!< 0x10000000 */
5252 #define CAN_F9R2_FB28          CAN_F9R2_FB28_Msk                               /*!<Filter bit 28 */
5253 #define CAN_F9R2_FB29_Pos      (29U)
5254 #define CAN_F9R2_FB29_Msk      (0x1UL << CAN_F9R2_FB29_Pos)                     /*!< 0x20000000 */
5255 #define CAN_F9R2_FB29          CAN_F9R2_FB29_Msk                               /*!<Filter bit 29 */
5256 #define CAN_F9R2_FB30_Pos      (30U)
5257 #define CAN_F9R2_FB30_Msk      (0x1UL << CAN_F9R2_FB30_Pos)                     /*!< 0x40000000 */
5258 #define CAN_F9R2_FB30          CAN_F9R2_FB30_Msk                               /*!<Filter bit 30 */
5259 #define CAN_F9R2_FB31_Pos      (31U)
5260 #define CAN_F9R2_FB31_Msk      (0x1UL << CAN_F9R2_FB31_Pos)                     /*!< 0x80000000 */
5261 #define CAN_F9R2_FB31          CAN_F9R2_FB31_Msk                               /*!<Filter bit 31 */
5262 
5263 /*******************  Bit definition for CAN_F10R2 register  ******************/
5264 #define CAN_F10R2_FB0_Pos      (0U)
5265 #define CAN_F10R2_FB0_Msk      (0x1UL << CAN_F10R2_FB0_Pos)                     /*!< 0x00000001 */
5266 #define CAN_F10R2_FB0          CAN_F10R2_FB0_Msk                               /*!<Filter bit 0 */
5267 #define CAN_F10R2_FB1_Pos      (1U)
5268 #define CAN_F10R2_FB1_Msk      (0x1UL << CAN_F10R2_FB1_Pos)                     /*!< 0x00000002 */
5269 #define CAN_F10R2_FB1          CAN_F10R2_FB1_Msk                               /*!<Filter bit 1 */
5270 #define CAN_F10R2_FB2_Pos      (2U)
5271 #define CAN_F10R2_FB2_Msk      (0x1UL << CAN_F10R2_FB2_Pos)                     /*!< 0x00000004 */
5272 #define CAN_F10R2_FB2          CAN_F10R2_FB2_Msk                               /*!<Filter bit 2 */
5273 #define CAN_F10R2_FB3_Pos      (3U)
5274 #define CAN_F10R2_FB3_Msk      (0x1UL << CAN_F10R2_FB3_Pos)                     /*!< 0x00000008 */
5275 #define CAN_F10R2_FB3          CAN_F10R2_FB3_Msk                               /*!<Filter bit 3 */
5276 #define CAN_F10R2_FB4_Pos      (4U)
5277 #define CAN_F10R2_FB4_Msk      (0x1UL << CAN_F10R2_FB4_Pos)                     /*!< 0x00000010 */
5278 #define CAN_F10R2_FB4          CAN_F10R2_FB4_Msk                               /*!<Filter bit 4 */
5279 #define CAN_F10R2_FB5_Pos      (5U)
5280 #define CAN_F10R2_FB5_Msk      (0x1UL << CAN_F10R2_FB5_Pos)                     /*!< 0x00000020 */
5281 #define CAN_F10R2_FB5          CAN_F10R2_FB5_Msk                               /*!<Filter bit 5 */
5282 #define CAN_F10R2_FB6_Pos      (6U)
5283 #define CAN_F10R2_FB6_Msk      (0x1UL << CAN_F10R2_FB6_Pos)                     /*!< 0x00000040 */
5284 #define CAN_F10R2_FB6          CAN_F10R2_FB6_Msk                               /*!<Filter bit 6 */
5285 #define CAN_F10R2_FB7_Pos      (7U)
5286 #define CAN_F10R2_FB7_Msk      (0x1UL << CAN_F10R2_FB7_Pos)                     /*!< 0x00000080 */
5287 #define CAN_F10R2_FB7          CAN_F10R2_FB7_Msk                               /*!<Filter bit 7 */
5288 #define CAN_F10R2_FB8_Pos      (8U)
5289 #define CAN_F10R2_FB8_Msk      (0x1UL << CAN_F10R2_FB8_Pos)                     /*!< 0x00000100 */
5290 #define CAN_F10R2_FB8          CAN_F10R2_FB8_Msk                               /*!<Filter bit 8 */
5291 #define CAN_F10R2_FB9_Pos      (9U)
5292 #define CAN_F10R2_FB9_Msk      (0x1UL << CAN_F10R2_FB9_Pos)                     /*!< 0x00000200 */
5293 #define CAN_F10R2_FB9          CAN_F10R2_FB9_Msk                               /*!<Filter bit 9 */
5294 #define CAN_F10R2_FB10_Pos     (10U)
5295 #define CAN_F10R2_FB10_Msk     (0x1UL << CAN_F10R2_FB10_Pos)                    /*!< 0x00000400 */
5296 #define CAN_F10R2_FB10         CAN_F10R2_FB10_Msk                              /*!<Filter bit 10 */
5297 #define CAN_F10R2_FB11_Pos     (11U)
5298 #define CAN_F10R2_FB11_Msk     (0x1UL << CAN_F10R2_FB11_Pos)                    /*!< 0x00000800 */
5299 #define CAN_F10R2_FB11         CAN_F10R2_FB11_Msk                              /*!<Filter bit 11 */
5300 #define CAN_F10R2_FB12_Pos     (12U)
5301 #define CAN_F10R2_FB12_Msk     (0x1UL << CAN_F10R2_FB12_Pos)                    /*!< 0x00001000 */
5302 #define CAN_F10R2_FB12         CAN_F10R2_FB12_Msk                              /*!<Filter bit 12 */
5303 #define CAN_F10R2_FB13_Pos     (13U)
5304 #define CAN_F10R2_FB13_Msk     (0x1UL << CAN_F10R2_FB13_Pos)                    /*!< 0x00002000 */
5305 #define CAN_F10R2_FB13         CAN_F10R2_FB13_Msk                              /*!<Filter bit 13 */
5306 #define CAN_F10R2_FB14_Pos     (14U)
5307 #define CAN_F10R2_FB14_Msk     (0x1UL << CAN_F10R2_FB14_Pos)                    /*!< 0x00004000 */
5308 #define CAN_F10R2_FB14         CAN_F10R2_FB14_Msk                              /*!<Filter bit 14 */
5309 #define CAN_F10R2_FB15_Pos     (15U)
5310 #define CAN_F10R2_FB15_Msk     (0x1UL << CAN_F10R2_FB15_Pos)                    /*!< 0x00008000 */
5311 #define CAN_F10R2_FB15         CAN_F10R2_FB15_Msk                              /*!<Filter bit 15 */
5312 #define CAN_F10R2_FB16_Pos     (16U)
5313 #define CAN_F10R2_FB16_Msk     (0x1UL << CAN_F10R2_FB16_Pos)                    /*!< 0x00010000 */
5314 #define CAN_F10R2_FB16         CAN_F10R2_FB16_Msk                              /*!<Filter bit 16 */
5315 #define CAN_F10R2_FB17_Pos     (17U)
5316 #define CAN_F10R2_FB17_Msk     (0x1UL << CAN_F10R2_FB17_Pos)                    /*!< 0x00020000 */
5317 #define CAN_F10R2_FB17         CAN_F10R2_FB17_Msk                              /*!<Filter bit 17 */
5318 #define CAN_F10R2_FB18_Pos     (18U)
5319 #define CAN_F10R2_FB18_Msk     (0x1UL << CAN_F10R2_FB18_Pos)                    /*!< 0x00040000 */
5320 #define CAN_F10R2_FB18         CAN_F10R2_FB18_Msk                              /*!<Filter bit 18 */
5321 #define CAN_F10R2_FB19_Pos     (19U)
5322 #define CAN_F10R2_FB19_Msk     (0x1UL << CAN_F10R2_FB19_Pos)                    /*!< 0x00080000 */
5323 #define CAN_F10R2_FB19         CAN_F10R2_FB19_Msk                              /*!<Filter bit 19 */
5324 #define CAN_F10R2_FB20_Pos     (20U)
5325 #define CAN_F10R2_FB20_Msk     (0x1UL << CAN_F10R2_FB20_Pos)                    /*!< 0x00100000 */
5326 #define CAN_F10R2_FB20         CAN_F10R2_FB20_Msk                              /*!<Filter bit 20 */
5327 #define CAN_F10R2_FB21_Pos     (21U)
5328 #define CAN_F10R2_FB21_Msk     (0x1UL << CAN_F10R2_FB21_Pos)                    /*!< 0x00200000 */
5329 #define CAN_F10R2_FB21         CAN_F10R2_FB21_Msk                              /*!<Filter bit 21 */
5330 #define CAN_F10R2_FB22_Pos     (22U)
5331 #define CAN_F10R2_FB22_Msk     (0x1UL << CAN_F10R2_FB22_Pos)                    /*!< 0x00400000 */
5332 #define CAN_F10R2_FB22         CAN_F10R2_FB22_Msk                              /*!<Filter bit 22 */
5333 #define CAN_F10R2_FB23_Pos     (23U)
5334 #define CAN_F10R2_FB23_Msk     (0x1UL << CAN_F10R2_FB23_Pos)                    /*!< 0x00800000 */
5335 #define CAN_F10R2_FB23         CAN_F10R2_FB23_Msk                              /*!<Filter bit 23 */
5336 #define CAN_F10R2_FB24_Pos     (24U)
5337 #define CAN_F10R2_FB24_Msk     (0x1UL << CAN_F10R2_FB24_Pos)                    /*!< 0x01000000 */
5338 #define CAN_F10R2_FB24         CAN_F10R2_FB24_Msk                              /*!<Filter bit 24 */
5339 #define CAN_F10R2_FB25_Pos     (25U)
5340 #define CAN_F10R2_FB25_Msk     (0x1UL << CAN_F10R2_FB25_Pos)                    /*!< 0x02000000 */
5341 #define CAN_F10R2_FB25         CAN_F10R2_FB25_Msk                              /*!<Filter bit 25 */
5342 #define CAN_F10R2_FB26_Pos     (26U)
5343 #define CAN_F10R2_FB26_Msk     (0x1UL << CAN_F10R2_FB26_Pos)                    /*!< 0x04000000 */
5344 #define CAN_F10R2_FB26         CAN_F10R2_FB26_Msk                              /*!<Filter bit 26 */
5345 #define CAN_F10R2_FB27_Pos     (27U)
5346 #define CAN_F10R2_FB27_Msk     (0x1UL << CAN_F10R2_FB27_Pos)                    /*!< 0x08000000 */
5347 #define CAN_F10R2_FB27         CAN_F10R2_FB27_Msk                              /*!<Filter bit 27 */
5348 #define CAN_F10R2_FB28_Pos     (28U)
5349 #define CAN_F10R2_FB28_Msk     (0x1UL << CAN_F10R2_FB28_Pos)                    /*!< 0x10000000 */
5350 #define CAN_F10R2_FB28         CAN_F10R2_FB28_Msk                              /*!<Filter bit 28 */
5351 #define CAN_F10R2_FB29_Pos     (29U)
5352 #define CAN_F10R2_FB29_Msk     (0x1UL << CAN_F10R2_FB29_Pos)                    /*!< 0x20000000 */
5353 #define CAN_F10R2_FB29         CAN_F10R2_FB29_Msk                              /*!<Filter bit 29 */
5354 #define CAN_F10R2_FB30_Pos     (30U)
5355 #define CAN_F10R2_FB30_Msk     (0x1UL << CAN_F10R2_FB30_Pos)                    /*!< 0x40000000 */
5356 #define CAN_F10R2_FB30         CAN_F10R2_FB30_Msk                              /*!<Filter bit 30 */
5357 #define CAN_F10R2_FB31_Pos     (31U)
5358 #define CAN_F10R2_FB31_Msk     (0x1UL << CAN_F10R2_FB31_Pos)                    /*!< 0x80000000 */
5359 #define CAN_F10R2_FB31         CAN_F10R2_FB31_Msk                              /*!<Filter bit 31 */
5360 
5361 /*******************  Bit definition for CAN_F11R2 register  ******************/
5362 #define CAN_F11R2_FB0_Pos      (0U)
5363 #define CAN_F11R2_FB0_Msk      (0x1UL << CAN_F11R2_FB0_Pos)                     /*!< 0x00000001 */
5364 #define CAN_F11R2_FB0          CAN_F11R2_FB0_Msk                               /*!<Filter bit 0 */
5365 #define CAN_F11R2_FB1_Pos      (1U)
5366 #define CAN_F11R2_FB1_Msk      (0x1UL << CAN_F11R2_FB1_Pos)                     /*!< 0x00000002 */
5367 #define CAN_F11R2_FB1          CAN_F11R2_FB1_Msk                               /*!<Filter bit 1 */
5368 #define CAN_F11R2_FB2_Pos      (2U)
5369 #define CAN_F11R2_FB2_Msk      (0x1UL << CAN_F11R2_FB2_Pos)                     /*!< 0x00000004 */
5370 #define CAN_F11R2_FB2          CAN_F11R2_FB2_Msk                               /*!<Filter bit 2 */
5371 #define CAN_F11R2_FB3_Pos      (3U)
5372 #define CAN_F11R2_FB3_Msk      (0x1UL << CAN_F11R2_FB3_Pos)                     /*!< 0x00000008 */
5373 #define CAN_F11R2_FB3          CAN_F11R2_FB3_Msk                               /*!<Filter bit 3 */
5374 #define CAN_F11R2_FB4_Pos      (4U)
5375 #define CAN_F11R2_FB4_Msk      (0x1UL << CAN_F11R2_FB4_Pos)                     /*!< 0x00000010 */
5376 #define CAN_F11R2_FB4          CAN_F11R2_FB4_Msk                               /*!<Filter bit 4 */
5377 #define CAN_F11R2_FB5_Pos      (5U)
5378 #define CAN_F11R2_FB5_Msk      (0x1UL << CAN_F11R2_FB5_Pos)                     /*!< 0x00000020 */
5379 #define CAN_F11R2_FB5          CAN_F11R2_FB5_Msk                               /*!<Filter bit 5 */
5380 #define CAN_F11R2_FB6_Pos      (6U)
5381 #define CAN_F11R2_FB6_Msk      (0x1UL << CAN_F11R2_FB6_Pos)                     /*!< 0x00000040 */
5382 #define CAN_F11R2_FB6          CAN_F11R2_FB6_Msk                               /*!<Filter bit 6 */
5383 #define CAN_F11R2_FB7_Pos      (7U)
5384 #define CAN_F11R2_FB7_Msk      (0x1UL << CAN_F11R2_FB7_Pos)                     /*!< 0x00000080 */
5385 #define CAN_F11R2_FB7          CAN_F11R2_FB7_Msk                               /*!<Filter bit 7 */
5386 #define CAN_F11R2_FB8_Pos      (8U)
5387 #define CAN_F11R2_FB8_Msk      (0x1UL << CAN_F11R2_FB8_Pos)                     /*!< 0x00000100 */
5388 #define CAN_F11R2_FB8          CAN_F11R2_FB8_Msk                               /*!<Filter bit 8 */
5389 #define CAN_F11R2_FB9_Pos      (9U)
5390 #define CAN_F11R2_FB9_Msk      (0x1UL << CAN_F11R2_FB9_Pos)                     /*!< 0x00000200 */
5391 #define CAN_F11R2_FB9          CAN_F11R2_FB9_Msk                               /*!<Filter bit 9 */
5392 #define CAN_F11R2_FB10_Pos     (10U)
5393 #define CAN_F11R2_FB10_Msk     (0x1UL << CAN_F11R2_FB10_Pos)                    /*!< 0x00000400 */
5394 #define CAN_F11R2_FB10         CAN_F11R2_FB10_Msk                              /*!<Filter bit 10 */
5395 #define CAN_F11R2_FB11_Pos     (11U)
5396 #define CAN_F11R2_FB11_Msk     (0x1UL << CAN_F11R2_FB11_Pos)                    /*!< 0x00000800 */
5397 #define CAN_F11R2_FB11         CAN_F11R2_FB11_Msk                              /*!<Filter bit 11 */
5398 #define CAN_F11R2_FB12_Pos     (12U)
5399 #define CAN_F11R2_FB12_Msk     (0x1UL << CAN_F11R2_FB12_Pos)                    /*!< 0x00001000 */
5400 #define CAN_F11R2_FB12         CAN_F11R2_FB12_Msk                              /*!<Filter bit 12 */
5401 #define CAN_F11R2_FB13_Pos     (13U)
5402 #define CAN_F11R2_FB13_Msk     (0x1UL << CAN_F11R2_FB13_Pos)                    /*!< 0x00002000 */
5403 #define CAN_F11R2_FB13         CAN_F11R2_FB13_Msk                              /*!<Filter bit 13 */
5404 #define CAN_F11R2_FB14_Pos     (14U)
5405 #define CAN_F11R2_FB14_Msk     (0x1UL << CAN_F11R2_FB14_Pos)                    /*!< 0x00004000 */
5406 #define CAN_F11R2_FB14         CAN_F11R2_FB14_Msk                              /*!<Filter bit 14 */
5407 #define CAN_F11R2_FB15_Pos     (15U)
5408 #define CAN_F11R2_FB15_Msk     (0x1UL << CAN_F11R2_FB15_Pos)                    /*!< 0x00008000 */
5409 #define CAN_F11R2_FB15         CAN_F11R2_FB15_Msk                              /*!<Filter bit 15 */
5410 #define CAN_F11R2_FB16_Pos     (16U)
5411 #define CAN_F11R2_FB16_Msk     (0x1UL << CAN_F11R2_FB16_Pos)                    /*!< 0x00010000 */
5412 #define CAN_F11R2_FB16         CAN_F11R2_FB16_Msk                              /*!<Filter bit 16 */
5413 #define CAN_F11R2_FB17_Pos     (17U)
5414 #define CAN_F11R2_FB17_Msk     (0x1UL << CAN_F11R2_FB17_Pos)                    /*!< 0x00020000 */
5415 #define CAN_F11R2_FB17         CAN_F11R2_FB17_Msk                              /*!<Filter bit 17 */
5416 #define CAN_F11R2_FB18_Pos     (18U)
5417 #define CAN_F11R2_FB18_Msk     (0x1UL << CAN_F11R2_FB18_Pos)                    /*!< 0x00040000 */
5418 #define CAN_F11R2_FB18         CAN_F11R2_FB18_Msk                              /*!<Filter bit 18 */
5419 #define CAN_F11R2_FB19_Pos     (19U)
5420 #define CAN_F11R2_FB19_Msk     (0x1UL << CAN_F11R2_FB19_Pos)                    /*!< 0x00080000 */
5421 #define CAN_F11R2_FB19         CAN_F11R2_FB19_Msk                              /*!<Filter bit 19 */
5422 #define CAN_F11R2_FB20_Pos     (20U)
5423 #define CAN_F11R2_FB20_Msk     (0x1UL << CAN_F11R2_FB20_Pos)                    /*!< 0x00100000 */
5424 #define CAN_F11R2_FB20         CAN_F11R2_FB20_Msk                              /*!<Filter bit 20 */
5425 #define CAN_F11R2_FB21_Pos     (21U)
5426 #define CAN_F11R2_FB21_Msk     (0x1UL << CAN_F11R2_FB21_Pos)                    /*!< 0x00200000 */
5427 #define CAN_F11R2_FB21         CAN_F11R2_FB21_Msk                              /*!<Filter bit 21 */
5428 #define CAN_F11R2_FB22_Pos     (22U)
5429 #define CAN_F11R2_FB22_Msk     (0x1UL << CAN_F11R2_FB22_Pos)                    /*!< 0x00400000 */
5430 #define CAN_F11R2_FB22         CAN_F11R2_FB22_Msk                              /*!<Filter bit 22 */
5431 #define CAN_F11R2_FB23_Pos     (23U)
5432 #define CAN_F11R2_FB23_Msk     (0x1UL << CAN_F11R2_FB23_Pos)                    /*!< 0x00800000 */
5433 #define CAN_F11R2_FB23         CAN_F11R2_FB23_Msk                              /*!<Filter bit 23 */
5434 #define CAN_F11R2_FB24_Pos     (24U)
5435 #define CAN_F11R2_FB24_Msk     (0x1UL << CAN_F11R2_FB24_Pos)                    /*!< 0x01000000 */
5436 #define CAN_F11R2_FB24         CAN_F11R2_FB24_Msk                              /*!<Filter bit 24 */
5437 #define CAN_F11R2_FB25_Pos     (25U)
5438 #define CAN_F11R2_FB25_Msk     (0x1UL << CAN_F11R2_FB25_Pos)                    /*!< 0x02000000 */
5439 #define CAN_F11R2_FB25         CAN_F11R2_FB25_Msk                              /*!<Filter bit 25 */
5440 #define CAN_F11R2_FB26_Pos     (26U)
5441 #define CAN_F11R2_FB26_Msk     (0x1UL << CAN_F11R2_FB26_Pos)                    /*!< 0x04000000 */
5442 #define CAN_F11R2_FB26         CAN_F11R2_FB26_Msk                              /*!<Filter bit 26 */
5443 #define CAN_F11R2_FB27_Pos     (27U)
5444 #define CAN_F11R2_FB27_Msk     (0x1UL << CAN_F11R2_FB27_Pos)                    /*!< 0x08000000 */
5445 #define CAN_F11R2_FB27         CAN_F11R2_FB27_Msk                              /*!<Filter bit 27 */
5446 #define CAN_F11R2_FB28_Pos     (28U)
5447 #define CAN_F11R2_FB28_Msk     (0x1UL << CAN_F11R2_FB28_Pos)                    /*!< 0x10000000 */
5448 #define CAN_F11R2_FB28         CAN_F11R2_FB28_Msk                              /*!<Filter bit 28 */
5449 #define CAN_F11R2_FB29_Pos     (29U)
5450 #define CAN_F11R2_FB29_Msk     (0x1UL << CAN_F11R2_FB29_Pos)                    /*!< 0x20000000 */
5451 #define CAN_F11R2_FB29         CAN_F11R2_FB29_Msk                              /*!<Filter bit 29 */
5452 #define CAN_F11R2_FB30_Pos     (30U)
5453 #define CAN_F11R2_FB30_Msk     (0x1UL << CAN_F11R2_FB30_Pos)                    /*!< 0x40000000 */
5454 #define CAN_F11R2_FB30         CAN_F11R2_FB30_Msk                              /*!<Filter bit 30 */
5455 #define CAN_F11R2_FB31_Pos     (31U)
5456 #define CAN_F11R2_FB31_Msk     (0x1UL << CAN_F11R2_FB31_Pos)                    /*!< 0x80000000 */
5457 #define CAN_F11R2_FB31         CAN_F11R2_FB31_Msk                              /*!<Filter bit 31 */
5458 
5459 /*******************  Bit definition for CAN_F12R2 register  ******************/
5460 #define CAN_F12R2_FB0_Pos      (0U)
5461 #define CAN_F12R2_FB0_Msk      (0x1UL << CAN_F12R2_FB0_Pos)                     /*!< 0x00000001 */
5462 #define CAN_F12R2_FB0          CAN_F12R2_FB0_Msk                               /*!<Filter bit 0 */
5463 #define CAN_F12R2_FB1_Pos      (1U)
5464 #define CAN_F12R2_FB1_Msk      (0x1UL << CAN_F12R2_FB1_Pos)                     /*!< 0x00000002 */
5465 #define CAN_F12R2_FB1          CAN_F12R2_FB1_Msk                               /*!<Filter bit 1 */
5466 #define CAN_F12R2_FB2_Pos      (2U)
5467 #define CAN_F12R2_FB2_Msk      (0x1UL << CAN_F12R2_FB2_Pos)                     /*!< 0x00000004 */
5468 #define CAN_F12R2_FB2          CAN_F12R2_FB2_Msk                               /*!<Filter bit 2 */
5469 #define CAN_F12R2_FB3_Pos      (3U)
5470 #define CAN_F12R2_FB3_Msk      (0x1UL << CAN_F12R2_FB3_Pos)                     /*!< 0x00000008 */
5471 #define CAN_F12R2_FB3          CAN_F12R2_FB3_Msk                               /*!<Filter bit 3 */
5472 #define CAN_F12R2_FB4_Pos      (4U)
5473 #define CAN_F12R2_FB4_Msk      (0x1UL << CAN_F12R2_FB4_Pos)                     /*!< 0x00000010 */
5474 #define CAN_F12R2_FB4          CAN_F12R2_FB4_Msk                               /*!<Filter bit 4 */
5475 #define CAN_F12R2_FB5_Pos      (5U)
5476 #define CAN_F12R2_FB5_Msk      (0x1UL << CAN_F12R2_FB5_Pos)                     /*!< 0x00000020 */
5477 #define CAN_F12R2_FB5          CAN_F12R2_FB5_Msk                               /*!<Filter bit 5 */
5478 #define CAN_F12R2_FB6_Pos      (6U)
5479 #define CAN_F12R2_FB6_Msk      (0x1UL << CAN_F12R2_FB6_Pos)                     /*!< 0x00000040 */
5480 #define CAN_F12R2_FB6          CAN_F12R2_FB6_Msk                               /*!<Filter bit 6 */
5481 #define CAN_F12R2_FB7_Pos      (7U)
5482 #define CAN_F12R2_FB7_Msk      (0x1UL << CAN_F12R2_FB7_Pos)                     /*!< 0x00000080 */
5483 #define CAN_F12R2_FB7          CAN_F12R2_FB7_Msk                               /*!<Filter bit 7 */
5484 #define CAN_F12R2_FB8_Pos      (8U)
5485 #define CAN_F12R2_FB8_Msk      (0x1UL << CAN_F12R2_FB8_Pos)                     /*!< 0x00000100 */
5486 #define CAN_F12R2_FB8          CAN_F12R2_FB8_Msk                               /*!<Filter bit 8 */
5487 #define CAN_F12R2_FB9_Pos      (9U)
5488 #define CAN_F12R2_FB9_Msk      (0x1UL << CAN_F12R2_FB9_Pos)                     /*!< 0x00000200 */
5489 #define CAN_F12R2_FB9          CAN_F12R2_FB9_Msk                               /*!<Filter bit 9 */
5490 #define CAN_F12R2_FB10_Pos     (10U)
5491 #define CAN_F12R2_FB10_Msk     (0x1UL << CAN_F12R2_FB10_Pos)                    /*!< 0x00000400 */
5492 #define CAN_F12R2_FB10         CAN_F12R2_FB10_Msk                              /*!<Filter bit 10 */
5493 #define CAN_F12R2_FB11_Pos     (11U)
5494 #define CAN_F12R2_FB11_Msk     (0x1UL << CAN_F12R2_FB11_Pos)                    /*!< 0x00000800 */
5495 #define CAN_F12R2_FB11         CAN_F12R2_FB11_Msk                              /*!<Filter bit 11 */
5496 #define CAN_F12R2_FB12_Pos     (12U)
5497 #define CAN_F12R2_FB12_Msk     (0x1UL << CAN_F12R2_FB12_Pos)                    /*!< 0x00001000 */
5498 #define CAN_F12R2_FB12         CAN_F12R2_FB12_Msk                              /*!<Filter bit 12 */
5499 #define CAN_F12R2_FB13_Pos     (13U)
5500 #define CAN_F12R2_FB13_Msk     (0x1UL << CAN_F12R2_FB13_Pos)                    /*!< 0x00002000 */
5501 #define CAN_F12R2_FB13         CAN_F12R2_FB13_Msk                              /*!<Filter bit 13 */
5502 #define CAN_F12R2_FB14_Pos     (14U)
5503 #define CAN_F12R2_FB14_Msk     (0x1UL << CAN_F12R2_FB14_Pos)                    /*!< 0x00004000 */
5504 #define CAN_F12R2_FB14         CAN_F12R2_FB14_Msk                              /*!<Filter bit 14 */
5505 #define CAN_F12R2_FB15_Pos     (15U)
5506 #define CAN_F12R2_FB15_Msk     (0x1UL << CAN_F12R2_FB15_Pos)                    /*!< 0x00008000 */
5507 #define CAN_F12R2_FB15         CAN_F12R2_FB15_Msk                              /*!<Filter bit 15 */
5508 #define CAN_F12R2_FB16_Pos     (16U)
5509 #define CAN_F12R2_FB16_Msk     (0x1UL << CAN_F12R2_FB16_Pos)                    /*!< 0x00010000 */
5510 #define CAN_F12R2_FB16         CAN_F12R2_FB16_Msk                              /*!<Filter bit 16 */
5511 #define CAN_F12R2_FB17_Pos     (17U)
5512 #define CAN_F12R2_FB17_Msk     (0x1UL << CAN_F12R2_FB17_Pos)                    /*!< 0x00020000 */
5513 #define CAN_F12R2_FB17         CAN_F12R2_FB17_Msk                              /*!<Filter bit 17 */
5514 #define CAN_F12R2_FB18_Pos     (18U)
5515 #define CAN_F12R2_FB18_Msk     (0x1UL << CAN_F12R2_FB18_Pos)                    /*!< 0x00040000 */
5516 #define CAN_F12R2_FB18         CAN_F12R2_FB18_Msk                              /*!<Filter bit 18 */
5517 #define CAN_F12R2_FB19_Pos     (19U)
5518 #define CAN_F12R2_FB19_Msk     (0x1UL << CAN_F12R2_FB19_Pos)                    /*!< 0x00080000 */
5519 #define CAN_F12R2_FB19         CAN_F12R2_FB19_Msk                              /*!<Filter bit 19 */
5520 #define CAN_F12R2_FB20_Pos     (20U)
5521 #define CAN_F12R2_FB20_Msk     (0x1UL << CAN_F12R2_FB20_Pos)                    /*!< 0x00100000 */
5522 #define CAN_F12R2_FB20         CAN_F12R2_FB20_Msk                              /*!<Filter bit 20 */
5523 #define CAN_F12R2_FB21_Pos     (21U)
5524 #define CAN_F12R2_FB21_Msk     (0x1UL << CAN_F12R2_FB21_Pos)                    /*!< 0x00200000 */
5525 #define CAN_F12R2_FB21         CAN_F12R2_FB21_Msk                              /*!<Filter bit 21 */
5526 #define CAN_F12R2_FB22_Pos     (22U)
5527 #define CAN_F12R2_FB22_Msk     (0x1UL << CAN_F12R2_FB22_Pos)                    /*!< 0x00400000 */
5528 #define CAN_F12R2_FB22         CAN_F12R2_FB22_Msk                              /*!<Filter bit 22 */
5529 #define CAN_F12R2_FB23_Pos     (23U)
5530 #define CAN_F12R2_FB23_Msk     (0x1UL << CAN_F12R2_FB23_Pos)                    /*!< 0x00800000 */
5531 #define CAN_F12R2_FB23         CAN_F12R2_FB23_Msk                              /*!<Filter bit 23 */
5532 #define CAN_F12R2_FB24_Pos     (24U)
5533 #define CAN_F12R2_FB24_Msk     (0x1UL << CAN_F12R2_FB24_Pos)                    /*!< 0x01000000 */
5534 #define CAN_F12R2_FB24         CAN_F12R2_FB24_Msk                              /*!<Filter bit 24 */
5535 #define CAN_F12R2_FB25_Pos     (25U)
5536 #define CAN_F12R2_FB25_Msk     (0x1UL << CAN_F12R2_FB25_Pos)                    /*!< 0x02000000 */
5537 #define CAN_F12R2_FB25         CAN_F12R2_FB25_Msk                              /*!<Filter bit 25 */
5538 #define CAN_F12R2_FB26_Pos     (26U)
5539 #define CAN_F12R2_FB26_Msk     (0x1UL << CAN_F12R2_FB26_Pos)                    /*!< 0x04000000 */
5540 #define CAN_F12R2_FB26         CAN_F12R2_FB26_Msk                              /*!<Filter bit 26 */
5541 #define CAN_F12R2_FB27_Pos     (27U)
5542 #define CAN_F12R2_FB27_Msk     (0x1UL << CAN_F12R2_FB27_Pos)                    /*!< 0x08000000 */
5543 #define CAN_F12R2_FB27         CAN_F12R2_FB27_Msk                              /*!<Filter bit 27 */
5544 #define CAN_F12R2_FB28_Pos     (28U)
5545 #define CAN_F12R2_FB28_Msk     (0x1UL << CAN_F12R2_FB28_Pos)                    /*!< 0x10000000 */
5546 #define CAN_F12R2_FB28         CAN_F12R2_FB28_Msk                              /*!<Filter bit 28 */
5547 #define CAN_F12R2_FB29_Pos     (29U)
5548 #define CAN_F12R2_FB29_Msk     (0x1UL << CAN_F12R2_FB29_Pos)                    /*!< 0x20000000 */
5549 #define CAN_F12R2_FB29         CAN_F12R2_FB29_Msk                              /*!<Filter bit 29 */
5550 #define CAN_F12R2_FB30_Pos     (30U)
5551 #define CAN_F12R2_FB30_Msk     (0x1UL << CAN_F12R2_FB30_Pos)                    /*!< 0x40000000 */
5552 #define CAN_F12R2_FB30         CAN_F12R2_FB30_Msk                              /*!<Filter bit 30 */
5553 #define CAN_F12R2_FB31_Pos     (31U)
5554 #define CAN_F12R2_FB31_Msk     (0x1UL << CAN_F12R2_FB31_Pos)                    /*!< 0x80000000 */
5555 #define CAN_F12R2_FB31         CAN_F12R2_FB31_Msk                              /*!<Filter bit 31 */
5556 
5557 /*******************  Bit definition for CAN_F13R2 register  ******************/
5558 #define CAN_F13R2_FB0_Pos      (0U)
5559 #define CAN_F13R2_FB0_Msk      (0x1UL << CAN_F13R2_FB0_Pos)                     /*!< 0x00000001 */
5560 #define CAN_F13R2_FB0          CAN_F13R2_FB0_Msk                               /*!<Filter bit 0 */
5561 #define CAN_F13R2_FB1_Pos      (1U)
5562 #define CAN_F13R2_FB1_Msk      (0x1UL << CAN_F13R2_FB1_Pos)                     /*!< 0x00000002 */
5563 #define CAN_F13R2_FB1          CAN_F13R2_FB1_Msk                               /*!<Filter bit 1 */
5564 #define CAN_F13R2_FB2_Pos      (2U)
5565 #define CAN_F13R2_FB2_Msk      (0x1UL << CAN_F13R2_FB2_Pos)                     /*!< 0x00000004 */
5566 #define CAN_F13R2_FB2          CAN_F13R2_FB2_Msk                               /*!<Filter bit 2 */
5567 #define CAN_F13R2_FB3_Pos      (3U)
5568 #define CAN_F13R2_FB3_Msk      (0x1UL << CAN_F13R2_FB3_Pos)                     /*!< 0x00000008 */
5569 #define CAN_F13R2_FB3          CAN_F13R2_FB3_Msk                               /*!<Filter bit 3 */
5570 #define CAN_F13R2_FB4_Pos      (4U)
5571 #define CAN_F13R2_FB4_Msk      (0x1UL << CAN_F13R2_FB4_Pos)                     /*!< 0x00000010 */
5572 #define CAN_F13R2_FB4          CAN_F13R2_FB4_Msk                               /*!<Filter bit 4 */
5573 #define CAN_F13R2_FB5_Pos      (5U)
5574 #define CAN_F13R2_FB5_Msk      (0x1UL << CAN_F13R2_FB5_Pos)                     /*!< 0x00000020 */
5575 #define CAN_F13R2_FB5          CAN_F13R2_FB5_Msk                               /*!<Filter bit 5 */
5576 #define CAN_F13R2_FB6_Pos      (6U)
5577 #define CAN_F13R2_FB6_Msk      (0x1UL << CAN_F13R2_FB6_Pos)                     /*!< 0x00000040 */
5578 #define CAN_F13R2_FB6          CAN_F13R2_FB6_Msk                               /*!<Filter bit 6 */
5579 #define CAN_F13R2_FB7_Pos      (7U)
5580 #define CAN_F13R2_FB7_Msk      (0x1UL << CAN_F13R2_FB7_Pos)                     /*!< 0x00000080 */
5581 #define CAN_F13R2_FB7          CAN_F13R2_FB7_Msk                               /*!<Filter bit 7 */
5582 #define CAN_F13R2_FB8_Pos      (8U)
5583 #define CAN_F13R2_FB8_Msk      (0x1UL << CAN_F13R2_FB8_Pos)                     /*!< 0x00000100 */
5584 #define CAN_F13R2_FB8          CAN_F13R2_FB8_Msk                               /*!<Filter bit 8 */
5585 #define CAN_F13R2_FB9_Pos      (9U)
5586 #define CAN_F13R2_FB9_Msk      (0x1UL << CAN_F13R2_FB9_Pos)                     /*!< 0x00000200 */
5587 #define CAN_F13R2_FB9          CAN_F13R2_FB9_Msk                               /*!<Filter bit 9 */
5588 #define CAN_F13R2_FB10_Pos     (10U)
5589 #define CAN_F13R2_FB10_Msk     (0x1UL << CAN_F13R2_FB10_Pos)                    /*!< 0x00000400 */
5590 #define CAN_F13R2_FB10         CAN_F13R2_FB10_Msk                              /*!<Filter bit 10 */
5591 #define CAN_F13R2_FB11_Pos     (11U)
5592 #define CAN_F13R2_FB11_Msk     (0x1UL << CAN_F13R2_FB11_Pos)                    /*!< 0x00000800 */
5593 #define CAN_F13R2_FB11         CAN_F13R2_FB11_Msk                              /*!<Filter bit 11 */
5594 #define CAN_F13R2_FB12_Pos     (12U)
5595 #define CAN_F13R2_FB12_Msk     (0x1UL << CAN_F13R2_FB12_Pos)                    /*!< 0x00001000 */
5596 #define CAN_F13R2_FB12         CAN_F13R2_FB12_Msk                              /*!<Filter bit 12 */
5597 #define CAN_F13R2_FB13_Pos     (13U)
5598 #define CAN_F13R2_FB13_Msk     (0x1UL << CAN_F13R2_FB13_Pos)                    /*!< 0x00002000 */
5599 #define CAN_F13R2_FB13         CAN_F13R2_FB13_Msk                              /*!<Filter bit 13 */
5600 #define CAN_F13R2_FB14_Pos     (14U)
5601 #define CAN_F13R2_FB14_Msk     (0x1UL << CAN_F13R2_FB14_Pos)                    /*!< 0x00004000 */
5602 #define CAN_F13R2_FB14         CAN_F13R2_FB14_Msk                              /*!<Filter bit 14 */
5603 #define CAN_F13R2_FB15_Pos     (15U)
5604 #define CAN_F13R2_FB15_Msk     (0x1UL << CAN_F13R2_FB15_Pos)                    /*!< 0x00008000 */
5605 #define CAN_F13R2_FB15         CAN_F13R2_FB15_Msk                              /*!<Filter bit 15 */
5606 #define CAN_F13R2_FB16_Pos     (16U)
5607 #define CAN_F13R2_FB16_Msk     (0x1UL << CAN_F13R2_FB16_Pos)                    /*!< 0x00010000 */
5608 #define CAN_F13R2_FB16         CAN_F13R2_FB16_Msk                              /*!<Filter bit 16 */
5609 #define CAN_F13R2_FB17_Pos     (17U)
5610 #define CAN_F13R2_FB17_Msk     (0x1UL << CAN_F13R2_FB17_Pos)                    /*!< 0x00020000 */
5611 #define CAN_F13R2_FB17         CAN_F13R2_FB17_Msk                              /*!<Filter bit 17 */
5612 #define CAN_F13R2_FB18_Pos     (18U)
5613 #define CAN_F13R2_FB18_Msk     (0x1UL << CAN_F13R2_FB18_Pos)                    /*!< 0x00040000 */
5614 #define CAN_F13R2_FB18         CAN_F13R2_FB18_Msk                              /*!<Filter bit 18 */
5615 #define CAN_F13R2_FB19_Pos     (19U)
5616 #define CAN_F13R2_FB19_Msk     (0x1UL << CAN_F13R2_FB19_Pos)                    /*!< 0x00080000 */
5617 #define CAN_F13R2_FB19         CAN_F13R2_FB19_Msk                              /*!<Filter bit 19 */
5618 #define CAN_F13R2_FB20_Pos     (20U)
5619 #define CAN_F13R2_FB20_Msk     (0x1UL << CAN_F13R2_FB20_Pos)                    /*!< 0x00100000 */
5620 #define CAN_F13R2_FB20         CAN_F13R2_FB20_Msk                              /*!<Filter bit 20 */
5621 #define CAN_F13R2_FB21_Pos     (21U)
5622 #define CAN_F13R2_FB21_Msk     (0x1UL << CAN_F13R2_FB21_Pos)                    /*!< 0x00200000 */
5623 #define CAN_F13R2_FB21         CAN_F13R2_FB21_Msk                              /*!<Filter bit 21 */
5624 #define CAN_F13R2_FB22_Pos     (22U)
5625 #define CAN_F13R2_FB22_Msk     (0x1UL << CAN_F13R2_FB22_Pos)                    /*!< 0x00400000 */
5626 #define CAN_F13R2_FB22         CAN_F13R2_FB22_Msk                              /*!<Filter bit 22 */
5627 #define CAN_F13R2_FB23_Pos     (23U)
5628 #define CAN_F13R2_FB23_Msk     (0x1UL << CAN_F13R2_FB23_Pos)                    /*!< 0x00800000 */
5629 #define CAN_F13R2_FB23         CAN_F13R2_FB23_Msk                              /*!<Filter bit 23 */
5630 #define CAN_F13R2_FB24_Pos     (24U)
5631 #define CAN_F13R2_FB24_Msk     (0x1UL << CAN_F13R2_FB24_Pos)                    /*!< 0x01000000 */
5632 #define CAN_F13R2_FB24         CAN_F13R2_FB24_Msk                              /*!<Filter bit 24 */
5633 #define CAN_F13R2_FB25_Pos     (25U)
5634 #define CAN_F13R2_FB25_Msk     (0x1UL << CAN_F13R2_FB25_Pos)                    /*!< 0x02000000 */
5635 #define CAN_F13R2_FB25         CAN_F13R2_FB25_Msk                              /*!<Filter bit 25 */
5636 #define CAN_F13R2_FB26_Pos     (26U)
5637 #define CAN_F13R2_FB26_Msk     (0x1UL << CAN_F13R2_FB26_Pos)                    /*!< 0x04000000 */
5638 #define CAN_F13R2_FB26         CAN_F13R2_FB26_Msk                              /*!<Filter bit 26 */
5639 #define CAN_F13R2_FB27_Pos     (27U)
5640 #define CAN_F13R2_FB27_Msk     (0x1UL << CAN_F13R2_FB27_Pos)                    /*!< 0x08000000 */
5641 #define CAN_F13R2_FB27         CAN_F13R2_FB27_Msk                              /*!<Filter bit 27 */
5642 #define CAN_F13R2_FB28_Pos     (28U)
5643 #define CAN_F13R2_FB28_Msk     (0x1UL << CAN_F13R2_FB28_Pos)                    /*!< 0x10000000 */
5644 #define CAN_F13R2_FB28         CAN_F13R2_FB28_Msk                              /*!<Filter bit 28 */
5645 #define CAN_F13R2_FB29_Pos     (29U)
5646 #define CAN_F13R2_FB29_Msk     (0x1UL << CAN_F13R2_FB29_Pos)                    /*!< 0x20000000 */
5647 #define CAN_F13R2_FB29         CAN_F13R2_FB29_Msk                              /*!<Filter bit 29 */
5648 #define CAN_F13R2_FB30_Pos     (30U)
5649 #define CAN_F13R2_FB30_Msk     (0x1UL << CAN_F13R2_FB30_Pos)                    /*!< 0x40000000 */
5650 #define CAN_F13R2_FB30         CAN_F13R2_FB30_Msk                              /*!<Filter bit 30 */
5651 #define CAN_F13R2_FB31_Pos     (31U)
5652 #define CAN_F13R2_FB31_Msk     (0x1UL << CAN_F13R2_FB31_Pos)                    /*!< 0x80000000 */
5653 #define CAN_F13R2_FB31         CAN_F13R2_FB31_Msk                              /*!<Filter bit 31 */
5654 
5655 /******************************************************************************/
5656 /*                                                                            */
5657 /*                          CRC calculation unit                              */
5658 /*                                                                            */
5659 /******************************************************************************/
5660 /*******************  Bit definition for CRC_DR register  *********************/
5661 #define CRC_DR_DR_Pos       (0U)
5662 #define CRC_DR_DR_Msk       (0xFFFFFFFFUL << CRC_DR_DR_Pos)                     /*!< 0xFFFFFFFF */
5663 #define CRC_DR_DR           CRC_DR_DR_Msk                                      /*!< Data register bits */
5664 
5665 
5666 /*******************  Bit definition for CRC_IDR register  ********************/
5667 #define CRC_IDR_IDR_Pos     (0U)
5668 #define CRC_IDR_IDR_Msk     (0xFFUL << CRC_IDR_IDR_Pos)                         /*!< 0x000000FF */
5669 #define CRC_IDR_IDR         CRC_IDR_IDR_Msk                                    /*!< General-purpose 8-bit data register bits */
5670 
5671 
5672 /********************  Bit definition for CRC_CR register  ********************/
5673 #define CRC_CR_RESET_Pos    (0U)
5674 #define CRC_CR_RESET_Msk    (0x1UL << CRC_CR_RESET_Pos)                         /*!< 0x00000001 */
5675 #define CRC_CR_RESET        CRC_CR_RESET_Msk                                   /*!< RESET bit */
5676 
5677 /******************************************************************************/
5678 /*                                                                            */
5679 /*                      Digital to Analog Converter                           */
5680 /*                                                                            */
5681 /******************************************************************************/
5682 /*
5683  * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
5684  */
5685 #define DAC_CHANNEL2_SUPPORT                                    /*!< DAC feature available only on specific devices: availability of DAC channel 2 */
5686 /********************  Bit definition for DAC_CR register  ********************/
5687 #define DAC_CR_EN1_Pos              (0U)
5688 #define DAC_CR_EN1_Msk              (0x1UL << DAC_CR_EN1_Pos)                   /*!< 0x00000001 */
5689 #define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!<DAC channel1 enable */
5690 #define DAC_CR_BOFF1_Pos            (1U)
5691 #define DAC_CR_BOFF1_Msk            (0x1UL << DAC_CR_BOFF1_Pos)                 /*!< 0x00000002 */
5692 #define DAC_CR_BOFF1                DAC_CR_BOFF1_Msk                           /*!<DAC channel1 output buffer disable */
5693 #define DAC_CR_TEN1_Pos             (2U)
5694 #define DAC_CR_TEN1_Msk             (0x1UL << DAC_CR_TEN1_Pos)                  /*!< 0x00000004 */
5695 #define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!<DAC channel1 Trigger enable */
5696 
5697 #define DAC_CR_TSEL1_Pos            (3U)
5698 #define DAC_CR_TSEL1_Msk            (0x7UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000038 */
5699 #define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
5700 #define DAC_CR_TSEL1_0              (0x1UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000008 */
5701 #define DAC_CR_TSEL1_1              (0x2UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000010 */
5702 #define DAC_CR_TSEL1_2              (0x4UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000020 */
5703 
5704 #define DAC_CR_WAVE1_Pos            (6U)
5705 #define DAC_CR_WAVE1_Msk            (0x3UL << DAC_CR_WAVE1_Pos)                 /*!< 0x000000C0 */
5706 #define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
5707 #define DAC_CR_WAVE1_0              (0x1UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000040 */
5708 #define DAC_CR_WAVE1_1              (0x2UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000080 */
5709 
5710 #define DAC_CR_MAMP1_Pos            (8U)
5711 #define DAC_CR_MAMP1_Msk            (0xFUL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000F00 */
5712 #define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
5713 #define DAC_CR_MAMP1_0              (0x1UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000100 */
5714 #define DAC_CR_MAMP1_1              (0x2UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000200 */
5715 #define DAC_CR_MAMP1_2              (0x4UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000400 */
5716 #define DAC_CR_MAMP1_3              (0x8UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000800 */
5717 
5718 #define DAC_CR_DMAEN1_Pos           (12U)
5719 #define DAC_CR_DMAEN1_Msk           (0x1UL << DAC_CR_DMAEN1_Pos)                /*!< 0x00001000 */
5720 #define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!<DAC channel1 DMA enable */
5721 #define DAC_CR_DMAUDRIE1_Pos        (13U)
5722 #define DAC_CR_DMAUDRIE1_Msk        (0x1UL << DAC_CR_DMAUDRIE1_Pos)             /*!< 0x00002000 */
5723 #define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!<DAC channel1 DMA underrun interrupt enable*/
5724 #define DAC_CR_EN2_Pos              (16U)
5725 #define DAC_CR_EN2_Msk              (0x1UL << DAC_CR_EN2_Pos)                   /*!< 0x00010000 */
5726 #define DAC_CR_EN2                  DAC_CR_EN2_Msk                             /*!<DAC channel2 enable */
5727 #define DAC_CR_BOFF2_Pos            (17U)
5728 #define DAC_CR_BOFF2_Msk            (0x1UL << DAC_CR_BOFF2_Pos)                 /*!< 0x00020000 */
5729 #define DAC_CR_BOFF2                DAC_CR_BOFF2_Msk                           /*!<DAC channel2 output buffer disable */
5730 #define DAC_CR_TEN2_Pos             (18U)
5731 #define DAC_CR_TEN2_Msk             (0x1UL << DAC_CR_TEN2_Pos)                  /*!< 0x00040000 */
5732 #define DAC_CR_TEN2                 DAC_CR_TEN2_Msk                            /*!<DAC channel2 Trigger enable */
5733 
5734 #define DAC_CR_TSEL2_Pos            (19U)
5735 #define DAC_CR_TSEL2_Msk            (0x7UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00380000 */
5736 #define DAC_CR_TSEL2                DAC_CR_TSEL2_Msk                           /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
5737 #define DAC_CR_TSEL2_0              (0x1UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00080000 */
5738 #define DAC_CR_TSEL2_1              (0x2UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00100000 */
5739 #define DAC_CR_TSEL2_2              (0x4UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00200000 */
5740 
5741 #define DAC_CR_WAVE2_Pos            (22U)
5742 #define DAC_CR_WAVE2_Msk            (0x3UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00C00000 */
5743 #define DAC_CR_WAVE2                DAC_CR_WAVE2_Msk                           /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
5744 #define DAC_CR_WAVE2_0              (0x1UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00400000 */
5745 #define DAC_CR_WAVE2_1              (0x2UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00800000 */
5746 
5747 #define DAC_CR_MAMP2_Pos            (24U)
5748 #define DAC_CR_MAMP2_Msk            (0xFUL << DAC_CR_MAMP2_Pos)                 /*!< 0x0F000000 */
5749 #define DAC_CR_MAMP2                DAC_CR_MAMP2_Msk                           /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
5750 #define DAC_CR_MAMP2_0              (0x1UL << DAC_CR_MAMP2_Pos)                 /*!< 0x01000000 */
5751 #define DAC_CR_MAMP2_1              (0x2UL << DAC_CR_MAMP2_Pos)                 /*!< 0x02000000 */
5752 #define DAC_CR_MAMP2_2              (0x4UL << DAC_CR_MAMP2_Pos)                 /*!< 0x04000000 */
5753 #define DAC_CR_MAMP2_3              (0x8UL << DAC_CR_MAMP2_Pos)                 /*!< 0x08000000 */
5754 
5755 #define DAC_CR_DMAEN2_Pos           (28U)
5756 #define DAC_CR_DMAEN2_Msk           (0x1UL << DAC_CR_DMAEN2_Pos)                /*!< 0x10000000 */
5757 #define DAC_CR_DMAEN2               DAC_CR_DMAEN2_Msk                          /*!<DAC channel2 DMA enabled */
5758 #define DAC_CR_DMAUDRIE2_Pos        (29U)
5759 #define DAC_CR_DMAUDRIE2_Msk        (0x1UL << DAC_CR_DMAUDRIE2_Pos)             /*!< 0x20000000 */
5760 #define DAC_CR_DMAUDRIE2            DAC_CR_DMAUDRIE2_Msk                       /*!<DAC channel2 DMA underrun interrupt enable*/
5761 
5762 /*****************  Bit definition for DAC_SWTRIGR register  ******************/
5763 #define DAC_SWTRIGR_SWTRIG1_Pos     (0U)
5764 #define DAC_SWTRIGR_SWTRIG1_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)          /*!< 0x00000001 */
5765 #define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!<DAC channel1 software trigger */
5766 #define DAC_SWTRIGR_SWTRIG2_Pos     (1U)
5767 #define DAC_SWTRIGR_SWTRIG2_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)          /*!< 0x00000002 */
5768 #define DAC_SWTRIGR_SWTRIG2         DAC_SWTRIGR_SWTRIG2_Msk                    /*!<DAC channel2 software trigger */
5769 
5770 /*****************  Bit definition for DAC_DHR12R1 register  ******************/
5771 #define DAC_DHR12R1_DACC1DHR_Pos    (0U)
5772 #define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)       /*!< 0x00000FFF */
5773 #define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
5774 
5775 /*****************  Bit definition for DAC_DHR12L1 register  ******************/
5776 #define DAC_DHR12L1_DACC1DHR_Pos    (4U)
5777 #define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)       /*!< 0x0000FFF0 */
5778 #define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
5779 
5780 /******************  Bit definition for DAC_DHR8R1 register  ******************/
5781 #define DAC_DHR8R1_DACC1DHR_Pos     (0U)
5782 #define DAC_DHR8R1_DACC1DHR_Msk     (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)         /*!< 0x000000FF */
5783 #define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
5784 
5785 /*****************  Bit definition for DAC_DHR12R2 register  ******************/
5786 #define DAC_DHR12R2_DACC2DHR_Pos    (0U)
5787 #define DAC_DHR12R2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)       /*!< 0x00000FFF */
5788 #define DAC_DHR12R2_DACC2DHR        DAC_DHR12R2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */
5789 
5790 /*****************  Bit definition for DAC_DHR12L2 register  ******************/
5791 #define DAC_DHR12L2_DACC2DHR_Pos    (4U)
5792 #define DAC_DHR12L2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)       /*!< 0x0000FFF0 */
5793 #define DAC_DHR12L2_DACC2DHR        DAC_DHR12L2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */
5794 
5795 /******************  Bit definition for DAC_DHR8R2 register  ******************/
5796 #define DAC_DHR8R2_DACC2DHR_Pos     (0U)
5797 #define DAC_DHR8R2_DACC2DHR_Msk     (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)         /*!< 0x000000FF */
5798 #define DAC_DHR8R2_DACC2DHR         DAC_DHR8R2_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */
5799 
5800 /*****************  Bit definition for DAC_DHR12RD register  ******************/
5801 #define DAC_DHR12RD_DACC1DHR_Pos    (0U)
5802 #define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)       /*!< 0x00000FFF */
5803 #define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
5804 #define DAC_DHR12RD_DACC2DHR_Pos    (16U)
5805 #define DAC_DHR12RD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)       /*!< 0x0FFF0000 */
5806 #define DAC_DHR12RD_DACC2DHR        DAC_DHR12RD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */
5807 
5808 /*****************  Bit definition for DAC_DHR12LD register  ******************/
5809 #define DAC_DHR12LD_DACC1DHR_Pos    (4U)
5810 #define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)       /*!< 0x0000FFF0 */
5811 #define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
5812 #define DAC_DHR12LD_DACC2DHR_Pos    (20U)
5813 #define DAC_DHR12LD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)       /*!< 0xFFF00000 */
5814 #define DAC_DHR12LD_DACC2DHR        DAC_DHR12LD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */
5815 
5816 /******************  Bit definition for DAC_DHR8RD register  ******************/
5817 #define DAC_DHR8RD_DACC1DHR_Pos     (0U)
5818 #define DAC_DHR8RD_DACC1DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)         /*!< 0x000000FF */
5819 #define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
5820 #define DAC_DHR8RD_DACC2DHR_Pos     (8U)
5821 #define DAC_DHR8RD_DACC2DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)         /*!< 0x0000FF00 */
5822 #define DAC_DHR8RD_DACC2DHR         DAC_DHR8RD_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */
5823 
5824 /*******************  Bit definition for DAC_DOR1 register  *******************/
5825 #define DAC_DOR1_DACC1DOR_Pos       (0U)
5826 #define DAC_DOR1_DACC1DOR_Msk       (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)          /*!< 0x00000FFF */
5827 #define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!<DAC channel1 data output */
5828 
5829 /*******************  Bit definition for DAC_DOR2 register  *******************/
5830 #define DAC_DOR2_DACC2DOR_Pos       (0U)
5831 #define DAC_DOR2_DACC2DOR_Msk       (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)          /*!< 0x00000FFF */
5832 #define DAC_DOR2_DACC2DOR           DAC_DOR2_DACC2DOR_Msk                      /*!<DAC channel2 data output */
5833 
5834 /********************  Bit definition for DAC_SR register  ********************/
5835 #define DAC_SR_DMAUDR1_Pos          (13U)
5836 #define DAC_SR_DMAUDR1_Msk          (0x1UL << DAC_SR_DMAUDR1_Pos)               /*!< 0x00002000 */
5837 #define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!<DAC channel1 DMA underrun flag */
5838 #define DAC_SR_DMAUDR2_Pos          (29U)
5839 #define DAC_SR_DMAUDR2_Msk          (0x1UL << DAC_SR_DMAUDR2_Pos)               /*!< 0x20000000 */
5840 #define DAC_SR_DMAUDR2              DAC_SR_DMAUDR2_Msk                         /*!<DAC channel2 DMA underrun flag */
5841 
5842 /******************************************************************************/
5843 /*                                                                            */
5844 /*                                    DCMI                                    */
5845 /*                                                                            */
5846 /******************************************************************************/
5847 /********************  Bits definition for DCMI_CR register  ******************/
5848 #define DCMI_CR_CAPTURE_Pos        (0U)
5849 #define DCMI_CR_CAPTURE_Msk        (0x1UL << DCMI_CR_CAPTURE_Pos)               /*!< 0x00000001 */
5850 #define DCMI_CR_CAPTURE            DCMI_CR_CAPTURE_Msk
5851 #define DCMI_CR_CM_Pos             (1U)
5852 #define DCMI_CR_CM_Msk             (0x1UL << DCMI_CR_CM_Pos)                    /*!< 0x00000002 */
5853 #define DCMI_CR_CM                 DCMI_CR_CM_Msk
5854 #define DCMI_CR_CROP_Pos           (2U)
5855 #define DCMI_CR_CROP_Msk           (0x1UL << DCMI_CR_CROP_Pos)                  /*!< 0x00000004 */
5856 #define DCMI_CR_CROP               DCMI_CR_CROP_Msk
5857 #define DCMI_CR_JPEG_Pos           (3U)
5858 #define DCMI_CR_JPEG_Msk           (0x1UL << DCMI_CR_JPEG_Pos)                  /*!< 0x00000008 */
5859 #define DCMI_CR_JPEG               DCMI_CR_JPEG_Msk
5860 #define DCMI_CR_ESS_Pos            (4U)
5861 #define DCMI_CR_ESS_Msk            (0x1UL << DCMI_CR_ESS_Pos)                   /*!< 0x00000010 */
5862 #define DCMI_CR_ESS                DCMI_CR_ESS_Msk
5863 #define DCMI_CR_PCKPOL_Pos         (5U)
5864 #define DCMI_CR_PCKPOL_Msk         (0x1UL << DCMI_CR_PCKPOL_Pos)                /*!< 0x00000020 */
5865 #define DCMI_CR_PCKPOL             DCMI_CR_PCKPOL_Msk
5866 #define DCMI_CR_HSPOL_Pos          (6U)
5867 #define DCMI_CR_HSPOL_Msk          (0x1UL << DCMI_CR_HSPOL_Pos)                 /*!< 0x00000040 */
5868 #define DCMI_CR_HSPOL              DCMI_CR_HSPOL_Msk
5869 #define DCMI_CR_VSPOL_Pos          (7U)
5870 #define DCMI_CR_VSPOL_Msk          (0x1UL << DCMI_CR_VSPOL_Pos)                 /*!< 0x00000080 */
5871 #define DCMI_CR_VSPOL              DCMI_CR_VSPOL_Msk
5872 #define DCMI_CR_FCRC_0             0x00000100U
5873 #define DCMI_CR_FCRC_1             0x00000200U
5874 #define DCMI_CR_EDM_0              0x00000400U
5875 #define DCMI_CR_EDM_1              0x00000800U
5876 #define DCMI_CR_OUTEN_Pos          (13U)
5877 #define DCMI_CR_OUTEN_Msk          (0x1UL << DCMI_CR_OUTEN_Pos)                 /*!< 0x00002000 */
5878 #define DCMI_CR_OUTEN              DCMI_CR_OUTEN_Msk
5879 #define DCMI_CR_ENABLE_Pos         (14U)
5880 #define DCMI_CR_ENABLE_Msk         (0x1UL << DCMI_CR_ENABLE_Pos)                /*!< 0x00004000 */
5881 #define DCMI_CR_ENABLE             DCMI_CR_ENABLE_Msk
5882 #define DCMI_CR_BSM_0              0x00010000U
5883 #define DCMI_CR_BSM_1              0x00020000U
5884 #define DCMI_CR_OEBS_Pos           (18U)
5885 #define DCMI_CR_OEBS_Msk           (0x1UL << DCMI_CR_OEBS_Pos)                  /*!< 0x00040000 */
5886 #define DCMI_CR_OEBS               DCMI_CR_OEBS_Msk
5887 #define DCMI_CR_LSM_Pos            (19U)
5888 #define DCMI_CR_LSM_Msk            (0x1UL << DCMI_CR_LSM_Pos)                   /*!< 0x00080000 */
5889 #define DCMI_CR_LSM                DCMI_CR_LSM_Msk
5890 #define DCMI_CR_OELS_Pos           (20U)
5891 #define DCMI_CR_OELS_Msk           (0x1UL << DCMI_CR_OELS_Pos)                  /*!< 0x00100000 */
5892 #define DCMI_CR_OELS               DCMI_CR_OELS_Msk
5893 
5894 /********************  Bits definition for DCMI_SR register  ******************/
5895 #define DCMI_SR_HSYNC_Pos          (0U)
5896 #define DCMI_SR_HSYNC_Msk          (0x1UL << DCMI_SR_HSYNC_Pos)                 /*!< 0x00000001 */
5897 #define DCMI_SR_HSYNC              DCMI_SR_HSYNC_Msk
5898 #define DCMI_SR_VSYNC_Pos          (1U)
5899 #define DCMI_SR_VSYNC_Msk          (0x1UL << DCMI_SR_VSYNC_Pos)                 /*!< 0x00000002 */
5900 #define DCMI_SR_VSYNC              DCMI_SR_VSYNC_Msk
5901 #define DCMI_SR_FNE_Pos            (2U)
5902 #define DCMI_SR_FNE_Msk            (0x1UL << DCMI_SR_FNE_Pos)                   /*!< 0x00000004 */
5903 #define DCMI_SR_FNE                DCMI_SR_FNE_Msk
5904 
5905 /********************  Bits definition for DCMI_RIS register  *****************/
5906 #define DCMI_RIS_FRAME_RIS_Pos     (0U)
5907 #define DCMI_RIS_FRAME_RIS_Msk     (0x1UL << DCMI_RIS_FRAME_RIS_Pos)            /*!< 0x00000001 */
5908 #define DCMI_RIS_FRAME_RIS         DCMI_RIS_FRAME_RIS_Msk
5909 #define DCMI_RIS_OVR_RIS_Pos       (1U)
5910 #define DCMI_RIS_OVR_RIS_Msk       (0x1UL << DCMI_RIS_OVR_RIS_Pos)              /*!< 0x00000002 */
5911 #define DCMI_RIS_OVR_RIS           DCMI_RIS_OVR_RIS_Msk
5912 #define DCMI_RIS_ERR_RIS_Pos       (2U)
5913 #define DCMI_RIS_ERR_RIS_Msk       (0x1UL << DCMI_RIS_ERR_RIS_Pos)              /*!< 0x00000004 */
5914 #define DCMI_RIS_ERR_RIS           DCMI_RIS_ERR_RIS_Msk
5915 #define DCMI_RIS_VSYNC_RIS_Pos     (3U)
5916 #define DCMI_RIS_VSYNC_RIS_Msk     (0x1UL << DCMI_RIS_VSYNC_RIS_Pos)            /*!< 0x00000008 */
5917 #define DCMI_RIS_VSYNC_RIS         DCMI_RIS_VSYNC_RIS_Msk
5918 #define DCMI_RIS_LINE_RIS_Pos      (4U)
5919 #define DCMI_RIS_LINE_RIS_Msk      (0x1UL << DCMI_RIS_LINE_RIS_Pos)             /*!< 0x00000010 */
5920 #define DCMI_RIS_LINE_RIS          DCMI_RIS_LINE_RIS_Msk
5921 /* Legacy defines */
5922 #define DCMI_RISR_FRAME_RIS                  DCMI_RIS_FRAME_RIS
5923 #define DCMI_RISR_OVR_RIS                    DCMI_RIS_OVR_RIS
5924 #define DCMI_RISR_ERR_RIS                    DCMI_RIS_ERR_RIS
5925 #define DCMI_RISR_VSYNC_RIS                  DCMI_RIS_VSYNC_RIS
5926 #define DCMI_RISR_LINE_RIS                   DCMI_RIS_LINE_RIS
5927 #define DCMI_RISR_OVF_RIS                    DCMI_RIS_OVR_RIS
5928 
5929 /********************  Bits definition for DCMI_IER register  *****************/
5930 #define DCMI_IER_FRAME_IE_Pos      (0U)
5931 #define DCMI_IER_FRAME_IE_Msk      (0x1UL << DCMI_IER_FRAME_IE_Pos)             /*!< 0x00000001 */
5932 #define DCMI_IER_FRAME_IE          DCMI_IER_FRAME_IE_Msk
5933 #define DCMI_IER_OVR_IE_Pos        (1U)
5934 #define DCMI_IER_OVR_IE_Msk        (0x1UL << DCMI_IER_OVR_IE_Pos)               /*!< 0x00000002 */
5935 #define DCMI_IER_OVR_IE            DCMI_IER_OVR_IE_Msk
5936 #define DCMI_IER_ERR_IE_Pos        (2U)
5937 #define DCMI_IER_ERR_IE_Msk        (0x1UL << DCMI_IER_ERR_IE_Pos)               /*!< 0x00000004 */
5938 #define DCMI_IER_ERR_IE            DCMI_IER_ERR_IE_Msk
5939 #define DCMI_IER_VSYNC_IE_Pos      (3U)
5940 #define DCMI_IER_VSYNC_IE_Msk      (0x1UL << DCMI_IER_VSYNC_IE_Pos)             /*!< 0x00000008 */
5941 #define DCMI_IER_VSYNC_IE          DCMI_IER_VSYNC_IE_Msk
5942 #define DCMI_IER_LINE_IE_Pos       (4U)
5943 #define DCMI_IER_LINE_IE_Msk       (0x1UL << DCMI_IER_LINE_IE_Pos)              /*!< 0x00000010 */
5944 #define DCMI_IER_LINE_IE           DCMI_IER_LINE_IE_Msk
5945 /* Legacy defines */
5946 #define DCMI_IER_OVF_IE                      DCMI_IER_OVR_IE
5947 
5948 /********************  Bits definition for DCMI_MIS register  *****************/
5949 #define DCMI_MIS_FRAME_MIS_Pos     (0U)
5950 #define DCMI_MIS_FRAME_MIS_Msk     (0x1UL << DCMI_MIS_FRAME_MIS_Pos)            /*!< 0x00000001 */
5951 #define DCMI_MIS_FRAME_MIS         DCMI_MIS_FRAME_MIS_Msk
5952 #define DCMI_MIS_OVR_MIS_Pos       (1U)
5953 #define DCMI_MIS_OVR_MIS_Msk       (0x1UL << DCMI_MIS_OVR_MIS_Pos)              /*!< 0x00000002 */
5954 #define DCMI_MIS_OVR_MIS           DCMI_MIS_OVR_MIS_Msk
5955 #define DCMI_MIS_ERR_MIS_Pos       (2U)
5956 #define DCMI_MIS_ERR_MIS_Msk       (0x1UL << DCMI_MIS_ERR_MIS_Pos)              /*!< 0x00000004 */
5957 #define DCMI_MIS_ERR_MIS           DCMI_MIS_ERR_MIS_Msk
5958 #define DCMI_MIS_VSYNC_MIS_Pos     (3U)
5959 #define DCMI_MIS_VSYNC_MIS_Msk     (0x1UL << DCMI_MIS_VSYNC_MIS_Pos)            /*!< 0x00000008 */
5960 #define DCMI_MIS_VSYNC_MIS         DCMI_MIS_VSYNC_MIS_Msk
5961 #define DCMI_MIS_LINE_MIS_Pos      (4U)
5962 #define DCMI_MIS_LINE_MIS_Msk      (0x1UL << DCMI_MIS_LINE_MIS_Pos)             /*!< 0x00000010 */
5963 #define DCMI_MIS_LINE_MIS          DCMI_MIS_LINE_MIS_Msk
5964 
5965 /* Legacy defines */
5966 #define DCMI_MISR_FRAME_MIS                  DCMI_MIS_FRAME_MIS
5967 #define DCMI_MISR_OVF_MIS                    DCMI_MIS_OVR_MIS
5968 #define DCMI_MISR_ERR_MIS                    DCMI_MIS_ERR_MIS
5969 #define DCMI_MISR_VSYNC_MIS                  DCMI_MIS_VSYNC_MIS
5970 #define DCMI_MISR_LINE_MIS                   DCMI_MIS_LINE_MIS
5971 
5972 /********************  Bits definition for DCMI_ICR register  *****************/
5973 #define DCMI_ICR_FRAME_ISC_Pos     (0U)
5974 #define DCMI_ICR_FRAME_ISC_Msk     (0x1UL << DCMI_ICR_FRAME_ISC_Pos)            /*!< 0x00000001 */
5975 #define DCMI_ICR_FRAME_ISC         DCMI_ICR_FRAME_ISC_Msk
5976 #define DCMI_ICR_OVR_ISC_Pos       (1U)
5977 #define DCMI_ICR_OVR_ISC_Msk       (0x1UL << DCMI_ICR_OVR_ISC_Pos)              /*!< 0x00000002 */
5978 #define DCMI_ICR_OVR_ISC           DCMI_ICR_OVR_ISC_Msk
5979 #define DCMI_ICR_ERR_ISC_Pos       (2U)
5980 #define DCMI_ICR_ERR_ISC_Msk       (0x1UL << DCMI_ICR_ERR_ISC_Pos)              /*!< 0x00000004 */
5981 #define DCMI_ICR_ERR_ISC           DCMI_ICR_ERR_ISC_Msk
5982 #define DCMI_ICR_VSYNC_ISC_Pos     (3U)
5983 #define DCMI_ICR_VSYNC_ISC_Msk     (0x1UL << DCMI_ICR_VSYNC_ISC_Pos)            /*!< 0x00000008 */
5984 #define DCMI_ICR_VSYNC_ISC         DCMI_ICR_VSYNC_ISC_Msk
5985 #define DCMI_ICR_LINE_ISC_Pos      (4U)
5986 #define DCMI_ICR_LINE_ISC_Msk      (0x1UL << DCMI_ICR_LINE_ISC_Pos)             /*!< 0x00000010 */
5987 #define DCMI_ICR_LINE_ISC          DCMI_ICR_LINE_ISC_Msk
5988 
5989 /* Legacy defines */
5990 #define DCMI_ICR_OVF_ISC                     DCMI_ICR_OVR_ISC
5991 
5992 /********************  Bits definition for DCMI_ESCR register  ******************/
5993 #define DCMI_ESCR_FSC_Pos          (0U)
5994 #define DCMI_ESCR_FSC_Msk          (0xFFUL << DCMI_ESCR_FSC_Pos)                /*!< 0x000000FF */
5995 #define DCMI_ESCR_FSC              DCMI_ESCR_FSC_Msk
5996 #define DCMI_ESCR_LSC_Pos          (8U)
5997 #define DCMI_ESCR_LSC_Msk          (0xFFUL << DCMI_ESCR_LSC_Pos)                /*!< 0x0000FF00 */
5998 #define DCMI_ESCR_LSC              DCMI_ESCR_LSC_Msk
5999 #define DCMI_ESCR_LEC_Pos          (16U)
6000 #define DCMI_ESCR_LEC_Msk          (0xFFUL << DCMI_ESCR_LEC_Pos)                /*!< 0x00FF0000 */
6001 #define DCMI_ESCR_LEC              DCMI_ESCR_LEC_Msk
6002 #define DCMI_ESCR_FEC_Pos          (24U)
6003 #define DCMI_ESCR_FEC_Msk          (0xFFUL << DCMI_ESCR_FEC_Pos)                /*!< 0xFF000000 */
6004 #define DCMI_ESCR_FEC              DCMI_ESCR_FEC_Msk
6005 
6006 /********************  Bits definition for DCMI_ESUR register  ******************/
6007 #define DCMI_ESUR_FSU_Pos          (0U)
6008 #define DCMI_ESUR_FSU_Msk          (0xFFUL << DCMI_ESUR_FSU_Pos)                /*!< 0x000000FF */
6009 #define DCMI_ESUR_FSU              DCMI_ESUR_FSU_Msk
6010 #define DCMI_ESUR_LSU_Pos          (8U)
6011 #define DCMI_ESUR_LSU_Msk          (0xFFUL << DCMI_ESUR_LSU_Pos)                /*!< 0x0000FF00 */
6012 #define DCMI_ESUR_LSU              DCMI_ESUR_LSU_Msk
6013 #define DCMI_ESUR_LEU_Pos          (16U)
6014 #define DCMI_ESUR_LEU_Msk          (0xFFUL << DCMI_ESUR_LEU_Pos)                /*!< 0x00FF0000 */
6015 #define DCMI_ESUR_LEU              DCMI_ESUR_LEU_Msk
6016 #define DCMI_ESUR_FEU_Pos          (24U)
6017 #define DCMI_ESUR_FEU_Msk          (0xFFUL << DCMI_ESUR_FEU_Pos)                /*!< 0xFF000000 */
6018 #define DCMI_ESUR_FEU              DCMI_ESUR_FEU_Msk
6019 
6020 /********************  Bits definition for DCMI_CWSTRT register  ******************/
6021 #define DCMI_CWSTRT_HOFFCNT_Pos    (0U)
6022 #define DCMI_CWSTRT_HOFFCNT_Msk    (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos)        /*!< 0x00003FFF */
6023 #define DCMI_CWSTRT_HOFFCNT        DCMI_CWSTRT_HOFFCNT_Msk
6024 #define DCMI_CWSTRT_VST_Pos        (16U)
6025 #define DCMI_CWSTRT_VST_Msk        (0x1FFFUL << DCMI_CWSTRT_VST_Pos)            /*!< 0x1FFF0000 */
6026 #define DCMI_CWSTRT_VST            DCMI_CWSTRT_VST_Msk
6027 
6028 /********************  Bits definition for DCMI_CWSIZE register  ******************/
6029 #define DCMI_CWSIZE_CAPCNT_Pos     (0U)
6030 #define DCMI_CWSIZE_CAPCNT_Msk     (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos)         /*!< 0x00003FFF */
6031 #define DCMI_CWSIZE_CAPCNT         DCMI_CWSIZE_CAPCNT_Msk
6032 #define DCMI_CWSIZE_VLINE_Pos      (16U)
6033 #define DCMI_CWSIZE_VLINE_Msk      (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos)          /*!< 0x3FFF0000 */
6034 #define DCMI_CWSIZE_VLINE          DCMI_CWSIZE_VLINE_Msk
6035 
6036 /********************  Bits definition for DCMI_DR register  *********************/
6037 #define DCMI_DR_BYTE0_Pos          (0U)
6038 #define DCMI_DR_BYTE0_Msk          (0xFFUL << DCMI_DR_BYTE0_Pos)                /*!< 0x000000FF */
6039 #define DCMI_DR_BYTE0              DCMI_DR_BYTE0_Msk
6040 #define DCMI_DR_BYTE1_Pos          (8U)
6041 #define DCMI_DR_BYTE1_Msk          (0xFFUL << DCMI_DR_BYTE1_Pos)                /*!< 0x0000FF00 */
6042 #define DCMI_DR_BYTE1              DCMI_DR_BYTE1_Msk
6043 #define DCMI_DR_BYTE2_Pos          (16U)
6044 #define DCMI_DR_BYTE2_Msk          (0xFFUL << DCMI_DR_BYTE2_Pos)                /*!< 0x00FF0000 */
6045 #define DCMI_DR_BYTE2              DCMI_DR_BYTE2_Msk
6046 #define DCMI_DR_BYTE3_Pos          (24U)
6047 #define DCMI_DR_BYTE3_Msk          (0xFFUL << DCMI_DR_BYTE3_Pos)                /*!< 0xFF000000 */
6048 #define DCMI_DR_BYTE3              DCMI_DR_BYTE3_Msk
6049 
6050 /******************************************************************************/
6051 /*                                                                            */
6052 /*                             DMA Controller                                 */
6053 /*                                                                            */
6054 /******************************************************************************/
6055 /********************  Bits definition for DMA_SxCR register  *****************/
6056 #define DMA_SxCR_CHSEL_Pos       (25U)
6057 #define DMA_SxCR_CHSEL_Msk       (0x7UL << DMA_SxCR_CHSEL_Pos)                  /*!< 0x0E000000 */
6058 #define DMA_SxCR_CHSEL           DMA_SxCR_CHSEL_Msk
6059 #define DMA_SxCR_CHSEL_0         0x02000000U
6060 #define DMA_SxCR_CHSEL_1         0x04000000U
6061 #define DMA_SxCR_CHSEL_2         0x08000000U
6062 #define DMA_SxCR_MBURST_Pos      (23U)
6063 #define DMA_SxCR_MBURST_Msk      (0x3UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x01800000 */
6064 #define DMA_SxCR_MBURST          DMA_SxCR_MBURST_Msk
6065 #define DMA_SxCR_MBURST_0        (0x1UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x00800000 */
6066 #define DMA_SxCR_MBURST_1        (0x2UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x01000000 */
6067 #define DMA_SxCR_PBURST_Pos      (21U)
6068 #define DMA_SxCR_PBURST_Msk      (0x3UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00600000 */
6069 #define DMA_SxCR_PBURST          DMA_SxCR_PBURST_Msk
6070 #define DMA_SxCR_PBURST_0        (0x1UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00200000 */
6071 #define DMA_SxCR_PBURST_1        (0x2UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00400000 */
6072 #define DMA_SxCR_CT_Pos          (19U)
6073 #define DMA_SxCR_CT_Msk          (0x1UL << DMA_SxCR_CT_Pos)                     /*!< 0x00080000 */
6074 #define DMA_SxCR_CT              DMA_SxCR_CT_Msk
6075 #define DMA_SxCR_DBM_Pos         (18U)
6076 #define DMA_SxCR_DBM_Msk         (0x1UL << DMA_SxCR_DBM_Pos)                    /*!< 0x00040000 */
6077 #define DMA_SxCR_DBM             DMA_SxCR_DBM_Msk
6078 #define DMA_SxCR_PL_Pos          (16U)
6079 #define DMA_SxCR_PL_Msk          (0x3UL << DMA_SxCR_PL_Pos)                     /*!< 0x00030000 */
6080 #define DMA_SxCR_PL              DMA_SxCR_PL_Msk
6081 #define DMA_SxCR_PL_0            (0x1UL << DMA_SxCR_PL_Pos)                     /*!< 0x00010000 */
6082 #define DMA_SxCR_PL_1            (0x2UL << DMA_SxCR_PL_Pos)                     /*!< 0x00020000 */
6083 #define DMA_SxCR_PINCOS_Pos      (15U)
6084 #define DMA_SxCR_PINCOS_Msk      (0x1UL << DMA_SxCR_PINCOS_Pos)                 /*!< 0x00008000 */
6085 #define DMA_SxCR_PINCOS          DMA_SxCR_PINCOS_Msk
6086 #define DMA_SxCR_MSIZE_Pos       (13U)
6087 #define DMA_SxCR_MSIZE_Msk       (0x3UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00006000 */
6088 #define DMA_SxCR_MSIZE           DMA_SxCR_MSIZE_Msk
6089 #define DMA_SxCR_MSIZE_0         (0x1UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00002000 */
6090 #define DMA_SxCR_MSIZE_1         (0x2UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00004000 */
6091 #define DMA_SxCR_PSIZE_Pos       (11U)
6092 #define DMA_SxCR_PSIZE_Msk       (0x3UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00001800 */
6093 #define DMA_SxCR_PSIZE           DMA_SxCR_PSIZE_Msk
6094 #define DMA_SxCR_PSIZE_0         (0x1UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00000800 */
6095 #define DMA_SxCR_PSIZE_1         (0x2UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00001000 */
6096 #define DMA_SxCR_MINC_Pos        (10U)
6097 #define DMA_SxCR_MINC_Msk        (0x1UL << DMA_SxCR_MINC_Pos)                   /*!< 0x00000400 */
6098 #define DMA_SxCR_MINC            DMA_SxCR_MINC_Msk
6099 #define DMA_SxCR_PINC_Pos        (9U)
6100 #define DMA_SxCR_PINC_Msk        (0x1UL << DMA_SxCR_PINC_Pos)                   /*!< 0x00000200 */
6101 #define DMA_SxCR_PINC            DMA_SxCR_PINC_Msk
6102 #define DMA_SxCR_CIRC_Pos        (8U)
6103 #define DMA_SxCR_CIRC_Msk        (0x1UL << DMA_SxCR_CIRC_Pos)                   /*!< 0x00000100 */
6104 #define DMA_SxCR_CIRC            DMA_SxCR_CIRC_Msk
6105 #define DMA_SxCR_DIR_Pos         (6U)
6106 #define DMA_SxCR_DIR_Msk         (0x3UL << DMA_SxCR_DIR_Pos)                    /*!< 0x000000C0 */
6107 #define DMA_SxCR_DIR             DMA_SxCR_DIR_Msk
6108 #define DMA_SxCR_DIR_0           (0x1UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000040 */
6109 #define DMA_SxCR_DIR_1           (0x2UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000080 */
6110 #define DMA_SxCR_PFCTRL_Pos      (5U)
6111 #define DMA_SxCR_PFCTRL_Msk      (0x1UL << DMA_SxCR_PFCTRL_Pos)                 /*!< 0x00000020 */
6112 #define DMA_SxCR_PFCTRL          DMA_SxCR_PFCTRL_Msk
6113 #define DMA_SxCR_TCIE_Pos        (4U)
6114 #define DMA_SxCR_TCIE_Msk        (0x1UL << DMA_SxCR_TCIE_Pos)                   /*!< 0x00000010 */
6115 #define DMA_SxCR_TCIE            DMA_SxCR_TCIE_Msk
6116 #define DMA_SxCR_HTIE_Pos        (3U)
6117 #define DMA_SxCR_HTIE_Msk        (0x1UL << DMA_SxCR_HTIE_Pos)                   /*!< 0x00000008 */
6118 #define DMA_SxCR_HTIE            DMA_SxCR_HTIE_Msk
6119 #define DMA_SxCR_TEIE_Pos        (2U)
6120 #define DMA_SxCR_TEIE_Msk        (0x1UL << DMA_SxCR_TEIE_Pos)                   /*!< 0x00000004 */
6121 #define DMA_SxCR_TEIE            DMA_SxCR_TEIE_Msk
6122 #define DMA_SxCR_DMEIE_Pos       (1U)
6123 #define DMA_SxCR_DMEIE_Msk       (0x1UL << DMA_SxCR_DMEIE_Pos)                  /*!< 0x00000002 */
6124 #define DMA_SxCR_DMEIE           DMA_SxCR_DMEIE_Msk
6125 #define DMA_SxCR_EN_Pos          (0U)
6126 #define DMA_SxCR_EN_Msk          (0x1UL << DMA_SxCR_EN_Pos)                     /*!< 0x00000001 */
6127 #define DMA_SxCR_EN              DMA_SxCR_EN_Msk
6128 
6129 /* Legacy defines */
6130 #define DMA_SxCR_ACK_Pos         (20U)
6131 #define DMA_SxCR_ACK_Msk         (0x1UL << DMA_SxCR_ACK_Pos)                    /*!< 0x00100000 */
6132 #define DMA_SxCR_ACK             DMA_SxCR_ACK_Msk
6133 
6134 /********************  Bits definition for DMA_SxCNDTR register  **************/
6135 #define DMA_SxNDT_Pos            (0U)
6136 #define DMA_SxNDT_Msk            (0xFFFFUL << DMA_SxNDT_Pos)                    /*!< 0x0000FFFF */
6137 #define DMA_SxNDT                DMA_SxNDT_Msk
6138 #define DMA_SxNDT_0              (0x0001UL << DMA_SxNDT_Pos)                    /*!< 0x00000001 */
6139 #define DMA_SxNDT_1              (0x0002UL << DMA_SxNDT_Pos)                    /*!< 0x00000002 */
6140 #define DMA_SxNDT_2              (0x0004UL << DMA_SxNDT_Pos)                    /*!< 0x00000004 */
6141 #define DMA_SxNDT_3              (0x0008UL << DMA_SxNDT_Pos)                    /*!< 0x00000008 */
6142 #define DMA_SxNDT_4              (0x0010UL << DMA_SxNDT_Pos)                    /*!< 0x00000010 */
6143 #define DMA_SxNDT_5              (0x0020UL << DMA_SxNDT_Pos)                    /*!< 0x00000020 */
6144 #define DMA_SxNDT_6              (0x0040UL << DMA_SxNDT_Pos)                    /*!< 0x00000040 */
6145 #define DMA_SxNDT_7              (0x0080UL << DMA_SxNDT_Pos)                    /*!< 0x00000080 */
6146 #define DMA_SxNDT_8              (0x0100UL << DMA_SxNDT_Pos)                    /*!< 0x00000100 */
6147 #define DMA_SxNDT_9              (0x0200UL << DMA_SxNDT_Pos)                    /*!< 0x00000200 */
6148 #define DMA_SxNDT_10             (0x0400UL << DMA_SxNDT_Pos)                    /*!< 0x00000400 */
6149 #define DMA_SxNDT_11             (0x0800UL << DMA_SxNDT_Pos)                    /*!< 0x00000800 */
6150 #define DMA_SxNDT_12             (0x1000UL << DMA_SxNDT_Pos)                    /*!< 0x00001000 */
6151 #define DMA_SxNDT_13             (0x2000UL << DMA_SxNDT_Pos)                    /*!< 0x00002000 */
6152 #define DMA_SxNDT_14             (0x4000UL << DMA_SxNDT_Pos)                    /*!< 0x00004000 */
6153 #define DMA_SxNDT_15             (0x8000UL << DMA_SxNDT_Pos)                    /*!< 0x00008000 */
6154 
6155 /********************  Bits definition for DMA_SxFCR register  ****************/
6156 #define DMA_SxFCR_FEIE_Pos       (7U)
6157 #define DMA_SxFCR_FEIE_Msk       (0x1UL << DMA_SxFCR_FEIE_Pos)                  /*!< 0x00000080 */
6158 #define DMA_SxFCR_FEIE           DMA_SxFCR_FEIE_Msk
6159 #define DMA_SxFCR_FS_Pos         (3U)
6160 #define DMA_SxFCR_FS_Msk         (0x7UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000038 */
6161 #define DMA_SxFCR_FS             DMA_SxFCR_FS_Msk
6162 #define DMA_SxFCR_FS_0           (0x1UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000008 */
6163 #define DMA_SxFCR_FS_1           (0x2UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000010 */
6164 #define DMA_SxFCR_FS_2           (0x4UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000020 */
6165 #define DMA_SxFCR_DMDIS_Pos      (2U)
6166 #define DMA_SxFCR_DMDIS_Msk      (0x1UL << DMA_SxFCR_DMDIS_Pos)                 /*!< 0x00000004 */
6167 #define DMA_SxFCR_DMDIS          DMA_SxFCR_DMDIS_Msk
6168 #define DMA_SxFCR_FTH_Pos        (0U)
6169 #define DMA_SxFCR_FTH_Msk        (0x3UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000003 */
6170 #define DMA_SxFCR_FTH            DMA_SxFCR_FTH_Msk
6171 #define DMA_SxFCR_FTH_0          (0x1UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000001 */
6172 #define DMA_SxFCR_FTH_1          (0x2UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000002 */
6173 
6174 /********************  Bits definition for DMA_LISR register  *****************/
6175 #define DMA_LISR_TCIF3_Pos       (27U)
6176 #define DMA_LISR_TCIF3_Msk       (0x1UL << DMA_LISR_TCIF3_Pos)                  /*!< 0x08000000 */
6177 #define DMA_LISR_TCIF3           DMA_LISR_TCIF3_Msk
6178 #define DMA_LISR_HTIF3_Pos       (26U)
6179 #define DMA_LISR_HTIF3_Msk       (0x1UL << DMA_LISR_HTIF3_Pos)                  /*!< 0x04000000 */
6180 #define DMA_LISR_HTIF3           DMA_LISR_HTIF3_Msk
6181 #define DMA_LISR_TEIF3_Pos       (25U)
6182 #define DMA_LISR_TEIF3_Msk       (0x1UL << DMA_LISR_TEIF3_Pos)                  /*!< 0x02000000 */
6183 #define DMA_LISR_TEIF3           DMA_LISR_TEIF3_Msk
6184 #define DMA_LISR_DMEIF3_Pos      (24U)
6185 #define DMA_LISR_DMEIF3_Msk      (0x1UL << DMA_LISR_DMEIF3_Pos)                 /*!< 0x01000000 */
6186 #define DMA_LISR_DMEIF3          DMA_LISR_DMEIF3_Msk
6187 #define DMA_LISR_FEIF3_Pos       (22U)
6188 #define DMA_LISR_FEIF3_Msk       (0x1UL << DMA_LISR_FEIF3_Pos)                  /*!< 0x00400000 */
6189 #define DMA_LISR_FEIF3           DMA_LISR_FEIF3_Msk
6190 #define DMA_LISR_TCIF2_Pos       (21U)
6191 #define DMA_LISR_TCIF2_Msk       (0x1UL << DMA_LISR_TCIF2_Pos)                  /*!< 0x00200000 */
6192 #define DMA_LISR_TCIF2           DMA_LISR_TCIF2_Msk
6193 #define DMA_LISR_HTIF2_Pos       (20U)
6194 #define DMA_LISR_HTIF2_Msk       (0x1UL << DMA_LISR_HTIF2_Pos)                  /*!< 0x00100000 */
6195 #define DMA_LISR_HTIF2           DMA_LISR_HTIF2_Msk
6196 #define DMA_LISR_TEIF2_Pos       (19U)
6197 #define DMA_LISR_TEIF2_Msk       (0x1UL << DMA_LISR_TEIF2_Pos)                  /*!< 0x00080000 */
6198 #define DMA_LISR_TEIF2           DMA_LISR_TEIF2_Msk
6199 #define DMA_LISR_DMEIF2_Pos      (18U)
6200 #define DMA_LISR_DMEIF2_Msk      (0x1UL << DMA_LISR_DMEIF2_Pos)                 /*!< 0x00040000 */
6201 #define DMA_LISR_DMEIF2          DMA_LISR_DMEIF2_Msk
6202 #define DMA_LISR_FEIF2_Pos       (16U)
6203 #define DMA_LISR_FEIF2_Msk       (0x1UL << DMA_LISR_FEIF2_Pos)                  /*!< 0x00010000 */
6204 #define DMA_LISR_FEIF2           DMA_LISR_FEIF2_Msk
6205 #define DMA_LISR_TCIF1_Pos       (11U)
6206 #define DMA_LISR_TCIF1_Msk       (0x1UL << DMA_LISR_TCIF1_Pos)                  /*!< 0x00000800 */
6207 #define DMA_LISR_TCIF1           DMA_LISR_TCIF1_Msk
6208 #define DMA_LISR_HTIF1_Pos       (10U)
6209 #define DMA_LISR_HTIF1_Msk       (0x1UL << DMA_LISR_HTIF1_Pos)                  /*!< 0x00000400 */
6210 #define DMA_LISR_HTIF1           DMA_LISR_HTIF1_Msk
6211 #define DMA_LISR_TEIF1_Pos       (9U)
6212 #define DMA_LISR_TEIF1_Msk       (0x1UL << DMA_LISR_TEIF1_Pos)                  /*!< 0x00000200 */
6213 #define DMA_LISR_TEIF1           DMA_LISR_TEIF1_Msk
6214 #define DMA_LISR_DMEIF1_Pos      (8U)
6215 #define DMA_LISR_DMEIF1_Msk      (0x1UL << DMA_LISR_DMEIF1_Pos)                 /*!< 0x00000100 */
6216 #define DMA_LISR_DMEIF1          DMA_LISR_DMEIF1_Msk
6217 #define DMA_LISR_FEIF1_Pos       (6U)
6218 #define DMA_LISR_FEIF1_Msk       (0x1UL << DMA_LISR_FEIF1_Pos)                  /*!< 0x00000040 */
6219 #define DMA_LISR_FEIF1           DMA_LISR_FEIF1_Msk
6220 #define DMA_LISR_TCIF0_Pos       (5U)
6221 #define DMA_LISR_TCIF0_Msk       (0x1UL << DMA_LISR_TCIF0_Pos)                  /*!< 0x00000020 */
6222 #define DMA_LISR_TCIF0           DMA_LISR_TCIF0_Msk
6223 #define DMA_LISR_HTIF0_Pos       (4U)
6224 #define DMA_LISR_HTIF0_Msk       (0x1UL << DMA_LISR_HTIF0_Pos)                  /*!< 0x00000010 */
6225 #define DMA_LISR_HTIF0           DMA_LISR_HTIF0_Msk
6226 #define DMA_LISR_TEIF0_Pos       (3U)
6227 #define DMA_LISR_TEIF0_Msk       (0x1UL << DMA_LISR_TEIF0_Pos)                  /*!< 0x00000008 */
6228 #define DMA_LISR_TEIF0           DMA_LISR_TEIF0_Msk
6229 #define DMA_LISR_DMEIF0_Pos      (2U)
6230 #define DMA_LISR_DMEIF0_Msk      (0x1UL << DMA_LISR_DMEIF0_Pos)                 /*!< 0x00000004 */
6231 #define DMA_LISR_DMEIF0          DMA_LISR_DMEIF0_Msk
6232 #define DMA_LISR_FEIF0_Pos       (0U)
6233 #define DMA_LISR_FEIF0_Msk       (0x1UL << DMA_LISR_FEIF0_Pos)                  /*!< 0x00000001 */
6234 #define DMA_LISR_FEIF0           DMA_LISR_FEIF0_Msk
6235 
6236 /********************  Bits definition for DMA_HISR register  *****************/
6237 #define DMA_HISR_TCIF7_Pos       (27U)
6238 #define DMA_HISR_TCIF7_Msk       (0x1UL << DMA_HISR_TCIF7_Pos)                  /*!< 0x08000000 */
6239 #define DMA_HISR_TCIF7           DMA_HISR_TCIF7_Msk
6240 #define DMA_HISR_HTIF7_Pos       (26U)
6241 #define DMA_HISR_HTIF7_Msk       (0x1UL << DMA_HISR_HTIF7_Pos)                  /*!< 0x04000000 */
6242 #define DMA_HISR_HTIF7           DMA_HISR_HTIF7_Msk
6243 #define DMA_HISR_TEIF7_Pos       (25U)
6244 #define DMA_HISR_TEIF7_Msk       (0x1UL << DMA_HISR_TEIF7_Pos)                  /*!< 0x02000000 */
6245 #define DMA_HISR_TEIF7           DMA_HISR_TEIF7_Msk
6246 #define DMA_HISR_DMEIF7_Pos      (24U)
6247 #define DMA_HISR_DMEIF7_Msk      (0x1UL << DMA_HISR_DMEIF7_Pos)                 /*!< 0x01000000 */
6248 #define DMA_HISR_DMEIF7          DMA_HISR_DMEIF7_Msk
6249 #define DMA_HISR_FEIF7_Pos       (22U)
6250 #define DMA_HISR_FEIF7_Msk       (0x1UL << DMA_HISR_FEIF7_Pos)                  /*!< 0x00400000 */
6251 #define DMA_HISR_FEIF7           DMA_HISR_FEIF7_Msk
6252 #define DMA_HISR_TCIF6_Pos       (21U)
6253 #define DMA_HISR_TCIF6_Msk       (0x1UL << DMA_HISR_TCIF6_Pos)                  /*!< 0x00200000 */
6254 #define DMA_HISR_TCIF6           DMA_HISR_TCIF6_Msk
6255 #define DMA_HISR_HTIF6_Pos       (20U)
6256 #define DMA_HISR_HTIF6_Msk       (0x1UL << DMA_HISR_HTIF6_Pos)                  /*!< 0x00100000 */
6257 #define DMA_HISR_HTIF6           DMA_HISR_HTIF6_Msk
6258 #define DMA_HISR_TEIF6_Pos       (19U)
6259 #define DMA_HISR_TEIF6_Msk       (0x1UL << DMA_HISR_TEIF6_Pos)                  /*!< 0x00080000 */
6260 #define DMA_HISR_TEIF6           DMA_HISR_TEIF6_Msk
6261 #define DMA_HISR_DMEIF6_Pos      (18U)
6262 #define DMA_HISR_DMEIF6_Msk      (0x1UL << DMA_HISR_DMEIF6_Pos)                 /*!< 0x00040000 */
6263 #define DMA_HISR_DMEIF6          DMA_HISR_DMEIF6_Msk
6264 #define DMA_HISR_FEIF6_Pos       (16U)
6265 #define DMA_HISR_FEIF6_Msk       (0x1UL << DMA_HISR_FEIF6_Pos)                  /*!< 0x00010000 */
6266 #define DMA_HISR_FEIF6           DMA_HISR_FEIF6_Msk
6267 #define DMA_HISR_TCIF5_Pos       (11U)
6268 #define DMA_HISR_TCIF5_Msk       (0x1UL << DMA_HISR_TCIF5_Pos)                  /*!< 0x00000800 */
6269 #define DMA_HISR_TCIF5           DMA_HISR_TCIF5_Msk
6270 #define DMA_HISR_HTIF5_Pos       (10U)
6271 #define DMA_HISR_HTIF5_Msk       (0x1UL << DMA_HISR_HTIF5_Pos)                  /*!< 0x00000400 */
6272 #define DMA_HISR_HTIF5           DMA_HISR_HTIF5_Msk
6273 #define DMA_HISR_TEIF5_Pos       (9U)
6274 #define DMA_HISR_TEIF5_Msk       (0x1UL << DMA_HISR_TEIF5_Pos)                  /*!< 0x00000200 */
6275 #define DMA_HISR_TEIF5           DMA_HISR_TEIF5_Msk
6276 #define DMA_HISR_DMEIF5_Pos      (8U)
6277 #define DMA_HISR_DMEIF5_Msk      (0x1UL << DMA_HISR_DMEIF5_Pos)                 /*!< 0x00000100 */
6278 #define DMA_HISR_DMEIF5          DMA_HISR_DMEIF5_Msk
6279 #define DMA_HISR_FEIF5_Pos       (6U)
6280 #define DMA_HISR_FEIF5_Msk       (0x1UL << DMA_HISR_FEIF5_Pos)                  /*!< 0x00000040 */
6281 #define DMA_HISR_FEIF5           DMA_HISR_FEIF5_Msk
6282 #define DMA_HISR_TCIF4_Pos       (5U)
6283 #define DMA_HISR_TCIF4_Msk       (0x1UL << DMA_HISR_TCIF4_Pos)                  /*!< 0x00000020 */
6284 #define DMA_HISR_TCIF4           DMA_HISR_TCIF4_Msk
6285 #define DMA_HISR_HTIF4_Pos       (4U)
6286 #define DMA_HISR_HTIF4_Msk       (0x1UL << DMA_HISR_HTIF4_Pos)                  /*!< 0x00000010 */
6287 #define DMA_HISR_HTIF4           DMA_HISR_HTIF4_Msk
6288 #define DMA_HISR_TEIF4_Pos       (3U)
6289 #define DMA_HISR_TEIF4_Msk       (0x1UL << DMA_HISR_TEIF4_Pos)                  /*!< 0x00000008 */
6290 #define DMA_HISR_TEIF4           DMA_HISR_TEIF4_Msk
6291 #define DMA_HISR_DMEIF4_Pos      (2U)
6292 #define DMA_HISR_DMEIF4_Msk      (0x1UL << DMA_HISR_DMEIF4_Pos)                 /*!< 0x00000004 */
6293 #define DMA_HISR_DMEIF4          DMA_HISR_DMEIF4_Msk
6294 #define DMA_HISR_FEIF4_Pos       (0U)
6295 #define DMA_HISR_FEIF4_Msk       (0x1UL << DMA_HISR_FEIF4_Pos)                  /*!< 0x00000001 */
6296 #define DMA_HISR_FEIF4           DMA_HISR_FEIF4_Msk
6297 
6298 /********************  Bits definition for DMA_LIFCR register  ****************/
6299 #define DMA_LIFCR_CTCIF3_Pos     (27U)
6300 #define DMA_LIFCR_CTCIF3_Msk     (0x1UL << DMA_LIFCR_CTCIF3_Pos)                /*!< 0x08000000 */
6301 #define DMA_LIFCR_CTCIF3         DMA_LIFCR_CTCIF3_Msk
6302 #define DMA_LIFCR_CHTIF3_Pos     (26U)
6303 #define DMA_LIFCR_CHTIF3_Msk     (0x1UL << DMA_LIFCR_CHTIF3_Pos)                /*!< 0x04000000 */
6304 #define DMA_LIFCR_CHTIF3         DMA_LIFCR_CHTIF3_Msk
6305 #define DMA_LIFCR_CTEIF3_Pos     (25U)
6306 #define DMA_LIFCR_CTEIF3_Msk     (0x1UL << DMA_LIFCR_CTEIF3_Pos)                /*!< 0x02000000 */
6307 #define DMA_LIFCR_CTEIF3         DMA_LIFCR_CTEIF3_Msk
6308 #define DMA_LIFCR_CDMEIF3_Pos    (24U)
6309 #define DMA_LIFCR_CDMEIF3_Msk    (0x1UL << DMA_LIFCR_CDMEIF3_Pos)               /*!< 0x01000000 */
6310 #define DMA_LIFCR_CDMEIF3        DMA_LIFCR_CDMEIF3_Msk
6311 #define DMA_LIFCR_CFEIF3_Pos     (22U)
6312 #define DMA_LIFCR_CFEIF3_Msk     (0x1UL << DMA_LIFCR_CFEIF3_Pos)                /*!< 0x00400000 */
6313 #define DMA_LIFCR_CFEIF3         DMA_LIFCR_CFEIF3_Msk
6314 #define DMA_LIFCR_CTCIF2_Pos     (21U)
6315 #define DMA_LIFCR_CTCIF2_Msk     (0x1UL << DMA_LIFCR_CTCIF2_Pos)                /*!< 0x00200000 */
6316 #define DMA_LIFCR_CTCIF2         DMA_LIFCR_CTCIF2_Msk
6317 #define DMA_LIFCR_CHTIF2_Pos     (20U)
6318 #define DMA_LIFCR_CHTIF2_Msk     (0x1UL << DMA_LIFCR_CHTIF2_Pos)                /*!< 0x00100000 */
6319 #define DMA_LIFCR_CHTIF2         DMA_LIFCR_CHTIF2_Msk
6320 #define DMA_LIFCR_CTEIF2_Pos     (19U)
6321 #define DMA_LIFCR_CTEIF2_Msk     (0x1UL << DMA_LIFCR_CTEIF2_Pos)                /*!< 0x00080000 */
6322 #define DMA_LIFCR_CTEIF2         DMA_LIFCR_CTEIF2_Msk
6323 #define DMA_LIFCR_CDMEIF2_Pos    (18U)
6324 #define DMA_LIFCR_CDMEIF2_Msk    (0x1UL << DMA_LIFCR_CDMEIF2_Pos)               /*!< 0x00040000 */
6325 #define DMA_LIFCR_CDMEIF2        DMA_LIFCR_CDMEIF2_Msk
6326 #define DMA_LIFCR_CFEIF2_Pos     (16U)
6327 #define DMA_LIFCR_CFEIF2_Msk     (0x1UL << DMA_LIFCR_CFEIF2_Pos)                /*!< 0x00010000 */
6328 #define DMA_LIFCR_CFEIF2         DMA_LIFCR_CFEIF2_Msk
6329 #define DMA_LIFCR_CTCIF1_Pos     (11U)
6330 #define DMA_LIFCR_CTCIF1_Msk     (0x1UL << DMA_LIFCR_CTCIF1_Pos)                /*!< 0x00000800 */
6331 #define DMA_LIFCR_CTCIF1         DMA_LIFCR_CTCIF1_Msk
6332 #define DMA_LIFCR_CHTIF1_Pos     (10U)
6333 #define DMA_LIFCR_CHTIF1_Msk     (0x1UL << DMA_LIFCR_CHTIF1_Pos)                /*!< 0x00000400 */
6334 #define DMA_LIFCR_CHTIF1         DMA_LIFCR_CHTIF1_Msk
6335 #define DMA_LIFCR_CTEIF1_Pos     (9U)
6336 #define DMA_LIFCR_CTEIF1_Msk     (0x1UL << DMA_LIFCR_CTEIF1_Pos)                /*!< 0x00000200 */
6337 #define DMA_LIFCR_CTEIF1         DMA_LIFCR_CTEIF1_Msk
6338 #define DMA_LIFCR_CDMEIF1_Pos    (8U)
6339 #define DMA_LIFCR_CDMEIF1_Msk    (0x1UL << DMA_LIFCR_CDMEIF1_Pos)               /*!< 0x00000100 */
6340 #define DMA_LIFCR_CDMEIF1        DMA_LIFCR_CDMEIF1_Msk
6341 #define DMA_LIFCR_CFEIF1_Pos     (6U)
6342 #define DMA_LIFCR_CFEIF1_Msk     (0x1UL << DMA_LIFCR_CFEIF1_Pos)                /*!< 0x00000040 */
6343 #define DMA_LIFCR_CFEIF1         DMA_LIFCR_CFEIF1_Msk
6344 #define DMA_LIFCR_CTCIF0_Pos     (5U)
6345 #define DMA_LIFCR_CTCIF0_Msk     (0x1UL << DMA_LIFCR_CTCIF0_Pos)                /*!< 0x00000020 */
6346 #define DMA_LIFCR_CTCIF0         DMA_LIFCR_CTCIF0_Msk
6347 #define DMA_LIFCR_CHTIF0_Pos     (4U)
6348 #define DMA_LIFCR_CHTIF0_Msk     (0x1UL << DMA_LIFCR_CHTIF0_Pos)                /*!< 0x00000010 */
6349 #define DMA_LIFCR_CHTIF0         DMA_LIFCR_CHTIF0_Msk
6350 #define DMA_LIFCR_CTEIF0_Pos     (3U)
6351 #define DMA_LIFCR_CTEIF0_Msk     (0x1UL << DMA_LIFCR_CTEIF0_Pos)                /*!< 0x00000008 */
6352 #define DMA_LIFCR_CTEIF0         DMA_LIFCR_CTEIF0_Msk
6353 #define DMA_LIFCR_CDMEIF0_Pos    (2U)
6354 #define DMA_LIFCR_CDMEIF0_Msk    (0x1UL << DMA_LIFCR_CDMEIF0_Pos)               /*!< 0x00000004 */
6355 #define DMA_LIFCR_CDMEIF0        DMA_LIFCR_CDMEIF0_Msk
6356 #define DMA_LIFCR_CFEIF0_Pos     (0U)
6357 #define DMA_LIFCR_CFEIF0_Msk     (0x1UL << DMA_LIFCR_CFEIF0_Pos)                /*!< 0x00000001 */
6358 #define DMA_LIFCR_CFEIF0         DMA_LIFCR_CFEIF0_Msk
6359 
6360 /********************  Bits definition for DMA_HIFCR  register  ****************/
6361 #define DMA_HIFCR_CTCIF7_Pos     (27U)
6362 #define DMA_HIFCR_CTCIF7_Msk     (0x1UL << DMA_HIFCR_CTCIF7_Pos)                /*!< 0x08000000 */
6363 #define DMA_HIFCR_CTCIF7         DMA_HIFCR_CTCIF7_Msk
6364 #define DMA_HIFCR_CHTIF7_Pos     (26U)
6365 #define DMA_HIFCR_CHTIF7_Msk     (0x1UL << DMA_HIFCR_CHTIF7_Pos)                /*!< 0x04000000 */
6366 #define DMA_HIFCR_CHTIF7         DMA_HIFCR_CHTIF7_Msk
6367 #define DMA_HIFCR_CTEIF7_Pos     (25U)
6368 #define DMA_HIFCR_CTEIF7_Msk     (0x1UL << DMA_HIFCR_CTEIF7_Pos)                /*!< 0x02000000 */
6369 #define DMA_HIFCR_CTEIF7         DMA_HIFCR_CTEIF7_Msk
6370 #define DMA_HIFCR_CDMEIF7_Pos    (24U)
6371 #define DMA_HIFCR_CDMEIF7_Msk    (0x1UL << DMA_HIFCR_CDMEIF7_Pos)               /*!< 0x01000000 */
6372 #define DMA_HIFCR_CDMEIF7        DMA_HIFCR_CDMEIF7_Msk
6373 #define DMA_HIFCR_CFEIF7_Pos     (22U)
6374 #define DMA_HIFCR_CFEIF7_Msk     (0x1UL << DMA_HIFCR_CFEIF7_Pos)                /*!< 0x00400000 */
6375 #define DMA_HIFCR_CFEIF7         DMA_HIFCR_CFEIF7_Msk
6376 #define DMA_HIFCR_CTCIF6_Pos     (21U)
6377 #define DMA_HIFCR_CTCIF6_Msk     (0x1UL << DMA_HIFCR_CTCIF6_Pos)                /*!< 0x00200000 */
6378 #define DMA_HIFCR_CTCIF6         DMA_HIFCR_CTCIF6_Msk
6379 #define DMA_HIFCR_CHTIF6_Pos     (20U)
6380 #define DMA_HIFCR_CHTIF6_Msk     (0x1UL << DMA_HIFCR_CHTIF6_Pos)                /*!< 0x00100000 */
6381 #define DMA_HIFCR_CHTIF6         DMA_HIFCR_CHTIF6_Msk
6382 #define DMA_HIFCR_CTEIF6_Pos     (19U)
6383 #define DMA_HIFCR_CTEIF6_Msk     (0x1UL << DMA_HIFCR_CTEIF6_Pos)                /*!< 0x00080000 */
6384 #define DMA_HIFCR_CTEIF6         DMA_HIFCR_CTEIF6_Msk
6385 #define DMA_HIFCR_CDMEIF6_Pos    (18U)
6386 #define DMA_HIFCR_CDMEIF6_Msk    (0x1UL << DMA_HIFCR_CDMEIF6_Pos)               /*!< 0x00040000 */
6387 #define DMA_HIFCR_CDMEIF6        DMA_HIFCR_CDMEIF6_Msk
6388 #define DMA_HIFCR_CFEIF6_Pos     (16U)
6389 #define DMA_HIFCR_CFEIF6_Msk     (0x1UL << DMA_HIFCR_CFEIF6_Pos)                /*!< 0x00010000 */
6390 #define DMA_HIFCR_CFEIF6         DMA_HIFCR_CFEIF6_Msk
6391 #define DMA_HIFCR_CTCIF5_Pos     (11U)
6392 #define DMA_HIFCR_CTCIF5_Msk     (0x1UL << DMA_HIFCR_CTCIF5_Pos)                /*!< 0x00000800 */
6393 #define DMA_HIFCR_CTCIF5         DMA_HIFCR_CTCIF5_Msk
6394 #define DMA_HIFCR_CHTIF5_Pos     (10U)
6395 #define DMA_HIFCR_CHTIF5_Msk     (0x1UL << DMA_HIFCR_CHTIF5_Pos)                /*!< 0x00000400 */
6396 #define DMA_HIFCR_CHTIF5         DMA_HIFCR_CHTIF5_Msk
6397 #define DMA_HIFCR_CTEIF5_Pos     (9U)
6398 #define DMA_HIFCR_CTEIF5_Msk     (0x1UL << DMA_HIFCR_CTEIF5_Pos)                /*!< 0x00000200 */
6399 #define DMA_HIFCR_CTEIF5         DMA_HIFCR_CTEIF5_Msk
6400 #define DMA_HIFCR_CDMEIF5_Pos    (8U)
6401 #define DMA_HIFCR_CDMEIF5_Msk    (0x1UL << DMA_HIFCR_CDMEIF5_Pos)               /*!< 0x00000100 */
6402 #define DMA_HIFCR_CDMEIF5        DMA_HIFCR_CDMEIF5_Msk
6403 #define DMA_HIFCR_CFEIF5_Pos     (6U)
6404 #define DMA_HIFCR_CFEIF5_Msk     (0x1UL << DMA_HIFCR_CFEIF5_Pos)                /*!< 0x00000040 */
6405 #define DMA_HIFCR_CFEIF5         DMA_HIFCR_CFEIF5_Msk
6406 #define DMA_HIFCR_CTCIF4_Pos     (5U)
6407 #define DMA_HIFCR_CTCIF4_Msk     (0x1UL << DMA_HIFCR_CTCIF4_Pos)                /*!< 0x00000020 */
6408 #define DMA_HIFCR_CTCIF4         DMA_HIFCR_CTCIF4_Msk
6409 #define DMA_HIFCR_CHTIF4_Pos     (4U)
6410 #define DMA_HIFCR_CHTIF4_Msk     (0x1UL << DMA_HIFCR_CHTIF4_Pos)                /*!< 0x00000010 */
6411 #define DMA_HIFCR_CHTIF4         DMA_HIFCR_CHTIF4_Msk
6412 #define DMA_HIFCR_CTEIF4_Pos     (3U)
6413 #define DMA_HIFCR_CTEIF4_Msk     (0x1UL << DMA_HIFCR_CTEIF4_Pos)                /*!< 0x00000008 */
6414 #define DMA_HIFCR_CTEIF4         DMA_HIFCR_CTEIF4_Msk
6415 #define DMA_HIFCR_CDMEIF4_Pos    (2U)
6416 #define DMA_HIFCR_CDMEIF4_Msk    (0x1UL << DMA_HIFCR_CDMEIF4_Pos)               /*!< 0x00000004 */
6417 #define DMA_HIFCR_CDMEIF4        DMA_HIFCR_CDMEIF4_Msk
6418 #define DMA_HIFCR_CFEIF4_Pos     (0U)
6419 #define DMA_HIFCR_CFEIF4_Msk     (0x1UL << DMA_HIFCR_CFEIF4_Pos)                /*!< 0x00000001 */
6420 #define DMA_HIFCR_CFEIF4         DMA_HIFCR_CFEIF4_Msk
6421 
6422 /******************  Bit definition for DMA_SxPAR register  ********************/
6423 #define DMA_SxPAR_PA_Pos         (0U)
6424 #define DMA_SxPAR_PA_Msk         (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos)             /*!< 0xFFFFFFFF */
6425 #define DMA_SxPAR_PA             DMA_SxPAR_PA_Msk                              /*!< Peripheral Address */
6426 
6427 /******************  Bit definition for DMA_SxM0AR register  ********************/
6428 #define DMA_SxM0AR_M0A_Pos       (0U)
6429 #define DMA_SxM0AR_M0A_Msk       (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos)           /*!< 0xFFFFFFFF */
6430 #define DMA_SxM0AR_M0A           DMA_SxM0AR_M0A_Msk                            /*!< Memory Address */
6431 
6432 /******************  Bit definition for DMA_SxM1AR register  ********************/
6433 #define DMA_SxM1AR_M1A_Pos       (0U)
6434 #define DMA_SxM1AR_M1A_Msk       (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos)           /*!< 0xFFFFFFFF */
6435 #define DMA_SxM1AR_M1A           DMA_SxM1AR_M1A_Msk                            /*!< Memory Address */
6436 
6437 
6438 /******************************************************************************/
6439 /*                                                                            */
6440 /*                         AHB Master DMA2D Controller (DMA2D)                */
6441 /*                                                                            */
6442 /******************************************************************************/
6443 
6444 /********************  Bit definition for DMA2D_CR register  ******************/
6445 
6446 #define DMA2D_CR_START_Pos         (0U)
6447 #define DMA2D_CR_START_Msk         (0x1UL << DMA2D_CR_START_Pos)                /*!< 0x00000001 */
6448 #define DMA2D_CR_START             DMA2D_CR_START_Msk                          /*!< Start transfer */
6449 #define DMA2D_CR_SUSP_Pos          (1U)
6450 #define DMA2D_CR_SUSP_Msk          (0x1UL << DMA2D_CR_SUSP_Pos)                 /*!< 0x00000002 */
6451 #define DMA2D_CR_SUSP              DMA2D_CR_SUSP_Msk                           /*!< Suspend transfer */
6452 #define DMA2D_CR_ABORT_Pos         (2U)
6453 #define DMA2D_CR_ABORT_Msk         (0x1UL << DMA2D_CR_ABORT_Pos)                /*!< 0x00000004 */
6454 #define DMA2D_CR_ABORT             DMA2D_CR_ABORT_Msk                          /*!< Abort transfer */
6455 #define DMA2D_CR_TEIE_Pos          (8U)
6456 #define DMA2D_CR_TEIE_Msk          (0x1UL << DMA2D_CR_TEIE_Pos)                 /*!< 0x00000100 */
6457 #define DMA2D_CR_TEIE              DMA2D_CR_TEIE_Msk                           /*!< Transfer Error Interrupt Enable */
6458 #define DMA2D_CR_TCIE_Pos          (9U)
6459 #define DMA2D_CR_TCIE_Msk          (0x1UL << DMA2D_CR_TCIE_Pos)                 /*!< 0x00000200 */
6460 #define DMA2D_CR_TCIE              DMA2D_CR_TCIE_Msk                           /*!< Transfer Complete Interrupt Enable */
6461 #define DMA2D_CR_TWIE_Pos          (10U)
6462 #define DMA2D_CR_TWIE_Msk          (0x1UL << DMA2D_CR_TWIE_Pos)                 /*!< 0x00000400 */
6463 #define DMA2D_CR_TWIE              DMA2D_CR_TWIE_Msk                           /*!< Transfer Watermark Interrupt Enable */
6464 #define DMA2D_CR_CAEIE_Pos         (11U)
6465 #define DMA2D_CR_CAEIE_Msk         (0x1UL << DMA2D_CR_CAEIE_Pos)                /*!< 0x00000800 */
6466 #define DMA2D_CR_CAEIE             DMA2D_CR_CAEIE_Msk                          /*!< CLUT Access Error Interrupt Enable */
6467 #define DMA2D_CR_CTCIE_Pos         (12U)
6468 #define DMA2D_CR_CTCIE_Msk         (0x1UL << DMA2D_CR_CTCIE_Pos)                /*!< 0x00001000 */
6469 #define DMA2D_CR_CTCIE             DMA2D_CR_CTCIE_Msk                          /*!< CLUT Transfer Complete Interrupt Enable */
6470 #define DMA2D_CR_CEIE_Pos          (13U)
6471 #define DMA2D_CR_CEIE_Msk          (0x1UL << DMA2D_CR_CEIE_Pos)                 /*!< 0x00002000 */
6472 #define DMA2D_CR_CEIE              DMA2D_CR_CEIE_Msk                           /*!< Configuration Error Interrupt Enable */
6473 #define DMA2D_CR_MODE_Pos          (16U)
6474 #define DMA2D_CR_MODE_Msk          (0x3UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00030000 */
6475 #define DMA2D_CR_MODE              DMA2D_CR_MODE_Msk                           /*!< DMA2D Mode[1:0] */
6476 #define DMA2D_CR_MODE_0            (0x1UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00010000 */
6477 #define DMA2D_CR_MODE_1            (0x2UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00020000 */
6478 
6479 /********************  Bit definition for DMA2D_ISR register  *****************/
6480 
6481 #define DMA2D_ISR_TEIF_Pos         (0U)
6482 #define DMA2D_ISR_TEIF_Msk         (0x1UL << DMA2D_ISR_TEIF_Pos)                /*!< 0x00000001 */
6483 #define DMA2D_ISR_TEIF             DMA2D_ISR_TEIF_Msk                          /*!< Transfer Error Interrupt Flag */
6484 #define DMA2D_ISR_TCIF_Pos         (1U)
6485 #define DMA2D_ISR_TCIF_Msk         (0x1UL << DMA2D_ISR_TCIF_Pos)                /*!< 0x00000002 */
6486 #define DMA2D_ISR_TCIF             DMA2D_ISR_TCIF_Msk                          /*!< Transfer Complete Interrupt Flag */
6487 #define DMA2D_ISR_TWIF_Pos         (2U)
6488 #define DMA2D_ISR_TWIF_Msk         (0x1UL << DMA2D_ISR_TWIF_Pos)                /*!< 0x00000004 */
6489 #define DMA2D_ISR_TWIF             DMA2D_ISR_TWIF_Msk                          /*!< Transfer Watermark Interrupt Flag */
6490 #define DMA2D_ISR_CAEIF_Pos        (3U)
6491 #define DMA2D_ISR_CAEIF_Msk        (0x1UL << DMA2D_ISR_CAEIF_Pos)               /*!< 0x00000008 */
6492 #define DMA2D_ISR_CAEIF            DMA2D_ISR_CAEIF_Msk                         /*!< CLUT Access Error Interrupt Flag */
6493 #define DMA2D_ISR_CTCIF_Pos        (4U)
6494 #define DMA2D_ISR_CTCIF_Msk        (0x1UL << DMA2D_ISR_CTCIF_Pos)               /*!< 0x00000010 */
6495 #define DMA2D_ISR_CTCIF            DMA2D_ISR_CTCIF_Msk                         /*!< CLUT Transfer Complete Interrupt Flag */
6496 #define DMA2D_ISR_CEIF_Pos         (5U)
6497 #define DMA2D_ISR_CEIF_Msk         (0x1UL << DMA2D_ISR_CEIF_Pos)                /*!< 0x00000020 */
6498 #define DMA2D_ISR_CEIF             DMA2D_ISR_CEIF_Msk                          /*!< Configuration Error Interrupt Flag */
6499 
6500 /********************  Bit definition for DMA2D_IFCR register  ****************/
6501 
6502 #define DMA2D_IFCR_CTEIF_Pos       (0U)
6503 #define DMA2D_IFCR_CTEIF_Msk       (0x1UL << DMA2D_IFCR_CTEIF_Pos)              /*!< 0x00000001 */
6504 #define DMA2D_IFCR_CTEIF           DMA2D_IFCR_CTEIF_Msk                        /*!< Clears Transfer Error Interrupt Flag         */
6505 #define DMA2D_IFCR_CTCIF_Pos       (1U)
6506 #define DMA2D_IFCR_CTCIF_Msk       (0x1UL << DMA2D_IFCR_CTCIF_Pos)              /*!< 0x00000002 */
6507 #define DMA2D_IFCR_CTCIF           DMA2D_IFCR_CTCIF_Msk                        /*!< Clears Transfer Complete Interrupt Flag      */
6508 #define DMA2D_IFCR_CTWIF_Pos       (2U)
6509 #define DMA2D_IFCR_CTWIF_Msk       (0x1UL << DMA2D_IFCR_CTWIF_Pos)              /*!< 0x00000004 */
6510 #define DMA2D_IFCR_CTWIF           DMA2D_IFCR_CTWIF_Msk                        /*!< Clears Transfer Watermark Interrupt Flag     */
6511 #define DMA2D_IFCR_CAECIF_Pos      (3U)
6512 #define DMA2D_IFCR_CAECIF_Msk      (0x1UL << DMA2D_IFCR_CAECIF_Pos)             /*!< 0x00000008 */
6513 #define DMA2D_IFCR_CAECIF          DMA2D_IFCR_CAECIF_Msk                       /*!< Clears CLUT Access Error Interrupt Flag      */
6514 #define DMA2D_IFCR_CCTCIF_Pos      (4U)
6515 #define DMA2D_IFCR_CCTCIF_Msk      (0x1UL << DMA2D_IFCR_CCTCIF_Pos)             /*!< 0x00000010 */
6516 #define DMA2D_IFCR_CCTCIF          DMA2D_IFCR_CCTCIF_Msk                       /*!< Clears CLUT Transfer Complete Interrupt Flag */
6517 #define DMA2D_IFCR_CCEIF_Pos       (5U)
6518 #define DMA2D_IFCR_CCEIF_Msk       (0x1UL << DMA2D_IFCR_CCEIF_Pos)              /*!< 0x00000020 */
6519 #define DMA2D_IFCR_CCEIF           DMA2D_IFCR_CCEIF_Msk                        /*!< Clears Configuration Error Interrupt Flag    */
6520 
6521 /* Legacy defines */
6522 #define DMA2D_IFSR_CTEIF                   DMA2D_IFCR_CTEIF                     /*!< Clears Transfer Error Interrupt Flag         */
6523 #define DMA2D_IFSR_CTCIF                   DMA2D_IFCR_CTCIF                     /*!< Clears Transfer Complete Interrupt Flag      */
6524 #define DMA2D_IFSR_CTWIF                   DMA2D_IFCR_CTWIF                     /*!< Clears Transfer Watermark Interrupt Flag     */
6525 #define DMA2D_IFSR_CCAEIF                  DMA2D_IFCR_CAECIF                    /*!< Clears CLUT Access Error Interrupt Flag      */
6526 #define DMA2D_IFSR_CCTCIF                  DMA2D_IFCR_CCTCIF                    /*!< Clears CLUT Transfer Complete Interrupt Flag */
6527 #define DMA2D_IFSR_CCEIF                   DMA2D_IFCR_CCEIF                     /*!< Clears Configuration Error Interrupt Flag    */
6528 
6529 /********************  Bit definition for DMA2D_FGMAR register  ***************/
6530 
6531 #define DMA2D_FGMAR_MA_Pos         (0U)
6532 #define DMA2D_FGMAR_MA_Msk         (0xFFFFFFFFUL << DMA2D_FGMAR_MA_Pos)         /*!< 0xFFFFFFFF */
6533 #define DMA2D_FGMAR_MA             DMA2D_FGMAR_MA_Msk                          /*!< Memory Address */
6534 
6535 /********************  Bit definition for DMA2D_FGOR register  ****************/
6536 
6537 #define DMA2D_FGOR_LO_Pos          (0U)
6538 #define DMA2D_FGOR_LO_Msk          (0x3FFFUL << DMA2D_FGOR_LO_Pos)              /*!< 0x00003FFF */
6539 #define DMA2D_FGOR_LO              DMA2D_FGOR_LO_Msk                           /*!< Line Offset */
6540 
6541 /********************  Bit definition for DMA2D_BGMAR register  ***************/
6542 
6543 #define DMA2D_BGMAR_MA_Pos         (0U)
6544 #define DMA2D_BGMAR_MA_Msk         (0xFFFFFFFFUL << DMA2D_BGMAR_MA_Pos)         /*!< 0xFFFFFFFF */
6545 #define DMA2D_BGMAR_MA             DMA2D_BGMAR_MA_Msk                          /*!< Memory Address */
6546 
6547 /********************  Bit definition for DMA2D_BGOR register  ****************/
6548 
6549 #define DMA2D_BGOR_LO_Pos          (0U)
6550 #define DMA2D_BGOR_LO_Msk          (0x3FFFUL << DMA2D_BGOR_LO_Pos)              /*!< 0x00003FFF */
6551 #define DMA2D_BGOR_LO              DMA2D_BGOR_LO_Msk                           /*!< Line Offset */
6552 
6553 /********************  Bit definition for DMA2D_FGPFCCR register  *************/
6554 
6555 #define DMA2D_FGPFCCR_CM_Pos       (0U)
6556 #define DMA2D_FGPFCCR_CM_Msk       (0xFUL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x0000000F */
6557 #define DMA2D_FGPFCCR_CM           DMA2D_FGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */
6558 #define DMA2D_FGPFCCR_CM_0         (0x1UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000001 */
6559 #define DMA2D_FGPFCCR_CM_1         (0x2UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000002 */
6560 #define DMA2D_FGPFCCR_CM_2         (0x4UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000004 */
6561 #define DMA2D_FGPFCCR_CM_3         (0x8UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000008 */
6562 #define DMA2D_FGPFCCR_CCM_Pos      (4U)
6563 #define DMA2D_FGPFCCR_CCM_Msk      (0x1UL << DMA2D_FGPFCCR_CCM_Pos)             /*!< 0x00000010 */
6564 #define DMA2D_FGPFCCR_CCM          DMA2D_FGPFCCR_CCM_Msk                       /*!< CLUT Color mode */
6565 #define DMA2D_FGPFCCR_START_Pos    (5U)
6566 #define DMA2D_FGPFCCR_START_Msk    (0x1UL << DMA2D_FGPFCCR_START_Pos)           /*!< 0x00000020 */
6567 #define DMA2D_FGPFCCR_START        DMA2D_FGPFCCR_START_Msk                     /*!< Start */
6568 #define DMA2D_FGPFCCR_CS_Pos       (8U)
6569 #define DMA2D_FGPFCCR_CS_Msk       (0xFFUL << DMA2D_FGPFCCR_CS_Pos)             /*!< 0x0000FF00 */
6570 #define DMA2D_FGPFCCR_CS           DMA2D_FGPFCCR_CS_Msk                        /*!< CLUT size */
6571 #define DMA2D_FGPFCCR_AM_Pos       (16U)
6572 #define DMA2D_FGPFCCR_AM_Msk       (0x3UL << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00030000 */
6573 #define DMA2D_FGPFCCR_AM           DMA2D_FGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */
6574 #define DMA2D_FGPFCCR_AM_0         (0x1UL << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00010000 */
6575 #define DMA2D_FGPFCCR_AM_1         (0x2UL << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00020000 */
6576 #define DMA2D_FGPFCCR_ALPHA_Pos    (24U)
6577 #define DMA2D_FGPFCCR_ALPHA_Msk    (0xFFUL << DMA2D_FGPFCCR_ALPHA_Pos)          /*!< 0xFF000000 */
6578 #define DMA2D_FGPFCCR_ALPHA        DMA2D_FGPFCCR_ALPHA_Msk                     /*!< Alpha value */
6579 
6580 /********************  Bit definition for DMA2D_FGCOLR register  **************/
6581 
6582 #define DMA2D_FGCOLR_BLUE_Pos      (0U)
6583 #define DMA2D_FGCOLR_BLUE_Msk      (0xFFUL << DMA2D_FGCOLR_BLUE_Pos)            /*!< 0x000000FF */
6584 #define DMA2D_FGCOLR_BLUE          DMA2D_FGCOLR_BLUE_Msk                       /*!< Blue Value */
6585 #define DMA2D_FGCOLR_GREEN_Pos     (8U)
6586 #define DMA2D_FGCOLR_GREEN_Msk     (0xFFUL << DMA2D_FGCOLR_GREEN_Pos)           /*!< 0x0000FF00 */
6587 #define DMA2D_FGCOLR_GREEN         DMA2D_FGCOLR_GREEN_Msk                      /*!< Green Value */
6588 #define DMA2D_FGCOLR_RED_Pos       (16U)
6589 #define DMA2D_FGCOLR_RED_Msk       (0xFFUL << DMA2D_FGCOLR_RED_Pos)             /*!< 0x00FF0000 */
6590 #define DMA2D_FGCOLR_RED           DMA2D_FGCOLR_RED_Msk                        /*!< Red Value */
6591 
6592 /********************  Bit definition for DMA2D_BGPFCCR register  *************/
6593 
6594 #define DMA2D_BGPFCCR_CM_Pos       (0U)
6595 #define DMA2D_BGPFCCR_CM_Msk       (0xFUL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x0000000F */
6596 #define DMA2D_BGPFCCR_CM           DMA2D_BGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */
6597 #define DMA2D_BGPFCCR_CM_0         (0x1UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000001 */
6598 #define DMA2D_BGPFCCR_CM_1         (0x2UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000002 */
6599 #define DMA2D_BGPFCCR_CM_2         (0x4UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000004 */
6600 #define DMA2D_BGPFCCR_CM_3         0x00000008U                                 /*!< Input color mode CM bit 3 */
6601 #define DMA2D_BGPFCCR_CCM_Pos      (4U)
6602 #define DMA2D_BGPFCCR_CCM_Msk      (0x1UL << DMA2D_BGPFCCR_CCM_Pos)             /*!< 0x00000010 */
6603 #define DMA2D_BGPFCCR_CCM          DMA2D_BGPFCCR_CCM_Msk                       /*!< CLUT Color mode */
6604 #define DMA2D_BGPFCCR_START_Pos    (5U)
6605 #define DMA2D_BGPFCCR_START_Msk    (0x1UL << DMA2D_BGPFCCR_START_Pos)           /*!< 0x00000020 */
6606 #define DMA2D_BGPFCCR_START        DMA2D_BGPFCCR_START_Msk                     /*!< Start */
6607 #define DMA2D_BGPFCCR_CS_Pos       (8U)
6608 #define DMA2D_BGPFCCR_CS_Msk       (0xFFUL << DMA2D_BGPFCCR_CS_Pos)             /*!< 0x0000FF00 */
6609 #define DMA2D_BGPFCCR_CS           DMA2D_BGPFCCR_CS_Msk                        /*!< CLUT size */
6610 #define DMA2D_BGPFCCR_AM_Pos       (16U)
6611 #define DMA2D_BGPFCCR_AM_Msk       (0x3UL << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00030000 */
6612 #define DMA2D_BGPFCCR_AM           DMA2D_BGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */
6613 #define DMA2D_BGPFCCR_AM_0         (0x1UL << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00010000 */
6614 #define DMA2D_BGPFCCR_AM_1         (0x2UL << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00020000 */
6615 #define DMA2D_BGPFCCR_ALPHA_Pos    (24U)
6616 #define DMA2D_BGPFCCR_ALPHA_Msk    (0xFFUL << DMA2D_BGPFCCR_ALPHA_Pos)          /*!< 0xFF000000 */
6617 #define DMA2D_BGPFCCR_ALPHA        DMA2D_BGPFCCR_ALPHA_Msk                     /*!< background Input Alpha value */
6618 
6619 /********************  Bit definition for DMA2D_BGCOLR register  **************/
6620 
6621 #define DMA2D_BGCOLR_BLUE_Pos      (0U)
6622 #define DMA2D_BGCOLR_BLUE_Msk      (0xFFUL << DMA2D_BGCOLR_BLUE_Pos)            /*!< 0x000000FF */
6623 #define DMA2D_BGCOLR_BLUE          DMA2D_BGCOLR_BLUE_Msk                       /*!< Blue Value */
6624 #define DMA2D_BGCOLR_GREEN_Pos     (8U)
6625 #define DMA2D_BGCOLR_GREEN_Msk     (0xFFUL << DMA2D_BGCOLR_GREEN_Pos)           /*!< 0x0000FF00 */
6626 #define DMA2D_BGCOLR_GREEN         DMA2D_BGCOLR_GREEN_Msk                      /*!< Green Value */
6627 #define DMA2D_BGCOLR_RED_Pos       (16U)
6628 #define DMA2D_BGCOLR_RED_Msk       (0xFFUL << DMA2D_BGCOLR_RED_Pos)             /*!< 0x00FF0000 */
6629 #define DMA2D_BGCOLR_RED           DMA2D_BGCOLR_RED_Msk                        /*!< Red Value */
6630 
6631 /********************  Bit definition for DMA2D_FGCMAR register  **************/
6632 
6633 #define DMA2D_FGCMAR_MA_Pos        (0U)
6634 #define DMA2D_FGCMAR_MA_Msk        (0xFFFFFFFFUL << DMA2D_FGCMAR_MA_Pos)        /*!< 0xFFFFFFFF */
6635 #define DMA2D_FGCMAR_MA            DMA2D_FGCMAR_MA_Msk                         /*!< Memory Address */
6636 
6637 /********************  Bit definition for DMA2D_BGCMAR register  **************/
6638 
6639 #define DMA2D_BGCMAR_MA_Pos        (0U)
6640 #define DMA2D_BGCMAR_MA_Msk        (0xFFFFFFFFUL << DMA2D_BGCMAR_MA_Pos)        /*!< 0xFFFFFFFF */
6641 #define DMA2D_BGCMAR_MA            DMA2D_BGCMAR_MA_Msk                         /*!< Memory Address */
6642 
6643 /********************  Bit definition for DMA2D_OPFCCR register  **************/
6644 
6645 #define DMA2D_OPFCCR_CM_Pos        (0U)
6646 #define DMA2D_OPFCCR_CM_Msk        (0x7UL << DMA2D_OPFCCR_CM_Pos)               /*!< 0x00000007 */
6647 #define DMA2D_OPFCCR_CM            DMA2D_OPFCCR_CM_Msk                         /*!< Color mode CM[2:0] */
6648 #define DMA2D_OPFCCR_CM_0          (0x1UL << DMA2D_OPFCCR_CM_Pos)               /*!< 0x00000001 */
6649 #define DMA2D_OPFCCR_CM_1          (0x2UL << DMA2D_OPFCCR_CM_Pos)               /*!< 0x00000002 */
6650 #define DMA2D_OPFCCR_CM_2          (0x4UL << DMA2D_OPFCCR_CM_Pos)               /*!< 0x00000004 */
6651 
6652 /********************  Bit definition for DMA2D_OCOLR register  ***************/
6653 
6654 /*!<Mode_ARGB8888/RGB888 */
6655 
6656 #define DMA2D_OCOLR_BLUE_1         0x000000FFU                                 /*!< BLUE Value */
6657 #define DMA2D_OCOLR_GREEN_1        0x0000FF00U                                 /*!< GREEN Value  */
6658 #define DMA2D_OCOLR_RED_1          0x00FF0000U                                 /*!< Red Value */
6659 #define DMA2D_OCOLR_ALPHA_1        0xFF000000U                                 /*!< Alpha Channel Value */
6660 
6661 /*!<Mode_RGB565 */
6662 #define DMA2D_OCOLR_BLUE_2         0x0000001FU                                 /*!< BLUE Value */
6663 #define DMA2D_OCOLR_GREEN_2        0x000007E0U                                 /*!< GREEN Value  */
6664 #define DMA2D_OCOLR_RED_2          0x0000F800U                                 /*!< Red Value */
6665 
6666 /*!<Mode_ARGB1555 */
6667 #define DMA2D_OCOLR_BLUE_3         0x0000001FU                                 /*!< BLUE Value */
6668 #define DMA2D_OCOLR_GREEN_3        0x000003E0U                                 /*!< GREEN Value  */
6669 #define DMA2D_OCOLR_RED_3          0x00007C00U                                 /*!< Red Value */
6670 #define DMA2D_OCOLR_ALPHA_3        0x00008000U                                 /*!< Alpha Channel Value */
6671 
6672 /*!<Mode_ARGB4444 */
6673 #define DMA2D_OCOLR_BLUE_4         0x0000000FU                                 /*!< BLUE Value */
6674 #define DMA2D_OCOLR_GREEN_4        0x000000F0U                                 /*!< GREEN Value  */
6675 #define DMA2D_OCOLR_RED_4          0x00000F00U                                 /*!< Red Value */
6676 #define DMA2D_OCOLR_ALPHA_4        0x0000F000U                                 /*!< Alpha Channel Value */
6677 
6678 /********************  Bit definition for DMA2D_OMAR register  ****************/
6679 
6680 #define DMA2D_OMAR_MA_Pos          (0U)
6681 #define DMA2D_OMAR_MA_Msk          (0xFFFFFFFFUL << DMA2D_OMAR_MA_Pos)          /*!< 0xFFFFFFFF */
6682 #define DMA2D_OMAR_MA              DMA2D_OMAR_MA_Msk                           /*!< Memory Address */
6683 
6684 /********************  Bit definition for DMA2D_OOR register  *****************/
6685 
6686 #define DMA2D_OOR_LO_Pos           (0U)
6687 #define DMA2D_OOR_LO_Msk           (0x3FFFUL << DMA2D_OOR_LO_Pos)               /*!< 0x00003FFF */
6688 #define DMA2D_OOR_LO               DMA2D_OOR_LO_Msk                            /*!< Line Offset */
6689 
6690 /********************  Bit definition for DMA2D_NLR register  *****************/
6691 
6692 #define DMA2D_NLR_NL_Pos           (0U)
6693 #define DMA2D_NLR_NL_Msk           (0xFFFFUL << DMA2D_NLR_NL_Pos)               /*!< 0x0000FFFF */
6694 #define DMA2D_NLR_NL               DMA2D_NLR_NL_Msk                            /*!< Number of Lines */
6695 #define DMA2D_NLR_PL_Pos           (16U)
6696 #define DMA2D_NLR_PL_Msk           (0x3FFFUL << DMA2D_NLR_PL_Pos)               /*!< 0x3FFF0000 */
6697 #define DMA2D_NLR_PL               DMA2D_NLR_PL_Msk                            /*!< Pixel per Lines */
6698 
6699 /********************  Bit definition for DMA2D_LWR register  *****************/
6700 
6701 #define DMA2D_LWR_LW_Pos           (0U)
6702 #define DMA2D_LWR_LW_Msk           (0xFFFFUL << DMA2D_LWR_LW_Pos)               /*!< 0x0000FFFF */
6703 #define DMA2D_LWR_LW               DMA2D_LWR_LW_Msk                            /*!< Line Watermark */
6704 
6705 /********************  Bit definition for DMA2D_AMTCR register  ***************/
6706 
6707 #define DMA2D_AMTCR_EN_Pos         (0U)
6708 #define DMA2D_AMTCR_EN_Msk         (0x1UL << DMA2D_AMTCR_EN_Pos)                /*!< 0x00000001 */
6709 #define DMA2D_AMTCR_EN             DMA2D_AMTCR_EN_Msk                          /*!< Enable */
6710 #define DMA2D_AMTCR_DT_Pos         (8U)
6711 #define DMA2D_AMTCR_DT_Msk         (0xFFUL << DMA2D_AMTCR_DT_Pos)               /*!< 0x0000FF00 */
6712 #define DMA2D_AMTCR_DT             DMA2D_AMTCR_DT_Msk                          /*!< Dead Time */
6713 
6714 /********************  Bit definition for DMA2D_FGCLUT register  **************/
6715 
6716 /********************  Bit definition for DMA2D_BGCLUT register  **************/
6717 
6718 
6719 /******************************************************************************/
6720 /*                                                                            */
6721 /*                     Display Serial Interface (DSI)                         */
6722 /*                                                                            */
6723 /******************************************************************************/
6724 /*******************  Bit definition for DSI_VR register  *****************/
6725 #define DSI_VR_Pos                    (1U)
6726 #define DSI_VR_Msk                    (0x18999815UL << DSI_VR_Pos)              /*!< 0x3133302A */
6727 #define DSI_VR                        DSI_VR_Msk                               /*!< DSI Host Version */
6728 
6729 /*******************  Bit definition for DSI_CR register  *****************/
6730 #define DSI_CR_EN_Pos                 (0U)
6731 #define DSI_CR_EN_Msk                 (0x1UL << DSI_CR_EN_Pos)                  /*!< 0x00000001 */
6732 #define DSI_CR_EN                     DSI_CR_EN_Msk                            /*!< DSI Host power up and reset */
6733 
6734 /*******************  Bit definition for DSI_CCR register  ****************/
6735 #define DSI_CCR_TXECKDIV_Pos          (0U)
6736 #define DSI_CCR_TXECKDIV_Msk          (0xFFUL << DSI_CCR_TXECKDIV_Pos)          /*!< 0x000000FF */
6737 #define DSI_CCR_TXECKDIV              DSI_CCR_TXECKDIV_Msk                     /*!< TX Escape Clock Division */
6738 #define DSI_CCR_TXECKDIV0_Pos         (0U)
6739 #define DSI_CCR_TXECKDIV0_Msk         (0x1UL << DSI_CCR_TXECKDIV0_Pos)          /*!< 0x00000001 */
6740 #define DSI_CCR_TXECKDIV0             DSI_CCR_TXECKDIV0_Msk
6741 #define DSI_CCR_TXECKDIV1_Pos         (1U)
6742 #define DSI_CCR_TXECKDIV1_Msk         (0x1UL << DSI_CCR_TXECKDIV1_Pos)          /*!< 0x00000002 */
6743 #define DSI_CCR_TXECKDIV1             DSI_CCR_TXECKDIV1_Msk
6744 #define DSI_CCR_TXECKDIV2_Pos         (2U)
6745 #define DSI_CCR_TXECKDIV2_Msk         (0x1UL << DSI_CCR_TXECKDIV2_Pos)          /*!< 0x00000004 */
6746 #define DSI_CCR_TXECKDIV2             DSI_CCR_TXECKDIV2_Msk
6747 #define DSI_CCR_TXECKDIV3_Pos         (3U)
6748 #define DSI_CCR_TXECKDIV3_Msk         (0x1UL << DSI_CCR_TXECKDIV3_Pos)          /*!< 0x00000008 */
6749 #define DSI_CCR_TXECKDIV3             DSI_CCR_TXECKDIV3_Msk
6750 #define DSI_CCR_TXECKDIV4_Pos         (4U)
6751 #define DSI_CCR_TXECKDIV4_Msk         (0x1UL << DSI_CCR_TXECKDIV4_Pos)          /*!< 0x00000010 */
6752 #define DSI_CCR_TXECKDIV4             DSI_CCR_TXECKDIV4_Msk
6753 #define DSI_CCR_TXECKDIV5_Pos         (5U)
6754 #define DSI_CCR_TXECKDIV5_Msk         (0x1UL << DSI_CCR_TXECKDIV5_Pos)          /*!< 0x00000020 */
6755 #define DSI_CCR_TXECKDIV5             DSI_CCR_TXECKDIV5_Msk
6756 #define DSI_CCR_TXECKDIV6_Pos         (6U)
6757 #define DSI_CCR_TXECKDIV6_Msk         (0x1UL << DSI_CCR_TXECKDIV6_Pos)          /*!< 0x00000040 */
6758 #define DSI_CCR_TXECKDIV6             DSI_CCR_TXECKDIV6_Msk
6759 #define DSI_CCR_TXECKDIV7_Pos         (7U)
6760 #define DSI_CCR_TXECKDIV7_Msk         (0x1UL << DSI_CCR_TXECKDIV7_Pos)          /*!< 0x00000080 */
6761 #define DSI_CCR_TXECKDIV7             DSI_CCR_TXECKDIV7_Msk
6762 
6763 #define DSI_CCR_TOCKDIV_Pos           (8U)
6764 #define DSI_CCR_TOCKDIV_Msk           (0xFFUL << DSI_CCR_TOCKDIV_Pos)           /*!< 0x0000FF00 */
6765 #define DSI_CCR_TOCKDIV               DSI_CCR_TOCKDIV_Msk                      /*!< Timeout Clock Division */
6766 #define DSI_CCR_TOCKDIV0_Pos          (8U)
6767 #define DSI_CCR_TOCKDIV0_Msk          (0x1UL << DSI_CCR_TOCKDIV0_Pos)           /*!< 0x00000100 */
6768 #define DSI_CCR_TOCKDIV0              DSI_CCR_TOCKDIV0_Msk
6769 #define DSI_CCR_TOCKDIV1_Pos          (9U)
6770 #define DSI_CCR_TOCKDIV1_Msk          (0x1UL << DSI_CCR_TOCKDIV1_Pos)           /*!< 0x00000200 */
6771 #define DSI_CCR_TOCKDIV1              DSI_CCR_TOCKDIV1_Msk
6772 #define DSI_CCR_TOCKDIV2_Pos          (10U)
6773 #define DSI_CCR_TOCKDIV2_Msk          (0x1UL << DSI_CCR_TOCKDIV2_Pos)           /*!< 0x00000400 */
6774 #define DSI_CCR_TOCKDIV2              DSI_CCR_TOCKDIV2_Msk
6775 #define DSI_CCR_TOCKDIV3_Pos          (11U)
6776 #define DSI_CCR_TOCKDIV3_Msk          (0x1UL << DSI_CCR_TOCKDIV3_Pos)           /*!< 0x00000800 */
6777 #define DSI_CCR_TOCKDIV3              DSI_CCR_TOCKDIV3_Msk
6778 #define DSI_CCR_TOCKDIV4_Pos          (12U)
6779 #define DSI_CCR_TOCKDIV4_Msk          (0x1UL << DSI_CCR_TOCKDIV4_Pos)           /*!< 0x00001000 */
6780 #define DSI_CCR_TOCKDIV4              DSI_CCR_TOCKDIV4_Msk
6781 #define DSI_CCR_TOCKDIV5_Pos          (13U)
6782 #define DSI_CCR_TOCKDIV5_Msk          (0x1UL << DSI_CCR_TOCKDIV5_Pos)           /*!< 0x00002000 */
6783 #define DSI_CCR_TOCKDIV5              DSI_CCR_TOCKDIV5_Msk
6784 #define DSI_CCR_TOCKDIV6_Pos          (14U)
6785 #define DSI_CCR_TOCKDIV6_Msk          (0x1UL << DSI_CCR_TOCKDIV6_Pos)           /*!< 0x00004000 */
6786 #define DSI_CCR_TOCKDIV6              DSI_CCR_TOCKDIV6_Msk
6787 #define DSI_CCR_TOCKDIV7_Pos          (15U)
6788 #define DSI_CCR_TOCKDIV7_Msk          (0x1UL << DSI_CCR_TOCKDIV7_Pos)           /*!< 0x00008000 */
6789 #define DSI_CCR_TOCKDIV7              DSI_CCR_TOCKDIV7_Msk
6790 
6791 /*******************  Bit definition for DSI_LVCIDR register  *************/
6792 #define DSI_LVCIDR_VCID_Pos           (0U)
6793 #define DSI_LVCIDR_VCID_Msk           (0x3UL << DSI_LVCIDR_VCID_Pos)            /*!< 0x00000003 */
6794 #define DSI_LVCIDR_VCID               DSI_LVCIDR_VCID_Msk                      /*!< Virtual Channel ID */
6795 #define DSI_LVCIDR_VCID0_Pos          (0U)
6796 #define DSI_LVCIDR_VCID0_Msk          (0x1UL << DSI_LVCIDR_VCID0_Pos)           /*!< 0x00000001 */
6797 #define DSI_LVCIDR_VCID0              DSI_LVCIDR_VCID0_Msk
6798 #define DSI_LVCIDR_VCID1_Pos          (1U)
6799 #define DSI_LVCIDR_VCID1_Msk          (0x1UL << DSI_LVCIDR_VCID1_Pos)           /*!< 0x00000002 */
6800 #define DSI_LVCIDR_VCID1              DSI_LVCIDR_VCID1_Msk
6801 
6802 /*******************  Bit definition for DSI_LCOLCR register  *************/
6803 #define DSI_LCOLCR_COLC_Pos           (0U)
6804 #define DSI_LCOLCR_COLC_Msk           (0xFUL << DSI_LCOLCR_COLC_Pos)            /*!< 0x0000000F */
6805 #define DSI_LCOLCR_COLC               DSI_LCOLCR_COLC_Msk                      /*!< Color Coding */
6806 #define DSI_LCOLCR_COLC0_Pos          (0U)
6807 #define DSI_LCOLCR_COLC0_Msk          (0x1UL << DSI_LCOLCR_COLC0_Pos)           /*!< 0x00000001 */
6808 #define DSI_LCOLCR_COLC0              DSI_LCOLCR_COLC0_Msk
6809 #define DSI_LCOLCR_COLC1_Pos          (5U)
6810 #define DSI_LCOLCR_COLC1_Msk          (0x1UL << DSI_LCOLCR_COLC1_Pos)           /*!< 0x00000020 */
6811 #define DSI_LCOLCR_COLC1              DSI_LCOLCR_COLC1_Msk
6812 #define DSI_LCOLCR_COLC2_Pos          (6U)
6813 #define DSI_LCOLCR_COLC2_Msk          (0x1UL << DSI_LCOLCR_COLC2_Pos)           /*!< 0x00000040 */
6814 #define DSI_LCOLCR_COLC2              DSI_LCOLCR_COLC2_Msk
6815 #define DSI_LCOLCR_COLC3_Pos          (7U)
6816 #define DSI_LCOLCR_COLC3_Msk          (0x1UL << DSI_LCOLCR_COLC3_Pos)           /*!< 0x00000080 */
6817 #define DSI_LCOLCR_COLC3              DSI_LCOLCR_COLC3_Msk
6818 
6819 #define DSI_LCOLCR_LPE_Pos            (8U)
6820 #define DSI_LCOLCR_LPE_Msk            (0x1UL << DSI_LCOLCR_LPE_Pos)             /*!< 0x00000100 */
6821 #define DSI_LCOLCR_LPE                DSI_LCOLCR_LPE_Msk                       /*!< Loosly Packet Enable */
6822 
6823 /*******************  Bit definition for DSI_LPCR register  ***************/
6824 #define DSI_LPCR_DEP_Pos              (0U)
6825 #define DSI_LPCR_DEP_Msk              (0x1UL << DSI_LPCR_DEP_Pos)               /*!< 0x00000001 */
6826 #define DSI_LPCR_DEP                  DSI_LPCR_DEP_Msk                         /*!< Data Enable Polarity */
6827 #define DSI_LPCR_VSP_Pos              (1U)
6828 #define DSI_LPCR_VSP_Msk              (0x1UL << DSI_LPCR_VSP_Pos)               /*!< 0x00000002 */
6829 #define DSI_LPCR_VSP                  DSI_LPCR_VSP_Msk                         /*!< VSYNC Polarity */
6830 #define DSI_LPCR_HSP_Pos              (2U)
6831 #define DSI_LPCR_HSP_Msk              (0x1UL << DSI_LPCR_HSP_Pos)               /*!< 0x00000004 */
6832 #define DSI_LPCR_HSP                  DSI_LPCR_HSP_Msk                         /*!< HSYNC Polarity */
6833 
6834 /*******************  Bit definition for DSI_LPMCR register  **************/
6835 #define DSI_LPMCR_VLPSIZE_Pos         (0U)
6836 #define DSI_LPMCR_VLPSIZE_Msk         (0xFFUL << DSI_LPMCR_VLPSIZE_Pos)         /*!< 0x000000FF */
6837 #define DSI_LPMCR_VLPSIZE             DSI_LPMCR_VLPSIZE_Msk                    /*!< VACT Largest Packet Size */
6838 #define DSI_LPMCR_VLPSIZE0_Pos        (0U)
6839 #define DSI_LPMCR_VLPSIZE0_Msk        (0x1UL << DSI_LPMCR_VLPSIZE0_Pos)         /*!< 0x00000001 */
6840 #define DSI_LPMCR_VLPSIZE0            DSI_LPMCR_VLPSIZE0_Msk
6841 #define DSI_LPMCR_VLPSIZE1_Pos        (1U)
6842 #define DSI_LPMCR_VLPSIZE1_Msk        (0x1UL << DSI_LPMCR_VLPSIZE1_Pos)         /*!< 0x00000002 */
6843 #define DSI_LPMCR_VLPSIZE1            DSI_LPMCR_VLPSIZE1_Msk
6844 #define DSI_LPMCR_VLPSIZE2_Pos        (2U)
6845 #define DSI_LPMCR_VLPSIZE2_Msk        (0x1UL << DSI_LPMCR_VLPSIZE2_Pos)         /*!< 0x00000004 */
6846 #define DSI_LPMCR_VLPSIZE2            DSI_LPMCR_VLPSIZE2_Msk
6847 #define DSI_LPMCR_VLPSIZE3_Pos        (3U)
6848 #define DSI_LPMCR_VLPSIZE3_Msk        (0x1UL << DSI_LPMCR_VLPSIZE3_Pos)         /*!< 0x00000008 */
6849 #define DSI_LPMCR_VLPSIZE3            DSI_LPMCR_VLPSIZE3_Msk
6850 #define DSI_LPMCR_VLPSIZE4_Pos        (4U)
6851 #define DSI_LPMCR_VLPSIZE4_Msk        (0x1UL << DSI_LPMCR_VLPSIZE4_Pos)         /*!< 0x00000010 */
6852 #define DSI_LPMCR_VLPSIZE4            DSI_LPMCR_VLPSIZE4_Msk
6853 #define DSI_LPMCR_VLPSIZE5_Pos        (5U)
6854 #define DSI_LPMCR_VLPSIZE5_Msk        (0x1UL << DSI_LPMCR_VLPSIZE5_Pos)         /*!< 0x00000020 */
6855 #define DSI_LPMCR_VLPSIZE5            DSI_LPMCR_VLPSIZE5_Msk
6856 #define DSI_LPMCR_VLPSIZE6_Pos        (6U)
6857 #define DSI_LPMCR_VLPSIZE6_Msk        (0x1UL << DSI_LPMCR_VLPSIZE6_Pos)         /*!< 0x00000040 */
6858 #define DSI_LPMCR_VLPSIZE6            DSI_LPMCR_VLPSIZE6_Msk
6859 #define DSI_LPMCR_VLPSIZE7_Pos        (7U)
6860 #define DSI_LPMCR_VLPSIZE7_Msk        (0x1UL << DSI_LPMCR_VLPSIZE7_Pos)         /*!< 0x00000080 */
6861 #define DSI_LPMCR_VLPSIZE7            DSI_LPMCR_VLPSIZE7_Msk
6862 
6863 #define DSI_LPMCR_LPSIZE_Pos          (16U)
6864 #define DSI_LPMCR_LPSIZE_Msk          (0xFFUL << DSI_LPMCR_LPSIZE_Pos)          /*!< 0x00FF0000 */
6865 #define DSI_LPMCR_LPSIZE              DSI_LPMCR_LPSIZE_Msk                     /*!< Largest Packet Size */
6866 #define DSI_LPMCR_LPSIZE0_Pos         (16U)
6867 #define DSI_LPMCR_LPSIZE0_Msk         (0x1UL << DSI_LPMCR_LPSIZE0_Pos)          /*!< 0x00010000 */
6868 #define DSI_LPMCR_LPSIZE0             DSI_LPMCR_LPSIZE0_Msk
6869 #define DSI_LPMCR_LPSIZE1_Pos         (17U)
6870 #define DSI_LPMCR_LPSIZE1_Msk         (0x1UL << DSI_LPMCR_LPSIZE1_Pos)          /*!< 0x00020000 */
6871 #define DSI_LPMCR_LPSIZE1             DSI_LPMCR_LPSIZE1_Msk
6872 #define DSI_LPMCR_LPSIZE2_Pos         (18U)
6873 #define DSI_LPMCR_LPSIZE2_Msk         (0x1UL << DSI_LPMCR_LPSIZE2_Pos)          /*!< 0x00040000 */
6874 #define DSI_LPMCR_LPSIZE2             DSI_LPMCR_LPSIZE2_Msk
6875 #define DSI_LPMCR_LPSIZE3_Pos         (19U)
6876 #define DSI_LPMCR_LPSIZE3_Msk         (0x1UL << DSI_LPMCR_LPSIZE3_Pos)          /*!< 0x00080000 */
6877 #define DSI_LPMCR_LPSIZE3             DSI_LPMCR_LPSIZE3_Msk
6878 #define DSI_LPMCR_LPSIZE4_Pos         (20U)
6879 #define DSI_LPMCR_LPSIZE4_Msk         (0x1UL << DSI_LPMCR_LPSIZE4_Pos)          /*!< 0x00100000 */
6880 #define DSI_LPMCR_LPSIZE4             DSI_LPMCR_LPSIZE4_Msk
6881 #define DSI_LPMCR_LPSIZE5_Pos         (21U)
6882 #define DSI_LPMCR_LPSIZE5_Msk         (0x1UL << DSI_LPMCR_LPSIZE5_Pos)          /*!< 0x00200000 */
6883 #define DSI_LPMCR_LPSIZE5             DSI_LPMCR_LPSIZE5_Msk
6884 #define DSI_LPMCR_LPSIZE6_Pos         (22U)
6885 #define DSI_LPMCR_LPSIZE6_Msk         (0x1UL << DSI_LPMCR_LPSIZE6_Pos)          /*!< 0x00400000 */
6886 #define DSI_LPMCR_LPSIZE6             DSI_LPMCR_LPSIZE6_Msk
6887 #define DSI_LPMCR_LPSIZE7_Pos         (23U)
6888 #define DSI_LPMCR_LPSIZE7_Msk         (0x1UL << DSI_LPMCR_LPSIZE7_Pos)          /*!< 0x00800000 */
6889 #define DSI_LPMCR_LPSIZE7             DSI_LPMCR_LPSIZE7_Msk
6890 
6891 /*******************  Bit definition for DSI_PCR register  ****************/
6892 #define DSI_PCR_ETTXE_Pos             (0U)
6893 #define DSI_PCR_ETTXE_Msk             (0x1UL << DSI_PCR_ETTXE_Pos)              /*!< 0x00000001 */
6894 #define DSI_PCR_ETTXE                 DSI_PCR_ETTXE_Msk                        /*!< EoTp Transmission Enable */
6895 #define DSI_PCR_ETRXE_Pos             (1U)
6896 #define DSI_PCR_ETRXE_Msk             (0x1UL << DSI_PCR_ETRXE_Pos)              /*!< 0x00000002 */
6897 #define DSI_PCR_ETRXE                 DSI_PCR_ETRXE_Msk                        /*!< EoTp Reception Enable */
6898 #define DSI_PCR_BTAE_Pos              (2U)
6899 #define DSI_PCR_BTAE_Msk              (0x1UL << DSI_PCR_BTAE_Pos)               /*!< 0x00000004 */
6900 #define DSI_PCR_BTAE                  DSI_PCR_BTAE_Msk                         /*!< Bus Turn Around Enable */
6901 #define DSI_PCR_ECCRXE_Pos            (3U)
6902 #define DSI_PCR_ECCRXE_Msk            (0x1UL << DSI_PCR_ECCRXE_Pos)             /*!< 0x00000008 */
6903 #define DSI_PCR_ECCRXE                DSI_PCR_ECCRXE_Msk                       /*!< ECC Reception Enable */
6904 #define DSI_PCR_CRCRXE_Pos            (4U)
6905 #define DSI_PCR_CRCRXE_Msk            (0x1UL << DSI_PCR_CRCRXE_Pos)             /*!< 0x00000010 */
6906 #define DSI_PCR_CRCRXE                DSI_PCR_CRCRXE_Msk                       /*!< CRC Reception Enable */
6907 
6908 /*******************  Bit definition for DSI_GVCIDR register  *************/
6909 #define DSI_GVCIDR_VCID_Pos           (0U)
6910 #define DSI_GVCIDR_VCID_Msk           (0x3UL << DSI_GVCIDR_VCID_Pos)            /*!< 0x00000003 */
6911 #define DSI_GVCIDR_VCID               DSI_GVCIDR_VCID_Msk                      /*!< Virtual Channel ID */
6912 #define DSI_GVCIDR_VCID0_Pos          (0U)
6913 #define DSI_GVCIDR_VCID0_Msk          (0x1UL << DSI_GVCIDR_VCID0_Pos)           /*!< 0x00000001 */
6914 #define DSI_GVCIDR_VCID0              DSI_GVCIDR_VCID0_Msk
6915 #define DSI_GVCIDR_VCID1_Pos          (1U)
6916 #define DSI_GVCIDR_VCID1_Msk          (0x1UL << DSI_GVCIDR_VCID1_Pos)           /*!< 0x00000002 */
6917 #define DSI_GVCIDR_VCID1              DSI_GVCIDR_VCID1_Msk
6918 
6919 /*******************  Bit definition for DSI_MCR register  ****************/
6920 #define DSI_MCR_CMDM_Pos              (0U)
6921 #define DSI_MCR_CMDM_Msk              (0x1UL << DSI_MCR_CMDM_Pos)               /*!< 0x00000001 */
6922 #define DSI_MCR_CMDM                  DSI_MCR_CMDM_Msk                         /*!< Command Mode */
6923 
6924 /*******************  Bit definition for DSI_VMCR register  ***************/
6925 #define DSI_VMCR_VMT_Pos              (0U)
6926 #define DSI_VMCR_VMT_Msk              (0x3UL << DSI_VMCR_VMT_Pos)               /*!< 0x00000003 */
6927 #define DSI_VMCR_VMT                  DSI_VMCR_VMT_Msk                         /*!< Video Mode Type */
6928 #define DSI_VMCR_VMT0_Pos             (0U)
6929 #define DSI_VMCR_VMT0_Msk             (0x1UL << DSI_VMCR_VMT0_Pos)              /*!< 0x00000001 */
6930 #define DSI_VMCR_VMT0                 DSI_VMCR_VMT0_Msk
6931 #define DSI_VMCR_VMT1_Pos             (1U)
6932 #define DSI_VMCR_VMT1_Msk             (0x1UL << DSI_VMCR_VMT1_Pos)              /*!< 0x00000002 */
6933 #define DSI_VMCR_VMT1                 DSI_VMCR_VMT1_Msk
6934 
6935 #define DSI_VMCR_LPVSAE_Pos           (8U)
6936 #define DSI_VMCR_LPVSAE_Msk           (0x1UL << DSI_VMCR_LPVSAE_Pos)            /*!< 0x00000100 */
6937 #define DSI_VMCR_LPVSAE               DSI_VMCR_LPVSAE_Msk                      /*!< Low-Power Vertical Sync Active Enable */
6938 #define DSI_VMCR_LPVBPE_Pos           (9U)
6939 #define DSI_VMCR_LPVBPE_Msk           (0x1UL << DSI_VMCR_LPVBPE_Pos)            /*!< 0x00000200 */
6940 #define DSI_VMCR_LPVBPE               DSI_VMCR_LPVBPE_Msk                      /*!< Low-power Vertical Back-Porch Enable */
6941 #define DSI_VMCR_LPVFPE_Pos           (10U)
6942 #define DSI_VMCR_LPVFPE_Msk           (0x1UL << DSI_VMCR_LPVFPE_Pos)            /*!< 0x00000400 */
6943 #define DSI_VMCR_LPVFPE               DSI_VMCR_LPVFPE_Msk                      /*!< Low-power Vertical Front-porch Enable */
6944 #define DSI_VMCR_LPVAE_Pos            (11U)
6945 #define DSI_VMCR_LPVAE_Msk            (0x1UL << DSI_VMCR_LPVAE_Pos)             /*!< 0x00000800 */
6946 #define DSI_VMCR_LPVAE                DSI_VMCR_LPVAE_Msk                       /*!< Low-Power Vertical Active Enable */
6947 #define DSI_VMCR_LPHBPE_Pos           (12U)
6948 #define DSI_VMCR_LPHBPE_Msk           (0x1UL << DSI_VMCR_LPHBPE_Pos)            /*!< 0x00001000 */
6949 #define DSI_VMCR_LPHBPE               DSI_VMCR_LPHBPE_Msk                      /*!< Low-Power Horizontal Back-Porch Enable */
6950 #define DSI_VMCR_LPHFPE_Pos           (13U)
6951 #define DSI_VMCR_LPHFPE_Msk           (0x1UL << DSI_VMCR_LPHFPE_Pos)            /*!< 0x00002000 */
6952 #define DSI_VMCR_LPHFPE               DSI_VMCR_LPHFPE_Msk                      /*!< Low-Power Horizontal Front-Porch Enable */
6953 #define DSI_VMCR_FBTAAE_Pos           (14U)
6954 #define DSI_VMCR_FBTAAE_Msk           (0x1UL << DSI_VMCR_FBTAAE_Pos)            /*!< 0x00004000 */
6955 #define DSI_VMCR_FBTAAE               DSI_VMCR_FBTAAE_Msk                      /*!< Frame Bus-Turn-Around Acknowledge Enable */
6956 #define DSI_VMCR_LPCE_Pos             (15U)
6957 #define DSI_VMCR_LPCE_Msk             (0x1UL << DSI_VMCR_LPCE_Pos)              /*!< 0x00008000 */
6958 #define DSI_VMCR_LPCE                 DSI_VMCR_LPCE_Msk                        /*!< Low-Power Command Enable */
6959 #define DSI_VMCR_PGE_Pos              (16U)
6960 #define DSI_VMCR_PGE_Msk              (0x1UL << DSI_VMCR_PGE_Pos)               /*!< 0x00010000 */
6961 #define DSI_VMCR_PGE                  DSI_VMCR_PGE_Msk                         /*!< Pattern Generator Enable */
6962 #define DSI_VMCR_PGM_Pos              (20U)
6963 #define DSI_VMCR_PGM_Msk              (0x1UL << DSI_VMCR_PGM_Pos)               /*!< 0x00100000 */
6964 #define DSI_VMCR_PGM                  DSI_VMCR_PGM_Msk                         /*!< Pattern Generator Mode */
6965 #define DSI_VMCR_PGO_Pos              (24U)
6966 #define DSI_VMCR_PGO_Msk              (0x1UL << DSI_VMCR_PGO_Pos)               /*!< 0x01000000 */
6967 #define DSI_VMCR_PGO                  DSI_VMCR_PGO_Msk                         /*!< Pattern Generator Orientation */
6968 
6969 /*******************  Bit definition for DSI_VPCR register  ***************/
6970 #define DSI_VPCR_VPSIZE_Pos           (0U)
6971 #define DSI_VPCR_VPSIZE_Msk           (0x3FFFUL << DSI_VPCR_VPSIZE_Pos)         /*!< 0x00003FFF */
6972 #define DSI_VPCR_VPSIZE               DSI_VPCR_VPSIZE_Msk                      /*!< Video Packet Size */
6973 #define DSI_VPCR_VPSIZE0_Pos          (0U)
6974 #define DSI_VPCR_VPSIZE0_Msk          (0x1UL << DSI_VPCR_VPSIZE0_Pos)           /*!< 0x00000001 */
6975 #define DSI_VPCR_VPSIZE0              DSI_VPCR_VPSIZE0_Msk
6976 #define DSI_VPCR_VPSIZE1_Pos          (1U)
6977 #define DSI_VPCR_VPSIZE1_Msk          (0x1UL << DSI_VPCR_VPSIZE1_Pos)           /*!< 0x00000002 */
6978 #define DSI_VPCR_VPSIZE1              DSI_VPCR_VPSIZE1_Msk
6979 #define DSI_VPCR_VPSIZE2_Pos          (2U)
6980 #define DSI_VPCR_VPSIZE2_Msk          (0x1UL << DSI_VPCR_VPSIZE2_Pos)           /*!< 0x00000004 */
6981 #define DSI_VPCR_VPSIZE2              DSI_VPCR_VPSIZE2_Msk
6982 #define DSI_VPCR_VPSIZE3_Pos          (3U)
6983 #define DSI_VPCR_VPSIZE3_Msk          (0x1UL << DSI_VPCR_VPSIZE3_Pos)           /*!< 0x00000008 */
6984 #define DSI_VPCR_VPSIZE3              DSI_VPCR_VPSIZE3_Msk
6985 #define DSI_VPCR_VPSIZE4_Pos          (4U)
6986 #define DSI_VPCR_VPSIZE4_Msk          (0x1UL << DSI_VPCR_VPSIZE4_Pos)           /*!< 0x00000010 */
6987 #define DSI_VPCR_VPSIZE4              DSI_VPCR_VPSIZE4_Msk
6988 #define DSI_VPCR_VPSIZE5_Pos          (5U)
6989 #define DSI_VPCR_VPSIZE5_Msk          (0x1UL << DSI_VPCR_VPSIZE5_Pos)           /*!< 0x00000020 */
6990 #define DSI_VPCR_VPSIZE5              DSI_VPCR_VPSIZE5_Msk
6991 #define DSI_VPCR_VPSIZE6_Pos          (6U)
6992 #define DSI_VPCR_VPSIZE6_Msk          (0x1UL << DSI_VPCR_VPSIZE6_Pos)           /*!< 0x00000040 */
6993 #define DSI_VPCR_VPSIZE6              DSI_VPCR_VPSIZE6_Msk
6994 #define DSI_VPCR_VPSIZE7_Pos          (7U)
6995 #define DSI_VPCR_VPSIZE7_Msk          (0x1UL << DSI_VPCR_VPSIZE7_Pos)           /*!< 0x00000080 */
6996 #define DSI_VPCR_VPSIZE7              DSI_VPCR_VPSIZE7_Msk
6997 #define DSI_VPCR_VPSIZE8_Pos          (8U)
6998 #define DSI_VPCR_VPSIZE8_Msk          (0x1UL << DSI_VPCR_VPSIZE8_Pos)           /*!< 0x00000100 */
6999 #define DSI_VPCR_VPSIZE8              DSI_VPCR_VPSIZE8_Msk
7000 #define DSI_VPCR_VPSIZE9_Pos          (9U)
7001 #define DSI_VPCR_VPSIZE9_Msk          (0x1UL << DSI_VPCR_VPSIZE9_Pos)           /*!< 0x00000200 */
7002 #define DSI_VPCR_VPSIZE9              DSI_VPCR_VPSIZE9_Msk
7003 #define DSI_VPCR_VPSIZE10_Pos         (10U)
7004 #define DSI_VPCR_VPSIZE10_Msk         (0x1UL << DSI_VPCR_VPSIZE10_Pos)          /*!< 0x00000400 */
7005 #define DSI_VPCR_VPSIZE10             DSI_VPCR_VPSIZE10_Msk
7006 #define DSI_VPCR_VPSIZE11_Pos         (11U)
7007 #define DSI_VPCR_VPSIZE11_Msk         (0x1UL << DSI_VPCR_VPSIZE11_Pos)          /*!< 0x00000800 */
7008 #define DSI_VPCR_VPSIZE11             DSI_VPCR_VPSIZE11_Msk
7009 #define DSI_VPCR_VPSIZE12_Pos         (12U)
7010 #define DSI_VPCR_VPSIZE12_Msk         (0x1UL << DSI_VPCR_VPSIZE12_Pos)          /*!< 0x00001000 */
7011 #define DSI_VPCR_VPSIZE12             DSI_VPCR_VPSIZE12_Msk
7012 #define DSI_VPCR_VPSIZE13_Pos         (13U)
7013 #define DSI_VPCR_VPSIZE13_Msk         (0x1UL << DSI_VPCR_VPSIZE13_Pos)          /*!< 0x00002000 */
7014 #define DSI_VPCR_VPSIZE13             DSI_VPCR_VPSIZE13_Msk
7015 
7016 /*******************  Bit definition for DSI_VCCR register  ***************/
7017 #define DSI_VCCR_NUMC_Pos             (0U)
7018 #define DSI_VCCR_NUMC_Msk             (0x1FFFUL << DSI_VCCR_NUMC_Pos)           /*!< 0x00001FFF */
7019 #define DSI_VCCR_NUMC                 DSI_VCCR_NUMC_Msk                        /*!< Number of Chunks */
7020 #define DSI_VCCR_NUMC0_Pos            (0U)
7021 #define DSI_VCCR_NUMC0_Msk            (0x1UL << DSI_VCCR_NUMC0_Pos)             /*!< 0x00000001 */
7022 #define DSI_VCCR_NUMC0                DSI_VCCR_NUMC0_Msk
7023 #define DSI_VCCR_NUMC1_Pos            (1U)
7024 #define DSI_VCCR_NUMC1_Msk            (0x1UL << DSI_VCCR_NUMC1_Pos)             /*!< 0x00000002 */
7025 #define DSI_VCCR_NUMC1                DSI_VCCR_NUMC1_Msk
7026 #define DSI_VCCR_NUMC2_Pos            (2U)
7027 #define DSI_VCCR_NUMC2_Msk            (0x1UL << DSI_VCCR_NUMC2_Pos)             /*!< 0x00000004 */
7028 #define DSI_VCCR_NUMC2                DSI_VCCR_NUMC2_Msk
7029 #define DSI_VCCR_NUMC3_Pos            (3U)
7030 #define DSI_VCCR_NUMC3_Msk            (0x1UL << DSI_VCCR_NUMC3_Pos)             /*!< 0x00000008 */
7031 #define DSI_VCCR_NUMC3                DSI_VCCR_NUMC3_Msk
7032 #define DSI_VCCR_NUMC4_Pos            (4U)
7033 #define DSI_VCCR_NUMC4_Msk            (0x1UL << DSI_VCCR_NUMC4_Pos)             /*!< 0x00000010 */
7034 #define DSI_VCCR_NUMC4                DSI_VCCR_NUMC4_Msk
7035 #define DSI_VCCR_NUMC5_Pos            (5U)
7036 #define DSI_VCCR_NUMC5_Msk            (0x1UL << DSI_VCCR_NUMC5_Pos)             /*!< 0x00000020 */
7037 #define DSI_VCCR_NUMC5                DSI_VCCR_NUMC5_Msk
7038 #define DSI_VCCR_NUMC6_Pos            (6U)
7039 #define DSI_VCCR_NUMC6_Msk            (0x1UL << DSI_VCCR_NUMC6_Pos)             /*!< 0x00000040 */
7040 #define DSI_VCCR_NUMC6                DSI_VCCR_NUMC6_Msk
7041 #define DSI_VCCR_NUMC7_Pos            (7U)
7042 #define DSI_VCCR_NUMC7_Msk            (0x1UL << DSI_VCCR_NUMC7_Pos)             /*!< 0x00000080 */
7043 #define DSI_VCCR_NUMC7                DSI_VCCR_NUMC7_Msk
7044 #define DSI_VCCR_NUMC8_Pos            (8U)
7045 #define DSI_VCCR_NUMC8_Msk            (0x1UL << DSI_VCCR_NUMC8_Pos)             /*!< 0x00000100 */
7046 #define DSI_VCCR_NUMC8                DSI_VCCR_NUMC8_Msk
7047 #define DSI_VCCR_NUMC9_Pos            (9U)
7048 #define DSI_VCCR_NUMC9_Msk            (0x1UL << DSI_VCCR_NUMC9_Pos)             /*!< 0x00000200 */
7049 #define DSI_VCCR_NUMC9                DSI_VCCR_NUMC9_Msk
7050 #define DSI_VCCR_NUMC10_Pos           (10U)
7051 #define DSI_VCCR_NUMC10_Msk           (0x1UL << DSI_VCCR_NUMC10_Pos)            /*!< 0x00000400 */
7052 #define DSI_VCCR_NUMC10               DSI_VCCR_NUMC10_Msk
7053 #define DSI_VCCR_NUMC11_Pos           (11U)
7054 #define DSI_VCCR_NUMC11_Msk           (0x1UL << DSI_VCCR_NUMC11_Pos)            /*!< 0x00000800 */
7055 #define DSI_VCCR_NUMC11               DSI_VCCR_NUMC11_Msk
7056 #define DSI_VCCR_NUMC12_Pos           (12U)
7057 #define DSI_VCCR_NUMC12_Msk           (0x1UL << DSI_VCCR_NUMC12_Pos)            /*!< 0x00001000 */
7058 #define DSI_VCCR_NUMC12               DSI_VCCR_NUMC12_Msk
7059 
7060 /*******************  Bit definition for DSI_VNPCR register  **************/
7061 #define DSI_VNPCR_NPSIZE_Pos          (0U)
7062 #define DSI_VNPCR_NPSIZE_Msk          (0x1FFFUL << DSI_VNPCR_NPSIZE_Pos)        /*!< 0x00001FFF */
7063 #define DSI_VNPCR_NPSIZE              DSI_VNPCR_NPSIZE_Msk                     /*!< Null Packet Size */
7064 #define DSI_VNPCR_NPSIZE0_Pos         (0U)
7065 #define DSI_VNPCR_NPSIZE0_Msk         (0x1UL << DSI_VNPCR_NPSIZE0_Pos)          /*!< 0x00000001 */
7066 #define DSI_VNPCR_NPSIZE0             DSI_VNPCR_NPSIZE0_Msk
7067 #define DSI_VNPCR_NPSIZE1_Pos         (1U)
7068 #define DSI_VNPCR_NPSIZE1_Msk         (0x1UL << DSI_VNPCR_NPSIZE1_Pos)          /*!< 0x00000002 */
7069 #define DSI_VNPCR_NPSIZE1             DSI_VNPCR_NPSIZE1_Msk
7070 #define DSI_VNPCR_NPSIZE2_Pos         (2U)
7071 #define DSI_VNPCR_NPSIZE2_Msk         (0x1UL << DSI_VNPCR_NPSIZE2_Pos)          /*!< 0x00000004 */
7072 #define DSI_VNPCR_NPSIZE2             DSI_VNPCR_NPSIZE2_Msk
7073 #define DSI_VNPCR_NPSIZE3_Pos         (3U)
7074 #define DSI_VNPCR_NPSIZE3_Msk         (0x1UL << DSI_VNPCR_NPSIZE3_Pos)          /*!< 0x00000008 */
7075 #define DSI_VNPCR_NPSIZE3             DSI_VNPCR_NPSIZE3_Msk
7076 #define DSI_VNPCR_NPSIZE4_Pos         (4U)
7077 #define DSI_VNPCR_NPSIZE4_Msk         (0x1UL << DSI_VNPCR_NPSIZE4_Pos)          /*!< 0x00000010 */
7078 #define DSI_VNPCR_NPSIZE4             DSI_VNPCR_NPSIZE4_Msk
7079 #define DSI_VNPCR_NPSIZE5_Pos         (5U)
7080 #define DSI_VNPCR_NPSIZE5_Msk         (0x1UL << DSI_VNPCR_NPSIZE5_Pos)          /*!< 0x00000020 */
7081 #define DSI_VNPCR_NPSIZE5             DSI_VNPCR_NPSIZE5_Msk
7082 #define DSI_VNPCR_NPSIZE6_Pos         (6U)
7083 #define DSI_VNPCR_NPSIZE6_Msk         (0x1UL << DSI_VNPCR_NPSIZE6_Pos)          /*!< 0x00000040 */
7084 #define DSI_VNPCR_NPSIZE6             DSI_VNPCR_NPSIZE6_Msk
7085 #define DSI_VNPCR_NPSIZE7_Pos         (7U)
7086 #define DSI_VNPCR_NPSIZE7_Msk         (0x1UL << DSI_VNPCR_NPSIZE7_Pos)          /*!< 0x00000080 */
7087 #define DSI_VNPCR_NPSIZE7             DSI_VNPCR_NPSIZE7_Msk
7088 #define DSI_VNPCR_NPSIZE8_Pos         (8U)
7089 #define DSI_VNPCR_NPSIZE8_Msk         (0x1UL << DSI_VNPCR_NPSIZE8_Pos)          /*!< 0x00000100 */
7090 #define DSI_VNPCR_NPSIZE8             DSI_VNPCR_NPSIZE8_Msk
7091 #define DSI_VNPCR_NPSIZE9_Pos         (9U)
7092 #define DSI_VNPCR_NPSIZE9_Msk         (0x1UL << DSI_VNPCR_NPSIZE9_Pos)          /*!< 0x00000200 */
7093 #define DSI_VNPCR_NPSIZE9             DSI_VNPCR_NPSIZE9_Msk
7094 #define DSI_VNPCR_NPSIZE10_Pos        (10U)
7095 #define DSI_VNPCR_NPSIZE10_Msk        (0x1UL << DSI_VNPCR_NPSIZE10_Pos)         /*!< 0x00000400 */
7096 #define DSI_VNPCR_NPSIZE10            DSI_VNPCR_NPSIZE10_Msk
7097 #define DSI_VNPCR_NPSIZE11_Pos        (11U)
7098 #define DSI_VNPCR_NPSIZE11_Msk        (0x1UL << DSI_VNPCR_NPSIZE11_Pos)         /*!< 0x00000800 */
7099 #define DSI_VNPCR_NPSIZE11            DSI_VNPCR_NPSIZE11_Msk
7100 #define DSI_VNPCR_NPSIZE12_Pos        (12U)
7101 #define DSI_VNPCR_NPSIZE12_Msk        (0x1UL << DSI_VNPCR_NPSIZE12_Pos)         /*!< 0x00001000 */
7102 #define DSI_VNPCR_NPSIZE12            DSI_VNPCR_NPSIZE12_Msk
7103 
7104 /*******************  Bit definition for DSI_VHSACR register  *************/
7105 #define DSI_VHSACR_HSA_Pos            (0U)
7106 #define DSI_VHSACR_HSA_Msk            (0xFFFUL << DSI_VHSACR_HSA_Pos)           /*!< 0x00000FFF */
7107 #define DSI_VHSACR_HSA                DSI_VHSACR_HSA_Msk                       /*!< Horizontal Synchronism Active duration */
7108 #define DSI_VHSACR_HSA0_Pos           (0U)
7109 #define DSI_VHSACR_HSA0_Msk           (0x1UL << DSI_VHSACR_HSA0_Pos)            /*!< 0x00000001 */
7110 #define DSI_VHSACR_HSA0               DSI_VHSACR_HSA0_Msk
7111 #define DSI_VHSACR_HSA1_Pos           (1U)
7112 #define DSI_VHSACR_HSA1_Msk           (0x1UL << DSI_VHSACR_HSA1_Pos)            /*!< 0x00000002 */
7113 #define DSI_VHSACR_HSA1               DSI_VHSACR_HSA1_Msk
7114 #define DSI_VHSACR_HSA2_Pos           (2U)
7115 #define DSI_VHSACR_HSA2_Msk           (0x1UL << DSI_VHSACR_HSA2_Pos)            /*!< 0x00000004 */
7116 #define DSI_VHSACR_HSA2               DSI_VHSACR_HSA2_Msk
7117 #define DSI_VHSACR_HSA3_Pos           (3U)
7118 #define DSI_VHSACR_HSA3_Msk           (0x1UL << DSI_VHSACR_HSA3_Pos)            /*!< 0x00000008 */
7119 #define DSI_VHSACR_HSA3               DSI_VHSACR_HSA3_Msk
7120 #define DSI_VHSACR_HSA4_Pos           (4U)
7121 #define DSI_VHSACR_HSA4_Msk           (0x1UL << DSI_VHSACR_HSA4_Pos)            /*!< 0x00000010 */
7122 #define DSI_VHSACR_HSA4               DSI_VHSACR_HSA4_Msk
7123 #define DSI_VHSACR_HSA5_Pos           (5U)
7124 #define DSI_VHSACR_HSA5_Msk           (0x1UL << DSI_VHSACR_HSA5_Pos)            /*!< 0x00000020 */
7125 #define DSI_VHSACR_HSA5               DSI_VHSACR_HSA5_Msk
7126 #define DSI_VHSACR_HSA6_Pos           (6U)
7127 #define DSI_VHSACR_HSA6_Msk           (0x1UL << DSI_VHSACR_HSA6_Pos)            /*!< 0x00000040 */
7128 #define DSI_VHSACR_HSA6               DSI_VHSACR_HSA6_Msk
7129 #define DSI_VHSACR_HSA7_Pos           (7U)
7130 #define DSI_VHSACR_HSA7_Msk           (0x1UL << DSI_VHSACR_HSA7_Pos)            /*!< 0x00000080 */
7131 #define DSI_VHSACR_HSA7               DSI_VHSACR_HSA7_Msk
7132 #define DSI_VHSACR_HSA8_Pos           (8U)
7133 #define DSI_VHSACR_HSA8_Msk           (0x1UL << DSI_VHSACR_HSA8_Pos)            /*!< 0x00000100 */
7134 #define DSI_VHSACR_HSA8               DSI_VHSACR_HSA8_Msk
7135 #define DSI_VHSACR_HSA9_Pos           (9U)
7136 #define DSI_VHSACR_HSA9_Msk           (0x1UL << DSI_VHSACR_HSA9_Pos)            /*!< 0x00000200 */
7137 #define DSI_VHSACR_HSA9               DSI_VHSACR_HSA9_Msk
7138 #define DSI_VHSACR_HSA10_Pos          (10U)
7139 #define DSI_VHSACR_HSA10_Msk          (0x1UL << DSI_VHSACR_HSA10_Pos)           /*!< 0x00000400 */
7140 #define DSI_VHSACR_HSA10              DSI_VHSACR_HSA10_Msk
7141 #define DSI_VHSACR_HSA11_Pos          (11U)
7142 #define DSI_VHSACR_HSA11_Msk          (0x1UL << DSI_VHSACR_HSA11_Pos)           /*!< 0x00000800 */
7143 #define DSI_VHSACR_HSA11              DSI_VHSACR_HSA11_Msk
7144 
7145 /*******************  Bit definition for DSI_VHBPCR register  *************/
7146 #define DSI_VHBPCR_HBP_Pos            (0U)
7147 #define DSI_VHBPCR_HBP_Msk            (0xFFFUL << DSI_VHBPCR_HBP_Pos)           /*!< 0x00000FFF */
7148 #define DSI_VHBPCR_HBP                DSI_VHBPCR_HBP_Msk                       /*!< Horizontal Back-Porch duration */
7149 #define DSI_VHBPCR_HBP0_Pos           (0U)
7150 #define DSI_VHBPCR_HBP0_Msk           (0x1UL << DSI_VHBPCR_HBP0_Pos)            /*!< 0x00000001 */
7151 #define DSI_VHBPCR_HBP0               DSI_VHBPCR_HBP0_Msk
7152 #define DSI_VHBPCR_HBP1_Pos           (1U)
7153 #define DSI_VHBPCR_HBP1_Msk           (0x1UL << DSI_VHBPCR_HBP1_Pos)            /*!< 0x00000002 */
7154 #define DSI_VHBPCR_HBP1               DSI_VHBPCR_HBP1_Msk
7155 #define DSI_VHBPCR_HBP2_Pos           (2U)
7156 #define DSI_VHBPCR_HBP2_Msk           (0x1UL << DSI_VHBPCR_HBP2_Pos)            /*!< 0x00000004 */
7157 #define DSI_VHBPCR_HBP2               DSI_VHBPCR_HBP2_Msk
7158 #define DSI_VHBPCR_HBP3_Pos           (3U)
7159 #define DSI_VHBPCR_HBP3_Msk           (0x1UL << DSI_VHBPCR_HBP3_Pos)            /*!< 0x00000008 */
7160 #define DSI_VHBPCR_HBP3               DSI_VHBPCR_HBP3_Msk
7161 #define DSI_VHBPCR_HBP4_Pos           (4U)
7162 #define DSI_VHBPCR_HBP4_Msk           (0x1UL << DSI_VHBPCR_HBP4_Pos)            /*!< 0x00000010 */
7163 #define DSI_VHBPCR_HBP4               DSI_VHBPCR_HBP4_Msk
7164 #define DSI_VHBPCR_HBP5_Pos           (5U)
7165 #define DSI_VHBPCR_HBP5_Msk           (0x1UL << DSI_VHBPCR_HBP5_Pos)            /*!< 0x00000020 */
7166 #define DSI_VHBPCR_HBP5               DSI_VHBPCR_HBP5_Msk
7167 #define DSI_VHBPCR_HBP6_Pos           (6U)
7168 #define DSI_VHBPCR_HBP6_Msk           (0x1UL << DSI_VHBPCR_HBP6_Pos)            /*!< 0x00000040 */
7169 #define DSI_VHBPCR_HBP6               DSI_VHBPCR_HBP6_Msk
7170 #define DSI_VHBPCR_HBP7_Pos           (7U)
7171 #define DSI_VHBPCR_HBP7_Msk           (0x1UL << DSI_VHBPCR_HBP7_Pos)            /*!< 0x00000080 */
7172 #define DSI_VHBPCR_HBP7               DSI_VHBPCR_HBP7_Msk
7173 #define DSI_VHBPCR_HBP8_Pos           (8U)
7174 #define DSI_VHBPCR_HBP8_Msk           (0x1UL << DSI_VHBPCR_HBP8_Pos)            /*!< 0x00000100 */
7175 #define DSI_VHBPCR_HBP8               DSI_VHBPCR_HBP8_Msk
7176 #define DSI_VHBPCR_HBP9_Pos           (9U)
7177 #define DSI_VHBPCR_HBP9_Msk           (0x1UL << DSI_VHBPCR_HBP9_Pos)            /*!< 0x00000200 */
7178 #define DSI_VHBPCR_HBP9               DSI_VHBPCR_HBP9_Msk
7179 #define DSI_VHBPCR_HBP10_Pos          (10U)
7180 #define DSI_VHBPCR_HBP10_Msk          (0x1UL << DSI_VHBPCR_HBP10_Pos)           /*!< 0x00000400 */
7181 #define DSI_VHBPCR_HBP10              DSI_VHBPCR_HBP10_Msk
7182 #define DSI_VHBPCR_HBP11_Pos          (11U)
7183 #define DSI_VHBPCR_HBP11_Msk          (0x1UL << DSI_VHBPCR_HBP11_Pos)           /*!< 0x00000800 */
7184 #define DSI_VHBPCR_HBP11              DSI_VHBPCR_HBP11_Msk
7185 
7186 /*******************  Bit definition for DSI_VLCR register  ***************/
7187 #define DSI_VLCR_HLINE_Pos            (0U)
7188 #define DSI_VLCR_HLINE_Msk            (0x7FFFUL << DSI_VLCR_HLINE_Pos)          /*!< 0x00007FFF */
7189 #define DSI_VLCR_HLINE                DSI_VLCR_HLINE_Msk                       /*!< Horizontal Line duration */
7190 #define DSI_VLCR_HLINE0_Pos           (0U)
7191 #define DSI_VLCR_HLINE0_Msk           (0x1UL << DSI_VLCR_HLINE0_Pos)            /*!< 0x00000001 */
7192 #define DSI_VLCR_HLINE0               DSI_VLCR_HLINE0_Msk
7193 #define DSI_VLCR_HLINE1_Pos           (1U)
7194 #define DSI_VLCR_HLINE1_Msk           (0x1UL << DSI_VLCR_HLINE1_Pos)            /*!< 0x00000002 */
7195 #define DSI_VLCR_HLINE1               DSI_VLCR_HLINE1_Msk
7196 #define DSI_VLCR_HLINE2_Pos           (2U)
7197 #define DSI_VLCR_HLINE2_Msk           (0x1UL << DSI_VLCR_HLINE2_Pos)            /*!< 0x00000004 */
7198 #define DSI_VLCR_HLINE2               DSI_VLCR_HLINE2_Msk
7199 #define DSI_VLCR_HLINE3_Pos           (3U)
7200 #define DSI_VLCR_HLINE3_Msk           (0x1UL << DSI_VLCR_HLINE3_Pos)            /*!< 0x00000008 */
7201 #define DSI_VLCR_HLINE3               DSI_VLCR_HLINE3_Msk
7202 #define DSI_VLCR_HLINE4_Pos           (4U)
7203 #define DSI_VLCR_HLINE4_Msk           (0x1UL << DSI_VLCR_HLINE4_Pos)            /*!< 0x00000010 */
7204 #define DSI_VLCR_HLINE4               DSI_VLCR_HLINE4_Msk
7205 #define DSI_VLCR_HLINE5_Pos           (5U)
7206 #define DSI_VLCR_HLINE5_Msk           (0x1UL << DSI_VLCR_HLINE5_Pos)            /*!< 0x00000020 */
7207 #define DSI_VLCR_HLINE5               DSI_VLCR_HLINE5_Msk
7208 #define DSI_VLCR_HLINE6_Pos           (6U)
7209 #define DSI_VLCR_HLINE6_Msk           (0x1UL << DSI_VLCR_HLINE6_Pos)            /*!< 0x00000040 */
7210 #define DSI_VLCR_HLINE6               DSI_VLCR_HLINE6_Msk
7211 #define DSI_VLCR_HLINE7_Pos           (7U)
7212 #define DSI_VLCR_HLINE7_Msk           (0x1UL << DSI_VLCR_HLINE7_Pos)            /*!< 0x00000080 */
7213 #define DSI_VLCR_HLINE7               DSI_VLCR_HLINE7_Msk
7214 #define DSI_VLCR_HLINE8_Pos           (8U)
7215 #define DSI_VLCR_HLINE8_Msk           (0x1UL << DSI_VLCR_HLINE8_Pos)            /*!< 0x00000100 */
7216 #define DSI_VLCR_HLINE8               DSI_VLCR_HLINE8_Msk
7217 #define DSI_VLCR_HLINE9_Pos           (9U)
7218 #define DSI_VLCR_HLINE9_Msk           (0x1UL << DSI_VLCR_HLINE9_Pos)            /*!< 0x00000200 */
7219 #define DSI_VLCR_HLINE9               DSI_VLCR_HLINE9_Msk
7220 #define DSI_VLCR_HLINE10_Pos          (10U)
7221 #define DSI_VLCR_HLINE10_Msk          (0x1UL << DSI_VLCR_HLINE10_Pos)           /*!< 0x00000400 */
7222 #define DSI_VLCR_HLINE10              DSI_VLCR_HLINE10_Msk
7223 #define DSI_VLCR_HLINE11_Pos          (11U)
7224 #define DSI_VLCR_HLINE11_Msk          (0x1UL << DSI_VLCR_HLINE11_Pos)           /*!< 0x00000800 */
7225 #define DSI_VLCR_HLINE11              DSI_VLCR_HLINE11_Msk
7226 #define DSI_VLCR_HLINE12_Pos          (12U)
7227 #define DSI_VLCR_HLINE12_Msk          (0x1UL << DSI_VLCR_HLINE12_Pos)           /*!< 0x00001000 */
7228 #define DSI_VLCR_HLINE12              DSI_VLCR_HLINE12_Msk
7229 #define DSI_VLCR_HLINE13_Pos          (13U)
7230 #define DSI_VLCR_HLINE13_Msk          (0x1UL << DSI_VLCR_HLINE13_Pos)           /*!< 0x00002000 */
7231 #define DSI_VLCR_HLINE13              DSI_VLCR_HLINE13_Msk
7232 #define DSI_VLCR_HLINE14_Pos          (14U)
7233 #define DSI_VLCR_HLINE14_Msk          (0x1UL << DSI_VLCR_HLINE14_Pos)           /*!< 0x00004000 */
7234 #define DSI_VLCR_HLINE14              DSI_VLCR_HLINE14_Msk
7235 
7236 /*******************  Bit definition for DSI_VVSACR register  *************/
7237 #define DSI_VVSACR_VSA_Pos            (0U)
7238 #define DSI_VVSACR_VSA_Msk            (0x3FFUL << DSI_VVSACR_VSA_Pos)           /*!< 0x000003FF */
7239 #define DSI_VVSACR_VSA                DSI_VVSACR_VSA_Msk                       /*!< Vertical Synchronism Active duration */
7240 #define DSI_VVSACR_VSA0_Pos           (0U)
7241 #define DSI_VVSACR_VSA0_Msk           (0x1UL << DSI_VVSACR_VSA0_Pos)            /*!< 0x00000001 */
7242 #define DSI_VVSACR_VSA0               DSI_VVSACR_VSA0_Msk
7243 #define DSI_VVSACR_VSA1_Pos           (1U)
7244 #define DSI_VVSACR_VSA1_Msk           (0x1UL << DSI_VVSACR_VSA1_Pos)            /*!< 0x00000002 */
7245 #define DSI_VVSACR_VSA1               DSI_VVSACR_VSA1_Msk
7246 #define DSI_VVSACR_VSA2_Pos           (2U)
7247 #define DSI_VVSACR_VSA2_Msk           (0x1UL << DSI_VVSACR_VSA2_Pos)            /*!< 0x00000004 */
7248 #define DSI_VVSACR_VSA2               DSI_VVSACR_VSA2_Msk
7249 #define DSI_VVSACR_VSA3_Pos           (3U)
7250 #define DSI_VVSACR_VSA3_Msk           (0x1UL << DSI_VVSACR_VSA3_Pos)            /*!< 0x00000008 */
7251 #define DSI_VVSACR_VSA3               DSI_VVSACR_VSA3_Msk
7252 #define DSI_VVSACR_VSA4_Pos           (4U)
7253 #define DSI_VVSACR_VSA4_Msk           (0x1UL << DSI_VVSACR_VSA4_Pos)            /*!< 0x00000010 */
7254 #define DSI_VVSACR_VSA4               DSI_VVSACR_VSA4_Msk
7255 #define DSI_VVSACR_VSA5_Pos           (5U)
7256 #define DSI_VVSACR_VSA5_Msk           (0x1UL << DSI_VVSACR_VSA5_Pos)            /*!< 0x00000020 */
7257 #define DSI_VVSACR_VSA5               DSI_VVSACR_VSA5_Msk
7258 #define DSI_VVSACR_VSA6_Pos           (6U)
7259 #define DSI_VVSACR_VSA6_Msk           (0x1UL << DSI_VVSACR_VSA6_Pos)            /*!< 0x00000040 */
7260 #define DSI_VVSACR_VSA6               DSI_VVSACR_VSA6_Msk
7261 #define DSI_VVSACR_VSA7_Pos           (7U)
7262 #define DSI_VVSACR_VSA7_Msk           (0x1UL << DSI_VVSACR_VSA7_Pos)            /*!< 0x00000080 */
7263 #define DSI_VVSACR_VSA7               DSI_VVSACR_VSA7_Msk
7264 #define DSI_VVSACR_VSA8_Pos           (8U)
7265 #define DSI_VVSACR_VSA8_Msk           (0x1UL << DSI_VVSACR_VSA8_Pos)            /*!< 0x00000100 */
7266 #define DSI_VVSACR_VSA8               DSI_VVSACR_VSA8_Msk
7267 #define DSI_VVSACR_VSA9_Pos           (9U)
7268 #define DSI_VVSACR_VSA9_Msk           (0x1UL << DSI_VVSACR_VSA9_Pos)            /*!< 0x00000200 */
7269 #define DSI_VVSACR_VSA9               DSI_VVSACR_VSA9_Msk
7270 
7271 /*******************  Bit definition for DSI_VVBPCR register  *************/
7272 #define DSI_VVBPCR_VBP_Pos            (0U)
7273 #define DSI_VVBPCR_VBP_Msk            (0x3FFUL << DSI_VVBPCR_VBP_Pos)           /*!< 0x000003FF */
7274 #define DSI_VVBPCR_VBP                DSI_VVBPCR_VBP_Msk                       /*!< Vertical Back-Porch duration */
7275 #define DSI_VVBPCR_VBP0_Pos           (0U)
7276 #define DSI_VVBPCR_VBP0_Msk           (0x1UL << DSI_VVBPCR_VBP0_Pos)            /*!< 0x00000001 */
7277 #define DSI_VVBPCR_VBP0               DSI_VVBPCR_VBP0_Msk
7278 #define DSI_VVBPCR_VBP1_Pos           (1U)
7279 #define DSI_VVBPCR_VBP1_Msk           (0x1UL << DSI_VVBPCR_VBP1_Pos)            /*!< 0x00000002 */
7280 #define DSI_VVBPCR_VBP1               DSI_VVBPCR_VBP1_Msk
7281 #define DSI_VVBPCR_VBP2_Pos           (2U)
7282 #define DSI_VVBPCR_VBP2_Msk           (0x1UL << DSI_VVBPCR_VBP2_Pos)            /*!< 0x00000004 */
7283 #define DSI_VVBPCR_VBP2               DSI_VVBPCR_VBP2_Msk
7284 #define DSI_VVBPCR_VBP3_Pos           (3U)
7285 #define DSI_VVBPCR_VBP3_Msk           (0x1UL << DSI_VVBPCR_VBP3_Pos)            /*!< 0x00000008 */
7286 #define DSI_VVBPCR_VBP3               DSI_VVBPCR_VBP3_Msk
7287 #define DSI_VVBPCR_VBP4_Pos           (4U)
7288 #define DSI_VVBPCR_VBP4_Msk           (0x1UL << DSI_VVBPCR_VBP4_Pos)            /*!< 0x00000010 */
7289 #define DSI_VVBPCR_VBP4               DSI_VVBPCR_VBP4_Msk
7290 #define DSI_VVBPCR_VBP5_Pos           (5U)
7291 #define DSI_VVBPCR_VBP5_Msk           (0x1UL << DSI_VVBPCR_VBP5_Pos)            /*!< 0x00000020 */
7292 #define DSI_VVBPCR_VBP5               DSI_VVBPCR_VBP5_Msk
7293 #define DSI_VVBPCR_VBP6_Pos           (6U)
7294 #define DSI_VVBPCR_VBP6_Msk           (0x1UL << DSI_VVBPCR_VBP6_Pos)            /*!< 0x00000040 */
7295 #define DSI_VVBPCR_VBP6               DSI_VVBPCR_VBP6_Msk
7296 #define DSI_VVBPCR_VBP7_Pos           (7U)
7297 #define DSI_VVBPCR_VBP7_Msk           (0x1UL << DSI_VVBPCR_VBP7_Pos)            /*!< 0x00000080 */
7298 #define DSI_VVBPCR_VBP7               DSI_VVBPCR_VBP7_Msk
7299 #define DSI_VVBPCR_VBP8_Pos           (8U)
7300 #define DSI_VVBPCR_VBP8_Msk           (0x1UL << DSI_VVBPCR_VBP8_Pos)            /*!< 0x00000100 */
7301 #define DSI_VVBPCR_VBP8               DSI_VVBPCR_VBP8_Msk
7302 #define DSI_VVBPCR_VBP9_Pos           (9U)
7303 #define DSI_VVBPCR_VBP9_Msk           (0x1UL << DSI_VVBPCR_VBP9_Pos)            /*!< 0x00000200 */
7304 #define DSI_VVBPCR_VBP9               DSI_VVBPCR_VBP9_Msk
7305 
7306 /*******************  Bit definition for DSI_VVFPCR register  *************/
7307 #define DSI_VVFPCR_VFP_Pos            (0U)
7308 #define DSI_VVFPCR_VFP_Msk            (0x3FFUL << DSI_VVFPCR_VFP_Pos)           /*!< 0x000003FF */
7309 #define DSI_VVFPCR_VFP                DSI_VVFPCR_VFP_Msk                       /*!< Vertical Front-Porch duration */
7310 #define DSI_VVFPCR_VFP0_Pos           (0U)
7311 #define DSI_VVFPCR_VFP0_Msk           (0x1UL << DSI_VVFPCR_VFP0_Pos)            /*!< 0x00000001 */
7312 #define DSI_VVFPCR_VFP0               DSI_VVFPCR_VFP0_Msk
7313 #define DSI_VVFPCR_VFP1_Pos           (1U)
7314 #define DSI_VVFPCR_VFP1_Msk           (0x1UL << DSI_VVFPCR_VFP1_Pos)            /*!< 0x00000002 */
7315 #define DSI_VVFPCR_VFP1               DSI_VVFPCR_VFP1_Msk
7316 #define DSI_VVFPCR_VFP2_Pos           (2U)
7317 #define DSI_VVFPCR_VFP2_Msk           (0x1UL << DSI_VVFPCR_VFP2_Pos)            /*!< 0x00000004 */
7318 #define DSI_VVFPCR_VFP2               DSI_VVFPCR_VFP2_Msk
7319 #define DSI_VVFPCR_VFP3_Pos           (3U)
7320 #define DSI_VVFPCR_VFP3_Msk           (0x1UL << DSI_VVFPCR_VFP3_Pos)            /*!< 0x00000008 */
7321 #define DSI_VVFPCR_VFP3               DSI_VVFPCR_VFP3_Msk
7322 #define DSI_VVFPCR_VFP4_Pos           (4U)
7323 #define DSI_VVFPCR_VFP4_Msk           (0x1UL << DSI_VVFPCR_VFP4_Pos)            /*!< 0x00000010 */
7324 #define DSI_VVFPCR_VFP4               DSI_VVFPCR_VFP4_Msk
7325 #define DSI_VVFPCR_VFP5_Pos           (5U)
7326 #define DSI_VVFPCR_VFP5_Msk           (0x1UL << DSI_VVFPCR_VFP5_Pos)            /*!< 0x00000020 */
7327 #define DSI_VVFPCR_VFP5               DSI_VVFPCR_VFP5_Msk
7328 #define DSI_VVFPCR_VFP6_Pos           (6U)
7329 #define DSI_VVFPCR_VFP6_Msk           (0x1UL << DSI_VVFPCR_VFP6_Pos)            /*!< 0x00000040 */
7330 #define DSI_VVFPCR_VFP6               DSI_VVFPCR_VFP6_Msk
7331 #define DSI_VVFPCR_VFP7_Pos           (7U)
7332 #define DSI_VVFPCR_VFP7_Msk           (0x1UL << DSI_VVFPCR_VFP7_Pos)            /*!< 0x00000080 */
7333 #define DSI_VVFPCR_VFP7               DSI_VVFPCR_VFP7_Msk
7334 #define DSI_VVFPCR_VFP8_Pos           (8U)
7335 #define DSI_VVFPCR_VFP8_Msk           (0x1UL << DSI_VVFPCR_VFP8_Pos)            /*!< 0x00000100 */
7336 #define DSI_VVFPCR_VFP8               DSI_VVFPCR_VFP8_Msk
7337 #define DSI_VVFPCR_VFP9_Pos           (9U)
7338 #define DSI_VVFPCR_VFP9_Msk           (0x1UL << DSI_VVFPCR_VFP9_Pos)            /*!< 0x00000200 */
7339 #define DSI_VVFPCR_VFP9               DSI_VVFPCR_VFP9_Msk
7340 
7341 /*******************  Bit definition for DSI_VVACR register  **************/
7342 #define DSI_VVACR_VA_Pos              (0U)
7343 #define DSI_VVACR_VA_Msk              (0x3FFFUL << DSI_VVACR_VA_Pos)            /*!< 0x00003FFF */
7344 #define DSI_VVACR_VA                  DSI_VVACR_VA_Msk                         /*!< Vertical Active duration */
7345 #define DSI_VVACR_VA0_Pos             (0U)
7346 #define DSI_VVACR_VA0_Msk             (0x1UL << DSI_VVACR_VA0_Pos)              /*!< 0x00000001 */
7347 #define DSI_VVACR_VA0                 DSI_VVACR_VA0_Msk
7348 #define DSI_VVACR_VA1_Pos             (1U)
7349 #define DSI_VVACR_VA1_Msk             (0x1UL << DSI_VVACR_VA1_Pos)              /*!< 0x00000002 */
7350 #define DSI_VVACR_VA1                 DSI_VVACR_VA1_Msk
7351 #define DSI_VVACR_VA2_Pos             (2U)
7352 #define DSI_VVACR_VA2_Msk             (0x1UL << DSI_VVACR_VA2_Pos)              /*!< 0x00000004 */
7353 #define DSI_VVACR_VA2                 DSI_VVACR_VA2_Msk
7354 #define DSI_VVACR_VA3_Pos             (3U)
7355 #define DSI_VVACR_VA3_Msk             (0x1UL << DSI_VVACR_VA3_Pos)              /*!< 0x00000008 */
7356 #define DSI_VVACR_VA3                 DSI_VVACR_VA3_Msk
7357 #define DSI_VVACR_VA4_Pos             (4U)
7358 #define DSI_VVACR_VA4_Msk             (0x1UL << DSI_VVACR_VA4_Pos)              /*!< 0x00000010 */
7359 #define DSI_VVACR_VA4                 DSI_VVACR_VA4_Msk
7360 #define DSI_VVACR_VA5_Pos             (5U)
7361 #define DSI_VVACR_VA5_Msk             (0x1UL << DSI_VVACR_VA5_Pos)              /*!< 0x00000020 */
7362 #define DSI_VVACR_VA5                 DSI_VVACR_VA5_Msk
7363 #define DSI_VVACR_VA6_Pos             (6U)
7364 #define DSI_VVACR_VA6_Msk             (0x1UL << DSI_VVACR_VA6_Pos)              /*!< 0x00000040 */
7365 #define DSI_VVACR_VA6                 DSI_VVACR_VA6_Msk
7366 #define DSI_VVACR_VA7_Pos             (7U)
7367 #define DSI_VVACR_VA7_Msk             (0x1UL << DSI_VVACR_VA7_Pos)              /*!< 0x00000080 */
7368 #define DSI_VVACR_VA7                 DSI_VVACR_VA7_Msk
7369 #define DSI_VVACR_VA8_Pos             (8U)
7370 #define DSI_VVACR_VA8_Msk             (0x1UL << DSI_VVACR_VA8_Pos)              /*!< 0x00000100 */
7371 #define DSI_VVACR_VA8                 DSI_VVACR_VA8_Msk
7372 #define DSI_VVACR_VA9_Pos             (9U)
7373 #define DSI_VVACR_VA9_Msk             (0x1UL << DSI_VVACR_VA9_Pos)              /*!< 0x00000200 */
7374 #define DSI_VVACR_VA9                 DSI_VVACR_VA9_Msk
7375 #define DSI_VVACR_VA10_Pos            (10U)
7376 #define DSI_VVACR_VA10_Msk            (0x1UL << DSI_VVACR_VA10_Pos)             /*!< 0x00000400 */
7377 #define DSI_VVACR_VA10                DSI_VVACR_VA10_Msk
7378 #define DSI_VVACR_VA11_Pos            (11U)
7379 #define DSI_VVACR_VA11_Msk            (0x1UL << DSI_VVACR_VA11_Pos)             /*!< 0x00000800 */
7380 #define DSI_VVACR_VA11                DSI_VVACR_VA11_Msk
7381 #define DSI_VVACR_VA12_Pos            (12U)
7382 #define DSI_VVACR_VA12_Msk            (0x1UL << DSI_VVACR_VA12_Pos)             /*!< 0x00001000 */
7383 #define DSI_VVACR_VA12                DSI_VVACR_VA12_Msk
7384 #define DSI_VVACR_VA13_Pos            (13U)
7385 #define DSI_VVACR_VA13_Msk            (0x1UL << DSI_VVACR_VA13_Pos)             /*!< 0x00002000 */
7386 #define DSI_VVACR_VA13                DSI_VVACR_VA13_Msk
7387 
7388 /*******************  Bit definition for DSI_LCCR register  ***************/
7389 #define DSI_LCCR_CMDSIZE_Pos          (0U)
7390 #define DSI_LCCR_CMDSIZE_Msk          (0xFFFFUL << DSI_LCCR_CMDSIZE_Pos)        /*!< 0x0000FFFF */
7391 #define DSI_LCCR_CMDSIZE              DSI_LCCR_CMDSIZE_Msk                     /*!< Command Size */
7392 #define DSI_LCCR_CMDSIZE0_Pos         (0U)
7393 #define DSI_LCCR_CMDSIZE0_Msk         (0x1UL << DSI_LCCR_CMDSIZE0_Pos)          /*!< 0x00000001 */
7394 #define DSI_LCCR_CMDSIZE0             DSI_LCCR_CMDSIZE0_Msk
7395 #define DSI_LCCR_CMDSIZE1_Pos         (1U)
7396 #define DSI_LCCR_CMDSIZE1_Msk         (0x1UL << DSI_LCCR_CMDSIZE1_Pos)          /*!< 0x00000002 */
7397 #define DSI_LCCR_CMDSIZE1             DSI_LCCR_CMDSIZE1_Msk
7398 #define DSI_LCCR_CMDSIZE2_Pos         (2U)
7399 #define DSI_LCCR_CMDSIZE2_Msk         (0x1UL << DSI_LCCR_CMDSIZE2_Pos)          /*!< 0x00000004 */
7400 #define DSI_LCCR_CMDSIZE2             DSI_LCCR_CMDSIZE2_Msk
7401 #define DSI_LCCR_CMDSIZE3_Pos         (3U)
7402 #define DSI_LCCR_CMDSIZE3_Msk         (0x1UL << DSI_LCCR_CMDSIZE3_Pos)          /*!< 0x00000008 */
7403 #define DSI_LCCR_CMDSIZE3             DSI_LCCR_CMDSIZE3_Msk
7404 #define DSI_LCCR_CMDSIZE4_Pos         (4U)
7405 #define DSI_LCCR_CMDSIZE4_Msk         (0x1UL << DSI_LCCR_CMDSIZE4_Pos)          /*!< 0x00000010 */
7406 #define DSI_LCCR_CMDSIZE4             DSI_LCCR_CMDSIZE4_Msk
7407 #define DSI_LCCR_CMDSIZE5_Pos         (5U)
7408 #define DSI_LCCR_CMDSIZE5_Msk         (0x1UL << DSI_LCCR_CMDSIZE5_Pos)          /*!< 0x00000020 */
7409 #define DSI_LCCR_CMDSIZE5             DSI_LCCR_CMDSIZE5_Msk
7410 #define DSI_LCCR_CMDSIZE6_Pos         (6U)
7411 #define DSI_LCCR_CMDSIZE6_Msk         (0x1UL << DSI_LCCR_CMDSIZE6_Pos)          /*!< 0x00000040 */
7412 #define DSI_LCCR_CMDSIZE6             DSI_LCCR_CMDSIZE6_Msk
7413 #define DSI_LCCR_CMDSIZE7_Pos         (7U)
7414 #define DSI_LCCR_CMDSIZE7_Msk         (0x1UL << DSI_LCCR_CMDSIZE7_Pos)          /*!< 0x00000080 */
7415 #define DSI_LCCR_CMDSIZE7             DSI_LCCR_CMDSIZE7_Msk
7416 #define DSI_LCCR_CMDSIZE8_Pos         (8U)
7417 #define DSI_LCCR_CMDSIZE8_Msk         (0x1UL << DSI_LCCR_CMDSIZE8_Pos)          /*!< 0x00000100 */
7418 #define DSI_LCCR_CMDSIZE8             DSI_LCCR_CMDSIZE8_Msk
7419 #define DSI_LCCR_CMDSIZE9_Pos         (9U)
7420 #define DSI_LCCR_CMDSIZE9_Msk         (0x1UL << DSI_LCCR_CMDSIZE9_Pos)          /*!< 0x00000200 */
7421 #define DSI_LCCR_CMDSIZE9             DSI_LCCR_CMDSIZE9_Msk
7422 #define DSI_LCCR_CMDSIZE10_Pos        (10U)
7423 #define DSI_LCCR_CMDSIZE10_Msk        (0x1UL << DSI_LCCR_CMDSIZE10_Pos)         /*!< 0x00000400 */
7424 #define DSI_LCCR_CMDSIZE10            DSI_LCCR_CMDSIZE10_Msk
7425 #define DSI_LCCR_CMDSIZE11_Pos        (11U)
7426 #define DSI_LCCR_CMDSIZE11_Msk        (0x1UL << DSI_LCCR_CMDSIZE11_Pos)         /*!< 0x00000800 */
7427 #define DSI_LCCR_CMDSIZE11            DSI_LCCR_CMDSIZE11_Msk
7428 #define DSI_LCCR_CMDSIZE12_Pos        (12U)
7429 #define DSI_LCCR_CMDSIZE12_Msk        (0x1UL << DSI_LCCR_CMDSIZE12_Pos)         /*!< 0x00001000 */
7430 #define DSI_LCCR_CMDSIZE12            DSI_LCCR_CMDSIZE12_Msk
7431 #define DSI_LCCR_CMDSIZE13_Pos        (13U)
7432 #define DSI_LCCR_CMDSIZE13_Msk        (0x1UL << DSI_LCCR_CMDSIZE13_Pos)         /*!< 0x00002000 */
7433 #define DSI_LCCR_CMDSIZE13            DSI_LCCR_CMDSIZE13_Msk
7434 #define DSI_LCCR_CMDSIZE14_Pos        (14U)
7435 #define DSI_LCCR_CMDSIZE14_Msk        (0x1UL << DSI_LCCR_CMDSIZE14_Pos)         /*!< 0x00004000 */
7436 #define DSI_LCCR_CMDSIZE14            DSI_LCCR_CMDSIZE14_Msk
7437 #define DSI_LCCR_CMDSIZE15_Pos        (15U)
7438 #define DSI_LCCR_CMDSIZE15_Msk        (0x1UL << DSI_LCCR_CMDSIZE15_Pos)         /*!< 0x00008000 */
7439 #define DSI_LCCR_CMDSIZE15            DSI_LCCR_CMDSIZE15_Msk
7440 
7441 /*******************  Bit definition for DSI_CMCR register  ***************/
7442 #define DSI_CMCR_TEARE_Pos            (0U)
7443 #define DSI_CMCR_TEARE_Msk            (0x1UL << DSI_CMCR_TEARE_Pos)             /*!< 0x00000001 */
7444 #define DSI_CMCR_TEARE                DSI_CMCR_TEARE_Msk                       /*!< Tearing Effect Acknowledge Request Enable */
7445 #define DSI_CMCR_ARE_Pos              (1U)
7446 #define DSI_CMCR_ARE_Msk              (0x1UL << DSI_CMCR_ARE_Pos)               /*!< 0x00000002 */
7447 #define DSI_CMCR_ARE                  DSI_CMCR_ARE_Msk                         /*!< Acknowledge Request Enable */
7448 #define DSI_CMCR_GSW0TX_Pos           (8U)
7449 #define DSI_CMCR_GSW0TX_Msk           (0x1UL << DSI_CMCR_GSW0TX_Pos)            /*!< 0x00000100 */
7450 #define DSI_CMCR_GSW0TX               DSI_CMCR_GSW0TX_Msk                      /*!< Generic Short Write Zero parameters Transmission */
7451 #define DSI_CMCR_GSW1TX_Pos           (9U)
7452 #define DSI_CMCR_GSW1TX_Msk           (0x1UL << DSI_CMCR_GSW1TX_Pos)            /*!< 0x00000200 */
7453 #define DSI_CMCR_GSW1TX               DSI_CMCR_GSW1TX_Msk                      /*!< Generic Short Write One parameters Transmission */
7454 #define DSI_CMCR_GSW2TX_Pos           (10U)
7455 #define DSI_CMCR_GSW2TX_Msk           (0x1UL << DSI_CMCR_GSW2TX_Pos)            /*!< 0x00000400 */
7456 #define DSI_CMCR_GSW2TX               DSI_CMCR_GSW2TX_Msk                      /*!< Generic Short Write Two parameters Transmission */
7457 #define DSI_CMCR_GSR0TX_Pos           (11U)
7458 #define DSI_CMCR_GSR0TX_Msk           (0x1UL << DSI_CMCR_GSR0TX_Pos)            /*!< 0x00000800 */
7459 #define DSI_CMCR_GSR0TX               DSI_CMCR_GSR0TX_Msk                      /*!< Generic Short Read Zero parameters Transmission */
7460 #define DSI_CMCR_GSR1TX_Pos           (12U)
7461 #define DSI_CMCR_GSR1TX_Msk           (0x1UL << DSI_CMCR_GSR1TX_Pos)            /*!< 0x00001000 */
7462 #define DSI_CMCR_GSR1TX               DSI_CMCR_GSR1TX_Msk                      /*!< Generic Short Read One parameters Transmission */
7463 #define DSI_CMCR_GSR2TX_Pos           (13U)
7464 #define DSI_CMCR_GSR2TX_Msk           (0x1UL << DSI_CMCR_GSR2TX_Pos)            /*!< 0x00002000 */
7465 #define DSI_CMCR_GSR2TX               DSI_CMCR_GSR2TX_Msk                      /*!< Generic Short Read Two parameters Transmission */
7466 #define DSI_CMCR_GLWTX_Pos            (14U)
7467 #define DSI_CMCR_GLWTX_Msk            (0x1UL << DSI_CMCR_GLWTX_Pos)             /*!< 0x00004000 */
7468 #define DSI_CMCR_GLWTX                DSI_CMCR_GLWTX_Msk                       /*!< Generic Long Write Transmission */
7469 #define DSI_CMCR_DSW0TX_Pos           (16U)
7470 #define DSI_CMCR_DSW0TX_Msk           (0x1UL << DSI_CMCR_DSW0TX_Pos)            /*!< 0x00010000 */
7471 #define DSI_CMCR_DSW0TX               DSI_CMCR_DSW0TX_Msk                      /*!< DCS Short Write Zero parameter Transmission */
7472 #define DSI_CMCR_DSW1TX_Pos           (17U)
7473 #define DSI_CMCR_DSW1TX_Msk           (0x1UL << DSI_CMCR_DSW1TX_Pos)            /*!< 0x00020000 */
7474 #define DSI_CMCR_DSW1TX               DSI_CMCR_DSW1TX_Msk                      /*!< DCS Short Read One parameter Transmission */
7475 #define DSI_CMCR_DSR0TX_Pos           (18U)
7476 #define DSI_CMCR_DSR0TX_Msk           (0x1UL << DSI_CMCR_DSR0TX_Pos)            /*!< 0x00040000 */
7477 #define DSI_CMCR_DSR0TX               DSI_CMCR_DSR0TX_Msk                      /*!< DCS Short Read Zero parameter Transmission */
7478 #define DSI_CMCR_DLWTX_Pos            (19U)
7479 #define DSI_CMCR_DLWTX_Msk            (0x1UL << DSI_CMCR_DLWTX_Pos)             /*!< 0x00080000 */
7480 #define DSI_CMCR_DLWTX                DSI_CMCR_DLWTX_Msk                       /*!< DCS Long Write Transmission */
7481 #define DSI_CMCR_MRDPS_Pos            (24U)
7482 #define DSI_CMCR_MRDPS_Msk            (0x1UL << DSI_CMCR_MRDPS_Pos)             /*!< 0x01000000 */
7483 #define DSI_CMCR_MRDPS                DSI_CMCR_MRDPS_Msk                       /*!< Maximum Read Packet Size */
7484 
7485 /*******************  Bit definition for DSI_GHCR register  ***************/
7486 #define DSI_GHCR_DT_Pos               (0U)
7487 #define DSI_GHCR_DT_Msk               (0x3FUL << DSI_GHCR_DT_Pos)               /*!< 0x0000003F */
7488 #define DSI_GHCR_DT                   DSI_GHCR_DT_Msk                          /*!< Type */
7489 #define DSI_GHCR_DT0_Pos              (0U)
7490 #define DSI_GHCR_DT0_Msk              (0x1UL << DSI_GHCR_DT0_Pos)               /*!< 0x00000001 */
7491 #define DSI_GHCR_DT0                  DSI_GHCR_DT0_Msk
7492 #define DSI_GHCR_DT1_Pos              (1U)
7493 #define DSI_GHCR_DT1_Msk              (0x1UL << DSI_GHCR_DT1_Pos)               /*!< 0x00000002 */
7494 #define DSI_GHCR_DT1                  DSI_GHCR_DT1_Msk
7495 #define DSI_GHCR_DT2_Pos              (2U)
7496 #define DSI_GHCR_DT2_Msk              (0x1UL << DSI_GHCR_DT2_Pos)               /*!< 0x00000004 */
7497 #define DSI_GHCR_DT2                  DSI_GHCR_DT2_Msk
7498 #define DSI_GHCR_DT3_Pos              (3U)
7499 #define DSI_GHCR_DT3_Msk              (0x1UL << DSI_GHCR_DT3_Pos)               /*!< 0x00000008 */
7500 #define DSI_GHCR_DT3                  DSI_GHCR_DT3_Msk
7501 #define DSI_GHCR_DT4_Pos              (4U)
7502 #define DSI_GHCR_DT4_Msk              (0x1UL << DSI_GHCR_DT4_Pos)               /*!< 0x00000010 */
7503 #define DSI_GHCR_DT4                  DSI_GHCR_DT4_Msk
7504 #define DSI_GHCR_DT5_Pos              (5U)
7505 #define DSI_GHCR_DT5_Msk              (0x1UL << DSI_GHCR_DT5_Pos)               /*!< 0x00000020 */
7506 #define DSI_GHCR_DT5                  DSI_GHCR_DT5_Msk
7507 
7508 #define DSI_GHCR_VCID_Pos             (6U)
7509 #define DSI_GHCR_VCID_Msk             (0x3UL << DSI_GHCR_VCID_Pos)              /*!< 0x000000C0 */
7510 #define DSI_GHCR_VCID                 DSI_GHCR_VCID_Msk                        /*!< Channel */
7511 #define DSI_GHCR_VCID0_Pos            (6U)
7512 #define DSI_GHCR_VCID0_Msk            (0x1UL << DSI_GHCR_VCID0_Pos)             /*!< 0x00000040 */
7513 #define DSI_GHCR_VCID0                DSI_GHCR_VCID0_Msk
7514 #define DSI_GHCR_VCID1_Pos            (7U)
7515 #define DSI_GHCR_VCID1_Msk            (0x1UL << DSI_GHCR_VCID1_Pos)             /*!< 0x00000080 */
7516 #define DSI_GHCR_VCID1                DSI_GHCR_VCID1_Msk
7517 
7518 #define DSI_GHCR_WCLSB_Pos            (8U)
7519 #define DSI_GHCR_WCLSB_Msk            (0xFFUL << DSI_GHCR_WCLSB_Pos)            /*!< 0x0000FF00 */
7520 #define DSI_GHCR_WCLSB                DSI_GHCR_WCLSB_Msk                       /*!< WordCount LSB */
7521 #define DSI_GHCR_WCLSB0_Pos           (8U)
7522 #define DSI_GHCR_WCLSB0_Msk           (0x1UL << DSI_GHCR_WCLSB0_Pos)            /*!< 0x00000100 */
7523 #define DSI_GHCR_WCLSB0               DSI_GHCR_WCLSB0_Msk
7524 #define DSI_GHCR_WCLSB1_Pos           (9U)
7525 #define DSI_GHCR_WCLSB1_Msk           (0x1UL << DSI_GHCR_WCLSB1_Pos)            /*!< 0x00000200 */
7526 #define DSI_GHCR_WCLSB1               DSI_GHCR_WCLSB1_Msk
7527 #define DSI_GHCR_WCLSB2_Pos           (10U)
7528 #define DSI_GHCR_WCLSB2_Msk           (0x1UL << DSI_GHCR_WCLSB2_Pos)            /*!< 0x00000400 */
7529 #define DSI_GHCR_WCLSB2               DSI_GHCR_WCLSB2_Msk
7530 #define DSI_GHCR_WCLSB3_Pos           (11U)
7531 #define DSI_GHCR_WCLSB3_Msk           (0x1UL << DSI_GHCR_WCLSB3_Pos)            /*!< 0x00000800 */
7532 #define DSI_GHCR_WCLSB3               DSI_GHCR_WCLSB3_Msk
7533 #define DSI_GHCR_WCLSB4_Pos           (12U)
7534 #define DSI_GHCR_WCLSB4_Msk           (0x1UL << DSI_GHCR_WCLSB4_Pos)            /*!< 0x00001000 */
7535 #define DSI_GHCR_WCLSB4               DSI_GHCR_WCLSB4_Msk
7536 #define DSI_GHCR_WCLSB5_Pos           (13U)
7537 #define DSI_GHCR_WCLSB5_Msk           (0x1UL << DSI_GHCR_WCLSB5_Pos)            /*!< 0x00002000 */
7538 #define DSI_GHCR_WCLSB5               DSI_GHCR_WCLSB5_Msk
7539 #define DSI_GHCR_WCLSB6_Pos           (14U)
7540 #define DSI_GHCR_WCLSB6_Msk           (0x1UL << DSI_GHCR_WCLSB6_Pos)            /*!< 0x00004000 */
7541 #define DSI_GHCR_WCLSB6               DSI_GHCR_WCLSB6_Msk
7542 #define DSI_GHCR_WCLSB7_Pos           (15U)
7543 #define DSI_GHCR_WCLSB7_Msk           (0x1UL << DSI_GHCR_WCLSB7_Pos)            /*!< 0x00008000 */
7544 #define DSI_GHCR_WCLSB7               DSI_GHCR_WCLSB7_Msk
7545 
7546 #define DSI_GHCR_WCMSB_Pos            (16U)
7547 #define DSI_GHCR_WCMSB_Msk            (0xFFUL << DSI_GHCR_WCMSB_Pos)            /*!< 0x00FF0000 */
7548 #define DSI_GHCR_WCMSB                DSI_GHCR_WCMSB_Msk                       /*!< WordCount MSB */
7549 #define DSI_GHCR_WCMSB0_Pos           (16U)
7550 #define DSI_GHCR_WCMSB0_Msk           (0x1UL << DSI_GHCR_WCMSB0_Pos)            /*!< 0x00010000 */
7551 #define DSI_GHCR_WCMSB0               DSI_GHCR_WCMSB0_Msk
7552 #define DSI_GHCR_WCMSB1_Pos           (17U)
7553 #define DSI_GHCR_WCMSB1_Msk           (0x1UL << DSI_GHCR_WCMSB1_Pos)            /*!< 0x00020000 */
7554 #define DSI_GHCR_WCMSB1               DSI_GHCR_WCMSB1_Msk
7555 #define DSI_GHCR_WCMSB2_Pos           (18U)
7556 #define DSI_GHCR_WCMSB2_Msk           (0x1UL << DSI_GHCR_WCMSB2_Pos)            /*!< 0x00040000 */
7557 #define DSI_GHCR_WCMSB2               DSI_GHCR_WCMSB2_Msk
7558 #define DSI_GHCR_WCMSB3_Pos           (19U)
7559 #define DSI_GHCR_WCMSB3_Msk           (0x1UL << DSI_GHCR_WCMSB3_Pos)            /*!< 0x00080000 */
7560 #define DSI_GHCR_WCMSB3               DSI_GHCR_WCMSB3_Msk
7561 #define DSI_GHCR_WCMSB4_Pos           (20U)
7562 #define DSI_GHCR_WCMSB4_Msk           (0x1UL << DSI_GHCR_WCMSB4_Pos)            /*!< 0x00100000 */
7563 #define DSI_GHCR_WCMSB4               DSI_GHCR_WCMSB4_Msk
7564 #define DSI_GHCR_WCMSB5_Pos           (21U)
7565 #define DSI_GHCR_WCMSB5_Msk           (0x1UL << DSI_GHCR_WCMSB5_Pos)            /*!< 0x00200000 */
7566 #define DSI_GHCR_WCMSB5               DSI_GHCR_WCMSB5_Msk
7567 #define DSI_GHCR_WCMSB6_Pos           (22U)
7568 #define DSI_GHCR_WCMSB6_Msk           (0x1UL << DSI_GHCR_WCMSB6_Pos)            /*!< 0x00400000 */
7569 #define DSI_GHCR_WCMSB6               DSI_GHCR_WCMSB6_Msk
7570 #define DSI_GHCR_WCMSB7_Pos           (23U)
7571 #define DSI_GHCR_WCMSB7_Msk           (0x1UL << DSI_GHCR_WCMSB7_Pos)            /*!< 0x00800000 */
7572 #define DSI_GHCR_WCMSB7               DSI_GHCR_WCMSB7_Msk
7573 
7574 /*******************  Bit definition for DSI_GPDR register  ***************/
7575 #define DSI_GPDR_DATA1_Pos            (0U)
7576 #define DSI_GPDR_DATA1_Msk            (0xFFUL << DSI_GPDR_DATA1_Pos)            /*!< 0x000000FF */
7577 #define DSI_GPDR_DATA1                DSI_GPDR_DATA1_Msk                       /*!< Payload Byte 1 */
7578 #define DSI_GPDR_DATA1_0              (0x01UL << DSI_GPDR_DATA1_Pos)            /*!< 0x00000001 */
7579 #define DSI_GPDR_DATA1_1              (0x02UL << DSI_GPDR_DATA1_Pos)            /*!< 0x00000002 */
7580 #define DSI_GPDR_DATA1_2              (0x04UL << DSI_GPDR_DATA1_Pos)            /*!< 0x00000004 */
7581 #define DSI_GPDR_DATA1_3              (0x08UL << DSI_GPDR_DATA1_Pos)            /*!< 0x00000008 */
7582 #define DSI_GPDR_DATA1_4              (0x10UL << DSI_GPDR_DATA1_Pos)            /*!< 0x00000010 */
7583 #define DSI_GPDR_DATA1_5              (0x20UL << DSI_GPDR_DATA1_Pos)            /*!< 0x00000020 */
7584 #define DSI_GPDR_DATA1_6              (0x40UL << DSI_GPDR_DATA1_Pos)            /*!< 0x00000040 */
7585 #define DSI_GPDR_DATA1_7              (0x80UL << DSI_GPDR_DATA1_Pos)            /*!< 0x00000080 */
7586 
7587 #define DSI_GPDR_DATA2_Pos            (8U)
7588 #define DSI_GPDR_DATA2_Msk            (0xFFUL << DSI_GPDR_DATA2_Pos)            /*!< 0x0000FF00 */
7589 #define DSI_GPDR_DATA2                DSI_GPDR_DATA2_Msk                       /*!< Payload Byte 2 */
7590 #define DSI_GPDR_DATA2_0              (0x01UL << DSI_GPDR_DATA2_Pos)            /*!< 0x00000100 */
7591 #define DSI_GPDR_DATA2_1              (0x02UL << DSI_GPDR_DATA2_Pos)            /*!< 0x00000200 */
7592 #define DSI_GPDR_DATA2_2              (0x04UL << DSI_GPDR_DATA2_Pos)            /*!< 0x00000400 */
7593 #define DSI_GPDR_DATA2_3              (0x08UL << DSI_GPDR_DATA2_Pos)            /*!< 0x00000800 */
7594 #define DSI_GPDR_DATA2_4              (0x10UL << DSI_GPDR_DATA2_Pos)            /*!< 0x00001000 */
7595 #define DSI_GPDR_DATA2_5              (0x20UL << DSI_GPDR_DATA2_Pos)            /*!< 0x00002000 */
7596 #define DSI_GPDR_DATA2_6              (0x40UL << DSI_GPDR_DATA2_Pos)            /*!< 0x00004000 */
7597 #define DSI_GPDR_DATA2_7              (0x80UL << DSI_GPDR_DATA2_Pos)            /*!< 0x00008000 */
7598 
7599 #define DSI_GPDR_DATA3_Pos            (16U)
7600 #define DSI_GPDR_DATA3_Msk            (0xFFUL << DSI_GPDR_DATA3_Pos)            /*!< 0x00FF0000 */
7601 #define DSI_GPDR_DATA3                DSI_GPDR_DATA3_Msk                       /*!< Payload Byte 3 */
7602 #define DSI_GPDR_DATA3_0              (0x01UL << DSI_GPDR_DATA3_Pos)            /*!< 0x00010000 */
7603 #define DSI_GPDR_DATA3_1              (0x02UL << DSI_GPDR_DATA3_Pos)            /*!< 0x00020000 */
7604 #define DSI_GPDR_DATA3_2              (0x04UL << DSI_GPDR_DATA3_Pos)            /*!< 0x00040000 */
7605 #define DSI_GPDR_DATA3_3              (0x08UL << DSI_GPDR_DATA3_Pos)            /*!< 0x00080000 */
7606 #define DSI_GPDR_DATA3_4              (0x10UL << DSI_GPDR_DATA3_Pos)            /*!< 0x00100000 */
7607 #define DSI_GPDR_DATA3_5              (0x20UL << DSI_GPDR_DATA3_Pos)            /*!< 0x00200000 */
7608 #define DSI_GPDR_DATA3_6              (0x40UL << DSI_GPDR_DATA3_Pos)            /*!< 0x00400000 */
7609 #define DSI_GPDR_DATA3_7              (0x80UL << DSI_GPDR_DATA3_Pos)            /*!< 0x00800000 */
7610 
7611 #define DSI_GPDR_DATA4_Pos            (24U)
7612 #define DSI_GPDR_DATA4_Msk            (0xFFUL << DSI_GPDR_DATA4_Pos)            /*!< 0xFF000000 */
7613 #define DSI_GPDR_DATA4                DSI_GPDR_DATA4_Msk                       /*!< Payload Byte 4 */
7614 #define DSI_GPDR_DATA4_0              (0x01UL << DSI_GPDR_DATA4_Pos)            /*!< 0x01000000 */
7615 #define DSI_GPDR_DATA4_1              (0x02UL << DSI_GPDR_DATA4_Pos)            /*!< 0x02000000 */
7616 #define DSI_GPDR_DATA4_2              (0x04UL << DSI_GPDR_DATA4_Pos)            /*!< 0x04000000 */
7617 #define DSI_GPDR_DATA4_3              (0x08UL << DSI_GPDR_DATA4_Pos)            /*!< 0x08000000 */
7618 #define DSI_GPDR_DATA4_4              (0x10UL << DSI_GPDR_DATA4_Pos)            /*!< 0x10000000 */
7619 #define DSI_GPDR_DATA4_5              (0x20UL << DSI_GPDR_DATA4_Pos)            /*!< 0x20000000 */
7620 #define DSI_GPDR_DATA4_6              (0x40UL << DSI_GPDR_DATA4_Pos)            /*!< 0x40000000 */
7621 #define DSI_GPDR_DATA4_7              (0x80UL << DSI_GPDR_DATA4_Pos)            /*!< 0x80000000 */
7622 
7623 /*******************  Bit definition for DSI_GPSR register  ***************/
7624 #define DSI_GPSR_CMDFE_Pos            (0U)
7625 #define DSI_GPSR_CMDFE_Msk            (0x1UL << DSI_GPSR_CMDFE_Pos)             /*!< 0x00000001 */
7626 #define DSI_GPSR_CMDFE                DSI_GPSR_CMDFE_Msk                       /*!< Command FIFO Empty */
7627 #define DSI_GPSR_CMDFF_Pos            (1U)
7628 #define DSI_GPSR_CMDFF_Msk            (0x1UL << DSI_GPSR_CMDFF_Pos)             /*!< 0x00000002 */
7629 #define DSI_GPSR_CMDFF                DSI_GPSR_CMDFF_Msk                       /*!< Command FIFO Full */
7630 #define DSI_GPSR_PWRFE_Pos            (2U)
7631 #define DSI_GPSR_PWRFE_Msk            (0x1UL << DSI_GPSR_PWRFE_Pos)             /*!< 0x00000004 */
7632 #define DSI_GPSR_PWRFE                DSI_GPSR_PWRFE_Msk                       /*!< Payload Write FIFO Empty */
7633 #define DSI_GPSR_PWRFF_Pos            (3U)
7634 #define DSI_GPSR_PWRFF_Msk            (0x1UL << DSI_GPSR_PWRFF_Pos)             /*!< 0x00000008 */
7635 #define DSI_GPSR_PWRFF                DSI_GPSR_PWRFF_Msk                       /*!< Payload Write FIFO Full */
7636 #define DSI_GPSR_PRDFE_Pos            (4U)
7637 #define DSI_GPSR_PRDFE_Msk            (0x1UL << DSI_GPSR_PRDFE_Pos)             /*!< 0x00000010 */
7638 #define DSI_GPSR_PRDFE                DSI_GPSR_PRDFE_Msk                       /*!< Payload Read FIFO Empty */
7639 #define DSI_GPSR_PRDFF_Pos            (5U)
7640 #define DSI_GPSR_PRDFF_Msk            (0x1UL << DSI_GPSR_PRDFF_Pos)             /*!< 0x00000020 */
7641 #define DSI_GPSR_PRDFF                DSI_GPSR_PRDFF_Msk                       /*!< Payload Read FIFO Full */
7642 #define DSI_GPSR_RCB_Pos              (6U)
7643 #define DSI_GPSR_RCB_Msk              (0x1UL << DSI_GPSR_RCB_Pos)               /*!< 0x00000040 */
7644 #define DSI_GPSR_RCB                  DSI_GPSR_RCB_Msk                         /*!< Read Command Busy */
7645 
7646 /*******************  Bit definition for DSI_TCCR0 register  **************/
7647 #define DSI_TCCR0_LPRX_TOCNT_Pos      (0U)
7648 #define DSI_TCCR0_LPRX_TOCNT_Msk      (0xFFFFUL << DSI_TCCR0_LPRX_TOCNT_Pos)    /*!< 0x0000FFFF */
7649 #define DSI_TCCR0_LPRX_TOCNT          DSI_TCCR0_LPRX_TOCNT_Msk                 /*!< Low-power Reception Timeout Counter */
7650 #define DSI_TCCR0_LPRX_TOCNT0_Pos     (0U)
7651 #define DSI_TCCR0_LPRX_TOCNT0_Msk     (0x1UL << DSI_TCCR0_LPRX_TOCNT0_Pos)      /*!< 0x00000001 */
7652 #define DSI_TCCR0_LPRX_TOCNT0         DSI_TCCR0_LPRX_TOCNT0_Msk
7653 #define DSI_TCCR0_LPRX_TOCNT1_Pos     (1U)
7654 #define DSI_TCCR0_LPRX_TOCNT1_Msk     (0x1UL << DSI_TCCR0_LPRX_TOCNT1_Pos)      /*!< 0x00000002 */
7655 #define DSI_TCCR0_LPRX_TOCNT1         DSI_TCCR0_LPRX_TOCNT1_Msk
7656 #define DSI_TCCR0_LPRX_TOCNT2_Pos     (2U)
7657 #define DSI_TCCR0_LPRX_TOCNT2_Msk     (0x1UL << DSI_TCCR0_LPRX_TOCNT2_Pos)      /*!< 0x00000004 */
7658 #define DSI_TCCR0_LPRX_TOCNT2         DSI_TCCR0_LPRX_TOCNT2_Msk
7659 #define DSI_TCCR0_LPRX_TOCNT3_Pos     (3U)
7660 #define DSI_TCCR0_LPRX_TOCNT3_Msk     (0x1UL << DSI_TCCR0_LPRX_TOCNT3_Pos)      /*!< 0x00000008 */
7661 #define DSI_TCCR0_LPRX_TOCNT3         DSI_TCCR0_LPRX_TOCNT3_Msk
7662 #define DSI_TCCR0_LPRX_TOCNT4_Pos     (4U)
7663 #define DSI_TCCR0_LPRX_TOCNT4_Msk     (0x1UL << DSI_TCCR0_LPRX_TOCNT4_Pos)      /*!< 0x00000010 */
7664 #define DSI_TCCR0_LPRX_TOCNT4         DSI_TCCR0_LPRX_TOCNT4_Msk
7665 #define DSI_TCCR0_LPRX_TOCNT5_Pos     (5U)
7666 #define DSI_TCCR0_LPRX_TOCNT5_Msk     (0x1UL << DSI_TCCR0_LPRX_TOCNT5_Pos)      /*!< 0x00000020 */
7667 #define DSI_TCCR0_LPRX_TOCNT5         DSI_TCCR0_LPRX_TOCNT5_Msk
7668 #define DSI_TCCR0_LPRX_TOCNT6_Pos     (6U)
7669 #define DSI_TCCR0_LPRX_TOCNT6_Msk     (0x1UL << DSI_TCCR0_LPRX_TOCNT6_Pos)      /*!< 0x00000040 */
7670 #define DSI_TCCR0_LPRX_TOCNT6         DSI_TCCR0_LPRX_TOCNT6_Msk
7671 #define DSI_TCCR0_LPRX_TOCNT7_Pos     (7U)
7672 #define DSI_TCCR0_LPRX_TOCNT7_Msk     (0x1UL << DSI_TCCR0_LPRX_TOCNT7_Pos)      /*!< 0x00000080 */
7673 #define DSI_TCCR0_LPRX_TOCNT7         DSI_TCCR0_LPRX_TOCNT7_Msk
7674 #define DSI_TCCR0_LPRX_TOCNT8_Pos     (8U)
7675 #define DSI_TCCR0_LPRX_TOCNT8_Msk     (0x1UL << DSI_TCCR0_LPRX_TOCNT8_Pos)      /*!< 0x00000100 */
7676 #define DSI_TCCR0_LPRX_TOCNT8         DSI_TCCR0_LPRX_TOCNT8_Msk
7677 #define DSI_TCCR0_LPRX_TOCNT9_Pos     (9U)
7678 #define DSI_TCCR0_LPRX_TOCNT9_Msk     (0x1UL << DSI_TCCR0_LPRX_TOCNT9_Pos)      /*!< 0x00000200 */
7679 #define DSI_TCCR0_LPRX_TOCNT9         DSI_TCCR0_LPRX_TOCNT9_Msk
7680 #define DSI_TCCR0_LPRX_TOCNT10_Pos    (10U)
7681 #define DSI_TCCR0_LPRX_TOCNT10_Msk    (0x1UL << DSI_TCCR0_LPRX_TOCNT10_Pos)     /*!< 0x00000400 */
7682 #define DSI_TCCR0_LPRX_TOCNT10        DSI_TCCR0_LPRX_TOCNT10_Msk
7683 #define DSI_TCCR0_LPRX_TOCNT11_Pos    (11U)
7684 #define DSI_TCCR0_LPRX_TOCNT11_Msk    (0x1UL << DSI_TCCR0_LPRX_TOCNT11_Pos)     /*!< 0x00000800 */
7685 #define DSI_TCCR0_LPRX_TOCNT11        DSI_TCCR0_LPRX_TOCNT11_Msk
7686 #define DSI_TCCR0_LPRX_TOCNT12_Pos    (12U)
7687 #define DSI_TCCR0_LPRX_TOCNT12_Msk    (0x1UL << DSI_TCCR0_LPRX_TOCNT12_Pos)     /*!< 0x00001000 */
7688 #define DSI_TCCR0_LPRX_TOCNT12        DSI_TCCR0_LPRX_TOCNT12_Msk
7689 #define DSI_TCCR0_LPRX_TOCNT13_Pos    (13U)
7690 #define DSI_TCCR0_LPRX_TOCNT13_Msk    (0x1UL << DSI_TCCR0_LPRX_TOCNT13_Pos)     /*!< 0x00002000 */
7691 #define DSI_TCCR0_LPRX_TOCNT13        DSI_TCCR0_LPRX_TOCNT13_Msk
7692 #define DSI_TCCR0_LPRX_TOCNT14_Pos    (14U)
7693 #define DSI_TCCR0_LPRX_TOCNT14_Msk    (0x1UL << DSI_TCCR0_LPRX_TOCNT14_Pos)     /*!< 0x00004000 */
7694 #define DSI_TCCR0_LPRX_TOCNT14        DSI_TCCR0_LPRX_TOCNT14_Msk
7695 #define DSI_TCCR0_LPRX_TOCNT15_Pos    (15U)
7696 #define DSI_TCCR0_LPRX_TOCNT15_Msk    (0x1UL << DSI_TCCR0_LPRX_TOCNT15_Pos)     /*!< 0x00008000 */
7697 #define DSI_TCCR0_LPRX_TOCNT15        DSI_TCCR0_LPRX_TOCNT15_Msk
7698 
7699 #define DSI_TCCR0_HSTX_TOCNT_Pos      (16U)
7700 #define DSI_TCCR0_HSTX_TOCNT_Msk      (0xFFFFUL << DSI_TCCR0_HSTX_TOCNT_Pos)    /*!< 0xFFFF0000 */
7701 #define DSI_TCCR0_HSTX_TOCNT          DSI_TCCR0_HSTX_TOCNT_Msk                 /*!< High-Speed Transmission Timeout Counter */
7702 #define DSI_TCCR0_HSTX_TOCNT0_Pos     (16U)
7703 #define DSI_TCCR0_HSTX_TOCNT0_Msk     (0x1UL << DSI_TCCR0_HSTX_TOCNT0_Pos)      /*!< 0x00010000 */
7704 #define DSI_TCCR0_HSTX_TOCNT0         DSI_TCCR0_HSTX_TOCNT0_Msk
7705 #define DSI_TCCR0_HSTX_TOCNT1_Pos     (17U)
7706 #define DSI_TCCR0_HSTX_TOCNT1_Msk     (0x1UL << DSI_TCCR0_HSTX_TOCNT1_Pos)      /*!< 0x00020000 */
7707 #define DSI_TCCR0_HSTX_TOCNT1         DSI_TCCR0_HSTX_TOCNT1_Msk
7708 #define DSI_TCCR0_HSTX_TOCNT2_Pos     (18U)
7709 #define DSI_TCCR0_HSTX_TOCNT2_Msk     (0x1UL << DSI_TCCR0_HSTX_TOCNT2_Pos)      /*!< 0x00040000 */
7710 #define DSI_TCCR0_HSTX_TOCNT2         DSI_TCCR0_HSTX_TOCNT2_Msk
7711 #define DSI_TCCR0_HSTX_TOCNT3_Pos     (19U)
7712 #define DSI_TCCR0_HSTX_TOCNT3_Msk     (0x1UL << DSI_TCCR0_HSTX_TOCNT3_Pos)      /*!< 0x00080000 */
7713 #define DSI_TCCR0_HSTX_TOCNT3         DSI_TCCR0_HSTX_TOCNT3_Msk
7714 #define DSI_TCCR0_HSTX_TOCNT4_Pos     (20U)
7715 #define DSI_TCCR0_HSTX_TOCNT4_Msk     (0x1UL << DSI_TCCR0_HSTX_TOCNT4_Pos)      /*!< 0x00100000 */
7716 #define DSI_TCCR0_HSTX_TOCNT4         DSI_TCCR0_HSTX_TOCNT4_Msk
7717 #define DSI_TCCR0_HSTX_TOCNT5_Pos     (21U)
7718 #define DSI_TCCR0_HSTX_TOCNT5_Msk     (0x1UL << DSI_TCCR0_HSTX_TOCNT5_Pos)      /*!< 0x00200000 */
7719 #define DSI_TCCR0_HSTX_TOCNT5         DSI_TCCR0_HSTX_TOCNT5_Msk
7720 #define DSI_TCCR0_HSTX_TOCNT6_Pos     (22U)
7721 #define DSI_TCCR0_HSTX_TOCNT6_Msk     (0x1UL << DSI_TCCR0_HSTX_TOCNT6_Pos)      /*!< 0x00400000 */
7722 #define DSI_TCCR0_HSTX_TOCNT6         DSI_TCCR0_HSTX_TOCNT6_Msk
7723 #define DSI_TCCR0_HSTX_TOCNT7_Pos     (23U)
7724 #define DSI_TCCR0_HSTX_TOCNT7_Msk     (0x1UL << DSI_TCCR0_HSTX_TOCNT7_Pos)      /*!< 0x00800000 */
7725 #define DSI_TCCR0_HSTX_TOCNT7         DSI_TCCR0_HSTX_TOCNT7_Msk
7726 #define DSI_TCCR0_HSTX_TOCNT8_Pos     (24U)
7727 #define DSI_TCCR0_HSTX_TOCNT8_Msk     (0x1UL << DSI_TCCR0_HSTX_TOCNT8_Pos)      /*!< 0x01000000 */
7728 #define DSI_TCCR0_HSTX_TOCNT8         DSI_TCCR0_HSTX_TOCNT8_Msk
7729 #define DSI_TCCR0_HSTX_TOCNT9_Pos     (25U)
7730 #define DSI_TCCR0_HSTX_TOCNT9_Msk     (0x1UL << DSI_TCCR0_HSTX_TOCNT9_Pos)      /*!< 0x02000000 */
7731 #define DSI_TCCR0_HSTX_TOCNT9         DSI_TCCR0_HSTX_TOCNT9_Msk
7732 #define DSI_TCCR0_HSTX_TOCNT10_Pos    (26U)
7733 #define DSI_TCCR0_HSTX_TOCNT10_Msk    (0x1UL << DSI_TCCR0_HSTX_TOCNT10_Pos)     /*!< 0x04000000 */
7734 #define DSI_TCCR0_HSTX_TOCNT10        DSI_TCCR0_HSTX_TOCNT10_Msk
7735 #define DSI_TCCR0_HSTX_TOCNT11_Pos    (27U)
7736 #define DSI_TCCR0_HSTX_TOCNT11_Msk    (0x1UL << DSI_TCCR0_HSTX_TOCNT11_Pos)     /*!< 0x08000000 */
7737 #define DSI_TCCR0_HSTX_TOCNT11        DSI_TCCR0_HSTX_TOCNT11_Msk
7738 #define DSI_TCCR0_HSTX_TOCNT12_Pos    (28U)
7739 #define DSI_TCCR0_HSTX_TOCNT12_Msk    (0x1UL << DSI_TCCR0_HSTX_TOCNT12_Pos)     /*!< 0x10000000 */
7740 #define DSI_TCCR0_HSTX_TOCNT12        DSI_TCCR0_HSTX_TOCNT12_Msk
7741 #define DSI_TCCR0_HSTX_TOCNT13_Pos    (29U)
7742 #define DSI_TCCR0_HSTX_TOCNT13_Msk    (0x1UL << DSI_TCCR0_HSTX_TOCNT13_Pos)     /*!< 0x20000000 */
7743 #define DSI_TCCR0_HSTX_TOCNT13        DSI_TCCR0_HSTX_TOCNT13_Msk
7744 #define DSI_TCCR0_HSTX_TOCNT14_Pos    (30U)
7745 #define DSI_TCCR0_HSTX_TOCNT14_Msk    (0x1UL << DSI_TCCR0_HSTX_TOCNT14_Pos)     /*!< 0x40000000 */
7746 #define DSI_TCCR0_HSTX_TOCNT14        DSI_TCCR0_HSTX_TOCNT14_Msk
7747 #define DSI_TCCR0_HSTX_TOCNT15_Pos    (31U)
7748 #define DSI_TCCR0_HSTX_TOCNT15_Msk    (0x1UL << DSI_TCCR0_HSTX_TOCNT15_Pos)     /*!< 0x80000000 */
7749 #define DSI_TCCR0_HSTX_TOCNT15        DSI_TCCR0_HSTX_TOCNT15_Msk
7750 
7751 /*******************  Bit definition for DSI_TCCR1 register  **************/
7752 #define DSI_TCCR1_HSRD_TOCNT_Pos      (0U)
7753 #define DSI_TCCR1_HSRD_TOCNT_Msk      (0xFFFFUL << DSI_TCCR1_HSRD_TOCNT_Pos)    /*!< 0x0000FFFF */
7754 #define DSI_TCCR1_HSRD_TOCNT          DSI_TCCR1_HSRD_TOCNT_Msk                 /*!< High-Speed Read Timeout Counter */
7755 #define DSI_TCCR1_HSRD_TOCNT0_Pos     (0U)
7756 #define DSI_TCCR1_HSRD_TOCNT0_Msk     (0x1UL << DSI_TCCR1_HSRD_TOCNT0_Pos)      /*!< 0x00000001 */
7757 #define DSI_TCCR1_HSRD_TOCNT0         DSI_TCCR1_HSRD_TOCNT0_Msk
7758 #define DSI_TCCR1_HSRD_TOCNT1_Pos     (1U)
7759 #define DSI_TCCR1_HSRD_TOCNT1_Msk     (0x1UL << DSI_TCCR1_HSRD_TOCNT1_Pos)      /*!< 0x00000002 */
7760 #define DSI_TCCR1_HSRD_TOCNT1         DSI_TCCR1_HSRD_TOCNT1_Msk
7761 #define DSI_TCCR1_HSRD_TOCNT2_Pos     (2U)
7762 #define DSI_TCCR1_HSRD_TOCNT2_Msk     (0x1UL << DSI_TCCR1_HSRD_TOCNT2_Pos)      /*!< 0x00000004 */
7763 #define DSI_TCCR1_HSRD_TOCNT2         DSI_TCCR1_HSRD_TOCNT2_Msk
7764 #define DSI_TCCR1_HSRD_TOCNT3_Pos     (3U)
7765 #define DSI_TCCR1_HSRD_TOCNT3_Msk     (0x1UL << DSI_TCCR1_HSRD_TOCNT3_Pos)      /*!< 0x00000008 */
7766 #define DSI_TCCR1_HSRD_TOCNT3         DSI_TCCR1_HSRD_TOCNT3_Msk
7767 #define DSI_TCCR1_HSRD_TOCNT4_Pos     (4U)
7768 #define DSI_TCCR1_HSRD_TOCNT4_Msk     (0x1UL << DSI_TCCR1_HSRD_TOCNT4_Pos)      /*!< 0x00000010 */
7769 #define DSI_TCCR1_HSRD_TOCNT4         DSI_TCCR1_HSRD_TOCNT4_Msk
7770 #define DSI_TCCR1_HSRD_TOCNT5_Pos     (5U)
7771 #define DSI_TCCR1_HSRD_TOCNT5_Msk     (0x1UL << DSI_TCCR1_HSRD_TOCNT5_Pos)      /*!< 0x00000020 */
7772 #define DSI_TCCR1_HSRD_TOCNT5         DSI_TCCR1_HSRD_TOCNT5_Msk
7773 #define DSI_TCCR1_HSRD_TOCNT6_Pos     (6U)
7774 #define DSI_TCCR1_HSRD_TOCNT6_Msk     (0x1UL << DSI_TCCR1_HSRD_TOCNT6_Pos)      /*!< 0x00000040 */
7775 #define DSI_TCCR1_HSRD_TOCNT6         DSI_TCCR1_HSRD_TOCNT6_Msk
7776 #define DSI_TCCR1_HSRD_TOCNT7_Pos     (7U)
7777 #define DSI_TCCR1_HSRD_TOCNT7_Msk     (0x1UL << DSI_TCCR1_HSRD_TOCNT7_Pos)      /*!< 0x00000080 */
7778 #define DSI_TCCR1_HSRD_TOCNT7         DSI_TCCR1_HSRD_TOCNT7_Msk
7779 #define DSI_TCCR1_HSRD_TOCNT8_Pos     (8U)
7780 #define DSI_TCCR1_HSRD_TOCNT8_Msk     (0x1UL << DSI_TCCR1_HSRD_TOCNT8_Pos)      /*!< 0x00000100 */
7781 #define DSI_TCCR1_HSRD_TOCNT8         DSI_TCCR1_HSRD_TOCNT8_Msk
7782 #define DSI_TCCR1_HSRD_TOCNT9_Pos     (9U)
7783 #define DSI_TCCR1_HSRD_TOCNT9_Msk     (0x1UL << DSI_TCCR1_HSRD_TOCNT9_Pos)      /*!< 0x00000200 */
7784 #define DSI_TCCR1_HSRD_TOCNT9         DSI_TCCR1_HSRD_TOCNT9_Msk
7785 #define DSI_TCCR1_HSRD_TOCNT10_Pos    (10U)
7786 #define DSI_TCCR1_HSRD_TOCNT10_Msk    (0x1UL << DSI_TCCR1_HSRD_TOCNT10_Pos)     /*!< 0x00000400 */
7787 #define DSI_TCCR1_HSRD_TOCNT10        DSI_TCCR1_HSRD_TOCNT10_Msk
7788 #define DSI_TCCR1_HSRD_TOCNT11_Pos    (11U)
7789 #define DSI_TCCR1_HSRD_TOCNT11_Msk    (0x1UL << DSI_TCCR1_HSRD_TOCNT11_Pos)     /*!< 0x00000800 */
7790 #define DSI_TCCR1_HSRD_TOCNT11        DSI_TCCR1_HSRD_TOCNT11_Msk
7791 #define DSI_TCCR1_HSRD_TOCNT12_Pos    (12U)
7792 #define DSI_TCCR1_HSRD_TOCNT12_Msk    (0x1UL << DSI_TCCR1_HSRD_TOCNT12_Pos)     /*!< 0x00001000 */
7793 #define DSI_TCCR1_HSRD_TOCNT12        DSI_TCCR1_HSRD_TOCNT12_Msk
7794 #define DSI_TCCR1_HSRD_TOCNT13_Pos    (13U)
7795 #define DSI_TCCR1_HSRD_TOCNT13_Msk    (0x1UL << DSI_TCCR1_HSRD_TOCNT13_Pos)     /*!< 0x00002000 */
7796 #define DSI_TCCR1_HSRD_TOCNT13        DSI_TCCR1_HSRD_TOCNT13_Msk
7797 #define DSI_TCCR1_HSRD_TOCNT14_Pos    (14U)
7798 #define DSI_TCCR1_HSRD_TOCNT14_Msk    (0x1UL << DSI_TCCR1_HSRD_TOCNT14_Pos)     /*!< 0x00004000 */
7799 #define DSI_TCCR1_HSRD_TOCNT14        DSI_TCCR1_HSRD_TOCNT14_Msk
7800 #define DSI_TCCR1_HSRD_TOCNT15_Pos    (15U)
7801 #define DSI_TCCR1_HSRD_TOCNT15_Msk    (0x1UL << DSI_TCCR1_HSRD_TOCNT15_Pos)     /*!< 0x00008000 */
7802 #define DSI_TCCR1_HSRD_TOCNT15        DSI_TCCR1_HSRD_TOCNT15_Msk
7803 
7804 /*******************  Bit definition for DSI_TCCR2 register  **************/
7805 #define DSI_TCCR2_LPRD_TOCNT_Pos      (0U)
7806 #define DSI_TCCR2_LPRD_TOCNT_Msk      (0xFFFFUL << DSI_TCCR2_LPRD_TOCNT_Pos)    /*!< 0x0000FFFF */
7807 #define DSI_TCCR2_LPRD_TOCNT          DSI_TCCR2_LPRD_TOCNT_Msk                 /*!< Low-Power Read Timeout Counter */
7808 #define DSI_TCCR2_LPRD_TOCNT0_Pos     (0U)
7809 #define DSI_TCCR2_LPRD_TOCNT0_Msk     (0x1UL << DSI_TCCR2_LPRD_TOCNT0_Pos)      /*!< 0x00000001 */
7810 #define DSI_TCCR2_LPRD_TOCNT0         DSI_TCCR2_LPRD_TOCNT0_Msk
7811 #define DSI_TCCR2_LPRD_TOCNT1_Pos     (1U)
7812 #define DSI_TCCR2_LPRD_TOCNT1_Msk     (0x1UL << DSI_TCCR2_LPRD_TOCNT1_Pos)      /*!< 0x00000002 */
7813 #define DSI_TCCR2_LPRD_TOCNT1         DSI_TCCR2_LPRD_TOCNT1_Msk
7814 #define DSI_TCCR2_LPRD_TOCNT2_Pos     (2U)
7815 #define DSI_TCCR2_LPRD_TOCNT2_Msk     (0x1UL << DSI_TCCR2_LPRD_TOCNT2_Pos)      /*!< 0x00000004 */
7816 #define DSI_TCCR2_LPRD_TOCNT2         DSI_TCCR2_LPRD_TOCNT2_Msk
7817 #define DSI_TCCR2_LPRD_TOCNT3_Pos     (3U)
7818 #define DSI_TCCR2_LPRD_TOCNT3_Msk     (0x1UL << DSI_TCCR2_LPRD_TOCNT3_Pos)      /*!< 0x00000008 */
7819 #define DSI_TCCR2_LPRD_TOCNT3         DSI_TCCR2_LPRD_TOCNT3_Msk
7820 #define DSI_TCCR2_LPRD_TOCNT4_Pos     (4U)
7821 #define DSI_TCCR2_LPRD_TOCNT4_Msk     (0x1UL << DSI_TCCR2_LPRD_TOCNT4_Pos)      /*!< 0x00000010 */
7822 #define DSI_TCCR2_LPRD_TOCNT4         DSI_TCCR2_LPRD_TOCNT4_Msk
7823 #define DSI_TCCR2_LPRD_TOCNT5_Pos     (5U)
7824 #define DSI_TCCR2_LPRD_TOCNT5_Msk     (0x1UL << DSI_TCCR2_LPRD_TOCNT5_Pos)      /*!< 0x00000020 */
7825 #define DSI_TCCR2_LPRD_TOCNT5         DSI_TCCR2_LPRD_TOCNT5_Msk
7826 #define DSI_TCCR2_LPRD_TOCNT6_Pos     (6U)
7827 #define DSI_TCCR2_LPRD_TOCNT6_Msk     (0x1UL << DSI_TCCR2_LPRD_TOCNT6_Pos)      /*!< 0x00000040 */
7828 #define DSI_TCCR2_LPRD_TOCNT6         DSI_TCCR2_LPRD_TOCNT6_Msk
7829 #define DSI_TCCR2_LPRD_TOCNT7_Pos     (7U)
7830 #define DSI_TCCR2_LPRD_TOCNT7_Msk     (0x1UL << DSI_TCCR2_LPRD_TOCNT7_Pos)      /*!< 0x00000080 */
7831 #define DSI_TCCR2_LPRD_TOCNT7         DSI_TCCR2_LPRD_TOCNT7_Msk
7832 #define DSI_TCCR2_LPRD_TOCNT8_Pos     (8U)
7833 #define DSI_TCCR2_LPRD_TOCNT8_Msk     (0x1UL << DSI_TCCR2_LPRD_TOCNT8_Pos)      /*!< 0x00000100 */
7834 #define DSI_TCCR2_LPRD_TOCNT8         DSI_TCCR2_LPRD_TOCNT8_Msk
7835 #define DSI_TCCR2_LPRD_TOCNT9_Pos     (9U)
7836 #define DSI_TCCR2_LPRD_TOCNT9_Msk     (0x1UL << DSI_TCCR2_LPRD_TOCNT9_Pos)      /*!< 0x00000200 */
7837 #define DSI_TCCR2_LPRD_TOCNT9         DSI_TCCR2_LPRD_TOCNT9_Msk
7838 #define DSI_TCCR2_LPRD_TOCNT10_Pos    (10U)
7839 #define DSI_TCCR2_LPRD_TOCNT10_Msk    (0x1UL << DSI_TCCR2_LPRD_TOCNT10_Pos)     /*!< 0x00000400 */
7840 #define DSI_TCCR2_LPRD_TOCNT10        DSI_TCCR2_LPRD_TOCNT10_Msk
7841 #define DSI_TCCR2_LPRD_TOCNT11_Pos    (11U)
7842 #define DSI_TCCR2_LPRD_TOCNT11_Msk    (0x1UL << DSI_TCCR2_LPRD_TOCNT11_Pos)     /*!< 0x00000800 */
7843 #define DSI_TCCR2_LPRD_TOCNT11        DSI_TCCR2_LPRD_TOCNT11_Msk
7844 #define DSI_TCCR2_LPRD_TOCNT12_Pos    (12U)
7845 #define DSI_TCCR2_LPRD_TOCNT12_Msk    (0x1UL << DSI_TCCR2_LPRD_TOCNT12_Pos)     /*!< 0x00001000 */
7846 #define DSI_TCCR2_LPRD_TOCNT12        DSI_TCCR2_LPRD_TOCNT12_Msk
7847 #define DSI_TCCR2_LPRD_TOCNT13_Pos    (13U)
7848 #define DSI_TCCR2_LPRD_TOCNT13_Msk    (0x1UL << DSI_TCCR2_LPRD_TOCNT13_Pos)     /*!< 0x00002000 */
7849 #define DSI_TCCR2_LPRD_TOCNT13        DSI_TCCR2_LPRD_TOCNT13_Msk
7850 #define DSI_TCCR2_LPRD_TOCNT14_Pos    (14U)
7851 #define DSI_TCCR2_LPRD_TOCNT14_Msk    (0x1UL << DSI_TCCR2_LPRD_TOCNT14_Pos)     /*!< 0x00004000 */
7852 #define DSI_TCCR2_LPRD_TOCNT14        DSI_TCCR2_LPRD_TOCNT14_Msk
7853 #define DSI_TCCR2_LPRD_TOCNT15_Pos    (15U)
7854 #define DSI_TCCR2_LPRD_TOCNT15_Msk    (0x1UL << DSI_TCCR2_LPRD_TOCNT15_Pos)     /*!< 0x00008000 */
7855 #define DSI_TCCR2_LPRD_TOCNT15        DSI_TCCR2_LPRD_TOCNT15_Msk
7856 
7857 /*******************  Bit definition for DSI_TCCR3 register  **************/
7858 #define DSI_TCCR3_HSWR_TOCNT_Pos      (0U)
7859 #define DSI_TCCR3_HSWR_TOCNT_Msk      (0xFFFFUL << DSI_TCCR3_HSWR_TOCNT_Pos)    /*!< 0x0000FFFF */
7860 #define DSI_TCCR3_HSWR_TOCNT          DSI_TCCR3_HSWR_TOCNT_Msk                 /*!< High-Speed Write Timeout Counter */
7861 #define DSI_TCCR3_HSWR_TOCNT0_Pos     (0U)
7862 #define DSI_TCCR3_HSWR_TOCNT0_Msk     (0x1UL << DSI_TCCR3_HSWR_TOCNT0_Pos)      /*!< 0x00000001 */
7863 #define DSI_TCCR3_HSWR_TOCNT0         DSI_TCCR3_HSWR_TOCNT0_Msk
7864 #define DSI_TCCR3_HSWR_TOCNT1_Pos     (1U)
7865 #define DSI_TCCR3_HSWR_TOCNT1_Msk     (0x1UL << DSI_TCCR3_HSWR_TOCNT1_Pos)      /*!< 0x00000002 */
7866 #define DSI_TCCR3_HSWR_TOCNT1         DSI_TCCR3_HSWR_TOCNT1_Msk
7867 #define DSI_TCCR3_HSWR_TOCNT2_Pos     (2U)
7868 #define DSI_TCCR3_HSWR_TOCNT2_Msk     (0x1UL << DSI_TCCR3_HSWR_TOCNT2_Pos)      /*!< 0x00000004 */
7869 #define DSI_TCCR3_HSWR_TOCNT2         DSI_TCCR3_HSWR_TOCNT2_Msk
7870 #define DSI_TCCR3_HSWR_TOCNT3_Pos     (3U)
7871 #define DSI_TCCR3_HSWR_TOCNT3_Msk     (0x1UL << DSI_TCCR3_HSWR_TOCNT3_Pos)      /*!< 0x00000008 */
7872 #define DSI_TCCR3_HSWR_TOCNT3         DSI_TCCR3_HSWR_TOCNT3_Msk
7873 #define DSI_TCCR3_HSWR_TOCNT4_Pos     (4U)
7874 #define DSI_TCCR3_HSWR_TOCNT4_Msk     (0x1UL << DSI_TCCR3_HSWR_TOCNT4_Pos)      /*!< 0x00000010 */
7875 #define DSI_TCCR3_HSWR_TOCNT4         DSI_TCCR3_HSWR_TOCNT4_Msk
7876 #define DSI_TCCR3_HSWR_TOCNT5_Pos     (5U)
7877 #define DSI_TCCR3_HSWR_TOCNT5_Msk     (0x1UL << DSI_TCCR3_HSWR_TOCNT5_Pos)      /*!< 0x00000020 */
7878 #define DSI_TCCR3_HSWR_TOCNT5         DSI_TCCR3_HSWR_TOCNT5_Msk
7879 #define DSI_TCCR3_HSWR_TOCNT6_Pos     (6U)
7880 #define DSI_TCCR3_HSWR_TOCNT6_Msk     (0x1UL << DSI_TCCR3_HSWR_TOCNT6_Pos)      /*!< 0x00000040 */
7881 #define DSI_TCCR3_HSWR_TOCNT6         DSI_TCCR3_HSWR_TOCNT6_Msk
7882 #define DSI_TCCR3_HSWR_TOCNT7_Pos     (7U)
7883 #define DSI_TCCR3_HSWR_TOCNT7_Msk     (0x1UL << DSI_TCCR3_HSWR_TOCNT7_Pos)      /*!< 0x00000080 */
7884 #define DSI_TCCR3_HSWR_TOCNT7         DSI_TCCR3_HSWR_TOCNT7_Msk
7885 #define DSI_TCCR3_HSWR_TOCNT8_Pos     (8U)
7886 #define DSI_TCCR3_HSWR_TOCNT8_Msk     (0x1UL << DSI_TCCR3_HSWR_TOCNT8_Pos)      /*!< 0x00000100 */
7887 #define DSI_TCCR3_HSWR_TOCNT8         DSI_TCCR3_HSWR_TOCNT8_Msk
7888 #define DSI_TCCR3_HSWR_TOCNT9_Pos     (9U)
7889 #define DSI_TCCR3_HSWR_TOCNT9_Msk     (0x1UL << DSI_TCCR3_HSWR_TOCNT9_Pos)      /*!< 0x00000200 */
7890 #define DSI_TCCR3_HSWR_TOCNT9         DSI_TCCR3_HSWR_TOCNT9_Msk
7891 #define DSI_TCCR3_HSWR_TOCNT10_Pos    (10U)
7892 #define DSI_TCCR3_HSWR_TOCNT10_Msk    (0x1UL << DSI_TCCR3_HSWR_TOCNT10_Pos)     /*!< 0x00000400 */
7893 #define DSI_TCCR3_HSWR_TOCNT10        DSI_TCCR3_HSWR_TOCNT10_Msk
7894 #define DSI_TCCR3_HSWR_TOCNT11_Pos    (11U)
7895 #define DSI_TCCR3_HSWR_TOCNT11_Msk    (0x1UL << DSI_TCCR3_HSWR_TOCNT11_Pos)     /*!< 0x00000800 */
7896 #define DSI_TCCR3_HSWR_TOCNT11        DSI_TCCR3_HSWR_TOCNT11_Msk
7897 #define DSI_TCCR3_HSWR_TOCNT12_Pos    (12U)
7898 #define DSI_TCCR3_HSWR_TOCNT12_Msk    (0x1UL << DSI_TCCR3_HSWR_TOCNT12_Pos)     /*!< 0x00001000 */
7899 #define DSI_TCCR3_HSWR_TOCNT12        DSI_TCCR3_HSWR_TOCNT12_Msk
7900 #define DSI_TCCR3_HSWR_TOCNT13_Pos    (13U)
7901 #define DSI_TCCR3_HSWR_TOCNT13_Msk    (0x1UL << DSI_TCCR3_HSWR_TOCNT13_Pos)     /*!< 0x00002000 */
7902 #define DSI_TCCR3_HSWR_TOCNT13        DSI_TCCR3_HSWR_TOCNT13_Msk
7903 #define DSI_TCCR3_HSWR_TOCNT14_Pos    (14U)
7904 #define DSI_TCCR3_HSWR_TOCNT14_Msk    (0x1UL << DSI_TCCR3_HSWR_TOCNT14_Pos)     /*!< 0x00004000 */
7905 #define DSI_TCCR3_HSWR_TOCNT14        DSI_TCCR3_HSWR_TOCNT14_Msk
7906 #define DSI_TCCR3_HSWR_TOCNT15_Pos    (15U)
7907 #define DSI_TCCR3_HSWR_TOCNT15_Msk    (0x1UL << DSI_TCCR3_HSWR_TOCNT15_Pos)     /*!< 0x00008000 */
7908 #define DSI_TCCR3_HSWR_TOCNT15        DSI_TCCR3_HSWR_TOCNT15_Msk
7909 
7910 #define DSI_TCCR3_PM_Pos              (24U)
7911 #define DSI_TCCR3_PM_Msk              (0x1UL << DSI_TCCR3_PM_Pos)               /*!< 0x01000000 */
7912 #define DSI_TCCR3_PM                  DSI_TCCR3_PM_Msk                         /*!< Presp Mode */
7913 
7914 /*******************  Bit definition for DSI_TCCR4 register  **************/
7915 #define DSI_TCCR4_LPWR_TOCNT_Pos      (0U)
7916 #define DSI_TCCR4_LPWR_TOCNT_Msk      (0xFFFFUL << DSI_TCCR4_LPWR_TOCNT_Pos)    /*!< 0x0000FFFF */
7917 #define DSI_TCCR4_LPWR_TOCNT          DSI_TCCR4_LPWR_TOCNT_Msk                 /*!< Low-Power Write Timeout Counter */
7918 #define DSI_TCCR4_LPWR_TOCNT0_Pos     (0U)
7919 #define DSI_TCCR4_LPWR_TOCNT0_Msk     (0x1UL << DSI_TCCR4_LPWR_TOCNT0_Pos)      /*!< 0x00000001 */
7920 #define DSI_TCCR4_LPWR_TOCNT0         DSI_TCCR4_LPWR_TOCNT0_Msk
7921 #define DSI_TCCR4_LPWR_TOCNT1_Pos     (1U)
7922 #define DSI_TCCR4_LPWR_TOCNT1_Msk     (0x1UL << DSI_TCCR4_LPWR_TOCNT1_Pos)      /*!< 0x00000002 */
7923 #define DSI_TCCR4_LPWR_TOCNT1         DSI_TCCR4_LPWR_TOCNT1_Msk
7924 #define DSI_TCCR4_LPWR_TOCNT2_Pos     (2U)
7925 #define DSI_TCCR4_LPWR_TOCNT2_Msk     (0x1UL << DSI_TCCR4_LPWR_TOCNT2_Pos)      /*!< 0x00000004 */
7926 #define DSI_TCCR4_LPWR_TOCNT2         DSI_TCCR4_LPWR_TOCNT2_Msk
7927 #define DSI_TCCR4_LPWR_TOCNT3_Pos     (3U)
7928 #define DSI_TCCR4_LPWR_TOCNT3_Msk     (0x1UL << DSI_TCCR4_LPWR_TOCNT3_Pos)      /*!< 0x00000008 */
7929 #define DSI_TCCR4_LPWR_TOCNT3         DSI_TCCR4_LPWR_TOCNT3_Msk
7930 #define DSI_TCCR4_LPWR_TOCNT4_Pos     (4U)
7931 #define DSI_TCCR4_LPWR_TOCNT4_Msk     (0x1UL << DSI_TCCR4_LPWR_TOCNT4_Pos)      /*!< 0x00000010 */
7932 #define DSI_TCCR4_LPWR_TOCNT4         DSI_TCCR4_LPWR_TOCNT4_Msk
7933 #define DSI_TCCR4_LPWR_TOCNT5_Pos     (5U)
7934 #define DSI_TCCR4_LPWR_TOCNT5_Msk     (0x1UL << DSI_TCCR4_LPWR_TOCNT5_Pos)      /*!< 0x00000020 */
7935 #define DSI_TCCR4_LPWR_TOCNT5         DSI_TCCR4_LPWR_TOCNT5_Msk
7936 #define DSI_TCCR4_LPWR_TOCNT6_Pos     (6U)
7937 #define DSI_TCCR4_LPWR_TOCNT6_Msk     (0x1UL << DSI_TCCR4_LPWR_TOCNT6_Pos)      /*!< 0x00000040 */
7938 #define DSI_TCCR4_LPWR_TOCNT6         DSI_TCCR4_LPWR_TOCNT6_Msk
7939 #define DSI_TCCR4_LPWR_TOCNT7_Pos     (7U)
7940 #define DSI_TCCR4_LPWR_TOCNT7_Msk     (0x1UL << DSI_TCCR4_LPWR_TOCNT7_Pos)      /*!< 0x00000080 */
7941 #define DSI_TCCR4_LPWR_TOCNT7         DSI_TCCR4_LPWR_TOCNT7_Msk
7942 #define DSI_TCCR4_LPWR_TOCNT8_Pos     (8U)
7943 #define DSI_TCCR4_LPWR_TOCNT8_Msk     (0x1UL << DSI_TCCR4_LPWR_TOCNT8_Pos)      /*!< 0x00000100 */
7944 #define DSI_TCCR4_LPWR_TOCNT8         DSI_TCCR4_LPWR_TOCNT8_Msk
7945 #define DSI_TCCR4_LPWR_TOCNT9_Pos     (9U)
7946 #define DSI_TCCR4_LPWR_TOCNT9_Msk     (0x1UL << DSI_TCCR4_LPWR_TOCNT9_Pos)      /*!< 0x00000200 */
7947 #define DSI_TCCR4_LPWR_TOCNT9         DSI_TCCR4_LPWR_TOCNT9_Msk
7948 #define DSI_TCCR4_LPWR_TOCNT10_Pos    (10U)
7949 #define DSI_TCCR4_LPWR_TOCNT10_Msk    (0x1UL << DSI_TCCR4_LPWR_TOCNT10_Pos)     /*!< 0x00000400 */
7950 #define DSI_TCCR4_LPWR_TOCNT10        DSI_TCCR4_LPWR_TOCNT10_Msk
7951 #define DSI_TCCR4_LPWR_TOCNT11_Pos    (11U)
7952 #define DSI_TCCR4_LPWR_TOCNT11_Msk    (0x1UL << DSI_TCCR4_LPWR_TOCNT11_Pos)     /*!< 0x00000800 */
7953 #define DSI_TCCR4_LPWR_TOCNT11        DSI_TCCR4_LPWR_TOCNT11_Msk
7954 #define DSI_TCCR4_LPWR_TOCNT12_Pos    (12U)
7955 #define DSI_TCCR4_LPWR_TOCNT12_Msk    (0x1UL << DSI_TCCR4_LPWR_TOCNT12_Pos)     /*!< 0x00001000 */
7956 #define DSI_TCCR4_LPWR_TOCNT12        DSI_TCCR4_LPWR_TOCNT12_Msk
7957 #define DSI_TCCR4_LPWR_TOCNT13_Pos    (13U)
7958 #define DSI_TCCR4_LPWR_TOCNT13_Msk    (0x1UL << DSI_TCCR4_LPWR_TOCNT13_Pos)     /*!< 0x00002000 */
7959 #define DSI_TCCR4_LPWR_TOCNT13        DSI_TCCR4_LPWR_TOCNT13_Msk
7960 #define DSI_TCCR4_LPWR_TOCNT14_Pos    (14U)
7961 #define DSI_TCCR4_LPWR_TOCNT14_Msk    (0x1UL << DSI_TCCR4_LPWR_TOCNT14_Pos)     /*!< 0x00004000 */
7962 #define DSI_TCCR4_LPWR_TOCNT14        DSI_TCCR4_LPWR_TOCNT14_Msk
7963 #define DSI_TCCR4_LPWR_TOCNT15_Pos    (15U)
7964 #define DSI_TCCR4_LPWR_TOCNT15_Msk    (0x1UL << DSI_TCCR4_LPWR_TOCNT15_Pos)     /*!< 0x00008000 */
7965 #define DSI_TCCR4_LPWR_TOCNT15        DSI_TCCR4_LPWR_TOCNT15_Msk
7966 
7967 /*******************  Bit definition for DSI_TCCR5 register  **************/
7968 #define DSI_TCCR5_BTA_TOCNT_Pos       (0U)
7969 #define DSI_TCCR5_BTA_TOCNT_Msk       (0xFFFFUL << DSI_TCCR5_BTA_TOCNT_Pos)     /*!< 0x0000FFFF */
7970 #define DSI_TCCR5_BTA_TOCNT           DSI_TCCR5_BTA_TOCNT_Msk                  /*!< Bus-Turn-Around Timeout Counter */
7971 #define DSI_TCCR5_BTA_TOCNT0_Pos      (0U)
7972 #define DSI_TCCR5_BTA_TOCNT0_Msk      (0x1UL << DSI_TCCR5_BTA_TOCNT0_Pos)       /*!< 0x00000001 */
7973 #define DSI_TCCR5_BTA_TOCNT0          DSI_TCCR5_BTA_TOCNT0_Msk
7974 #define DSI_TCCR5_BTA_TOCNT1_Pos      (1U)
7975 #define DSI_TCCR5_BTA_TOCNT1_Msk      (0x1UL << DSI_TCCR5_BTA_TOCNT1_Pos)       /*!< 0x00000002 */
7976 #define DSI_TCCR5_BTA_TOCNT1          DSI_TCCR5_BTA_TOCNT1_Msk
7977 #define DSI_TCCR5_BTA_TOCNT2_Pos      (2U)
7978 #define DSI_TCCR5_BTA_TOCNT2_Msk      (0x1UL << DSI_TCCR5_BTA_TOCNT2_Pos)       /*!< 0x00000004 */
7979 #define DSI_TCCR5_BTA_TOCNT2          DSI_TCCR5_BTA_TOCNT2_Msk
7980 #define DSI_TCCR5_BTA_TOCNT3_Pos      (3U)
7981 #define DSI_TCCR5_BTA_TOCNT3_Msk      (0x1UL << DSI_TCCR5_BTA_TOCNT3_Pos)       /*!< 0x00000008 */
7982 #define DSI_TCCR5_BTA_TOCNT3          DSI_TCCR5_BTA_TOCNT3_Msk
7983 #define DSI_TCCR5_BTA_TOCNT4_Pos      (4U)
7984 #define DSI_TCCR5_BTA_TOCNT4_Msk      (0x1UL << DSI_TCCR5_BTA_TOCNT4_Pos)       /*!< 0x00000010 */
7985 #define DSI_TCCR5_BTA_TOCNT4          DSI_TCCR5_BTA_TOCNT4_Msk
7986 #define DSI_TCCR5_BTA_TOCNT5_Pos      (5U)
7987 #define DSI_TCCR5_BTA_TOCNT5_Msk      (0x1UL << DSI_TCCR5_BTA_TOCNT5_Pos)       /*!< 0x00000020 */
7988 #define DSI_TCCR5_BTA_TOCNT5          DSI_TCCR5_BTA_TOCNT5_Msk
7989 #define DSI_TCCR5_BTA_TOCNT6_Pos      (6U)
7990 #define DSI_TCCR5_BTA_TOCNT6_Msk      (0x1UL << DSI_TCCR5_BTA_TOCNT6_Pos)       /*!< 0x00000040 */
7991 #define DSI_TCCR5_BTA_TOCNT6          DSI_TCCR5_BTA_TOCNT6_Msk
7992 #define DSI_TCCR5_BTA_TOCNT7_Pos      (7U)
7993 #define DSI_TCCR5_BTA_TOCNT7_Msk      (0x1UL << DSI_TCCR5_BTA_TOCNT7_Pos)       /*!< 0x00000080 */
7994 #define DSI_TCCR5_BTA_TOCNT7          DSI_TCCR5_BTA_TOCNT7_Msk
7995 #define DSI_TCCR5_BTA_TOCNT8_Pos      (8U)
7996 #define DSI_TCCR5_BTA_TOCNT8_Msk      (0x1UL << DSI_TCCR5_BTA_TOCNT8_Pos)       /*!< 0x00000100 */
7997 #define DSI_TCCR5_BTA_TOCNT8          DSI_TCCR5_BTA_TOCNT8_Msk
7998 #define DSI_TCCR5_BTA_TOCNT9_Pos      (9U)
7999 #define DSI_TCCR5_BTA_TOCNT9_Msk      (0x1UL << DSI_TCCR5_BTA_TOCNT9_Pos)       /*!< 0x00000200 */
8000 #define DSI_TCCR5_BTA_TOCNT9          DSI_TCCR5_BTA_TOCNT9_Msk
8001 #define DSI_TCCR5_BTA_TOCNT10_Pos     (10U)
8002 #define DSI_TCCR5_BTA_TOCNT10_Msk     (0x1UL << DSI_TCCR5_BTA_TOCNT10_Pos)      /*!< 0x00000400 */
8003 #define DSI_TCCR5_BTA_TOCNT10         DSI_TCCR5_BTA_TOCNT10_Msk
8004 #define DSI_TCCR5_BTA_TOCNT11_Pos     (11U)
8005 #define DSI_TCCR5_BTA_TOCNT11_Msk     (0x1UL << DSI_TCCR5_BTA_TOCNT11_Pos)      /*!< 0x00000800 */
8006 #define DSI_TCCR5_BTA_TOCNT11         DSI_TCCR5_BTA_TOCNT11_Msk
8007 #define DSI_TCCR5_BTA_TOCNT12_Pos     (12U)
8008 #define DSI_TCCR5_BTA_TOCNT12_Msk     (0x1UL << DSI_TCCR5_BTA_TOCNT12_Pos)      /*!< 0x00001000 */
8009 #define DSI_TCCR5_BTA_TOCNT12         DSI_TCCR5_BTA_TOCNT12_Msk
8010 #define DSI_TCCR5_BTA_TOCNT13_Pos     (13U)
8011 #define DSI_TCCR5_BTA_TOCNT13_Msk     (0x1UL << DSI_TCCR5_BTA_TOCNT13_Pos)      /*!< 0x00002000 */
8012 #define DSI_TCCR5_BTA_TOCNT13         DSI_TCCR5_BTA_TOCNT13_Msk
8013 #define DSI_TCCR5_BTA_TOCNT14_Pos     (14U)
8014 #define DSI_TCCR5_BTA_TOCNT14_Msk     (0x1UL << DSI_TCCR5_BTA_TOCNT14_Pos)      /*!< 0x00004000 */
8015 #define DSI_TCCR5_BTA_TOCNT14         DSI_TCCR5_BTA_TOCNT14_Msk
8016 #define DSI_TCCR5_BTA_TOCNT15_Pos     (15U)
8017 #define DSI_TCCR5_BTA_TOCNT15_Msk     (0x1UL << DSI_TCCR5_BTA_TOCNT15_Pos)      /*!< 0x00008000 */
8018 #define DSI_TCCR5_BTA_TOCNT15         DSI_TCCR5_BTA_TOCNT15_Msk
8019 
8020 /*******************  Bit definition for DSI_TDCR register  ***************/
8021 #define DSI_TDCR_3DM                  0x00000003U                              /*!< 3D Mode */
8022 #define DSI_TDCR_3DM0                 0x00000001U
8023 #define DSI_TDCR_3DM1                 0x00000002U
8024 
8025 #define DSI_TDCR_3DF                  0x0000000CU                              /*!< 3D Format */
8026 #define DSI_TDCR_3DF0                 0x00000004U
8027 #define DSI_TDCR_3DF1                 0x00000008U
8028 
8029 #define DSI_TDCR_SVS_Pos              (4U)
8030 #define DSI_TDCR_SVS_Msk              (0x1UL << DSI_TDCR_SVS_Pos)               /*!< 0x00000010 */
8031 #define DSI_TDCR_SVS                  DSI_TDCR_SVS_Msk                         /*!< Second VSYNC */
8032 #define DSI_TDCR_RF_Pos               (5U)
8033 #define DSI_TDCR_RF_Msk               (0x1UL << DSI_TDCR_RF_Pos)                /*!< 0x00000020 */
8034 #define DSI_TDCR_RF                   DSI_TDCR_RF_Msk                          /*!< Right First */
8035 #define DSI_TDCR_S3DC_Pos             (16U)
8036 #define DSI_TDCR_S3DC_Msk             (0x1UL << DSI_TDCR_S3DC_Pos)              /*!< 0x00010000 */
8037 #define DSI_TDCR_S3DC                 DSI_TDCR_S3DC_Msk                        /*!< Send 3D Control */
8038 
8039 /*******************  Bit definition for DSI_CLCR register  ***************/
8040 #define DSI_CLCR_DPCC_Pos             (0U)
8041 #define DSI_CLCR_DPCC_Msk             (0x1UL << DSI_CLCR_DPCC_Pos)              /*!< 0x00000001 */
8042 #define DSI_CLCR_DPCC                 DSI_CLCR_DPCC_Msk                        /*!< D-PHY Clock Control */
8043 #define DSI_CLCR_ACR_Pos              (1U)
8044 #define DSI_CLCR_ACR_Msk              (0x1UL << DSI_CLCR_ACR_Pos)               /*!< 0x00000002 */
8045 #define DSI_CLCR_ACR                  DSI_CLCR_ACR_Msk                         /*!< Automatic Clocklane Control */
8046 
8047 /*******************  Bit definition for DSI_CLTCR register  **************/
8048 #define DSI_CLTCR_LP2HS_TIME_Pos      (0U)
8049 #define DSI_CLTCR_LP2HS_TIME_Msk      (0x3FFUL << DSI_CLTCR_LP2HS_TIME_Pos)     /*!< 0x000003FF */
8050 #define DSI_CLTCR_LP2HS_TIME          DSI_CLTCR_LP2HS_TIME_Msk                 /*!< Low-Power to High-Speed Time */
8051 #define DSI_CLTCR_LP2HS_TIME0_Pos     (0U)
8052 #define DSI_CLTCR_LP2HS_TIME0_Msk     (0x1UL << DSI_CLTCR_LP2HS_TIME0_Pos)      /*!< 0x00000001 */
8053 #define DSI_CLTCR_LP2HS_TIME0         DSI_CLTCR_LP2HS_TIME0_Msk
8054 #define DSI_CLTCR_LP2HS_TIME1_Pos     (1U)
8055 #define DSI_CLTCR_LP2HS_TIME1_Msk     (0x1UL << DSI_CLTCR_LP2HS_TIME1_Pos)      /*!< 0x00000002 */
8056 #define DSI_CLTCR_LP2HS_TIME1         DSI_CLTCR_LP2HS_TIME1_Msk
8057 #define DSI_CLTCR_LP2HS_TIME2_Pos     (2U)
8058 #define DSI_CLTCR_LP2HS_TIME2_Msk     (0x1UL << DSI_CLTCR_LP2HS_TIME2_Pos)      /*!< 0x00000004 */
8059 #define DSI_CLTCR_LP2HS_TIME2         DSI_CLTCR_LP2HS_TIME2_Msk
8060 #define DSI_CLTCR_LP2HS_TIME3_Pos     (3U)
8061 #define DSI_CLTCR_LP2HS_TIME3_Msk     (0x1UL << DSI_CLTCR_LP2HS_TIME3_Pos)      /*!< 0x00000008 */
8062 #define DSI_CLTCR_LP2HS_TIME3         DSI_CLTCR_LP2HS_TIME3_Msk
8063 #define DSI_CLTCR_LP2HS_TIME4_Pos     (4U)
8064 #define DSI_CLTCR_LP2HS_TIME4_Msk     (0x1UL << DSI_CLTCR_LP2HS_TIME4_Pos)      /*!< 0x00000010 */
8065 #define DSI_CLTCR_LP2HS_TIME4         DSI_CLTCR_LP2HS_TIME4_Msk
8066 #define DSI_CLTCR_LP2HS_TIME5_Pos     (5U)
8067 #define DSI_CLTCR_LP2HS_TIME5_Msk     (0x1UL << DSI_CLTCR_LP2HS_TIME5_Pos)      /*!< 0x00000020 */
8068 #define DSI_CLTCR_LP2HS_TIME5         DSI_CLTCR_LP2HS_TIME5_Msk
8069 #define DSI_CLTCR_LP2HS_TIME6_Pos     (6U)
8070 #define DSI_CLTCR_LP2HS_TIME6_Msk     (0x1UL << DSI_CLTCR_LP2HS_TIME6_Pos)      /*!< 0x00000040 */
8071 #define DSI_CLTCR_LP2HS_TIME6         DSI_CLTCR_LP2HS_TIME6_Msk
8072 #define DSI_CLTCR_LP2HS_TIME7_Pos     (7U)
8073 #define DSI_CLTCR_LP2HS_TIME7_Msk     (0x1UL << DSI_CLTCR_LP2HS_TIME7_Pos)      /*!< 0x00000080 */
8074 #define DSI_CLTCR_LP2HS_TIME7         DSI_CLTCR_LP2HS_TIME7_Msk
8075 #define DSI_CLTCR_LP2HS_TIME8_Pos     (8U)
8076 #define DSI_CLTCR_LP2HS_TIME8_Msk     (0x1UL << DSI_CLTCR_LP2HS_TIME8_Pos)      /*!< 0x00000100 */
8077 #define DSI_CLTCR_LP2HS_TIME8         DSI_CLTCR_LP2HS_TIME8_Msk
8078 #define DSI_CLTCR_LP2HS_TIME9_Pos     (9U)
8079 #define DSI_CLTCR_LP2HS_TIME9_Msk     (0x1UL << DSI_CLTCR_LP2HS_TIME9_Pos)      /*!< 0x00000200 */
8080 #define DSI_CLTCR_LP2HS_TIME9         DSI_CLTCR_LP2HS_TIME9_Msk
8081 
8082 #define DSI_CLTCR_HS2LP_TIME_Pos      (16U)
8083 #define DSI_CLTCR_HS2LP_TIME_Msk      (0x3FFUL << DSI_CLTCR_HS2LP_TIME_Pos)     /*!< 0x03FF0000 */
8084 #define DSI_CLTCR_HS2LP_TIME          DSI_CLTCR_HS2LP_TIME_Msk                 /*!< High-Speed to Low-Power Time */
8085 #define DSI_CLTCR_HS2LP_TIME0_Pos     (16U)
8086 #define DSI_CLTCR_HS2LP_TIME0_Msk     (0x1UL << DSI_CLTCR_HS2LP_TIME0_Pos)      /*!< 0x00010000 */
8087 #define DSI_CLTCR_HS2LP_TIME0         DSI_CLTCR_HS2LP_TIME0_Msk
8088 #define DSI_CLTCR_HS2LP_TIME1_Pos     (17U)
8089 #define DSI_CLTCR_HS2LP_TIME1_Msk     (0x1UL << DSI_CLTCR_HS2LP_TIME1_Pos)      /*!< 0x00020000 */
8090 #define DSI_CLTCR_HS2LP_TIME1         DSI_CLTCR_HS2LP_TIME1_Msk
8091 #define DSI_CLTCR_HS2LP_TIME2_Pos     (18U)
8092 #define DSI_CLTCR_HS2LP_TIME2_Msk     (0x1UL << DSI_CLTCR_HS2LP_TIME2_Pos)      /*!< 0x00040000 */
8093 #define DSI_CLTCR_HS2LP_TIME2         DSI_CLTCR_HS2LP_TIME2_Msk
8094 #define DSI_CLTCR_HS2LP_TIME3_Pos     (19U)
8095 #define DSI_CLTCR_HS2LP_TIME3_Msk     (0x1UL << DSI_CLTCR_HS2LP_TIME3_Pos)      /*!< 0x00080000 */
8096 #define DSI_CLTCR_HS2LP_TIME3         DSI_CLTCR_HS2LP_TIME3_Msk
8097 #define DSI_CLTCR_HS2LP_TIME4_Pos     (20U)
8098 #define DSI_CLTCR_HS2LP_TIME4_Msk     (0x1UL << DSI_CLTCR_HS2LP_TIME4_Pos)      /*!< 0x00100000 */
8099 #define DSI_CLTCR_HS2LP_TIME4         DSI_CLTCR_HS2LP_TIME4_Msk
8100 #define DSI_CLTCR_HS2LP_TIME5_Pos     (21U)
8101 #define DSI_CLTCR_HS2LP_TIME5_Msk     (0x1UL << DSI_CLTCR_HS2LP_TIME5_Pos)      /*!< 0x00200000 */
8102 #define DSI_CLTCR_HS2LP_TIME5         DSI_CLTCR_HS2LP_TIME5_Msk
8103 #define DSI_CLTCR_HS2LP_TIME6_Pos     (22U)
8104 #define DSI_CLTCR_HS2LP_TIME6_Msk     (0x1UL << DSI_CLTCR_HS2LP_TIME6_Pos)      /*!< 0x00400000 */
8105 #define DSI_CLTCR_HS2LP_TIME6         DSI_CLTCR_HS2LP_TIME6_Msk
8106 #define DSI_CLTCR_HS2LP_TIME7_Pos     (23U)
8107 #define DSI_CLTCR_HS2LP_TIME7_Msk     (0x1UL << DSI_CLTCR_HS2LP_TIME7_Pos)      /*!< 0x00800000 */
8108 #define DSI_CLTCR_HS2LP_TIME7         DSI_CLTCR_HS2LP_TIME7_Msk
8109 #define DSI_CLTCR_HS2LP_TIME8_Pos     (24U)
8110 #define DSI_CLTCR_HS2LP_TIME8_Msk     (0x1UL << DSI_CLTCR_HS2LP_TIME8_Pos)      /*!< 0x01000000 */
8111 #define DSI_CLTCR_HS2LP_TIME8         DSI_CLTCR_HS2LP_TIME8_Msk
8112 #define DSI_CLTCR_HS2LP_TIME9_Pos     (25U)
8113 #define DSI_CLTCR_HS2LP_TIME9_Msk     (0x1UL << DSI_CLTCR_HS2LP_TIME9_Pos)      /*!< 0x02000000 */
8114 #define DSI_CLTCR_HS2LP_TIME9         DSI_CLTCR_HS2LP_TIME9_Msk
8115 
8116 /*******************  Bit definition for DSI_DLTCR register  **************/
8117 #define DSI_DLTCR_MRD_TIME_Pos        (0U)
8118 #define DSI_DLTCR_MRD_TIME_Msk        (0x7FFFUL << DSI_DLTCR_MRD_TIME_Pos)      /*!< 0x00007FFF */
8119 #define DSI_DLTCR_MRD_TIME            DSI_DLTCR_MRD_TIME_Msk                   /*!< Maximum Read Time */
8120 #define DSI_DLTCR_MRD_TIME0_Pos       (0U)
8121 #define DSI_DLTCR_MRD_TIME0_Msk       (0x1UL << DSI_DLTCR_MRD_TIME0_Pos)        /*!< 0x00000001 */
8122 #define DSI_DLTCR_MRD_TIME0           DSI_DLTCR_MRD_TIME0_Msk
8123 #define DSI_DLTCR_MRD_TIME1_Pos       (1U)
8124 #define DSI_DLTCR_MRD_TIME1_Msk       (0x1UL << DSI_DLTCR_MRD_TIME1_Pos)        /*!< 0x00000002 */
8125 #define DSI_DLTCR_MRD_TIME1           DSI_DLTCR_MRD_TIME1_Msk
8126 #define DSI_DLTCR_MRD_TIME2_Pos       (2U)
8127 #define DSI_DLTCR_MRD_TIME2_Msk       (0x1UL << DSI_DLTCR_MRD_TIME2_Pos)        /*!< 0x00000004 */
8128 #define DSI_DLTCR_MRD_TIME2           DSI_DLTCR_MRD_TIME2_Msk
8129 #define DSI_DLTCR_MRD_TIME3_Pos       (3U)
8130 #define DSI_DLTCR_MRD_TIME3_Msk       (0x1UL << DSI_DLTCR_MRD_TIME3_Pos)        /*!< 0x00000008 */
8131 #define DSI_DLTCR_MRD_TIME3           DSI_DLTCR_MRD_TIME3_Msk
8132 #define DSI_DLTCR_MRD_TIME4_Pos       (4U)
8133 #define DSI_DLTCR_MRD_TIME4_Msk       (0x1UL << DSI_DLTCR_MRD_TIME4_Pos)        /*!< 0x00000010 */
8134 #define DSI_DLTCR_MRD_TIME4           DSI_DLTCR_MRD_TIME4_Msk
8135 #define DSI_DLTCR_MRD_TIME5_Pos       (5U)
8136 #define DSI_DLTCR_MRD_TIME5_Msk       (0x1UL << DSI_DLTCR_MRD_TIME5_Pos)        /*!< 0x00000020 */
8137 #define DSI_DLTCR_MRD_TIME5           DSI_DLTCR_MRD_TIME5_Msk
8138 #define DSI_DLTCR_MRD_TIME6_Pos       (6U)
8139 #define DSI_DLTCR_MRD_TIME6_Msk       (0x1UL << DSI_DLTCR_MRD_TIME6_Pos)        /*!< 0x00000040 */
8140 #define DSI_DLTCR_MRD_TIME6           DSI_DLTCR_MRD_TIME6_Msk
8141 #define DSI_DLTCR_MRD_TIME7_Pos       (7U)
8142 #define DSI_DLTCR_MRD_TIME7_Msk       (0x1UL << DSI_DLTCR_MRD_TIME7_Pos)        /*!< 0x00000080 */
8143 #define DSI_DLTCR_MRD_TIME7           DSI_DLTCR_MRD_TIME7_Msk
8144 #define DSI_DLTCR_MRD_TIME8_Pos       (8U)
8145 #define DSI_DLTCR_MRD_TIME8_Msk       (0x1UL << DSI_DLTCR_MRD_TIME8_Pos)        /*!< 0x00000100 */
8146 #define DSI_DLTCR_MRD_TIME8           DSI_DLTCR_MRD_TIME8_Msk
8147 #define DSI_DLTCR_MRD_TIME9_Pos       (9U)
8148 #define DSI_DLTCR_MRD_TIME9_Msk       (0x1UL << DSI_DLTCR_MRD_TIME9_Pos)        /*!< 0x00000200 */
8149 #define DSI_DLTCR_MRD_TIME9           DSI_DLTCR_MRD_TIME9_Msk
8150 #define DSI_DLTCR_MRD_TIME10_Pos      (10U)
8151 #define DSI_DLTCR_MRD_TIME10_Msk      (0x1UL << DSI_DLTCR_MRD_TIME10_Pos)       /*!< 0x00000400 */
8152 #define DSI_DLTCR_MRD_TIME10          DSI_DLTCR_MRD_TIME10_Msk
8153 #define DSI_DLTCR_MRD_TIME11_Pos      (11U)
8154 #define DSI_DLTCR_MRD_TIME11_Msk      (0x1UL << DSI_DLTCR_MRD_TIME11_Pos)       /*!< 0x00000800 */
8155 #define DSI_DLTCR_MRD_TIME11          DSI_DLTCR_MRD_TIME11_Msk
8156 #define DSI_DLTCR_MRD_TIME12_Pos      (12U)
8157 #define DSI_DLTCR_MRD_TIME12_Msk      (0x1UL << DSI_DLTCR_MRD_TIME12_Pos)       /*!< 0x00001000 */
8158 #define DSI_DLTCR_MRD_TIME12          DSI_DLTCR_MRD_TIME12_Msk
8159 #define DSI_DLTCR_MRD_TIME13_Pos      (13U)
8160 #define DSI_DLTCR_MRD_TIME13_Msk      (0x1UL << DSI_DLTCR_MRD_TIME13_Pos)       /*!< 0x00002000 */
8161 #define DSI_DLTCR_MRD_TIME13          DSI_DLTCR_MRD_TIME13_Msk
8162 #define DSI_DLTCR_MRD_TIME14_Pos      (14U)
8163 #define DSI_DLTCR_MRD_TIME14_Msk      (0x1UL << DSI_DLTCR_MRD_TIME14_Pos)       /*!< 0x00004000 */
8164 #define DSI_DLTCR_MRD_TIME14          DSI_DLTCR_MRD_TIME14_Msk
8165 
8166 #define DSI_DLTCR_LP2HS_TIME_Pos      (16U)
8167 #define DSI_DLTCR_LP2HS_TIME_Msk      (0xFFUL << DSI_DLTCR_LP2HS_TIME_Pos)      /*!< 0x00FF0000 */
8168 #define DSI_DLTCR_LP2HS_TIME          DSI_DLTCR_LP2HS_TIME_Msk                 /*!< Low-Power To High-Speed Time */
8169 #define DSI_DLTCR_LP2HS_TIME0_Pos     (16U)
8170 #define DSI_DLTCR_LP2HS_TIME0_Msk     (0x1UL << DSI_DLTCR_LP2HS_TIME0_Pos)      /*!< 0x00010000 */
8171 #define DSI_DLTCR_LP2HS_TIME0         DSI_DLTCR_LP2HS_TIME0_Msk
8172 #define DSI_DLTCR_LP2HS_TIME1_Pos     (17U)
8173 #define DSI_DLTCR_LP2HS_TIME1_Msk     (0x1UL << DSI_DLTCR_LP2HS_TIME1_Pos)      /*!< 0x00020000 */
8174 #define DSI_DLTCR_LP2HS_TIME1         DSI_DLTCR_LP2HS_TIME1_Msk
8175 #define DSI_DLTCR_LP2HS_TIME2_Pos     (18U)
8176 #define DSI_DLTCR_LP2HS_TIME2_Msk     (0x1UL << DSI_DLTCR_LP2HS_TIME2_Pos)      /*!< 0x00040000 */
8177 #define DSI_DLTCR_LP2HS_TIME2         DSI_DLTCR_LP2HS_TIME2_Msk
8178 #define DSI_DLTCR_LP2HS_TIME3_Pos     (19U)
8179 #define DSI_DLTCR_LP2HS_TIME3_Msk     (0x1UL << DSI_DLTCR_LP2HS_TIME3_Pos)      /*!< 0x00080000 */
8180 #define DSI_DLTCR_LP2HS_TIME3         DSI_DLTCR_LP2HS_TIME3_Msk
8181 #define DSI_DLTCR_LP2HS_TIME4_Pos     (20U)
8182 #define DSI_DLTCR_LP2HS_TIME4_Msk     (0x1UL << DSI_DLTCR_LP2HS_TIME4_Pos)      /*!< 0x00100000 */
8183 #define DSI_DLTCR_LP2HS_TIME4         DSI_DLTCR_LP2HS_TIME4_Msk
8184 #define DSI_DLTCR_LP2HS_TIME5_Pos     (21U)
8185 #define DSI_DLTCR_LP2HS_TIME5_Msk     (0x1UL << DSI_DLTCR_LP2HS_TIME5_Pos)      /*!< 0x00200000 */
8186 #define DSI_DLTCR_LP2HS_TIME5         DSI_DLTCR_LP2HS_TIME5_Msk
8187 #define DSI_DLTCR_LP2HS_TIME6_Pos     (22U)
8188 #define DSI_DLTCR_LP2HS_TIME6_Msk     (0x1UL << DSI_DLTCR_LP2HS_TIME6_Pos)      /*!< 0x00400000 */
8189 #define DSI_DLTCR_LP2HS_TIME6         DSI_DLTCR_LP2HS_TIME6_Msk
8190 #define DSI_DLTCR_LP2HS_TIME7_Pos     (23U)
8191 #define DSI_DLTCR_LP2HS_TIME7_Msk     (0x1UL << DSI_DLTCR_LP2HS_TIME7_Pos)      /*!< 0x00800000 */
8192 #define DSI_DLTCR_LP2HS_TIME7         DSI_DLTCR_LP2HS_TIME7_Msk
8193 
8194 #define DSI_DLTCR_HS2LP_TIME_Pos      (24U)
8195 #define DSI_DLTCR_HS2LP_TIME_Msk      (0xFFUL << DSI_DLTCR_HS2LP_TIME_Pos)      /*!< 0xFF000000 */
8196 #define DSI_DLTCR_HS2LP_TIME          DSI_DLTCR_HS2LP_TIME_Msk                 /*!< High-Speed To Low-Power Time */
8197 #define DSI_DLTCR_HS2LP_TIME0_Pos     (24U)
8198 #define DSI_DLTCR_HS2LP_TIME0_Msk     (0x1UL << DSI_DLTCR_HS2LP_TIME0_Pos)      /*!< 0x01000000 */
8199 #define DSI_DLTCR_HS2LP_TIME0         DSI_DLTCR_HS2LP_TIME0_Msk
8200 #define DSI_DLTCR_HS2LP_TIME1_Pos     (25U)
8201 #define DSI_DLTCR_HS2LP_TIME1_Msk     (0x1UL << DSI_DLTCR_HS2LP_TIME1_Pos)      /*!< 0x02000000 */
8202 #define DSI_DLTCR_HS2LP_TIME1         DSI_DLTCR_HS2LP_TIME1_Msk
8203 #define DSI_DLTCR_HS2LP_TIME2_Pos     (26U)
8204 #define DSI_DLTCR_HS2LP_TIME2_Msk     (0x1UL << DSI_DLTCR_HS2LP_TIME2_Pos)      /*!< 0x04000000 */
8205 #define DSI_DLTCR_HS2LP_TIME2         DSI_DLTCR_HS2LP_TIME2_Msk
8206 #define DSI_DLTCR_HS2LP_TIME3_Pos     (27U)
8207 #define DSI_DLTCR_HS2LP_TIME3_Msk     (0x1UL << DSI_DLTCR_HS2LP_TIME3_Pos)      /*!< 0x08000000 */
8208 #define DSI_DLTCR_HS2LP_TIME3         DSI_DLTCR_HS2LP_TIME3_Msk
8209 #define DSI_DLTCR_HS2LP_TIME4_Pos     (28U)
8210 #define DSI_DLTCR_HS2LP_TIME4_Msk     (0x1UL << DSI_DLTCR_HS2LP_TIME4_Pos)      /*!< 0x10000000 */
8211 #define DSI_DLTCR_HS2LP_TIME4         DSI_DLTCR_HS2LP_TIME4_Msk
8212 #define DSI_DLTCR_HS2LP_TIME5_Pos     (29U)
8213 #define DSI_DLTCR_HS2LP_TIME5_Msk     (0x1UL << DSI_DLTCR_HS2LP_TIME5_Pos)      /*!< 0x20000000 */
8214 #define DSI_DLTCR_HS2LP_TIME5         DSI_DLTCR_HS2LP_TIME5_Msk
8215 #define DSI_DLTCR_HS2LP_TIME6_Pos     (30U)
8216 #define DSI_DLTCR_HS2LP_TIME6_Msk     (0x1UL << DSI_DLTCR_HS2LP_TIME6_Pos)      /*!< 0x40000000 */
8217 #define DSI_DLTCR_HS2LP_TIME6         DSI_DLTCR_HS2LP_TIME6_Msk
8218 #define DSI_DLTCR_HS2LP_TIME7_Pos     (31U)
8219 #define DSI_DLTCR_HS2LP_TIME7_Msk     (0x1UL << DSI_DLTCR_HS2LP_TIME7_Pos)      /*!< 0x80000000 */
8220 #define DSI_DLTCR_HS2LP_TIME7         DSI_DLTCR_HS2LP_TIME7_Msk
8221 
8222 /*******************  Bit definition for DSI_PCTLR register  **************/
8223 #define DSI_PCTLR_DEN_Pos             (1U)
8224 #define DSI_PCTLR_DEN_Msk             (0x1UL << DSI_PCTLR_DEN_Pos)              /*!< 0x00000002 */
8225 #define DSI_PCTLR_DEN                 DSI_PCTLR_DEN_Msk                        /*!< Digital Enable */
8226 #define DSI_PCTLR_CKE_Pos             (2U)
8227 #define DSI_PCTLR_CKE_Msk             (0x1UL << DSI_PCTLR_CKE_Pos)              /*!< 0x00000004 */
8228 #define DSI_PCTLR_CKE                 DSI_PCTLR_CKE_Msk                        /*!< Clock Enable */
8229 
8230 /*******************  Bit definition for DSI_PCONFR register  *************/
8231 #define DSI_PCONFR_NL_Pos             (0U)
8232 #define DSI_PCONFR_NL_Msk             (0x3UL << DSI_PCONFR_NL_Pos)              /*!< 0x00000003 */
8233 #define DSI_PCONFR_NL                 DSI_PCONFR_NL_Msk                        /*!< Number of Lanes */
8234 #define DSI_PCONFR_NL0_Pos            (0U)
8235 #define DSI_PCONFR_NL0_Msk            (0x1UL << DSI_PCONFR_NL0_Pos)             /*!< 0x00000001 */
8236 #define DSI_PCONFR_NL0                DSI_PCONFR_NL0_Msk
8237 #define DSI_PCONFR_NL1_Pos            (1U)
8238 #define DSI_PCONFR_NL1_Msk            (0x1UL << DSI_PCONFR_NL1_Pos)             /*!< 0x00000002 */
8239 #define DSI_PCONFR_NL1                DSI_PCONFR_NL1_Msk
8240 
8241 #define DSI_PCONFR_SW_TIME_Pos        (8U)
8242 #define DSI_PCONFR_SW_TIME_Msk        (0xFFUL << DSI_PCONFR_SW_TIME_Pos)        /*!< 0x0000FF00 */
8243 #define DSI_PCONFR_SW_TIME            DSI_PCONFR_SW_TIME_Msk                   /*!< Stop Wait Time */
8244 #define DSI_PCONFR_SW_TIME0_Pos       (8U)
8245 #define DSI_PCONFR_SW_TIME0_Msk       (0x1UL << DSI_PCONFR_SW_TIME0_Pos)        /*!< 0x00000100 */
8246 #define DSI_PCONFR_SW_TIME0           DSI_PCONFR_SW_TIME0_Msk
8247 #define DSI_PCONFR_SW_TIME1_Pos       (9U)
8248 #define DSI_PCONFR_SW_TIME1_Msk       (0x1UL << DSI_PCONFR_SW_TIME1_Pos)        /*!< 0x00000200 */
8249 #define DSI_PCONFR_SW_TIME1           DSI_PCONFR_SW_TIME1_Msk
8250 #define DSI_PCONFR_SW_TIME2_Pos       (10U)
8251 #define DSI_PCONFR_SW_TIME2_Msk       (0x1UL << DSI_PCONFR_SW_TIME2_Pos)        /*!< 0x00000400 */
8252 #define DSI_PCONFR_SW_TIME2           DSI_PCONFR_SW_TIME2_Msk
8253 #define DSI_PCONFR_SW_TIME3_Pos       (11U)
8254 #define DSI_PCONFR_SW_TIME3_Msk       (0x1UL << DSI_PCONFR_SW_TIME3_Pos)        /*!< 0x00000800 */
8255 #define DSI_PCONFR_SW_TIME3           DSI_PCONFR_SW_TIME3_Msk
8256 #define DSI_PCONFR_SW_TIME4_Pos       (12U)
8257 #define DSI_PCONFR_SW_TIME4_Msk       (0x1UL << DSI_PCONFR_SW_TIME4_Pos)        /*!< 0x00001000 */
8258 #define DSI_PCONFR_SW_TIME4           DSI_PCONFR_SW_TIME4_Msk
8259 #define DSI_PCONFR_SW_TIME5_Pos       (13U)
8260 #define DSI_PCONFR_SW_TIME5_Msk       (0x1UL << DSI_PCONFR_SW_TIME5_Pos)        /*!< 0x00002000 */
8261 #define DSI_PCONFR_SW_TIME5           DSI_PCONFR_SW_TIME5_Msk
8262 #define DSI_PCONFR_SW_TIME6_Pos       (14U)
8263 #define DSI_PCONFR_SW_TIME6_Msk       (0x1UL << DSI_PCONFR_SW_TIME6_Pos)        /*!< 0x00004000 */
8264 #define DSI_PCONFR_SW_TIME6           DSI_PCONFR_SW_TIME6_Msk
8265 #define DSI_PCONFR_SW_TIME7_Pos       (15U)
8266 #define DSI_PCONFR_SW_TIME7_Msk       (0x1UL << DSI_PCONFR_SW_TIME7_Pos)        /*!< 0x00008000 */
8267 #define DSI_PCONFR_SW_TIME7           DSI_PCONFR_SW_TIME7_Msk
8268 
8269 /*******************  Bit definition for DSI_PUCR register  ***************/
8270 #define DSI_PUCR_URCL_Pos             (0U)
8271 #define DSI_PUCR_URCL_Msk             (0x1UL << DSI_PUCR_URCL_Pos)              /*!< 0x00000001 */
8272 #define DSI_PUCR_URCL                 DSI_PUCR_URCL_Msk                        /*!< ULPS Request on Clock Lane */
8273 #define DSI_PUCR_UECL_Pos             (1U)
8274 #define DSI_PUCR_UECL_Msk             (0x1UL << DSI_PUCR_UECL_Pos)              /*!< 0x00000002 */
8275 #define DSI_PUCR_UECL                 DSI_PUCR_UECL_Msk                        /*!< ULPS Exit on Clock Lane */
8276 #define DSI_PUCR_URDL_Pos             (2U)
8277 #define DSI_PUCR_URDL_Msk             (0x1UL << DSI_PUCR_URDL_Pos)              /*!< 0x00000004 */
8278 #define DSI_PUCR_URDL                 DSI_PUCR_URDL_Msk                        /*!< ULPS Request on Data Lane */
8279 #define DSI_PUCR_UEDL_Pos             (3U)
8280 #define DSI_PUCR_UEDL_Msk             (0x1UL << DSI_PUCR_UEDL_Pos)              /*!< 0x00000008 */
8281 #define DSI_PUCR_UEDL                 DSI_PUCR_UEDL_Msk                        /*!< ULPS Exit on Data Lane */
8282 
8283 /*******************  Bit definition for DSI_PTTCR register  **************/
8284 #define DSI_PTTCR_TX_TRIG_Pos         (0U)
8285 #define DSI_PTTCR_TX_TRIG_Msk         (0xFUL << DSI_PTTCR_TX_TRIG_Pos)          /*!< 0x0000000F */
8286 #define DSI_PTTCR_TX_TRIG             DSI_PTTCR_TX_TRIG_Msk                    /*!< Transmission Trigger */
8287 #define DSI_PTTCR_TX_TRIG0_Pos        (0U)
8288 #define DSI_PTTCR_TX_TRIG0_Msk        (0x1UL << DSI_PTTCR_TX_TRIG0_Pos)         /*!< 0x00000001 */
8289 #define DSI_PTTCR_TX_TRIG0            DSI_PTTCR_TX_TRIG0_Msk
8290 #define DSI_PTTCR_TX_TRIG1_Pos        (1U)
8291 #define DSI_PTTCR_TX_TRIG1_Msk        (0x1UL << DSI_PTTCR_TX_TRIG1_Pos)         /*!< 0x00000002 */
8292 #define DSI_PTTCR_TX_TRIG1            DSI_PTTCR_TX_TRIG1_Msk
8293 #define DSI_PTTCR_TX_TRIG2_Pos        (2U)
8294 #define DSI_PTTCR_TX_TRIG2_Msk        (0x1UL << DSI_PTTCR_TX_TRIG2_Pos)         /*!< 0x00000004 */
8295 #define DSI_PTTCR_TX_TRIG2            DSI_PTTCR_TX_TRIG2_Msk
8296 #define DSI_PTTCR_TX_TRIG3_Pos        (3U)
8297 #define DSI_PTTCR_TX_TRIG3_Msk        (0x1UL << DSI_PTTCR_TX_TRIG3_Pos)         /*!< 0x00000008 */
8298 #define DSI_PTTCR_TX_TRIG3            DSI_PTTCR_TX_TRIG3_Msk
8299 
8300 /*******************  Bit definition for DSI_PSR register  ****************/
8301 #define DSI_PSR_PD_Pos                (1U)
8302 #define DSI_PSR_PD_Msk                (0x1UL << DSI_PSR_PD_Pos)                 /*!< 0x00000002 */
8303 #define DSI_PSR_PD                    DSI_PSR_PD_Msk                           /*!< PHY Direction */
8304 #define DSI_PSR_PSSC_Pos              (2U)
8305 #define DSI_PSR_PSSC_Msk              (0x1UL << DSI_PSR_PSSC_Pos)               /*!< 0x00000004 */
8306 #define DSI_PSR_PSSC                  DSI_PSR_PSSC_Msk                         /*!< PHY Stop State Clock lane */
8307 #define DSI_PSR_UANC_Pos              (3U)
8308 #define DSI_PSR_UANC_Msk              (0x1UL << DSI_PSR_UANC_Pos)               /*!< 0x00000008 */
8309 #define DSI_PSR_UANC                  DSI_PSR_UANC_Msk                         /*!< ULPS Active Not Clock lane */
8310 #define DSI_PSR_PSS0_Pos              (4U)
8311 #define DSI_PSR_PSS0_Msk              (0x1UL << DSI_PSR_PSS0_Pos)               /*!< 0x00000010 */
8312 #define DSI_PSR_PSS0                  DSI_PSR_PSS0_Msk                         /*!< PHY Stop State lane 0 */
8313 #define DSI_PSR_UAN0_Pos              (5U)
8314 #define DSI_PSR_UAN0_Msk              (0x1UL << DSI_PSR_UAN0_Pos)               /*!< 0x00000020 */
8315 #define DSI_PSR_UAN0                  DSI_PSR_UAN0_Msk                         /*!< ULPS Active Not lane 0 */
8316 #define DSI_PSR_RUE0_Pos              (6U)
8317 #define DSI_PSR_RUE0_Msk              (0x1UL << DSI_PSR_RUE0_Pos)               /*!< 0x00000040 */
8318 #define DSI_PSR_RUE0                  DSI_PSR_RUE0_Msk                         /*!< RX ULPS Escape lane 0 */
8319 #define DSI_PSR_PSS1_Pos              (7U)
8320 #define DSI_PSR_PSS1_Msk              (0x1UL << DSI_PSR_PSS1_Pos)               /*!< 0x00000080 */
8321 #define DSI_PSR_PSS1                  DSI_PSR_PSS1_Msk                         /*!< PHY Stop State lane 1 */
8322 #define DSI_PSR_UAN1_Pos              (8U)
8323 #define DSI_PSR_UAN1_Msk              (0x1UL << DSI_PSR_UAN1_Pos)               /*!< 0x00000100 */
8324 #define DSI_PSR_UAN1                  DSI_PSR_UAN1_Msk                         /*!< ULPS Active Not lane 1 */
8325 
8326 /*******************  Bit definition for DSI_ISR0 register  ***************/
8327 #define DSI_ISR0_AE0_Pos              (0U)
8328 #define DSI_ISR0_AE0_Msk              (0x1UL << DSI_ISR0_AE0_Pos)               /*!< 0x00000001 */
8329 #define DSI_ISR0_AE0                  DSI_ISR0_AE0_Msk                         /*!< Acknowledge Error 0 */
8330 #define DSI_ISR0_AE1_Pos              (1U)
8331 #define DSI_ISR0_AE1_Msk              (0x1UL << DSI_ISR0_AE1_Pos)               /*!< 0x00000002 */
8332 #define DSI_ISR0_AE1                  DSI_ISR0_AE1_Msk                         /*!< Acknowledge Error 1 */
8333 #define DSI_ISR0_AE2_Pos              (2U)
8334 #define DSI_ISR0_AE2_Msk              (0x1UL << DSI_ISR0_AE2_Pos)               /*!< 0x00000004 */
8335 #define DSI_ISR0_AE2                  DSI_ISR0_AE2_Msk                         /*!< Acknowledge Error 2 */
8336 #define DSI_ISR0_AE3_Pos              (3U)
8337 #define DSI_ISR0_AE3_Msk              (0x1UL << DSI_ISR0_AE3_Pos)               /*!< 0x00000008 */
8338 #define DSI_ISR0_AE3                  DSI_ISR0_AE3_Msk                         /*!< Acknowledge Error 3 */
8339 #define DSI_ISR0_AE4_Pos              (4U)
8340 #define DSI_ISR0_AE4_Msk              (0x1UL << DSI_ISR0_AE4_Pos)               /*!< 0x00000010 */
8341 #define DSI_ISR0_AE4                  DSI_ISR0_AE4_Msk                         /*!< Acknowledge Error 4 */
8342 #define DSI_ISR0_AE5_Pos              (5U)
8343 #define DSI_ISR0_AE5_Msk              (0x1UL << DSI_ISR0_AE5_Pos)               /*!< 0x00000020 */
8344 #define DSI_ISR0_AE5                  DSI_ISR0_AE5_Msk                         /*!< Acknowledge Error 5 */
8345 #define DSI_ISR0_AE6_Pos              (6U)
8346 #define DSI_ISR0_AE6_Msk              (0x1UL << DSI_ISR0_AE6_Pos)               /*!< 0x00000040 */
8347 #define DSI_ISR0_AE6                  DSI_ISR0_AE6_Msk                         /*!< Acknowledge Error 6 */
8348 #define DSI_ISR0_AE7_Pos              (7U)
8349 #define DSI_ISR0_AE7_Msk              (0x1UL << DSI_ISR0_AE7_Pos)               /*!< 0x00000080 */
8350 #define DSI_ISR0_AE7                  DSI_ISR0_AE7_Msk                         /*!< Acknowledge Error 7 */
8351 #define DSI_ISR0_AE8_Pos              (8U)
8352 #define DSI_ISR0_AE8_Msk              (0x1UL << DSI_ISR0_AE8_Pos)               /*!< 0x00000100 */
8353 #define DSI_ISR0_AE8                  DSI_ISR0_AE8_Msk                         /*!< Acknowledge Error 8 */
8354 #define DSI_ISR0_AE9_Pos              (9U)
8355 #define DSI_ISR0_AE9_Msk              (0x1UL << DSI_ISR0_AE9_Pos)               /*!< 0x00000200 */
8356 #define DSI_ISR0_AE9                  DSI_ISR0_AE9_Msk                         /*!< Acknowledge Error 9 */
8357 #define DSI_ISR0_AE10_Pos             (10U)
8358 #define DSI_ISR0_AE10_Msk             (0x1UL << DSI_ISR0_AE10_Pos)              /*!< 0x00000400 */
8359 #define DSI_ISR0_AE10                 DSI_ISR0_AE10_Msk                        /*!< Acknowledge Error 10 */
8360 #define DSI_ISR0_AE11_Pos             (11U)
8361 #define DSI_ISR0_AE11_Msk             (0x1UL << DSI_ISR0_AE11_Pos)              /*!< 0x00000800 */
8362 #define DSI_ISR0_AE11                 DSI_ISR0_AE11_Msk                        /*!< Acknowledge Error 11 */
8363 #define DSI_ISR0_AE12_Pos             (12U)
8364 #define DSI_ISR0_AE12_Msk             (0x1UL << DSI_ISR0_AE12_Pos)              /*!< 0x00001000 */
8365 #define DSI_ISR0_AE12                 DSI_ISR0_AE12_Msk                        /*!< Acknowledge Error 12 */
8366 #define DSI_ISR0_AE13_Pos             (13U)
8367 #define DSI_ISR0_AE13_Msk             (0x1UL << DSI_ISR0_AE13_Pos)              /*!< 0x00002000 */
8368 #define DSI_ISR0_AE13                 DSI_ISR0_AE13_Msk                        /*!< Acknowledge Error 13 */
8369 #define DSI_ISR0_AE14_Pos             (14U)
8370 #define DSI_ISR0_AE14_Msk             (0x1UL << DSI_ISR0_AE14_Pos)              /*!< 0x00004000 */
8371 #define DSI_ISR0_AE14                 DSI_ISR0_AE14_Msk                        /*!< Acknowledge Error 14 */
8372 #define DSI_ISR0_AE15_Pos             (15U)
8373 #define DSI_ISR0_AE15_Msk             (0x1UL << DSI_ISR0_AE15_Pos)              /*!< 0x00008000 */
8374 #define DSI_ISR0_AE15                 DSI_ISR0_AE15_Msk                        /*!< Acknowledge Error 15 */
8375 #define DSI_ISR0_PE0_Pos              (16U)
8376 #define DSI_ISR0_PE0_Msk              (0x1UL << DSI_ISR0_PE0_Pos)               /*!< 0x00010000 */
8377 #define DSI_ISR0_PE0                  DSI_ISR0_PE0_Msk                         /*!< PHY Error 0 */
8378 #define DSI_ISR0_PE1_Pos              (17U)
8379 #define DSI_ISR0_PE1_Msk              (0x1UL << DSI_ISR0_PE1_Pos)               /*!< 0x00020000 */
8380 #define DSI_ISR0_PE1                  DSI_ISR0_PE1_Msk                         /*!< PHY Error 1 */
8381 #define DSI_ISR0_PE2_Pos              (18U)
8382 #define DSI_ISR0_PE2_Msk              (0x1UL << DSI_ISR0_PE2_Pos)               /*!< 0x00040000 */
8383 #define DSI_ISR0_PE2                  DSI_ISR0_PE2_Msk                         /*!< PHY Error 2 */
8384 #define DSI_ISR0_PE3_Pos              (19U)
8385 #define DSI_ISR0_PE3_Msk              (0x1UL << DSI_ISR0_PE3_Pos)               /*!< 0x00080000 */
8386 #define DSI_ISR0_PE3                  DSI_ISR0_PE3_Msk                         /*!< PHY Error 3 */
8387 #define DSI_ISR0_PE4_Pos              (20U)
8388 #define DSI_ISR0_PE4_Msk              (0x1UL << DSI_ISR0_PE4_Pos)               /*!< 0x00100000 */
8389 #define DSI_ISR0_PE4                  DSI_ISR0_PE4_Msk                         /*!< PHY Error 4 */
8390 
8391 /*******************  Bit definition for DSI_ISR1 register  ***************/
8392 #define DSI_ISR1_TOHSTX_Pos           (0U)
8393 #define DSI_ISR1_TOHSTX_Msk           (0x1UL << DSI_ISR1_TOHSTX_Pos)            /*!< 0x00000001 */
8394 #define DSI_ISR1_TOHSTX               DSI_ISR1_TOHSTX_Msk                      /*!< Timeout High-Speed Transmission */
8395 #define DSI_ISR1_TOLPRX_Pos           (1U)
8396 #define DSI_ISR1_TOLPRX_Msk           (0x1UL << DSI_ISR1_TOLPRX_Pos)            /*!< 0x00000002 */
8397 #define DSI_ISR1_TOLPRX               DSI_ISR1_TOLPRX_Msk                      /*!< Timeout Low-Power Reception */
8398 #define DSI_ISR1_ECCSE_Pos            (2U)
8399 #define DSI_ISR1_ECCSE_Msk            (0x1UL << DSI_ISR1_ECCSE_Pos)             /*!< 0x00000004 */
8400 #define DSI_ISR1_ECCSE                DSI_ISR1_ECCSE_Msk                       /*!< ECC Single-bit Error */
8401 #define DSI_ISR1_ECCME_Pos            (3U)
8402 #define DSI_ISR1_ECCME_Msk            (0x1UL << DSI_ISR1_ECCME_Pos)             /*!< 0x00000008 */
8403 #define DSI_ISR1_ECCME                DSI_ISR1_ECCME_Msk                       /*!< ECC Multi-bit Error */
8404 #define DSI_ISR1_CRCE_Pos             (4U)
8405 #define DSI_ISR1_CRCE_Msk             (0x1UL << DSI_ISR1_CRCE_Pos)              /*!< 0x00000010 */
8406 #define DSI_ISR1_CRCE                 DSI_ISR1_CRCE_Msk                        /*!< CRC Error */
8407 #define DSI_ISR1_PSE_Pos              (5U)
8408 #define DSI_ISR1_PSE_Msk              (0x1UL << DSI_ISR1_PSE_Pos)               /*!< 0x00000020 */
8409 #define DSI_ISR1_PSE                  DSI_ISR1_PSE_Msk                         /*!< Packet Size Error */
8410 #define DSI_ISR1_EOTPE_Pos            (6U)
8411 #define DSI_ISR1_EOTPE_Msk            (0x1UL << DSI_ISR1_EOTPE_Pos)             /*!< 0x00000040 */
8412 #define DSI_ISR1_EOTPE                DSI_ISR1_EOTPE_Msk                       /*!< EoTp Error */
8413 #define DSI_ISR1_LPWRE_Pos            (7U)
8414 #define DSI_ISR1_LPWRE_Msk            (0x1UL << DSI_ISR1_LPWRE_Pos)             /*!< 0x00000080 */
8415 #define DSI_ISR1_LPWRE                DSI_ISR1_LPWRE_Msk                       /*!< LTDC Payload Write Error */
8416 #define DSI_ISR1_GCWRE_Pos            (8U)
8417 #define DSI_ISR1_GCWRE_Msk            (0x1UL << DSI_ISR1_GCWRE_Pos)             /*!< 0x00000100 */
8418 #define DSI_ISR1_GCWRE                DSI_ISR1_GCWRE_Msk                       /*!< Generic Command Write Error */
8419 #define DSI_ISR1_GPWRE_Pos            (9U)
8420 #define DSI_ISR1_GPWRE_Msk            (0x1UL << DSI_ISR1_GPWRE_Pos)             /*!< 0x00000200 */
8421 #define DSI_ISR1_GPWRE                DSI_ISR1_GPWRE_Msk                       /*!< Generic Payload Write Error */
8422 #define DSI_ISR1_GPTXE_Pos            (10U)
8423 #define DSI_ISR1_GPTXE_Msk            (0x1UL << DSI_ISR1_GPTXE_Pos)             /*!< 0x00000400 */
8424 #define DSI_ISR1_GPTXE                DSI_ISR1_GPTXE_Msk                       /*!< Generic Payload Transmit Error */
8425 #define DSI_ISR1_GPRDE_Pos            (11U)
8426 #define DSI_ISR1_GPRDE_Msk            (0x1UL << DSI_ISR1_GPRDE_Pos)             /*!< 0x00000800 */
8427 #define DSI_ISR1_GPRDE                DSI_ISR1_GPRDE_Msk                       /*!< Generic Payload Read Error */
8428 #define DSI_ISR1_GPRXE_Pos            (12U)
8429 #define DSI_ISR1_GPRXE_Msk            (0x1UL << DSI_ISR1_GPRXE_Pos)             /*!< 0x00001000 */
8430 #define DSI_ISR1_GPRXE                DSI_ISR1_GPRXE_Msk                       /*!< Generic Payload Receive Error */
8431 
8432 /*******************  Bit definition for DSI_IER0 register  ***************/
8433 #define DSI_IER0_AE0IE_Pos            (0U)
8434 #define DSI_IER0_AE0IE_Msk            (0x1UL << DSI_IER0_AE0IE_Pos)             /*!< 0x00000001 */
8435 #define DSI_IER0_AE0IE                DSI_IER0_AE0IE_Msk                       /*!< Acknowledge Error 0 Interrupt Enable */
8436 #define DSI_IER0_AE1IE_Pos            (1U)
8437 #define DSI_IER0_AE1IE_Msk            (0x1UL << DSI_IER0_AE1IE_Pos)             /*!< 0x00000002 */
8438 #define DSI_IER0_AE1IE                DSI_IER0_AE1IE_Msk                       /*!< Acknowledge Error 1 Interrupt Enable */
8439 #define DSI_IER0_AE2IE_Pos            (2U)
8440 #define DSI_IER0_AE2IE_Msk            (0x1UL << DSI_IER0_AE2IE_Pos)             /*!< 0x00000004 */
8441 #define DSI_IER0_AE2IE                DSI_IER0_AE2IE_Msk                       /*!< Acknowledge Error 2 Interrupt Enable */
8442 #define DSI_IER0_AE3IE_Pos            (3U)
8443 #define DSI_IER0_AE3IE_Msk            (0x1UL << DSI_IER0_AE3IE_Pos)             /*!< 0x00000008 */
8444 #define DSI_IER0_AE3IE                DSI_IER0_AE3IE_Msk                       /*!< Acknowledge Error 3 Interrupt Enable */
8445 #define DSI_IER0_AE4IE_Pos            (4U)
8446 #define DSI_IER0_AE4IE_Msk            (0x1UL << DSI_IER0_AE4IE_Pos)             /*!< 0x00000010 */
8447 #define DSI_IER0_AE4IE                DSI_IER0_AE4IE_Msk                       /*!< Acknowledge Error 4 Interrupt Enable */
8448 #define DSI_IER0_AE5IE_Pos            (5U)
8449 #define DSI_IER0_AE5IE_Msk            (0x1UL << DSI_IER0_AE5IE_Pos)             /*!< 0x00000020 */
8450 #define DSI_IER0_AE5IE                DSI_IER0_AE5IE_Msk                       /*!< Acknowledge Error 5 Interrupt Enable */
8451 #define DSI_IER0_AE6IE_Pos            (6U)
8452 #define DSI_IER0_AE6IE_Msk            (0x1UL << DSI_IER0_AE6IE_Pos)             /*!< 0x00000040 */
8453 #define DSI_IER0_AE6IE                DSI_IER0_AE6IE_Msk                       /*!< Acknowledge Error 6 Interrupt Enable */
8454 #define DSI_IER0_AE7IE_Pos            (7U)
8455 #define DSI_IER0_AE7IE_Msk            (0x1UL << DSI_IER0_AE7IE_Pos)             /*!< 0x00000080 */
8456 #define DSI_IER0_AE7IE                DSI_IER0_AE7IE_Msk                       /*!< Acknowledge Error 7 Interrupt Enable */
8457 #define DSI_IER0_AE8IE_Pos            (8U)
8458 #define DSI_IER0_AE8IE_Msk            (0x1UL << DSI_IER0_AE8IE_Pos)             /*!< 0x00000100 */
8459 #define DSI_IER0_AE8IE                DSI_IER0_AE8IE_Msk                       /*!< Acknowledge Error 8 Interrupt Enable */
8460 #define DSI_IER0_AE9IE_Pos            (9U)
8461 #define DSI_IER0_AE9IE_Msk            (0x1UL << DSI_IER0_AE9IE_Pos)             /*!< 0x00000200 */
8462 #define DSI_IER0_AE9IE                DSI_IER0_AE9IE_Msk                       /*!< Acknowledge Error 9 Interrupt Enable */
8463 #define DSI_IER0_AE10IE_Pos           (10U)
8464 #define DSI_IER0_AE10IE_Msk           (0x1UL << DSI_IER0_AE10IE_Pos)            /*!< 0x00000400 */
8465 #define DSI_IER0_AE10IE               DSI_IER0_AE10IE_Msk                      /*!< Acknowledge Error 10 Interrupt Enable */
8466 #define DSI_IER0_AE11IE_Pos           (11U)
8467 #define DSI_IER0_AE11IE_Msk           (0x1UL << DSI_IER0_AE11IE_Pos)            /*!< 0x00000800 */
8468 #define DSI_IER0_AE11IE               DSI_IER0_AE11IE_Msk                      /*!< Acknowledge Error 11 Interrupt Enable */
8469 #define DSI_IER0_AE12IE_Pos           (12U)
8470 #define DSI_IER0_AE12IE_Msk           (0x1UL << DSI_IER0_AE12IE_Pos)            /*!< 0x00001000 */
8471 #define DSI_IER0_AE12IE               DSI_IER0_AE12IE_Msk                      /*!< Acknowledge Error 12 Interrupt Enable */
8472 #define DSI_IER0_AE13IE_Pos           (13U)
8473 #define DSI_IER0_AE13IE_Msk           (0x1UL << DSI_IER0_AE13IE_Pos)            /*!< 0x00002000 */
8474 #define DSI_IER0_AE13IE               DSI_IER0_AE13IE_Msk                      /*!< Acknowledge Error 13 Interrupt Enable */
8475 #define DSI_IER0_AE14IE_Pos           (14U)
8476 #define DSI_IER0_AE14IE_Msk           (0x1UL << DSI_IER0_AE14IE_Pos)            /*!< 0x00004000 */
8477 #define DSI_IER0_AE14IE               DSI_IER0_AE14IE_Msk                      /*!< Acknowledge Error 14 Interrupt Enable */
8478 #define DSI_IER0_AE15IE_Pos           (15U)
8479 #define DSI_IER0_AE15IE_Msk           (0x1UL << DSI_IER0_AE15IE_Pos)            /*!< 0x00008000 */
8480 #define DSI_IER0_AE15IE               DSI_IER0_AE15IE_Msk                      /*!< Acknowledge Error 15 Interrupt Enable */
8481 #define DSI_IER0_PE0IE_Pos            (16U)
8482 #define DSI_IER0_PE0IE_Msk            (0x1UL << DSI_IER0_PE0IE_Pos)             /*!< 0x00010000 */
8483 #define DSI_IER0_PE0IE                DSI_IER0_PE0IE_Msk                       /*!< PHY Error 0 Interrupt Enable */
8484 #define DSI_IER0_PE1IE_Pos            (17U)
8485 #define DSI_IER0_PE1IE_Msk            (0x1UL << DSI_IER0_PE1IE_Pos)             /*!< 0x00020000 */
8486 #define DSI_IER0_PE1IE                DSI_IER0_PE1IE_Msk                       /*!< PHY Error 1 Interrupt Enable */
8487 #define DSI_IER0_PE2IE_Pos            (18U)
8488 #define DSI_IER0_PE2IE_Msk            (0x1UL << DSI_IER0_PE2IE_Pos)             /*!< 0x00040000 */
8489 #define DSI_IER0_PE2IE                DSI_IER0_PE2IE_Msk                       /*!< PHY Error 2 Interrupt Enable */
8490 #define DSI_IER0_PE3IE_Pos            (19U)
8491 #define DSI_IER0_PE3IE_Msk            (0x1UL << DSI_IER0_PE3IE_Pos)             /*!< 0x00080000 */
8492 #define DSI_IER0_PE3IE                DSI_IER0_PE3IE_Msk                       /*!< PHY Error 3 Interrupt Enable */
8493 #define DSI_IER0_PE4IE_Pos            (20U)
8494 #define DSI_IER0_PE4IE_Msk            (0x1UL << DSI_IER0_PE4IE_Pos)             /*!< 0x00100000 */
8495 #define DSI_IER0_PE4IE                DSI_IER0_PE4IE_Msk                       /*!< PHY Error 4 Interrupt Enable */
8496 
8497 /*******************  Bit definition for DSI_IER1 register  ***************/
8498 #define DSI_IER1_TOHSTXIE_Pos         (0U)
8499 #define DSI_IER1_TOHSTXIE_Msk         (0x1UL << DSI_IER1_TOHSTXIE_Pos)          /*!< 0x00000001 */
8500 #define DSI_IER1_TOHSTXIE             DSI_IER1_TOHSTXIE_Msk                    /*!< Timeout High-Speed Transmission Interrupt Enable */
8501 #define DSI_IER1_TOLPRXIE_Pos         (1U)
8502 #define DSI_IER1_TOLPRXIE_Msk         (0x1UL << DSI_IER1_TOLPRXIE_Pos)          /*!< 0x00000002 */
8503 #define DSI_IER1_TOLPRXIE             DSI_IER1_TOLPRXIE_Msk                    /*!< Timeout Low-Power Reception Interrupt Enable */
8504 #define DSI_IER1_ECCSEIE_Pos          (2U)
8505 #define DSI_IER1_ECCSEIE_Msk          (0x1UL << DSI_IER1_ECCSEIE_Pos)           /*!< 0x00000004 */
8506 #define DSI_IER1_ECCSEIE              DSI_IER1_ECCSEIE_Msk                     /*!< ECC Single-bit Error Interrupt Enable */
8507 #define DSI_IER1_ECCMEIE_Pos          (3U)
8508 #define DSI_IER1_ECCMEIE_Msk          (0x1UL << DSI_IER1_ECCMEIE_Pos)           /*!< 0x00000008 */
8509 #define DSI_IER1_ECCMEIE              DSI_IER1_ECCMEIE_Msk                     /*!< ECC Multi-bit Error Interrupt Enable */
8510 #define DSI_IER1_CRCEIE_Pos           (4U)
8511 #define DSI_IER1_CRCEIE_Msk           (0x1UL << DSI_IER1_CRCEIE_Pos)            /*!< 0x00000010 */
8512 #define DSI_IER1_CRCEIE               DSI_IER1_CRCEIE_Msk                      /*!< CRC Error Interrupt Enable */
8513 #define DSI_IER1_PSEIE_Pos            (5U)
8514 #define DSI_IER1_PSEIE_Msk            (0x1UL << DSI_IER1_PSEIE_Pos)             /*!< 0x00000020 */
8515 #define DSI_IER1_PSEIE                DSI_IER1_PSEIE_Msk                       /*!< Packet Size Error Interrupt Enable */
8516 #define DSI_IER1_EOTPEIE_Pos          (6U)
8517 #define DSI_IER1_EOTPEIE_Msk          (0x1UL << DSI_IER1_EOTPEIE_Pos)           /*!< 0x00000040 */
8518 #define DSI_IER1_EOTPEIE              DSI_IER1_EOTPEIE_Msk                     /*!< EoTp Error Interrupt Enable */
8519 #define DSI_IER1_LPWREIE_Pos          (7U)
8520 #define DSI_IER1_LPWREIE_Msk          (0x1UL << DSI_IER1_LPWREIE_Pos)           /*!< 0x00000080 */
8521 #define DSI_IER1_LPWREIE              DSI_IER1_LPWREIE_Msk                     /*!< LTDC Payload Write Error Interrupt Enable */
8522 #define DSI_IER1_GCWREIE_Pos          (8U)
8523 #define DSI_IER1_GCWREIE_Msk          (0x1UL << DSI_IER1_GCWREIE_Pos)           /*!< 0x00000100 */
8524 #define DSI_IER1_GCWREIE              DSI_IER1_GCWREIE_Msk                     /*!< Generic Command Write Error Interrupt Enable */
8525 #define DSI_IER1_GPWREIE_Pos          (9U)
8526 #define DSI_IER1_GPWREIE_Msk          (0x1UL << DSI_IER1_GPWREIE_Pos)           /*!< 0x00000200 */
8527 #define DSI_IER1_GPWREIE              DSI_IER1_GPWREIE_Msk                     /*!< Generic Payload Write Error Interrupt Enable */
8528 #define DSI_IER1_GPTXEIE_Pos          (10U)
8529 #define DSI_IER1_GPTXEIE_Msk          (0x1UL << DSI_IER1_GPTXEIE_Pos)           /*!< 0x00000400 */
8530 #define DSI_IER1_GPTXEIE              DSI_IER1_GPTXEIE_Msk                     /*!< Generic Payload Transmit Error Interrupt Enable */
8531 #define DSI_IER1_GPRDEIE_Pos          (11U)
8532 #define DSI_IER1_GPRDEIE_Msk          (0x1UL << DSI_IER1_GPRDEIE_Pos)           /*!< 0x00000800 */
8533 #define DSI_IER1_GPRDEIE              DSI_IER1_GPRDEIE_Msk                     /*!< Generic Payload Read Error Interrupt Enable */
8534 #define DSI_IER1_GPRXEIE_Pos          (12U)
8535 #define DSI_IER1_GPRXEIE_Msk          (0x1UL << DSI_IER1_GPRXEIE_Pos)           /*!< 0x00001000 */
8536 #define DSI_IER1_GPRXEIE              DSI_IER1_GPRXEIE_Msk                     /*!< Generic Payload Receive Error Interrupt Enable */
8537 
8538 /*******************  Bit definition for DSI_FIR0 register  ***************/
8539 #define DSI_FIR0_FAE0_Pos             (0U)
8540 #define DSI_FIR0_FAE0_Msk             (0x1UL << DSI_FIR0_FAE0_Pos)              /*!< 0x00000001 */
8541 #define DSI_FIR0_FAE0                 DSI_FIR0_FAE0_Msk                        /*!< Force Acknowledge Error 0 */
8542 #define DSI_FIR0_FAE1_Pos             (1U)
8543 #define DSI_FIR0_FAE1_Msk             (0x1UL << DSI_FIR0_FAE1_Pos)              /*!< 0x00000002 */
8544 #define DSI_FIR0_FAE1                 DSI_FIR0_FAE1_Msk                        /*!< Force Acknowledge Error 1 */
8545 #define DSI_FIR0_FAE2_Pos             (2U)
8546 #define DSI_FIR0_FAE2_Msk             (0x1UL << DSI_FIR0_FAE2_Pos)              /*!< 0x00000004 */
8547 #define DSI_FIR0_FAE2                 DSI_FIR0_FAE2_Msk                        /*!< Force Acknowledge Error 2 */
8548 #define DSI_FIR0_FAE3_Pos             (3U)
8549 #define DSI_FIR0_FAE3_Msk             (0x1UL << DSI_FIR0_FAE3_Pos)              /*!< 0x00000008 */
8550 #define DSI_FIR0_FAE3                 DSI_FIR0_FAE3_Msk                        /*!< Force Acknowledge Error 3 */
8551 #define DSI_FIR0_FAE4_Pos             (4U)
8552 #define DSI_FIR0_FAE4_Msk             (0x1UL << DSI_FIR0_FAE4_Pos)              /*!< 0x00000010 */
8553 #define DSI_FIR0_FAE4                 DSI_FIR0_FAE4_Msk                        /*!< Force Acknowledge Error 4 */
8554 #define DSI_FIR0_FAE5_Pos             (5U)
8555 #define DSI_FIR0_FAE5_Msk             (0x1UL << DSI_FIR0_FAE5_Pos)              /*!< 0x00000020 */
8556 #define DSI_FIR0_FAE5                 DSI_FIR0_FAE5_Msk                        /*!< Force Acknowledge Error 5 */
8557 #define DSI_FIR0_FAE6_Pos             (6U)
8558 #define DSI_FIR0_FAE6_Msk             (0x1UL << DSI_FIR0_FAE6_Pos)              /*!< 0x00000040 */
8559 #define DSI_FIR0_FAE6                 DSI_FIR0_FAE6_Msk                        /*!< Force Acknowledge Error 6 */
8560 #define DSI_FIR0_FAE7_Pos             (7U)
8561 #define DSI_FIR0_FAE7_Msk             (0x1UL << DSI_FIR0_FAE7_Pos)              /*!< 0x00000080 */
8562 #define DSI_FIR0_FAE7                 DSI_FIR0_FAE7_Msk                        /*!< Force Acknowledge Error 7 */
8563 #define DSI_FIR0_FAE8_Pos             (8U)
8564 #define DSI_FIR0_FAE8_Msk             (0x1UL << DSI_FIR0_FAE8_Pos)              /*!< 0x00000100 */
8565 #define DSI_FIR0_FAE8                 DSI_FIR0_FAE8_Msk                        /*!< Force Acknowledge Error 8 */
8566 #define DSI_FIR0_FAE9_Pos             (9U)
8567 #define DSI_FIR0_FAE9_Msk             (0x1UL << DSI_FIR0_FAE9_Pos)              /*!< 0x00000200 */
8568 #define DSI_FIR0_FAE9                 DSI_FIR0_FAE9_Msk                        /*!< Force Acknowledge Error 9 */
8569 #define DSI_FIR0_FAE10_Pos            (10U)
8570 #define DSI_FIR0_FAE10_Msk            (0x1UL << DSI_FIR0_FAE10_Pos)             /*!< 0x00000400 */
8571 #define DSI_FIR0_FAE10                DSI_FIR0_FAE10_Msk                       /*!< Force Acknowledge Error 10 */
8572 #define DSI_FIR0_FAE11_Pos            (11U)
8573 #define DSI_FIR0_FAE11_Msk            (0x1UL << DSI_FIR0_FAE11_Pos)             /*!< 0x00000800 */
8574 #define DSI_FIR0_FAE11                DSI_FIR0_FAE11_Msk                       /*!< Force Acknowledge Error 11 */
8575 #define DSI_FIR0_FAE12_Pos            (12U)
8576 #define DSI_FIR0_FAE12_Msk            (0x1UL << DSI_FIR0_FAE12_Pos)             /*!< 0x00001000 */
8577 #define DSI_FIR0_FAE12                DSI_FIR0_FAE12_Msk                       /*!< Force Acknowledge Error 12 */
8578 #define DSI_FIR0_FAE13_Pos            (13U)
8579 #define DSI_FIR0_FAE13_Msk            (0x1UL << DSI_FIR0_FAE13_Pos)             /*!< 0x00002000 */
8580 #define DSI_FIR0_FAE13                DSI_FIR0_FAE13_Msk                       /*!< Force Acknowledge Error 13 */
8581 #define DSI_FIR0_FAE14_Pos            (14U)
8582 #define DSI_FIR0_FAE14_Msk            (0x1UL << DSI_FIR0_FAE14_Pos)             /*!< 0x00004000 */
8583 #define DSI_FIR0_FAE14                DSI_FIR0_FAE14_Msk                       /*!< Force Acknowledge Error 14 */
8584 #define DSI_FIR0_FAE15_Pos            (15U)
8585 #define DSI_FIR0_FAE15_Msk            (0x1UL << DSI_FIR0_FAE15_Pos)             /*!< 0x00008000 */
8586 #define DSI_FIR0_FAE15                DSI_FIR0_FAE15_Msk                       /*!< Force Acknowledge Error 15 */
8587 #define DSI_FIR0_FPE0_Pos             (16U)
8588 #define DSI_FIR0_FPE0_Msk             (0x1UL << DSI_FIR0_FPE0_Pos)              /*!< 0x00010000 */
8589 #define DSI_FIR0_FPE0                 DSI_FIR0_FPE0_Msk                        /*!< Force PHY Error 0 */
8590 #define DSI_FIR0_FPE1_Pos             (17U)
8591 #define DSI_FIR0_FPE1_Msk             (0x1UL << DSI_FIR0_FPE1_Pos)              /*!< 0x00020000 */
8592 #define DSI_FIR0_FPE1                 DSI_FIR0_FPE1_Msk                        /*!< Force PHY Error 1 */
8593 #define DSI_FIR0_FPE2_Pos             (18U)
8594 #define DSI_FIR0_FPE2_Msk             (0x1UL << DSI_FIR0_FPE2_Pos)              /*!< 0x00040000 */
8595 #define DSI_FIR0_FPE2                 DSI_FIR0_FPE2_Msk                        /*!< Force PHY Error 2 */
8596 #define DSI_FIR0_FPE3_Pos             (19U)
8597 #define DSI_FIR0_FPE3_Msk             (0x1UL << DSI_FIR0_FPE3_Pos)              /*!< 0x00080000 */
8598 #define DSI_FIR0_FPE3                 DSI_FIR0_FPE3_Msk                        /*!< Force PHY Error 3 */
8599 #define DSI_FIR0_FPE4_Pos             (20U)
8600 #define DSI_FIR0_FPE4_Msk             (0x1UL << DSI_FIR0_FPE4_Pos)              /*!< 0x00100000 */
8601 #define DSI_FIR0_FPE4                 DSI_FIR0_FPE4_Msk                        /*!< Force PHY Error 4 */
8602 
8603 /*******************  Bit definition for DSI_FIR1 register  ***************/
8604 #define DSI_FIR1_FTOHSTX_Pos          (0U)
8605 #define DSI_FIR1_FTOHSTX_Msk          (0x1UL << DSI_FIR1_FTOHSTX_Pos)           /*!< 0x00000001 */
8606 #define DSI_FIR1_FTOHSTX              DSI_FIR1_FTOHSTX_Msk                     /*!< Force Timeout High-Speed Transmission */
8607 #define DSI_FIR1_FTOLPRX_Pos          (1U)
8608 #define DSI_FIR1_FTOLPRX_Msk          (0x1UL << DSI_FIR1_FTOLPRX_Pos)           /*!< 0x00000002 */
8609 #define DSI_FIR1_FTOLPRX              DSI_FIR1_FTOLPRX_Msk                     /*!< Force Timeout Low-Power Reception */
8610 #define DSI_FIR1_FECCSE_Pos           (2U)
8611 #define DSI_FIR1_FECCSE_Msk           (0x1UL << DSI_FIR1_FECCSE_Pos)            /*!< 0x00000004 */
8612 #define DSI_FIR1_FECCSE               DSI_FIR1_FECCSE_Msk                      /*!< Force ECC Single-bit Error */
8613 #define DSI_FIR1_FECCME_Pos           (3U)
8614 #define DSI_FIR1_FECCME_Msk           (0x1UL << DSI_FIR1_FECCME_Pos)            /*!< 0x00000008 */
8615 #define DSI_FIR1_FECCME               DSI_FIR1_FECCME_Msk                      /*!< Force ECC Multi-bit Error */
8616 #define DSI_FIR1_FCRCE_Pos            (4U)
8617 #define DSI_FIR1_FCRCE_Msk            (0x1UL << DSI_FIR1_FCRCE_Pos)             /*!< 0x00000010 */
8618 #define DSI_FIR1_FCRCE                DSI_FIR1_FCRCE_Msk                       /*!< Force CRC Error */
8619 #define DSI_FIR1_FPSE_Pos             (5U)
8620 #define DSI_FIR1_FPSE_Msk             (0x1UL << DSI_FIR1_FPSE_Pos)              /*!< 0x00000020 */
8621 #define DSI_FIR1_FPSE                 DSI_FIR1_FPSE_Msk                        /*!< Force Packet Size Error */
8622 #define DSI_FIR1_FEOTPE_Pos           (6U)
8623 #define DSI_FIR1_FEOTPE_Msk           (0x1UL << DSI_FIR1_FEOTPE_Pos)            /*!< 0x00000040 */
8624 #define DSI_FIR1_FEOTPE               DSI_FIR1_FEOTPE_Msk                      /*!< Force EoTp Error */
8625 #define DSI_FIR1_FLPWRE_Pos           (7U)
8626 #define DSI_FIR1_FLPWRE_Msk           (0x1UL << DSI_FIR1_FLPWRE_Pos)            /*!< 0x00000080 */
8627 #define DSI_FIR1_FLPWRE               DSI_FIR1_FLPWRE_Msk                      /*!< Force LTDC Payload Write Error */
8628 #define DSI_FIR1_FGCWRE_Pos           (8U)
8629 #define DSI_FIR1_FGCWRE_Msk           (0x1UL << DSI_FIR1_FGCWRE_Pos)            /*!< 0x00000100 */
8630 #define DSI_FIR1_FGCWRE               DSI_FIR1_FGCWRE_Msk                      /*!< Force Generic Command Write Error */
8631 #define DSI_FIR1_FGPWRE_Pos           (9U)
8632 #define DSI_FIR1_FGPWRE_Msk           (0x1UL << DSI_FIR1_FGPWRE_Pos)            /*!< 0x00000200 */
8633 #define DSI_FIR1_FGPWRE               DSI_FIR1_FGPWRE_Msk                      /*!< Force Generic Payload Write Error */
8634 #define DSI_FIR1_FGPTXE_Pos           (10U)
8635 #define DSI_FIR1_FGPTXE_Msk           (0x1UL << DSI_FIR1_FGPTXE_Pos)            /*!< 0x00000400 */
8636 #define DSI_FIR1_FGPTXE               DSI_FIR1_FGPTXE_Msk                      /*!< Force Generic Payload Transmit Error */
8637 #define DSI_FIR1_FGPRDE_Pos           (11U)
8638 #define DSI_FIR1_FGPRDE_Msk           (0x1UL << DSI_FIR1_FGPRDE_Pos)            /*!< 0x00000800 */
8639 #define DSI_FIR1_FGPRDE               DSI_FIR1_FGPRDE_Msk                      /*!< Force Generic Payload Read Error */
8640 #define DSI_FIR1_FGPRXE_Pos           (12U)
8641 #define DSI_FIR1_FGPRXE_Msk           (0x1UL << DSI_FIR1_FGPRXE_Pos)            /*!< 0x00001000 */
8642 #define DSI_FIR1_FGPRXE               DSI_FIR1_FGPRXE_Msk                      /*!< Force Generic Payload Receive Error */
8643 
8644 /*******************  Bit definition for DSI_VSCR register  ***************/
8645 #define DSI_VSCR_EN_Pos               (0U)
8646 #define DSI_VSCR_EN_Msk               (0x1UL << DSI_VSCR_EN_Pos)                /*!< 0x00000001 */
8647 #define DSI_VSCR_EN                   DSI_VSCR_EN_Msk                          /*!< Enable */
8648 #define DSI_VSCR_UR_Pos               (8U)
8649 #define DSI_VSCR_UR_Msk               (0x1UL << DSI_VSCR_UR_Pos)                /*!< 0x00000100 */
8650 #define DSI_VSCR_UR                   DSI_VSCR_UR_Msk                          /*!< Update Register */
8651 
8652 /*******************  Bit definition for DSI_LCVCIDR register  ************/
8653 #define DSI_LCVCIDR_VCID_Pos          (0U)
8654 #define DSI_LCVCIDR_VCID_Msk          (0x3UL << DSI_LCVCIDR_VCID_Pos)           /*!< 0x00000003 */
8655 #define DSI_LCVCIDR_VCID              DSI_LCVCIDR_VCID_Msk                     /*!< Virtual Channel ID */
8656 #define DSI_LCVCIDR_VCID0_Pos         (0U)
8657 #define DSI_LCVCIDR_VCID0_Msk         (0x1UL << DSI_LCVCIDR_VCID0_Pos)          /*!< 0x00000001 */
8658 #define DSI_LCVCIDR_VCID0             DSI_LCVCIDR_VCID0_Msk
8659 #define DSI_LCVCIDR_VCID1_Pos         (1U)
8660 #define DSI_LCVCIDR_VCID1_Msk         (0x1UL << DSI_LCVCIDR_VCID1_Pos)          /*!< 0x00000002 */
8661 #define DSI_LCVCIDR_VCID1             DSI_LCVCIDR_VCID1_Msk
8662 
8663 /*******************  Bit definition for DSI_LCCCR register  **************/
8664 #define DSI_LCCCR_COLC_Pos            (0U)
8665 #define DSI_LCCCR_COLC_Msk            (0xFUL << DSI_LCCCR_COLC_Pos)             /*!< 0x0000000F */
8666 #define DSI_LCCCR_COLC                DSI_LCCCR_COLC_Msk                       /*!< Color Coding */
8667 #define DSI_LCCCR_COLC0_Pos           (0U)
8668 #define DSI_LCCCR_COLC0_Msk           (0x1UL << DSI_LCCCR_COLC0_Pos)            /*!< 0x00000001 */
8669 #define DSI_LCCCR_COLC0               DSI_LCCCR_COLC0_Msk
8670 #define DSI_LCCCR_COLC1_Pos           (1U)
8671 #define DSI_LCCCR_COLC1_Msk           (0x1UL << DSI_LCCCR_COLC1_Pos)            /*!< 0x00000002 */
8672 #define DSI_LCCCR_COLC1               DSI_LCCCR_COLC1_Msk
8673 #define DSI_LCCCR_COLC2_Pos           (2U)
8674 #define DSI_LCCCR_COLC2_Msk           (0x1UL << DSI_LCCCR_COLC2_Pos)            /*!< 0x00000004 */
8675 #define DSI_LCCCR_COLC2               DSI_LCCCR_COLC2_Msk
8676 #define DSI_LCCCR_COLC3_Pos           (3U)
8677 #define DSI_LCCCR_COLC3_Msk           (0x1UL << DSI_LCCCR_COLC3_Pos)            /*!< 0x00000008 */
8678 #define DSI_LCCCR_COLC3               DSI_LCCCR_COLC3_Msk
8679 
8680 #define DSI_LCCCR_LPE_Pos             (8U)
8681 #define DSI_LCCCR_LPE_Msk             (0x1UL << DSI_LCCCR_LPE_Pos)              /*!< 0x00000100 */
8682 #define DSI_LCCCR_LPE                 DSI_LCCCR_LPE_Msk                        /*!< Loosely Packed Enable */
8683 
8684 /*******************  Bit definition for DSI_LPMCCR register  *************/
8685 #define DSI_LPMCCR_VLPSIZE_Pos        (0U)
8686 #define DSI_LPMCCR_VLPSIZE_Msk        (0xFFUL << DSI_LPMCCR_VLPSIZE_Pos)        /*!< 0x000000FF */
8687 #define DSI_LPMCCR_VLPSIZE            DSI_LPMCCR_VLPSIZE_Msk                   /*!< VACT Largest Packet Size */
8688 #define DSI_LPMCCR_VLPSIZE0_Pos       (0U)
8689 #define DSI_LPMCCR_VLPSIZE0_Msk       (0x1UL << DSI_LPMCCR_VLPSIZE0_Pos)        /*!< 0x00000001 */
8690 #define DSI_LPMCCR_VLPSIZE0           DSI_LPMCCR_VLPSIZE0_Msk
8691 #define DSI_LPMCCR_VLPSIZE1_Pos       (1U)
8692 #define DSI_LPMCCR_VLPSIZE1_Msk       (0x1UL << DSI_LPMCCR_VLPSIZE1_Pos)        /*!< 0x00000002 */
8693 #define DSI_LPMCCR_VLPSIZE1           DSI_LPMCCR_VLPSIZE1_Msk
8694 #define DSI_LPMCCR_VLPSIZE2_Pos       (2U)
8695 #define DSI_LPMCCR_VLPSIZE2_Msk       (0x1UL << DSI_LPMCCR_VLPSIZE2_Pos)        /*!< 0x00000004 */
8696 #define DSI_LPMCCR_VLPSIZE2           DSI_LPMCCR_VLPSIZE2_Msk
8697 #define DSI_LPMCCR_VLPSIZE3_Pos       (3U)
8698 #define DSI_LPMCCR_VLPSIZE3_Msk       (0x1UL << DSI_LPMCCR_VLPSIZE3_Pos)        /*!< 0x00000008 */
8699 #define DSI_LPMCCR_VLPSIZE3           DSI_LPMCCR_VLPSIZE3_Msk
8700 #define DSI_LPMCCR_VLPSIZE4_Pos       (4U)
8701 #define DSI_LPMCCR_VLPSIZE4_Msk       (0x1UL << DSI_LPMCCR_VLPSIZE4_Pos)        /*!< 0x00000010 */
8702 #define DSI_LPMCCR_VLPSIZE4           DSI_LPMCCR_VLPSIZE4_Msk
8703 #define DSI_LPMCCR_VLPSIZE5_Pos       (5U)
8704 #define DSI_LPMCCR_VLPSIZE5_Msk       (0x1UL << DSI_LPMCCR_VLPSIZE5_Pos)        /*!< 0x00000020 */
8705 #define DSI_LPMCCR_VLPSIZE5           DSI_LPMCCR_VLPSIZE5_Msk
8706 #define DSI_LPMCCR_VLPSIZE6_Pos       (6U)
8707 #define DSI_LPMCCR_VLPSIZE6_Msk       (0x1UL << DSI_LPMCCR_VLPSIZE6_Pos)        /*!< 0x00000040 */
8708 #define DSI_LPMCCR_VLPSIZE6           DSI_LPMCCR_VLPSIZE6_Msk
8709 #define DSI_LPMCCR_VLPSIZE7_Pos       (7U)
8710 #define DSI_LPMCCR_VLPSIZE7_Msk       (0x1UL << DSI_LPMCCR_VLPSIZE7_Pos)        /*!< 0x00000080 */
8711 #define DSI_LPMCCR_VLPSIZE7           DSI_LPMCCR_VLPSIZE7_Msk
8712 
8713 #define DSI_LPMCCR_LPSIZE_Pos         (16U)
8714 #define DSI_LPMCCR_LPSIZE_Msk         (0xFFUL << DSI_LPMCCR_LPSIZE_Pos)         /*!< 0x00FF0000 */
8715 #define DSI_LPMCCR_LPSIZE             DSI_LPMCCR_LPSIZE_Msk                    /*!< Largest Packet Size */
8716 #define DSI_LPMCCR_LPSIZE0_Pos        (16U)
8717 #define DSI_LPMCCR_LPSIZE0_Msk        (0x1UL << DSI_LPMCCR_LPSIZE0_Pos)         /*!< 0x00010000 */
8718 #define DSI_LPMCCR_LPSIZE0            DSI_LPMCCR_LPSIZE0_Msk
8719 #define DSI_LPMCCR_LPSIZE1_Pos        (17U)
8720 #define DSI_LPMCCR_LPSIZE1_Msk        (0x1UL << DSI_LPMCCR_LPSIZE1_Pos)         /*!< 0x00020000 */
8721 #define DSI_LPMCCR_LPSIZE1            DSI_LPMCCR_LPSIZE1_Msk
8722 #define DSI_LPMCCR_LPSIZE2_Pos        (18U)
8723 #define DSI_LPMCCR_LPSIZE2_Msk        (0x1UL << DSI_LPMCCR_LPSIZE2_Pos)         /*!< 0x00040000 */
8724 #define DSI_LPMCCR_LPSIZE2            DSI_LPMCCR_LPSIZE2_Msk
8725 #define DSI_LPMCCR_LPSIZE3_Pos        (19U)
8726 #define DSI_LPMCCR_LPSIZE3_Msk        (0x1UL << DSI_LPMCCR_LPSIZE3_Pos)         /*!< 0x00080000 */
8727 #define DSI_LPMCCR_LPSIZE3            DSI_LPMCCR_LPSIZE3_Msk
8728 #define DSI_LPMCCR_LPSIZE4_Pos        (20U)
8729 #define DSI_LPMCCR_LPSIZE4_Msk        (0x1UL << DSI_LPMCCR_LPSIZE4_Pos)         /*!< 0x00100000 */
8730 #define DSI_LPMCCR_LPSIZE4            DSI_LPMCCR_LPSIZE4_Msk
8731 #define DSI_LPMCCR_LPSIZE5_Pos        (21U)
8732 #define DSI_LPMCCR_LPSIZE5_Msk        (0x1UL << DSI_LPMCCR_LPSIZE5_Pos)         /*!< 0x00200000 */
8733 #define DSI_LPMCCR_LPSIZE5            DSI_LPMCCR_LPSIZE5_Msk
8734 #define DSI_LPMCCR_LPSIZE6_Pos        (22U)
8735 #define DSI_LPMCCR_LPSIZE6_Msk        (0x1UL << DSI_LPMCCR_LPSIZE6_Pos)         /*!< 0x00400000 */
8736 #define DSI_LPMCCR_LPSIZE6            DSI_LPMCCR_LPSIZE6_Msk
8737 #define DSI_LPMCCR_LPSIZE7_Pos        (23U)
8738 #define DSI_LPMCCR_LPSIZE7_Msk        (0x1UL << DSI_LPMCCR_LPSIZE7_Pos)         /*!< 0x00800000 */
8739 #define DSI_LPMCCR_LPSIZE7            DSI_LPMCCR_LPSIZE7_Msk
8740 
8741 /*******************  Bit definition for DSI_VMCCR register  **************/
8742 #define DSI_VMCCR_VMT_Pos             (0U)
8743 #define DSI_VMCCR_VMT_Msk             (0x3UL << DSI_VMCCR_VMT_Pos)              /*!< 0x00000003 */
8744 #define DSI_VMCCR_VMT                 DSI_VMCCR_VMT_Msk                        /*!< Video Mode Type */
8745 #define DSI_VMCCR_VMT0_Pos            (0U)
8746 #define DSI_VMCCR_VMT0_Msk            (0x1UL << DSI_VMCCR_VMT0_Pos)             /*!< 0x00000001 */
8747 #define DSI_VMCCR_VMT0                DSI_VMCCR_VMT0_Msk
8748 #define DSI_VMCCR_VMT1_Pos            (1U)
8749 #define DSI_VMCCR_VMT1_Msk            (0x1UL << DSI_VMCCR_VMT1_Pos)             /*!< 0x00000002 */
8750 #define DSI_VMCCR_VMT1                DSI_VMCCR_VMT1_Msk
8751 
8752 #define DSI_VMCCR_LPVSAE_Pos          (8U)
8753 #define DSI_VMCCR_LPVSAE_Msk          (0x1UL << DSI_VMCCR_LPVSAE_Pos)           /*!< 0x00000100 */
8754 #define DSI_VMCCR_LPVSAE              DSI_VMCCR_LPVSAE_Msk                     /*!< Low-power Vertical Sync time Enable */
8755 #define DSI_VMCCR_LPVBPE_Pos          (9U)
8756 #define DSI_VMCCR_LPVBPE_Msk          (0x1UL << DSI_VMCCR_LPVBPE_Pos)           /*!< 0x00000200 */
8757 #define DSI_VMCCR_LPVBPE              DSI_VMCCR_LPVBPE_Msk                     /*!< Low-power Vertical Back-porch Enable */
8758 #define DSI_VMCCR_LPVFPE_Pos          (10U)
8759 #define DSI_VMCCR_LPVFPE_Msk          (0x1UL << DSI_VMCCR_LPVFPE_Pos)           /*!< 0x00000400 */
8760 #define DSI_VMCCR_LPVFPE              DSI_VMCCR_LPVFPE_Msk                     /*!< Low-power Vertical Front-porch Enable */
8761 #define DSI_VMCCR_LPVAE_Pos           (11U)
8762 #define DSI_VMCCR_LPVAE_Msk           (0x1UL << DSI_VMCCR_LPVAE_Pos)            /*!< 0x00000800 */
8763 #define DSI_VMCCR_LPVAE               DSI_VMCCR_LPVAE_Msk                      /*!< Low-power Vertical Active Enable */
8764 #define DSI_VMCCR_LPHBPE_Pos          (12U)
8765 #define DSI_VMCCR_LPHBPE_Msk          (0x1UL << DSI_VMCCR_LPHBPE_Pos)           /*!< 0x00001000 */
8766 #define DSI_VMCCR_LPHBPE              DSI_VMCCR_LPHBPE_Msk                     /*!< Low-power Horizontal Back-porch Enable */
8767 #define DSI_VMCCR_LPHFE_Pos           (13U)
8768 #define DSI_VMCCR_LPHFE_Msk           (0x1UL << DSI_VMCCR_LPHFE_Pos)            /*!< 0x00002000 */
8769 #define DSI_VMCCR_LPHFE               DSI_VMCCR_LPHFE_Msk                      /*!< Low-power Horizontal Front-porch Enable */
8770 #define DSI_VMCCR_FBTAAE_Pos          (14U)
8771 #define DSI_VMCCR_FBTAAE_Msk          (0x1UL << DSI_VMCCR_FBTAAE_Pos)           /*!< 0x00004000 */
8772 #define DSI_VMCCR_FBTAAE              DSI_VMCCR_FBTAAE_Msk                     /*!< Frame BTA Acknowledge Enable */
8773 #define DSI_VMCCR_LPCE_Pos            (15U)
8774 #define DSI_VMCCR_LPCE_Msk            (0x1UL << DSI_VMCCR_LPCE_Pos)             /*!< 0x00008000 */
8775 #define DSI_VMCCR_LPCE                DSI_VMCCR_LPCE_Msk                       /*!< Low-power Command Enable */
8776 
8777 /*******************  Bit definition for DSI_VPCCR register  **************/
8778 #define DSI_VPCCR_VPSIZE_Pos          (0U)
8779 #define DSI_VPCCR_VPSIZE_Msk          (0x3FFFUL << DSI_VPCCR_VPSIZE_Pos)        /*!< 0x00003FFF */
8780 #define DSI_VPCCR_VPSIZE              DSI_VPCCR_VPSIZE_Msk                     /*!< Video Packet Size */
8781 #define DSI_VPCCR_VPSIZE0_Pos         (0U)
8782 #define DSI_VPCCR_VPSIZE0_Msk         (0x1UL << DSI_VPCCR_VPSIZE0_Pos)          /*!< 0x00000001 */
8783 #define DSI_VPCCR_VPSIZE0             DSI_VPCCR_VPSIZE0_Msk
8784 #define DSI_VPCCR_VPSIZE1_Pos         (1U)
8785 #define DSI_VPCCR_VPSIZE1_Msk         (0x1UL << DSI_VPCCR_VPSIZE1_Pos)          /*!< 0x00000002 */
8786 #define DSI_VPCCR_VPSIZE1             DSI_VPCCR_VPSIZE1_Msk
8787 #define DSI_VPCCR_VPSIZE2_Pos         (2U)
8788 #define DSI_VPCCR_VPSIZE2_Msk         (0x1UL << DSI_VPCCR_VPSIZE2_Pos)          /*!< 0x00000004 */
8789 #define DSI_VPCCR_VPSIZE2             DSI_VPCCR_VPSIZE2_Msk
8790 #define DSI_VPCCR_VPSIZE3_Pos         (3U)
8791 #define DSI_VPCCR_VPSIZE3_Msk         (0x1UL << DSI_VPCCR_VPSIZE3_Pos)          /*!< 0x00000008 */
8792 #define DSI_VPCCR_VPSIZE3             DSI_VPCCR_VPSIZE3_Msk
8793 #define DSI_VPCCR_VPSIZE4_Pos         (4U)
8794 #define DSI_VPCCR_VPSIZE4_Msk         (0x1UL << DSI_VPCCR_VPSIZE4_Pos)          /*!< 0x00000010 */
8795 #define DSI_VPCCR_VPSIZE4             DSI_VPCCR_VPSIZE4_Msk
8796 #define DSI_VPCCR_VPSIZE5_Pos         (5U)
8797 #define DSI_VPCCR_VPSIZE5_Msk         (0x1UL << DSI_VPCCR_VPSIZE5_Pos)          /*!< 0x00000020 */
8798 #define DSI_VPCCR_VPSIZE5             DSI_VPCCR_VPSIZE5_Msk
8799 #define DSI_VPCCR_VPSIZE6_Pos         (6U)
8800 #define DSI_VPCCR_VPSIZE6_Msk         (0x1UL << DSI_VPCCR_VPSIZE6_Pos)          /*!< 0x00000040 */
8801 #define DSI_VPCCR_VPSIZE6             DSI_VPCCR_VPSIZE6_Msk
8802 #define DSI_VPCCR_VPSIZE7_Pos         (7U)
8803 #define DSI_VPCCR_VPSIZE7_Msk         (0x1UL << DSI_VPCCR_VPSIZE7_Pos)          /*!< 0x00000080 */
8804 #define DSI_VPCCR_VPSIZE7             DSI_VPCCR_VPSIZE7_Msk
8805 #define DSI_VPCCR_VPSIZE8_Pos         (8U)
8806 #define DSI_VPCCR_VPSIZE8_Msk         (0x1UL << DSI_VPCCR_VPSIZE8_Pos)          /*!< 0x00000100 */
8807 #define DSI_VPCCR_VPSIZE8             DSI_VPCCR_VPSIZE8_Msk
8808 #define DSI_VPCCR_VPSIZE9_Pos         (9U)
8809 #define DSI_VPCCR_VPSIZE9_Msk         (0x1UL << DSI_VPCCR_VPSIZE9_Pos)          /*!< 0x00000200 */
8810 #define DSI_VPCCR_VPSIZE9             DSI_VPCCR_VPSIZE9_Msk
8811 #define DSI_VPCCR_VPSIZE10_Pos        (10U)
8812 #define DSI_VPCCR_VPSIZE10_Msk        (0x1UL << DSI_VPCCR_VPSIZE10_Pos)         /*!< 0x00000400 */
8813 #define DSI_VPCCR_VPSIZE10            DSI_VPCCR_VPSIZE10_Msk
8814 #define DSI_VPCCR_VPSIZE11_Pos        (11U)
8815 #define DSI_VPCCR_VPSIZE11_Msk        (0x1UL << DSI_VPCCR_VPSIZE11_Pos)         /*!< 0x00000800 */
8816 #define DSI_VPCCR_VPSIZE11            DSI_VPCCR_VPSIZE11_Msk
8817 #define DSI_VPCCR_VPSIZE12_Pos        (12U)
8818 #define DSI_VPCCR_VPSIZE12_Msk        (0x1UL << DSI_VPCCR_VPSIZE12_Pos)         /*!< 0x00001000 */
8819 #define DSI_VPCCR_VPSIZE12            DSI_VPCCR_VPSIZE12_Msk
8820 #define DSI_VPCCR_VPSIZE13_Pos        (13U)
8821 #define DSI_VPCCR_VPSIZE13_Msk        (0x1UL << DSI_VPCCR_VPSIZE13_Pos)         /*!< 0x00002000 */
8822 #define DSI_VPCCR_VPSIZE13            DSI_VPCCR_VPSIZE13_Msk
8823 
8824 /*******************  Bit definition for DSI_VCCCR register  **************/
8825 #define DSI_VCCCR_NUMC_Pos            (0U)
8826 #define DSI_VCCCR_NUMC_Msk            (0x1FFFUL << DSI_VCCCR_NUMC_Pos)          /*!< 0x00001FFF */
8827 #define DSI_VCCCR_NUMC                DSI_VCCCR_NUMC_Msk                       /*!< Number of Chunks */
8828 #define DSI_VCCCR_NUMC0_Pos           (0U)
8829 #define DSI_VCCCR_NUMC0_Msk           (0x1UL << DSI_VCCCR_NUMC0_Pos)            /*!< 0x00000001 */
8830 #define DSI_VCCCR_NUMC0               DSI_VCCCR_NUMC0_Msk
8831 #define DSI_VCCCR_NUMC1_Pos           (1U)
8832 #define DSI_VCCCR_NUMC1_Msk           (0x1UL << DSI_VCCCR_NUMC1_Pos)            /*!< 0x00000002 */
8833 #define DSI_VCCCR_NUMC1               DSI_VCCCR_NUMC1_Msk
8834 #define DSI_VCCCR_NUMC2_Pos           (2U)
8835 #define DSI_VCCCR_NUMC2_Msk           (0x1UL << DSI_VCCCR_NUMC2_Pos)            /*!< 0x00000004 */
8836 #define DSI_VCCCR_NUMC2               DSI_VCCCR_NUMC2_Msk
8837 #define DSI_VCCCR_NUMC3_Pos           (3U)
8838 #define DSI_VCCCR_NUMC3_Msk           (0x1UL << DSI_VCCCR_NUMC3_Pos)            /*!< 0x00000008 */
8839 #define DSI_VCCCR_NUMC3               DSI_VCCCR_NUMC3_Msk
8840 #define DSI_VCCCR_NUMC4_Pos           (4U)
8841 #define DSI_VCCCR_NUMC4_Msk           (0x1UL << DSI_VCCCR_NUMC4_Pos)            /*!< 0x00000010 */
8842 #define DSI_VCCCR_NUMC4               DSI_VCCCR_NUMC4_Msk
8843 #define DSI_VCCCR_NUMC5_Pos           (5U)
8844 #define DSI_VCCCR_NUMC5_Msk           (0x1UL << DSI_VCCCR_NUMC5_Pos)            /*!< 0x00000020 */
8845 #define DSI_VCCCR_NUMC5               DSI_VCCCR_NUMC5_Msk
8846 #define DSI_VCCCR_NUMC6_Pos           (6U)
8847 #define DSI_VCCCR_NUMC6_Msk           (0x1UL << DSI_VCCCR_NUMC6_Pos)            /*!< 0x00000040 */
8848 #define DSI_VCCCR_NUMC6               DSI_VCCCR_NUMC6_Msk
8849 #define DSI_VCCCR_NUMC7_Pos           (7U)
8850 #define DSI_VCCCR_NUMC7_Msk           (0x1UL << DSI_VCCCR_NUMC7_Pos)            /*!< 0x00000080 */
8851 #define DSI_VCCCR_NUMC7               DSI_VCCCR_NUMC7_Msk
8852 #define DSI_VCCCR_NUMC8_Pos           (8U)
8853 #define DSI_VCCCR_NUMC8_Msk           (0x1UL << DSI_VCCCR_NUMC8_Pos)            /*!< 0x00000100 */
8854 #define DSI_VCCCR_NUMC8               DSI_VCCCR_NUMC8_Msk
8855 #define DSI_VCCCR_NUMC9_Pos           (9U)
8856 #define DSI_VCCCR_NUMC9_Msk           (0x1UL << DSI_VCCCR_NUMC9_Pos)            /*!< 0x00000200 */
8857 #define DSI_VCCCR_NUMC9               DSI_VCCCR_NUMC9_Msk
8858 #define DSI_VCCCR_NUMC10_Pos          (10U)
8859 #define DSI_VCCCR_NUMC10_Msk          (0x1UL << DSI_VCCCR_NUMC10_Pos)           /*!< 0x00000400 */
8860 #define DSI_VCCCR_NUMC10              DSI_VCCCR_NUMC10_Msk
8861 #define DSI_VCCCR_NUMC11_Pos          (11U)
8862 #define DSI_VCCCR_NUMC11_Msk          (0x1UL << DSI_VCCCR_NUMC11_Pos)           /*!< 0x00000800 */
8863 #define DSI_VCCCR_NUMC11              DSI_VCCCR_NUMC11_Msk
8864 #define DSI_VCCCR_NUMC12_Pos          (12U)
8865 #define DSI_VCCCR_NUMC12_Msk          (0x1UL << DSI_VCCCR_NUMC12_Pos)           /*!< 0x00001000 */
8866 #define DSI_VCCCR_NUMC12              DSI_VCCCR_NUMC12_Msk
8867 
8868 /*******************  Bit definition for DSI_VNPCCR register  *************/
8869 #define DSI_VNPCCR_NPSIZE_Pos         (0U)
8870 #define DSI_VNPCCR_NPSIZE_Msk         (0x1FFFUL << DSI_VNPCCR_NPSIZE_Pos)       /*!< 0x00001FFF */
8871 #define DSI_VNPCCR_NPSIZE             DSI_VNPCCR_NPSIZE_Msk                    /*!< Number of Chunks */
8872 #define DSI_VNPCCR_NPSIZE0_Pos        (0U)
8873 #define DSI_VNPCCR_NPSIZE0_Msk        (0x1UL << DSI_VNPCCR_NPSIZE0_Pos)         /*!< 0x00000001 */
8874 #define DSI_VNPCCR_NPSIZE0            DSI_VNPCCR_NPSIZE0_Msk
8875 #define DSI_VNPCCR_NPSIZE1_Pos        (1U)
8876 #define DSI_VNPCCR_NPSIZE1_Msk        (0x1UL << DSI_VNPCCR_NPSIZE1_Pos)         /*!< 0x00000002 */
8877 #define DSI_VNPCCR_NPSIZE1            DSI_VNPCCR_NPSIZE1_Msk
8878 #define DSI_VNPCCR_NPSIZE2_Pos        (2U)
8879 #define DSI_VNPCCR_NPSIZE2_Msk        (0x1UL << DSI_VNPCCR_NPSIZE2_Pos)         /*!< 0x00000004 */
8880 #define DSI_VNPCCR_NPSIZE2            DSI_VNPCCR_NPSIZE2_Msk
8881 #define DSI_VNPCCR_NPSIZE3_Pos        (3U)
8882 #define DSI_VNPCCR_NPSIZE3_Msk        (0x1UL << DSI_VNPCCR_NPSIZE3_Pos)         /*!< 0x00000008 */
8883 #define DSI_VNPCCR_NPSIZE3            DSI_VNPCCR_NPSIZE3_Msk
8884 #define DSI_VNPCCR_NPSIZE4_Pos        (4U)
8885 #define DSI_VNPCCR_NPSIZE4_Msk        (0x1UL << DSI_VNPCCR_NPSIZE4_Pos)         /*!< 0x00000010 */
8886 #define DSI_VNPCCR_NPSIZE4            DSI_VNPCCR_NPSIZE4_Msk
8887 #define DSI_VNPCCR_NPSIZE5_Pos        (5U)
8888 #define DSI_VNPCCR_NPSIZE5_Msk        (0x1UL << DSI_VNPCCR_NPSIZE5_Pos)         /*!< 0x00000020 */
8889 #define DSI_VNPCCR_NPSIZE5            DSI_VNPCCR_NPSIZE5_Msk
8890 #define DSI_VNPCCR_NPSIZE6_Pos        (6U)
8891 #define DSI_VNPCCR_NPSIZE6_Msk        (0x1UL << DSI_VNPCCR_NPSIZE6_Pos)         /*!< 0x00000040 */
8892 #define DSI_VNPCCR_NPSIZE6            DSI_VNPCCR_NPSIZE6_Msk
8893 #define DSI_VNPCCR_NPSIZE7_Pos        (7U)
8894 #define DSI_VNPCCR_NPSIZE7_Msk        (0x1UL << DSI_VNPCCR_NPSIZE7_Pos)         /*!< 0x00000080 */
8895 #define DSI_VNPCCR_NPSIZE7            DSI_VNPCCR_NPSIZE7_Msk
8896 #define DSI_VNPCCR_NPSIZE8_Pos        (8U)
8897 #define DSI_VNPCCR_NPSIZE8_Msk        (0x1UL << DSI_VNPCCR_NPSIZE8_Pos)         /*!< 0x00000100 */
8898 #define DSI_VNPCCR_NPSIZE8            DSI_VNPCCR_NPSIZE8_Msk
8899 #define DSI_VNPCCR_NPSIZE9_Pos        (9U)
8900 #define DSI_VNPCCR_NPSIZE9_Msk        (0x1UL << DSI_VNPCCR_NPSIZE9_Pos)         /*!< 0x00000200 */
8901 #define DSI_VNPCCR_NPSIZE9            DSI_VNPCCR_NPSIZE9_Msk
8902 #define DSI_VNPCCR_NPSIZE10_Pos       (10U)
8903 #define DSI_VNPCCR_NPSIZE10_Msk       (0x1UL << DSI_VNPCCR_NPSIZE10_Pos)        /*!< 0x00000400 */
8904 #define DSI_VNPCCR_NPSIZE10           DSI_VNPCCR_NPSIZE10_Msk
8905 #define DSI_VNPCCR_NPSIZE11_Pos       (11U)
8906 #define DSI_VNPCCR_NPSIZE11_Msk       (0x1UL << DSI_VNPCCR_NPSIZE11_Pos)        /*!< 0x00000800 */
8907 #define DSI_VNPCCR_NPSIZE11           DSI_VNPCCR_NPSIZE11_Msk
8908 #define DSI_VNPCCR_NPSIZE12_Pos       (12U)
8909 #define DSI_VNPCCR_NPSIZE12_Msk       (0x1UL << DSI_VNPCCR_NPSIZE12_Pos)        /*!< 0x00001000 */
8910 #define DSI_VNPCCR_NPSIZE12           DSI_VNPCCR_NPSIZE12_Msk
8911 
8912 /*******************  Bit definition for DSI_VHSACCR register  ************/
8913 #define DSI_VHSACCR_HSA_Pos           (0U)
8914 #define DSI_VHSACCR_HSA_Msk           (0xFFFUL << DSI_VHSACCR_HSA_Pos)          /*!< 0x00000FFF */
8915 #define DSI_VHSACCR_HSA               DSI_VHSACCR_HSA_Msk                      /*!< Horizontal Synchronism Active duration */
8916 #define DSI_VHSACCR_HSA0_Pos          (0U)
8917 #define DSI_VHSACCR_HSA0_Msk          (0x1UL << DSI_VHSACCR_HSA0_Pos)           /*!< 0x00000001 */
8918 #define DSI_VHSACCR_HSA0              DSI_VHSACCR_HSA0_Msk
8919 #define DSI_VHSACCR_HSA1_Pos          (1U)
8920 #define DSI_VHSACCR_HSA1_Msk          (0x1UL << DSI_VHSACCR_HSA1_Pos)           /*!< 0x00000002 */
8921 #define DSI_VHSACCR_HSA1              DSI_VHSACCR_HSA1_Msk
8922 #define DSI_VHSACCR_HSA2_Pos          (2U)
8923 #define DSI_VHSACCR_HSA2_Msk          (0x1UL << DSI_VHSACCR_HSA2_Pos)           /*!< 0x00000004 */
8924 #define DSI_VHSACCR_HSA2              DSI_VHSACCR_HSA2_Msk
8925 #define DSI_VHSACCR_HSA3_Pos          (3U)
8926 #define DSI_VHSACCR_HSA3_Msk          (0x1UL << DSI_VHSACCR_HSA3_Pos)           /*!< 0x00000008 */
8927 #define DSI_VHSACCR_HSA3              DSI_VHSACCR_HSA3_Msk
8928 #define DSI_VHSACCR_HSA4_Pos          (4U)
8929 #define DSI_VHSACCR_HSA4_Msk          (0x1UL << DSI_VHSACCR_HSA4_Pos)           /*!< 0x00000010 */
8930 #define DSI_VHSACCR_HSA4              DSI_VHSACCR_HSA4_Msk
8931 #define DSI_VHSACCR_HSA5_Pos          (5U)
8932 #define DSI_VHSACCR_HSA5_Msk          (0x1UL << DSI_VHSACCR_HSA5_Pos)           /*!< 0x00000020 */
8933 #define DSI_VHSACCR_HSA5              DSI_VHSACCR_HSA5_Msk
8934 #define DSI_VHSACCR_HSA6_Pos          (6U)
8935 #define DSI_VHSACCR_HSA6_Msk          (0x1UL << DSI_VHSACCR_HSA6_Pos)           /*!< 0x00000040 */
8936 #define DSI_VHSACCR_HSA6              DSI_VHSACCR_HSA6_Msk
8937 #define DSI_VHSACCR_HSA7_Pos          (7U)
8938 #define DSI_VHSACCR_HSA7_Msk          (0x1UL << DSI_VHSACCR_HSA7_Pos)           /*!< 0x00000080 */
8939 #define DSI_VHSACCR_HSA7              DSI_VHSACCR_HSA7_Msk
8940 #define DSI_VHSACCR_HSA8_Pos          (8U)
8941 #define DSI_VHSACCR_HSA8_Msk          (0x1UL << DSI_VHSACCR_HSA8_Pos)           /*!< 0x00000100 */
8942 #define DSI_VHSACCR_HSA8              DSI_VHSACCR_HSA8_Msk
8943 #define DSI_VHSACCR_HSA9_Pos          (9U)
8944 #define DSI_VHSACCR_HSA9_Msk          (0x1UL << DSI_VHSACCR_HSA9_Pos)           /*!< 0x00000200 */
8945 #define DSI_VHSACCR_HSA9              DSI_VHSACCR_HSA9_Msk
8946 #define DSI_VHSACCR_HSA10_Pos         (10U)
8947 #define DSI_VHSACCR_HSA10_Msk         (0x1UL << DSI_VHSACCR_HSA10_Pos)          /*!< 0x00000400 */
8948 #define DSI_VHSACCR_HSA10             DSI_VHSACCR_HSA10_Msk
8949 #define DSI_VHSACCR_HSA11_Pos         (11U)
8950 #define DSI_VHSACCR_HSA11_Msk         (0x1UL << DSI_VHSACCR_HSA11_Pos)          /*!< 0x00000800 */
8951 #define DSI_VHSACCR_HSA11             DSI_VHSACCR_HSA11_Msk
8952 
8953 /*******************  Bit definition for DSI_VHBPCCR register  ************/
8954 #define DSI_VHBPCCR_HBP_Pos           (0U)
8955 #define DSI_VHBPCCR_HBP_Msk           (0xFFFUL << DSI_VHBPCCR_HBP_Pos)          /*!< 0x00000FFF */
8956 #define DSI_VHBPCCR_HBP               DSI_VHBPCCR_HBP_Msk                      /*!< Horizontal Back-Porch duration */
8957 #define DSI_VHBPCCR_HBP0_Pos          (0U)
8958 #define DSI_VHBPCCR_HBP0_Msk          (0x1UL << DSI_VHBPCCR_HBP0_Pos)           /*!< 0x00000001 */
8959 #define DSI_VHBPCCR_HBP0              DSI_VHBPCCR_HBP0_Msk
8960 #define DSI_VHBPCCR_HBP1_Pos          (1U)
8961 #define DSI_VHBPCCR_HBP1_Msk          (0x1UL << DSI_VHBPCCR_HBP1_Pos)           /*!< 0x00000002 */
8962 #define DSI_VHBPCCR_HBP1              DSI_VHBPCCR_HBP1_Msk
8963 #define DSI_VHBPCCR_HBP2_Pos          (2U)
8964 #define DSI_VHBPCCR_HBP2_Msk          (0x1UL << DSI_VHBPCCR_HBP2_Pos)           /*!< 0x00000004 */
8965 #define DSI_VHBPCCR_HBP2              DSI_VHBPCCR_HBP2_Msk
8966 #define DSI_VHBPCCR_HBP3_Pos          (3U)
8967 #define DSI_VHBPCCR_HBP3_Msk          (0x1UL << DSI_VHBPCCR_HBP3_Pos)           /*!< 0x00000008 */
8968 #define DSI_VHBPCCR_HBP3              DSI_VHBPCCR_HBP3_Msk
8969 #define DSI_VHBPCCR_HBP4_Pos          (4U)
8970 #define DSI_VHBPCCR_HBP4_Msk          (0x1UL << DSI_VHBPCCR_HBP4_Pos)           /*!< 0x00000010 */
8971 #define DSI_VHBPCCR_HBP4              DSI_VHBPCCR_HBP4_Msk
8972 #define DSI_VHBPCCR_HBP5_Pos          (5U)
8973 #define DSI_VHBPCCR_HBP5_Msk          (0x1UL << DSI_VHBPCCR_HBP5_Pos)           /*!< 0x00000020 */
8974 #define DSI_VHBPCCR_HBP5              DSI_VHBPCCR_HBP5_Msk
8975 #define DSI_VHBPCCR_HBP6_Pos          (6U)
8976 #define DSI_VHBPCCR_HBP6_Msk          (0x1UL << DSI_VHBPCCR_HBP6_Pos)           /*!< 0x00000040 */
8977 #define DSI_VHBPCCR_HBP6              DSI_VHBPCCR_HBP6_Msk
8978 #define DSI_VHBPCCR_HBP7_Pos          (7U)
8979 #define DSI_VHBPCCR_HBP7_Msk          (0x1UL << DSI_VHBPCCR_HBP7_Pos)           /*!< 0x00000080 */
8980 #define DSI_VHBPCCR_HBP7              DSI_VHBPCCR_HBP7_Msk
8981 #define DSI_VHBPCCR_HBP8_Pos          (8U)
8982 #define DSI_VHBPCCR_HBP8_Msk          (0x1UL << DSI_VHBPCCR_HBP8_Pos)           /*!< 0x00000100 */
8983 #define DSI_VHBPCCR_HBP8              DSI_VHBPCCR_HBP8_Msk
8984 #define DSI_VHBPCCR_HBP9_Pos          (9U)
8985 #define DSI_VHBPCCR_HBP9_Msk          (0x1UL << DSI_VHBPCCR_HBP9_Pos)           /*!< 0x00000200 */
8986 #define DSI_VHBPCCR_HBP9              DSI_VHBPCCR_HBP9_Msk
8987 #define DSI_VHBPCCR_HBP10_Pos         (10U)
8988 #define DSI_VHBPCCR_HBP10_Msk         (0x1UL << DSI_VHBPCCR_HBP10_Pos)          /*!< 0x00000400 */
8989 #define DSI_VHBPCCR_HBP10             DSI_VHBPCCR_HBP10_Msk
8990 #define DSI_VHBPCCR_HBP11_Pos         (11U)
8991 #define DSI_VHBPCCR_HBP11_Msk         (0x1UL << DSI_VHBPCCR_HBP11_Pos)          /*!< 0x00000800 */
8992 #define DSI_VHBPCCR_HBP11             DSI_VHBPCCR_HBP11_Msk
8993 
8994 /*******************  Bit definition for DSI_VLCCR register  **************/
8995 #define DSI_VLCCR_HLINE_Pos           (0U)
8996 #define DSI_VLCCR_HLINE_Msk           (0x7FFFUL << DSI_VLCCR_HLINE_Pos)         /*!< 0x00007FFF */
8997 #define DSI_VLCCR_HLINE               DSI_VLCCR_HLINE_Msk                      /*!< Horizontal Line duration */
8998 #define DSI_VLCCR_HLINE0_Pos          (0U)
8999 #define DSI_VLCCR_HLINE0_Msk          (0x1UL << DSI_VLCCR_HLINE0_Pos)           /*!< 0x00000001 */
9000 #define DSI_VLCCR_HLINE0              DSI_VLCCR_HLINE0_Msk
9001 #define DSI_VLCCR_HLINE1_Pos          (1U)
9002 #define DSI_VLCCR_HLINE1_Msk          (0x1UL << DSI_VLCCR_HLINE1_Pos)           /*!< 0x00000002 */
9003 #define DSI_VLCCR_HLINE1              DSI_VLCCR_HLINE1_Msk
9004 #define DSI_VLCCR_HLINE2_Pos          (2U)
9005 #define DSI_VLCCR_HLINE2_Msk          (0x1UL << DSI_VLCCR_HLINE2_Pos)           /*!< 0x00000004 */
9006 #define DSI_VLCCR_HLINE2              DSI_VLCCR_HLINE2_Msk
9007 #define DSI_VLCCR_HLINE3_Pos          (3U)
9008 #define DSI_VLCCR_HLINE3_Msk          (0x1UL << DSI_VLCCR_HLINE3_Pos)           /*!< 0x00000008 */
9009 #define DSI_VLCCR_HLINE3              DSI_VLCCR_HLINE3_Msk
9010 #define DSI_VLCCR_HLINE4_Pos          (4U)
9011 #define DSI_VLCCR_HLINE4_Msk          (0x1UL << DSI_VLCCR_HLINE4_Pos)           /*!< 0x00000010 */
9012 #define DSI_VLCCR_HLINE4              DSI_VLCCR_HLINE4_Msk
9013 #define DSI_VLCCR_HLINE5_Pos          (5U)
9014 #define DSI_VLCCR_HLINE5_Msk          (0x1UL << DSI_VLCCR_HLINE5_Pos)           /*!< 0x00000020 */
9015 #define DSI_VLCCR_HLINE5              DSI_VLCCR_HLINE5_Msk
9016 #define DSI_VLCCR_HLINE6_Pos          (6U)
9017 #define DSI_VLCCR_HLINE6_Msk          (0x1UL << DSI_VLCCR_HLINE6_Pos)           /*!< 0x00000040 */
9018 #define DSI_VLCCR_HLINE6              DSI_VLCCR_HLINE6_Msk
9019 #define DSI_VLCCR_HLINE7_Pos          (7U)
9020 #define DSI_VLCCR_HLINE7_Msk          (0x1UL << DSI_VLCCR_HLINE7_Pos)           /*!< 0x00000080 */
9021 #define DSI_VLCCR_HLINE7              DSI_VLCCR_HLINE7_Msk
9022 #define DSI_VLCCR_HLINE8_Pos          (8U)
9023 #define DSI_VLCCR_HLINE8_Msk          (0x1UL << DSI_VLCCR_HLINE8_Pos)           /*!< 0x00000100 */
9024 #define DSI_VLCCR_HLINE8              DSI_VLCCR_HLINE8_Msk
9025 #define DSI_VLCCR_HLINE9_Pos          (9U)
9026 #define DSI_VLCCR_HLINE9_Msk          (0x1UL << DSI_VLCCR_HLINE9_Pos)           /*!< 0x00000200 */
9027 #define DSI_VLCCR_HLINE9              DSI_VLCCR_HLINE9_Msk
9028 #define DSI_VLCCR_HLINE10_Pos         (10U)
9029 #define DSI_VLCCR_HLINE10_Msk         (0x1UL << DSI_VLCCR_HLINE10_Pos)          /*!< 0x00000400 */
9030 #define DSI_VLCCR_HLINE10             DSI_VLCCR_HLINE10_Msk
9031 #define DSI_VLCCR_HLINE11_Pos         (11U)
9032 #define DSI_VLCCR_HLINE11_Msk         (0x1UL << DSI_VLCCR_HLINE11_Pos)          /*!< 0x00000800 */
9033 #define DSI_VLCCR_HLINE11             DSI_VLCCR_HLINE11_Msk
9034 #define DSI_VLCCR_HLINE12_Pos         (12U)
9035 #define DSI_VLCCR_HLINE12_Msk         (0x1UL << DSI_VLCCR_HLINE12_Pos)          /*!< 0x00001000 */
9036 #define DSI_VLCCR_HLINE12             DSI_VLCCR_HLINE12_Msk
9037 #define DSI_VLCCR_HLINE13_Pos         (13U)
9038 #define DSI_VLCCR_HLINE13_Msk         (0x1UL << DSI_VLCCR_HLINE13_Pos)          /*!< 0x00002000 */
9039 #define DSI_VLCCR_HLINE13             DSI_VLCCR_HLINE13_Msk
9040 #define DSI_VLCCR_HLINE14_Pos         (14U)
9041 #define DSI_VLCCR_HLINE14_Msk         (0x1UL << DSI_VLCCR_HLINE14_Pos)          /*!< 0x00004000 */
9042 #define DSI_VLCCR_HLINE14             DSI_VLCCR_HLINE14_Msk
9043 
9044 /*******************  Bit definition for DSI_VVSACCR register  ***************/
9045 #define DSI_VVSACCR_VSA_Pos           (0U)
9046 #define DSI_VVSACCR_VSA_Msk           (0x3FFUL << DSI_VVSACCR_VSA_Pos)          /*!< 0x000003FF */
9047 #define DSI_VVSACCR_VSA               DSI_VVSACCR_VSA_Msk                      /*!< Vertical Synchronism Active duration */
9048 #define DSI_VVSACCR_VSA0_Pos          (0U)
9049 #define DSI_VVSACCR_VSA0_Msk          (0x1UL << DSI_VVSACCR_VSA0_Pos)           /*!< 0x00000001 */
9050 #define DSI_VVSACCR_VSA0              DSI_VVSACCR_VSA0_Msk
9051 #define DSI_VVSACCR_VSA1_Pos          (1U)
9052 #define DSI_VVSACCR_VSA1_Msk          (0x1UL << DSI_VVSACCR_VSA1_Pos)           /*!< 0x00000002 */
9053 #define DSI_VVSACCR_VSA1              DSI_VVSACCR_VSA1_Msk
9054 #define DSI_VVSACCR_VSA2_Pos          (2U)
9055 #define DSI_VVSACCR_VSA2_Msk          (0x1UL << DSI_VVSACCR_VSA2_Pos)           /*!< 0x00000004 */
9056 #define DSI_VVSACCR_VSA2              DSI_VVSACCR_VSA2_Msk
9057 #define DSI_VVSACCR_VSA3_Pos          (3U)
9058 #define DSI_VVSACCR_VSA3_Msk          (0x1UL << DSI_VVSACCR_VSA3_Pos)           /*!< 0x00000008 */
9059 #define DSI_VVSACCR_VSA3              DSI_VVSACCR_VSA3_Msk
9060 #define DSI_VVSACCR_VSA4_Pos          (4U)
9061 #define DSI_VVSACCR_VSA4_Msk          (0x1UL << DSI_VVSACCR_VSA4_Pos)           /*!< 0x00000010 */
9062 #define DSI_VVSACCR_VSA4              DSI_VVSACCR_VSA4_Msk
9063 #define DSI_VVSACCR_VSA5_Pos          (5U)
9064 #define DSI_VVSACCR_VSA5_Msk          (0x1UL << DSI_VVSACCR_VSA5_Pos)           /*!< 0x00000020 */
9065 #define DSI_VVSACCR_VSA5              DSI_VVSACCR_VSA5_Msk
9066 #define DSI_VVSACCR_VSA6_Pos          (6U)
9067 #define DSI_VVSACCR_VSA6_Msk          (0x1UL << DSI_VVSACCR_VSA6_Pos)           /*!< 0x00000040 */
9068 #define DSI_VVSACCR_VSA6              DSI_VVSACCR_VSA6_Msk
9069 #define DSI_VVSACCR_VSA7_Pos          (7U)
9070 #define DSI_VVSACCR_VSA7_Msk          (0x1UL << DSI_VVSACCR_VSA7_Pos)           /*!< 0x00000080 */
9071 #define DSI_VVSACCR_VSA7              DSI_VVSACCR_VSA7_Msk
9072 #define DSI_VVSACCR_VSA8_Pos          (8U)
9073 #define DSI_VVSACCR_VSA8_Msk          (0x1UL << DSI_VVSACCR_VSA8_Pos)           /*!< 0x00000100 */
9074 #define DSI_VVSACCR_VSA8              DSI_VVSACCR_VSA8_Msk
9075 #define DSI_VVSACCR_VSA9_Pos          (9U)
9076 #define DSI_VVSACCR_VSA9_Msk          (0x1UL << DSI_VVSACCR_VSA9_Pos)           /*!< 0x00000200 */
9077 #define DSI_VVSACCR_VSA9              DSI_VVSACCR_VSA9_Msk
9078 
9079 /*******************  Bit definition for DSI_VVBPCCR register  ************/
9080 #define DSI_VVBPCCR_VBP_Pos           (0U)
9081 #define DSI_VVBPCCR_VBP_Msk           (0x3FFUL << DSI_VVBPCCR_VBP_Pos)          /*!< 0x000003FF */
9082 #define DSI_VVBPCCR_VBP               DSI_VVBPCCR_VBP_Msk                      /*!< Vertical Back-Porch duration */
9083 #define DSI_VVBPCCR_VBP0_Pos          (0U)
9084 #define DSI_VVBPCCR_VBP0_Msk          (0x1UL << DSI_VVBPCCR_VBP0_Pos)           /*!< 0x00000001 */
9085 #define DSI_VVBPCCR_VBP0              DSI_VVBPCCR_VBP0_Msk
9086 #define DSI_VVBPCCR_VBP1_Pos          (1U)
9087 #define DSI_VVBPCCR_VBP1_Msk          (0x1UL << DSI_VVBPCCR_VBP1_Pos)           /*!< 0x00000002 */
9088 #define DSI_VVBPCCR_VBP1              DSI_VVBPCCR_VBP1_Msk
9089 #define DSI_VVBPCCR_VBP2_Pos          (2U)
9090 #define DSI_VVBPCCR_VBP2_Msk          (0x1UL << DSI_VVBPCCR_VBP2_Pos)           /*!< 0x00000004 */
9091 #define DSI_VVBPCCR_VBP2              DSI_VVBPCCR_VBP2_Msk
9092 #define DSI_VVBPCCR_VBP3_Pos          (3U)
9093 #define DSI_VVBPCCR_VBP3_Msk          (0x1UL << DSI_VVBPCCR_VBP3_Pos)           /*!< 0x00000008 */
9094 #define DSI_VVBPCCR_VBP3              DSI_VVBPCCR_VBP3_Msk
9095 #define DSI_VVBPCCR_VBP4_Pos          (4U)
9096 #define DSI_VVBPCCR_VBP4_Msk          (0x1UL << DSI_VVBPCCR_VBP4_Pos)           /*!< 0x00000010 */
9097 #define DSI_VVBPCCR_VBP4              DSI_VVBPCCR_VBP4_Msk
9098 #define DSI_VVBPCCR_VBP5_Pos          (5U)
9099 #define DSI_VVBPCCR_VBP5_Msk          (0x1UL << DSI_VVBPCCR_VBP5_Pos)           /*!< 0x00000020 */
9100 #define DSI_VVBPCCR_VBP5              DSI_VVBPCCR_VBP5_Msk
9101 #define DSI_VVBPCCR_VBP6_Pos          (6U)
9102 #define DSI_VVBPCCR_VBP6_Msk          (0x1UL << DSI_VVBPCCR_VBP6_Pos)           /*!< 0x00000040 */
9103 #define DSI_VVBPCCR_VBP6              DSI_VVBPCCR_VBP6_Msk
9104 #define DSI_VVBPCCR_VBP7_Pos          (7U)
9105 #define DSI_VVBPCCR_VBP7_Msk          (0x1UL << DSI_VVBPCCR_VBP7_Pos)           /*!< 0x00000080 */
9106 #define DSI_VVBPCCR_VBP7              DSI_VVBPCCR_VBP7_Msk
9107 #define DSI_VVBPCCR_VBP8_Pos          (8U)
9108 #define DSI_VVBPCCR_VBP8_Msk          (0x1UL << DSI_VVBPCCR_VBP8_Pos)           /*!< 0x00000100 */
9109 #define DSI_VVBPCCR_VBP8              DSI_VVBPCCR_VBP8_Msk
9110 #define DSI_VVBPCCR_VBP9_Pos          (9U)
9111 #define DSI_VVBPCCR_VBP9_Msk          (0x1UL << DSI_VVBPCCR_VBP9_Pos)           /*!< 0x00000200 */
9112 #define DSI_VVBPCCR_VBP9              DSI_VVBPCCR_VBP9_Msk
9113 
9114 /*******************  Bit definition for DSI_VVFPCCR register  ************/
9115 #define DSI_VVFPCCR_VFP_Pos           (0U)
9116 #define DSI_VVFPCCR_VFP_Msk           (0x3FFUL << DSI_VVFPCCR_VFP_Pos)          /*!< 0x000003FF */
9117 #define DSI_VVFPCCR_VFP               DSI_VVFPCCR_VFP_Msk                      /*!< Vertical Front-Porch duration */
9118 #define DSI_VVFPCCR_VFP0_Pos          (0U)
9119 #define DSI_VVFPCCR_VFP0_Msk          (0x1UL << DSI_VVFPCCR_VFP0_Pos)           /*!< 0x00000001 */
9120 #define DSI_VVFPCCR_VFP0              DSI_VVFPCCR_VFP0_Msk
9121 #define DSI_VVFPCCR_VFP1_Pos          (1U)
9122 #define DSI_VVFPCCR_VFP1_Msk          (0x1UL << DSI_VVFPCCR_VFP1_Pos)           /*!< 0x00000002 */
9123 #define DSI_VVFPCCR_VFP1              DSI_VVFPCCR_VFP1_Msk
9124 #define DSI_VVFPCCR_VFP2_Pos          (2U)
9125 #define DSI_VVFPCCR_VFP2_Msk          (0x1UL << DSI_VVFPCCR_VFP2_Pos)           /*!< 0x00000004 */
9126 #define DSI_VVFPCCR_VFP2              DSI_VVFPCCR_VFP2_Msk
9127 #define DSI_VVFPCCR_VFP3_Pos          (3U)
9128 #define DSI_VVFPCCR_VFP3_Msk          (0x1UL << DSI_VVFPCCR_VFP3_Pos)           /*!< 0x00000008 */
9129 #define DSI_VVFPCCR_VFP3              DSI_VVFPCCR_VFP3_Msk
9130 #define DSI_VVFPCCR_VFP4_Pos          (4U)
9131 #define DSI_VVFPCCR_VFP4_Msk          (0x1UL << DSI_VVFPCCR_VFP4_Pos)           /*!< 0x00000010 */
9132 #define DSI_VVFPCCR_VFP4              DSI_VVFPCCR_VFP4_Msk
9133 #define DSI_VVFPCCR_VFP5_Pos          (5U)
9134 #define DSI_VVFPCCR_VFP5_Msk          (0x1UL << DSI_VVFPCCR_VFP5_Pos)           /*!< 0x00000020 */
9135 #define DSI_VVFPCCR_VFP5              DSI_VVFPCCR_VFP5_Msk
9136 #define DSI_VVFPCCR_VFP6_Pos          (6U)
9137 #define DSI_VVFPCCR_VFP6_Msk          (0x1UL << DSI_VVFPCCR_VFP6_Pos)           /*!< 0x00000040 */
9138 #define DSI_VVFPCCR_VFP6              DSI_VVFPCCR_VFP6_Msk
9139 #define DSI_VVFPCCR_VFP7_Pos          (7U)
9140 #define DSI_VVFPCCR_VFP7_Msk          (0x1UL << DSI_VVFPCCR_VFP7_Pos)           /*!< 0x00000080 */
9141 #define DSI_VVFPCCR_VFP7              DSI_VVFPCCR_VFP7_Msk
9142 #define DSI_VVFPCCR_VFP8_Pos          (8U)
9143 #define DSI_VVFPCCR_VFP8_Msk          (0x1UL << DSI_VVFPCCR_VFP8_Pos)           /*!< 0x00000100 */
9144 #define DSI_VVFPCCR_VFP8              DSI_VVFPCCR_VFP8_Msk
9145 #define DSI_VVFPCCR_VFP9_Pos          (9U)
9146 #define DSI_VVFPCCR_VFP9_Msk          (0x1UL << DSI_VVFPCCR_VFP9_Pos)           /*!< 0x00000200 */
9147 #define DSI_VVFPCCR_VFP9              DSI_VVFPCCR_VFP9_Msk
9148 
9149 /*******************  Bit definition for DSI_VVACCR register  *************/
9150 #define DSI_VVACCR_VA_Pos             (0U)
9151 #define DSI_VVACCR_VA_Msk             (0x3FFFUL << DSI_VVACCR_VA_Pos)           /*!< 0x00003FFF */
9152 #define DSI_VVACCR_VA                 DSI_VVACCR_VA_Msk                        /*!< Vertical Active duration */
9153 #define DSI_VVACCR_VA0_Pos            (0U)
9154 #define DSI_VVACCR_VA0_Msk            (0x1UL << DSI_VVACCR_VA0_Pos)             /*!< 0x00000001 */
9155 #define DSI_VVACCR_VA0                DSI_VVACCR_VA0_Msk
9156 #define DSI_VVACCR_VA1_Pos            (1U)
9157 #define DSI_VVACCR_VA1_Msk            (0x1UL << DSI_VVACCR_VA1_Pos)             /*!< 0x00000002 */
9158 #define DSI_VVACCR_VA1                DSI_VVACCR_VA1_Msk
9159 #define DSI_VVACCR_VA2_Pos            (2U)
9160 #define DSI_VVACCR_VA2_Msk            (0x1UL << DSI_VVACCR_VA2_Pos)             /*!< 0x00000004 */
9161 #define DSI_VVACCR_VA2                DSI_VVACCR_VA2_Msk
9162 #define DSI_VVACCR_VA3_Pos            (3U)
9163 #define DSI_VVACCR_VA3_Msk            (0x1UL << DSI_VVACCR_VA3_Pos)             /*!< 0x00000008 */
9164 #define DSI_VVACCR_VA3                DSI_VVACCR_VA3_Msk
9165 #define DSI_VVACCR_VA4_Pos            (4U)
9166 #define DSI_VVACCR_VA4_Msk            (0x1UL << DSI_VVACCR_VA4_Pos)             /*!< 0x00000010 */
9167 #define DSI_VVACCR_VA4                DSI_VVACCR_VA4_Msk
9168 #define DSI_VVACCR_VA5_Pos            (5U)
9169 #define DSI_VVACCR_VA5_Msk            (0x1UL << DSI_VVACCR_VA5_Pos)             /*!< 0x00000020 */
9170 #define DSI_VVACCR_VA5                DSI_VVACCR_VA5_Msk
9171 #define DSI_VVACCR_VA6_Pos            (6U)
9172 #define DSI_VVACCR_VA6_Msk            (0x1UL << DSI_VVACCR_VA6_Pos)             /*!< 0x00000040 */
9173 #define DSI_VVACCR_VA6                DSI_VVACCR_VA6_Msk
9174 #define DSI_VVACCR_VA7_Pos            (7U)
9175 #define DSI_VVACCR_VA7_Msk            (0x1UL << DSI_VVACCR_VA7_Pos)             /*!< 0x00000080 */
9176 #define DSI_VVACCR_VA7                DSI_VVACCR_VA7_Msk
9177 #define DSI_VVACCR_VA8_Pos            (8U)
9178 #define DSI_VVACCR_VA8_Msk            (0x1UL << DSI_VVACCR_VA8_Pos)             /*!< 0x00000100 */
9179 #define DSI_VVACCR_VA8                DSI_VVACCR_VA8_Msk
9180 #define DSI_VVACCR_VA9_Pos            (9U)
9181 #define DSI_VVACCR_VA9_Msk            (0x1UL << DSI_VVACCR_VA9_Pos)             /*!< 0x00000200 */
9182 #define DSI_VVACCR_VA9                DSI_VVACCR_VA9_Msk
9183 #define DSI_VVACCR_VA10_Pos           (10U)
9184 #define DSI_VVACCR_VA10_Msk           (0x1UL << DSI_VVACCR_VA10_Pos)            /*!< 0x00000400 */
9185 #define DSI_VVACCR_VA10               DSI_VVACCR_VA10_Msk
9186 #define DSI_VVACCR_VA11_Pos           (11U)
9187 #define DSI_VVACCR_VA11_Msk           (0x1UL << DSI_VVACCR_VA11_Pos)            /*!< 0x00000800 */
9188 #define DSI_VVACCR_VA11               DSI_VVACCR_VA11_Msk
9189 #define DSI_VVACCR_VA12_Pos           (12U)
9190 #define DSI_VVACCR_VA12_Msk           (0x1UL << DSI_VVACCR_VA12_Pos)            /*!< 0x00001000 */
9191 #define DSI_VVACCR_VA12               DSI_VVACCR_VA12_Msk
9192 #define DSI_VVACCR_VA13_Pos           (13U)
9193 #define DSI_VVACCR_VA13_Msk           (0x1UL << DSI_VVACCR_VA13_Pos)            /*!< 0x00002000 */
9194 #define DSI_VVACCR_VA13               DSI_VVACCR_VA13_Msk
9195 
9196 /*******************  Bit definition for DSI_TDCCR register  **************/
9197 #define DSI_TDCCR_3DM                 0x00000003U                              /*!< 3D Mode */
9198 #define DSI_TDCCR_3DM0                0x00000001U
9199 #define DSI_TDCCR_3DM1                0x00000002U
9200 
9201 #define DSI_TDCCR_3DF                 0x0000000CU                              /*!< 3D Format */
9202 #define DSI_TDCCR_3DF0                0x00000004U
9203 #define DSI_TDCCR_3DF1                0x00000008U
9204 
9205 #define DSI_TDCCR_SVS_Pos             (4U)
9206 #define DSI_TDCCR_SVS_Msk             (0x1UL << DSI_TDCCR_SVS_Pos)              /*!< 0x00000010 */
9207 #define DSI_TDCCR_SVS                 DSI_TDCCR_SVS_Msk                        /*!< Second VSYNC */
9208 #define DSI_TDCCR_RF_Pos              (5U)
9209 #define DSI_TDCCR_RF_Msk              (0x1UL << DSI_TDCCR_RF_Pos)               /*!< 0x00000020 */
9210 #define DSI_TDCCR_RF                  DSI_TDCCR_RF_Msk                         /*!< Right First */
9211 #define DSI_TDCCR_S3DC_Pos            (16U)
9212 #define DSI_TDCCR_S3DC_Msk            (0x1UL << DSI_TDCCR_S3DC_Pos)             /*!< 0x00010000 */
9213 #define DSI_TDCCR_S3DC                DSI_TDCCR_S3DC_Msk                       /*!< Send 3D Control */
9214 
9215 /*******************  Bit definition for DSI_WCFGR register  ***************/
9216 #define DSI_WCFGR_DSIM_Pos            (0U)
9217 #define DSI_WCFGR_DSIM_Msk            (0x1UL << DSI_WCFGR_DSIM_Pos)             /*!< 0x00000001 */
9218 #define DSI_WCFGR_DSIM                DSI_WCFGR_DSIM_Msk                       /*!< DSI Mode */
9219 #define DSI_WCFGR_COLMUX_Pos          (1U)
9220 #define DSI_WCFGR_COLMUX_Msk          (0x7UL << DSI_WCFGR_COLMUX_Pos)           /*!< 0x0000000E */
9221 #define DSI_WCFGR_COLMUX              DSI_WCFGR_COLMUX_Msk                     /*!< Color Multiplexing */
9222 #define DSI_WCFGR_COLMUX0_Pos         (1U)
9223 #define DSI_WCFGR_COLMUX0_Msk         (0x1UL << DSI_WCFGR_COLMUX0_Pos)          /*!< 0x00000002 */
9224 #define DSI_WCFGR_COLMUX0             DSI_WCFGR_COLMUX0_Msk
9225 #define DSI_WCFGR_COLMUX1_Pos         (2U)
9226 #define DSI_WCFGR_COLMUX1_Msk         (0x1UL << DSI_WCFGR_COLMUX1_Pos)          /*!< 0x00000004 */
9227 #define DSI_WCFGR_COLMUX1             DSI_WCFGR_COLMUX1_Msk
9228 #define DSI_WCFGR_COLMUX2_Pos         (3U)
9229 #define DSI_WCFGR_COLMUX2_Msk         (0x1UL << DSI_WCFGR_COLMUX2_Pos)          /*!< 0x00000008 */
9230 #define DSI_WCFGR_COLMUX2             DSI_WCFGR_COLMUX2_Msk
9231 
9232 #define DSI_WCFGR_TESRC_Pos           (4U)
9233 #define DSI_WCFGR_TESRC_Msk           (0x1UL << DSI_WCFGR_TESRC_Pos)            /*!< 0x00000010 */
9234 #define DSI_WCFGR_TESRC               DSI_WCFGR_TESRC_Msk                      /*!< Tearing Effect Source */
9235 #define DSI_WCFGR_TEPOL_Pos           (5U)
9236 #define DSI_WCFGR_TEPOL_Msk           (0x1UL << DSI_WCFGR_TEPOL_Pos)            /*!< 0x00000020 */
9237 #define DSI_WCFGR_TEPOL               DSI_WCFGR_TEPOL_Msk                      /*!< Tearing Effect Polarity */
9238 #define DSI_WCFGR_AR_Pos              (6U)
9239 #define DSI_WCFGR_AR_Msk              (0x1UL << DSI_WCFGR_AR_Pos)               /*!< 0x00000040 */
9240 #define DSI_WCFGR_AR                  DSI_WCFGR_AR_Msk                         /*!< Automatic Refresh */
9241 #define DSI_WCFGR_VSPOL_Pos           (7U)
9242 #define DSI_WCFGR_VSPOL_Msk           (0x1UL << DSI_WCFGR_VSPOL_Pos)            /*!< 0x00000080 */
9243 #define DSI_WCFGR_VSPOL               DSI_WCFGR_VSPOL_Msk                      /*!< VSync Polarity */
9244 
9245 /*******************  Bit definition for DSI_WCR register  *****************/
9246 #define DSI_WCR_COLM_Pos              (0U)
9247 #define DSI_WCR_COLM_Msk              (0x1UL << DSI_WCR_COLM_Pos)               /*!< 0x00000001 */
9248 #define DSI_WCR_COLM                  DSI_WCR_COLM_Msk                         /*!< Color Mode */
9249 #define DSI_WCR_SHTDN_Pos             (1U)
9250 #define DSI_WCR_SHTDN_Msk             (0x1UL << DSI_WCR_SHTDN_Pos)              /*!< 0x00000002 */
9251 #define DSI_WCR_SHTDN                 DSI_WCR_SHTDN_Msk                        /*!< Shutdown */
9252 #define DSI_WCR_LTDCEN_Pos            (2U)
9253 #define DSI_WCR_LTDCEN_Msk            (0x1UL << DSI_WCR_LTDCEN_Pos)             /*!< 0x00000004 */
9254 #define DSI_WCR_LTDCEN                DSI_WCR_LTDCEN_Msk                       /*!< LTDC Enable */
9255 #define DSI_WCR_DSIEN_Pos             (3U)
9256 #define DSI_WCR_DSIEN_Msk             (0x1UL << DSI_WCR_DSIEN_Pos)              /*!< 0x00000008 */
9257 #define DSI_WCR_DSIEN                 DSI_WCR_DSIEN_Msk                        /*!< DSI Enable */
9258 
9259 /*******************  Bit definition for DSI_WIER register  ****************/
9260 #define DSI_WIER_TEIE_Pos             (0U)
9261 #define DSI_WIER_TEIE_Msk             (0x1UL << DSI_WIER_TEIE_Pos)              /*!< 0x00000001 */
9262 #define DSI_WIER_TEIE                 DSI_WIER_TEIE_Msk                        /*!< Tearing Effect Interrupt Enable */
9263 #define DSI_WIER_ERIE_Pos             (1U)
9264 #define DSI_WIER_ERIE_Msk             (0x1UL << DSI_WIER_ERIE_Pos)              /*!< 0x00000002 */
9265 #define DSI_WIER_ERIE                 DSI_WIER_ERIE_Msk                        /*!< End of Refresh Interrupt Enable */
9266 #define DSI_WIER_PLLLIE_Pos           (9U)
9267 #define DSI_WIER_PLLLIE_Msk           (0x1UL << DSI_WIER_PLLLIE_Pos)            /*!< 0x00000200 */
9268 #define DSI_WIER_PLLLIE               DSI_WIER_PLLLIE_Msk                      /*!< PLL Lock Interrupt Enable */
9269 #define DSI_WIER_PLLUIE_Pos           (10U)
9270 #define DSI_WIER_PLLUIE_Msk           (0x1UL << DSI_WIER_PLLUIE_Pos)            /*!< 0x00000400 */
9271 #define DSI_WIER_PLLUIE               DSI_WIER_PLLUIE_Msk                      /*!< PLL Unlock Interrupt Enable */
9272 #define DSI_WIER_RRIE_Pos             (13U)
9273 #define DSI_WIER_RRIE_Msk             (0x1UL << DSI_WIER_RRIE_Pos)              /*!< 0x00002000 */
9274 #define DSI_WIER_RRIE                 DSI_WIER_RRIE_Msk                        /*!< Regulator Ready Interrupt Enable */
9275 
9276 /*******************  Bit definition for DSI_WISR register  ****************/
9277 #define DSI_WISR_TEIF_Pos             (0U)
9278 #define DSI_WISR_TEIF_Msk             (0x1UL << DSI_WISR_TEIF_Pos)              /*!< 0x00000001 */
9279 #define DSI_WISR_TEIF                 DSI_WISR_TEIF_Msk                        /*!< Tearing Effect Interrupt Flag */
9280 #define DSI_WISR_ERIF_Pos             (1U)
9281 #define DSI_WISR_ERIF_Msk             (0x1UL << DSI_WISR_ERIF_Pos)              /*!< 0x00000002 */
9282 #define DSI_WISR_ERIF                 DSI_WISR_ERIF_Msk                        /*!< End of Refresh Interrupt Flag */
9283 #define DSI_WISR_BUSY_Pos             (2U)
9284 #define DSI_WISR_BUSY_Msk             (0x1UL << DSI_WISR_BUSY_Pos)              /*!< 0x00000004 */
9285 #define DSI_WISR_BUSY                 DSI_WISR_BUSY_Msk                        /*!< Busy Flag */
9286 #define DSI_WISR_PLLLS_Pos            (8U)
9287 #define DSI_WISR_PLLLS_Msk            (0x1UL << DSI_WISR_PLLLS_Pos)             /*!< 0x00000100 */
9288 #define DSI_WISR_PLLLS                DSI_WISR_PLLLS_Msk                       /*!< PLL Lock Status */
9289 #define DSI_WISR_PLLLIF_Pos           (9U)
9290 #define DSI_WISR_PLLLIF_Msk           (0x1UL << DSI_WISR_PLLLIF_Pos)            /*!< 0x00000200 */
9291 #define DSI_WISR_PLLLIF               DSI_WISR_PLLLIF_Msk                      /*!< PLL Lock Interrupt Flag */
9292 #define DSI_WISR_PLLUIF_Pos           (10U)
9293 #define DSI_WISR_PLLUIF_Msk           (0x1UL << DSI_WISR_PLLUIF_Pos)            /*!< 0x00000400 */
9294 #define DSI_WISR_PLLUIF               DSI_WISR_PLLUIF_Msk                      /*!< PLL Unlock Interrupt Flag */
9295 #define DSI_WISR_RRS_Pos              (12U)
9296 #define DSI_WISR_RRS_Msk              (0x1UL << DSI_WISR_RRS_Pos)               /*!< 0x00001000 */
9297 #define DSI_WISR_RRS                  DSI_WISR_RRS_Msk                         /*!< Regulator Ready Flag */
9298 #define DSI_WISR_RRIF_Pos             (13U)
9299 #define DSI_WISR_RRIF_Msk             (0x1UL << DSI_WISR_RRIF_Pos)              /*!< 0x00002000 */
9300 #define DSI_WISR_RRIF                 DSI_WISR_RRIF_Msk                        /*!< Regulator Ready Interrupt Flag */
9301 
9302 /*******************  Bit definition for DSI_WIFCR register  ***************/
9303 #define DSI_WIFCR_CTEIF_Pos           (0U)
9304 #define DSI_WIFCR_CTEIF_Msk           (0x1UL << DSI_WIFCR_CTEIF_Pos)            /*!< 0x00000001 */
9305 #define DSI_WIFCR_CTEIF               DSI_WIFCR_CTEIF_Msk                      /*!< Clear Tearing Effect Interrupt Flag */
9306 #define DSI_WIFCR_CERIF_Pos           (1U)
9307 #define DSI_WIFCR_CERIF_Msk           (0x1UL << DSI_WIFCR_CERIF_Pos)            /*!< 0x00000002 */
9308 #define DSI_WIFCR_CERIF               DSI_WIFCR_CERIF_Msk                      /*!< Clear End of Refresh Interrupt Flag */
9309 #define DSI_WIFCR_CPLLLIF_Pos         (9U)
9310 #define DSI_WIFCR_CPLLLIF_Msk         (0x1UL << DSI_WIFCR_CPLLLIF_Pos)          /*!< 0x00000200 */
9311 #define DSI_WIFCR_CPLLLIF             DSI_WIFCR_CPLLLIF_Msk                    /*!< Clear PLL Lock Interrupt Flag */
9312 #define DSI_WIFCR_CPLLUIF_Pos         (10U)
9313 #define DSI_WIFCR_CPLLUIF_Msk         (0x1UL << DSI_WIFCR_CPLLUIF_Pos)          /*!< 0x00000400 */
9314 #define DSI_WIFCR_CPLLUIF             DSI_WIFCR_CPLLUIF_Msk                    /*!< Clear PLL Unlock Interrupt Flag */
9315 #define DSI_WIFCR_CRRIF_Pos           (13U)
9316 #define DSI_WIFCR_CRRIF_Msk           (0x1UL << DSI_WIFCR_CRRIF_Pos)            /*!< 0x00002000 */
9317 #define DSI_WIFCR_CRRIF               DSI_WIFCR_CRRIF_Msk                      /*!< Clear Regulator Ready Interrupt Flag */
9318 
9319 /*******************  Bit definition for DSI_WPCR0 register  ***************/
9320 #define DSI_WPCR0_UIX4_Pos            (0U)
9321 #define DSI_WPCR0_UIX4_Msk            (0x3FUL << DSI_WPCR0_UIX4_Pos)            /*!< 0x0000003F */
9322 #define DSI_WPCR0_UIX4                DSI_WPCR0_UIX4_Msk                       /*!< Unit Interval multiplied by 4 */
9323 #define DSI_WPCR0_UIX4_0              (0x01UL << DSI_WPCR0_UIX4_Pos)            /*!< 0x00000001 */
9324 #define DSI_WPCR0_UIX4_1              (0x02UL << DSI_WPCR0_UIX4_Pos)            /*!< 0x00000002 */
9325 #define DSI_WPCR0_UIX4_2              (0x04UL << DSI_WPCR0_UIX4_Pos)            /*!< 0x00000004 */
9326 #define DSI_WPCR0_UIX4_3              (0x08UL << DSI_WPCR0_UIX4_Pos)            /*!< 0x00000008 */
9327 #define DSI_WPCR0_UIX4_4              (0x10UL << DSI_WPCR0_UIX4_Pos)            /*!< 0x00000010 */
9328 #define DSI_WPCR0_UIX4_5              (0x20UL << DSI_WPCR0_UIX4_Pos)            /*!< 0x00000020 */
9329 
9330 #define DSI_WPCR0_SWCL_Pos            (6U)
9331 #define DSI_WPCR0_SWCL_Msk            (0x1UL << DSI_WPCR0_SWCL_Pos)             /*!< 0x00000040 */
9332 #define DSI_WPCR0_SWCL                DSI_WPCR0_SWCL_Msk                       /*!< Swap pins on clock lane */
9333 #define DSI_WPCR0_SWDL0_Pos           (7U)
9334 #define DSI_WPCR0_SWDL0_Msk           (0x1UL << DSI_WPCR0_SWDL0_Pos)            /*!< 0x00000080 */
9335 #define DSI_WPCR0_SWDL0               DSI_WPCR0_SWDL0_Msk                      /*!< Swap pins on data lane 1 */
9336 #define DSI_WPCR0_SWDL1_Pos           (8U)
9337 #define DSI_WPCR0_SWDL1_Msk           (0x1UL << DSI_WPCR0_SWDL1_Pos)            /*!< 0x00000100 */
9338 #define DSI_WPCR0_SWDL1               DSI_WPCR0_SWDL1_Msk                      /*!< Swap pins on data lane 2 */
9339 #define DSI_WPCR0_HSICL_Pos           (9U)
9340 #define DSI_WPCR0_HSICL_Msk           (0x1UL << DSI_WPCR0_HSICL_Pos)            /*!< 0x00000200 */
9341 #define DSI_WPCR0_HSICL               DSI_WPCR0_HSICL_Msk                      /*!< Invert the high-speed data signal on clock lane */
9342 #define DSI_WPCR0_HSIDL0_Pos          (10U)
9343 #define DSI_WPCR0_HSIDL0_Msk          (0x1UL << DSI_WPCR0_HSIDL0_Pos)           /*!< 0x00000400 */
9344 #define DSI_WPCR0_HSIDL0              DSI_WPCR0_HSIDL0_Msk                     /*!< Invert the high-speed data signal on lane 1 */
9345 #define DSI_WPCR0_HSIDL1_Pos          (11U)
9346 #define DSI_WPCR0_HSIDL1_Msk          (0x1UL << DSI_WPCR0_HSIDL1_Pos)           /*!< 0x00000800 */
9347 #define DSI_WPCR0_HSIDL1              DSI_WPCR0_HSIDL1_Msk                     /*!< Invert the high-speed data signal on lane 2 */
9348 #define DSI_WPCR0_FTXSMCL_Pos         (12U)
9349 #define DSI_WPCR0_FTXSMCL_Msk         (0x1UL << DSI_WPCR0_FTXSMCL_Pos)          /*!< 0x00001000 */
9350 #define DSI_WPCR0_FTXSMCL             DSI_WPCR0_FTXSMCL_Msk                    /*!< Force clock lane in TX stop mode */
9351 #define DSI_WPCR0_FTXSMDL_Pos         (13U)
9352 #define DSI_WPCR0_FTXSMDL_Msk         (0x1UL << DSI_WPCR0_FTXSMDL_Pos)          /*!< 0x00002000 */
9353 #define DSI_WPCR0_FTXSMDL             DSI_WPCR0_FTXSMDL_Msk                    /*!< Force data lanes in TX stop mode */
9354 #define DSI_WPCR0_CDOFFDL_Pos         (14U)
9355 #define DSI_WPCR0_CDOFFDL_Msk         (0x1UL << DSI_WPCR0_CDOFFDL_Pos)          /*!< 0x00004000 */
9356 #define DSI_WPCR0_CDOFFDL             DSI_WPCR0_CDOFFDL_Msk                    /*!< Contention detection OFF */
9357 #define DSI_WPCR0_TDDL_Pos            (16U)
9358 #define DSI_WPCR0_TDDL_Msk            (0x1UL << DSI_WPCR0_TDDL_Pos)             /*!< 0x00010000 */
9359 #define DSI_WPCR0_TDDL                DSI_WPCR0_TDDL_Msk                       /*!< Turn Disable Data Lanes */
9360 #define DSI_WPCR0_PDEN_Pos            (18U)
9361 #define DSI_WPCR0_PDEN_Msk            (0x1UL << DSI_WPCR0_PDEN_Pos)             /*!< 0x00040000 */
9362 #define DSI_WPCR0_PDEN                DSI_WPCR0_PDEN_Msk                       /*!< Pull-Down Enable */
9363 #define DSI_WPCR0_TCLKPREPEN_Pos      (19U)
9364 #define DSI_WPCR0_TCLKPREPEN_Msk      (0x1UL << DSI_WPCR0_TCLKPREPEN_Pos)       /*!< 0x00080000 */
9365 #define DSI_WPCR0_TCLKPREPEN          DSI_WPCR0_TCLKPREPEN_Msk                 /*!< Timer for t-CLKPREP Enable */
9366 #define DSI_WPCR0_TCLKZEROEN_Pos      (20U)
9367 #define DSI_WPCR0_TCLKZEROEN_Msk      (0x1UL << DSI_WPCR0_TCLKZEROEN_Pos)       /*!< 0x00100000 */
9368 #define DSI_WPCR0_TCLKZEROEN          DSI_WPCR0_TCLKZEROEN_Msk                 /*!< Timer for t-CLKZERO Enable */
9369 #define DSI_WPCR0_THSPREPEN_Pos       (21U)
9370 #define DSI_WPCR0_THSPREPEN_Msk       (0x1UL << DSI_WPCR0_THSPREPEN_Pos)        /*!< 0x00200000 */
9371 #define DSI_WPCR0_THSPREPEN           DSI_WPCR0_THSPREPEN_Msk                  /*!< Timer for t-HSPREP Enable */
9372 #define DSI_WPCR0_THSTRAILEN_Pos      (22U)
9373 #define DSI_WPCR0_THSTRAILEN_Msk      (0x1UL << DSI_WPCR0_THSTRAILEN_Pos)       /*!< 0x00400000 */
9374 #define DSI_WPCR0_THSTRAILEN          DSI_WPCR0_THSTRAILEN_Msk                 /*!< Timer for t-HSTRAIL Enable */
9375 #define DSI_WPCR0_THSZEROEN_Pos       (23U)
9376 #define DSI_WPCR0_THSZEROEN_Msk       (0x1UL << DSI_WPCR0_THSZEROEN_Pos)        /*!< 0x00800000 */
9377 #define DSI_WPCR0_THSZEROEN           DSI_WPCR0_THSZEROEN_Msk                  /*!< Timer for t-HSZERO Enable */
9378 #define DSI_WPCR0_TLPXDEN_Pos         (24U)
9379 #define DSI_WPCR0_TLPXDEN_Msk         (0x1UL << DSI_WPCR0_TLPXDEN_Pos)          /*!< 0x01000000 */
9380 #define DSI_WPCR0_TLPXDEN             DSI_WPCR0_TLPXDEN_Msk                    /*!< Timer for t-LPXD Enable */
9381 #define DSI_WPCR0_THSEXITEN_Pos       (25U)
9382 #define DSI_WPCR0_THSEXITEN_Msk       (0x1UL << DSI_WPCR0_THSEXITEN_Pos)        /*!< 0x02000000 */
9383 #define DSI_WPCR0_THSEXITEN           DSI_WPCR0_THSEXITEN_Msk                  /*!< Timer for t-HSEXIT Enable */
9384 #define DSI_WPCR0_TLPXCEN_Pos         (26U)
9385 #define DSI_WPCR0_TLPXCEN_Msk         (0x1UL << DSI_WPCR0_TLPXCEN_Pos)          /*!< 0x04000000 */
9386 #define DSI_WPCR0_TLPXCEN             DSI_WPCR0_TLPXCEN_Msk                    /*!< Timer for t-LPXC Enable */
9387 #define DSI_WPCR0_TCLKPOSTEN_Pos      (27U)
9388 #define DSI_WPCR0_TCLKPOSTEN_Msk      (0x1UL << DSI_WPCR0_TCLKPOSTEN_Pos)       /*!< 0x08000000 */
9389 #define DSI_WPCR0_TCLKPOSTEN          DSI_WPCR0_TCLKPOSTEN_Msk                 /*!< Timer for t-CLKPOST Enable */
9390 
9391 /*******************  Bit definition for DSI_WPCR1 register  ***************/
9392 #define DSI_WPCR1_HSTXDCL_Pos         (0U)
9393 #define DSI_WPCR1_HSTXDCL_Msk         (0x3UL << DSI_WPCR1_HSTXDCL_Pos)          /*!< 0x00000003 */
9394 #define DSI_WPCR1_HSTXDCL             DSI_WPCR1_HSTXDCL_Msk                    /*!< High-Speed Transmission Delay on Clock Lane */
9395 #define DSI_WPCR1_HSTXDCL0_Pos        (0U)
9396 #define DSI_WPCR1_HSTXDCL0_Msk        (0x1UL << DSI_WPCR1_HSTXDCL0_Pos)         /*!< 0x00000001 */
9397 #define DSI_WPCR1_HSTXDCL0            DSI_WPCR1_HSTXDCL0_Msk
9398 #define DSI_WPCR1_HSTXDCL1_Pos        (1U)
9399 #define DSI_WPCR1_HSTXDCL1_Msk        (0x1UL << DSI_WPCR1_HSTXDCL1_Pos)         /*!< 0x00000002 */
9400 #define DSI_WPCR1_HSTXDCL1            DSI_WPCR1_HSTXDCL1_Msk
9401 
9402 #define DSI_WPCR1_HSTXDDL_Pos         (2U)
9403 #define DSI_WPCR1_HSTXDDL_Msk         (0x3UL << DSI_WPCR1_HSTXDDL_Pos)          /*!< 0x0000000C */
9404 #define DSI_WPCR1_HSTXDDL             DSI_WPCR1_HSTXDDL_Msk                    /*!< High-Speed Transmission Delay on Data Lane */
9405 #define DSI_WPCR1_HSTXDDL0_Pos        (2U)
9406 #define DSI_WPCR1_HSTXDDL0_Msk        (0x1UL << DSI_WPCR1_HSTXDDL0_Pos)         /*!< 0x00000004 */
9407 #define DSI_WPCR1_HSTXDDL0            DSI_WPCR1_HSTXDDL0_Msk
9408 #define DSI_WPCR1_HSTXDDL1_Pos        (3U)
9409 #define DSI_WPCR1_HSTXDDL1_Msk        (0x1UL << DSI_WPCR1_HSTXDDL1_Pos)         /*!< 0x00000008 */
9410 #define DSI_WPCR1_HSTXDDL1            DSI_WPCR1_HSTXDDL1_Msk
9411 
9412 #define DSI_WPCR1_LPSRCCL_Pos         (6U)
9413 #define DSI_WPCR1_LPSRCCL_Msk         (0x3UL << DSI_WPCR1_LPSRCCL_Pos)          /*!< 0x000000C0 */
9414 #define DSI_WPCR1_LPSRCCL             DSI_WPCR1_LPSRCCL_Msk                    /*!< Low-Power transmission Slew Rate Compensation on Clock Lane */
9415 #define DSI_WPCR1_LPSRCCL0_Pos        (6U)
9416 #define DSI_WPCR1_LPSRCCL0_Msk        (0x1UL << DSI_WPCR1_LPSRCCL0_Pos)         /*!< 0x00000040 */
9417 #define DSI_WPCR1_LPSRCCL0            DSI_WPCR1_LPSRCCL0_Msk
9418 #define DSI_WPCR1_LPSRCCL1_Pos        (7U)
9419 #define DSI_WPCR1_LPSRCCL1_Msk        (0x1UL << DSI_WPCR1_LPSRCCL1_Pos)         /*!< 0x00000080 */
9420 #define DSI_WPCR1_LPSRCCL1            DSI_WPCR1_LPSRCCL1_Msk
9421 
9422 #define DSI_WPCR1_LPSRCDL_Pos         (8U)
9423 #define DSI_WPCR1_LPSRCDL_Msk         (0x3UL << DSI_WPCR1_LPSRCDL_Pos)          /*!< 0x00000300 */
9424 #define DSI_WPCR1_LPSRCDL             DSI_WPCR1_LPSRCDL_Msk                    /*!< Low-Power transmission Slew Rate Compensation on Data Lane */
9425 #define DSI_WPCR1_LPSRCDL0_Pos        (8U)
9426 #define DSI_WPCR1_LPSRCDL0_Msk        (0x1UL << DSI_WPCR1_LPSRCDL0_Pos)         /*!< 0x00000100 */
9427 #define DSI_WPCR1_LPSRCDL0            DSI_WPCR1_LPSRCDL0_Msk
9428 #define DSI_WPCR1_LPSRCDL1_Pos        (9U)
9429 #define DSI_WPCR1_LPSRCDL1_Msk        (0x1UL << DSI_WPCR1_LPSRCDL1_Pos)         /*!< 0x00000200 */
9430 #define DSI_WPCR1_LPSRCDL1            DSI_WPCR1_LPSRCDL1_Msk
9431 
9432 #define DSI_WPCR1_SDDC_Pos            (12U)
9433 #define DSI_WPCR1_SDDC_Msk            (0x1UL << DSI_WPCR1_SDDC_Pos)             /*!< 0x00001000 */
9434 #define DSI_WPCR1_SDDC                DSI_WPCR1_SDDC_Msk                       /*!< SDD Control */
9435 
9436 #define DSI_WPCR1_LPRXVCDL_Pos        (14U)
9437 #define DSI_WPCR1_LPRXVCDL_Msk        (0x3UL << DSI_WPCR1_LPRXVCDL_Pos)         /*!< 0x0000C000 */
9438 #define DSI_WPCR1_LPRXVCDL            DSI_WPCR1_LPRXVCDL_Msk                   /*!< Low-Power Reception V-IL Compensation on Data Lanes */
9439 #define DSI_WPCR1_LPRXVCDL0_Pos       (14U)
9440 #define DSI_WPCR1_LPRXVCDL0_Msk       (0x1UL << DSI_WPCR1_LPRXVCDL0_Pos)        /*!< 0x00004000 */
9441 #define DSI_WPCR1_LPRXVCDL0           DSI_WPCR1_LPRXVCDL0_Msk
9442 #define DSI_WPCR1_LPRXVCDL1_Pos       (15U)
9443 #define DSI_WPCR1_LPRXVCDL1_Msk       (0x1UL << DSI_WPCR1_LPRXVCDL1_Pos)        /*!< 0x00008000 */
9444 #define DSI_WPCR1_LPRXVCDL1           DSI_WPCR1_LPRXVCDL1_Msk
9445 
9446 #define DSI_WPCR1_HSTXSRCCL_Pos       (16U)
9447 #define DSI_WPCR1_HSTXSRCCL_Msk       (0x3UL << DSI_WPCR1_HSTXSRCCL_Pos)        /*!< 0x00030000 */
9448 #define DSI_WPCR1_HSTXSRCCL           DSI_WPCR1_HSTXSRCCL_Msk                  /*!< High-Speed Transmission Delay on Clock Lane */
9449 #define DSI_WPCR1_HSTXSRCCL0_Pos      (16U)
9450 #define DSI_WPCR1_HSTXSRCCL0_Msk      (0x1UL << DSI_WPCR1_HSTXSRCCL0_Pos)       /*!< 0x00010000 */
9451 #define DSI_WPCR1_HSTXSRCCL0          DSI_WPCR1_HSTXSRCCL0_Msk
9452 #define DSI_WPCR1_HSTXSRCCL1_Pos      (17U)
9453 #define DSI_WPCR1_HSTXSRCCL1_Msk      (0x1UL << DSI_WPCR1_HSTXSRCCL1_Pos)       /*!< 0x00020000 */
9454 #define DSI_WPCR1_HSTXSRCCL1          DSI_WPCR1_HSTXSRCCL1_Msk
9455 
9456 #define DSI_WPCR1_HSTXSRCDL_Pos       (18U)
9457 #define DSI_WPCR1_HSTXSRCDL_Msk       (0x3UL << DSI_WPCR1_HSTXSRCDL_Pos)        /*!< 0x000C0000 */
9458 #define DSI_WPCR1_HSTXSRCDL           DSI_WPCR1_HSTXSRCDL_Msk                  /*!< High-Speed Transmission Delay on Data Lane */
9459 #define DSI_WPCR1_HSTXSRCDL0_Pos      (18U)
9460 #define DSI_WPCR1_HSTXSRCDL0_Msk      (0x1UL << DSI_WPCR1_HSTXSRCDL0_Pos)       /*!< 0x00040000 */
9461 #define DSI_WPCR1_HSTXSRCDL0          DSI_WPCR1_HSTXSRCDL0_Msk
9462 #define DSI_WPCR1_HSTXSRCDL1_Pos      (19U)
9463 #define DSI_WPCR1_HSTXSRCDL1_Msk      (0x1UL << DSI_WPCR1_HSTXSRCDL1_Pos)       /*!< 0x00080000 */
9464 #define DSI_WPCR1_HSTXSRCDL1          DSI_WPCR1_HSTXSRCDL1_Msk
9465 
9466 #define DSI_WPCR1_FLPRXLPM_Pos        (22U)
9467 #define DSI_WPCR1_FLPRXLPM_Msk        (0x1UL << DSI_WPCR1_FLPRXLPM_Pos)         /*!< 0x00400000 */
9468 #define DSI_WPCR1_FLPRXLPM            DSI_WPCR1_FLPRXLPM_Msk                   /*!< Forces LP Receiver in Low-Power Mode */
9469 
9470 #define DSI_WPCR1_LPRXFT_Pos          (25U)
9471 #define DSI_WPCR1_LPRXFT_Msk          (0x3UL << DSI_WPCR1_LPRXFT_Pos)           /*!< 0x06000000 */
9472 #define DSI_WPCR1_LPRXFT              DSI_WPCR1_LPRXFT_Msk                     /*!< Low-Power RX low-pass Filtering Tuning */
9473 #define DSI_WPCR1_LPRXFT0_Pos         (25U)
9474 #define DSI_WPCR1_LPRXFT0_Msk         (0x1UL << DSI_WPCR1_LPRXFT0_Pos)          /*!< 0x02000000 */
9475 #define DSI_WPCR1_LPRXFT0             DSI_WPCR1_LPRXFT0_Msk
9476 #define DSI_WPCR1_LPRXFT1_Pos         (26U)
9477 #define DSI_WPCR1_LPRXFT1_Msk         (0x1UL << DSI_WPCR1_LPRXFT1_Pos)          /*!< 0x04000000 */
9478 #define DSI_WPCR1_LPRXFT1             DSI_WPCR1_LPRXFT1_Msk
9479 
9480 /*******************  Bit definition for DSI_WPCR2 register  ***************/
9481 #define DSI_WPCR2_TCLKPREP_Pos        (0U)
9482 #define DSI_WPCR2_TCLKPREP_Msk        (0xFFUL << DSI_WPCR2_TCLKPREP_Pos)        /*!< 0x000000FF */
9483 #define DSI_WPCR2_TCLKPREP            DSI_WPCR2_TCLKPREP_Msk                   /*!< t-CLKPREP */
9484 #define DSI_WPCR2_TCLKPREP0_Pos       (0U)
9485 #define DSI_WPCR2_TCLKPREP0_Msk       (0x1UL << DSI_WPCR2_TCLKPREP0_Pos)        /*!< 0x00000001 */
9486 #define DSI_WPCR2_TCLKPREP0           DSI_WPCR2_TCLKPREP0_Msk
9487 #define DSI_WPCR2_TCLKPREP1_Pos       (1U)
9488 #define DSI_WPCR2_TCLKPREP1_Msk       (0x1UL << DSI_WPCR2_TCLKPREP1_Pos)        /*!< 0x00000002 */
9489 #define DSI_WPCR2_TCLKPREP1           DSI_WPCR2_TCLKPREP1_Msk
9490 #define DSI_WPCR2_TCLKPREP2_Pos       (2U)
9491 #define DSI_WPCR2_TCLKPREP2_Msk       (0x1UL << DSI_WPCR2_TCLKPREP2_Pos)        /*!< 0x00000004 */
9492 #define DSI_WPCR2_TCLKPREP2           DSI_WPCR2_TCLKPREP2_Msk
9493 #define DSI_WPCR2_TCLKPREP3_Pos       (3U)
9494 #define DSI_WPCR2_TCLKPREP3_Msk       (0x1UL << DSI_WPCR2_TCLKPREP3_Pos)        /*!< 0x00000008 */
9495 #define DSI_WPCR2_TCLKPREP3           DSI_WPCR2_TCLKPREP3_Msk
9496 #define DSI_WPCR2_TCLKPREP4_Pos       (4U)
9497 #define DSI_WPCR2_TCLKPREP4_Msk       (0x1UL << DSI_WPCR2_TCLKPREP4_Pos)        /*!< 0x00000010 */
9498 #define DSI_WPCR2_TCLKPREP4           DSI_WPCR2_TCLKPREP4_Msk
9499 #define DSI_WPCR2_TCLKPREP5_Pos       (5U)
9500 #define DSI_WPCR2_TCLKPREP5_Msk       (0x1UL << DSI_WPCR2_TCLKPREP5_Pos)        /*!< 0x00000020 */
9501 #define DSI_WPCR2_TCLKPREP5           DSI_WPCR2_TCLKPREP5_Msk
9502 #define DSI_WPCR2_TCLKPREP6_Pos       (6U)
9503 #define DSI_WPCR2_TCLKPREP6_Msk       (0x1UL << DSI_WPCR2_TCLKPREP6_Pos)        /*!< 0x00000040 */
9504 #define DSI_WPCR2_TCLKPREP6           DSI_WPCR2_TCLKPREP6_Msk
9505 #define DSI_WPCR2_TCLKPREP7_Pos       (7U)
9506 #define DSI_WPCR2_TCLKPREP7_Msk       (0x1UL << DSI_WPCR2_TCLKPREP7_Pos)        /*!< 0x00000080 */
9507 #define DSI_WPCR2_TCLKPREP7           DSI_WPCR2_TCLKPREP7_Msk
9508 
9509 #define DSI_WPCR2_TCLKZERO_Pos        (8U)
9510 #define DSI_WPCR2_TCLKZERO_Msk        (0xFFUL << DSI_WPCR2_TCLKZERO_Pos)        /*!< 0x0000FF00 */
9511 #define DSI_WPCR2_TCLKZERO            DSI_WPCR2_TCLKZERO_Msk                   /*!< t-CLKZERO */
9512 #define DSI_WPCR2_TCLKZERO0_Pos       (8U)
9513 #define DSI_WPCR2_TCLKZERO0_Msk       (0x1UL << DSI_WPCR2_TCLKZERO0_Pos)        /*!< 0x00000100 */
9514 #define DSI_WPCR2_TCLKZERO0           DSI_WPCR2_TCLKZERO0_Msk
9515 #define DSI_WPCR2_TCLKZERO1_Pos       (9U)
9516 #define DSI_WPCR2_TCLKZERO1_Msk       (0x1UL << DSI_WPCR2_TCLKZERO1_Pos)        /*!< 0x00000200 */
9517 #define DSI_WPCR2_TCLKZERO1           DSI_WPCR2_TCLKZERO1_Msk
9518 #define DSI_WPCR2_TCLKZERO2_Pos       (10U)
9519 #define DSI_WPCR2_TCLKZERO2_Msk       (0x1UL << DSI_WPCR2_TCLKZERO2_Pos)        /*!< 0x00000400 */
9520 #define DSI_WPCR2_TCLKZERO2           DSI_WPCR2_TCLKZERO2_Msk
9521 #define DSI_WPCR2_TCLKZERO3_Pos       (11U)
9522 #define DSI_WPCR2_TCLKZERO3_Msk       (0x1UL << DSI_WPCR2_TCLKZERO3_Pos)        /*!< 0x00000800 */
9523 #define DSI_WPCR2_TCLKZERO3           DSI_WPCR2_TCLKZERO3_Msk
9524 #define DSI_WPCR2_TCLKZERO4_Pos       (12U)
9525 #define DSI_WPCR2_TCLKZERO4_Msk       (0x1UL << DSI_WPCR2_TCLKZERO4_Pos)        /*!< 0x00001000 */
9526 #define DSI_WPCR2_TCLKZERO4           DSI_WPCR2_TCLKZERO4_Msk
9527 #define DSI_WPCR2_TCLKZERO5_Pos       (13U)
9528 #define DSI_WPCR2_TCLKZERO5_Msk       (0x1UL << DSI_WPCR2_TCLKZERO5_Pos)        /*!< 0x00002000 */
9529 #define DSI_WPCR2_TCLKZERO5           DSI_WPCR2_TCLKZERO5_Msk
9530 #define DSI_WPCR2_TCLKZERO6_Pos       (14U)
9531 #define DSI_WPCR2_TCLKZERO6_Msk       (0x1UL << DSI_WPCR2_TCLKZERO6_Pos)        /*!< 0x00004000 */
9532 #define DSI_WPCR2_TCLKZERO6           DSI_WPCR2_TCLKZERO6_Msk
9533 #define DSI_WPCR2_TCLKZERO7_Pos       (15U)
9534 #define DSI_WPCR2_TCLKZERO7_Msk       (0x1UL << DSI_WPCR2_TCLKZERO7_Pos)        /*!< 0x00008000 */
9535 #define DSI_WPCR2_TCLKZERO7           DSI_WPCR2_TCLKZERO7_Msk
9536 
9537 #define DSI_WPCR2_THSPREP_Pos         (16U)
9538 #define DSI_WPCR2_THSPREP_Msk         (0xFFUL << DSI_WPCR2_THSPREP_Pos)         /*!< 0x00FF0000 */
9539 #define DSI_WPCR2_THSPREP             DSI_WPCR2_THSPREP_Msk                    /*!< t-HSPREP */
9540 #define DSI_WPCR2_THSPREP0_Pos        (16U)
9541 #define DSI_WPCR2_THSPREP0_Msk        (0x1UL << DSI_WPCR2_THSPREP0_Pos)         /*!< 0x00010000 */
9542 #define DSI_WPCR2_THSPREP0            DSI_WPCR2_THSPREP0_Msk
9543 #define DSI_WPCR2_THSPREP1_Pos        (17U)
9544 #define DSI_WPCR2_THSPREP1_Msk        (0x1UL << DSI_WPCR2_THSPREP1_Pos)         /*!< 0x00020000 */
9545 #define DSI_WPCR2_THSPREP1            DSI_WPCR2_THSPREP1_Msk
9546 #define DSI_WPCR2_THSPREP2_Pos        (18U)
9547 #define DSI_WPCR2_THSPREP2_Msk        (0x1UL << DSI_WPCR2_THSPREP2_Pos)         /*!< 0x00040000 */
9548 #define DSI_WPCR2_THSPREP2            DSI_WPCR2_THSPREP2_Msk
9549 #define DSI_WPCR2_THSPREP3_Pos        (19U)
9550 #define DSI_WPCR2_THSPREP3_Msk        (0x1UL << DSI_WPCR2_THSPREP3_Pos)         /*!< 0x00080000 */
9551 #define DSI_WPCR2_THSPREP3            DSI_WPCR2_THSPREP3_Msk
9552 #define DSI_WPCR2_THSPREP4_Pos        (20U)
9553 #define DSI_WPCR2_THSPREP4_Msk        (0x1UL << DSI_WPCR2_THSPREP4_Pos)         /*!< 0x00100000 */
9554 #define DSI_WPCR2_THSPREP4            DSI_WPCR2_THSPREP4_Msk
9555 #define DSI_WPCR2_THSPREP5_Pos        (21U)
9556 #define DSI_WPCR2_THSPREP5_Msk        (0x1UL << DSI_WPCR2_THSPREP5_Pos)         /*!< 0x00200000 */
9557 #define DSI_WPCR2_THSPREP5            DSI_WPCR2_THSPREP5_Msk
9558 #define DSI_WPCR2_THSPREP6_Pos        (22U)
9559 #define DSI_WPCR2_THSPREP6_Msk        (0x1UL << DSI_WPCR2_THSPREP6_Pos)         /*!< 0x00400000 */
9560 #define DSI_WPCR2_THSPREP6            DSI_WPCR2_THSPREP6_Msk
9561 #define DSI_WPCR2_THSPREP7_Pos        (23U)
9562 #define DSI_WPCR2_THSPREP7_Msk        (0x1UL << DSI_WPCR2_THSPREP7_Pos)         /*!< 0x00800000 */
9563 #define DSI_WPCR2_THSPREP7            DSI_WPCR2_THSPREP7_Msk
9564 
9565 #define DSI_WPCR2_THSTRAIL_Pos        (24U)
9566 #define DSI_WPCR2_THSTRAIL_Msk        (0xFFUL << DSI_WPCR2_THSTRAIL_Pos)        /*!< 0xFF000000 */
9567 #define DSI_WPCR2_THSTRAIL            DSI_WPCR2_THSTRAIL_Msk                   /*!< t-HSTRAIL */
9568 #define DSI_WPCR2_THSTRAIL0_Pos       (24U)
9569 #define DSI_WPCR2_THSTRAIL0_Msk       (0x1UL << DSI_WPCR2_THSTRAIL0_Pos)        /*!< 0x01000000 */
9570 #define DSI_WPCR2_THSTRAIL0           DSI_WPCR2_THSTRAIL0_Msk
9571 #define DSI_WPCR2_THSTRAIL1_Pos       (25U)
9572 #define DSI_WPCR2_THSTRAIL1_Msk       (0x1UL << DSI_WPCR2_THSTRAIL1_Pos)        /*!< 0x02000000 */
9573 #define DSI_WPCR2_THSTRAIL1           DSI_WPCR2_THSTRAIL1_Msk
9574 #define DSI_WPCR2_THSTRAIL2_Pos       (26U)
9575 #define DSI_WPCR2_THSTRAIL2_Msk       (0x1UL << DSI_WPCR2_THSTRAIL2_Pos)        /*!< 0x04000000 */
9576 #define DSI_WPCR2_THSTRAIL2           DSI_WPCR2_THSTRAIL2_Msk
9577 #define DSI_WPCR2_THSTRAIL3_Pos       (27U)
9578 #define DSI_WPCR2_THSTRAIL3_Msk       (0x1UL << DSI_WPCR2_THSTRAIL3_Pos)        /*!< 0x08000000 */
9579 #define DSI_WPCR2_THSTRAIL3           DSI_WPCR2_THSTRAIL3_Msk
9580 #define DSI_WPCR2_THSTRAIL4_Pos       (28U)
9581 #define DSI_WPCR2_THSTRAIL4_Msk       (0x1UL << DSI_WPCR2_THSTRAIL4_Pos)        /*!< 0x10000000 */
9582 #define DSI_WPCR2_THSTRAIL4           DSI_WPCR2_THSTRAIL4_Msk
9583 #define DSI_WPCR2_THSTRAIL5_Pos       (29U)
9584 #define DSI_WPCR2_THSTRAIL5_Msk       (0x1UL << DSI_WPCR2_THSTRAIL5_Pos)        /*!< 0x20000000 */
9585 #define DSI_WPCR2_THSTRAIL5           DSI_WPCR2_THSTRAIL5_Msk
9586 #define DSI_WPCR2_THSTRAIL6_Pos       (30U)
9587 #define DSI_WPCR2_THSTRAIL6_Msk       (0x1UL << DSI_WPCR2_THSTRAIL6_Pos)        /*!< 0x40000000 */
9588 #define DSI_WPCR2_THSTRAIL6           DSI_WPCR2_THSTRAIL6_Msk
9589 #define DSI_WPCR2_THSTRAIL7_Pos       (31U)
9590 #define DSI_WPCR2_THSTRAIL7_Msk       (0x1UL << DSI_WPCR2_THSTRAIL7_Pos)        /*!< 0x80000000 */
9591 #define DSI_WPCR2_THSTRAIL7           DSI_WPCR2_THSTRAIL7_Msk
9592 
9593 /*******************  Bit definition for DSI_WPCR3 register  ***************/
9594 #define DSI_WPCR3_THSZERO_Pos         (0U)
9595 #define DSI_WPCR3_THSZERO_Msk         (0xFFUL << DSI_WPCR3_THSZERO_Pos)         /*!< 0x000000FF */
9596 #define DSI_WPCR3_THSZERO             DSI_WPCR3_THSZERO_Msk                    /*!< t-HSZERO */
9597 #define DSI_WPCR3_THSZERO0_Pos        (0U)
9598 #define DSI_WPCR3_THSZERO0_Msk        (0x1UL << DSI_WPCR3_THSZERO0_Pos)         /*!< 0x00000001 */
9599 #define DSI_WPCR3_THSZERO0            DSI_WPCR3_THSZERO0_Msk
9600 #define DSI_WPCR3_THSZERO1_Pos        (1U)
9601 #define DSI_WPCR3_THSZERO1_Msk        (0x1UL << DSI_WPCR3_THSZERO1_Pos)         /*!< 0x00000002 */
9602 #define DSI_WPCR3_THSZERO1            DSI_WPCR3_THSZERO1_Msk
9603 #define DSI_WPCR3_THSZERO2_Pos        (2U)
9604 #define DSI_WPCR3_THSZERO2_Msk        (0x1UL << DSI_WPCR3_THSZERO2_Pos)         /*!< 0x00000004 */
9605 #define DSI_WPCR3_THSZERO2            DSI_WPCR3_THSZERO2_Msk
9606 #define DSI_WPCR3_THSZERO3_Pos        (3U)
9607 #define DSI_WPCR3_THSZERO3_Msk        (0x1UL << DSI_WPCR3_THSZERO3_Pos)         /*!< 0x00000008 */
9608 #define DSI_WPCR3_THSZERO3            DSI_WPCR3_THSZERO3_Msk
9609 #define DSI_WPCR3_THSZERO4_Pos        (4U)
9610 #define DSI_WPCR3_THSZERO4_Msk        (0x1UL << DSI_WPCR3_THSZERO4_Pos)         /*!< 0x00000010 */
9611 #define DSI_WPCR3_THSZERO4            DSI_WPCR3_THSZERO4_Msk
9612 #define DSI_WPCR3_THSZERO5_Pos        (5U)
9613 #define DSI_WPCR3_THSZERO5_Msk        (0x1UL << DSI_WPCR3_THSZERO5_Pos)         /*!< 0x00000020 */
9614 #define DSI_WPCR3_THSZERO5            DSI_WPCR3_THSZERO5_Msk
9615 #define DSI_WPCR3_THSZERO6_Pos        (6U)
9616 #define DSI_WPCR3_THSZERO6_Msk        (0x1UL << DSI_WPCR3_THSZERO6_Pos)         /*!< 0x00000040 */
9617 #define DSI_WPCR3_THSZERO6            DSI_WPCR3_THSZERO6_Msk
9618 #define DSI_WPCR3_THSZERO7_Pos        (7U)
9619 #define DSI_WPCR3_THSZERO7_Msk        (0x1UL << DSI_WPCR3_THSZERO7_Pos)         /*!< 0x00000080 */
9620 #define DSI_WPCR3_THSZERO7            DSI_WPCR3_THSZERO7_Msk
9621 
9622 #define DSI_WPCR3_TLPXD_Pos           (8U)
9623 #define DSI_WPCR3_TLPXD_Msk           (0xFFUL << DSI_WPCR3_TLPXD_Pos)           /*!< 0x0000FF00 */
9624 #define DSI_WPCR3_TLPXD               DSI_WPCR3_TLPXD_Msk                      /*!< t-LPXD */
9625 #define DSI_WPCR3_TLPXD0_Pos          (8U)
9626 #define DSI_WPCR3_TLPXD0_Msk          (0x1UL << DSI_WPCR3_TLPXD0_Pos)           /*!< 0x00000100 */
9627 #define DSI_WPCR3_TLPXD0              DSI_WPCR3_TLPXD0_Msk
9628 #define DSI_WPCR3_TLPXD1_Pos          (9U)
9629 #define DSI_WPCR3_TLPXD1_Msk          (0x1UL << DSI_WPCR3_TLPXD1_Pos)           /*!< 0x00000200 */
9630 #define DSI_WPCR3_TLPXD1              DSI_WPCR3_TLPXD1_Msk
9631 #define DSI_WPCR3_TLPXD2_Pos          (10U)
9632 #define DSI_WPCR3_TLPXD2_Msk          (0x1UL << DSI_WPCR3_TLPXD2_Pos)           /*!< 0x00000400 */
9633 #define DSI_WPCR3_TLPXD2              DSI_WPCR3_TLPXD2_Msk
9634 #define DSI_WPCR3_TLPXD3_Pos          (11U)
9635 #define DSI_WPCR3_TLPXD3_Msk          (0x1UL << DSI_WPCR3_TLPXD3_Pos)           /*!< 0x00000800 */
9636 #define DSI_WPCR3_TLPXD3              DSI_WPCR3_TLPXD3_Msk
9637 #define DSI_WPCR3_TLPXD4_Pos          (12U)
9638 #define DSI_WPCR3_TLPXD4_Msk          (0x1UL << DSI_WPCR3_TLPXD4_Pos)           /*!< 0x00001000 */
9639 #define DSI_WPCR3_TLPXD4              DSI_WPCR3_TLPXD4_Msk
9640 #define DSI_WPCR3_TLPXD5_Pos          (13U)
9641 #define DSI_WPCR3_TLPXD5_Msk          (0x1UL << DSI_WPCR3_TLPXD5_Pos)           /*!< 0x00002000 */
9642 #define DSI_WPCR3_TLPXD5              DSI_WPCR3_TLPXD5_Msk
9643 #define DSI_WPCR3_TLPXD6_Pos          (14U)
9644 #define DSI_WPCR3_TLPXD6_Msk          (0x1UL << DSI_WPCR3_TLPXD6_Pos)           /*!< 0x00004000 */
9645 #define DSI_WPCR3_TLPXD6              DSI_WPCR3_TLPXD6_Msk
9646 #define DSI_WPCR3_TLPXD7_Pos          (15U)
9647 #define DSI_WPCR3_TLPXD7_Msk          (0x1UL << DSI_WPCR3_TLPXD7_Pos)           /*!< 0x00008000 */
9648 #define DSI_WPCR3_TLPXD7              DSI_WPCR3_TLPXD7_Msk
9649 
9650 #define DSI_WPCR3_THSEXIT_Pos         (16U)
9651 #define DSI_WPCR3_THSEXIT_Msk         (0xFFUL << DSI_WPCR3_THSEXIT_Pos)         /*!< 0x00FF0000 */
9652 #define DSI_WPCR3_THSEXIT             DSI_WPCR3_THSEXIT_Msk                    /*!< t-HSEXIT */
9653 #define DSI_WPCR3_THSEXIT0_Pos        (16U)
9654 #define DSI_WPCR3_THSEXIT0_Msk        (0x1UL << DSI_WPCR3_THSEXIT0_Pos)         /*!< 0x00010000 */
9655 #define DSI_WPCR3_THSEXIT0            DSI_WPCR3_THSEXIT0_Msk
9656 #define DSI_WPCR3_THSEXIT1_Pos        (17U)
9657 #define DSI_WPCR3_THSEXIT1_Msk        (0x1UL << DSI_WPCR3_THSEXIT1_Pos)         /*!< 0x00020000 */
9658 #define DSI_WPCR3_THSEXIT1            DSI_WPCR3_THSEXIT1_Msk
9659 #define DSI_WPCR3_THSEXIT2_Pos        (18U)
9660 #define DSI_WPCR3_THSEXIT2_Msk        (0x1UL << DSI_WPCR3_THSEXIT2_Pos)         /*!< 0x00040000 */
9661 #define DSI_WPCR3_THSEXIT2            DSI_WPCR3_THSEXIT2_Msk
9662 #define DSI_WPCR3_THSEXIT3_Pos        (19U)
9663 #define DSI_WPCR3_THSEXIT3_Msk        (0x1UL << DSI_WPCR3_THSEXIT3_Pos)         /*!< 0x00080000 */
9664 #define DSI_WPCR3_THSEXIT3            DSI_WPCR3_THSEXIT3_Msk
9665 #define DSI_WPCR3_THSEXIT4_Pos        (20U)
9666 #define DSI_WPCR3_THSEXIT4_Msk        (0x1UL << DSI_WPCR3_THSEXIT4_Pos)         /*!< 0x00100000 */
9667 #define DSI_WPCR3_THSEXIT4            DSI_WPCR3_THSEXIT4_Msk
9668 #define DSI_WPCR3_THSEXIT5_Pos        (21U)
9669 #define DSI_WPCR3_THSEXIT5_Msk        (0x1UL << DSI_WPCR3_THSEXIT5_Pos)         /*!< 0x00200000 */
9670 #define DSI_WPCR3_THSEXIT5            DSI_WPCR3_THSEXIT5_Msk
9671 #define DSI_WPCR3_THSEXIT6_Pos        (22U)
9672 #define DSI_WPCR3_THSEXIT6_Msk        (0x1UL << DSI_WPCR3_THSEXIT6_Pos)         /*!< 0x00400000 */
9673 #define DSI_WPCR3_THSEXIT6            DSI_WPCR3_THSEXIT6_Msk
9674 #define DSI_WPCR3_THSEXIT7_Pos        (23U)
9675 #define DSI_WPCR3_THSEXIT7_Msk        (0x1UL << DSI_WPCR3_THSEXIT7_Pos)         /*!< 0x00800000 */
9676 #define DSI_WPCR3_THSEXIT7            DSI_WPCR3_THSEXIT7_Msk
9677 
9678 #define DSI_WPCR3_TLPXC_Pos           (24U)
9679 #define DSI_WPCR3_TLPXC_Msk           (0xFFUL << DSI_WPCR3_TLPXC_Pos)           /*!< 0xFF000000 */
9680 #define DSI_WPCR3_TLPXC               DSI_WPCR3_TLPXC_Msk                      /*!< t-LPXC */
9681 #define DSI_WPCR3_TLPXC0_Pos          (24U)
9682 #define DSI_WPCR3_TLPXC0_Msk          (0x1UL << DSI_WPCR3_TLPXC0_Pos)           /*!< 0x01000000 */
9683 #define DSI_WPCR3_TLPXC0              DSI_WPCR3_TLPXC0_Msk
9684 #define DSI_WPCR3_TLPXC1_Pos          (25U)
9685 #define DSI_WPCR3_TLPXC1_Msk          (0x1UL << DSI_WPCR3_TLPXC1_Pos)           /*!< 0x02000000 */
9686 #define DSI_WPCR3_TLPXC1              DSI_WPCR3_TLPXC1_Msk
9687 #define DSI_WPCR3_TLPXC2_Pos          (26U)
9688 #define DSI_WPCR3_TLPXC2_Msk          (0x1UL << DSI_WPCR3_TLPXC2_Pos)           /*!< 0x04000000 */
9689 #define DSI_WPCR3_TLPXC2              DSI_WPCR3_TLPXC2_Msk
9690 #define DSI_WPCR3_TLPXC3_Pos          (27U)
9691 #define DSI_WPCR3_TLPXC3_Msk          (0x1UL << DSI_WPCR3_TLPXC3_Pos)           /*!< 0x08000000 */
9692 #define DSI_WPCR3_TLPXC3              DSI_WPCR3_TLPXC3_Msk
9693 #define DSI_WPCR3_TLPXC4_Pos          (28U)
9694 #define DSI_WPCR3_TLPXC4_Msk          (0x1UL << DSI_WPCR3_TLPXC4_Pos)           /*!< 0x10000000 */
9695 #define DSI_WPCR3_TLPXC4              DSI_WPCR3_TLPXC4_Msk
9696 #define DSI_WPCR3_TLPXC5_Pos          (29U)
9697 #define DSI_WPCR3_TLPXC5_Msk          (0x1UL << DSI_WPCR3_TLPXC5_Pos)           /*!< 0x20000000 */
9698 #define DSI_WPCR3_TLPXC5              DSI_WPCR3_TLPXC5_Msk
9699 #define DSI_WPCR3_TLPXC6_Pos          (30U)
9700 #define DSI_WPCR3_TLPXC6_Msk          (0x1UL << DSI_WPCR3_TLPXC6_Pos)           /*!< 0x40000000 */
9701 #define DSI_WPCR3_TLPXC6              DSI_WPCR3_TLPXC6_Msk
9702 #define DSI_WPCR3_TLPXC7_Pos          (31U)
9703 #define DSI_WPCR3_TLPXC7_Msk          (0x1UL << DSI_WPCR3_TLPXC7_Pos)           /*!< 0x80000000 */
9704 #define DSI_WPCR3_TLPXC7              DSI_WPCR3_TLPXC7_Msk
9705 
9706 /*******************  Bit definition for DSI_WPCR4 register  ***************/
9707 #define DSI_WPCR4_TCLKPOST_Pos        (0U)
9708 #define DSI_WPCR4_TCLKPOST_Msk        (0xFFUL << DSI_WPCR4_TCLKPOST_Pos)        /*!< 0x000000FF */
9709 #define DSI_WPCR4_TCLKPOST            DSI_WPCR4_TCLKPOST_Msk                   /*!< t-CLKPOST */
9710 #define DSI_WPCR4_TCLKPOST0_Pos       (0U)
9711 #define DSI_WPCR4_TCLKPOST0_Msk       (0x1UL << DSI_WPCR4_TCLKPOST0_Pos)        /*!< 0x00000001 */
9712 #define DSI_WPCR4_TCLKPOST0           DSI_WPCR4_TCLKPOST0_Msk
9713 #define DSI_WPCR4_TCLKPOST1_Pos       (1U)
9714 #define DSI_WPCR4_TCLKPOST1_Msk       (0x1UL << DSI_WPCR4_TCLKPOST1_Pos)        /*!< 0x00000002 */
9715 #define DSI_WPCR4_TCLKPOST1           DSI_WPCR4_TCLKPOST1_Msk
9716 #define DSI_WPCR4_TCLKPOST2_Pos       (2U)
9717 #define DSI_WPCR4_TCLKPOST2_Msk       (0x1UL << DSI_WPCR4_TCLKPOST2_Pos)        /*!< 0x00000004 */
9718 #define DSI_WPCR4_TCLKPOST2           DSI_WPCR4_TCLKPOST2_Msk
9719 #define DSI_WPCR4_TCLKPOST3_Pos       (3U)
9720 #define DSI_WPCR4_TCLKPOST3_Msk       (0x1UL << DSI_WPCR4_TCLKPOST3_Pos)        /*!< 0x00000008 */
9721 #define DSI_WPCR4_TCLKPOST3           DSI_WPCR4_TCLKPOST3_Msk
9722 #define DSI_WPCR4_TCLKPOST4_Pos       (4U)
9723 #define DSI_WPCR4_TCLKPOST4_Msk       (0x1UL << DSI_WPCR4_TCLKPOST4_Pos)        /*!< 0x00000010 */
9724 #define DSI_WPCR4_TCLKPOST4           DSI_WPCR4_TCLKPOST4_Msk
9725 #define DSI_WPCR4_TCLKPOST5_Pos       (5U)
9726 #define DSI_WPCR4_TCLKPOST5_Msk       (0x1UL << DSI_WPCR4_TCLKPOST5_Pos)        /*!< 0x00000020 */
9727 #define DSI_WPCR4_TCLKPOST5           DSI_WPCR4_TCLKPOST5_Msk
9728 #define DSI_WPCR4_TCLKPOST6_Pos       (6U)
9729 #define DSI_WPCR4_TCLKPOST6_Msk       (0x1UL << DSI_WPCR4_TCLKPOST6_Pos)        /*!< 0x00000040 */
9730 #define DSI_WPCR4_TCLKPOST6           DSI_WPCR4_TCLKPOST6_Msk
9731 #define DSI_WPCR4_TCLKPOST7_Pos       (7U)
9732 #define DSI_WPCR4_TCLKPOST7_Msk       (0x1UL << DSI_WPCR4_TCLKPOST7_Pos)        /*!< 0x00000080 */
9733 #define DSI_WPCR4_TCLKPOST7           DSI_WPCR4_TCLKPOST7_Msk
9734 
9735 /*******************  Bit definition for DSI_WRPCR register  ***************/
9736 #define DSI_WRPCR_PLLEN_Pos           (0U)
9737 #define DSI_WRPCR_PLLEN_Msk           (0x1UL << DSI_WRPCR_PLLEN_Pos)            /*!< 0x00000001 */
9738 #define DSI_WRPCR_PLLEN               DSI_WRPCR_PLLEN_Msk                      /*!< PLL Enable */
9739 #define DSI_WRPCR_PLL_NDIV_Pos        (2U)
9740 #define DSI_WRPCR_PLL_NDIV_Msk        (0x7FUL << DSI_WRPCR_PLL_NDIV_Pos)        /*!< 0x000001FC */
9741 #define DSI_WRPCR_PLL_NDIV            DSI_WRPCR_PLL_NDIV_Msk                   /*!< PLL Loop Division Factor */
9742 #define DSI_WRPCR_PLL_NDIV0_Pos       (2U)
9743 #define DSI_WRPCR_PLL_NDIV0_Msk       (0x1UL << DSI_WRPCR_PLL_NDIV0_Pos)        /*!< 0x00000004 */
9744 #define DSI_WRPCR_PLL_NDIV0           DSI_WRPCR_PLL_NDIV0_Msk
9745 #define DSI_WRPCR_PLL_NDIV1_Pos       (3U)
9746 #define DSI_WRPCR_PLL_NDIV1_Msk       (0x1UL << DSI_WRPCR_PLL_NDIV1_Pos)        /*!< 0x00000008 */
9747 #define DSI_WRPCR_PLL_NDIV1           DSI_WRPCR_PLL_NDIV1_Msk
9748 #define DSI_WRPCR_PLL_NDIV2_Pos       (4U)
9749 #define DSI_WRPCR_PLL_NDIV2_Msk       (0x1UL << DSI_WRPCR_PLL_NDIV2_Pos)        /*!< 0x00000010 */
9750 #define DSI_WRPCR_PLL_NDIV2           DSI_WRPCR_PLL_NDIV2_Msk
9751 #define DSI_WRPCR_PLL_NDIV3_Pos       (5U)
9752 #define DSI_WRPCR_PLL_NDIV3_Msk       (0x1UL << DSI_WRPCR_PLL_NDIV3_Pos)        /*!< 0x00000020 */
9753 #define DSI_WRPCR_PLL_NDIV3           DSI_WRPCR_PLL_NDIV3_Msk
9754 #define DSI_WRPCR_PLL_NDIV4_Pos       (6U)
9755 #define DSI_WRPCR_PLL_NDIV4_Msk       (0x1UL << DSI_WRPCR_PLL_NDIV4_Pos)        /*!< 0x00000040 */
9756 #define DSI_WRPCR_PLL_NDIV4           DSI_WRPCR_PLL_NDIV4_Msk
9757 #define DSI_WRPCR_PLL_NDIV5_Pos       (7U)
9758 #define DSI_WRPCR_PLL_NDIV5_Msk       (0x1UL << DSI_WRPCR_PLL_NDIV5_Pos)        /*!< 0x00000080 */
9759 #define DSI_WRPCR_PLL_NDIV5           DSI_WRPCR_PLL_NDIV5_Msk
9760 #define DSI_WRPCR_PLL_NDIV6_Pos       (8U)
9761 #define DSI_WRPCR_PLL_NDIV6_Msk       (0x1UL << DSI_WRPCR_PLL_NDIV6_Pos)        /*!< 0x00000100 */
9762 #define DSI_WRPCR_PLL_NDIV6           DSI_WRPCR_PLL_NDIV6_Msk
9763 
9764 #define DSI_WRPCR_PLL_IDF_Pos         (11U)
9765 #define DSI_WRPCR_PLL_IDF_Msk         (0xFUL << DSI_WRPCR_PLL_IDF_Pos)          /*!< 0x00007800 */
9766 #define DSI_WRPCR_PLL_IDF             DSI_WRPCR_PLL_IDF_Msk                    /*!< PLL Input Division Factor */
9767 #define DSI_WRPCR_PLL_IDF0_Pos        (11U)
9768 #define DSI_WRPCR_PLL_IDF0_Msk        (0x1UL << DSI_WRPCR_PLL_IDF0_Pos)         /*!< 0x00000800 */
9769 #define DSI_WRPCR_PLL_IDF0            DSI_WRPCR_PLL_IDF0_Msk
9770 #define DSI_WRPCR_PLL_IDF1_Pos        (12U)
9771 #define DSI_WRPCR_PLL_IDF1_Msk        (0x1UL << DSI_WRPCR_PLL_IDF1_Pos)         /*!< 0x00001000 */
9772 #define DSI_WRPCR_PLL_IDF1            DSI_WRPCR_PLL_IDF1_Msk
9773 #define DSI_WRPCR_PLL_IDF2_Pos        (13U)
9774 #define DSI_WRPCR_PLL_IDF2_Msk        (0x1UL << DSI_WRPCR_PLL_IDF2_Pos)         /*!< 0x00002000 */
9775 #define DSI_WRPCR_PLL_IDF2            DSI_WRPCR_PLL_IDF2_Msk
9776 #define DSI_WRPCR_PLL_IDF3_Pos        (14U)
9777 #define DSI_WRPCR_PLL_IDF3_Msk        (0x1UL << DSI_WRPCR_PLL_IDF3_Pos)         /*!< 0x00004000 */
9778 #define DSI_WRPCR_PLL_IDF3            DSI_WRPCR_PLL_IDF3_Msk
9779 
9780 #define DSI_WRPCR_PLL_ODF_Pos         (16U)
9781 #define DSI_WRPCR_PLL_ODF_Msk         (0x3UL << DSI_WRPCR_PLL_ODF_Pos)          /*!< 0x00030000 */
9782 #define DSI_WRPCR_PLL_ODF             DSI_WRPCR_PLL_ODF_Msk                    /*!< PLL Output Division Factor */
9783 #define DSI_WRPCR_PLL_ODF0_Pos        (16U)
9784 #define DSI_WRPCR_PLL_ODF0_Msk        (0x1UL << DSI_WRPCR_PLL_ODF0_Pos)         /*!< 0x00010000 */
9785 #define DSI_WRPCR_PLL_ODF0            DSI_WRPCR_PLL_ODF0_Msk
9786 #define DSI_WRPCR_PLL_ODF1_Pos        (17U)
9787 #define DSI_WRPCR_PLL_ODF1_Msk        (0x1UL << DSI_WRPCR_PLL_ODF1_Pos)         /*!< 0x00020000 */
9788 #define DSI_WRPCR_PLL_ODF1            DSI_WRPCR_PLL_ODF1_Msk
9789 
9790 #define DSI_WRPCR_REGEN_Pos           (24U)
9791 #define DSI_WRPCR_REGEN_Msk           (0x1UL << DSI_WRPCR_REGEN_Pos)            /*!< 0x01000000 */
9792 #define DSI_WRPCR_REGEN               DSI_WRPCR_REGEN_Msk                      /*!< Regulator Enable */
9793 
9794 /******************************************************************************/
9795 /*                                                                            */
9796 /*                    External Interrupt/Event Controller                     */
9797 /*                                                                            */
9798 /******************************************************************************/
9799 /*******************  Bit definition for EXTI_IMR register  *******************/
9800 #define EXTI_IMR_MR0_Pos          (0U)
9801 #define EXTI_IMR_MR0_Msk          (0x1UL << EXTI_IMR_MR0_Pos)                   /*!< 0x00000001 */
9802 #define EXTI_IMR_MR0              EXTI_IMR_MR0_Msk                             /*!< Interrupt Mask on line 0 */
9803 #define EXTI_IMR_MR1_Pos          (1U)
9804 #define EXTI_IMR_MR1_Msk          (0x1UL << EXTI_IMR_MR1_Pos)                   /*!< 0x00000002 */
9805 #define EXTI_IMR_MR1              EXTI_IMR_MR1_Msk                             /*!< Interrupt Mask on line 1 */
9806 #define EXTI_IMR_MR2_Pos          (2U)
9807 #define EXTI_IMR_MR2_Msk          (0x1UL << EXTI_IMR_MR2_Pos)                   /*!< 0x00000004 */
9808 #define EXTI_IMR_MR2              EXTI_IMR_MR2_Msk                             /*!< Interrupt Mask on line 2 */
9809 #define EXTI_IMR_MR3_Pos          (3U)
9810 #define EXTI_IMR_MR3_Msk          (0x1UL << EXTI_IMR_MR3_Pos)                   /*!< 0x00000008 */
9811 #define EXTI_IMR_MR3              EXTI_IMR_MR3_Msk                             /*!< Interrupt Mask on line 3 */
9812 #define EXTI_IMR_MR4_Pos          (4U)
9813 #define EXTI_IMR_MR4_Msk          (0x1UL << EXTI_IMR_MR4_Pos)                   /*!< 0x00000010 */
9814 #define EXTI_IMR_MR4              EXTI_IMR_MR4_Msk                             /*!< Interrupt Mask on line 4 */
9815 #define EXTI_IMR_MR5_Pos          (5U)
9816 #define EXTI_IMR_MR5_Msk          (0x1UL << EXTI_IMR_MR5_Pos)                   /*!< 0x00000020 */
9817 #define EXTI_IMR_MR5              EXTI_IMR_MR5_Msk                             /*!< Interrupt Mask on line 5 */
9818 #define EXTI_IMR_MR6_Pos          (6U)
9819 #define EXTI_IMR_MR6_Msk          (0x1UL << EXTI_IMR_MR6_Pos)                   /*!< 0x00000040 */
9820 #define EXTI_IMR_MR6              EXTI_IMR_MR6_Msk                             /*!< Interrupt Mask on line 6 */
9821 #define EXTI_IMR_MR7_Pos          (7U)
9822 #define EXTI_IMR_MR7_Msk          (0x1UL << EXTI_IMR_MR7_Pos)                   /*!< 0x00000080 */
9823 #define EXTI_IMR_MR7              EXTI_IMR_MR7_Msk                             /*!< Interrupt Mask on line 7 */
9824 #define EXTI_IMR_MR8_Pos          (8U)
9825 #define EXTI_IMR_MR8_Msk          (0x1UL << EXTI_IMR_MR8_Pos)                   /*!< 0x00000100 */
9826 #define EXTI_IMR_MR8              EXTI_IMR_MR8_Msk                             /*!< Interrupt Mask on line 8 */
9827 #define EXTI_IMR_MR9_Pos          (9U)
9828 #define EXTI_IMR_MR9_Msk          (0x1UL << EXTI_IMR_MR9_Pos)                   /*!< 0x00000200 */
9829 #define EXTI_IMR_MR9              EXTI_IMR_MR9_Msk                             /*!< Interrupt Mask on line 9 */
9830 #define EXTI_IMR_MR10_Pos         (10U)
9831 #define EXTI_IMR_MR10_Msk         (0x1UL << EXTI_IMR_MR10_Pos)                  /*!< 0x00000400 */
9832 #define EXTI_IMR_MR10             EXTI_IMR_MR10_Msk                            /*!< Interrupt Mask on line 10 */
9833 #define EXTI_IMR_MR11_Pos         (11U)
9834 #define EXTI_IMR_MR11_Msk         (0x1UL << EXTI_IMR_MR11_Pos)                  /*!< 0x00000800 */
9835 #define EXTI_IMR_MR11             EXTI_IMR_MR11_Msk                            /*!< Interrupt Mask on line 11 */
9836 #define EXTI_IMR_MR12_Pos         (12U)
9837 #define EXTI_IMR_MR12_Msk         (0x1UL << EXTI_IMR_MR12_Pos)                  /*!< 0x00001000 */
9838 #define EXTI_IMR_MR12             EXTI_IMR_MR12_Msk                            /*!< Interrupt Mask on line 12 */
9839 #define EXTI_IMR_MR13_Pos         (13U)
9840 #define EXTI_IMR_MR13_Msk         (0x1UL << EXTI_IMR_MR13_Pos)                  /*!< 0x00002000 */
9841 #define EXTI_IMR_MR13             EXTI_IMR_MR13_Msk                            /*!< Interrupt Mask on line 13 */
9842 #define EXTI_IMR_MR14_Pos         (14U)
9843 #define EXTI_IMR_MR14_Msk         (0x1UL << EXTI_IMR_MR14_Pos)                  /*!< 0x00004000 */
9844 #define EXTI_IMR_MR14             EXTI_IMR_MR14_Msk                            /*!< Interrupt Mask on line 14 */
9845 #define EXTI_IMR_MR15_Pos         (15U)
9846 #define EXTI_IMR_MR15_Msk         (0x1UL << EXTI_IMR_MR15_Pos)                  /*!< 0x00008000 */
9847 #define EXTI_IMR_MR15             EXTI_IMR_MR15_Msk                            /*!< Interrupt Mask on line 15 */
9848 #define EXTI_IMR_MR16_Pos         (16U)
9849 #define EXTI_IMR_MR16_Msk         (0x1UL << EXTI_IMR_MR16_Pos)                  /*!< 0x00010000 */
9850 #define EXTI_IMR_MR16             EXTI_IMR_MR16_Msk                            /*!< Interrupt Mask on line 16 */
9851 #define EXTI_IMR_MR17_Pos         (17U)
9852 #define EXTI_IMR_MR17_Msk         (0x1UL << EXTI_IMR_MR17_Pos)                  /*!< 0x00020000 */
9853 #define EXTI_IMR_MR17             EXTI_IMR_MR17_Msk                            /*!< Interrupt Mask on line 17 */
9854 #define EXTI_IMR_MR18_Pos         (18U)
9855 #define EXTI_IMR_MR18_Msk         (0x1UL << EXTI_IMR_MR18_Pos)                  /*!< 0x00040000 */
9856 #define EXTI_IMR_MR18             EXTI_IMR_MR18_Msk                            /*!< Interrupt Mask on line 18 */
9857 #define EXTI_IMR_MR19_Pos         (19U)
9858 #define EXTI_IMR_MR19_Msk         (0x1UL << EXTI_IMR_MR19_Pos)                  /*!< 0x00080000 */
9859 #define EXTI_IMR_MR19             EXTI_IMR_MR19_Msk                            /*!< Interrupt Mask on line 19 */
9860 #define EXTI_IMR_MR20_Pos         (20U)
9861 #define EXTI_IMR_MR20_Msk         (0x1UL << EXTI_IMR_MR20_Pos)                  /*!< 0x00100000 */
9862 #define EXTI_IMR_MR20             EXTI_IMR_MR20_Msk                            /*!< Interrupt Mask on line 20 */
9863 #define EXTI_IMR_MR21_Pos         (21U)
9864 #define EXTI_IMR_MR21_Msk         (0x1UL << EXTI_IMR_MR21_Pos)                  /*!< 0x00200000 */
9865 #define EXTI_IMR_MR21             EXTI_IMR_MR21_Msk                            /*!< Interrupt Mask on line 21 */
9866 #define EXTI_IMR_MR22_Pos         (22U)
9867 #define EXTI_IMR_MR22_Msk         (0x1UL << EXTI_IMR_MR22_Pos)                  /*!< 0x00400000 */
9868 #define EXTI_IMR_MR22             EXTI_IMR_MR22_Msk                            /*!< Interrupt Mask on line 22 */
9869 
9870 /* Reference Defines */
9871 #define  EXTI_IMR_IM0                        EXTI_IMR_MR0
9872 #define  EXTI_IMR_IM1                        EXTI_IMR_MR1
9873 #define  EXTI_IMR_IM2                        EXTI_IMR_MR2
9874 #define  EXTI_IMR_IM3                        EXTI_IMR_MR3
9875 #define  EXTI_IMR_IM4                        EXTI_IMR_MR4
9876 #define  EXTI_IMR_IM5                        EXTI_IMR_MR5
9877 #define  EXTI_IMR_IM6                        EXTI_IMR_MR6
9878 #define  EXTI_IMR_IM7                        EXTI_IMR_MR7
9879 #define  EXTI_IMR_IM8                        EXTI_IMR_MR8
9880 #define  EXTI_IMR_IM9                        EXTI_IMR_MR9
9881 #define  EXTI_IMR_IM10                       EXTI_IMR_MR10
9882 #define  EXTI_IMR_IM11                       EXTI_IMR_MR11
9883 #define  EXTI_IMR_IM12                       EXTI_IMR_MR12
9884 #define  EXTI_IMR_IM13                       EXTI_IMR_MR13
9885 #define  EXTI_IMR_IM14                       EXTI_IMR_MR14
9886 #define  EXTI_IMR_IM15                       EXTI_IMR_MR15
9887 #define  EXTI_IMR_IM16                       EXTI_IMR_MR16
9888 #define  EXTI_IMR_IM17                       EXTI_IMR_MR17
9889 #define  EXTI_IMR_IM18                       EXTI_IMR_MR18
9890 #define  EXTI_IMR_IM19                       EXTI_IMR_MR19
9891 #define  EXTI_IMR_IM20                       EXTI_IMR_MR20
9892 #define  EXTI_IMR_IM21                       EXTI_IMR_MR21
9893 #define  EXTI_IMR_IM22                       EXTI_IMR_MR22
9894 #define EXTI_IMR_IM_Pos           (0U)
9895 #define EXTI_IMR_IM_Msk           (0x7FFFFFUL << EXTI_IMR_IM_Pos)               /*!< 0x007FFFFF */
9896 #define EXTI_IMR_IM               EXTI_IMR_IM_Msk                              /*!< Interrupt Mask All */
9897 
9898 /*******************  Bit definition for EXTI_EMR register  *******************/
9899 #define EXTI_EMR_MR0_Pos          (0U)
9900 #define EXTI_EMR_MR0_Msk          (0x1UL << EXTI_EMR_MR0_Pos)                   /*!< 0x00000001 */
9901 #define EXTI_EMR_MR0              EXTI_EMR_MR0_Msk                             /*!< Event Mask on line 0 */
9902 #define EXTI_EMR_MR1_Pos          (1U)
9903 #define EXTI_EMR_MR1_Msk          (0x1UL << EXTI_EMR_MR1_Pos)                   /*!< 0x00000002 */
9904 #define EXTI_EMR_MR1              EXTI_EMR_MR1_Msk                             /*!< Event Mask on line 1 */
9905 #define EXTI_EMR_MR2_Pos          (2U)
9906 #define EXTI_EMR_MR2_Msk          (0x1UL << EXTI_EMR_MR2_Pos)                   /*!< 0x00000004 */
9907 #define EXTI_EMR_MR2              EXTI_EMR_MR2_Msk                             /*!< Event Mask on line 2 */
9908 #define EXTI_EMR_MR3_Pos          (3U)
9909 #define EXTI_EMR_MR3_Msk          (0x1UL << EXTI_EMR_MR3_Pos)                   /*!< 0x00000008 */
9910 #define EXTI_EMR_MR3              EXTI_EMR_MR3_Msk                             /*!< Event Mask on line 3 */
9911 #define EXTI_EMR_MR4_Pos          (4U)
9912 #define EXTI_EMR_MR4_Msk          (0x1UL << EXTI_EMR_MR4_Pos)                   /*!< 0x00000010 */
9913 #define EXTI_EMR_MR4              EXTI_EMR_MR4_Msk                             /*!< Event Mask on line 4 */
9914 #define EXTI_EMR_MR5_Pos          (5U)
9915 #define EXTI_EMR_MR5_Msk          (0x1UL << EXTI_EMR_MR5_Pos)                   /*!< 0x00000020 */
9916 #define EXTI_EMR_MR5              EXTI_EMR_MR5_Msk                             /*!< Event Mask on line 5 */
9917 #define EXTI_EMR_MR6_Pos          (6U)
9918 #define EXTI_EMR_MR6_Msk          (0x1UL << EXTI_EMR_MR6_Pos)                   /*!< 0x00000040 */
9919 #define EXTI_EMR_MR6              EXTI_EMR_MR6_Msk                             /*!< Event Mask on line 6 */
9920 #define EXTI_EMR_MR7_Pos          (7U)
9921 #define EXTI_EMR_MR7_Msk          (0x1UL << EXTI_EMR_MR7_Pos)                   /*!< 0x00000080 */
9922 #define EXTI_EMR_MR7              EXTI_EMR_MR7_Msk                             /*!< Event Mask on line 7 */
9923 #define EXTI_EMR_MR8_Pos          (8U)
9924 #define EXTI_EMR_MR8_Msk          (0x1UL << EXTI_EMR_MR8_Pos)                   /*!< 0x00000100 */
9925 #define EXTI_EMR_MR8              EXTI_EMR_MR8_Msk                             /*!< Event Mask on line 8 */
9926 #define EXTI_EMR_MR9_Pos          (9U)
9927 #define EXTI_EMR_MR9_Msk          (0x1UL << EXTI_EMR_MR9_Pos)                   /*!< 0x00000200 */
9928 #define EXTI_EMR_MR9              EXTI_EMR_MR9_Msk                             /*!< Event Mask on line 9 */
9929 #define EXTI_EMR_MR10_Pos         (10U)
9930 #define EXTI_EMR_MR10_Msk         (0x1UL << EXTI_EMR_MR10_Pos)                  /*!< 0x00000400 */
9931 #define EXTI_EMR_MR10             EXTI_EMR_MR10_Msk                            /*!< Event Mask on line 10 */
9932 #define EXTI_EMR_MR11_Pos         (11U)
9933 #define EXTI_EMR_MR11_Msk         (0x1UL << EXTI_EMR_MR11_Pos)                  /*!< 0x00000800 */
9934 #define EXTI_EMR_MR11             EXTI_EMR_MR11_Msk                            /*!< Event Mask on line 11 */
9935 #define EXTI_EMR_MR12_Pos         (12U)
9936 #define EXTI_EMR_MR12_Msk         (0x1UL << EXTI_EMR_MR12_Pos)                  /*!< 0x00001000 */
9937 #define EXTI_EMR_MR12             EXTI_EMR_MR12_Msk                            /*!< Event Mask on line 12 */
9938 #define EXTI_EMR_MR13_Pos         (13U)
9939 #define EXTI_EMR_MR13_Msk         (0x1UL << EXTI_EMR_MR13_Pos)                  /*!< 0x00002000 */
9940 #define EXTI_EMR_MR13             EXTI_EMR_MR13_Msk                            /*!< Event Mask on line 13 */
9941 #define EXTI_EMR_MR14_Pos         (14U)
9942 #define EXTI_EMR_MR14_Msk         (0x1UL << EXTI_EMR_MR14_Pos)                  /*!< 0x00004000 */
9943 #define EXTI_EMR_MR14             EXTI_EMR_MR14_Msk                            /*!< Event Mask on line 14 */
9944 #define EXTI_EMR_MR15_Pos         (15U)
9945 #define EXTI_EMR_MR15_Msk         (0x1UL << EXTI_EMR_MR15_Pos)                  /*!< 0x00008000 */
9946 #define EXTI_EMR_MR15             EXTI_EMR_MR15_Msk                            /*!< Event Mask on line 15 */
9947 #define EXTI_EMR_MR16_Pos         (16U)
9948 #define EXTI_EMR_MR16_Msk         (0x1UL << EXTI_EMR_MR16_Pos)                  /*!< 0x00010000 */
9949 #define EXTI_EMR_MR16             EXTI_EMR_MR16_Msk                            /*!< Event Mask on line 16 */
9950 #define EXTI_EMR_MR17_Pos         (17U)
9951 #define EXTI_EMR_MR17_Msk         (0x1UL << EXTI_EMR_MR17_Pos)                  /*!< 0x00020000 */
9952 #define EXTI_EMR_MR17             EXTI_EMR_MR17_Msk                            /*!< Event Mask on line 17 */
9953 #define EXTI_EMR_MR18_Pos         (18U)
9954 #define EXTI_EMR_MR18_Msk         (0x1UL << EXTI_EMR_MR18_Pos)                  /*!< 0x00040000 */
9955 #define EXTI_EMR_MR18             EXTI_EMR_MR18_Msk                            /*!< Event Mask on line 18 */
9956 #define EXTI_EMR_MR19_Pos         (19U)
9957 #define EXTI_EMR_MR19_Msk         (0x1UL << EXTI_EMR_MR19_Pos)                  /*!< 0x00080000 */
9958 #define EXTI_EMR_MR19             EXTI_EMR_MR19_Msk                            /*!< Event Mask on line 19 */
9959 #define EXTI_EMR_MR20_Pos         (20U)
9960 #define EXTI_EMR_MR20_Msk         (0x1UL << EXTI_EMR_MR20_Pos)                  /*!< 0x00100000 */
9961 #define EXTI_EMR_MR20             EXTI_EMR_MR20_Msk                            /*!< Event Mask on line 20 */
9962 #define EXTI_EMR_MR21_Pos         (21U)
9963 #define EXTI_EMR_MR21_Msk         (0x1UL << EXTI_EMR_MR21_Pos)                  /*!< 0x00200000 */
9964 #define EXTI_EMR_MR21             EXTI_EMR_MR21_Msk                            /*!< Event Mask on line 21 */
9965 #define EXTI_EMR_MR22_Pos         (22U)
9966 #define EXTI_EMR_MR22_Msk         (0x1UL << EXTI_EMR_MR22_Pos)                  /*!< 0x00400000 */
9967 #define EXTI_EMR_MR22             EXTI_EMR_MR22_Msk                            /*!< Event Mask on line 22 */
9968 
9969 /* Reference Defines */
9970 #define  EXTI_EMR_EM0                        EXTI_EMR_MR0
9971 #define  EXTI_EMR_EM1                        EXTI_EMR_MR1
9972 #define  EXTI_EMR_EM2                        EXTI_EMR_MR2
9973 #define  EXTI_EMR_EM3                        EXTI_EMR_MR3
9974 #define  EXTI_EMR_EM4                        EXTI_EMR_MR4
9975 #define  EXTI_EMR_EM5                        EXTI_EMR_MR5
9976 #define  EXTI_EMR_EM6                        EXTI_EMR_MR6
9977 #define  EXTI_EMR_EM7                        EXTI_EMR_MR7
9978 #define  EXTI_EMR_EM8                        EXTI_EMR_MR8
9979 #define  EXTI_EMR_EM9                        EXTI_EMR_MR9
9980 #define  EXTI_EMR_EM10                       EXTI_EMR_MR10
9981 #define  EXTI_EMR_EM11                       EXTI_EMR_MR11
9982 #define  EXTI_EMR_EM12                       EXTI_EMR_MR12
9983 #define  EXTI_EMR_EM13                       EXTI_EMR_MR13
9984 #define  EXTI_EMR_EM14                       EXTI_EMR_MR14
9985 #define  EXTI_EMR_EM15                       EXTI_EMR_MR15
9986 #define  EXTI_EMR_EM16                       EXTI_EMR_MR16
9987 #define  EXTI_EMR_EM17                       EXTI_EMR_MR17
9988 #define  EXTI_EMR_EM18                       EXTI_EMR_MR18
9989 #define  EXTI_EMR_EM19                       EXTI_EMR_MR19
9990 #define  EXTI_EMR_EM20                       EXTI_EMR_MR20
9991 #define  EXTI_EMR_EM21                       EXTI_EMR_MR21
9992 #define  EXTI_EMR_EM22                       EXTI_EMR_MR22
9993 
9994 /******************  Bit definition for EXTI_RTSR register  *******************/
9995 #define EXTI_RTSR_TR0_Pos         (0U)
9996 #define EXTI_RTSR_TR0_Msk         (0x1UL << EXTI_RTSR_TR0_Pos)                  /*!< 0x00000001 */
9997 #define EXTI_RTSR_TR0             EXTI_RTSR_TR0_Msk                            /*!< Rising trigger event configuration bit of line 0 */
9998 #define EXTI_RTSR_TR1_Pos         (1U)
9999 #define EXTI_RTSR_TR1_Msk         (0x1UL << EXTI_RTSR_TR1_Pos)                  /*!< 0x00000002 */
10000 #define EXTI_RTSR_TR1             EXTI_RTSR_TR1_Msk                            /*!< Rising trigger event configuration bit of line 1 */
10001 #define EXTI_RTSR_TR2_Pos         (2U)
10002 #define EXTI_RTSR_TR2_Msk         (0x1UL << EXTI_RTSR_TR2_Pos)                  /*!< 0x00000004 */
10003 #define EXTI_RTSR_TR2             EXTI_RTSR_TR2_Msk                            /*!< Rising trigger event configuration bit of line 2 */
10004 #define EXTI_RTSR_TR3_Pos         (3U)
10005 #define EXTI_RTSR_TR3_Msk         (0x1UL << EXTI_RTSR_TR3_Pos)                  /*!< 0x00000008 */
10006 #define EXTI_RTSR_TR3             EXTI_RTSR_TR3_Msk                            /*!< Rising trigger event configuration bit of line 3 */
10007 #define EXTI_RTSR_TR4_Pos         (4U)
10008 #define EXTI_RTSR_TR4_Msk         (0x1UL << EXTI_RTSR_TR4_Pos)                  /*!< 0x00000010 */
10009 #define EXTI_RTSR_TR4             EXTI_RTSR_TR4_Msk                            /*!< Rising trigger event configuration bit of line 4 */
10010 #define EXTI_RTSR_TR5_Pos         (5U)
10011 #define EXTI_RTSR_TR5_Msk         (0x1UL << EXTI_RTSR_TR5_Pos)                  /*!< 0x00000020 */
10012 #define EXTI_RTSR_TR5             EXTI_RTSR_TR5_Msk                            /*!< Rising trigger event configuration bit of line 5 */
10013 #define EXTI_RTSR_TR6_Pos         (6U)
10014 #define EXTI_RTSR_TR6_Msk         (0x1UL << EXTI_RTSR_TR6_Pos)                  /*!< 0x00000040 */
10015 #define EXTI_RTSR_TR6             EXTI_RTSR_TR6_Msk                            /*!< Rising trigger event configuration bit of line 6 */
10016 #define EXTI_RTSR_TR7_Pos         (7U)
10017 #define EXTI_RTSR_TR7_Msk         (0x1UL << EXTI_RTSR_TR7_Pos)                  /*!< 0x00000080 */
10018 #define EXTI_RTSR_TR7             EXTI_RTSR_TR7_Msk                            /*!< Rising trigger event configuration bit of line 7 */
10019 #define EXTI_RTSR_TR8_Pos         (8U)
10020 #define EXTI_RTSR_TR8_Msk         (0x1UL << EXTI_RTSR_TR8_Pos)                  /*!< 0x00000100 */
10021 #define EXTI_RTSR_TR8             EXTI_RTSR_TR8_Msk                            /*!< Rising trigger event configuration bit of line 8 */
10022 #define EXTI_RTSR_TR9_Pos         (9U)
10023 #define EXTI_RTSR_TR9_Msk         (0x1UL << EXTI_RTSR_TR9_Pos)                  /*!< 0x00000200 */
10024 #define EXTI_RTSR_TR9             EXTI_RTSR_TR9_Msk                            /*!< Rising trigger event configuration bit of line 9 */
10025 #define EXTI_RTSR_TR10_Pos        (10U)
10026 #define EXTI_RTSR_TR10_Msk        (0x1UL << EXTI_RTSR_TR10_Pos)                 /*!< 0x00000400 */
10027 #define EXTI_RTSR_TR10            EXTI_RTSR_TR10_Msk                           /*!< Rising trigger event configuration bit of line 10 */
10028 #define EXTI_RTSR_TR11_Pos        (11U)
10029 #define EXTI_RTSR_TR11_Msk        (0x1UL << EXTI_RTSR_TR11_Pos)                 /*!< 0x00000800 */
10030 #define EXTI_RTSR_TR11            EXTI_RTSR_TR11_Msk                           /*!< Rising trigger event configuration bit of line 11 */
10031 #define EXTI_RTSR_TR12_Pos        (12U)
10032 #define EXTI_RTSR_TR12_Msk        (0x1UL << EXTI_RTSR_TR12_Pos)                 /*!< 0x00001000 */
10033 #define EXTI_RTSR_TR12            EXTI_RTSR_TR12_Msk                           /*!< Rising trigger event configuration bit of line 12 */
10034 #define EXTI_RTSR_TR13_Pos        (13U)
10035 #define EXTI_RTSR_TR13_Msk        (0x1UL << EXTI_RTSR_TR13_Pos)                 /*!< 0x00002000 */
10036 #define EXTI_RTSR_TR13            EXTI_RTSR_TR13_Msk                           /*!< Rising trigger event configuration bit of line 13 */
10037 #define EXTI_RTSR_TR14_Pos        (14U)
10038 #define EXTI_RTSR_TR14_Msk        (0x1UL << EXTI_RTSR_TR14_Pos)                 /*!< 0x00004000 */
10039 #define EXTI_RTSR_TR14            EXTI_RTSR_TR14_Msk                           /*!< Rising trigger event configuration bit of line 14 */
10040 #define EXTI_RTSR_TR15_Pos        (15U)
10041 #define EXTI_RTSR_TR15_Msk        (0x1UL << EXTI_RTSR_TR15_Pos)                 /*!< 0x00008000 */
10042 #define EXTI_RTSR_TR15            EXTI_RTSR_TR15_Msk                           /*!< Rising trigger event configuration bit of line 15 */
10043 #define EXTI_RTSR_TR16_Pos        (16U)
10044 #define EXTI_RTSR_TR16_Msk        (0x1UL << EXTI_RTSR_TR16_Pos)                 /*!< 0x00010000 */
10045 #define EXTI_RTSR_TR16            EXTI_RTSR_TR16_Msk                           /*!< Rising trigger event configuration bit of line 16 */
10046 #define EXTI_RTSR_TR17_Pos        (17U)
10047 #define EXTI_RTSR_TR17_Msk        (0x1UL << EXTI_RTSR_TR17_Pos)                 /*!< 0x00020000 */
10048 #define EXTI_RTSR_TR17            EXTI_RTSR_TR17_Msk                           /*!< Rising trigger event configuration bit of line 17 */
10049 #define EXTI_RTSR_TR18_Pos        (18U)
10050 #define EXTI_RTSR_TR18_Msk        (0x1UL << EXTI_RTSR_TR18_Pos)                 /*!< 0x00040000 */
10051 #define EXTI_RTSR_TR18            EXTI_RTSR_TR18_Msk                           /*!< Rising trigger event configuration bit of line 18 */
10052 #define EXTI_RTSR_TR19_Pos        (19U)
10053 #define EXTI_RTSR_TR19_Msk        (0x1UL << EXTI_RTSR_TR19_Pos)                 /*!< 0x00080000 */
10054 #define EXTI_RTSR_TR19            EXTI_RTSR_TR19_Msk                           /*!< Rising trigger event configuration bit of line 19 */
10055 #define EXTI_RTSR_TR20_Pos        (20U)
10056 #define EXTI_RTSR_TR20_Msk        (0x1UL << EXTI_RTSR_TR20_Pos)                 /*!< 0x00100000 */
10057 #define EXTI_RTSR_TR20            EXTI_RTSR_TR20_Msk                           /*!< Rising trigger event configuration bit of line 20 */
10058 #define EXTI_RTSR_TR21_Pos        (21U)
10059 #define EXTI_RTSR_TR21_Msk        (0x1UL << EXTI_RTSR_TR21_Pos)                 /*!< 0x00200000 */
10060 #define EXTI_RTSR_TR21            EXTI_RTSR_TR21_Msk                           /*!< Rising trigger event configuration bit of line 21 */
10061 #define EXTI_RTSR_TR22_Pos        (22U)
10062 #define EXTI_RTSR_TR22_Msk        (0x1UL << EXTI_RTSR_TR22_Pos)                 /*!< 0x00400000 */
10063 #define EXTI_RTSR_TR22            EXTI_RTSR_TR22_Msk                           /*!< Rising trigger event configuration bit of line 22 */
10064 
10065 /******************  Bit definition for EXTI_FTSR register  *******************/
10066 #define EXTI_FTSR_TR0_Pos         (0U)
10067 #define EXTI_FTSR_TR0_Msk         (0x1UL << EXTI_FTSR_TR0_Pos)                  /*!< 0x00000001 */
10068 #define EXTI_FTSR_TR0             EXTI_FTSR_TR0_Msk                            /*!< Falling trigger event configuration bit of line 0 */
10069 #define EXTI_FTSR_TR1_Pos         (1U)
10070 #define EXTI_FTSR_TR1_Msk         (0x1UL << EXTI_FTSR_TR1_Pos)                  /*!< 0x00000002 */
10071 #define EXTI_FTSR_TR1             EXTI_FTSR_TR1_Msk                            /*!< Falling trigger event configuration bit of line 1 */
10072 #define EXTI_FTSR_TR2_Pos         (2U)
10073 #define EXTI_FTSR_TR2_Msk         (0x1UL << EXTI_FTSR_TR2_Pos)                  /*!< 0x00000004 */
10074 #define EXTI_FTSR_TR2             EXTI_FTSR_TR2_Msk                            /*!< Falling trigger event configuration bit of line 2 */
10075 #define EXTI_FTSR_TR3_Pos         (3U)
10076 #define EXTI_FTSR_TR3_Msk         (0x1UL << EXTI_FTSR_TR3_Pos)                  /*!< 0x00000008 */
10077 #define EXTI_FTSR_TR3             EXTI_FTSR_TR3_Msk                            /*!< Falling trigger event configuration bit of line 3 */
10078 #define EXTI_FTSR_TR4_Pos         (4U)
10079 #define EXTI_FTSR_TR4_Msk         (0x1UL << EXTI_FTSR_TR4_Pos)                  /*!< 0x00000010 */
10080 #define EXTI_FTSR_TR4             EXTI_FTSR_TR4_Msk                            /*!< Falling trigger event configuration bit of line 4 */
10081 #define EXTI_FTSR_TR5_Pos         (5U)
10082 #define EXTI_FTSR_TR5_Msk         (0x1UL << EXTI_FTSR_TR5_Pos)                  /*!< 0x00000020 */
10083 #define EXTI_FTSR_TR5             EXTI_FTSR_TR5_Msk                            /*!< Falling trigger event configuration bit of line 5 */
10084 #define EXTI_FTSR_TR6_Pos         (6U)
10085 #define EXTI_FTSR_TR6_Msk         (0x1UL << EXTI_FTSR_TR6_Pos)                  /*!< 0x00000040 */
10086 #define EXTI_FTSR_TR6             EXTI_FTSR_TR6_Msk                            /*!< Falling trigger event configuration bit of line 6 */
10087 #define EXTI_FTSR_TR7_Pos         (7U)
10088 #define EXTI_FTSR_TR7_Msk         (0x1UL << EXTI_FTSR_TR7_Pos)                  /*!< 0x00000080 */
10089 #define EXTI_FTSR_TR7             EXTI_FTSR_TR7_Msk                            /*!< Falling trigger event configuration bit of line 7 */
10090 #define EXTI_FTSR_TR8_Pos         (8U)
10091 #define EXTI_FTSR_TR8_Msk         (0x1UL << EXTI_FTSR_TR8_Pos)                  /*!< 0x00000100 */
10092 #define EXTI_FTSR_TR8             EXTI_FTSR_TR8_Msk                            /*!< Falling trigger event configuration bit of line 8 */
10093 #define EXTI_FTSR_TR9_Pos         (9U)
10094 #define EXTI_FTSR_TR9_Msk         (0x1UL << EXTI_FTSR_TR9_Pos)                  /*!< 0x00000200 */
10095 #define EXTI_FTSR_TR9             EXTI_FTSR_TR9_Msk                            /*!< Falling trigger event configuration bit of line 9 */
10096 #define EXTI_FTSR_TR10_Pos        (10U)
10097 #define EXTI_FTSR_TR10_Msk        (0x1UL << EXTI_FTSR_TR10_Pos)                 /*!< 0x00000400 */
10098 #define EXTI_FTSR_TR10            EXTI_FTSR_TR10_Msk                           /*!< Falling trigger event configuration bit of line 10 */
10099 #define EXTI_FTSR_TR11_Pos        (11U)
10100 #define EXTI_FTSR_TR11_Msk        (0x1UL << EXTI_FTSR_TR11_Pos)                 /*!< 0x00000800 */
10101 #define EXTI_FTSR_TR11            EXTI_FTSR_TR11_Msk                           /*!< Falling trigger event configuration bit of line 11 */
10102 #define EXTI_FTSR_TR12_Pos        (12U)
10103 #define EXTI_FTSR_TR12_Msk        (0x1UL << EXTI_FTSR_TR12_Pos)                 /*!< 0x00001000 */
10104 #define EXTI_FTSR_TR12            EXTI_FTSR_TR12_Msk                           /*!< Falling trigger event configuration bit of line 12 */
10105 #define EXTI_FTSR_TR13_Pos        (13U)
10106 #define EXTI_FTSR_TR13_Msk        (0x1UL << EXTI_FTSR_TR13_Pos)                 /*!< 0x00002000 */
10107 #define EXTI_FTSR_TR13            EXTI_FTSR_TR13_Msk                           /*!< Falling trigger event configuration bit of line 13 */
10108 #define EXTI_FTSR_TR14_Pos        (14U)
10109 #define EXTI_FTSR_TR14_Msk        (0x1UL << EXTI_FTSR_TR14_Pos)                 /*!< 0x00004000 */
10110 #define EXTI_FTSR_TR14            EXTI_FTSR_TR14_Msk                           /*!< Falling trigger event configuration bit of line 14 */
10111 #define EXTI_FTSR_TR15_Pos        (15U)
10112 #define EXTI_FTSR_TR15_Msk        (0x1UL << EXTI_FTSR_TR15_Pos)                 /*!< 0x00008000 */
10113 #define EXTI_FTSR_TR15            EXTI_FTSR_TR15_Msk                           /*!< Falling trigger event configuration bit of line 15 */
10114 #define EXTI_FTSR_TR16_Pos        (16U)
10115 #define EXTI_FTSR_TR16_Msk        (0x1UL << EXTI_FTSR_TR16_Pos)                 /*!< 0x00010000 */
10116 #define EXTI_FTSR_TR16            EXTI_FTSR_TR16_Msk                           /*!< Falling trigger event configuration bit of line 16 */
10117 #define EXTI_FTSR_TR17_Pos        (17U)
10118 #define EXTI_FTSR_TR17_Msk        (0x1UL << EXTI_FTSR_TR17_Pos)                 /*!< 0x00020000 */
10119 #define EXTI_FTSR_TR17            EXTI_FTSR_TR17_Msk                           /*!< Falling trigger event configuration bit of line 17 */
10120 #define EXTI_FTSR_TR18_Pos        (18U)
10121 #define EXTI_FTSR_TR18_Msk        (0x1UL << EXTI_FTSR_TR18_Pos)                 /*!< 0x00040000 */
10122 #define EXTI_FTSR_TR18            EXTI_FTSR_TR18_Msk                           /*!< Falling trigger event configuration bit of line 18 */
10123 #define EXTI_FTSR_TR19_Pos        (19U)
10124 #define EXTI_FTSR_TR19_Msk        (0x1UL << EXTI_FTSR_TR19_Pos)                 /*!< 0x00080000 */
10125 #define EXTI_FTSR_TR19            EXTI_FTSR_TR19_Msk                           /*!< Falling trigger event configuration bit of line 19 */
10126 #define EXTI_FTSR_TR20_Pos        (20U)
10127 #define EXTI_FTSR_TR20_Msk        (0x1UL << EXTI_FTSR_TR20_Pos)                 /*!< 0x00100000 */
10128 #define EXTI_FTSR_TR20            EXTI_FTSR_TR20_Msk                           /*!< Falling trigger event configuration bit of line 20 */
10129 #define EXTI_FTSR_TR21_Pos        (21U)
10130 #define EXTI_FTSR_TR21_Msk        (0x1UL << EXTI_FTSR_TR21_Pos)                 /*!< 0x00200000 */
10131 #define EXTI_FTSR_TR21            EXTI_FTSR_TR21_Msk                           /*!< Falling trigger event configuration bit of line 21 */
10132 #define EXTI_FTSR_TR22_Pos        (22U)
10133 #define EXTI_FTSR_TR22_Msk        (0x1UL << EXTI_FTSR_TR22_Pos)                 /*!< 0x00400000 */
10134 #define EXTI_FTSR_TR22            EXTI_FTSR_TR22_Msk                           /*!< Falling trigger event configuration bit of line 22 */
10135 
10136 /******************  Bit definition for EXTI_SWIER register  ******************/
10137 #define EXTI_SWIER_SWIER0_Pos     (0U)
10138 #define EXTI_SWIER_SWIER0_Msk     (0x1UL << EXTI_SWIER_SWIER0_Pos)              /*!< 0x00000001 */
10139 #define EXTI_SWIER_SWIER0         EXTI_SWIER_SWIER0_Msk                        /*!< Software Interrupt on line 0 */
10140 #define EXTI_SWIER_SWIER1_Pos     (1U)
10141 #define EXTI_SWIER_SWIER1_Msk     (0x1UL << EXTI_SWIER_SWIER1_Pos)              /*!< 0x00000002 */
10142 #define EXTI_SWIER_SWIER1         EXTI_SWIER_SWIER1_Msk                        /*!< Software Interrupt on line 1 */
10143 #define EXTI_SWIER_SWIER2_Pos     (2U)
10144 #define EXTI_SWIER_SWIER2_Msk     (0x1UL << EXTI_SWIER_SWIER2_Pos)              /*!< 0x00000004 */
10145 #define EXTI_SWIER_SWIER2         EXTI_SWIER_SWIER2_Msk                        /*!< Software Interrupt on line 2 */
10146 #define EXTI_SWIER_SWIER3_Pos     (3U)
10147 #define EXTI_SWIER_SWIER3_Msk     (0x1UL << EXTI_SWIER_SWIER3_Pos)              /*!< 0x00000008 */
10148 #define EXTI_SWIER_SWIER3         EXTI_SWIER_SWIER3_Msk                        /*!< Software Interrupt on line 3 */
10149 #define EXTI_SWIER_SWIER4_Pos     (4U)
10150 #define EXTI_SWIER_SWIER4_Msk     (0x1UL << EXTI_SWIER_SWIER4_Pos)              /*!< 0x00000010 */
10151 #define EXTI_SWIER_SWIER4         EXTI_SWIER_SWIER4_Msk                        /*!< Software Interrupt on line 4 */
10152 #define EXTI_SWIER_SWIER5_Pos     (5U)
10153 #define EXTI_SWIER_SWIER5_Msk     (0x1UL << EXTI_SWIER_SWIER5_Pos)              /*!< 0x00000020 */
10154 #define EXTI_SWIER_SWIER5         EXTI_SWIER_SWIER5_Msk                        /*!< Software Interrupt on line 5 */
10155 #define EXTI_SWIER_SWIER6_Pos     (6U)
10156 #define EXTI_SWIER_SWIER6_Msk     (0x1UL << EXTI_SWIER_SWIER6_Pos)              /*!< 0x00000040 */
10157 #define EXTI_SWIER_SWIER6         EXTI_SWIER_SWIER6_Msk                        /*!< Software Interrupt on line 6 */
10158 #define EXTI_SWIER_SWIER7_Pos     (7U)
10159 #define EXTI_SWIER_SWIER7_Msk     (0x1UL << EXTI_SWIER_SWIER7_Pos)              /*!< 0x00000080 */
10160 #define EXTI_SWIER_SWIER7         EXTI_SWIER_SWIER7_Msk                        /*!< Software Interrupt on line 7 */
10161 #define EXTI_SWIER_SWIER8_Pos     (8U)
10162 #define EXTI_SWIER_SWIER8_Msk     (0x1UL << EXTI_SWIER_SWIER8_Pos)              /*!< 0x00000100 */
10163 #define EXTI_SWIER_SWIER8         EXTI_SWIER_SWIER8_Msk                        /*!< Software Interrupt on line 8 */
10164 #define EXTI_SWIER_SWIER9_Pos     (9U)
10165 #define EXTI_SWIER_SWIER9_Msk     (0x1UL << EXTI_SWIER_SWIER9_Pos)              /*!< 0x00000200 */
10166 #define EXTI_SWIER_SWIER9         EXTI_SWIER_SWIER9_Msk                        /*!< Software Interrupt on line 9 */
10167 #define EXTI_SWIER_SWIER10_Pos    (10U)
10168 #define EXTI_SWIER_SWIER10_Msk    (0x1UL << EXTI_SWIER_SWIER10_Pos)             /*!< 0x00000400 */
10169 #define EXTI_SWIER_SWIER10        EXTI_SWIER_SWIER10_Msk                       /*!< Software Interrupt on line 10 */
10170 #define EXTI_SWIER_SWIER11_Pos    (11U)
10171 #define EXTI_SWIER_SWIER11_Msk    (0x1UL << EXTI_SWIER_SWIER11_Pos)             /*!< 0x00000800 */
10172 #define EXTI_SWIER_SWIER11        EXTI_SWIER_SWIER11_Msk                       /*!< Software Interrupt on line 11 */
10173 #define EXTI_SWIER_SWIER12_Pos    (12U)
10174 #define EXTI_SWIER_SWIER12_Msk    (0x1UL << EXTI_SWIER_SWIER12_Pos)             /*!< 0x00001000 */
10175 #define EXTI_SWIER_SWIER12        EXTI_SWIER_SWIER12_Msk                       /*!< Software Interrupt on line 12 */
10176 #define EXTI_SWIER_SWIER13_Pos    (13U)
10177 #define EXTI_SWIER_SWIER13_Msk    (0x1UL << EXTI_SWIER_SWIER13_Pos)             /*!< 0x00002000 */
10178 #define EXTI_SWIER_SWIER13        EXTI_SWIER_SWIER13_Msk                       /*!< Software Interrupt on line 13 */
10179 #define EXTI_SWIER_SWIER14_Pos    (14U)
10180 #define EXTI_SWIER_SWIER14_Msk    (0x1UL << EXTI_SWIER_SWIER14_Pos)             /*!< 0x00004000 */
10181 #define EXTI_SWIER_SWIER14        EXTI_SWIER_SWIER14_Msk                       /*!< Software Interrupt on line 14 */
10182 #define EXTI_SWIER_SWIER15_Pos    (15U)
10183 #define EXTI_SWIER_SWIER15_Msk    (0x1UL << EXTI_SWIER_SWIER15_Pos)             /*!< 0x00008000 */
10184 #define EXTI_SWIER_SWIER15        EXTI_SWIER_SWIER15_Msk                       /*!< Software Interrupt on line 15 */
10185 #define EXTI_SWIER_SWIER16_Pos    (16U)
10186 #define EXTI_SWIER_SWIER16_Msk    (0x1UL << EXTI_SWIER_SWIER16_Pos)             /*!< 0x00010000 */
10187 #define EXTI_SWIER_SWIER16        EXTI_SWIER_SWIER16_Msk                       /*!< Software Interrupt on line 16 */
10188 #define EXTI_SWIER_SWIER17_Pos    (17U)
10189 #define EXTI_SWIER_SWIER17_Msk    (0x1UL << EXTI_SWIER_SWIER17_Pos)             /*!< 0x00020000 */
10190 #define EXTI_SWIER_SWIER17        EXTI_SWIER_SWIER17_Msk                       /*!< Software Interrupt on line 17 */
10191 #define EXTI_SWIER_SWIER18_Pos    (18U)
10192 #define EXTI_SWIER_SWIER18_Msk    (0x1UL << EXTI_SWIER_SWIER18_Pos)             /*!< 0x00040000 */
10193 #define EXTI_SWIER_SWIER18        EXTI_SWIER_SWIER18_Msk                       /*!< Software Interrupt on line 18 */
10194 #define EXTI_SWIER_SWIER19_Pos    (19U)
10195 #define EXTI_SWIER_SWIER19_Msk    (0x1UL << EXTI_SWIER_SWIER19_Pos)             /*!< 0x00080000 */
10196 #define EXTI_SWIER_SWIER19        EXTI_SWIER_SWIER19_Msk                       /*!< Software Interrupt on line 19 */
10197 #define EXTI_SWIER_SWIER20_Pos    (20U)
10198 #define EXTI_SWIER_SWIER20_Msk    (0x1UL << EXTI_SWIER_SWIER20_Pos)             /*!< 0x00100000 */
10199 #define EXTI_SWIER_SWIER20        EXTI_SWIER_SWIER20_Msk                       /*!< Software Interrupt on line 20 */
10200 #define EXTI_SWIER_SWIER21_Pos    (21U)
10201 #define EXTI_SWIER_SWIER21_Msk    (0x1UL << EXTI_SWIER_SWIER21_Pos)             /*!< 0x00200000 */
10202 #define EXTI_SWIER_SWIER21        EXTI_SWIER_SWIER21_Msk                       /*!< Software Interrupt on line 21 */
10203 #define EXTI_SWIER_SWIER22_Pos    (22U)
10204 #define EXTI_SWIER_SWIER22_Msk    (0x1UL << EXTI_SWIER_SWIER22_Pos)             /*!< 0x00400000 */
10205 #define EXTI_SWIER_SWIER22        EXTI_SWIER_SWIER22_Msk                       /*!< Software Interrupt on line 22 */
10206 
10207 /*******************  Bit definition for EXTI_PR register  ********************/
10208 #define EXTI_PR_PR0_Pos           (0U)
10209 #define EXTI_PR_PR0_Msk           (0x1UL << EXTI_PR_PR0_Pos)                    /*!< 0x00000001 */
10210 #define EXTI_PR_PR0               EXTI_PR_PR0_Msk                              /*!< Pending bit for line 0 */
10211 #define EXTI_PR_PR1_Pos           (1U)
10212 #define EXTI_PR_PR1_Msk           (0x1UL << EXTI_PR_PR1_Pos)                    /*!< 0x00000002 */
10213 #define EXTI_PR_PR1               EXTI_PR_PR1_Msk                              /*!< Pending bit for line 1 */
10214 #define EXTI_PR_PR2_Pos           (2U)
10215 #define EXTI_PR_PR2_Msk           (0x1UL << EXTI_PR_PR2_Pos)                    /*!< 0x00000004 */
10216 #define EXTI_PR_PR2               EXTI_PR_PR2_Msk                              /*!< Pending bit for line 2 */
10217 #define EXTI_PR_PR3_Pos           (3U)
10218 #define EXTI_PR_PR3_Msk           (0x1UL << EXTI_PR_PR3_Pos)                    /*!< 0x00000008 */
10219 #define EXTI_PR_PR3               EXTI_PR_PR3_Msk                              /*!< Pending bit for line 3 */
10220 #define EXTI_PR_PR4_Pos           (4U)
10221 #define EXTI_PR_PR4_Msk           (0x1UL << EXTI_PR_PR4_Pos)                    /*!< 0x00000010 */
10222 #define EXTI_PR_PR4               EXTI_PR_PR4_Msk                              /*!< Pending bit for line 4 */
10223 #define EXTI_PR_PR5_Pos           (5U)
10224 #define EXTI_PR_PR5_Msk           (0x1UL << EXTI_PR_PR5_Pos)                    /*!< 0x00000020 */
10225 #define EXTI_PR_PR5               EXTI_PR_PR5_Msk                              /*!< Pending bit for line 5 */
10226 #define EXTI_PR_PR6_Pos           (6U)
10227 #define EXTI_PR_PR6_Msk           (0x1UL << EXTI_PR_PR6_Pos)                    /*!< 0x00000040 */
10228 #define EXTI_PR_PR6               EXTI_PR_PR6_Msk                              /*!< Pending bit for line 6 */
10229 #define EXTI_PR_PR7_Pos           (7U)
10230 #define EXTI_PR_PR7_Msk           (0x1UL << EXTI_PR_PR7_Pos)                    /*!< 0x00000080 */
10231 #define EXTI_PR_PR7               EXTI_PR_PR7_Msk                              /*!< Pending bit for line 7 */
10232 #define EXTI_PR_PR8_Pos           (8U)
10233 #define EXTI_PR_PR8_Msk           (0x1UL << EXTI_PR_PR8_Pos)                    /*!< 0x00000100 */
10234 #define EXTI_PR_PR8               EXTI_PR_PR8_Msk                              /*!< Pending bit for line 8 */
10235 #define EXTI_PR_PR9_Pos           (9U)
10236 #define EXTI_PR_PR9_Msk           (0x1UL << EXTI_PR_PR9_Pos)                    /*!< 0x00000200 */
10237 #define EXTI_PR_PR9               EXTI_PR_PR9_Msk                              /*!< Pending bit for line 9 */
10238 #define EXTI_PR_PR10_Pos          (10U)
10239 #define EXTI_PR_PR10_Msk          (0x1UL << EXTI_PR_PR10_Pos)                   /*!< 0x00000400 */
10240 #define EXTI_PR_PR10              EXTI_PR_PR10_Msk                             /*!< Pending bit for line 10 */
10241 #define EXTI_PR_PR11_Pos          (11U)
10242 #define EXTI_PR_PR11_Msk          (0x1UL << EXTI_PR_PR11_Pos)                   /*!< 0x00000800 */
10243 #define EXTI_PR_PR11              EXTI_PR_PR11_Msk                             /*!< Pending bit for line 11 */
10244 #define EXTI_PR_PR12_Pos          (12U)
10245 #define EXTI_PR_PR12_Msk          (0x1UL << EXTI_PR_PR12_Pos)                   /*!< 0x00001000 */
10246 #define EXTI_PR_PR12              EXTI_PR_PR12_Msk                             /*!< Pending bit for line 12 */
10247 #define EXTI_PR_PR13_Pos          (13U)
10248 #define EXTI_PR_PR13_Msk          (0x1UL << EXTI_PR_PR13_Pos)                   /*!< 0x00002000 */
10249 #define EXTI_PR_PR13              EXTI_PR_PR13_Msk                             /*!< Pending bit for line 13 */
10250 #define EXTI_PR_PR14_Pos          (14U)
10251 #define EXTI_PR_PR14_Msk          (0x1UL << EXTI_PR_PR14_Pos)                   /*!< 0x00004000 */
10252 #define EXTI_PR_PR14              EXTI_PR_PR14_Msk                             /*!< Pending bit for line 14 */
10253 #define EXTI_PR_PR15_Pos          (15U)
10254 #define EXTI_PR_PR15_Msk          (0x1UL << EXTI_PR_PR15_Pos)                   /*!< 0x00008000 */
10255 #define EXTI_PR_PR15              EXTI_PR_PR15_Msk                             /*!< Pending bit for line 15 */
10256 #define EXTI_PR_PR16_Pos          (16U)
10257 #define EXTI_PR_PR16_Msk          (0x1UL << EXTI_PR_PR16_Pos)                   /*!< 0x00010000 */
10258 #define EXTI_PR_PR16              EXTI_PR_PR16_Msk                             /*!< Pending bit for line 16 */
10259 #define EXTI_PR_PR17_Pos          (17U)
10260 #define EXTI_PR_PR17_Msk          (0x1UL << EXTI_PR_PR17_Pos)                   /*!< 0x00020000 */
10261 #define EXTI_PR_PR17              EXTI_PR_PR17_Msk                             /*!< Pending bit for line 17 */
10262 #define EXTI_PR_PR18_Pos          (18U)
10263 #define EXTI_PR_PR18_Msk          (0x1UL << EXTI_PR_PR18_Pos)                   /*!< 0x00040000 */
10264 #define EXTI_PR_PR18              EXTI_PR_PR18_Msk                             /*!< Pending bit for line 18 */
10265 #define EXTI_PR_PR19_Pos          (19U)
10266 #define EXTI_PR_PR19_Msk          (0x1UL << EXTI_PR_PR19_Pos)                   /*!< 0x00080000 */
10267 #define EXTI_PR_PR19              EXTI_PR_PR19_Msk                             /*!< Pending bit for line 19 */
10268 #define EXTI_PR_PR20_Pos          (20U)
10269 #define EXTI_PR_PR20_Msk          (0x1UL << EXTI_PR_PR20_Pos)                   /*!< 0x00100000 */
10270 #define EXTI_PR_PR20              EXTI_PR_PR20_Msk                             /*!< Pending bit for line 20 */
10271 #define EXTI_PR_PR21_Pos          (21U)
10272 #define EXTI_PR_PR21_Msk          (0x1UL << EXTI_PR_PR21_Pos)                   /*!< 0x00200000 */
10273 #define EXTI_PR_PR21              EXTI_PR_PR21_Msk                             /*!< Pending bit for line 21 */
10274 #define EXTI_PR_PR22_Pos          (22U)
10275 #define EXTI_PR_PR22_Msk          (0x1UL << EXTI_PR_PR22_Pos)                   /*!< 0x00400000 */
10276 #define EXTI_PR_PR22              EXTI_PR_PR22_Msk                             /*!< Pending bit for line 22 */
10277 
10278 /******************************************************************************/
10279 /*                                                                            */
10280 /*                                    FLASH                                   */
10281 /*                                                                            */
10282 /******************************************************************************/
10283 /*******************  Bits definition for FLASH_ACR register  *****************/
10284 #define FLASH_ACR_LATENCY_Pos          (0U)
10285 #define FLASH_ACR_LATENCY_Msk          (0xFUL << FLASH_ACR_LATENCY_Pos)         /*!< 0x0000000F */
10286 #define FLASH_ACR_LATENCY              FLASH_ACR_LATENCY_Msk
10287 #define FLASH_ACR_LATENCY_0WS          0x00000000U
10288 #define FLASH_ACR_LATENCY_1WS          0x00000001U
10289 #define FLASH_ACR_LATENCY_2WS          0x00000002U
10290 #define FLASH_ACR_LATENCY_3WS          0x00000003U
10291 #define FLASH_ACR_LATENCY_4WS          0x00000004U
10292 #define FLASH_ACR_LATENCY_5WS          0x00000005U
10293 #define FLASH_ACR_LATENCY_6WS          0x00000006U
10294 #define FLASH_ACR_LATENCY_7WS          0x00000007U
10295 
10296 #define FLASH_ACR_LATENCY_8WS          0x00000008U
10297 #define FLASH_ACR_LATENCY_9WS          0x00000009U
10298 #define FLASH_ACR_LATENCY_10WS         0x0000000AU
10299 #define FLASH_ACR_LATENCY_11WS         0x0000000BU
10300 #define FLASH_ACR_LATENCY_12WS         0x0000000CU
10301 #define FLASH_ACR_LATENCY_13WS         0x0000000DU
10302 #define FLASH_ACR_LATENCY_14WS         0x0000000EU
10303 #define FLASH_ACR_LATENCY_15WS         0x0000000FU
10304 #define FLASH_ACR_PRFTEN_Pos           (8U)
10305 #define FLASH_ACR_PRFTEN_Msk           (0x1UL << FLASH_ACR_PRFTEN_Pos)          /*!< 0x00000100 */
10306 #define FLASH_ACR_PRFTEN               FLASH_ACR_PRFTEN_Msk
10307 #define FLASH_ACR_ICEN_Pos             (9U)
10308 #define FLASH_ACR_ICEN_Msk             (0x1UL << FLASH_ACR_ICEN_Pos)            /*!< 0x00000200 */
10309 #define FLASH_ACR_ICEN                 FLASH_ACR_ICEN_Msk
10310 #define FLASH_ACR_DCEN_Pos             (10U)
10311 #define FLASH_ACR_DCEN_Msk             (0x1UL << FLASH_ACR_DCEN_Pos)            /*!< 0x00000400 */
10312 #define FLASH_ACR_DCEN                 FLASH_ACR_DCEN_Msk
10313 #define FLASH_ACR_ICRST_Pos            (11U)
10314 #define FLASH_ACR_ICRST_Msk            (0x1UL << FLASH_ACR_ICRST_Pos)           /*!< 0x00000800 */
10315 #define FLASH_ACR_ICRST                FLASH_ACR_ICRST_Msk
10316 #define FLASH_ACR_DCRST_Pos            (12U)
10317 #define FLASH_ACR_DCRST_Msk            (0x1UL << FLASH_ACR_DCRST_Pos)           /*!< 0x00001000 */
10318 #define FLASH_ACR_DCRST                FLASH_ACR_DCRST_Msk
10319 #define FLASH_ACR_BYTE0_ADDRESS_Pos    (10U)
10320 #define FLASH_ACR_BYTE0_ADDRESS_Msk    (0x10008FUL << FLASH_ACR_BYTE0_ADDRESS_Pos) /*!< 0x40023C00 */
10321 #define FLASH_ACR_BYTE0_ADDRESS        FLASH_ACR_BYTE0_ADDRESS_Msk
10322 #define FLASH_ACR_BYTE2_ADDRESS_Pos    (0U)
10323 #define FLASH_ACR_BYTE2_ADDRESS_Msk    (0x40023C03UL << FLASH_ACR_BYTE2_ADDRESS_Pos) /*!< 0x40023C03 */
10324 #define FLASH_ACR_BYTE2_ADDRESS        FLASH_ACR_BYTE2_ADDRESS_Msk
10325 
10326 /*******************  Bits definition for FLASH_SR register  ******************/
10327 #define FLASH_SR_EOP_Pos               (0U)
10328 #define FLASH_SR_EOP_Msk               (0x1UL << FLASH_SR_EOP_Pos)              /*!< 0x00000001 */
10329 #define FLASH_SR_EOP                   FLASH_SR_EOP_Msk
10330 #define FLASH_SR_SOP_Pos               (1U)
10331 #define FLASH_SR_SOP_Msk               (0x1UL << FLASH_SR_SOP_Pos)              /*!< 0x00000002 */
10332 #define FLASH_SR_SOP                   FLASH_SR_SOP_Msk
10333 #define FLASH_SR_WRPERR_Pos            (4U)
10334 #define FLASH_SR_WRPERR_Msk            (0x1UL << FLASH_SR_WRPERR_Pos)           /*!< 0x00000010 */
10335 #define FLASH_SR_WRPERR                FLASH_SR_WRPERR_Msk
10336 #define FLASH_SR_PGAERR_Pos            (5U)
10337 #define FLASH_SR_PGAERR_Msk            (0x1UL << FLASH_SR_PGAERR_Pos)           /*!< 0x00000020 */
10338 #define FLASH_SR_PGAERR                FLASH_SR_PGAERR_Msk
10339 #define FLASH_SR_PGPERR_Pos            (6U)
10340 #define FLASH_SR_PGPERR_Msk            (0x1UL << FLASH_SR_PGPERR_Pos)           /*!< 0x00000040 */
10341 #define FLASH_SR_PGPERR                FLASH_SR_PGPERR_Msk
10342 #define FLASH_SR_PGSERR_Pos            (7U)
10343 #define FLASH_SR_PGSERR_Msk            (0x1UL << FLASH_SR_PGSERR_Pos)           /*!< 0x00000080 */
10344 #define FLASH_SR_PGSERR                FLASH_SR_PGSERR_Msk
10345 #define FLASH_SR_RDERR_Pos            (8U)
10346 #define FLASH_SR_RDERR_Msk            (0x1UL << FLASH_SR_RDERR_Pos)             /*!< 0x00000100 */
10347 #define FLASH_SR_RDERR                FLASH_SR_RDERR_Msk
10348 #define FLASH_SR_BSY_Pos               (16U)
10349 #define FLASH_SR_BSY_Msk               (0x1UL << FLASH_SR_BSY_Pos)              /*!< 0x00010000 */
10350 #define FLASH_SR_BSY                   FLASH_SR_BSY_Msk
10351 
10352 /*******************  Bits definition for FLASH_CR register  ******************/
10353 #define FLASH_CR_PG_Pos                (0U)
10354 #define FLASH_CR_PG_Msk                (0x1UL << FLASH_CR_PG_Pos)               /*!< 0x00000001 */
10355 #define FLASH_CR_PG                    FLASH_CR_PG_Msk
10356 #define FLASH_CR_SER_Pos               (1U)
10357 #define FLASH_CR_SER_Msk               (0x1UL << FLASH_CR_SER_Pos)              /*!< 0x00000002 */
10358 #define FLASH_CR_SER                   FLASH_CR_SER_Msk
10359 #define FLASH_CR_MER_Pos               (2U)
10360 #define FLASH_CR_MER_Msk               (0x1UL << FLASH_CR_MER_Pos)              /*!< 0x00000004 */
10361 #define FLASH_CR_MER                   FLASH_CR_MER_Msk
10362 #define FLASH_CR_MER1                        FLASH_CR_MER
10363 #define FLASH_CR_SNB_Pos               (3U)
10364 #define FLASH_CR_SNB_Msk               (0x1FUL << FLASH_CR_SNB_Pos)             /*!< 0x000000F8 */
10365 #define FLASH_CR_SNB                   FLASH_CR_SNB_Msk
10366 #define FLASH_CR_SNB_0                 (0x01UL << FLASH_CR_SNB_Pos)             /*!< 0x00000008 */
10367 #define FLASH_CR_SNB_1                 (0x02UL << FLASH_CR_SNB_Pos)             /*!< 0x00000010 */
10368 #define FLASH_CR_SNB_2                 (0x04UL << FLASH_CR_SNB_Pos)             /*!< 0x00000020 */
10369 #define FLASH_CR_SNB_3                 (0x08UL << FLASH_CR_SNB_Pos)             /*!< 0x00000040 */
10370 #define FLASH_CR_SNB_4                 (0x10UL << FLASH_CR_SNB_Pos)             /*!< 0x00000080 */
10371 #define FLASH_CR_PSIZE_Pos             (8U)
10372 #define FLASH_CR_PSIZE_Msk             (0x3UL << FLASH_CR_PSIZE_Pos)            /*!< 0x00000300 */
10373 #define FLASH_CR_PSIZE                 FLASH_CR_PSIZE_Msk
10374 #define FLASH_CR_PSIZE_0               (0x1UL << FLASH_CR_PSIZE_Pos)            /*!< 0x00000100 */
10375 #define FLASH_CR_PSIZE_1               (0x2UL << FLASH_CR_PSIZE_Pos)            /*!< 0x00000200 */
10376 #define FLASH_CR_MER2_Pos              (15U)
10377 #define FLASH_CR_MER2_Msk              (0x1UL << FLASH_CR_MER2_Pos)             /*!< 0x00008000 */
10378 #define FLASH_CR_MER2                  FLASH_CR_MER2_Msk
10379 #define FLASH_CR_STRT_Pos              (16U)
10380 #define FLASH_CR_STRT_Msk              (0x1UL << FLASH_CR_STRT_Pos)             /*!< 0x00010000 */
10381 #define FLASH_CR_STRT                  FLASH_CR_STRT_Msk
10382 #define FLASH_CR_EOPIE_Pos             (24U)
10383 #define FLASH_CR_EOPIE_Msk             (0x1UL << FLASH_CR_EOPIE_Pos)            /*!< 0x01000000 */
10384 #define FLASH_CR_EOPIE                 FLASH_CR_EOPIE_Msk
10385 #define FLASH_CR_LOCK_Pos              (31U)
10386 #define FLASH_CR_LOCK_Msk              (0x1UL << FLASH_CR_LOCK_Pos)             /*!< 0x80000000 */
10387 #define FLASH_CR_LOCK                  FLASH_CR_LOCK_Msk
10388 
10389 /*******************  Bits definition for FLASH_OPTCR register  ***************/
10390 #define FLASH_OPTCR_OPTLOCK_Pos        (0U)
10391 #define FLASH_OPTCR_OPTLOCK_Msk        (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)       /*!< 0x00000001 */
10392 #define FLASH_OPTCR_OPTLOCK            FLASH_OPTCR_OPTLOCK_Msk
10393 #define FLASH_OPTCR_OPTSTRT_Pos        (1U)
10394 #define FLASH_OPTCR_OPTSTRT_Msk        (0x1UL << FLASH_OPTCR_OPTSTRT_Pos)       /*!< 0x00000002 */
10395 #define FLASH_OPTCR_OPTSTRT            FLASH_OPTCR_OPTSTRT_Msk
10396 
10397 #define FLASH_OPTCR_BOR_LEV_0          0x00000004U
10398 #define FLASH_OPTCR_BOR_LEV_1          0x00000008U
10399 #define FLASH_OPTCR_BOR_LEV_Pos        (2U)
10400 #define FLASH_OPTCR_BOR_LEV_Msk        (0x3UL << FLASH_OPTCR_BOR_LEV_Pos)       /*!< 0x0000000C */
10401 #define FLASH_OPTCR_BOR_LEV            FLASH_OPTCR_BOR_LEV_Msk
10402 #define FLASH_OPTCR_BFB2_Pos           (4U)
10403 #define FLASH_OPTCR_BFB2_Msk           (0x1UL << FLASH_OPTCR_BFB2_Pos)          /*!< 0x00000010 */
10404 #define FLASH_OPTCR_BFB2               FLASH_OPTCR_BFB2_Msk
10405 #define FLASH_OPTCR_WDG_SW_Pos         (5U)
10406 #define FLASH_OPTCR_WDG_SW_Msk         (0x1UL << FLASH_OPTCR_WDG_SW_Pos)        /*!< 0x00000020 */
10407 #define FLASH_OPTCR_WDG_SW             FLASH_OPTCR_WDG_SW_Msk
10408 #define FLASH_OPTCR_nRST_STOP_Pos      (6U)
10409 #define FLASH_OPTCR_nRST_STOP_Msk      (0x1UL << FLASH_OPTCR_nRST_STOP_Pos)     /*!< 0x00000040 */
10410 #define FLASH_OPTCR_nRST_STOP          FLASH_OPTCR_nRST_STOP_Msk
10411 #define FLASH_OPTCR_nRST_STDBY_Pos     (7U)
10412 #define FLASH_OPTCR_nRST_STDBY_Msk     (0x1UL << FLASH_OPTCR_nRST_STDBY_Pos)    /*!< 0x00000080 */
10413 #define FLASH_OPTCR_nRST_STDBY         FLASH_OPTCR_nRST_STDBY_Msk
10414 #define FLASH_OPTCR_RDP_Pos            (8U)
10415 #define FLASH_OPTCR_RDP_Msk            (0xFFUL << FLASH_OPTCR_RDP_Pos)          /*!< 0x0000FF00 */
10416 #define FLASH_OPTCR_RDP                FLASH_OPTCR_RDP_Msk
10417 #define FLASH_OPTCR_RDP_0              (0x01UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000100 */
10418 #define FLASH_OPTCR_RDP_1              (0x02UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000200 */
10419 #define FLASH_OPTCR_RDP_2              (0x04UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000400 */
10420 #define FLASH_OPTCR_RDP_3              (0x08UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000800 */
10421 #define FLASH_OPTCR_RDP_4              (0x10UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00001000 */
10422 #define FLASH_OPTCR_RDP_5              (0x20UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00002000 */
10423 #define FLASH_OPTCR_RDP_6              (0x40UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00004000 */
10424 #define FLASH_OPTCR_RDP_7              (0x80UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00008000 */
10425 #define FLASH_OPTCR_nWRP_Pos           (16U)
10426 #define FLASH_OPTCR_nWRP_Msk           (0xFFFUL << FLASH_OPTCR_nWRP_Pos)        /*!< 0x0FFF0000 */
10427 #define FLASH_OPTCR_nWRP               FLASH_OPTCR_nWRP_Msk
10428 #define FLASH_OPTCR_nWRP_0             0x00010000U
10429 #define FLASH_OPTCR_nWRP_1             0x00020000U
10430 #define FLASH_OPTCR_nWRP_2             0x00040000U
10431 #define FLASH_OPTCR_nWRP_3             0x00080000U
10432 #define FLASH_OPTCR_nWRP_4             0x00100000U
10433 #define FLASH_OPTCR_nWRP_5             0x00200000U
10434 #define FLASH_OPTCR_nWRP_6             0x00400000U
10435 #define FLASH_OPTCR_nWRP_7             0x00800000U
10436 #define FLASH_OPTCR_nWRP_8             0x01000000U
10437 #define FLASH_OPTCR_nWRP_9             0x02000000U
10438 #define FLASH_OPTCR_nWRP_10            0x04000000U
10439 #define FLASH_OPTCR_nWRP_11            0x08000000U
10440 #define FLASH_OPTCR_DB1M_Pos           (30U)
10441 #define FLASH_OPTCR_DB1M_Msk           (0x1UL << FLASH_OPTCR_DB1M_Pos)          /*!< 0x40000000 */
10442 #define FLASH_OPTCR_DB1M               FLASH_OPTCR_DB1M_Msk
10443 #define FLASH_OPTCR_SPRMOD_Pos         (31U)
10444 #define FLASH_OPTCR_SPRMOD_Msk         (0x1UL << FLASH_OPTCR_SPRMOD_Pos)        /*!< 0x80000000 */
10445 #define FLASH_OPTCR_SPRMOD             FLASH_OPTCR_SPRMOD_Msk
10446 
10447 /******************  Bits definition for FLASH_OPTCR1 register  ***************/
10448 #define FLASH_OPTCR1_nWRP_Pos          (16U)
10449 #define FLASH_OPTCR1_nWRP_Msk          (0xFFFUL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x0FFF0000 */
10450 #define FLASH_OPTCR1_nWRP              FLASH_OPTCR1_nWRP_Msk
10451 #define FLASH_OPTCR1_nWRP_0            (0x001UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00010000 */
10452 #define FLASH_OPTCR1_nWRP_1            (0x002UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00020000 */
10453 #define FLASH_OPTCR1_nWRP_2            (0x004UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00040000 */
10454 #define FLASH_OPTCR1_nWRP_3            (0x008UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00080000 */
10455 #define FLASH_OPTCR1_nWRP_4            (0x010UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00100000 */
10456 #define FLASH_OPTCR1_nWRP_5            (0x020UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00200000 */
10457 #define FLASH_OPTCR1_nWRP_6            (0x040UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00400000 */
10458 #define FLASH_OPTCR1_nWRP_7            (0x080UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00800000 */
10459 #define FLASH_OPTCR1_nWRP_8            (0x100UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x01000000 */
10460 #define FLASH_OPTCR1_nWRP_9            (0x200UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x02000000 */
10461 #define FLASH_OPTCR1_nWRP_10           (0x400UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x04000000 */
10462 #define FLASH_OPTCR1_nWRP_11           (0x800UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x08000000 */
10463 
10464 /******************************************************************************/
10465 /*                                                                            */
10466 /*                          Flexible Memory Controller                        */
10467 /*                                                                            */
10468 /******************************************************************************/
10469 /******************  Bit definition for FMC_BCR1 register  *******************/
10470 #define FMC_BCR1_MBKEN_Pos          (0U)
10471 #define FMC_BCR1_MBKEN_Msk          (0x1UL << FMC_BCR1_MBKEN_Pos)               /*!< 0x00000001 */
10472 #define FMC_BCR1_MBKEN              FMC_BCR1_MBKEN_Msk                         /*!<Memory bank enable bit                 */
10473 #define FMC_BCR1_MUXEN_Pos          (1U)
10474 #define FMC_BCR1_MUXEN_Msk          (0x1UL << FMC_BCR1_MUXEN_Pos)               /*!< 0x00000002 */
10475 #define FMC_BCR1_MUXEN              FMC_BCR1_MUXEN_Msk                         /*!<Address/data multiplexing enable bit   */
10476 
10477 #define FMC_BCR1_MTYP_Pos           (2U)
10478 #define FMC_BCR1_MTYP_Msk           (0x3UL << FMC_BCR1_MTYP_Pos)                /*!< 0x0000000C */
10479 #define FMC_BCR1_MTYP               FMC_BCR1_MTYP_Msk                          /*!<MTYP[1:0] bits (Memory type)           */
10480 #define FMC_BCR1_MTYP_0             (0x1UL << FMC_BCR1_MTYP_Pos)                /*!< 0x00000004 */
10481 #define FMC_BCR1_MTYP_1             (0x2UL << FMC_BCR1_MTYP_Pos)                /*!< 0x00000008 */
10482 
10483 #define FMC_BCR1_MWID_Pos           (4U)
10484 #define FMC_BCR1_MWID_Msk           (0x3UL << FMC_BCR1_MWID_Pos)                /*!< 0x00000030 */
10485 #define FMC_BCR1_MWID               FMC_BCR1_MWID_Msk                          /*!<MWID[1:0] bits (Memory data bus width) */
10486 #define FMC_BCR1_MWID_0             (0x1UL << FMC_BCR1_MWID_Pos)                /*!< 0x00000010 */
10487 #define FMC_BCR1_MWID_1             (0x2UL << FMC_BCR1_MWID_Pos)                /*!< 0x00000020 */
10488 
10489 #define FMC_BCR1_FACCEN_Pos         (6U)
10490 #define FMC_BCR1_FACCEN_Msk         (0x1UL << FMC_BCR1_FACCEN_Pos)              /*!< 0x00000040 */
10491 #define FMC_BCR1_FACCEN             FMC_BCR1_FACCEN_Msk                        /*!<Flash access enable        */
10492 #define FMC_BCR1_BURSTEN_Pos        (8U)
10493 #define FMC_BCR1_BURSTEN_Msk        (0x1UL << FMC_BCR1_BURSTEN_Pos)             /*!< 0x00000100 */
10494 #define FMC_BCR1_BURSTEN            FMC_BCR1_BURSTEN_Msk                       /*!<Burst enable bit           */
10495 #define FMC_BCR1_WAITPOL_Pos        (9U)
10496 #define FMC_BCR1_WAITPOL_Msk        (0x1UL << FMC_BCR1_WAITPOL_Pos)             /*!< 0x00000200 */
10497 #define FMC_BCR1_WAITPOL            FMC_BCR1_WAITPOL_Msk                       /*!<Wait signal polarity bit   */
10498 #define FMC_BCR1_WAITCFG_Pos        (11U)
10499 #define FMC_BCR1_WAITCFG_Msk        (0x1UL << FMC_BCR1_WAITCFG_Pos)             /*!< 0x00000800 */
10500 #define FMC_BCR1_WAITCFG            FMC_BCR1_WAITCFG_Msk                       /*!<Wait timing configuration  */
10501 #define FMC_BCR1_WREN_Pos           (12U)
10502 #define FMC_BCR1_WREN_Msk           (0x1UL << FMC_BCR1_WREN_Pos)                /*!< 0x00001000 */
10503 #define FMC_BCR1_WREN               FMC_BCR1_WREN_Msk                          /*!<Write enable bit           */
10504 #define FMC_BCR1_WAITEN_Pos         (13U)
10505 #define FMC_BCR1_WAITEN_Msk         (0x1UL << FMC_BCR1_WAITEN_Pos)              /*!< 0x00002000 */
10506 #define FMC_BCR1_WAITEN             FMC_BCR1_WAITEN_Msk                        /*!<Wait enable bit            */
10507 #define FMC_BCR1_EXTMOD_Pos         (14U)
10508 #define FMC_BCR1_EXTMOD_Msk         (0x1UL << FMC_BCR1_EXTMOD_Pos)              /*!< 0x00004000 */
10509 #define FMC_BCR1_EXTMOD             FMC_BCR1_EXTMOD_Msk                        /*!<Extended mode enable       */
10510 #define FMC_BCR1_ASYNCWAIT_Pos      (15U)
10511 #define FMC_BCR1_ASYNCWAIT_Msk      (0x1UL << FMC_BCR1_ASYNCWAIT_Pos)           /*!< 0x00008000 */
10512 #define FMC_BCR1_ASYNCWAIT          FMC_BCR1_ASYNCWAIT_Msk                     /*!<Asynchronous wait          */
10513 #define FMC_BCR1_CPSIZE_Pos         (16U)
10514 #define FMC_BCR1_CPSIZE_Msk         (0x7UL << FMC_BCR1_CPSIZE_Pos)              /*!< 0x00070000 */
10515 #define FMC_BCR1_CPSIZE             FMC_BCR1_CPSIZE_Msk                        /*!<CRAM page size             */
10516 #define FMC_BCR1_CPSIZE_0           (0x1UL << FMC_BCR1_CPSIZE_Pos)              /*!< 0x00010000 */
10517 #define FMC_BCR1_CPSIZE_1           (0x2UL << FMC_BCR1_CPSIZE_Pos)              /*!< 0x00020000 */
10518 #define FMC_BCR1_CPSIZE_2           (0x4UL << FMC_BCR1_CPSIZE_Pos)              /*!< 0x00040000 */
10519 #define FMC_BCR1_CBURSTRW_Pos       (19U)
10520 #define FMC_BCR1_CBURSTRW_Msk       (0x1UL << FMC_BCR1_CBURSTRW_Pos)            /*!< 0x00080000 */
10521 #define FMC_BCR1_CBURSTRW           FMC_BCR1_CBURSTRW_Msk                      /*!<Write burst enable         */
10522 #define FMC_BCR1_CCLKEN_Pos         (20U)
10523 #define FMC_BCR1_CCLKEN_Msk         (0x1UL << FMC_BCR1_CCLKEN_Pos)              /*!< 0x00100000 */
10524 #define FMC_BCR1_CCLKEN             FMC_BCR1_CCLKEN_Msk                        /*!<Continous clock enable     */
10525 #define FMC_BCR1_WFDIS_Pos          (21U)
10526 #define FMC_BCR1_WFDIS_Msk          (0x1UL << FMC_BCR1_WFDIS_Pos)               /*!< 0x00200000 */
10527 #define FMC_BCR1_WFDIS              FMC_BCR1_WFDIS_Msk                         /*!<Write FIFO Disable         */
10528 
10529 /******************  Bit definition for FMC_BCR2 register  *******************/
10530 #define FMC_BCR2_MBKEN_Pos          (0U)
10531 #define FMC_BCR2_MBKEN_Msk          (0x1UL << FMC_BCR2_MBKEN_Pos)               /*!< 0x00000001 */
10532 #define FMC_BCR2_MBKEN              FMC_BCR2_MBKEN_Msk                         /*!<Memory bank enable bit                 */
10533 #define FMC_BCR2_MUXEN_Pos          (1U)
10534 #define FMC_BCR2_MUXEN_Msk          (0x1UL << FMC_BCR2_MUXEN_Pos)               /*!< 0x00000002 */
10535 #define FMC_BCR2_MUXEN              FMC_BCR2_MUXEN_Msk                         /*!<Address/data multiplexing enable bit   */
10536 
10537 #define FMC_BCR2_MTYP_Pos           (2U)
10538 #define FMC_BCR2_MTYP_Msk           (0x3UL << FMC_BCR2_MTYP_Pos)                /*!< 0x0000000C */
10539 #define FMC_BCR2_MTYP               FMC_BCR2_MTYP_Msk                          /*!<MTYP[1:0] bits (Memory type)           */
10540 #define FMC_BCR2_MTYP_0             (0x1UL << FMC_BCR2_MTYP_Pos)                /*!< 0x00000004 */
10541 #define FMC_BCR2_MTYP_1             (0x2UL << FMC_BCR2_MTYP_Pos)                /*!< 0x00000008 */
10542 
10543 #define FMC_BCR2_MWID_Pos           (4U)
10544 #define FMC_BCR2_MWID_Msk           (0x3UL << FMC_BCR2_MWID_Pos)                /*!< 0x00000030 */
10545 #define FMC_BCR2_MWID               FMC_BCR2_MWID_Msk                          /*!<MWID[1:0] bits (Memory data bus width) */
10546 #define FMC_BCR2_MWID_0             (0x1UL << FMC_BCR2_MWID_Pos)                /*!< 0x00000010 */
10547 #define FMC_BCR2_MWID_1             (0x2UL << FMC_BCR2_MWID_Pos)                /*!< 0x00000020 */
10548 
10549 #define FMC_BCR2_FACCEN_Pos         (6U)
10550 #define FMC_BCR2_FACCEN_Msk         (0x1UL << FMC_BCR2_FACCEN_Pos)              /*!< 0x00000040 */
10551 #define FMC_BCR2_FACCEN             FMC_BCR2_FACCEN_Msk                        /*!<Flash access enable        */
10552 #define FMC_BCR2_BURSTEN_Pos        (8U)
10553 #define FMC_BCR2_BURSTEN_Msk        (0x1UL << FMC_BCR2_BURSTEN_Pos)             /*!< 0x00000100 */
10554 #define FMC_BCR2_BURSTEN            FMC_BCR2_BURSTEN_Msk                       /*!<Burst enable bit           */
10555 #define FMC_BCR2_WAITPOL_Pos        (9U)
10556 #define FMC_BCR2_WAITPOL_Msk        (0x1UL << FMC_BCR2_WAITPOL_Pos)             /*!< 0x00000200 */
10557 #define FMC_BCR2_WAITPOL            FMC_BCR2_WAITPOL_Msk                       /*!<Wait signal polarity bit   */
10558 #define FMC_BCR2_WAITCFG_Pos        (11U)
10559 #define FMC_BCR2_WAITCFG_Msk        (0x1UL << FMC_BCR2_WAITCFG_Pos)             /*!< 0x00000800 */
10560 #define FMC_BCR2_WAITCFG            FMC_BCR2_WAITCFG_Msk                       /*!<Wait timing configuration  */
10561 #define FMC_BCR2_WREN_Pos           (12U)
10562 #define FMC_BCR2_WREN_Msk           (0x1UL << FMC_BCR2_WREN_Pos)                /*!< 0x00001000 */
10563 #define FMC_BCR2_WREN               FMC_BCR2_WREN_Msk                          /*!<Write enable bit           */
10564 #define FMC_BCR2_WAITEN_Pos         (13U)
10565 #define FMC_BCR2_WAITEN_Msk         (0x1UL << FMC_BCR2_WAITEN_Pos)              /*!< 0x00002000 */
10566 #define FMC_BCR2_WAITEN             FMC_BCR2_WAITEN_Msk                        /*!<Wait enable bit            */
10567 #define FMC_BCR2_EXTMOD_Pos         (14U)
10568 #define FMC_BCR2_EXTMOD_Msk         (0x1UL << FMC_BCR2_EXTMOD_Pos)              /*!< 0x00004000 */
10569 #define FMC_BCR2_EXTMOD             FMC_BCR2_EXTMOD_Msk                        /*!<Extended mode enable       */
10570 #define FMC_BCR2_ASYNCWAIT_Pos      (15U)
10571 #define FMC_BCR2_ASYNCWAIT_Msk      (0x1UL << FMC_BCR2_ASYNCWAIT_Pos)           /*!< 0x00008000 */
10572 #define FMC_BCR2_ASYNCWAIT          FMC_BCR2_ASYNCWAIT_Msk                     /*!<Asynchronous wait          */
10573 #define FMC_BCR2_CBURSTRW_Pos       (19U)
10574 #define FMC_BCR2_CBURSTRW_Msk       (0x1UL << FMC_BCR2_CBURSTRW_Pos)            /*!< 0x00080000 */
10575 #define FMC_BCR2_CBURSTRW           FMC_BCR2_CBURSTRW_Msk                      /*!<Write burst enable         */
10576 
10577 /******************  Bit definition for FMC_BCR3 register  *******************/
10578 #define FMC_BCR3_MBKEN_Pos          (0U)
10579 #define FMC_BCR3_MBKEN_Msk          (0x1UL << FMC_BCR3_MBKEN_Pos)               /*!< 0x00000001 */
10580 #define FMC_BCR3_MBKEN              FMC_BCR3_MBKEN_Msk                         /*!<Memory bank enable bit                 */
10581 #define FMC_BCR3_MUXEN_Pos          (1U)
10582 #define FMC_BCR3_MUXEN_Msk          (0x1UL << FMC_BCR3_MUXEN_Pos)               /*!< 0x00000002 */
10583 #define FMC_BCR3_MUXEN              FMC_BCR3_MUXEN_Msk                         /*!<Address/data multiplexing enable bit   */
10584 
10585 #define FMC_BCR3_MTYP_Pos           (2U)
10586 #define FMC_BCR3_MTYP_Msk           (0x3UL << FMC_BCR3_MTYP_Pos)                /*!< 0x0000000C */
10587 #define FMC_BCR3_MTYP               FMC_BCR3_MTYP_Msk                          /*!<MTYP[1:0] bits (Memory type)           */
10588 #define FMC_BCR3_MTYP_0             (0x1UL << FMC_BCR3_MTYP_Pos)                /*!< 0x00000004 */
10589 #define FMC_BCR3_MTYP_1             (0x2UL << FMC_BCR3_MTYP_Pos)                /*!< 0x00000008 */
10590 
10591 #define FMC_BCR3_MWID_Pos           (4U)
10592 #define FMC_BCR3_MWID_Msk           (0x3UL << FMC_BCR3_MWID_Pos)                /*!< 0x00000030 */
10593 #define FMC_BCR3_MWID               FMC_BCR3_MWID_Msk                          /*!<MWID[1:0] bits (Memory data bus width) */
10594 #define FMC_BCR3_MWID_0             (0x1UL << FMC_BCR3_MWID_Pos)                /*!< 0x00000010 */
10595 #define FMC_BCR3_MWID_1             (0x2UL << FMC_BCR3_MWID_Pos)                /*!< 0x00000020 */
10596 
10597 #define FMC_BCR3_FACCEN_Pos         (6U)
10598 #define FMC_BCR3_FACCEN_Msk         (0x1UL << FMC_BCR3_FACCEN_Pos)              /*!< 0x00000040 */
10599 #define FMC_BCR3_FACCEN             FMC_BCR3_FACCEN_Msk                        /*!<Flash access enable        */
10600 #define FMC_BCR3_BURSTEN_Pos        (8U)
10601 #define FMC_BCR3_BURSTEN_Msk        (0x1UL << FMC_BCR3_BURSTEN_Pos)             /*!< 0x00000100 */
10602 #define FMC_BCR3_BURSTEN            FMC_BCR3_BURSTEN_Msk                       /*!<Burst enable bit           */
10603 #define FMC_BCR3_WAITPOL_Pos        (9U)
10604 #define FMC_BCR3_WAITPOL_Msk        (0x1UL << FMC_BCR3_WAITPOL_Pos)             /*!< 0x00000200 */
10605 #define FMC_BCR3_WAITPOL            FMC_BCR3_WAITPOL_Msk                       /*!<Wait signal polarity bit   */
10606 #define FMC_BCR3_WAITCFG_Pos        (11U)
10607 #define FMC_BCR3_WAITCFG_Msk        (0x1UL << FMC_BCR3_WAITCFG_Pos)             /*!< 0x00000800 */
10608 #define FMC_BCR3_WAITCFG            FMC_BCR3_WAITCFG_Msk                       /*!<Wait timing configuration  */
10609 #define FMC_BCR3_WREN_Pos           (12U)
10610 #define FMC_BCR3_WREN_Msk           (0x1UL << FMC_BCR3_WREN_Pos)                /*!< 0x00001000 */
10611 #define FMC_BCR3_WREN               FMC_BCR3_WREN_Msk                          /*!<Write enable bit           */
10612 #define FMC_BCR3_WAITEN_Pos         (13U)
10613 #define FMC_BCR3_WAITEN_Msk         (0x1UL << FMC_BCR3_WAITEN_Pos)              /*!< 0x00002000 */
10614 #define FMC_BCR3_WAITEN             FMC_BCR3_WAITEN_Msk                        /*!<Wait enable bit            */
10615 #define FMC_BCR3_EXTMOD_Pos         (14U)
10616 #define FMC_BCR3_EXTMOD_Msk         (0x1UL << FMC_BCR3_EXTMOD_Pos)              /*!< 0x00004000 */
10617 #define FMC_BCR3_EXTMOD             FMC_BCR3_EXTMOD_Msk                        /*!<Extended mode enable       */
10618 #define FMC_BCR3_ASYNCWAIT_Pos      (15U)
10619 #define FMC_BCR3_ASYNCWAIT_Msk      (0x1UL << FMC_BCR3_ASYNCWAIT_Pos)           /*!< 0x00008000 */
10620 #define FMC_BCR3_ASYNCWAIT          FMC_BCR3_ASYNCWAIT_Msk                     /*!<Asynchronous wait          */
10621 #define FMC_BCR3_CBURSTRW_Pos       (19U)
10622 #define FMC_BCR3_CBURSTRW_Msk       (0x1UL << FMC_BCR3_CBURSTRW_Pos)            /*!< 0x00080000 */
10623 #define FMC_BCR3_CBURSTRW           FMC_BCR3_CBURSTRW_Msk                      /*!<Write burst enable         */
10624 
10625 /******************  Bit definition for FMC_BCR4 register  *******************/
10626 #define FMC_BCR4_MBKEN_Pos          (0U)
10627 #define FMC_BCR4_MBKEN_Msk          (0x1UL << FMC_BCR4_MBKEN_Pos)               /*!< 0x00000001 */
10628 #define FMC_BCR4_MBKEN              FMC_BCR4_MBKEN_Msk                         /*!<Memory bank enable bit                 */
10629 #define FMC_BCR4_MUXEN_Pos          (1U)
10630 #define FMC_BCR4_MUXEN_Msk          (0x1UL << FMC_BCR4_MUXEN_Pos)               /*!< 0x00000002 */
10631 #define FMC_BCR4_MUXEN              FMC_BCR4_MUXEN_Msk                         /*!<Address/data multiplexing enable bit   */
10632 
10633 #define FMC_BCR4_MTYP_Pos           (2U)
10634 #define FMC_BCR4_MTYP_Msk           (0x3UL << FMC_BCR4_MTYP_Pos)                /*!< 0x0000000C */
10635 #define FMC_BCR4_MTYP               FMC_BCR4_MTYP_Msk                          /*!<MTYP[1:0] bits (Memory type)           */
10636 #define FMC_BCR4_MTYP_0             (0x1UL << FMC_BCR4_MTYP_Pos)                /*!< 0x00000004 */
10637 #define FMC_BCR4_MTYP_1             (0x2UL << FMC_BCR4_MTYP_Pos)                /*!< 0x00000008 */
10638 
10639 #define FMC_BCR4_MWID_Pos           (4U)
10640 #define FMC_BCR4_MWID_Msk           (0x3UL << FMC_BCR4_MWID_Pos)                /*!< 0x00000030 */
10641 #define FMC_BCR4_MWID               FMC_BCR4_MWID_Msk                          /*!<MWID[1:0] bits (Memory data bus width) */
10642 #define FMC_BCR4_MWID_0             (0x1UL << FMC_BCR4_MWID_Pos)                /*!< 0x00000010 */
10643 #define FMC_BCR4_MWID_1             (0x2UL << FMC_BCR4_MWID_Pos)                /*!< 0x00000020 */
10644 
10645 #define FMC_BCR4_FACCEN_Pos         (6U)
10646 #define FMC_BCR4_FACCEN_Msk         (0x1UL << FMC_BCR4_FACCEN_Pos)              /*!< 0x00000040 */
10647 #define FMC_BCR4_FACCEN             FMC_BCR4_FACCEN_Msk                        /*!<Flash access enable        */
10648 #define FMC_BCR4_BURSTEN_Pos        (8U)
10649 #define FMC_BCR4_BURSTEN_Msk        (0x1UL << FMC_BCR4_BURSTEN_Pos)             /*!< 0x00000100 */
10650 #define FMC_BCR4_BURSTEN            FMC_BCR4_BURSTEN_Msk                       /*!<Burst enable bit           */
10651 #define FMC_BCR4_WAITPOL_Pos        (9U)
10652 #define FMC_BCR4_WAITPOL_Msk        (0x1UL << FMC_BCR4_WAITPOL_Pos)             /*!< 0x00000200 */
10653 #define FMC_BCR4_WAITPOL            FMC_BCR4_WAITPOL_Msk                       /*!<Wait signal polarity bit   */
10654 #define FMC_BCR4_WAITCFG_Pos        (11U)
10655 #define FMC_BCR4_WAITCFG_Msk        (0x1UL << FMC_BCR4_WAITCFG_Pos)             /*!< 0x00000800 */
10656 #define FMC_BCR4_WAITCFG            FMC_BCR4_WAITCFG_Msk                       /*!<Wait timing configuration  */
10657 #define FMC_BCR4_WREN_Pos           (12U)
10658 #define FMC_BCR4_WREN_Msk           (0x1UL << FMC_BCR4_WREN_Pos)                /*!< 0x00001000 */
10659 #define FMC_BCR4_WREN               FMC_BCR4_WREN_Msk                          /*!<Write enable bit           */
10660 #define FMC_BCR4_WAITEN_Pos         (13U)
10661 #define FMC_BCR4_WAITEN_Msk         (0x1UL << FMC_BCR4_WAITEN_Pos)              /*!< 0x00002000 */
10662 #define FMC_BCR4_WAITEN             FMC_BCR4_WAITEN_Msk                        /*!<Wait enable bit            */
10663 #define FMC_BCR4_EXTMOD_Pos         (14U)
10664 #define FMC_BCR4_EXTMOD_Msk         (0x1UL << FMC_BCR4_EXTMOD_Pos)              /*!< 0x00004000 */
10665 #define FMC_BCR4_EXTMOD             FMC_BCR4_EXTMOD_Msk                        /*!<Extended mode enable       */
10666 #define FMC_BCR4_ASYNCWAIT_Pos      (15U)
10667 #define FMC_BCR4_ASYNCWAIT_Msk      (0x1UL << FMC_BCR4_ASYNCWAIT_Pos)           /*!< 0x00008000 */
10668 #define FMC_BCR4_ASYNCWAIT          FMC_BCR4_ASYNCWAIT_Msk                     /*!<Asynchronous wait          */
10669 #define FMC_BCR4_CBURSTRW_Pos       (19U)
10670 #define FMC_BCR4_CBURSTRW_Msk       (0x1UL << FMC_BCR4_CBURSTRW_Pos)            /*!< 0x00080000 */
10671 #define FMC_BCR4_CBURSTRW           FMC_BCR4_CBURSTRW_Msk                      /*!<Write burst enable         */
10672 
10673 /******************  Bit definition for FMC_BTR1 register  ******************/
10674 #define FMC_BTR1_ADDSET_Pos         (0U)
10675 #define FMC_BTR1_ADDSET_Msk         (0xFUL << FMC_BTR1_ADDSET_Pos)              /*!< 0x0000000F */
10676 #define FMC_BTR1_ADDSET             FMC_BTR1_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */
10677 #define FMC_BTR1_ADDSET_0           (0x1UL << FMC_BTR1_ADDSET_Pos)              /*!< 0x00000001 */
10678 #define FMC_BTR1_ADDSET_1           (0x2UL << FMC_BTR1_ADDSET_Pos)              /*!< 0x00000002 */
10679 #define FMC_BTR1_ADDSET_2           (0x4UL << FMC_BTR1_ADDSET_Pos)              /*!< 0x00000004 */
10680 #define FMC_BTR1_ADDSET_3           (0x8UL << FMC_BTR1_ADDSET_Pos)              /*!< 0x00000008 */
10681 
10682 #define FMC_BTR1_ADDHLD_Pos         (4U)
10683 #define FMC_BTR1_ADDHLD_Msk         (0xFUL << FMC_BTR1_ADDHLD_Pos)              /*!< 0x000000F0 */
10684 #define FMC_BTR1_ADDHLD             FMC_BTR1_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */
10685 #define FMC_BTR1_ADDHLD_0           (0x1UL << FMC_BTR1_ADDHLD_Pos)              /*!< 0x00000010 */
10686 #define FMC_BTR1_ADDHLD_1           (0x2UL << FMC_BTR1_ADDHLD_Pos)              /*!< 0x00000020 */
10687 #define FMC_BTR1_ADDHLD_2           (0x4UL << FMC_BTR1_ADDHLD_Pos)              /*!< 0x00000040 */
10688 #define FMC_BTR1_ADDHLD_3           (0x8UL << FMC_BTR1_ADDHLD_Pos)              /*!< 0x00000080 */
10689 
10690 #define FMC_BTR1_DATAST_Pos         (8U)
10691 #define FMC_BTR1_DATAST_Msk         (0xFFUL << FMC_BTR1_DATAST_Pos)             /*!< 0x0000FF00 */
10692 #define FMC_BTR1_DATAST             FMC_BTR1_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */
10693 #define FMC_BTR1_DATAST_0           (0x01UL << FMC_BTR1_DATAST_Pos)             /*!< 0x00000100 */
10694 #define FMC_BTR1_DATAST_1           (0x02UL << FMC_BTR1_DATAST_Pos)             /*!< 0x00000200 */
10695 #define FMC_BTR1_DATAST_2           (0x04UL << FMC_BTR1_DATAST_Pos)             /*!< 0x00000400 */
10696 #define FMC_BTR1_DATAST_3           (0x08UL << FMC_BTR1_DATAST_Pos)             /*!< 0x00000800 */
10697 #define FMC_BTR1_DATAST_4           (0x10UL << FMC_BTR1_DATAST_Pos)             /*!< 0x00001000 */
10698 #define FMC_BTR1_DATAST_5           (0x20UL << FMC_BTR1_DATAST_Pos)             /*!< 0x00002000 */
10699 #define FMC_BTR1_DATAST_6           (0x40UL << FMC_BTR1_DATAST_Pos)             /*!< 0x00004000 */
10700 #define FMC_BTR1_DATAST_7           (0x80UL << FMC_BTR1_DATAST_Pos)             /*!< 0x00008000 */
10701 
10702 #define FMC_BTR1_BUSTURN_Pos        (16U)
10703 #define FMC_BTR1_BUSTURN_Msk        (0xFUL << FMC_BTR1_BUSTURN_Pos)             /*!< 0x000F0000 */
10704 #define FMC_BTR1_BUSTURN            FMC_BTR1_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
10705 #define FMC_BTR1_BUSTURN_0          (0x1UL << FMC_BTR1_BUSTURN_Pos)             /*!< 0x00010000 */
10706 #define FMC_BTR1_BUSTURN_1          (0x2UL << FMC_BTR1_BUSTURN_Pos)             /*!< 0x00020000 */
10707 #define FMC_BTR1_BUSTURN_2          (0x4UL << FMC_BTR1_BUSTURN_Pos)             /*!< 0x00040000 */
10708 #define FMC_BTR1_BUSTURN_3          (0x8UL << FMC_BTR1_BUSTURN_Pos)             /*!< 0x00080000 */
10709 
10710 #define FMC_BTR1_CLKDIV_Pos         (20U)
10711 #define FMC_BTR1_CLKDIV_Msk         (0xFUL << FMC_BTR1_CLKDIV_Pos)              /*!< 0x00F00000 */
10712 #define FMC_BTR1_CLKDIV             FMC_BTR1_CLKDIV_Msk                        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
10713 #define FMC_BTR1_CLKDIV_0           (0x1UL << FMC_BTR1_CLKDIV_Pos)              /*!< 0x00100000 */
10714 #define FMC_BTR1_CLKDIV_1           (0x2UL << FMC_BTR1_CLKDIV_Pos)              /*!< 0x00200000 */
10715 #define FMC_BTR1_CLKDIV_2           (0x4UL << FMC_BTR1_CLKDIV_Pos)              /*!< 0x00400000 */
10716 #define FMC_BTR1_CLKDIV_3           (0x8UL << FMC_BTR1_CLKDIV_Pos)              /*!< 0x00800000 */
10717 
10718 #define FMC_BTR1_DATLAT_Pos         (24U)
10719 #define FMC_BTR1_DATLAT_Msk         (0xFUL << FMC_BTR1_DATLAT_Pos)              /*!< 0x0F000000 */
10720 #define FMC_BTR1_DATLAT             FMC_BTR1_DATLAT_Msk                        /*!<DATLA[3:0] bits (Data latency) */
10721 #define FMC_BTR1_DATLAT_0           (0x1UL << FMC_BTR1_DATLAT_Pos)              /*!< 0x01000000 */
10722 #define FMC_BTR1_DATLAT_1           (0x2UL << FMC_BTR1_DATLAT_Pos)              /*!< 0x02000000 */
10723 #define FMC_BTR1_DATLAT_2           (0x4UL << FMC_BTR1_DATLAT_Pos)              /*!< 0x04000000 */
10724 #define FMC_BTR1_DATLAT_3           (0x8UL << FMC_BTR1_DATLAT_Pos)              /*!< 0x08000000 */
10725 
10726 #define FMC_BTR1_ACCMOD_Pos         (28U)
10727 #define FMC_BTR1_ACCMOD_Msk         (0x3UL << FMC_BTR1_ACCMOD_Pos)              /*!< 0x30000000 */
10728 #define FMC_BTR1_ACCMOD             FMC_BTR1_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */
10729 #define FMC_BTR1_ACCMOD_0           (0x1UL << FMC_BTR1_ACCMOD_Pos)              /*!< 0x10000000 */
10730 #define FMC_BTR1_ACCMOD_1           (0x2UL << FMC_BTR1_ACCMOD_Pos)              /*!< 0x20000000 */
10731 
10732 /******************  Bit definition for FMC_BTR2 register  *******************/
10733 #define FMC_BTR2_ADDSET_Pos         (0U)
10734 #define FMC_BTR2_ADDSET_Msk         (0xFUL << FMC_BTR2_ADDSET_Pos)              /*!< 0x0000000F */
10735 #define FMC_BTR2_ADDSET             FMC_BTR2_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */
10736 #define FMC_BTR2_ADDSET_0           (0x1UL << FMC_BTR2_ADDSET_Pos)              /*!< 0x00000001 */
10737 #define FMC_BTR2_ADDSET_1           (0x2UL << FMC_BTR2_ADDSET_Pos)              /*!< 0x00000002 */
10738 #define FMC_BTR2_ADDSET_2           (0x4UL << FMC_BTR2_ADDSET_Pos)              /*!< 0x00000004 */
10739 #define FMC_BTR2_ADDSET_3           (0x8UL << FMC_BTR2_ADDSET_Pos)              /*!< 0x00000008 */
10740 
10741 #define FMC_BTR2_ADDHLD_Pos         (4U)
10742 #define FMC_BTR2_ADDHLD_Msk         (0xFUL << FMC_BTR2_ADDHLD_Pos)              /*!< 0x000000F0 */
10743 #define FMC_BTR2_ADDHLD             FMC_BTR2_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
10744 #define FMC_BTR2_ADDHLD_0           (0x1UL << FMC_BTR2_ADDHLD_Pos)              /*!< 0x00000010 */
10745 #define FMC_BTR2_ADDHLD_1           (0x2UL << FMC_BTR2_ADDHLD_Pos)              /*!< 0x00000020 */
10746 #define FMC_BTR2_ADDHLD_2           (0x4UL << FMC_BTR2_ADDHLD_Pos)              /*!< 0x00000040 */
10747 #define FMC_BTR2_ADDHLD_3           (0x8UL << FMC_BTR2_ADDHLD_Pos)              /*!< 0x00000080 */
10748 
10749 #define FMC_BTR2_DATAST_Pos         (8U)
10750 #define FMC_BTR2_DATAST_Msk         (0xFFUL << FMC_BTR2_DATAST_Pos)             /*!< 0x0000FF00 */
10751 #define FMC_BTR2_DATAST             FMC_BTR2_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */
10752 #define FMC_BTR2_DATAST_0           (0x01UL << FMC_BTR2_DATAST_Pos)             /*!< 0x00000100 */
10753 #define FMC_BTR2_DATAST_1           (0x02UL << FMC_BTR2_DATAST_Pos)             /*!< 0x00000200 */
10754 #define FMC_BTR2_DATAST_2           (0x04UL << FMC_BTR2_DATAST_Pos)             /*!< 0x00000400 */
10755 #define FMC_BTR2_DATAST_3           (0x08UL << FMC_BTR2_DATAST_Pos)             /*!< 0x00000800 */
10756 #define FMC_BTR2_DATAST_4           (0x10UL << FMC_BTR2_DATAST_Pos)             /*!< 0x00001000 */
10757 #define FMC_BTR2_DATAST_5           (0x20UL << FMC_BTR2_DATAST_Pos)             /*!< 0x00002000 */
10758 #define FMC_BTR2_DATAST_6           (0x40UL << FMC_BTR2_DATAST_Pos)             /*!< 0x00004000 */
10759 #define FMC_BTR2_DATAST_7           (0x80UL << FMC_BTR2_DATAST_Pos)             /*!< 0x00008000 */
10760 
10761 #define FMC_BTR2_BUSTURN_Pos        (16U)
10762 #define FMC_BTR2_BUSTURN_Msk        (0xFUL << FMC_BTR2_BUSTURN_Pos)             /*!< 0x000F0000 */
10763 #define FMC_BTR2_BUSTURN            FMC_BTR2_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
10764 #define FMC_BTR2_BUSTURN_0          (0x1UL << FMC_BTR2_BUSTURN_Pos)             /*!< 0x00010000 */
10765 #define FMC_BTR2_BUSTURN_1          (0x2UL << FMC_BTR2_BUSTURN_Pos)             /*!< 0x00020000 */
10766 #define FMC_BTR2_BUSTURN_2          (0x4UL << FMC_BTR2_BUSTURN_Pos)             /*!< 0x00040000 */
10767 #define FMC_BTR2_BUSTURN_3          (0x8UL << FMC_BTR2_BUSTURN_Pos)             /*!< 0x00080000 */
10768 
10769 #define FMC_BTR2_CLKDIV_Pos         (20U)
10770 #define FMC_BTR2_CLKDIV_Msk         (0xFUL << FMC_BTR2_CLKDIV_Pos)              /*!< 0x00F00000 */
10771 #define FMC_BTR2_CLKDIV             FMC_BTR2_CLKDIV_Msk                        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
10772 #define FMC_BTR2_CLKDIV_0           (0x1UL << FMC_BTR2_CLKDIV_Pos)              /*!< 0x00100000 */
10773 #define FMC_BTR2_CLKDIV_1           (0x2UL << FMC_BTR2_CLKDIV_Pos)              /*!< 0x00200000 */
10774 #define FMC_BTR2_CLKDIV_2           (0x4UL << FMC_BTR2_CLKDIV_Pos)              /*!< 0x00400000 */
10775 #define FMC_BTR2_CLKDIV_3           (0x8UL << FMC_BTR2_CLKDIV_Pos)              /*!< 0x00800000 */
10776 
10777 #define FMC_BTR2_DATLAT_Pos         (24U)
10778 #define FMC_BTR2_DATLAT_Msk         (0xFUL << FMC_BTR2_DATLAT_Pos)              /*!< 0x0F000000 */
10779 #define FMC_BTR2_DATLAT             FMC_BTR2_DATLAT_Msk                        /*!<DATLA[3:0] bits (Data latency) */
10780 #define FMC_BTR2_DATLAT_0           (0x1UL << FMC_BTR2_DATLAT_Pos)              /*!< 0x01000000 */
10781 #define FMC_BTR2_DATLAT_1           (0x2UL << FMC_BTR2_DATLAT_Pos)              /*!< 0x02000000 */
10782 #define FMC_BTR2_DATLAT_2           (0x4UL << FMC_BTR2_DATLAT_Pos)              /*!< 0x04000000 */
10783 #define FMC_BTR2_DATLAT_3           (0x8UL << FMC_BTR2_DATLAT_Pos)              /*!< 0x08000000 */
10784 
10785 #define FMC_BTR2_ACCMOD_Pos         (28U)
10786 #define FMC_BTR2_ACCMOD_Msk         (0x3UL << FMC_BTR2_ACCMOD_Pos)              /*!< 0x30000000 */
10787 #define FMC_BTR2_ACCMOD             FMC_BTR2_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */
10788 #define FMC_BTR2_ACCMOD_0           (0x1UL << FMC_BTR2_ACCMOD_Pos)              /*!< 0x10000000 */
10789 #define FMC_BTR2_ACCMOD_1           (0x2UL << FMC_BTR2_ACCMOD_Pos)              /*!< 0x20000000 */
10790 
10791 /*******************  Bit definition for FMC_BTR3 register  *******************/
10792 #define FMC_BTR3_ADDSET_Pos         (0U)
10793 #define FMC_BTR3_ADDSET_Msk         (0xFUL << FMC_BTR3_ADDSET_Pos)              /*!< 0x0000000F */
10794 #define FMC_BTR3_ADDSET             FMC_BTR3_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */
10795 #define FMC_BTR3_ADDSET_0           (0x1UL << FMC_BTR3_ADDSET_Pos)              /*!< 0x00000001 */
10796 #define FMC_BTR3_ADDSET_1           (0x2UL << FMC_BTR3_ADDSET_Pos)              /*!< 0x00000002 */
10797 #define FMC_BTR3_ADDSET_2           (0x4UL << FMC_BTR3_ADDSET_Pos)              /*!< 0x00000004 */
10798 #define FMC_BTR3_ADDSET_3           (0x8UL << FMC_BTR3_ADDSET_Pos)              /*!< 0x00000008 */
10799 
10800 #define FMC_BTR3_ADDHLD_Pos         (4U)
10801 #define FMC_BTR3_ADDHLD_Msk         (0xFUL << FMC_BTR3_ADDHLD_Pos)              /*!< 0x000000F0 */
10802 #define FMC_BTR3_ADDHLD             FMC_BTR3_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
10803 #define FMC_BTR3_ADDHLD_0           (0x1UL << FMC_BTR3_ADDHLD_Pos)              /*!< 0x00000010 */
10804 #define FMC_BTR3_ADDHLD_1           (0x2UL << FMC_BTR3_ADDHLD_Pos)              /*!< 0x00000020 */
10805 #define FMC_BTR3_ADDHLD_2           (0x4UL << FMC_BTR3_ADDHLD_Pos)              /*!< 0x00000040 */
10806 #define FMC_BTR3_ADDHLD_3           (0x8UL << FMC_BTR3_ADDHLD_Pos)              /*!< 0x00000080 */
10807 
10808 #define FMC_BTR3_DATAST_Pos         (8U)
10809 #define FMC_BTR3_DATAST_Msk         (0xFFUL << FMC_BTR3_DATAST_Pos)             /*!< 0x0000FF00 */
10810 #define FMC_BTR3_DATAST             FMC_BTR3_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */
10811 #define FMC_BTR3_DATAST_0           (0x01UL << FMC_BTR3_DATAST_Pos)             /*!< 0x00000100 */
10812 #define FMC_BTR3_DATAST_1           (0x02UL << FMC_BTR3_DATAST_Pos)             /*!< 0x00000200 */
10813 #define FMC_BTR3_DATAST_2           (0x04UL << FMC_BTR3_DATAST_Pos)             /*!< 0x00000400 */
10814 #define FMC_BTR3_DATAST_3           (0x08UL << FMC_BTR3_DATAST_Pos)             /*!< 0x00000800 */
10815 #define FMC_BTR3_DATAST_4           (0x10UL << FMC_BTR3_DATAST_Pos)             /*!< 0x00001000 */
10816 #define FMC_BTR3_DATAST_5           (0x20UL << FMC_BTR3_DATAST_Pos)             /*!< 0x00002000 */
10817 #define FMC_BTR3_DATAST_6           (0x40UL << FMC_BTR3_DATAST_Pos)             /*!< 0x00004000 */
10818 #define FMC_BTR3_DATAST_7           (0x80UL << FMC_BTR3_DATAST_Pos)             /*!< 0x00008000 */
10819 
10820 #define FMC_BTR3_BUSTURN_Pos        (16U)
10821 #define FMC_BTR3_BUSTURN_Msk        (0xFUL << FMC_BTR3_BUSTURN_Pos)             /*!< 0x000F0000 */
10822 #define FMC_BTR3_BUSTURN            FMC_BTR3_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
10823 #define FMC_BTR3_BUSTURN_0          (0x1UL << FMC_BTR3_BUSTURN_Pos)             /*!< 0x00010000 */
10824 #define FMC_BTR3_BUSTURN_1          (0x2UL << FMC_BTR3_BUSTURN_Pos)             /*!< 0x00020000 */
10825 #define FMC_BTR3_BUSTURN_2          (0x4UL << FMC_BTR3_BUSTURN_Pos)             /*!< 0x00040000 */
10826 #define FMC_BTR3_BUSTURN_3          (0x8UL << FMC_BTR3_BUSTURN_Pos)             /*!< 0x00080000 */
10827 
10828 #define FMC_BTR3_CLKDIV_Pos         (20U)
10829 #define FMC_BTR3_CLKDIV_Msk         (0xFUL << FMC_BTR3_CLKDIV_Pos)              /*!< 0x00F00000 */
10830 #define FMC_BTR3_CLKDIV             FMC_BTR3_CLKDIV_Msk                        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
10831 #define FMC_BTR3_CLKDIV_0           (0x1UL << FMC_BTR3_CLKDIV_Pos)              /*!< 0x00100000 */
10832 #define FMC_BTR3_CLKDIV_1           (0x2UL << FMC_BTR3_CLKDIV_Pos)              /*!< 0x00200000 */
10833 #define FMC_BTR3_CLKDIV_2           (0x4UL << FMC_BTR3_CLKDIV_Pos)              /*!< 0x00400000 */
10834 #define FMC_BTR3_CLKDIV_3           (0x8UL << FMC_BTR3_CLKDIV_Pos)              /*!< 0x00800000 */
10835 
10836 #define FMC_BTR3_DATLAT_Pos         (24U)
10837 #define FMC_BTR3_DATLAT_Msk         (0xFUL << FMC_BTR3_DATLAT_Pos)              /*!< 0x0F000000 */
10838 #define FMC_BTR3_DATLAT             FMC_BTR3_DATLAT_Msk                        /*!<DATLA[3:0] bits (Data latency) */
10839 #define FMC_BTR3_DATLAT_0           (0x1UL << FMC_BTR3_DATLAT_Pos)              /*!< 0x01000000 */
10840 #define FMC_BTR3_DATLAT_1           (0x2UL << FMC_BTR3_DATLAT_Pos)              /*!< 0x02000000 */
10841 #define FMC_BTR3_DATLAT_2           (0x4UL << FMC_BTR3_DATLAT_Pos)              /*!< 0x04000000 */
10842 #define FMC_BTR3_DATLAT_3           (0x8UL << FMC_BTR3_DATLAT_Pos)              /*!< 0x08000000 */
10843 
10844 #define FMC_BTR3_ACCMOD_Pos         (28U)
10845 #define FMC_BTR3_ACCMOD_Msk         (0x3UL << FMC_BTR3_ACCMOD_Pos)              /*!< 0x30000000 */
10846 #define FMC_BTR3_ACCMOD             FMC_BTR3_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */
10847 #define FMC_BTR3_ACCMOD_0           (0x1UL << FMC_BTR3_ACCMOD_Pos)              /*!< 0x10000000 */
10848 #define FMC_BTR3_ACCMOD_1           (0x2UL << FMC_BTR3_ACCMOD_Pos)              /*!< 0x20000000 */
10849 
10850 /******************  Bit definition for FMC_BTR4 register  *******************/
10851 #define FMC_BTR4_ADDSET_Pos         (0U)
10852 #define FMC_BTR4_ADDSET_Msk         (0xFUL << FMC_BTR4_ADDSET_Pos)              /*!< 0x0000000F */
10853 #define FMC_BTR4_ADDSET             FMC_BTR4_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */
10854 #define FMC_BTR4_ADDSET_0           (0x1UL << FMC_BTR4_ADDSET_Pos)              /*!< 0x00000001 */
10855 #define FMC_BTR4_ADDSET_1           (0x2UL << FMC_BTR4_ADDSET_Pos)              /*!< 0x00000002 */
10856 #define FMC_BTR4_ADDSET_2           (0x4UL << FMC_BTR4_ADDSET_Pos)              /*!< 0x00000004 */
10857 #define FMC_BTR4_ADDSET_3           (0x8UL << FMC_BTR4_ADDSET_Pos)              /*!< 0x00000008 */
10858 
10859 #define FMC_BTR4_ADDHLD_Pos         (4U)
10860 #define FMC_BTR4_ADDHLD_Msk         (0xFUL << FMC_BTR4_ADDHLD_Pos)              /*!< 0x000000F0 */
10861 #define FMC_BTR4_ADDHLD             FMC_BTR4_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
10862 #define FMC_BTR4_ADDHLD_0           (0x1UL << FMC_BTR4_ADDHLD_Pos)              /*!< 0x00000010 */
10863 #define FMC_BTR4_ADDHLD_1           (0x2UL << FMC_BTR4_ADDHLD_Pos)              /*!< 0x00000020 */
10864 #define FMC_BTR4_ADDHLD_2           (0x4UL << FMC_BTR4_ADDHLD_Pos)              /*!< 0x00000040 */
10865 #define FMC_BTR4_ADDHLD_3           (0x8UL << FMC_BTR4_ADDHLD_Pos)              /*!< 0x00000080 */
10866 
10867 #define FMC_BTR4_DATAST_Pos         (8U)
10868 #define FMC_BTR4_DATAST_Msk         (0xFFUL << FMC_BTR4_DATAST_Pos)             /*!< 0x0000FF00 */
10869 #define FMC_BTR4_DATAST             FMC_BTR4_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */
10870 #define FMC_BTR4_DATAST_0           (0x01UL << FMC_BTR4_DATAST_Pos)             /*!< 0x00000100 */
10871 #define FMC_BTR4_DATAST_1           (0x02UL << FMC_BTR4_DATAST_Pos)             /*!< 0x00000200 */
10872 #define FMC_BTR4_DATAST_2           (0x04UL << FMC_BTR4_DATAST_Pos)             /*!< 0x00000400 */
10873 #define FMC_BTR4_DATAST_3           (0x08UL << FMC_BTR4_DATAST_Pos)             /*!< 0x00000800 */
10874 #define FMC_BTR4_DATAST_4           (0x10UL << FMC_BTR4_DATAST_Pos)             /*!< 0x00001000 */
10875 #define FMC_BTR4_DATAST_5           (0x20UL << FMC_BTR4_DATAST_Pos)             /*!< 0x00002000 */
10876 #define FMC_BTR4_DATAST_6           (0x40UL << FMC_BTR4_DATAST_Pos)             /*!< 0x00004000 */
10877 #define FMC_BTR4_DATAST_7           (0x80UL << FMC_BTR4_DATAST_Pos)             /*!< 0x00008000 */
10878 
10879 #define FMC_BTR4_BUSTURN_Pos        (16U)
10880 #define FMC_BTR4_BUSTURN_Msk        (0xFUL << FMC_BTR4_BUSTURN_Pos)             /*!< 0x000F0000 */
10881 #define FMC_BTR4_BUSTURN            FMC_BTR4_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
10882 #define FMC_BTR4_BUSTURN_0          (0x1UL << FMC_BTR4_BUSTURN_Pos)             /*!< 0x00010000 */
10883 #define FMC_BTR4_BUSTURN_1          (0x2UL << FMC_BTR4_BUSTURN_Pos)             /*!< 0x00020000 */
10884 #define FMC_BTR4_BUSTURN_2          (0x4UL << FMC_BTR4_BUSTURN_Pos)             /*!< 0x00040000 */
10885 #define FMC_BTR4_BUSTURN_3          (0x8UL << FMC_BTR4_BUSTURN_Pos)             /*!< 0x00080000 */
10886 
10887 #define FMC_BTR4_CLKDIV_Pos         (20U)
10888 #define FMC_BTR4_CLKDIV_Msk         (0xFUL << FMC_BTR4_CLKDIV_Pos)              /*!< 0x00F00000 */
10889 #define FMC_BTR4_CLKDIV             FMC_BTR4_CLKDIV_Msk                        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
10890 #define FMC_BTR4_CLKDIV_0           (0x1UL << FMC_BTR4_CLKDIV_Pos)              /*!< 0x00100000 */
10891 #define FMC_BTR4_CLKDIV_1           (0x2UL << FMC_BTR4_CLKDIV_Pos)              /*!< 0x00200000 */
10892 #define FMC_BTR4_CLKDIV_2           (0x4UL << FMC_BTR4_CLKDIV_Pos)              /*!< 0x00400000 */
10893 #define FMC_BTR4_CLKDIV_3           (0x8UL << FMC_BTR4_CLKDIV_Pos)              /*!< 0x00800000 */
10894 
10895 #define FMC_BTR4_DATLAT_Pos         (24U)
10896 #define FMC_BTR4_DATLAT_Msk         (0xFUL << FMC_BTR4_DATLAT_Pos)              /*!< 0x0F000000 */
10897 #define FMC_BTR4_DATLAT             FMC_BTR4_DATLAT_Msk                        /*!<DATLA[3:0] bits (Data latency) */
10898 #define FMC_BTR4_DATLAT_0           (0x1UL << FMC_BTR4_DATLAT_Pos)              /*!< 0x01000000 */
10899 #define FMC_BTR4_DATLAT_1           (0x2UL << FMC_BTR4_DATLAT_Pos)              /*!< 0x02000000 */
10900 #define FMC_BTR4_DATLAT_2           (0x4UL << FMC_BTR4_DATLAT_Pos)              /*!< 0x04000000 */
10901 #define FMC_BTR4_DATLAT_3           (0x8UL << FMC_BTR4_DATLAT_Pos)              /*!< 0x08000000 */
10902 
10903 #define FMC_BTR4_ACCMOD_Pos         (28U)
10904 #define FMC_BTR4_ACCMOD_Msk         (0x3UL << FMC_BTR4_ACCMOD_Pos)              /*!< 0x30000000 */
10905 #define FMC_BTR4_ACCMOD             FMC_BTR4_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */
10906 #define FMC_BTR4_ACCMOD_0           (0x1UL << FMC_BTR4_ACCMOD_Pos)              /*!< 0x10000000 */
10907 #define FMC_BTR4_ACCMOD_1           (0x2UL << FMC_BTR4_ACCMOD_Pos)              /*!< 0x20000000 */
10908 
10909 /******************  Bit definition for FMC_BWTR1 register  ******************/
10910 #define FMC_BWTR1_ADDSET_Pos        (0U)
10911 #define FMC_BWTR1_ADDSET_Msk        (0xFUL << FMC_BWTR1_ADDSET_Pos)             /*!< 0x0000000F */
10912 #define FMC_BWTR1_ADDSET            FMC_BWTR1_ADDSET_Msk                       /*!<ADDSET[3:0] bits (Address setup phase duration) */
10913 #define FMC_BWTR1_ADDSET_0          (0x1UL << FMC_BWTR1_ADDSET_Pos)             /*!< 0x00000001 */
10914 #define FMC_BWTR1_ADDSET_1          (0x2UL << FMC_BWTR1_ADDSET_Pos)             /*!< 0x00000002 */
10915 #define FMC_BWTR1_ADDSET_2          (0x4UL << FMC_BWTR1_ADDSET_Pos)             /*!< 0x00000004 */
10916 #define FMC_BWTR1_ADDSET_3          (0x8UL << FMC_BWTR1_ADDSET_Pos)             /*!< 0x00000008 */
10917 
10918 #define FMC_BWTR1_ADDHLD_Pos        (4U)
10919 #define FMC_BWTR1_ADDHLD_Msk        (0xFUL << FMC_BWTR1_ADDHLD_Pos)             /*!< 0x000000F0 */
10920 #define FMC_BWTR1_ADDHLD            FMC_BWTR1_ADDHLD_Msk                       /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
10921 #define FMC_BWTR1_ADDHLD_0          (0x1UL << FMC_BWTR1_ADDHLD_Pos)             /*!< 0x00000010 */
10922 #define FMC_BWTR1_ADDHLD_1          (0x2UL << FMC_BWTR1_ADDHLD_Pos)             /*!< 0x00000020 */
10923 #define FMC_BWTR1_ADDHLD_2          (0x4UL << FMC_BWTR1_ADDHLD_Pos)             /*!< 0x00000040 */
10924 #define FMC_BWTR1_ADDHLD_3          (0x8UL << FMC_BWTR1_ADDHLD_Pos)             /*!< 0x00000080 */
10925 
10926 #define FMC_BWTR1_DATAST_Pos        (8U)
10927 #define FMC_BWTR1_DATAST_Msk        (0xFFUL << FMC_BWTR1_DATAST_Pos)            /*!< 0x0000FF00 */
10928 #define FMC_BWTR1_DATAST            FMC_BWTR1_DATAST_Msk                       /*!<DATAST [3:0] bits (Data-phase duration) */
10929 #define FMC_BWTR1_DATAST_0          (0x01UL << FMC_BWTR1_DATAST_Pos)            /*!< 0x00000100 */
10930 #define FMC_BWTR1_DATAST_1          (0x02UL << FMC_BWTR1_DATAST_Pos)            /*!< 0x00000200 */
10931 #define FMC_BWTR1_DATAST_2          (0x04UL << FMC_BWTR1_DATAST_Pos)            /*!< 0x00000400 */
10932 #define FMC_BWTR1_DATAST_3          (0x08UL << FMC_BWTR1_DATAST_Pos)            /*!< 0x00000800 */
10933 #define FMC_BWTR1_DATAST_4          (0x10UL << FMC_BWTR1_DATAST_Pos)            /*!< 0x00001000 */
10934 #define FMC_BWTR1_DATAST_5          (0x20UL << FMC_BWTR1_DATAST_Pos)            /*!< 0x00002000 */
10935 #define FMC_BWTR1_DATAST_6          (0x40UL << FMC_BWTR1_DATAST_Pos)            /*!< 0x00004000 */
10936 #define FMC_BWTR1_DATAST_7          (0x80UL << FMC_BWTR1_DATAST_Pos)            /*!< 0x00008000 */
10937 
10938 #define FMC_BWTR1_BUSTURN_Pos       (16U)
10939 #define FMC_BWTR1_BUSTURN_Msk       (0xFUL << FMC_BWTR1_BUSTURN_Pos)            /*!< 0x000F0000 */
10940 #define FMC_BWTR1_BUSTURN           FMC_BWTR1_BUSTURN_Msk                      /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
10941 #define FMC_BWTR1_BUSTURN_0         (0x1UL << FMC_BWTR1_BUSTURN_Pos)            /*!< 0x00010000 */
10942 #define FMC_BWTR1_BUSTURN_1         (0x2UL << FMC_BWTR1_BUSTURN_Pos)            /*!< 0x00020000 */
10943 #define FMC_BWTR1_BUSTURN_2         (0x4UL << FMC_BWTR1_BUSTURN_Pos)            /*!< 0x00040000 */
10944 #define FMC_BWTR1_BUSTURN_3         (0x8UL << FMC_BWTR1_BUSTURN_Pos)            /*!< 0x00080000 */
10945 
10946 #define FMC_BWTR1_ACCMOD_Pos        (28U)
10947 #define FMC_BWTR1_ACCMOD_Msk        (0x3UL << FMC_BWTR1_ACCMOD_Pos)             /*!< 0x30000000 */
10948 #define FMC_BWTR1_ACCMOD            FMC_BWTR1_ACCMOD_Msk                       /*!<ACCMOD[1:0] bits (Access mode) */
10949 #define FMC_BWTR1_ACCMOD_0          (0x1UL << FMC_BWTR1_ACCMOD_Pos)             /*!< 0x10000000 */
10950 #define FMC_BWTR1_ACCMOD_1          (0x2UL << FMC_BWTR1_ACCMOD_Pos)             /*!< 0x20000000 */
10951 
10952 /******************  Bit definition for FMC_BWTR2 register  ******************/
10953 #define FMC_BWTR2_ADDSET_Pos        (0U)
10954 #define FMC_BWTR2_ADDSET_Msk        (0xFUL << FMC_BWTR2_ADDSET_Pos)             /*!< 0x0000000F */
10955 #define FMC_BWTR2_ADDSET            FMC_BWTR2_ADDSET_Msk                       /*!<ADDSET[3:0] bits (Address setup phase duration) */
10956 #define FMC_BWTR2_ADDSET_0          (0x1UL << FMC_BWTR2_ADDSET_Pos)             /*!< 0x00000001 */
10957 #define FMC_BWTR2_ADDSET_1          (0x2UL << FMC_BWTR2_ADDSET_Pos)             /*!< 0x00000002 */
10958 #define FMC_BWTR2_ADDSET_2          (0x4UL << FMC_BWTR2_ADDSET_Pos)             /*!< 0x00000004 */
10959 #define FMC_BWTR2_ADDSET_3          (0x8UL << FMC_BWTR2_ADDSET_Pos)             /*!< 0x00000008 */
10960 
10961 #define FMC_BWTR2_ADDHLD_Pos        (4U)
10962 #define FMC_BWTR2_ADDHLD_Msk        (0xFUL << FMC_BWTR2_ADDHLD_Pos)             /*!< 0x000000F0 */
10963 #define FMC_BWTR2_ADDHLD            FMC_BWTR2_ADDHLD_Msk                       /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
10964 #define FMC_BWTR2_ADDHLD_0          (0x1UL << FMC_BWTR2_ADDHLD_Pos)             /*!< 0x00000010 */
10965 #define FMC_BWTR2_ADDHLD_1          (0x2UL << FMC_BWTR2_ADDHLD_Pos)             /*!< 0x00000020 */
10966 #define FMC_BWTR2_ADDHLD_2          (0x4UL << FMC_BWTR2_ADDHLD_Pos)             /*!< 0x00000040 */
10967 #define FMC_BWTR2_ADDHLD_3          (0x8UL << FMC_BWTR2_ADDHLD_Pos)             /*!< 0x00000080 */
10968 
10969 #define FMC_BWTR2_DATAST_Pos        (8U)
10970 #define FMC_BWTR2_DATAST_Msk        (0xFFUL << FMC_BWTR2_DATAST_Pos)            /*!< 0x0000FF00 */
10971 #define FMC_BWTR2_DATAST            FMC_BWTR2_DATAST_Msk                       /*!<DATAST [3:0] bits (Data-phase duration) */
10972 #define FMC_BWTR2_DATAST_0          (0x01UL << FMC_BWTR2_DATAST_Pos)            /*!< 0x00000100 */
10973 #define FMC_BWTR2_DATAST_1          (0x02UL << FMC_BWTR2_DATAST_Pos)            /*!< 0x00000200 */
10974 #define FMC_BWTR2_DATAST_2          (0x04UL << FMC_BWTR2_DATAST_Pos)            /*!< 0x00000400 */
10975 #define FMC_BWTR2_DATAST_3          (0x08UL << FMC_BWTR2_DATAST_Pos)            /*!< 0x00000800 */
10976 #define FMC_BWTR2_DATAST_4          (0x10UL << FMC_BWTR2_DATAST_Pos)            /*!< 0x00001000 */
10977 #define FMC_BWTR2_DATAST_5          (0x20UL << FMC_BWTR2_DATAST_Pos)            /*!< 0x00002000 */
10978 #define FMC_BWTR2_DATAST_6          (0x40UL << FMC_BWTR2_DATAST_Pos)            /*!< 0x00004000 */
10979 #define FMC_BWTR2_DATAST_7          (0x80UL << FMC_BWTR2_DATAST_Pos)            /*!< 0x00008000 */
10980 
10981 #define FMC_BWTR2_BUSTURN_Pos       (16U)
10982 #define FMC_BWTR2_BUSTURN_Msk       (0xFUL << FMC_BWTR2_BUSTURN_Pos)            /*!< 0x000F0000 */
10983 #define FMC_BWTR2_BUSTURN           FMC_BWTR2_BUSTURN_Msk                      /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
10984 #define FMC_BWTR2_BUSTURN_0         (0x1UL << FMC_BWTR2_BUSTURN_Pos)            /*!< 0x00010000 */
10985 #define FMC_BWTR2_BUSTURN_1         (0x2UL << FMC_BWTR2_BUSTURN_Pos)            /*!< 0x00020000 */
10986 #define FMC_BWTR2_BUSTURN_2         (0x4UL << FMC_BWTR2_BUSTURN_Pos)            /*!< 0x00040000 */
10987 #define FMC_BWTR2_BUSTURN_3         (0x8UL << FMC_BWTR2_BUSTURN_Pos)            /*!< 0x00080000 */
10988 
10989 #define FMC_BWTR2_ACCMOD_Pos        (28U)
10990 #define FMC_BWTR2_ACCMOD_Msk        (0x3UL << FMC_BWTR2_ACCMOD_Pos)             /*!< 0x30000000 */
10991 #define FMC_BWTR2_ACCMOD            FMC_BWTR2_ACCMOD_Msk                       /*!<ACCMOD[1:0] bits (Access mode) */
10992 #define FMC_BWTR2_ACCMOD_0          (0x1UL << FMC_BWTR2_ACCMOD_Pos)             /*!< 0x10000000 */
10993 #define FMC_BWTR2_ACCMOD_1          (0x2UL << FMC_BWTR2_ACCMOD_Pos)             /*!< 0x20000000 */
10994 
10995 /******************  Bit definition for FMC_BWTR3 register  ******************/
10996 #define FMC_BWTR3_ADDSET_Pos        (0U)
10997 #define FMC_BWTR3_ADDSET_Msk        (0xFUL << FMC_BWTR3_ADDSET_Pos)             /*!< 0x0000000F */
10998 #define FMC_BWTR3_ADDSET            FMC_BWTR3_ADDSET_Msk                       /*!<ADDSET[3:0] bits (Address setup phase duration) */
10999 #define FMC_BWTR3_ADDSET_0          (0x1UL << FMC_BWTR3_ADDSET_Pos)             /*!< 0x00000001 */
11000 #define FMC_BWTR3_ADDSET_1          (0x2UL << FMC_BWTR3_ADDSET_Pos)             /*!< 0x00000002 */
11001 #define FMC_BWTR3_ADDSET_2          (0x4UL << FMC_BWTR3_ADDSET_Pos)             /*!< 0x00000004 */
11002 #define FMC_BWTR3_ADDSET_3          (0x8UL << FMC_BWTR3_ADDSET_Pos)             /*!< 0x00000008 */
11003 
11004 #define FMC_BWTR3_ADDHLD_Pos        (4U)
11005 #define FMC_BWTR3_ADDHLD_Msk        (0xFUL << FMC_BWTR3_ADDHLD_Pos)             /*!< 0x000000F0 */
11006 #define FMC_BWTR3_ADDHLD            FMC_BWTR3_ADDHLD_Msk                       /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
11007 #define FMC_BWTR3_ADDHLD_0          (0x1UL << FMC_BWTR3_ADDHLD_Pos)             /*!< 0x00000010 */
11008 #define FMC_BWTR3_ADDHLD_1          (0x2UL << FMC_BWTR3_ADDHLD_Pos)             /*!< 0x00000020 */
11009 #define FMC_BWTR3_ADDHLD_2          (0x4UL << FMC_BWTR3_ADDHLD_Pos)             /*!< 0x00000040 */
11010 #define FMC_BWTR3_ADDHLD_3          (0x8UL << FMC_BWTR3_ADDHLD_Pos)             /*!< 0x00000080 */
11011 
11012 #define FMC_BWTR3_DATAST_Pos        (8U)
11013 #define FMC_BWTR3_DATAST_Msk        (0xFFUL << FMC_BWTR3_DATAST_Pos)            /*!< 0x0000FF00 */
11014 #define FMC_BWTR3_DATAST            FMC_BWTR3_DATAST_Msk                       /*!<DATAST [3:0] bits (Data-phase duration) */
11015 #define FMC_BWTR3_DATAST_0          (0x01UL << FMC_BWTR3_DATAST_Pos)            /*!< 0x00000100 */
11016 #define FMC_BWTR3_DATAST_1          (0x02UL << FMC_BWTR3_DATAST_Pos)            /*!< 0x00000200 */
11017 #define FMC_BWTR3_DATAST_2          (0x04UL << FMC_BWTR3_DATAST_Pos)            /*!< 0x00000400 */
11018 #define FMC_BWTR3_DATAST_3          (0x08UL << FMC_BWTR3_DATAST_Pos)            /*!< 0x00000800 */
11019 #define FMC_BWTR3_DATAST_4          (0x10UL << FMC_BWTR3_DATAST_Pos)            /*!< 0x00001000 */
11020 #define FMC_BWTR3_DATAST_5          (0x20UL << FMC_BWTR3_DATAST_Pos)            /*!< 0x00002000 */
11021 #define FMC_BWTR3_DATAST_6          (0x40UL << FMC_BWTR3_DATAST_Pos)            /*!< 0x00004000 */
11022 #define FMC_BWTR3_DATAST_7          (0x80UL << FMC_BWTR3_DATAST_Pos)            /*!< 0x00008000 */
11023 
11024 #define FMC_BWTR3_BUSTURN_Pos       (16U)
11025 #define FMC_BWTR3_BUSTURN_Msk       (0xFUL << FMC_BWTR3_BUSTURN_Pos)            /*!< 0x000F0000 */
11026 #define FMC_BWTR3_BUSTURN           FMC_BWTR3_BUSTURN_Msk                      /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
11027 #define FMC_BWTR3_BUSTURN_0         (0x1UL << FMC_BWTR3_BUSTURN_Pos)            /*!< 0x00010000 */
11028 #define FMC_BWTR3_BUSTURN_1         (0x2UL << FMC_BWTR3_BUSTURN_Pos)            /*!< 0x00020000 */
11029 #define FMC_BWTR3_BUSTURN_2         (0x4UL << FMC_BWTR3_BUSTURN_Pos)            /*!< 0x00040000 */
11030 #define FMC_BWTR3_BUSTURN_3         (0x8UL << FMC_BWTR3_BUSTURN_Pos)            /*!< 0x00080000 */
11031 
11032 #define FMC_BWTR3_ACCMOD_Pos        (28U)
11033 #define FMC_BWTR3_ACCMOD_Msk        (0x3UL << FMC_BWTR3_ACCMOD_Pos)             /*!< 0x30000000 */
11034 #define FMC_BWTR3_ACCMOD            FMC_BWTR3_ACCMOD_Msk                       /*!<ACCMOD[1:0] bits (Access mode) */
11035 #define FMC_BWTR3_ACCMOD_0          (0x1UL << FMC_BWTR3_ACCMOD_Pos)             /*!< 0x10000000 */
11036 #define FMC_BWTR3_ACCMOD_1          (0x2UL << FMC_BWTR3_ACCMOD_Pos)             /*!< 0x20000000 */
11037 
11038 /******************  Bit definition for FMC_BWTR4 register  ******************/
11039 #define FMC_BWTR4_ADDSET_Pos        (0U)
11040 #define FMC_BWTR4_ADDSET_Msk        (0xFUL << FMC_BWTR4_ADDSET_Pos)             /*!< 0x0000000F */
11041 #define FMC_BWTR4_ADDSET            FMC_BWTR4_ADDSET_Msk                       /*!<ADDSET[3:0] bits (Address setup phase duration) */
11042 #define FMC_BWTR4_ADDSET_0          (0x1UL << FMC_BWTR4_ADDSET_Pos)             /*!< 0x00000001 */
11043 #define FMC_BWTR4_ADDSET_1          (0x2UL << FMC_BWTR4_ADDSET_Pos)             /*!< 0x00000002 */
11044 #define FMC_BWTR4_ADDSET_2          (0x4UL << FMC_BWTR4_ADDSET_Pos)             /*!< 0x00000004 */
11045 #define FMC_BWTR4_ADDSET_3          (0x8UL << FMC_BWTR4_ADDSET_Pos)             /*!< 0x00000008 */
11046 
11047 #define FMC_BWTR4_ADDHLD_Pos        (4U)
11048 #define FMC_BWTR4_ADDHLD_Msk        (0xFUL << FMC_BWTR4_ADDHLD_Pos)             /*!< 0x000000F0 */
11049 #define FMC_BWTR4_ADDHLD            FMC_BWTR4_ADDHLD_Msk                       /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
11050 #define FMC_BWTR4_ADDHLD_0          (0x1UL << FMC_BWTR4_ADDHLD_Pos)             /*!< 0x00000010 */
11051 #define FMC_BWTR4_ADDHLD_1          (0x2UL << FMC_BWTR4_ADDHLD_Pos)             /*!< 0x00000020 */
11052 #define FMC_BWTR4_ADDHLD_2          (0x4UL << FMC_BWTR4_ADDHLD_Pos)             /*!< 0x00000040 */
11053 #define FMC_BWTR4_ADDHLD_3          (0x8UL << FMC_BWTR4_ADDHLD_Pos)             /*!< 0x00000080 */
11054 
11055 #define FMC_BWTR4_DATAST_Pos        (8U)
11056 #define FMC_BWTR4_DATAST_Msk        (0xFFUL << FMC_BWTR4_DATAST_Pos)            /*!< 0x0000FF00 */
11057 #define FMC_BWTR4_DATAST            FMC_BWTR4_DATAST_Msk                       /*!<DATAST [3:0] bits (Data-phase duration) */
11058 #define FMC_BWTR4_DATAST_0          (0x01UL << FMC_BWTR4_DATAST_Pos)            /*!< 0x00000100 */
11059 #define FMC_BWTR4_DATAST_1          (0x02UL << FMC_BWTR4_DATAST_Pos)            /*!< 0x00000200 */
11060 #define FMC_BWTR4_DATAST_2          (0x04UL << FMC_BWTR4_DATAST_Pos)            /*!< 0x00000400 */
11061 #define FMC_BWTR4_DATAST_3          (0x08UL << FMC_BWTR4_DATAST_Pos)            /*!< 0x00000800 */
11062 #define FMC_BWTR4_DATAST_4          (0x10UL << FMC_BWTR4_DATAST_Pos)            /*!< 0x00001000 */
11063 #define FMC_BWTR4_DATAST_5          (0x20UL << FMC_BWTR4_DATAST_Pos)            /*!< 0x00002000 */
11064 #define FMC_BWTR4_DATAST_6          (0x40UL << FMC_BWTR4_DATAST_Pos)            /*!< 0x00004000 */
11065 #define FMC_BWTR4_DATAST_7          (0x80UL << FMC_BWTR4_DATAST_Pos)            /*!< 0x00008000 */
11066 
11067 #define FMC_BWTR4_BUSTURN_Pos       (16U)
11068 #define FMC_BWTR4_BUSTURN_Msk       (0xFUL << FMC_BWTR4_BUSTURN_Pos)            /*!< 0x000F0000 */
11069 #define FMC_BWTR4_BUSTURN           FMC_BWTR4_BUSTURN_Msk                      /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
11070 #define FMC_BWTR4_BUSTURN_0         (0x1UL << FMC_BWTR4_BUSTURN_Pos)            /*!< 0x00010000 */
11071 #define FMC_BWTR4_BUSTURN_1         (0x2UL << FMC_BWTR4_BUSTURN_Pos)            /*!< 0x00020000 */
11072 #define FMC_BWTR4_BUSTURN_2         (0x4UL << FMC_BWTR4_BUSTURN_Pos)            /*!< 0x00040000 */
11073 #define FMC_BWTR4_BUSTURN_3         (0x8UL << FMC_BWTR4_BUSTURN_Pos)            /*!< 0x00080000 */
11074 
11075 #define FMC_BWTR4_ACCMOD_Pos        (28U)
11076 #define FMC_BWTR4_ACCMOD_Msk        (0x3UL << FMC_BWTR4_ACCMOD_Pos)             /*!< 0x30000000 */
11077 #define FMC_BWTR4_ACCMOD            FMC_BWTR4_ACCMOD_Msk                       /*!<ACCMOD[1:0] bits (Access mode) */
11078 #define FMC_BWTR4_ACCMOD_0          (0x1UL << FMC_BWTR4_ACCMOD_Pos)             /*!< 0x10000000 */
11079 #define FMC_BWTR4_ACCMOD_1          (0x2UL << FMC_BWTR4_ACCMOD_Pos)             /*!< 0x20000000 */
11080 
11081 /******************  Bit definition for FMC_PCR register  *******************/
11082 #define FMC_PCR_PWAITEN_Pos         (1U)
11083 #define FMC_PCR_PWAITEN_Msk         (0x1UL << FMC_PCR_PWAITEN_Pos)              /*!< 0x00000002 */
11084 #define FMC_PCR_PWAITEN             FMC_PCR_PWAITEN_Msk                        /*!<Wait feature enable bit                   */
11085 #define FMC_PCR_PBKEN_Pos           (2U)
11086 #define FMC_PCR_PBKEN_Msk           (0x1UL << FMC_PCR_PBKEN_Pos)                /*!< 0x00000004 */
11087 #define FMC_PCR_PBKEN               FMC_PCR_PBKEN_Msk                          /*!<PC Card/NAND Flash memory bank enable bit */
11088 #define FMC_PCR_PTYP_Pos            (3U)
11089 #define FMC_PCR_PTYP_Msk            (0x1UL << FMC_PCR_PTYP_Pos)                 /*!< 0x00000008 */
11090 #define FMC_PCR_PTYP                FMC_PCR_PTYP_Msk                           /*!<Memory type                               */
11091 
11092 #define FMC_PCR_PWID_Pos            (4U)
11093 #define FMC_PCR_PWID_Msk            (0x3UL << FMC_PCR_PWID_Pos)                 /*!< 0x00000030 */
11094 #define FMC_PCR_PWID                FMC_PCR_PWID_Msk                           /*!<PWID[1:0] bits (NAND Flash databus width) */
11095 #define FMC_PCR_PWID_0              (0x1UL << FMC_PCR_PWID_Pos)                 /*!< 0x00000010 */
11096 #define FMC_PCR_PWID_1              (0x2UL << FMC_PCR_PWID_Pos)                 /*!< 0x00000020 */
11097 
11098 #define FMC_PCR_ECCEN_Pos           (6U)
11099 #define FMC_PCR_ECCEN_Msk           (0x1UL << FMC_PCR_ECCEN_Pos)                /*!< 0x00000040 */
11100 #define FMC_PCR_ECCEN               FMC_PCR_ECCEN_Msk                          /*!<ECC computation logic enable bit          */
11101 
11102 #define FMC_PCR_TCLR_Pos            (9U)
11103 #define FMC_PCR_TCLR_Msk            (0xFUL << FMC_PCR_TCLR_Pos)                 /*!< 0x00001E00 */
11104 #define FMC_PCR_TCLR                FMC_PCR_TCLR_Msk                           /*!<TCLR[3:0] bits (CLE to RE delay)          */
11105 #define FMC_PCR_TCLR_0              (0x1UL << FMC_PCR_TCLR_Pos)                 /*!< 0x00000200 */
11106 #define FMC_PCR_TCLR_1              (0x2UL << FMC_PCR_TCLR_Pos)                 /*!< 0x00000400 */
11107 #define FMC_PCR_TCLR_2              (0x4UL << FMC_PCR_TCLR_Pos)                 /*!< 0x00000800 */
11108 #define FMC_PCR_TCLR_3              (0x8UL << FMC_PCR_TCLR_Pos)                 /*!< 0x00001000 */
11109 
11110 #define FMC_PCR_TAR_Pos             (13U)
11111 #define FMC_PCR_TAR_Msk             (0xFUL << FMC_PCR_TAR_Pos)                  /*!< 0x0001E000 */
11112 #define FMC_PCR_TAR                 FMC_PCR_TAR_Msk                            /*!<TAR[3:0] bits (ALE to RE delay)           */
11113 #define FMC_PCR_TAR_0               (0x1UL << FMC_PCR_TAR_Pos)                  /*!< 0x00002000 */
11114 #define FMC_PCR_TAR_1               (0x2UL << FMC_PCR_TAR_Pos)                  /*!< 0x00004000 */
11115 #define FMC_PCR_TAR_2               (0x4UL << FMC_PCR_TAR_Pos)                  /*!< 0x00008000 */
11116 #define FMC_PCR_TAR_3               (0x8UL << FMC_PCR_TAR_Pos)                  /*!< 0x00010000 */
11117 
11118 #define FMC_PCR_ECCPS_Pos           (17U)
11119 #define FMC_PCR_ECCPS_Msk           (0x7UL << FMC_PCR_ECCPS_Pos)                /*!< 0x000E0000 */
11120 #define FMC_PCR_ECCPS               FMC_PCR_ECCPS_Msk                          /*!<ECCPS[1:0] bits (ECC page size)           */
11121 #define FMC_PCR_ECCPS_0             (0x1UL << FMC_PCR_ECCPS_Pos)                /*!< 0x00020000 */
11122 #define FMC_PCR_ECCPS_1             (0x2UL << FMC_PCR_ECCPS_Pos)                /*!< 0x00040000 */
11123 #define FMC_PCR_ECCPS_2             (0x4UL << FMC_PCR_ECCPS_Pos)                /*!< 0x00080000 */
11124 
11125 /*******************  Bit definition for FMC_SR register  *******************/
11126 #define FMC_SR_IRS_Pos              (0U)
11127 #define FMC_SR_IRS_Msk              (0x1UL << FMC_SR_IRS_Pos)                   /*!< 0x00000001 */
11128 #define FMC_SR_IRS                  FMC_SR_IRS_Msk                             /*!<Interrupt Rising Edge status                */
11129 #define FMC_SR_ILS_Pos              (1U)
11130 #define FMC_SR_ILS_Msk              (0x1UL << FMC_SR_ILS_Pos)                   /*!< 0x00000002 */
11131 #define FMC_SR_ILS                  FMC_SR_ILS_Msk                             /*!<Interrupt Level status                      */
11132 #define FMC_SR_IFS_Pos              (2U)
11133 #define FMC_SR_IFS_Msk              (0x1UL << FMC_SR_IFS_Pos)                   /*!< 0x00000004 */
11134 #define FMC_SR_IFS                  FMC_SR_IFS_Msk                             /*!<Interrupt Falling Edge status               */
11135 #define FMC_SR_IREN_Pos             (3U)
11136 #define FMC_SR_IREN_Msk             (0x1UL << FMC_SR_IREN_Pos)                  /*!< 0x00000008 */
11137 #define FMC_SR_IREN                 FMC_SR_IREN_Msk                            /*!<Interrupt Rising Edge detection Enable bit  */
11138 #define FMC_SR_ILEN_Pos             (4U)
11139 #define FMC_SR_ILEN_Msk             (0x1UL << FMC_SR_ILEN_Pos)                  /*!< 0x00000010 */
11140 #define FMC_SR_ILEN                 FMC_SR_ILEN_Msk                            /*!<Interrupt Level detection Enable bit        */
11141 #define FMC_SR_IFEN_Pos             (5U)
11142 #define FMC_SR_IFEN_Msk             (0x1UL << FMC_SR_IFEN_Pos)                  /*!< 0x00000020 */
11143 #define FMC_SR_IFEN                 FMC_SR_IFEN_Msk                            /*!<Interrupt Falling Edge detection Enable bit */
11144 #define FMC_SR_FEMPT_Pos            (6U)
11145 #define FMC_SR_FEMPT_Msk            (0x1UL << FMC_SR_FEMPT_Pos)                 /*!< 0x00000040 */
11146 #define FMC_SR_FEMPT                FMC_SR_FEMPT_Msk                           /*!<FIFO empty                                  */
11147 
11148 /******************  Bit definition for FMC_PMEM register  ******************/
11149 #define FMC_PMEM_MEMSET2_Pos        (0U)
11150 #define FMC_PMEM_MEMSET2_Msk        (0xFFUL << FMC_PMEM_MEMSET2_Pos)            /*!< 0x000000FF */
11151 #define FMC_PMEM_MEMSET2            FMC_PMEM_MEMSET2_Msk                       /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
11152 #define FMC_PMEM_MEMSET2_0          (0x01UL << FMC_PMEM_MEMSET2_Pos)            /*!< 0x00000001 */
11153 #define FMC_PMEM_MEMSET2_1          (0x02UL << FMC_PMEM_MEMSET2_Pos)            /*!< 0x00000002 */
11154 #define FMC_PMEM_MEMSET2_2          (0x04UL << FMC_PMEM_MEMSET2_Pos)            /*!< 0x00000004 */
11155 #define FMC_PMEM_MEMSET2_3          (0x08UL << FMC_PMEM_MEMSET2_Pos)            /*!< 0x00000008 */
11156 #define FMC_PMEM_MEMSET2_4          (0x10UL << FMC_PMEM_MEMSET2_Pos)            /*!< 0x00000010 */
11157 #define FMC_PMEM_MEMSET2_5          (0x20UL << FMC_PMEM_MEMSET2_Pos)            /*!< 0x00000020 */
11158 #define FMC_PMEM_MEMSET2_6          (0x40UL << FMC_PMEM_MEMSET2_Pos)            /*!< 0x00000040 */
11159 #define FMC_PMEM_MEMSET2_7          (0x80UL << FMC_PMEM_MEMSET2_Pos)            /*!< 0x00000080 */
11160 
11161 #define FMC_PMEM_MEMWAIT2_Pos       (8U)
11162 #define FMC_PMEM_MEMWAIT2_Msk       (0xFFUL << FMC_PMEM_MEMWAIT2_Pos)           /*!< 0x0000FF00 */
11163 #define FMC_PMEM_MEMWAIT2           FMC_PMEM_MEMWAIT2_Msk                      /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
11164 #define FMC_PMEM_MEMWAIT2_0         (0x01UL << FMC_PMEM_MEMWAIT2_Pos)           /*!< 0x00000100 */
11165 #define FMC_PMEM_MEMWAIT2_1         (0x02UL << FMC_PMEM_MEMWAIT2_Pos)           /*!< 0x00000200 */
11166 #define FMC_PMEM_MEMWAIT2_2         (0x04UL << FMC_PMEM_MEMWAIT2_Pos)           /*!< 0x00000400 */
11167 #define FMC_PMEM_MEMWAIT2_3         (0x08UL << FMC_PMEM_MEMWAIT2_Pos)           /*!< 0x00000800 */
11168 #define FMC_PMEM_MEMWAIT2_4         (0x10UL << FMC_PMEM_MEMWAIT2_Pos)           /*!< 0x00001000 */
11169 #define FMC_PMEM_MEMWAIT2_5         (0x20UL << FMC_PMEM_MEMWAIT2_Pos)           /*!< 0x00002000 */
11170 #define FMC_PMEM_MEMWAIT2_6         (0x40UL << FMC_PMEM_MEMWAIT2_Pos)           /*!< 0x00004000 */
11171 #define FMC_PMEM_MEMWAIT2_7         (0x80UL << FMC_PMEM_MEMWAIT2_Pos)           /*!< 0x00008000 */
11172 
11173 #define FMC_PMEM_MEMHOLD2_Pos       (16U)
11174 #define FMC_PMEM_MEMHOLD2_Msk       (0xFFUL << FMC_PMEM_MEMHOLD2_Pos)           /*!< 0x00FF0000 */
11175 #define FMC_PMEM_MEMHOLD2           FMC_PMEM_MEMHOLD2_Msk                      /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
11176 #define FMC_PMEM_MEMHOLD2_0         (0x01UL << FMC_PMEM_MEMHOLD2_Pos)           /*!< 0x00010000 */
11177 #define FMC_PMEM_MEMHOLD2_1         (0x02UL << FMC_PMEM_MEMHOLD2_Pos)           /*!< 0x00020000 */
11178 #define FMC_PMEM_MEMHOLD2_2         (0x04UL << FMC_PMEM_MEMHOLD2_Pos)           /*!< 0x00040000 */
11179 #define FMC_PMEM_MEMHOLD2_3         (0x08UL << FMC_PMEM_MEMHOLD2_Pos)           /*!< 0x00080000 */
11180 #define FMC_PMEM_MEMHOLD2_4         (0x10UL << FMC_PMEM_MEMHOLD2_Pos)           /*!< 0x00100000 */
11181 #define FMC_PMEM_MEMHOLD2_5         (0x20UL << FMC_PMEM_MEMHOLD2_Pos)           /*!< 0x00200000 */
11182 #define FMC_PMEM_MEMHOLD2_6         (0x40UL << FMC_PMEM_MEMHOLD2_Pos)           /*!< 0x00400000 */
11183 #define FMC_PMEM_MEMHOLD2_7         (0x80UL << FMC_PMEM_MEMHOLD2_Pos)           /*!< 0x00800000 */
11184 
11185 #define FMC_PMEM_MEMHIZ2_Pos        (24U)
11186 #define FMC_PMEM_MEMHIZ2_Msk        (0xFFUL << FMC_PMEM_MEMHIZ2_Pos)            /*!< 0xFF000000 */
11187 #define FMC_PMEM_MEMHIZ2            FMC_PMEM_MEMHIZ2_Msk                       /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
11188 #define FMC_PMEM_MEMHIZ2_0          (0x01UL << FMC_PMEM_MEMHIZ2_Pos)            /*!< 0x01000000 */
11189 #define FMC_PMEM_MEMHIZ2_1          (0x02UL << FMC_PMEM_MEMHIZ2_Pos)            /*!< 0x02000000 */
11190 #define FMC_PMEM_MEMHIZ2_2          (0x04UL << FMC_PMEM_MEMHIZ2_Pos)            /*!< 0x04000000 */
11191 #define FMC_PMEM_MEMHIZ2_3          (0x08UL << FMC_PMEM_MEMHIZ2_Pos)            /*!< 0x08000000 */
11192 #define FMC_PMEM_MEMHIZ2_4          (0x10UL << FMC_PMEM_MEMHIZ2_Pos)            /*!< 0x10000000 */
11193 #define FMC_PMEM_MEMHIZ2_5          (0x20UL << FMC_PMEM_MEMHIZ2_Pos)            /*!< 0x20000000 */
11194 #define FMC_PMEM_MEMHIZ2_6          (0x40UL << FMC_PMEM_MEMHIZ2_Pos)            /*!< 0x40000000 */
11195 #define FMC_PMEM_MEMHIZ2_7          (0x80UL << FMC_PMEM_MEMHIZ2_Pos)            /*!< 0x80000000 */
11196 
11197 /******************  Bit definition for FMC_PATT register  ******************/
11198 #define FMC_PATT_ATTSET2_Pos        (0U)
11199 #define FMC_PATT_ATTSET2_Msk        (0xFFUL << FMC_PATT_ATTSET2_Pos)            /*!< 0x000000FF */
11200 #define FMC_PATT_ATTSET2            FMC_PATT_ATTSET2_Msk                       /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
11201 #define FMC_PATT_ATTSET2_0          (0x01UL << FMC_PATT_ATTSET2_Pos)            /*!< 0x00000001 */
11202 #define FMC_PATT_ATTSET2_1          (0x02UL << FMC_PATT_ATTSET2_Pos)            /*!< 0x00000002 */
11203 #define FMC_PATT_ATTSET2_2          (0x04UL << FMC_PATT_ATTSET2_Pos)            /*!< 0x00000004 */
11204 #define FMC_PATT_ATTSET2_3          (0x08UL << FMC_PATT_ATTSET2_Pos)            /*!< 0x00000008 */
11205 #define FMC_PATT_ATTSET2_4          (0x10UL << FMC_PATT_ATTSET2_Pos)            /*!< 0x00000010 */
11206 #define FMC_PATT_ATTSET2_5          (0x20UL << FMC_PATT_ATTSET2_Pos)            /*!< 0x00000020 */
11207 #define FMC_PATT_ATTSET2_6          (0x40UL << FMC_PATT_ATTSET2_Pos)            /*!< 0x00000040 */
11208 #define FMC_PATT_ATTSET2_7          (0x80UL << FMC_PATT_ATTSET2_Pos)            /*!< 0x00000080 */
11209 
11210 #define FMC_PATT_ATTWAIT2_Pos       (8U)
11211 #define FMC_PATT_ATTWAIT2_Msk       (0xFFUL << FMC_PATT_ATTWAIT2_Pos)           /*!< 0x0000FF00 */
11212 #define FMC_PATT_ATTWAIT2           FMC_PATT_ATTWAIT2_Msk                      /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
11213 #define FMC_PATT_ATTWAIT2_0         (0x01UL << FMC_PATT_ATTWAIT2_Pos)           /*!< 0x00000100 */
11214 #define FMC_PATT_ATTWAIT2_1         (0x02UL << FMC_PATT_ATTWAIT2_Pos)           /*!< 0x00000200 */
11215 #define FMC_PATT_ATTWAIT2_2         (0x04UL << FMC_PATT_ATTWAIT2_Pos)           /*!< 0x00000400 */
11216 #define FMC_PATT_ATTWAIT2_3         (0x08UL << FMC_PATT_ATTWAIT2_Pos)           /*!< 0x00000800 */
11217 #define FMC_PATT_ATTWAIT2_4         (0x10UL << FMC_PATT_ATTWAIT2_Pos)           /*!< 0x00001000 */
11218 #define FMC_PATT_ATTWAIT2_5         (0x20UL << FMC_PATT_ATTWAIT2_Pos)           /*!< 0x00002000 */
11219 #define FMC_PATT_ATTWAIT2_6         (0x40UL << FMC_PATT_ATTWAIT2_Pos)           /*!< 0x00004000 */
11220 #define FMC_PATT_ATTWAIT2_7         (0x80UL << FMC_PATT_ATTWAIT2_Pos)           /*!< 0x00008000 */
11221 
11222 #define FMC_PATT_ATTHOLD2_Pos       (16U)
11223 #define FMC_PATT_ATTHOLD2_Msk       (0xFFUL << FMC_PATT_ATTHOLD2_Pos)           /*!< 0x00FF0000 */
11224 #define FMC_PATT_ATTHOLD2           FMC_PATT_ATTHOLD2_Msk                      /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
11225 #define FMC_PATT_ATTHOLD2_0         (0x01UL << FMC_PATT_ATTHOLD2_Pos)           /*!< 0x00010000 */
11226 #define FMC_PATT_ATTHOLD2_1         (0x02UL << FMC_PATT_ATTHOLD2_Pos)           /*!< 0x00020000 */
11227 #define FMC_PATT_ATTHOLD2_2         (0x04UL << FMC_PATT_ATTHOLD2_Pos)           /*!< 0x00040000 */
11228 #define FMC_PATT_ATTHOLD2_3         (0x08UL << FMC_PATT_ATTHOLD2_Pos)           /*!< 0x00080000 */
11229 #define FMC_PATT_ATTHOLD2_4         (0x10UL << FMC_PATT_ATTHOLD2_Pos)           /*!< 0x00100000 */
11230 #define FMC_PATT_ATTHOLD2_5         (0x20UL << FMC_PATT_ATTHOLD2_Pos)           /*!< 0x00200000 */
11231 #define FMC_PATT_ATTHOLD2_6         (0x40UL << FMC_PATT_ATTHOLD2_Pos)           /*!< 0x00400000 */
11232 #define FMC_PATT_ATTHOLD2_7         (0x80UL << FMC_PATT_ATTHOLD2_Pos)           /*!< 0x00800000 */
11233 
11234 #define FMC_PATT_ATTHIZ2_Pos        (24U)
11235 #define FMC_PATT_ATTHIZ2_Msk        (0xFFUL << FMC_PATT_ATTHIZ2_Pos)            /*!< 0xFF000000 */
11236 #define FMC_PATT_ATTHIZ2            FMC_PATT_ATTHIZ2_Msk                       /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
11237 #define FMC_PATT_ATTHIZ2_0          (0x01UL << FMC_PATT_ATTHIZ2_Pos)            /*!< 0x01000000 */
11238 #define FMC_PATT_ATTHIZ2_1          (0x02UL << FMC_PATT_ATTHIZ2_Pos)            /*!< 0x02000000 */
11239 #define FMC_PATT_ATTHIZ2_2          (0x04UL << FMC_PATT_ATTHIZ2_Pos)            /*!< 0x04000000 */
11240 #define FMC_PATT_ATTHIZ2_3          (0x08UL << FMC_PATT_ATTHIZ2_Pos)            /*!< 0x08000000 */
11241 #define FMC_PATT_ATTHIZ2_4          (0x10UL << FMC_PATT_ATTHIZ2_Pos)            /*!< 0x10000000 */
11242 #define FMC_PATT_ATTHIZ2_5          (0x20UL << FMC_PATT_ATTHIZ2_Pos)            /*!< 0x20000000 */
11243 #define FMC_PATT_ATTHIZ2_6          (0x40UL << FMC_PATT_ATTHIZ2_Pos)            /*!< 0x40000000 */
11244 #define FMC_PATT_ATTHIZ2_7          (0x80UL << FMC_PATT_ATTHIZ2_Pos)            /*!< 0x80000000 */
11245 
11246 /******************  Bit definition for FMC_ECCR register  ******************/
11247 #define FMC_ECCR_ECC2_Pos           (0U)
11248 #define FMC_ECCR_ECC2_Msk           (0xFFFFFFFFUL << FMC_ECCR_ECC2_Pos)         /*!< 0xFFFFFFFF */
11249 #define FMC_ECCR_ECC2               FMC_ECCR_ECC2_Msk                          /*!<ECC result */
11250 
11251 /******************  Bit definition for FMC_SDCR1 register  ******************/
11252 #define FMC_SDCR1_NC_Pos            (0U)
11253 #define FMC_SDCR1_NC_Msk            (0x3UL << FMC_SDCR1_NC_Pos)                 /*!< 0x00000003 */
11254 #define FMC_SDCR1_NC                FMC_SDCR1_NC_Msk                           /*!<NC[1:0] bits (Number of column bits) */
11255 #define FMC_SDCR1_NC_0              (0x1UL << FMC_SDCR1_NC_Pos)                 /*!< 0x00000001 */
11256 #define FMC_SDCR1_NC_1              (0x2UL << FMC_SDCR1_NC_Pos)                 /*!< 0x00000002 */
11257 
11258 #define FMC_SDCR1_NR_Pos            (2U)
11259 #define FMC_SDCR1_NR_Msk            (0x3UL << FMC_SDCR1_NR_Pos)                 /*!< 0x0000000C */
11260 #define FMC_SDCR1_NR                FMC_SDCR1_NR_Msk                           /*!<NR[1:0] bits (Number of row bits) */
11261 #define FMC_SDCR1_NR_0              (0x1UL << FMC_SDCR1_NR_Pos)                 /*!< 0x00000004 */
11262 #define FMC_SDCR1_NR_1              (0x2UL << FMC_SDCR1_NR_Pos)                 /*!< 0x00000008 */
11263 
11264 #define FMC_SDCR1_MWID_Pos          (4U)
11265 #define FMC_SDCR1_MWID_Msk          (0x3UL << FMC_SDCR1_MWID_Pos)               /*!< 0x00000030 */
11266 #define FMC_SDCR1_MWID              FMC_SDCR1_MWID_Msk                         /*!<NR[1:0] bits (Number of row bits) */
11267 #define FMC_SDCR1_MWID_0            (0x1UL << FMC_SDCR1_MWID_Pos)               /*!< 0x00000010 */
11268 #define FMC_SDCR1_MWID_1            (0x2UL << FMC_SDCR1_MWID_Pos)               /*!< 0x00000020 */
11269 
11270 #define FMC_SDCR1_NB_Pos            (6U)
11271 #define FMC_SDCR1_NB_Msk            (0x1UL << FMC_SDCR1_NB_Pos)                 /*!< 0x00000040 */
11272 #define FMC_SDCR1_NB                FMC_SDCR1_NB_Msk                           /*!<Number of internal bank */
11273 
11274 #define FMC_SDCR1_CAS_Pos           (7U)
11275 #define FMC_SDCR1_CAS_Msk           (0x3UL << FMC_SDCR1_CAS_Pos)                /*!< 0x00000180 */
11276 #define FMC_SDCR1_CAS               FMC_SDCR1_CAS_Msk                          /*!<CAS[1:0] bits (CAS latency) */
11277 #define FMC_SDCR1_CAS_0             (0x1UL << FMC_SDCR1_CAS_Pos)                /*!< 0x00000080 */
11278 #define FMC_SDCR1_CAS_1             (0x2UL << FMC_SDCR1_CAS_Pos)                /*!< 0x00000100 */
11279 
11280 #define FMC_SDCR1_WP_Pos            (9U)
11281 #define FMC_SDCR1_WP_Msk            (0x1UL << FMC_SDCR1_WP_Pos)                 /*!< 0x00000200 */
11282 #define FMC_SDCR1_WP                FMC_SDCR1_WP_Msk                           /*!<Write protection */
11283 
11284 #define FMC_SDCR1_SDCLK_Pos         (10U)
11285 #define FMC_SDCR1_SDCLK_Msk         (0x3UL << FMC_SDCR1_SDCLK_Pos)              /*!< 0x00000C00 */
11286 #define FMC_SDCR1_SDCLK             FMC_SDCR1_SDCLK_Msk                        /*!<SDRAM clock configuration */
11287 #define FMC_SDCR1_SDCLK_0           (0x1UL << FMC_SDCR1_SDCLK_Pos)              /*!< 0x00000400 */
11288 #define FMC_SDCR1_SDCLK_1           (0x2UL << FMC_SDCR1_SDCLK_Pos)              /*!< 0x00000800 */
11289 
11290 #define FMC_SDCR1_RBURST_Pos        (12U)
11291 #define FMC_SDCR1_RBURST_Msk        (0x1UL << FMC_SDCR1_RBURST_Pos)             /*!< 0x00001000 */
11292 #define FMC_SDCR1_RBURST            FMC_SDCR1_RBURST_Msk                       /*!<Read burst */
11293 
11294 #define FMC_SDCR1_RPIPE_Pos         (13U)
11295 #define FMC_SDCR1_RPIPE_Msk         (0x3UL << FMC_SDCR1_RPIPE_Pos)              /*!< 0x00006000 */
11296 #define FMC_SDCR1_RPIPE             FMC_SDCR1_RPIPE_Msk                        /*!<Write protection */
11297 #define FMC_SDCR1_RPIPE_0           (0x1UL << FMC_SDCR1_RPIPE_Pos)              /*!< 0x00002000 */
11298 #define FMC_SDCR1_RPIPE_1           (0x2UL << FMC_SDCR1_RPIPE_Pos)              /*!< 0x00004000 */
11299 
11300 /******************  Bit definition for FMC_SDCR2 register  ******************/
11301 #define FMC_SDCR2_NC_Pos            (0U)
11302 #define FMC_SDCR2_NC_Msk            (0x3UL << FMC_SDCR2_NC_Pos)                 /*!< 0x00000003 */
11303 #define FMC_SDCR2_NC                FMC_SDCR2_NC_Msk                           /*!<NC[1:0] bits (Number of column bits) */
11304 #define FMC_SDCR2_NC_0              (0x1UL << FMC_SDCR2_NC_Pos)                 /*!< 0x00000001 */
11305 #define FMC_SDCR2_NC_1              (0x2UL << FMC_SDCR2_NC_Pos)                 /*!< 0x00000002 */
11306 
11307 #define FMC_SDCR2_NR_Pos            (2U)
11308 #define FMC_SDCR2_NR_Msk            (0x3UL << FMC_SDCR2_NR_Pos)                 /*!< 0x0000000C */
11309 #define FMC_SDCR2_NR                FMC_SDCR2_NR_Msk                           /*!<NR[1:0] bits (Number of row bits) */
11310 #define FMC_SDCR2_NR_0              (0x1UL << FMC_SDCR2_NR_Pos)                 /*!< 0x00000004 */
11311 #define FMC_SDCR2_NR_1              (0x2UL << FMC_SDCR2_NR_Pos)                 /*!< 0x00000008 */
11312 
11313 #define FMC_SDCR2_MWID_Pos          (4U)
11314 #define FMC_SDCR2_MWID_Msk          (0x3UL << FMC_SDCR2_MWID_Pos)               /*!< 0x00000030 */
11315 #define FMC_SDCR2_MWID              FMC_SDCR2_MWID_Msk                         /*!<NR[1:0] bits (Number of row bits) */
11316 #define FMC_SDCR2_MWID_0            (0x1UL << FMC_SDCR2_MWID_Pos)               /*!< 0x00000010 */
11317 #define FMC_SDCR2_MWID_1            (0x2UL << FMC_SDCR2_MWID_Pos)               /*!< 0x00000020 */
11318 
11319 #define FMC_SDCR2_NB_Pos            (6U)
11320 #define FMC_SDCR2_NB_Msk            (0x1UL << FMC_SDCR2_NB_Pos)                 /*!< 0x00000040 */
11321 #define FMC_SDCR2_NB                FMC_SDCR2_NB_Msk                           /*!<Number of internal bank */
11322 
11323 #define FMC_SDCR2_CAS_Pos           (7U)
11324 #define FMC_SDCR2_CAS_Msk           (0x3UL << FMC_SDCR2_CAS_Pos)                /*!< 0x00000180 */
11325 #define FMC_SDCR2_CAS               FMC_SDCR2_CAS_Msk                          /*!<CAS[1:0] bits (CAS latency) */
11326 #define FMC_SDCR2_CAS_0             (0x1UL << FMC_SDCR2_CAS_Pos)                /*!< 0x00000080 */
11327 #define FMC_SDCR2_CAS_1             (0x2UL << FMC_SDCR2_CAS_Pos)                /*!< 0x00000100 */
11328 
11329 #define FMC_SDCR2_WP_Pos            (9U)
11330 #define FMC_SDCR2_WP_Msk            (0x1UL << FMC_SDCR2_WP_Pos)                 /*!< 0x00000200 */
11331 #define FMC_SDCR2_WP                FMC_SDCR2_WP_Msk                           /*!<Write protection */
11332 
11333 #define FMC_SDCR2_SDCLK_Pos         (10U)
11334 #define FMC_SDCR2_SDCLK_Msk         (0x3UL << FMC_SDCR2_SDCLK_Pos)              /*!< 0x00000C00 */
11335 #define FMC_SDCR2_SDCLK             FMC_SDCR2_SDCLK_Msk                        /*!<SDCLK[1:0] (SDRAM clock configuration) */
11336 #define FMC_SDCR2_SDCLK_0           (0x1UL << FMC_SDCR2_SDCLK_Pos)              /*!< 0x00000400 */
11337 #define FMC_SDCR2_SDCLK_1           (0x2UL << FMC_SDCR2_SDCLK_Pos)              /*!< 0x00000800 */
11338 
11339 #define FMC_SDCR2_RBURST_Pos        (12U)
11340 #define FMC_SDCR2_RBURST_Msk        (0x1UL << FMC_SDCR2_RBURST_Pos)             /*!< 0x00001000 */
11341 #define FMC_SDCR2_RBURST            FMC_SDCR2_RBURST_Msk                       /*!<Read burst */
11342 
11343 #define FMC_SDCR2_RPIPE_Pos         (13U)
11344 #define FMC_SDCR2_RPIPE_Msk         (0x3UL << FMC_SDCR2_RPIPE_Pos)              /*!< 0x00006000 */
11345 #define FMC_SDCR2_RPIPE             FMC_SDCR2_RPIPE_Msk                        /*!<RPIPE[1:0](Read pipe) */
11346 #define FMC_SDCR2_RPIPE_0           (0x1UL << FMC_SDCR2_RPIPE_Pos)              /*!< 0x00002000 */
11347 #define FMC_SDCR2_RPIPE_1           (0x2UL << FMC_SDCR2_RPIPE_Pos)              /*!< 0x00004000 */
11348 
11349 /******************  Bit definition for FMC_SDTR1 register  ******************/
11350 #define FMC_SDTR1_TMRD_Pos          (0U)
11351 #define FMC_SDTR1_TMRD_Msk          (0xFUL << FMC_SDTR1_TMRD_Pos)               /*!< 0x0000000F */
11352 #define FMC_SDTR1_TMRD              FMC_SDTR1_TMRD_Msk                         /*!<TMRD[3:0] bits (Load mode register to active) */
11353 #define FMC_SDTR1_TMRD_0            (0x1UL << FMC_SDTR1_TMRD_Pos)               /*!< 0x00000001 */
11354 #define FMC_SDTR1_TMRD_1            (0x2UL << FMC_SDTR1_TMRD_Pos)               /*!< 0x00000002 */
11355 #define FMC_SDTR1_TMRD_2            (0x4UL << FMC_SDTR1_TMRD_Pos)               /*!< 0x00000004 */
11356 #define FMC_SDTR1_TMRD_3            (0x8UL << FMC_SDTR1_TMRD_Pos)               /*!< 0x00000008 */
11357 
11358 #define FMC_SDTR1_TXSR_Pos          (4U)
11359 #define FMC_SDTR1_TXSR_Msk          (0xFUL << FMC_SDTR1_TXSR_Pos)               /*!< 0x000000F0 */
11360 #define FMC_SDTR1_TXSR              FMC_SDTR1_TXSR_Msk                         /*!<TXSR[3:0] bits (Exit self refresh) */
11361 #define FMC_SDTR1_TXSR_0            (0x1UL << FMC_SDTR1_TXSR_Pos)               /*!< 0x00000010 */
11362 #define FMC_SDTR1_TXSR_1            (0x2UL << FMC_SDTR1_TXSR_Pos)               /*!< 0x00000020 */
11363 #define FMC_SDTR1_TXSR_2            (0x4UL << FMC_SDTR1_TXSR_Pos)               /*!< 0x00000040 */
11364 #define FMC_SDTR1_TXSR_3            (0x8UL << FMC_SDTR1_TXSR_Pos)               /*!< 0x00000080 */
11365 
11366 #define FMC_SDTR1_TRAS_Pos          (8U)
11367 #define FMC_SDTR1_TRAS_Msk          (0xFUL << FMC_SDTR1_TRAS_Pos)               /*!< 0x00000F00 */
11368 #define FMC_SDTR1_TRAS              FMC_SDTR1_TRAS_Msk                         /*!<TRAS[3:0] bits (Self refresh time) */
11369 #define FMC_SDTR1_TRAS_0            (0x1UL << FMC_SDTR1_TRAS_Pos)               /*!< 0x00000100 */
11370 #define FMC_SDTR1_TRAS_1            (0x2UL << FMC_SDTR1_TRAS_Pos)               /*!< 0x00000200 */
11371 #define FMC_SDTR1_TRAS_2            (0x4UL << FMC_SDTR1_TRAS_Pos)               /*!< 0x00000400 */
11372 #define FMC_SDTR1_TRAS_3            (0x8UL << FMC_SDTR1_TRAS_Pos)               /*!< 0x00000800 */
11373 
11374 #define FMC_SDTR1_TRC_Pos           (12U)
11375 #define FMC_SDTR1_TRC_Msk           (0xFUL << FMC_SDTR1_TRC_Pos)                /*!< 0x0000F000 */
11376 #define FMC_SDTR1_TRC               FMC_SDTR1_TRC_Msk                          /*!<TRC[2:0] bits (Row cycle delay) */
11377 #define FMC_SDTR1_TRC_0             (0x1UL << FMC_SDTR1_TRC_Pos)                /*!< 0x00001000 */
11378 #define FMC_SDTR1_TRC_1             (0x2UL << FMC_SDTR1_TRC_Pos)                /*!< 0x00002000 */
11379 #define FMC_SDTR1_TRC_2             (0x4UL << FMC_SDTR1_TRC_Pos)                /*!< 0x00004000 */
11380 
11381 #define FMC_SDTR1_TWR_Pos           (16U)
11382 #define FMC_SDTR1_TWR_Msk           (0xFUL << FMC_SDTR1_TWR_Pos)                /*!< 0x000F0000 */
11383 #define FMC_SDTR1_TWR               FMC_SDTR1_TWR_Msk                          /*!<TRC[2:0] bits (Write recovery delay) */
11384 #define FMC_SDTR1_TWR_0             (0x1UL << FMC_SDTR1_TWR_Pos)                /*!< 0x00010000 */
11385 #define FMC_SDTR1_TWR_1             (0x2UL << FMC_SDTR1_TWR_Pos)                /*!< 0x00020000 */
11386 #define FMC_SDTR1_TWR_2             (0x4UL << FMC_SDTR1_TWR_Pos)                /*!< 0x00040000 */
11387 
11388 #define FMC_SDTR1_TRP_Pos           (20U)
11389 #define FMC_SDTR1_TRP_Msk           (0xFUL << FMC_SDTR1_TRP_Pos)                /*!< 0x00F00000 */
11390 #define FMC_SDTR1_TRP               FMC_SDTR1_TRP_Msk                          /*!<TRP[2:0] bits (Row precharge delay) */
11391 #define FMC_SDTR1_TRP_0             (0x1UL << FMC_SDTR1_TRP_Pos)                /*!< 0x00100000 */
11392 #define FMC_SDTR1_TRP_1             (0x2UL << FMC_SDTR1_TRP_Pos)                /*!< 0x00200000 */
11393 #define FMC_SDTR1_TRP_2             (0x4UL << FMC_SDTR1_TRP_Pos)                /*!< 0x00400000 */
11394 
11395 #define FMC_SDTR1_TRCD_Pos          (24U)
11396 #define FMC_SDTR1_TRCD_Msk          (0xFUL << FMC_SDTR1_TRCD_Pos)               /*!< 0x0F000000 */
11397 #define FMC_SDTR1_TRCD              FMC_SDTR1_TRCD_Msk                         /*!<TRP[2:0] bits (Row to column delay) */
11398 #define FMC_SDTR1_TRCD_0            (0x1UL << FMC_SDTR1_TRCD_Pos)               /*!< 0x01000000 */
11399 #define FMC_SDTR1_TRCD_1            (0x2UL << FMC_SDTR1_TRCD_Pos)               /*!< 0x02000000 */
11400 #define FMC_SDTR1_TRCD_2            (0x4UL << FMC_SDTR1_TRCD_Pos)               /*!< 0x04000000 */
11401 
11402 /******************  Bit definition for FMC_SDTR2 register  ******************/
11403 #define FMC_SDTR2_TMRD_Pos          (0U)
11404 #define FMC_SDTR2_TMRD_Msk          (0xFUL << FMC_SDTR2_TMRD_Pos)               /*!< 0x0000000F */
11405 #define FMC_SDTR2_TMRD              FMC_SDTR2_TMRD_Msk                         /*!<TMRD[3:0] bits (Load mode register to active) */
11406 #define FMC_SDTR2_TMRD_0            (0x1UL << FMC_SDTR2_TMRD_Pos)               /*!< 0x00000001 */
11407 #define FMC_SDTR2_TMRD_1            (0x2UL << FMC_SDTR2_TMRD_Pos)               /*!< 0x00000002 */
11408 #define FMC_SDTR2_TMRD_2            (0x4UL << FMC_SDTR2_TMRD_Pos)               /*!< 0x00000004 */
11409 #define FMC_SDTR2_TMRD_3            (0x8UL << FMC_SDTR2_TMRD_Pos)               /*!< 0x00000008 */
11410 
11411 #define FMC_SDTR2_TXSR_Pos          (4U)
11412 #define FMC_SDTR2_TXSR_Msk          (0xFUL << FMC_SDTR2_TXSR_Pos)               /*!< 0x000000F0 */
11413 #define FMC_SDTR2_TXSR              FMC_SDTR2_TXSR_Msk                         /*!<TXSR[3:0] bits (Exit self refresh) */
11414 #define FMC_SDTR2_TXSR_0            (0x1UL << FMC_SDTR2_TXSR_Pos)               /*!< 0x00000010 */
11415 #define FMC_SDTR2_TXSR_1            (0x2UL << FMC_SDTR2_TXSR_Pos)               /*!< 0x00000020 */
11416 #define FMC_SDTR2_TXSR_2            (0x4UL << FMC_SDTR2_TXSR_Pos)               /*!< 0x00000040 */
11417 #define FMC_SDTR2_TXSR_3            (0x8UL << FMC_SDTR2_TXSR_Pos)               /*!< 0x00000080 */
11418 
11419 #define FMC_SDTR2_TRAS_Pos          (8U)
11420 #define FMC_SDTR2_TRAS_Msk          (0xFUL << FMC_SDTR2_TRAS_Pos)               /*!< 0x00000F00 */
11421 #define FMC_SDTR2_TRAS              FMC_SDTR2_TRAS_Msk                         /*!<TRAS[3:0] bits (Self refresh time) */
11422 #define FMC_SDTR2_TRAS_0            (0x1UL << FMC_SDTR2_TRAS_Pos)               /*!< 0x00000100 */
11423 #define FMC_SDTR2_TRAS_1            (0x2UL << FMC_SDTR2_TRAS_Pos)               /*!< 0x00000200 */
11424 #define FMC_SDTR2_TRAS_2            (0x4UL << FMC_SDTR2_TRAS_Pos)               /*!< 0x00000400 */
11425 #define FMC_SDTR2_TRAS_3            (0x8UL << FMC_SDTR2_TRAS_Pos)               /*!< 0x00000800 */
11426 
11427 #define FMC_SDTR2_TRC_Pos           (12U)
11428 #define FMC_SDTR2_TRC_Msk           (0xFUL << FMC_SDTR2_TRC_Pos)                /*!< 0x0000F000 */
11429 #define FMC_SDTR2_TRC               FMC_SDTR2_TRC_Msk                          /*!<TRC[2:0] bits (Row cycle delay) */
11430 #define FMC_SDTR2_TRC_0             (0x1UL << FMC_SDTR2_TRC_Pos)                /*!< 0x00001000 */
11431 #define FMC_SDTR2_TRC_1             (0x2UL << FMC_SDTR2_TRC_Pos)                /*!< 0x00002000 */
11432 #define FMC_SDTR2_TRC_2             (0x4UL << FMC_SDTR2_TRC_Pos)                /*!< 0x00004000 */
11433 
11434 #define FMC_SDTR2_TWR_Pos           (16U)
11435 #define FMC_SDTR2_TWR_Msk           (0xFUL << FMC_SDTR2_TWR_Pos)                /*!< 0x000F0000 */
11436 #define FMC_SDTR2_TWR               FMC_SDTR2_TWR_Msk                          /*!<TRC[2:0] bits (Write recovery delay) */
11437 #define FMC_SDTR2_TWR_0             (0x1UL << FMC_SDTR2_TWR_Pos)                /*!< 0x00010000 */
11438 #define FMC_SDTR2_TWR_1             (0x2UL << FMC_SDTR2_TWR_Pos)                /*!< 0x00020000 */
11439 #define FMC_SDTR2_TWR_2             (0x4UL << FMC_SDTR2_TWR_Pos)                /*!< 0x00040000 */
11440 
11441 #define FMC_SDTR2_TRP_Pos           (20U)
11442 #define FMC_SDTR2_TRP_Msk           (0xFUL << FMC_SDTR2_TRP_Pos)                /*!< 0x00F00000 */
11443 #define FMC_SDTR2_TRP               FMC_SDTR2_TRP_Msk                          /*!<TRP[2:0] bits (Row precharge delay) */
11444 #define FMC_SDTR2_TRP_0             (0x1UL << FMC_SDTR2_TRP_Pos)                /*!< 0x00100000 */
11445 #define FMC_SDTR2_TRP_1             (0x2UL << FMC_SDTR2_TRP_Pos)                /*!< 0x00200000 */
11446 #define FMC_SDTR2_TRP_2             (0x4UL << FMC_SDTR2_TRP_Pos)                /*!< 0x00400000 */
11447 
11448 #define FMC_SDTR2_TRCD_Pos          (24U)
11449 #define FMC_SDTR2_TRCD_Msk          (0xFUL << FMC_SDTR2_TRCD_Pos)               /*!< 0x0F000000 */
11450 #define FMC_SDTR2_TRCD              FMC_SDTR2_TRCD_Msk                         /*!<TRP[2:0] bits (Row to column delay) */
11451 #define FMC_SDTR2_TRCD_0            (0x1UL << FMC_SDTR2_TRCD_Pos)               /*!< 0x01000000 */
11452 #define FMC_SDTR2_TRCD_1            (0x2UL << FMC_SDTR2_TRCD_Pos)               /*!< 0x02000000 */
11453 #define FMC_SDTR2_TRCD_2            (0x4UL << FMC_SDTR2_TRCD_Pos)               /*!< 0x04000000 */
11454 
11455 /******************  Bit definition for FMC_SDCMR register  ******************/
11456 #define FMC_SDCMR_MODE_Pos          (0U)
11457 #define FMC_SDCMR_MODE_Msk          (0x7UL << FMC_SDCMR_MODE_Pos)               /*!< 0x00000007 */
11458 #define FMC_SDCMR_MODE              FMC_SDCMR_MODE_Msk                         /*!<MODE[2:0] bits (Command mode) */
11459 #define FMC_SDCMR_MODE_0            (0x1UL << FMC_SDCMR_MODE_Pos)               /*!< 0x00000001 */
11460 #define FMC_SDCMR_MODE_1            (0x2UL << FMC_SDCMR_MODE_Pos)               /*!< 0x00000002 */
11461 #define FMC_SDCMR_MODE_2            (0x4UL << FMC_SDCMR_MODE_Pos)               /*!< 0x00000004 */
11462 
11463 #define FMC_SDCMR_CTB2_Pos          (3U)
11464 #define FMC_SDCMR_CTB2_Msk          (0x1UL << FMC_SDCMR_CTB2_Pos)               /*!< 0x00000008 */
11465 #define FMC_SDCMR_CTB2              FMC_SDCMR_CTB2_Msk                         /*!<Command target 2 */
11466 
11467 #define FMC_SDCMR_CTB1_Pos          (4U)
11468 #define FMC_SDCMR_CTB1_Msk          (0x1UL << FMC_SDCMR_CTB1_Pos)               /*!< 0x00000010 */
11469 #define FMC_SDCMR_CTB1              FMC_SDCMR_CTB1_Msk                         /*!<Command target 1 */
11470 
11471 #define FMC_SDCMR_NRFS_Pos          (5U)
11472 #define FMC_SDCMR_NRFS_Msk          (0xFUL << FMC_SDCMR_NRFS_Pos)               /*!< 0x000001E0 */
11473 #define FMC_SDCMR_NRFS              FMC_SDCMR_NRFS_Msk                         /*!<NRFS[3:0] bits (Number of auto-refresh) */
11474 #define FMC_SDCMR_NRFS_0            (0x1UL << FMC_SDCMR_NRFS_Pos)               /*!< 0x00000020 */
11475 #define FMC_SDCMR_NRFS_1            (0x2UL << FMC_SDCMR_NRFS_Pos)               /*!< 0x00000040 */
11476 #define FMC_SDCMR_NRFS_2            (0x4UL << FMC_SDCMR_NRFS_Pos)               /*!< 0x00000080 */
11477 #define FMC_SDCMR_NRFS_3            (0x8UL << FMC_SDCMR_NRFS_Pos)               /*!< 0x00000100 */
11478 
11479 #define FMC_SDCMR_MRD_Pos           (9U)
11480 #define FMC_SDCMR_MRD_Msk           (0x1FFFUL << FMC_SDCMR_MRD_Pos)             /*!< 0x003FFE00 */
11481 #define FMC_SDCMR_MRD               FMC_SDCMR_MRD_Msk                          /*!<MRD[12:0] bits (Mode register definition) */
11482 
11483 /******************  Bit definition for FMC_SDRTR register  ******************/
11484 #define FMC_SDRTR_CRE_Pos           (0U)
11485 #define FMC_SDRTR_CRE_Msk           (0x1UL << FMC_SDRTR_CRE_Pos)                /*!< 0x00000001 */
11486 #define FMC_SDRTR_CRE               FMC_SDRTR_CRE_Msk                          /*!<Clear refresh error flag */
11487 
11488 #define FMC_SDRTR_COUNT_Pos         (1U)
11489 #define FMC_SDRTR_COUNT_Msk         (0x1FFFUL << FMC_SDRTR_COUNT_Pos)           /*!< 0x00003FFE */
11490 #define FMC_SDRTR_COUNT             FMC_SDRTR_COUNT_Msk                        /*!<COUNT[12:0] bits (Refresh timer count) */
11491 
11492 #define FMC_SDRTR_REIE_Pos          (14U)
11493 #define FMC_SDRTR_REIE_Msk          (0x1UL << FMC_SDRTR_REIE_Pos)               /*!< 0x00004000 */
11494 #define FMC_SDRTR_REIE              FMC_SDRTR_REIE_Msk                         /*!<RES interupt enable */
11495 
11496 /******************  Bit definition for FMC_SDSR register  ******************/
11497 #define FMC_SDSR_RE_Pos             (0U)
11498 #define FMC_SDSR_RE_Msk             (0x1UL << FMC_SDSR_RE_Pos)                  /*!< 0x00000001 */
11499 #define FMC_SDSR_RE                 FMC_SDSR_RE_Msk                            /*!<Refresh error flag */
11500 
11501 #define FMC_SDSR_MODES1_Pos         (1U)
11502 #define FMC_SDSR_MODES1_Msk         (0x3UL << FMC_SDSR_MODES1_Pos)              /*!< 0x00000006 */
11503 #define FMC_SDSR_MODES1             FMC_SDSR_MODES1_Msk                        /*!<MODES1[1:0]bits (Status mode for bank 1) */
11504 #define FMC_SDSR_MODES1_0           (0x1UL << FMC_SDSR_MODES1_Pos)              /*!< 0x00000002 */
11505 #define FMC_SDSR_MODES1_1           (0x2UL << FMC_SDSR_MODES1_Pos)              /*!< 0x00000004 */
11506 
11507 #define FMC_SDSR_MODES2_Pos         (3U)
11508 #define FMC_SDSR_MODES2_Msk         (0x3UL << FMC_SDSR_MODES2_Pos)              /*!< 0x00000018 */
11509 #define FMC_SDSR_MODES2             FMC_SDSR_MODES2_Msk                        /*!<MODES2[1:0]bits (Status mode for bank 2) */
11510 #define FMC_SDSR_MODES2_0           (0x1UL << FMC_SDSR_MODES2_Pos)              /*!< 0x00000008 */
11511 #define FMC_SDSR_MODES2_1           (0x2UL << FMC_SDSR_MODES2_Pos)              /*!< 0x00000010 */
11512 #define FMC_SDSR_BUSY_Pos           (5U)
11513 #define FMC_SDSR_BUSY_Msk           (0x1UL << FMC_SDSR_BUSY_Pos)                /*!< 0x00000020 */
11514 #define FMC_SDSR_BUSY               FMC_SDSR_BUSY_Msk                          /*!<Busy status */
11515 
11516 /******************************************************************************/
11517 /*                                                                            */
11518 /*                            General Purpose I/O                             */
11519 /*                                                                            */
11520 /******************************************************************************/
11521 /******************  Bits definition for GPIO_MODER register  *****************/
11522 #define GPIO_MODER_MODER0_Pos            (0U)
11523 #define GPIO_MODER_MODER0_Msk            (0x3UL << GPIO_MODER_MODER0_Pos)       /*!< 0x00000003 */
11524 #define GPIO_MODER_MODER0                GPIO_MODER_MODER0_Msk
11525 #define GPIO_MODER_MODER0_0              (0x1UL << GPIO_MODER_MODER0_Pos)       /*!< 0x00000001 */
11526 #define GPIO_MODER_MODER0_1              (0x2UL << GPIO_MODER_MODER0_Pos)       /*!< 0x00000002 */
11527 #define GPIO_MODER_MODER1_Pos            (2U)
11528 #define GPIO_MODER_MODER1_Msk            (0x3UL << GPIO_MODER_MODER1_Pos)       /*!< 0x0000000C */
11529 #define GPIO_MODER_MODER1                GPIO_MODER_MODER1_Msk
11530 #define GPIO_MODER_MODER1_0              (0x1UL << GPIO_MODER_MODER1_Pos)       /*!< 0x00000004 */
11531 #define GPIO_MODER_MODER1_1              (0x2UL << GPIO_MODER_MODER1_Pos)       /*!< 0x00000008 */
11532 #define GPIO_MODER_MODER2_Pos            (4U)
11533 #define GPIO_MODER_MODER2_Msk            (0x3UL << GPIO_MODER_MODER2_Pos)       /*!< 0x00000030 */
11534 #define GPIO_MODER_MODER2                GPIO_MODER_MODER2_Msk
11535 #define GPIO_MODER_MODER2_0              (0x1UL << GPIO_MODER_MODER2_Pos)       /*!< 0x00000010 */
11536 #define GPIO_MODER_MODER2_1              (0x2UL << GPIO_MODER_MODER2_Pos)       /*!< 0x00000020 */
11537 #define GPIO_MODER_MODER3_Pos            (6U)
11538 #define GPIO_MODER_MODER3_Msk            (0x3UL << GPIO_MODER_MODER3_Pos)       /*!< 0x000000C0 */
11539 #define GPIO_MODER_MODER3                GPIO_MODER_MODER3_Msk
11540 #define GPIO_MODER_MODER3_0              (0x1UL << GPIO_MODER_MODER3_Pos)       /*!< 0x00000040 */
11541 #define GPIO_MODER_MODER3_1              (0x2UL << GPIO_MODER_MODER3_Pos)       /*!< 0x00000080 */
11542 #define GPIO_MODER_MODER4_Pos            (8U)
11543 #define GPIO_MODER_MODER4_Msk            (0x3UL << GPIO_MODER_MODER4_Pos)       /*!< 0x00000300 */
11544 #define GPIO_MODER_MODER4                GPIO_MODER_MODER4_Msk
11545 #define GPIO_MODER_MODER4_0              (0x1UL << GPIO_MODER_MODER4_Pos)       /*!< 0x00000100 */
11546 #define GPIO_MODER_MODER4_1              (0x2UL << GPIO_MODER_MODER4_Pos)       /*!< 0x00000200 */
11547 #define GPIO_MODER_MODER5_Pos            (10U)
11548 #define GPIO_MODER_MODER5_Msk            (0x3UL << GPIO_MODER_MODER5_Pos)       /*!< 0x00000C00 */
11549 #define GPIO_MODER_MODER5                GPIO_MODER_MODER5_Msk
11550 #define GPIO_MODER_MODER5_0              (0x1UL << GPIO_MODER_MODER5_Pos)       /*!< 0x00000400 */
11551 #define GPIO_MODER_MODER5_1              (0x2UL << GPIO_MODER_MODER5_Pos)       /*!< 0x00000800 */
11552 #define GPIO_MODER_MODER6_Pos            (12U)
11553 #define GPIO_MODER_MODER6_Msk            (0x3UL << GPIO_MODER_MODER6_Pos)       /*!< 0x00003000 */
11554 #define GPIO_MODER_MODER6                GPIO_MODER_MODER6_Msk
11555 #define GPIO_MODER_MODER6_0              (0x1UL << GPIO_MODER_MODER6_Pos)       /*!< 0x00001000 */
11556 #define GPIO_MODER_MODER6_1              (0x2UL << GPIO_MODER_MODER6_Pos)       /*!< 0x00002000 */
11557 #define GPIO_MODER_MODER7_Pos            (14U)
11558 #define GPIO_MODER_MODER7_Msk            (0x3UL << GPIO_MODER_MODER7_Pos)       /*!< 0x0000C000 */
11559 #define GPIO_MODER_MODER7                GPIO_MODER_MODER7_Msk
11560 #define GPIO_MODER_MODER7_0              (0x1UL << GPIO_MODER_MODER7_Pos)       /*!< 0x00004000 */
11561 #define GPIO_MODER_MODER7_1              (0x2UL << GPIO_MODER_MODER7_Pos)       /*!< 0x00008000 */
11562 #define GPIO_MODER_MODER8_Pos            (16U)
11563 #define GPIO_MODER_MODER8_Msk            (0x3UL << GPIO_MODER_MODER8_Pos)       /*!< 0x00030000 */
11564 #define GPIO_MODER_MODER8                GPIO_MODER_MODER8_Msk
11565 #define GPIO_MODER_MODER8_0              (0x1UL << GPIO_MODER_MODER8_Pos)       /*!< 0x00010000 */
11566 #define GPIO_MODER_MODER8_1              (0x2UL << GPIO_MODER_MODER8_Pos)       /*!< 0x00020000 */
11567 #define GPIO_MODER_MODER9_Pos            (18U)
11568 #define GPIO_MODER_MODER9_Msk            (0x3UL << GPIO_MODER_MODER9_Pos)       /*!< 0x000C0000 */
11569 #define GPIO_MODER_MODER9                GPIO_MODER_MODER9_Msk
11570 #define GPIO_MODER_MODER9_0              (0x1UL << GPIO_MODER_MODER9_Pos)       /*!< 0x00040000 */
11571 #define GPIO_MODER_MODER9_1              (0x2UL << GPIO_MODER_MODER9_Pos)       /*!< 0x00080000 */
11572 #define GPIO_MODER_MODER10_Pos           (20U)
11573 #define GPIO_MODER_MODER10_Msk           (0x3UL << GPIO_MODER_MODER10_Pos)      /*!< 0x00300000 */
11574 #define GPIO_MODER_MODER10               GPIO_MODER_MODER10_Msk
11575 #define GPIO_MODER_MODER10_0             (0x1UL << GPIO_MODER_MODER10_Pos)      /*!< 0x00100000 */
11576 #define GPIO_MODER_MODER10_1             (0x2UL << GPIO_MODER_MODER10_Pos)      /*!< 0x00200000 */
11577 #define GPIO_MODER_MODER11_Pos           (22U)
11578 #define GPIO_MODER_MODER11_Msk           (0x3UL << GPIO_MODER_MODER11_Pos)      /*!< 0x00C00000 */
11579 #define GPIO_MODER_MODER11               GPIO_MODER_MODER11_Msk
11580 #define GPIO_MODER_MODER11_0             (0x1UL << GPIO_MODER_MODER11_Pos)      /*!< 0x00400000 */
11581 #define GPIO_MODER_MODER11_1             (0x2UL << GPIO_MODER_MODER11_Pos)      /*!< 0x00800000 */
11582 #define GPIO_MODER_MODER12_Pos           (24U)
11583 #define GPIO_MODER_MODER12_Msk           (0x3UL << GPIO_MODER_MODER12_Pos)      /*!< 0x03000000 */
11584 #define GPIO_MODER_MODER12               GPIO_MODER_MODER12_Msk
11585 #define GPIO_MODER_MODER12_0             (0x1UL << GPIO_MODER_MODER12_Pos)      /*!< 0x01000000 */
11586 #define GPIO_MODER_MODER12_1             (0x2UL << GPIO_MODER_MODER12_Pos)      /*!< 0x02000000 */
11587 #define GPIO_MODER_MODER13_Pos           (26U)
11588 #define GPIO_MODER_MODER13_Msk           (0x3UL << GPIO_MODER_MODER13_Pos)      /*!< 0x0C000000 */
11589 #define GPIO_MODER_MODER13               GPIO_MODER_MODER13_Msk
11590 #define GPIO_MODER_MODER13_0             (0x1UL << GPIO_MODER_MODER13_Pos)      /*!< 0x04000000 */
11591 #define GPIO_MODER_MODER13_1             (0x2UL << GPIO_MODER_MODER13_Pos)      /*!< 0x08000000 */
11592 #define GPIO_MODER_MODER14_Pos           (28U)
11593 #define GPIO_MODER_MODER14_Msk           (0x3UL << GPIO_MODER_MODER14_Pos)      /*!< 0x30000000 */
11594 #define GPIO_MODER_MODER14               GPIO_MODER_MODER14_Msk
11595 #define GPIO_MODER_MODER14_0             (0x1UL << GPIO_MODER_MODER14_Pos)      /*!< 0x10000000 */
11596 #define GPIO_MODER_MODER14_1             (0x2UL << GPIO_MODER_MODER14_Pos)      /*!< 0x20000000 */
11597 #define GPIO_MODER_MODER15_Pos           (30U)
11598 #define GPIO_MODER_MODER15_Msk           (0x3UL << GPIO_MODER_MODER15_Pos)      /*!< 0xC0000000 */
11599 #define GPIO_MODER_MODER15               GPIO_MODER_MODER15_Msk
11600 #define GPIO_MODER_MODER15_0             (0x1UL << GPIO_MODER_MODER15_Pos)      /*!< 0x40000000 */
11601 #define GPIO_MODER_MODER15_1             (0x2UL << GPIO_MODER_MODER15_Pos)      /*!< 0x80000000 */
11602 
11603 /* Legacy defines */
11604 #define GPIO_MODER_MODE0_Pos             GPIO_MODER_MODER0_Pos
11605 #define GPIO_MODER_MODE0_Msk             GPIO_MODER_MODER0_Msk
11606 #define GPIO_MODER_MODE0                 GPIO_MODER_MODER0
11607 #define GPIO_MODER_MODE0_0               GPIO_MODER_MODER0_0
11608 #define GPIO_MODER_MODE0_1               GPIO_MODER_MODER0_1
11609 #define GPIO_MODER_MODE1_Pos             GPIO_MODER_MODER1_Pos
11610 #define GPIO_MODER_MODE1_Msk             GPIO_MODER_MODER1_Msk
11611 #define GPIO_MODER_MODE1                 GPIO_MODER_MODER1
11612 #define GPIO_MODER_MODE1_0               GPIO_MODER_MODER1_0
11613 #define GPIO_MODER_MODE1_1               GPIO_MODER_MODER1_1
11614 #define GPIO_MODER_MODE2_Pos             GPIO_MODER_MODER2_PoS
11615 #define GPIO_MODER_MODE2_Msk             GPIO_MODER_MODER2_Msk
11616 #define GPIO_MODER_MODE2                 GPIO_MODER_MODER2
11617 #define GPIO_MODER_MODE2_0               GPIO_MODER_MODER2_0
11618 #define GPIO_MODER_MODE2_1               GPIO_MODER_MODER2_1
11619 #define GPIO_MODER_MODE3_Pos             GPIO_MODER_MODER3_Pos
11620 #define GPIO_MODER_MODE3_Msk             GPIO_MODER_MODER3_Msk
11621 #define GPIO_MODER_MODE3                 GPIO_MODER_MODER3
11622 #define GPIO_MODER_MODE3_0               GPIO_MODER_MODER3_0
11623 #define GPIO_MODER_MODE3_1               GPIO_MODER_MODER3_1
11624 #define GPIO_MODER_MODE4_Pos             GPIO_MODER_MODER4_Pos
11625 #define GPIO_MODER_MODE4_Msk             GPIO_MODER_MODER4_Msk
11626 #define GPIO_MODER_MODE4                 GPIO_MODER_MODER4
11627 #define GPIO_MODER_MODE4_0               GPIO_MODER_MODER4_0
11628 #define GPIO_MODER_MODE4_1               GPIO_MODER_MODER4_1
11629 #define GPIO_MODER_MODE5_Pos             GPIO_MODER_MODER5_Pos
11630 #define GPIO_MODER_MODE5_Msk             GPIO_MODER_MODER5_Msk
11631 #define GPIO_MODER_MODE5                 GPIO_MODER_MODER5
11632 #define GPIO_MODER_MODE5_0               GPIO_MODER_MODER5_0
11633 #define GPIO_MODER_MODE5_1               GPIO_MODER_MODER5_1
11634 #define GPIO_MODER_MODE6_Pos             GPIO_MODER_MODER6_Pos
11635 #define GPIO_MODER_MODE6_Msk             GPIO_MODER_MODER6_Msk
11636 #define GPIO_MODER_MODE6                 GPIO_MODER_MODER6
11637 #define GPIO_MODER_MODE6_0               GPIO_MODER_MODER6_0
11638 #define GPIO_MODER_MODE6_1               GPIO_MODER_MODER6_1
11639 #define GPIO_MODER_MODE7_Pos             GPIO_MODER_MODER7_Pos
11640 #define GPIO_MODER_MODE7_Msk             GPIO_MODER_MODER7_Msk
11641 #define GPIO_MODER_MODE7                 GPIO_MODER_MODER7
11642 #define GPIO_MODER_MODE7_0               GPIO_MODER_MODER7_0
11643 #define GPIO_MODER_MODE7_1               GPIO_MODER_MODER7_1
11644 #define GPIO_MODER_MODE8_Pos             GPIO_MODER_MODER8_Pos
11645 #define GPIO_MODER_MODE8_Msk             GPIO_MODER_MODER2_Msk
11646 #define GPIO_MODER_MODE8                 GPIO_MODER_MODER8
11647 #define GPIO_MODER_MODE8_0               GPIO_MODER_MODER8_0
11648 #define GPIO_MODER_MODE8_1               GPIO_MODER_MODER8_1
11649 #define GPIO_MODER_MODE9_Pos             GPIO_MODER_MODER9_Pos
11650 #define GPIO_MODER_MODE9_Msk             GPIO_MODER_MODER9_Msk
11651 #define GPIO_MODER_MODE9                 GPIO_MODER_MODER9
11652 #define GPIO_MODER_MODE9_0               GPIO_MODER_MODER9_0
11653 #define GPIO_MODER_MODE9_1               GPIO_MODER_MODER9_1
11654 #define GPIO_MODER_MODE10_Pos            GPIO_MODER_MODER10_Pos
11655 #define GPIO_MODER_MODE10_Msk            GPIO_MODER_MODER10_Msk
11656 #define GPIO_MODER_MODE10                GPIO_MODER_MODER10
11657 #define GPIO_MODER_MODE10_0              GPIO_MODER_MODER10_0
11658 #define GPIO_MODER_MODE10_1              GPIO_MODER_MODER10_1
11659 #define GPIO_MODER_MODE11_Pos            GPIO_MODER_MODER11_Pos
11660 #define GPIO_MODER_MODE11_Msk            GPIO_MODER_MODER11_Msk
11661 #define GPIO_MODER_MODE11                GPIO_MODER_MODER11
11662 #define GPIO_MODER_MODE11_0              GPIO_MODER_MODER11_0
11663 #define GPIO_MODER_MODE11_1              GPIO_MODER_MODER11_1
11664 #define GPIO_MODER_MODE12_Pos            GPIO_MODER_MODER12_Pos
11665 #define GPIO_MODER_MODE12_Msk            GPIO_MODER_MODER12_Msk
11666 #define GPIO_MODER_MODE12                GPIO_MODER_MODER12
11667 #define GPIO_MODER_MODE12_0              GPIO_MODER_MODER12_0
11668 #define GPIO_MODER_MODE12_1              GPIO_MODER_MODER12_1
11669 #define GPIO_MODER_MODE13_Pos            GPIO_MODER_MODER13_Pos
11670 #define GPIO_MODER_MODE13_Msk            GPIO_MODER_MODER13_Msk
11671 #define GPIO_MODER_MODE13                GPIO_MODER_MODER13
11672 #define GPIO_MODER_MODE13_0              GPIO_MODER_MODER13_0
11673 #define GPIO_MODER_MODE13_1              GPIO_MODER_MODER13_1
11674 #define GPIO_MODER_MODE14_Pos            GPIO_MODER_MODER14_Pos
11675 #define GPIO_MODER_MODE14_Msk            GPIO_MODER_MODER14_Msk
11676 #define GPIO_MODER_MODE14                GPIO_MODER_MODER14
11677 #define GPIO_MODER_MODE14_0              GPIO_MODER_MODER14_0
11678 #define GPIO_MODER_MODE14_1              GPIO_MODER_MODER14_1
11679 #define GPIO_MODER_MODE15_Pos            GPIO_MODER_MODER15_Pos
11680 #define GPIO_MODER_MODE15_Msk            GPIO_MODER_MODER15_Msk
11681 #define GPIO_MODER_MODE15                GPIO_MODER_MODER15
11682 #define GPIO_MODER_MODE15_0              GPIO_MODER_MODER15_0
11683 #define GPIO_MODER_MODE15_1              GPIO_MODER_MODER15_1
11684 
11685 /******************  Bits definition for GPIO_OTYPER register  ****************/
11686 #define GPIO_OTYPER_OT0_Pos              (0U)
11687 #define GPIO_OTYPER_OT0_Msk              (0x1UL << GPIO_OTYPER_OT0_Pos)         /*!< 0x00000001 */
11688 #define GPIO_OTYPER_OT0                  GPIO_OTYPER_OT0_Msk
11689 #define GPIO_OTYPER_OT1_Pos              (1U)
11690 #define GPIO_OTYPER_OT1_Msk              (0x1UL << GPIO_OTYPER_OT1_Pos)         /*!< 0x00000002 */
11691 #define GPIO_OTYPER_OT1                  GPIO_OTYPER_OT1_Msk
11692 #define GPIO_OTYPER_OT2_Pos              (2U)
11693 #define GPIO_OTYPER_OT2_Msk              (0x1UL << GPIO_OTYPER_OT2_Pos)         /*!< 0x00000004 */
11694 #define GPIO_OTYPER_OT2                  GPIO_OTYPER_OT2_Msk
11695 #define GPIO_OTYPER_OT3_Pos              (3U)
11696 #define GPIO_OTYPER_OT3_Msk              (0x1UL << GPIO_OTYPER_OT3_Pos)         /*!< 0x00000008 */
11697 #define GPIO_OTYPER_OT3                  GPIO_OTYPER_OT3_Msk
11698 #define GPIO_OTYPER_OT4_Pos              (4U)
11699 #define GPIO_OTYPER_OT4_Msk              (0x1UL << GPIO_OTYPER_OT4_Pos)         /*!< 0x00000010 */
11700 #define GPIO_OTYPER_OT4                  GPIO_OTYPER_OT4_Msk
11701 #define GPIO_OTYPER_OT5_Pos              (5U)
11702 #define GPIO_OTYPER_OT5_Msk              (0x1UL << GPIO_OTYPER_OT5_Pos)         /*!< 0x00000020 */
11703 #define GPIO_OTYPER_OT5                  GPIO_OTYPER_OT5_Msk
11704 #define GPIO_OTYPER_OT6_Pos              (6U)
11705 #define GPIO_OTYPER_OT6_Msk              (0x1UL << GPIO_OTYPER_OT6_Pos)         /*!< 0x00000040 */
11706 #define GPIO_OTYPER_OT6                  GPIO_OTYPER_OT6_Msk
11707 #define GPIO_OTYPER_OT7_Pos              (7U)
11708 #define GPIO_OTYPER_OT7_Msk              (0x1UL << GPIO_OTYPER_OT7_Pos)         /*!< 0x00000080 */
11709 #define GPIO_OTYPER_OT7                  GPIO_OTYPER_OT7_Msk
11710 #define GPIO_OTYPER_OT8_Pos              (8U)
11711 #define GPIO_OTYPER_OT8_Msk              (0x1UL << GPIO_OTYPER_OT8_Pos)         /*!< 0x00000100 */
11712 #define GPIO_OTYPER_OT8                  GPIO_OTYPER_OT8_Msk
11713 #define GPIO_OTYPER_OT9_Pos              (9U)
11714 #define GPIO_OTYPER_OT9_Msk              (0x1UL << GPIO_OTYPER_OT9_Pos)         /*!< 0x00000200 */
11715 #define GPIO_OTYPER_OT9                  GPIO_OTYPER_OT9_Msk
11716 #define GPIO_OTYPER_OT10_Pos             (10U)
11717 #define GPIO_OTYPER_OT10_Msk             (0x1UL << GPIO_OTYPER_OT10_Pos)        /*!< 0x00000400 */
11718 #define GPIO_OTYPER_OT10                 GPIO_OTYPER_OT10_Msk
11719 #define GPIO_OTYPER_OT11_Pos             (11U)
11720 #define GPIO_OTYPER_OT11_Msk             (0x1UL << GPIO_OTYPER_OT11_Pos)        /*!< 0x00000800 */
11721 #define GPIO_OTYPER_OT11                 GPIO_OTYPER_OT11_Msk
11722 #define GPIO_OTYPER_OT12_Pos             (12U)
11723 #define GPIO_OTYPER_OT12_Msk             (0x1UL << GPIO_OTYPER_OT12_Pos)        /*!< 0x00001000 */
11724 #define GPIO_OTYPER_OT12                 GPIO_OTYPER_OT12_Msk
11725 #define GPIO_OTYPER_OT13_Pos             (13U)
11726 #define GPIO_OTYPER_OT13_Msk             (0x1UL << GPIO_OTYPER_OT13_Pos)        /*!< 0x00002000 */
11727 #define GPIO_OTYPER_OT13                 GPIO_OTYPER_OT13_Msk
11728 #define GPIO_OTYPER_OT14_Pos             (14U)
11729 #define GPIO_OTYPER_OT14_Msk             (0x1UL << GPIO_OTYPER_OT14_Pos)        /*!< 0x00004000 */
11730 #define GPIO_OTYPER_OT14                 GPIO_OTYPER_OT14_Msk
11731 #define GPIO_OTYPER_OT15_Pos             (15U)
11732 #define GPIO_OTYPER_OT15_Msk             (0x1UL << GPIO_OTYPER_OT15_Pos)        /*!< 0x00008000 */
11733 #define GPIO_OTYPER_OT15                 GPIO_OTYPER_OT15_Msk
11734 
11735 /* Legacy defines */
11736 #define GPIO_OTYPER_OT_0                 GPIO_OTYPER_OT0
11737 #define GPIO_OTYPER_OT_1                 GPIO_OTYPER_OT1
11738 #define GPIO_OTYPER_OT_2                 GPIO_OTYPER_OT2
11739 #define GPIO_OTYPER_OT_3                 GPIO_OTYPER_OT3
11740 #define GPIO_OTYPER_OT_4                 GPIO_OTYPER_OT4
11741 #define GPIO_OTYPER_OT_5                 GPIO_OTYPER_OT5
11742 #define GPIO_OTYPER_OT_6                 GPIO_OTYPER_OT6
11743 #define GPIO_OTYPER_OT_7                 GPIO_OTYPER_OT7
11744 #define GPIO_OTYPER_OT_8                 GPIO_OTYPER_OT8
11745 #define GPIO_OTYPER_OT_9                 GPIO_OTYPER_OT9
11746 #define GPIO_OTYPER_OT_10                GPIO_OTYPER_OT10
11747 #define GPIO_OTYPER_OT_11                GPIO_OTYPER_OT11
11748 #define GPIO_OTYPER_OT_12                GPIO_OTYPER_OT12
11749 #define GPIO_OTYPER_OT_13                GPIO_OTYPER_OT13
11750 #define GPIO_OTYPER_OT_14                GPIO_OTYPER_OT14
11751 #define GPIO_OTYPER_OT_15                GPIO_OTYPER_OT15
11752 
11753 /******************  Bits definition for GPIO_OSPEEDR register  ***************/
11754 #define GPIO_OSPEEDR_OSPEED0_Pos         (0U)
11755 #define GPIO_OSPEEDR_OSPEED0_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)    /*!< 0x00000003 */
11756 #define GPIO_OSPEEDR_OSPEED0             GPIO_OSPEEDR_OSPEED0_Msk
11757 #define GPIO_OSPEEDR_OSPEED0_0           (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)    /*!< 0x00000001 */
11758 #define GPIO_OSPEEDR_OSPEED0_1           (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)    /*!< 0x00000002 */
11759 #define GPIO_OSPEEDR_OSPEED1_Pos         (2U)
11760 #define GPIO_OSPEEDR_OSPEED1_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)    /*!< 0x0000000C */
11761 #define GPIO_OSPEEDR_OSPEED1             GPIO_OSPEEDR_OSPEED1_Msk
11762 #define GPIO_OSPEEDR_OSPEED1_0           (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)    /*!< 0x00000004 */
11763 #define GPIO_OSPEEDR_OSPEED1_1           (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)    /*!< 0x00000008 */
11764 #define GPIO_OSPEEDR_OSPEED2_Pos         (4U)
11765 #define GPIO_OSPEEDR_OSPEED2_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)    /*!< 0x00000030 */
11766 #define GPIO_OSPEEDR_OSPEED2             GPIO_OSPEEDR_OSPEED2_Msk
11767 #define GPIO_OSPEEDR_OSPEED2_0           (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)    /*!< 0x00000010 */
11768 #define GPIO_OSPEEDR_OSPEED2_1           (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)    /*!< 0x00000020 */
11769 #define GPIO_OSPEEDR_OSPEED3_Pos         (6U)
11770 #define GPIO_OSPEEDR_OSPEED3_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)    /*!< 0x000000C0 */
11771 #define GPIO_OSPEEDR_OSPEED3             GPIO_OSPEEDR_OSPEED3_Msk
11772 #define GPIO_OSPEEDR_OSPEED3_0           (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)    /*!< 0x00000040 */
11773 #define GPIO_OSPEEDR_OSPEED3_1           (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)    /*!< 0x00000080 */
11774 #define GPIO_OSPEEDR_OSPEED4_Pos         (8U)
11775 #define GPIO_OSPEEDR_OSPEED4_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)    /*!< 0x00000300 */
11776 #define GPIO_OSPEEDR_OSPEED4             GPIO_OSPEEDR_OSPEED4_Msk
11777 #define GPIO_OSPEEDR_OSPEED4_0           (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)    /*!< 0x00000100 */
11778 #define GPIO_OSPEEDR_OSPEED4_1           (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)    /*!< 0x00000200 */
11779 #define GPIO_OSPEEDR_OSPEED5_Pos         (10U)
11780 #define GPIO_OSPEEDR_OSPEED5_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)    /*!< 0x00000C00 */
11781 #define GPIO_OSPEEDR_OSPEED5             GPIO_OSPEEDR_OSPEED5_Msk
11782 #define GPIO_OSPEEDR_OSPEED5_0           (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)    /*!< 0x00000400 */
11783 #define GPIO_OSPEEDR_OSPEED5_1           (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)    /*!< 0x00000800 */
11784 #define GPIO_OSPEEDR_OSPEED6_Pos         (12U)
11785 #define GPIO_OSPEEDR_OSPEED6_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)    /*!< 0x00003000 */
11786 #define GPIO_OSPEEDR_OSPEED6             GPIO_OSPEEDR_OSPEED6_Msk
11787 #define GPIO_OSPEEDR_OSPEED6_0           (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)    /*!< 0x00001000 */
11788 #define GPIO_OSPEEDR_OSPEED6_1           (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)    /*!< 0x00002000 */
11789 #define GPIO_OSPEEDR_OSPEED7_Pos         (14U)
11790 #define GPIO_OSPEEDR_OSPEED7_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)    /*!< 0x0000C000 */
11791 #define GPIO_OSPEEDR_OSPEED7             GPIO_OSPEEDR_OSPEED7_Msk
11792 #define GPIO_OSPEEDR_OSPEED7_0           (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)    /*!< 0x00004000 */
11793 #define GPIO_OSPEEDR_OSPEED7_1           (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)    /*!< 0x00008000 */
11794 #define GPIO_OSPEEDR_OSPEED8_Pos         (16U)
11795 #define GPIO_OSPEEDR_OSPEED8_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)    /*!< 0x00030000 */
11796 #define GPIO_OSPEEDR_OSPEED8             GPIO_OSPEEDR_OSPEED8_Msk
11797 #define GPIO_OSPEEDR_OSPEED8_0           (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)    /*!< 0x00010000 */
11798 #define GPIO_OSPEEDR_OSPEED8_1           (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)    /*!< 0x00020000 */
11799 #define GPIO_OSPEEDR_OSPEED9_Pos         (18U)
11800 #define GPIO_OSPEEDR_OSPEED9_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)    /*!< 0x000C0000 */
11801 #define GPIO_OSPEEDR_OSPEED9             GPIO_OSPEEDR_OSPEED9_Msk
11802 #define GPIO_OSPEEDR_OSPEED9_0           (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)    /*!< 0x00040000 */
11803 #define GPIO_OSPEEDR_OSPEED9_1           (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)    /*!< 0x00080000 */
11804 #define GPIO_OSPEEDR_OSPEED10_Pos        (20U)
11805 #define GPIO_OSPEEDR_OSPEED10_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)   /*!< 0x00300000 */
11806 #define GPIO_OSPEEDR_OSPEED10            GPIO_OSPEEDR_OSPEED10_Msk
11807 #define GPIO_OSPEEDR_OSPEED10_0          (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)   /*!< 0x00100000 */
11808 #define GPIO_OSPEEDR_OSPEED10_1          (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)   /*!< 0x00200000 */
11809 #define GPIO_OSPEEDR_OSPEED11_Pos        (22U)
11810 #define GPIO_OSPEEDR_OSPEED11_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)   /*!< 0x00C00000 */
11811 #define GPIO_OSPEEDR_OSPEED11            GPIO_OSPEEDR_OSPEED11_Msk
11812 #define GPIO_OSPEEDR_OSPEED11_0          (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)   /*!< 0x00400000 */
11813 #define GPIO_OSPEEDR_OSPEED11_1          (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)   /*!< 0x00800000 */
11814 #define GPIO_OSPEEDR_OSPEED12_Pos        (24U)
11815 #define GPIO_OSPEEDR_OSPEED12_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)   /*!< 0x03000000 */
11816 #define GPIO_OSPEEDR_OSPEED12            GPIO_OSPEEDR_OSPEED12_Msk
11817 #define GPIO_OSPEEDR_OSPEED12_0          (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)   /*!< 0x01000000 */
11818 #define GPIO_OSPEEDR_OSPEED12_1          (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)   /*!< 0x02000000 */
11819 #define GPIO_OSPEEDR_OSPEED13_Pos        (26U)
11820 #define GPIO_OSPEEDR_OSPEED13_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)   /*!< 0x0C000000 */
11821 #define GPIO_OSPEEDR_OSPEED13            GPIO_OSPEEDR_OSPEED13_Msk
11822 #define GPIO_OSPEEDR_OSPEED13_0          (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)   /*!< 0x04000000 */
11823 #define GPIO_OSPEEDR_OSPEED13_1          (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)   /*!< 0x08000000 */
11824 #define GPIO_OSPEEDR_OSPEED14_Pos        (28U)
11825 #define GPIO_OSPEEDR_OSPEED14_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)   /*!< 0x30000000 */
11826 #define GPIO_OSPEEDR_OSPEED14            GPIO_OSPEEDR_OSPEED14_Msk
11827 #define GPIO_OSPEEDR_OSPEED14_0          (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)   /*!< 0x10000000 */
11828 #define GPIO_OSPEEDR_OSPEED14_1          (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)   /*!< 0x20000000 */
11829 #define GPIO_OSPEEDR_OSPEED15_Pos        (30U)
11830 #define GPIO_OSPEEDR_OSPEED15_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)   /*!< 0xC0000000 */
11831 #define GPIO_OSPEEDR_OSPEED15            GPIO_OSPEEDR_OSPEED15_Msk
11832 #define GPIO_OSPEEDR_OSPEED15_0          (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)   /*!< 0x40000000 */
11833 #define GPIO_OSPEEDR_OSPEED15_1          (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)   /*!< 0x80000000 */
11834 
11835 /* Legacy defines */
11836 #define GPIO_OSPEEDER_OSPEEDR0           GPIO_OSPEEDR_OSPEED0
11837 #define GPIO_OSPEEDER_OSPEEDR0_0         GPIO_OSPEEDR_OSPEED0_0
11838 #define GPIO_OSPEEDER_OSPEEDR0_1         GPIO_OSPEEDR_OSPEED0_1
11839 #define GPIO_OSPEEDER_OSPEEDR1           GPIO_OSPEEDR_OSPEED1
11840 #define GPIO_OSPEEDER_OSPEEDR1_0         GPIO_OSPEEDR_OSPEED1_0
11841 #define GPIO_OSPEEDER_OSPEEDR1_1         GPIO_OSPEEDR_OSPEED1_1
11842 #define GPIO_OSPEEDER_OSPEEDR2           GPIO_OSPEEDR_OSPEED2
11843 #define GPIO_OSPEEDER_OSPEEDR2_0         GPIO_OSPEEDR_OSPEED2_0
11844 #define GPIO_OSPEEDER_OSPEEDR2_1         GPIO_OSPEEDR_OSPEED2_1
11845 #define GPIO_OSPEEDER_OSPEEDR3           GPIO_OSPEEDR_OSPEED3
11846 #define GPIO_OSPEEDER_OSPEEDR3_0         GPIO_OSPEEDR_OSPEED3_0
11847 #define GPIO_OSPEEDER_OSPEEDR3_1         GPIO_OSPEEDR_OSPEED3_1
11848 #define GPIO_OSPEEDER_OSPEEDR4           GPIO_OSPEEDR_OSPEED4
11849 #define GPIO_OSPEEDER_OSPEEDR4_0         GPIO_OSPEEDR_OSPEED4_0
11850 #define GPIO_OSPEEDER_OSPEEDR4_1         GPIO_OSPEEDR_OSPEED4_1
11851 #define GPIO_OSPEEDER_OSPEEDR5           GPIO_OSPEEDR_OSPEED5
11852 #define GPIO_OSPEEDER_OSPEEDR5_0         GPIO_OSPEEDR_OSPEED5_0
11853 #define GPIO_OSPEEDER_OSPEEDR5_1         GPIO_OSPEEDR_OSPEED5_1
11854 #define GPIO_OSPEEDER_OSPEEDR6           GPIO_OSPEEDR_OSPEED6
11855 #define GPIO_OSPEEDER_OSPEEDR6_0         GPIO_OSPEEDR_OSPEED6_0
11856 #define GPIO_OSPEEDER_OSPEEDR6_1         GPIO_OSPEEDR_OSPEED6_1
11857 #define GPIO_OSPEEDER_OSPEEDR7           GPIO_OSPEEDR_OSPEED7
11858 #define GPIO_OSPEEDER_OSPEEDR7_0         GPIO_OSPEEDR_OSPEED7_0
11859 #define GPIO_OSPEEDER_OSPEEDR7_1         GPIO_OSPEEDR_OSPEED7_1
11860 #define GPIO_OSPEEDER_OSPEEDR8           GPIO_OSPEEDR_OSPEED8
11861 #define GPIO_OSPEEDER_OSPEEDR8_0         GPIO_OSPEEDR_OSPEED8_0
11862 #define GPIO_OSPEEDER_OSPEEDR8_1         GPIO_OSPEEDR_OSPEED8_1
11863 #define GPIO_OSPEEDER_OSPEEDR9           GPIO_OSPEEDR_OSPEED9
11864 #define GPIO_OSPEEDER_OSPEEDR9_0         GPIO_OSPEEDR_OSPEED9_0
11865 #define GPIO_OSPEEDER_OSPEEDR9_1         GPIO_OSPEEDR_OSPEED9_1
11866 #define GPIO_OSPEEDER_OSPEEDR10          GPIO_OSPEEDR_OSPEED10
11867 #define GPIO_OSPEEDER_OSPEEDR10_0        GPIO_OSPEEDR_OSPEED10_0
11868 #define GPIO_OSPEEDER_OSPEEDR10_1        GPIO_OSPEEDR_OSPEED10_1
11869 #define GPIO_OSPEEDER_OSPEEDR11          GPIO_OSPEEDR_OSPEED11
11870 #define GPIO_OSPEEDER_OSPEEDR11_0        GPIO_OSPEEDR_OSPEED11_0
11871 #define GPIO_OSPEEDER_OSPEEDR11_1        GPIO_OSPEEDR_OSPEED11_1
11872 #define GPIO_OSPEEDER_OSPEEDR12          GPIO_OSPEEDR_OSPEED12
11873 #define GPIO_OSPEEDER_OSPEEDR12_0        GPIO_OSPEEDR_OSPEED12_0
11874 #define GPIO_OSPEEDER_OSPEEDR12_1        GPIO_OSPEEDR_OSPEED12_1
11875 #define GPIO_OSPEEDER_OSPEEDR13          GPIO_OSPEEDR_OSPEED13
11876 #define GPIO_OSPEEDER_OSPEEDR13_0        GPIO_OSPEEDR_OSPEED13_0
11877 #define GPIO_OSPEEDER_OSPEEDR13_1        GPIO_OSPEEDR_OSPEED13_1
11878 #define GPIO_OSPEEDER_OSPEEDR14          GPIO_OSPEEDR_OSPEED14
11879 #define GPIO_OSPEEDER_OSPEEDR14_0        GPIO_OSPEEDR_OSPEED14_0
11880 #define GPIO_OSPEEDER_OSPEEDR14_1        GPIO_OSPEEDR_OSPEED14_1
11881 #define GPIO_OSPEEDER_OSPEEDR15          GPIO_OSPEEDR_OSPEED15
11882 #define GPIO_OSPEEDER_OSPEEDR15_0        GPIO_OSPEEDR_OSPEED15_0
11883 #define GPIO_OSPEEDER_OSPEEDR15_1        GPIO_OSPEEDR_OSPEED15_1
11884 
11885 /******************  Bits definition for GPIO_PUPDR register  *****************/
11886 #define GPIO_PUPDR_PUPD0_Pos             (0U)
11887 #define GPIO_PUPDR_PUPD0_Msk             (0x3UL << GPIO_PUPDR_PUPD0_Pos)        /*!< 0x00000003 */
11888 #define GPIO_PUPDR_PUPD0                 GPIO_PUPDR_PUPD0_Msk
11889 #define GPIO_PUPDR_PUPD0_0               (0x1UL << GPIO_PUPDR_PUPD0_Pos)        /*!< 0x00000001 */
11890 #define GPIO_PUPDR_PUPD0_1               (0x2UL << GPIO_PUPDR_PUPD0_Pos)        /*!< 0x00000002 */
11891 #define GPIO_PUPDR_PUPD1_Pos             (2U)
11892 #define GPIO_PUPDR_PUPD1_Msk             (0x3UL << GPIO_PUPDR_PUPD1_Pos)        /*!< 0x0000000C */
11893 #define GPIO_PUPDR_PUPD1                 GPIO_PUPDR_PUPD1_Msk
11894 #define GPIO_PUPDR_PUPD1_0               (0x1UL << GPIO_PUPDR_PUPD1_Pos)        /*!< 0x00000004 */
11895 #define GPIO_PUPDR_PUPD1_1               (0x2UL << GPIO_PUPDR_PUPD1_Pos)        /*!< 0x00000008 */
11896 #define GPIO_PUPDR_PUPD2_Pos             (4U)
11897 #define GPIO_PUPDR_PUPD2_Msk             (0x3UL << GPIO_PUPDR_PUPD2_Pos)        /*!< 0x00000030 */
11898 #define GPIO_PUPDR_PUPD2                 GPIO_PUPDR_PUPD2_Msk
11899 #define GPIO_PUPDR_PUPD2_0               (0x1UL << GPIO_PUPDR_PUPD2_Pos)        /*!< 0x00000010 */
11900 #define GPIO_PUPDR_PUPD2_1               (0x2UL << GPIO_PUPDR_PUPD2_Pos)        /*!< 0x00000020 */
11901 #define GPIO_PUPDR_PUPD3_Pos             (6U)
11902 #define GPIO_PUPDR_PUPD3_Msk             (0x3UL << GPIO_PUPDR_PUPD3_Pos)        /*!< 0x000000C0 */
11903 #define GPIO_PUPDR_PUPD3                 GPIO_PUPDR_PUPD3_Msk
11904 #define GPIO_PUPDR_PUPD3_0               (0x1UL << GPIO_PUPDR_PUPD3_Pos)        /*!< 0x00000040 */
11905 #define GPIO_PUPDR_PUPD3_1               (0x2UL << GPIO_PUPDR_PUPD3_Pos)        /*!< 0x00000080 */
11906 #define GPIO_PUPDR_PUPD4_Pos             (8U)
11907 #define GPIO_PUPDR_PUPD4_Msk             (0x3UL << GPIO_PUPDR_PUPD4_Pos)        /*!< 0x00000300 */
11908 #define GPIO_PUPDR_PUPD4                 GPIO_PUPDR_PUPD4_Msk
11909 #define GPIO_PUPDR_PUPD4_0               (0x1UL << GPIO_PUPDR_PUPD4_Pos)        /*!< 0x00000100 */
11910 #define GPIO_PUPDR_PUPD4_1               (0x2UL << GPIO_PUPDR_PUPD4_Pos)        /*!< 0x00000200 */
11911 #define GPIO_PUPDR_PUPD5_Pos             (10U)
11912 #define GPIO_PUPDR_PUPD5_Msk             (0x3UL << GPIO_PUPDR_PUPD5_Pos)        /*!< 0x00000C00 */
11913 #define GPIO_PUPDR_PUPD5                 GPIO_PUPDR_PUPD5_Msk
11914 #define GPIO_PUPDR_PUPD5_0               (0x1UL << GPIO_PUPDR_PUPD5_Pos)        /*!< 0x00000400 */
11915 #define GPIO_PUPDR_PUPD5_1               (0x2UL << GPIO_PUPDR_PUPD5_Pos)        /*!< 0x00000800 */
11916 #define GPIO_PUPDR_PUPD6_Pos             (12U)
11917 #define GPIO_PUPDR_PUPD6_Msk             (0x3UL << GPIO_PUPDR_PUPD6_Pos)        /*!< 0x00003000 */
11918 #define GPIO_PUPDR_PUPD6                 GPIO_PUPDR_PUPD6_Msk
11919 #define GPIO_PUPDR_PUPD6_0               (0x1UL << GPIO_PUPDR_PUPD6_Pos)        /*!< 0x00001000 */
11920 #define GPIO_PUPDR_PUPD6_1               (0x2UL << GPIO_PUPDR_PUPD6_Pos)        /*!< 0x00002000 */
11921 #define GPIO_PUPDR_PUPD7_Pos             (14U)
11922 #define GPIO_PUPDR_PUPD7_Msk             (0x3UL << GPIO_PUPDR_PUPD7_Pos)        /*!< 0x0000C000 */
11923 #define GPIO_PUPDR_PUPD7                 GPIO_PUPDR_PUPD7_Msk
11924 #define GPIO_PUPDR_PUPD7_0               (0x1UL << GPIO_PUPDR_PUPD7_Pos)        /*!< 0x00004000 */
11925 #define GPIO_PUPDR_PUPD7_1               (0x2UL << GPIO_PUPDR_PUPD7_Pos)        /*!< 0x00008000 */
11926 #define GPIO_PUPDR_PUPD8_Pos             (16U)
11927 #define GPIO_PUPDR_PUPD8_Msk             (0x3UL << GPIO_PUPDR_PUPD8_Pos)        /*!< 0x00030000 */
11928 #define GPIO_PUPDR_PUPD8                 GPIO_PUPDR_PUPD8_Msk
11929 #define GPIO_PUPDR_PUPD8_0               (0x1UL << GPIO_PUPDR_PUPD8_Pos)        /*!< 0x00010000 */
11930 #define GPIO_PUPDR_PUPD8_1               (0x2UL << GPIO_PUPDR_PUPD8_Pos)        /*!< 0x00020000 */
11931 #define GPIO_PUPDR_PUPD9_Pos             (18U)
11932 #define GPIO_PUPDR_PUPD9_Msk             (0x3UL << GPIO_PUPDR_PUPD9_Pos)        /*!< 0x000C0000 */
11933 #define GPIO_PUPDR_PUPD9                 GPIO_PUPDR_PUPD9_Msk
11934 #define GPIO_PUPDR_PUPD9_0               (0x1UL << GPIO_PUPDR_PUPD9_Pos)        /*!< 0x00040000 */
11935 #define GPIO_PUPDR_PUPD9_1               (0x2UL << GPIO_PUPDR_PUPD9_Pos)        /*!< 0x00080000 */
11936 #define GPIO_PUPDR_PUPD10_Pos            (20U)
11937 #define GPIO_PUPDR_PUPD10_Msk            (0x3UL << GPIO_PUPDR_PUPD10_Pos)       /*!< 0x00300000 */
11938 #define GPIO_PUPDR_PUPD10                GPIO_PUPDR_PUPD10_Msk
11939 #define GPIO_PUPDR_PUPD10_0              (0x1UL << GPIO_PUPDR_PUPD10_Pos)       /*!< 0x00100000 */
11940 #define GPIO_PUPDR_PUPD10_1              (0x2UL << GPIO_PUPDR_PUPD10_Pos)       /*!< 0x00200000 */
11941 #define GPIO_PUPDR_PUPD11_Pos            (22U)
11942 #define GPIO_PUPDR_PUPD11_Msk            (0x3UL << GPIO_PUPDR_PUPD11_Pos)       /*!< 0x00C00000 */
11943 #define GPIO_PUPDR_PUPD11                GPIO_PUPDR_PUPD11_Msk
11944 #define GPIO_PUPDR_PUPD11_0              (0x1UL << GPIO_PUPDR_PUPD11_Pos)       /*!< 0x00400000 */
11945 #define GPIO_PUPDR_PUPD11_1              (0x2UL << GPIO_PUPDR_PUPD11_Pos)       /*!< 0x00800000 */
11946 #define GPIO_PUPDR_PUPD12_Pos            (24U)
11947 #define GPIO_PUPDR_PUPD12_Msk            (0x3UL << GPIO_PUPDR_PUPD12_Pos)       /*!< 0x03000000 */
11948 #define GPIO_PUPDR_PUPD12                GPIO_PUPDR_PUPD12_Msk
11949 #define GPIO_PUPDR_PUPD12_0              (0x1UL << GPIO_PUPDR_PUPD12_Pos)       /*!< 0x01000000 */
11950 #define GPIO_PUPDR_PUPD12_1              (0x2UL << GPIO_PUPDR_PUPD12_Pos)       /*!< 0x02000000 */
11951 #define GPIO_PUPDR_PUPD13_Pos            (26U)
11952 #define GPIO_PUPDR_PUPD13_Msk            (0x3UL << GPIO_PUPDR_PUPD13_Pos)       /*!< 0x0C000000 */
11953 #define GPIO_PUPDR_PUPD13                GPIO_PUPDR_PUPD13_Msk
11954 #define GPIO_PUPDR_PUPD13_0              (0x1UL << GPIO_PUPDR_PUPD13_Pos)       /*!< 0x04000000 */
11955 #define GPIO_PUPDR_PUPD13_1              (0x2UL << GPIO_PUPDR_PUPD13_Pos)       /*!< 0x08000000 */
11956 #define GPIO_PUPDR_PUPD14_Pos            (28U)
11957 #define GPIO_PUPDR_PUPD14_Msk            (0x3UL << GPIO_PUPDR_PUPD14_Pos)       /*!< 0x30000000 */
11958 #define GPIO_PUPDR_PUPD14                GPIO_PUPDR_PUPD14_Msk
11959 #define GPIO_PUPDR_PUPD14_0              (0x1UL << GPIO_PUPDR_PUPD14_Pos)       /*!< 0x10000000 */
11960 #define GPIO_PUPDR_PUPD14_1              (0x2UL << GPIO_PUPDR_PUPD14_Pos)       /*!< 0x20000000 */
11961 #define GPIO_PUPDR_PUPD15_Pos            (30U)
11962 #define GPIO_PUPDR_PUPD15_Msk            (0x3UL << GPIO_PUPDR_PUPD15_Pos)       /*!< 0xC0000000 */
11963 #define GPIO_PUPDR_PUPD15                GPIO_PUPDR_PUPD15_Msk
11964 #define GPIO_PUPDR_PUPD15_0              (0x1UL << GPIO_PUPDR_PUPD15_Pos)       /*!< 0x40000000 */
11965 #define GPIO_PUPDR_PUPD15_1              (0x2UL << GPIO_PUPDR_PUPD15_Pos)       /*!< 0x80000000 */
11966 
11967 /* Legacy defines */
11968 #define GPIO_PUPDR_PUPDR0                GPIO_PUPDR_PUPD0
11969 #define GPIO_PUPDR_PUPDR0_0              GPIO_PUPDR_PUPD0_0
11970 #define GPIO_PUPDR_PUPDR0_1              GPIO_PUPDR_PUPD0_1
11971 #define GPIO_PUPDR_PUPDR1                GPIO_PUPDR_PUPD1
11972 #define GPIO_PUPDR_PUPDR1_0              GPIO_PUPDR_PUPD1_0
11973 #define GPIO_PUPDR_PUPDR1_1              GPIO_PUPDR_PUPD1_1
11974 #define GPIO_PUPDR_PUPDR2                GPIO_PUPDR_PUPD2
11975 #define GPIO_PUPDR_PUPDR2_0              GPIO_PUPDR_PUPD2_0
11976 #define GPIO_PUPDR_PUPDR2_1              GPIO_PUPDR_PUPD2_1
11977 #define GPIO_PUPDR_PUPDR3                GPIO_PUPDR_PUPD3
11978 #define GPIO_PUPDR_PUPDR3_0              GPIO_PUPDR_PUPD3_0
11979 #define GPIO_PUPDR_PUPDR3_1              GPIO_PUPDR_PUPD3_1
11980 #define GPIO_PUPDR_PUPDR4                GPIO_PUPDR_PUPD4
11981 #define GPIO_PUPDR_PUPDR4_0              GPIO_PUPDR_PUPD4_0
11982 #define GPIO_PUPDR_PUPDR4_1              GPIO_PUPDR_PUPD4_1
11983 #define GPIO_PUPDR_PUPDR5                GPIO_PUPDR_PUPD5
11984 #define GPIO_PUPDR_PUPDR5_0              GPIO_PUPDR_PUPD5_0
11985 #define GPIO_PUPDR_PUPDR5_1              GPIO_PUPDR_PUPD5_1
11986 #define GPIO_PUPDR_PUPDR6                GPIO_PUPDR_PUPD6
11987 #define GPIO_PUPDR_PUPDR6_0              GPIO_PUPDR_PUPD6_0
11988 #define GPIO_PUPDR_PUPDR6_1              GPIO_PUPDR_PUPD6_1
11989 #define GPIO_PUPDR_PUPDR7                GPIO_PUPDR_PUPD7
11990 #define GPIO_PUPDR_PUPDR7_0              GPIO_PUPDR_PUPD7_0
11991 #define GPIO_PUPDR_PUPDR7_1              GPIO_PUPDR_PUPD7_1
11992 #define GPIO_PUPDR_PUPDR8                GPIO_PUPDR_PUPD8
11993 #define GPIO_PUPDR_PUPDR8_0              GPIO_PUPDR_PUPD8_0
11994 #define GPIO_PUPDR_PUPDR8_1              GPIO_PUPDR_PUPD8_1
11995 #define GPIO_PUPDR_PUPDR9                GPIO_PUPDR_PUPD9
11996 #define GPIO_PUPDR_PUPDR9_0              GPIO_PUPDR_PUPD9_0
11997 #define GPIO_PUPDR_PUPDR9_1              GPIO_PUPDR_PUPD9_1
11998 #define GPIO_PUPDR_PUPDR10               GPIO_PUPDR_PUPD10
11999 #define GPIO_PUPDR_PUPDR10_0             GPIO_PUPDR_PUPD10_0
12000 #define GPIO_PUPDR_PUPDR10_1             GPIO_PUPDR_PUPD10_1
12001 #define GPIO_PUPDR_PUPDR11               GPIO_PUPDR_PUPD11
12002 #define GPIO_PUPDR_PUPDR11_0             GPIO_PUPDR_PUPD11_0
12003 #define GPIO_PUPDR_PUPDR11_1             GPIO_PUPDR_PUPD11_1
12004 #define GPIO_PUPDR_PUPDR12               GPIO_PUPDR_PUPD12
12005 #define GPIO_PUPDR_PUPDR12_0             GPIO_PUPDR_PUPD12_0
12006 #define GPIO_PUPDR_PUPDR12_1             GPIO_PUPDR_PUPD12_1
12007 #define GPIO_PUPDR_PUPDR13               GPIO_PUPDR_PUPD13
12008 #define GPIO_PUPDR_PUPDR13_0             GPIO_PUPDR_PUPD13_0
12009 #define GPIO_PUPDR_PUPDR13_1             GPIO_PUPDR_PUPD13_1
12010 #define GPIO_PUPDR_PUPDR14               GPIO_PUPDR_PUPD14
12011 #define GPIO_PUPDR_PUPDR14_0             GPIO_PUPDR_PUPD14_0
12012 #define GPIO_PUPDR_PUPDR14_1             GPIO_PUPDR_PUPD14_1
12013 #define GPIO_PUPDR_PUPDR15               GPIO_PUPDR_PUPD15
12014 #define GPIO_PUPDR_PUPDR15_0             GPIO_PUPDR_PUPD15_0
12015 #define GPIO_PUPDR_PUPDR15_1             GPIO_PUPDR_PUPD15_1
12016 
12017 /******************  Bits definition for GPIO_IDR register  *******************/
12018 #define GPIO_IDR_ID0_Pos                 (0U)
12019 #define GPIO_IDR_ID0_Msk                 (0x1UL << GPIO_IDR_ID0_Pos)            /*!< 0x00000001 */
12020 #define GPIO_IDR_ID0                     GPIO_IDR_ID0_Msk
12021 #define GPIO_IDR_ID1_Pos                 (1U)
12022 #define GPIO_IDR_ID1_Msk                 (0x1UL << GPIO_IDR_ID1_Pos)            /*!< 0x00000002 */
12023 #define GPIO_IDR_ID1                     GPIO_IDR_ID1_Msk
12024 #define GPIO_IDR_ID2_Pos                 (2U)
12025 #define GPIO_IDR_ID2_Msk                 (0x1UL << GPIO_IDR_ID2_Pos)            /*!< 0x00000004 */
12026 #define GPIO_IDR_ID2                     GPIO_IDR_ID2_Msk
12027 #define GPIO_IDR_ID3_Pos                 (3U)
12028 #define GPIO_IDR_ID3_Msk                 (0x1UL << GPIO_IDR_ID3_Pos)            /*!< 0x00000008 */
12029 #define GPIO_IDR_ID3                     GPIO_IDR_ID3_Msk
12030 #define GPIO_IDR_ID4_Pos                 (4U)
12031 #define GPIO_IDR_ID4_Msk                 (0x1UL << GPIO_IDR_ID4_Pos)            /*!< 0x00000010 */
12032 #define GPIO_IDR_ID4                     GPIO_IDR_ID4_Msk
12033 #define GPIO_IDR_ID5_Pos                 (5U)
12034 #define GPIO_IDR_ID5_Msk                 (0x1UL << GPIO_IDR_ID5_Pos)            /*!< 0x00000020 */
12035 #define GPIO_IDR_ID5                     GPIO_IDR_ID5_Msk
12036 #define GPIO_IDR_ID6_Pos                 (6U)
12037 #define GPIO_IDR_ID6_Msk                 (0x1UL << GPIO_IDR_ID6_Pos)            /*!< 0x00000040 */
12038 #define GPIO_IDR_ID6                     GPIO_IDR_ID6_Msk
12039 #define GPIO_IDR_ID7_Pos                 (7U)
12040 #define GPIO_IDR_ID7_Msk                 (0x1UL << GPIO_IDR_ID7_Pos)            /*!< 0x00000080 */
12041 #define GPIO_IDR_ID7                     GPIO_IDR_ID7_Msk
12042 #define GPIO_IDR_ID8_Pos                 (8U)
12043 #define GPIO_IDR_ID8_Msk                 (0x1UL << GPIO_IDR_ID8_Pos)            /*!< 0x00000100 */
12044 #define GPIO_IDR_ID8                     GPIO_IDR_ID8_Msk
12045 #define GPIO_IDR_ID9_Pos                 (9U)
12046 #define GPIO_IDR_ID9_Msk                 (0x1UL << GPIO_IDR_ID9_Pos)            /*!< 0x00000200 */
12047 #define GPIO_IDR_ID9                     GPIO_IDR_ID9_Msk
12048 #define GPIO_IDR_ID10_Pos                (10U)
12049 #define GPIO_IDR_ID10_Msk                (0x1UL << GPIO_IDR_ID10_Pos)           /*!< 0x00000400 */
12050 #define GPIO_IDR_ID10                    GPIO_IDR_ID10_Msk
12051 #define GPIO_IDR_ID11_Pos                (11U)
12052 #define GPIO_IDR_ID11_Msk                (0x1UL << GPIO_IDR_ID11_Pos)           /*!< 0x00000800 */
12053 #define GPIO_IDR_ID11                    GPIO_IDR_ID11_Msk
12054 #define GPIO_IDR_ID12_Pos                (12U)
12055 #define GPIO_IDR_ID12_Msk                (0x1UL << GPIO_IDR_ID12_Pos)           /*!< 0x00001000 */
12056 #define GPIO_IDR_ID12                    GPIO_IDR_ID12_Msk
12057 #define GPIO_IDR_ID13_Pos                (13U)
12058 #define GPIO_IDR_ID13_Msk                (0x1UL << GPIO_IDR_ID13_Pos)           /*!< 0x00002000 */
12059 #define GPIO_IDR_ID13                    GPIO_IDR_ID13_Msk
12060 #define GPIO_IDR_ID14_Pos                (14U)
12061 #define GPIO_IDR_ID14_Msk                (0x1UL << GPIO_IDR_ID14_Pos)           /*!< 0x00004000 */
12062 #define GPIO_IDR_ID14                    GPIO_IDR_ID14_Msk
12063 #define GPIO_IDR_ID15_Pos                (15U)
12064 #define GPIO_IDR_ID15_Msk                (0x1UL << GPIO_IDR_ID15_Pos)           /*!< 0x00008000 */
12065 #define GPIO_IDR_ID15                    GPIO_IDR_ID15_Msk
12066 
12067 /* Legacy defines */
12068 #define GPIO_IDR_IDR_0                   GPIO_IDR_ID0
12069 #define GPIO_IDR_IDR_1                   GPIO_IDR_ID1
12070 #define GPIO_IDR_IDR_2                   GPIO_IDR_ID2
12071 #define GPIO_IDR_IDR_3                   GPIO_IDR_ID3
12072 #define GPIO_IDR_IDR_4                   GPIO_IDR_ID4
12073 #define GPIO_IDR_IDR_5                   GPIO_IDR_ID5
12074 #define GPIO_IDR_IDR_6                   GPIO_IDR_ID6
12075 #define GPIO_IDR_IDR_7                   GPIO_IDR_ID7
12076 #define GPIO_IDR_IDR_8                   GPIO_IDR_ID8
12077 #define GPIO_IDR_IDR_9                   GPIO_IDR_ID9
12078 #define GPIO_IDR_IDR_10                  GPIO_IDR_ID10
12079 #define GPIO_IDR_IDR_11                  GPIO_IDR_ID11
12080 #define GPIO_IDR_IDR_12                  GPIO_IDR_ID12
12081 #define GPIO_IDR_IDR_13                  GPIO_IDR_ID13
12082 #define GPIO_IDR_IDR_14                  GPIO_IDR_ID14
12083 #define GPIO_IDR_IDR_15                  GPIO_IDR_ID15
12084 
12085 /******************  Bits definition for GPIO_ODR register  *******************/
12086 #define GPIO_ODR_OD0_Pos                 (0U)
12087 #define GPIO_ODR_OD0_Msk                 (0x1UL << GPIO_ODR_OD0_Pos)            /*!< 0x00000001 */
12088 #define GPIO_ODR_OD0                     GPIO_ODR_OD0_Msk
12089 #define GPIO_ODR_OD1_Pos                 (1U)
12090 #define GPIO_ODR_OD1_Msk                 (0x1UL << GPIO_ODR_OD1_Pos)            /*!< 0x00000002 */
12091 #define GPIO_ODR_OD1                     GPIO_ODR_OD1_Msk
12092 #define GPIO_ODR_OD2_Pos                 (2U)
12093 #define GPIO_ODR_OD2_Msk                 (0x1UL << GPIO_ODR_OD2_Pos)            /*!< 0x00000004 */
12094 #define GPIO_ODR_OD2                     GPIO_ODR_OD2_Msk
12095 #define GPIO_ODR_OD3_Pos                 (3U)
12096 #define GPIO_ODR_OD3_Msk                 (0x1UL << GPIO_ODR_OD3_Pos)            /*!< 0x00000008 */
12097 #define GPIO_ODR_OD3                     GPIO_ODR_OD3_Msk
12098 #define GPIO_ODR_OD4_Pos                 (4U)
12099 #define GPIO_ODR_OD4_Msk                 (0x1UL << GPIO_ODR_OD4_Pos)            /*!< 0x00000010 */
12100 #define GPIO_ODR_OD4                     GPIO_ODR_OD4_Msk
12101 #define GPIO_ODR_OD5_Pos                 (5U)
12102 #define GPIO_ODR_OD5_Msk                 (0x1UL << GPIO_ODR_OD5_Pos)            /*!< 0x00000020 */
12103 #define GPIO_ODR_OD5                     GPIO_ODR_OD5_Msk
12104 #define GPIO_ODR_OD6_Pos                 (6U)
12105 #define GPIO_ODR_OD6_Msk                 (0x1UL << GPIO_ODR_OD6_Pos)            /*!< 0x00000040 */
12106 #define GPIO_ODR_OD6                     GPIO_ODR_OD6_Msk
12107 #define GPIO_ODR_OD7_Pos                 (7U)
12108 #define GPIO_ODR_OD7_Msk                 (0x1UL << GPIO_ODR_OD7_Pos)            /*!< 0x00000080 */
12109 #define GPIO_ODR_OD7                     GPIO_ODR_OD7_Msk
12110 #define GPIO_ODR_OD8_Pos                 (8U)
12111 #define GPIO_ODR_OD8_Msk                 (0x1UL << GPIO_ODR_OD8_Pos)            /*!< 0x00000100 */
12112 #define GPIO_ODR_OD8                     GPIO_ODR_OD8_Msk
12113 #define GPIO_ODR_OD9_Pos                 (9U)
12114 #define GPIO_ODR_OD9_Msk                 (0x1UL << GPIO_ODR_OD9_Pos)            /*!< 0x00000200 */
12115 #define GPIO_ODR_OD9                     GPIO_ODR_OD9_Msk
12116 #define GPIO_ODR_OD10_Pos                (10U)
12117 #define GPIO_ODR_OD10_Msk                (0x1UL << GPIO_ODR_OD10_Pos)           /*!< 0x00000400 */
12118 #define GPIO_ODR_OD10                    GPIO_ODR_OD10_Msk
12119 #define GPIO_ODR_OD11_Pos                (11U)
12120 #define GPIO_ODR_OD11_Msk                (0x1UL << GPIO_ODR_OD11_Pos)           /*!< 0x00000800 */
12121 #define GPIO_ODR_OD11                    GPIO_ODR_OD11_Msk
12122 #define GPIO_ODR_OD12_Pos                (12U)
12123 #define GPIO_ODR_OD12_Msk                (0x1UL << GPIO_ODR_OD12_Pos)           /*!< 0x00001000 */
12124 #define GPIO_ODR_OD12                    GPIO_ODR_OD12_Msk
12125 #define GPIO_ODR_OD13_Pos                (13U)
12126 #define GPIO_ODR_OD13_Msk                (0x1UL << GPIO_ODR_OD13_Pos)           /*!< 0x00002000 */
12127 #define GPIO_ODR_OD13                    GPIO_ODR_OD13_Msk
12128 #define GPIO_ODR_OD14_Pos                (14U)
12129 #define GPIO_ODR_OD14_Msk                (0x1UL << GPIO_ODR_OD14_Pos)           /*!< 0x00004000 */
12130 #define GPIO_ODR_OD14                    GPIO_ODR_OD14_Msk
12131 #define GPIO_ODR_OD15_Pos                (15U)
12132 #define GPIO_ODR_OD15_Msk                (0x1UL << GPIO_ODR_OD15_Pos)           /*!< 0x00008000 */
12133 #define GPIO_ODR_OD15                    GPIO_ODR_OD15_Msk
12134 /* Legacy defines */
12135 #define GPIO_ODR_ODR_0                   GPIO_ODR_OD0
12136 #define GPIO_ODR_ODR_1                   GPIO_ODR_OD1
12137 #define GPIO_ODR_ODR_2                   GPIO_ODR_OD2
12138 #define GPIO_ODR_ODR_3                   GPIO_ODR_OD3
12139 #define GPIO_ODR_ODR_4                   GPIO_ODR_OD4
12140 #define GPIO_ODR_ODR_5                   GPIO_ODR_OD5
12141 #define GPIO_ODR_ODR_6                   GPIO_ODR_OD6
12142 #define GPIO_ODR_ODR_7                   GPIO_ODR_OD7
12143 #define GPIO_ODR_ODR_8                   GPIO_ODR_OD8
12144 #define GPIO_ODR_ODR_9                   GPIO_ODR_OD9
12145 #define GPIO_ODR_ODR_10                  GPIO_ODR_OD10
12146 #define GPIO_ODR_ODR_11                  GPIO_ODR_OD11
12147 #define GPIO_ODR_ODR_12                  GPIO_ODR_OD12
12148 #define GPIO_ODR_ODR_13                  GPIO_ODR_OD13
12149 #define GPIO_ODR_ODR_14                  GPIO_ODR_OD14
12150 #define GPIO_ODR_ODR_15                  GPIO_ODR_OD15
12151 
12152 /******************  Bits definition for GPIO_BSRR register  ******************/
12153 #define GPIO_BSRR_BS0_Pos                (0U)
12154 #define GPIO_BSRR_BS0_Msk                (0x1UL << GPIO_BSRR_BS0_Pos)           /*!< 0x00000001 */
12155 #define GPIO_BSRR_BS0                    GPIO_BSRR_BS0_Msk
12156 #define GPIO_BSRR_BS1_Pos                (1U)
12157 #define GPIO_BSRR_BS1_Msk                (0x1UL << GPIO_BSRR_BS1_Pos)           /*!< 0x00000002 */
12158 #define GPIO_BSRR_BS1                    GPIO_BSRR_BS1_Msk
12159 #define GPIO_BSRR_BS2_Pos                (2U)
12160 #define GPIO_BSRR_BS2_Msk                (0x1UL << GPIO_BSRR_BS2_Pos)           /*!< 0x00000004 */
12161 #define GPIO_BSRR_BS2                    GPIO_BSRR_BS2_Msk
12162 #define GPIO_BSRR_BS3_Pos                (3U)
12163 #define GPIO_BSRR_BS3_Msk                (0x1UL << GPIO_BSRR_BS3_Pos)           /*!< 0x00000008 */
12164 #define GPIO_BSRR_BS3                    GPIO_BSRR_BS3_Msk
12165 #define GPIO_BSRR_BS4_Pos                (4U)
12166 #define GPIO_BSRR_BS4_Msk                (0x1UL << GPIO_BSRR_BS4_Pos)           /*!< 0x00000010 */
12167 #define GPIO_BSRR_BS4                    GPIO_BSRR_BS4_Msk
12168 #define GPIO_BSRR_BS5_Pos                (5U)
12169 #define GPIO_BSRR_BS5_Msk                (0x1UL << GPIO_BSRR_BS5_Pos)           /*!< 0x00000020 */
12170 #define GPIO_BSRR_BS5                    GPIO_BSRR_BS5_Msk
12171 #define GPIO_BSRR_BS6_Pos                (6U)
12172 #define GPIO_BSRR_BS6_Msk                (0x1UL << GPIO_BSRR_BS6_Pos)           /*!< 0x00000040 */
12173 #define GPIO_BSRR_BS6                    GPIO_BSRR_BS6_Msk
12174 #define GPIO_BSRR_BS7_Pos                (7U)
12175 #define GPIO_BSRR_BS7_Msk                (0x1UL << GPIO_BSRR_BS7_Pos)           /*!< 0x00000080 */
12176 #define GPIO_BSRR_BS7                    GPIO_BSRR_BS7_Msk
12177 #define GPIO_BSRR_BS8_Pos                (8U)
12178 #define GPIO_BSRR_BS8_Msk                (0x1UL << GPIO_BSRR_BS8_Pos)           /*!< 0x00000100 */
12179 #define GPIO_BSRR_BS8                    GPIO_BSRR_BS8_Msk
12180 #define GPIO_BSRR_BS9_Pos                (9U)
12181 #define GPIO_BSRR_BS9_Msk                (0x1UL << GPIO_BSRR_BS9_Pos)           /*!< 0x00000200 */
12182 #define GPIO_BSRR_BS9                    GPIO_BSRR_BS9_Msk
12183 #define GPIO_BSRR_BS10_Pos               (10U)
12184 #define GPIO_BSRR_BS10_Msk               (0x1UL << GPIO_BSRR_BS10_Pos)          /*!< 0x00000400 */
12185 #define GPIO_BSRR_BS10                   GPIO_BSRR_BS10_Msk
12186 #define GPIO_BSRR_BS11_Pos               (11U)
12187 #define GPIO_BSRR_BS11_Msk               (0x1UL << GPIO_BSRR_BS11_Pos)          /*!< 0x00000800 */
12188 #define GPIO_BSRR_BS11                   GPIO_BSRR_BS11_Msk
12189 #define GPIO_BSRR_BS12_Pos               (12U)
12190 #define GPIO_BSRR_BS12_Msk               (0x1UL << GPIO_BSRR_BS12_Pos)          /*!< 0x00001000 */
12191 #define GPIO_BSRR_BS12                   GPIO_BSRR_BS12_Msk
12192 #define GPIO_BSRR_BS13_Pos               (13U)
12193 #define GPIO_BSRR_BS13_Msk               (0x1UL << GPIO_BSRR_BS13_Pos)          /*!< 0x00002000 */
12194 #define GPIO_BSRR_BS13                   GPIO_BSRR_BS13_Msk
12195 #define GPIO_BSRR_BS14_Pos               (14U)
12196 #define GPIO_BSRR_BS14_Msk               (0x1UL << GPIO_BSRR_BS14_Pos)          /*!< 0x00004000 */
12197 #define GPIO_BSRR_BS14                   GPIO_BSRR_BS14_Msk
12198 #define GPIO_BSRR_BS15_Pos               (15U)
12199 #define GPIO_BSRR_BS15_Msk               (0x1UL << GPIO_BSRR_BS15_Pos)          /*!< 0x00008000 */
12200 #define GPIO_BSRR_BS15                   GPIO_BSRR_BS15_Msk
12201 #define GPIO_BSRR_BR0_Pos                (16U)
12202 #define GPIO_BSRR_BR0_Msk                (0x1UL << GPIO_BSRR_BR0_Pos)           /*!< 0x00010000 */
12203 #define GPIO_BSRR_BR0                    GPIO_BSRR_BR0_Msk
12204 #define GPIO_BSRR_BR1_Pos                (17U)
12205 #define GPIO_BSRR_BR1_Msk                (0x1UL << GPIO_BSRR_BR1_Pos)           /*!< 0x00020000 */
12206 #define GPIO_BSRR_BR1                    GPIO_BSRR_BR1_Msk
12207 #define GPIO_BSRR_BR2_Pos                (18U)
12208 #define GPIO_BSRR_BR2_Msk                (0x1UL << GPIO_BSRR_BR2_Pos)           /*!< 0x00040000 */
12209 #define GPIO_BSRR_BR2                    GPIO_BSRR_BR2_Msk
12210 #define GPIO_BSRR_BR3_Pos                (19U)
12211 #define GPIO_BSRR_BR3_Msk                (0x1UL << GPIO_BSRR_BR3_Pos)           /*!< 0x00080000 */
12212 #define GPIO_BSRR_BR3                    GPIO_BSRR_BR3_Msk
12213 #define GPIO_BSRR_BR4_Pos                (20U)
12214 #define GPIO_BSRR_BR4_Msk                (0x1UL << GPIO_BSRR_BR4_Pos)           /*!< 0x00100000 */
12215 #define GPIO_BSRR_BR4                    GPIO_BSRR_BR4_Msk
12216 #define GPIO_BSRR_BR5_Pos                (21U)
12217 #define GPIO_BSRR_BR5_Msk                (0x1UL << GPIO_BSRR_BR5_Pos)           /*!< 0x00200000 */
12218 #define GPIO_BSRR_BR5                    GPIO_BSRR_BR5_Msk
12219 #define GPIO_BSRR_BR6_Pos                (22U)
12220 #define GPIO_BSRR_BR6_Msk                (0x1UL << GPIO_BSRR_BR6_Pos)           /*!< 0x00400000 */
12221 #define GPIO_BSRR_BR6                    GPIO_BSRR_BR6_Msk
12222 #define GPIO_BSRR_BR7_Pos                (23U)
12223 #define GPIO_BSRR_BR7_Msk                (0x1UL << GPIO_BSRR_BR7_Pos)           /*!< 0x00800000 */
12224 #define GPIO_BSRR_BR7                    GPIO_BSRR_BR7_Msk
12225 #define GPIO_BSRR_BR8_Pos                (24U)
12226 #define GPIO_BSRR_BR8_Msk                (0x1UL << GPIO_BSRR_BR8_Pos)           /*!< 0x01000000 */
12227 #define GPIO_BSRR_BR8                    GPIO_BSRR_BR8_Msk
12228 #define GPIO_BSRR_BR9_Pos                (25U)
12229 #define GPIO_BSRR_BR9_Msk                (0x1UL << GPIO_BSRR_BR9_Pos)           /*!< 0x02000000 */
12230 #define GPIO_BSRR_BR9                    GPIO_BSRR_BR9_Msk
12231 #define GPIO_BSRR_BR10_Pos               (26U)
12232 #define GPIO_BSRR_BR10_Msk               (0x1UL << GPIO_BSRR_BR10_Pos)          /*!< 0x04000000 */
12233 #define GPIO_BSRR_BR10                   GPIO_BSRR_BR10_Msk
12234 #define GPIO_BSRR_BR11_Pos               (27U)
12235 #define GPIO_BSRR_BR11_Msk               (0x1UL << GPIO_BSRR_BR11_Pos)          /*!< 0x08000000 */
12236 #define GPIO_BSRR_BR11                   GPIO_BSRR_BR11_Msk
12237 #define GPIO_BSRR_BR12_Pos               (28U)
12238 #define GPIO_BSRR_BR12_Msk               (0x1UL << GPIO_BSRR_BR12_Pos)          /*!< 0x10000000 */
12239 #define GPIO_BSRR_BR12                   GPIO_BSRR_BR12_Msk
12240 #define GPIO_BSRR_BR13_Pos               (29U)
12241 #define GPIO_BSRR_BR13_Msk               (0x1UL << GPIO_BSRR_BR13_Pos)          /*!< 0x20000000 */
12242 #define GPIO_BSRR_BR13                   GPIO_BSRR_BR13_Msk
12243 #define GPIO_BSRR_BR14_Pos               (30U)
12244 #define GPIO_BSRR_BR14_Msk               (0x1UL << GPIO_BSRR_BR14_Pos)          /*!< 0x40000000 */
12245 #define GPIO_BSRR_BR14                   GPIO_BSRR_BR14_Msk
12246 #define GPIO_BSRR_BR15_Pos               (31U)
12247 #define GPIO_BSRR_BR15_Msk               (0x1UL << GPIO_BSRR_BR15_Pos)          /*!< 0x80000000 */
12248 #define GPIO_BSRR_BR15                   GPIO_BSRR_BR15_Msk
12249 
12250 /* Legacy defines */
12251 #define GPIO_BSRR_BS_0                   GPIO_BSRR_BS0
12252 #define GPIO_BSRR_BS_1                   GPIO_BSRR_BS1
12253 #define GPIO_BSRR_BS_2                   GPIO_BSRR_BS2
12254 #define GPIO_BSRR_BS_3                   GPIO_BSRR_BS3
12255 #define GPIO_BSRR_BS_4                   GPIO_BSRR_BS4
12256 #define GPIO_BSRR_BS_5                   GPIO_BSRR_BS5
12257 #define GPIO_BSRR_BS_6                   GPIO_BSRR_BS6
12258 #define GPIO_BSRR_BS_7                   GPIO_BSRR_BS7
12259 #define GPIO_BSRR_BS_8                   GPIO_BSRR_BS8
12260 #define GPIO_BSRR_BS_9                   GPIO_BSRR_BS9
12261 #define GPIO_BSRR_BS_10                  GPIO_BSRR_BS10
12262 #define GPIO_BSRR_BS_11                  GPIO_BSRR_BS11
12263 #define GPIO_BSRR_BS_12                  GPIO_BSRR_BS12
12264 #define GPIO_BSRR_BS_13                  GPIO_BSRR_BS13
12265 #define GPIO_BSRR_BS_14                  GPIO_BSRR_BS14
12266 #define GPIO_BSRR_BS_15                  GPIO_BSRR_BS15
12267 #define GPIO_BSRR_BR_0                   GPIO_BSRR_BR0
12268 #define GPIO_BSRR_BR_1                   GPIO_BSRR_BR1
12269 #define GPIO_BSRR_BR_2                   GPIO_BSRR_BR2
12270 #define GPIO_BSRR_BR_3                   GPIO_BSRR_BR3
12271 #define GPIO_BSRR_BR_4                   GPIO_BSRR_BR4
12272 #define GPIO_BSRR_BR_5                   GPIO_BSRR_BR5
12273 #define GPIO_BSRR_BR_6                   GPIO_BSRR_BR6
12274 #define GPIO_BSRR_BR_7                   GPIO_BSRR_BR7
12275 #define GPIO_BSRR_BR_8                   GPIO_BSRR_BR8
12276 #define GPIO_BSRR_BR_9                   GPIO_BSRR_BR9
12277 #define GPIO_BSRR_BR_10                  GPIO_BSRR_BR10
12278 #define GPIO_BSRR_BR_11                  GPIO_BSRR_BR11
12279 #define GPIO_BSRR_BR_12                  GPIO_BSRR_BR12
12280 #define GPIO_BSRR_BR_13                  GPIO_BSRR_BR13
12281 #define GPIO_BSRR_BR_14                  GPIO_BSRR_BR14
12282 #define GPIO_BSRR_BR_15                  GPIO_BSRR_BR15
12283 #define GPIO_BRR_BR0                     GPIO_BSRR_BR0
12284 #define GPIO_BRR_BR0_Pos                 GPIO_BSRR_BR0_Pos
12285 #define GPIO_BRR_BR0_Msk                 GPIO_BSRR_BR0_Msk
12286 #define GPIO_BRR_BR1                     GPIO_BSRR_BR1
12287 #define GPIO_BRR_BR1_Pos                 GPIO_BSRR_BR1_Pos
12288 #define GPIO_BRR_BR1_Msk                 GPIO_BSRR_BR1_Msk
12289 #define GPIO_BRR_BR2                     GPIO_BSRR_BR2
12290 #define GPIO_BRR_BR2_Pos                 GPIO_BSRR_BR2_Pos
12291 #define GPIO_BRR_BR2_Msk                 GPIO_BSRR_BR2_Msk
12292 #define GPIO_BRR_BR3                     GPIO_BSRR_BR3
12293 #define GPIO_BRR_BR3_Pos                 GPIO_BSRR_BR3_Pos
12294 #define GPIO_BRR_BR3_Msk                 GPIO_BSRR_BR3_Msk
12295 #define GPIO_BRR_BR4                     GPIO_BSRR_BR4
12296 #define GPIO_BRR_BR4_Pos                 GPIO_BSRR_BR4_Pos
12297 #define GPIO_BRR_BR4_Msk                 GPIO_BSRR_BR4_Msk
12298 #define GPIO_BRR_BR5                     GPIO_BSRR_BR5
12299 #define GPIO_BRR_BR5_Pos                 GPIO_BSRR_BR5_Pos
12300 #define GPIO_BRR_BR5_Msk                 GPIO_BSRR_BR5_Msk
12301 #define GPIO_BRR_BR6                     GPIO_BSRR_BR6
12302 #define GPIO_BRR_BR6_Pos                 GPIO_BSRR_BR6_Pos
12303 #define GPIO_BRR_BR6_Msk                 GPIO_BSRR_BR6_Msk
12304 #define GPIO_BRR_BR7                     GPIO_BSRR_BR7
12305 #define GPIO_BRR_BR7_Pos                 GPIO_BSRR_BR7_Pos
12306 #define GPIO_BRR_BR7_Msk                 GPIO_BSRR_BR7_Msk
12307 #define GPIO_BRR_BR8                     GPIO_BSRR_BR8
12308 #define GPIO_BRR_BR8_Pos                 GPIO_BSRR_BR8_Pos
12309 #define GPIO_BRR_BR8_Msk                 GPIO_BSRR_BR8_Msk
12310 #define GPIO_BRR_BR9                     GPIO_BSRR_BR9
12311 #define GPIO_BRR_BR9_Pos                 GPIO_BSRR_BR9_Pos
12312 #define GPIO_BRR_BR9_Msk                 GPIO_BSRR_BR9_Msk
12313 #define GPIO_BRR_BR10                    GPIO_BSRR_BR10
12314 #define GPIO_BRR_BR10_Pos                GPIO_BSRR_BR10_Pos
12315 #define GPIO_BRR_BR10_Msk                GPIO_BSRR_BR10_Msk
12316 #define GPIO_BRR_BR11                    GPIO_BSRR_BR11
12317 #define GPIO_BRR_BR11_Pos                GPIO_BSRR_BR11_Pos
12318 #define GPIO_BRR_BR11_Msk                GPIO_BSRR_BR11_Msk
12319 #define GPIO_BRR_BR12                    GPIO_BSRR_BR12
12320 #define GPIO_BRR_BR12_Pos                GPIO_BSRR_BR12_Pos
12321 #define GPIO_BRR_BR12_Msk                GPIO_BSRR_BR12_Msk
12322 #define GPIO_BRR_BR13                    GPIO_BSRR_BR13
12323 #define GPIO_BRR_BR13_Pos                GPIO_BSRR_BR13_Pos
12324 #define GPIO_BRR_BR13_Msk                GPIO_BSRR_BR13_Msk
12325 #define GPIO_BRR_BR14                    GPIO_BSRR_BR14
12326 #define GPIO_BRR_BR14_Pos                GPIO_BSRR_BR14_Pos
12327 #define GPIO_BRR_BR14_Msk                GPIO_BSRR_BR14_Msk
12328 #define GPIO_BRR_BR15                    GPIO_BSRR_BR15
12329 #define GPIO_BRR_BR15_Pos                GPIO_BSRR_BR15_Pos
12330 #define GPIO_BRR_BR15_Msk                GPIO_BSRR_BR15_Msk
12331 /****************** Bit definition for GPIO_LCKR register *********************/
12332 #define GPIO_LCKR_LCK0_Pos               (0U)
12333 #define GPIO_LCKR_LCK0_Msk               (0x1UL << GPIO_LCKR_LCK0_Pos)          /*!< 0x00000001 */
12334 #define GPIO_LCKR_LCK0                   GPIO_LCKR_LCK0_Msk
12335 #define GPIO_LCKR_LCK1_Pos               (1U)
12336 #define GPIO_LCKR_LCK1_Msk               (0x1UL << GPIO_LCKR_LCK1_Pos)          /*!< 0x00000002 */
12337 #define GPIO_LCKR_LCK1                   GPIO_LCKR_LCK1_Msk
12338 #define GPIO_LCKR_LCK2_Pos               (2U)
12339 #define GPIO_LCKR_LCK2_Msk               (0x1UL << GPIO_LCKR_LCK2_Pos)          /*!< 0x00000004 */
12340 #define GPIO_LCKR_LCK2                   GPIO_LCKR_LCK2_Msk
12341 #define GPIO_LCKR_LCK3_Pos               (3U)
12342 #define GPIO_LCKR_LCK3_Msk               (0x1UL << GPIO_LCKR_LCK3_Pos)          /*!< 0x00000008 */
12343 #define GPIO_LCKR_LCK3                   GPIO_LCKR_LCK3_Msk
12344 #define GPIO_LCKR_LCK4_Pos               (4U)
12345 #define GPIO_LCKR_LCK4_Msk               (0x1UL << GPIO_LCKR_LCK4_Pos)          /*!< 0x00000010 */
12346 #define GPIO_LCKR_LCK4                   GPIO_LCKR_LCK4_Msk
12347 #define GPIO_LCKR_LCK5_Pos               (5U)
12348 #define GPIO_LCKR_LCK5_Msk               (0x1UL << GPIO_LCKR_LCK5_Pos)          /*!< 0x00000020 */
12349 #define GPIO_LCKR_LCK5                   GPIO_LCKR_LCK5_Msk
12350 #define GPIO_LCKR_LCK6_Pos               (6U)
12351 #define GPIO_LCKR_LCK6_Msk               (0x1UL << GPIO_LCKR_LCK6_Pos)          /*!< 0x00000040 */
12352 #define GPIO_LCKR_LCK6                   GPIO_LCKR_LCK6_Msk
12353 #define GPIO_LCKR_LCK7_Pos               (7U)
12354 #define GPIO_LCKR_LCK7_Msk               (0x1UL << GPIO_LCKR_LCK7_Pos)          /*!< 0x00000080 */
12355 #define GPIO_LCKR_LCK7                   GPIO_LCKR_LCK7_Msk
12356 #define GPIO_LCKR_LCK8_Pos               (8U)
12357 #define GPIO_LCKR_LCK8_Msk               (0x1UL << GPIO_LCKR_LCK8_Pos)          /*!< 0x00000100 */
12358 #define GPIO_LCKR_LCK8                   GPIO_LCKR_LCK8_Msk
12359 #define GPIO_LCKR_LCK9_Pos               (9U)
12360 #define GPIO_LCKR_LCK9_Msk               (0x1UL << GPIO_LCKR_LCK9_Pos)          /*!< 0x00000200 */
12361 #define GPIO_LCKR_LCK9                   GPIO_LCKR_LCK9_Msk
12362 #define GPIO_LCKR_LCK10_Pos              (10U)
12363 #define GPIO_LCKR_LCK10_Msk              (0x1UL << GPIO_LCKR_LCK10_Pos)         /*!< 0x00000400 */
12364 #define GPIO_LCKR_LCK10                  GPIO_LCKR_LCK10_Msk
12365 #define GPIO_LCKR_LCK11_Pos              (11U)
12366 #define GPIO_LCKR_LCK11_Msk              (0x1UL << GPIO_LCKR_LCK11_Pos)         /*!< 0x00000800 */
12367 #define GPIO_LCKR_LCK11                  GPIO_LCKR_LCK11_Msk
12368 #define GPIO_LCKR_LCK12_Pos              (12U)
12369 #define GPIO_LCKR_LCK12_Msk              (0x1UL << GPIO_LCKR_LCK12_Pos)         /*!< 0x00001000 */
12370 #define GPIO_LCKR_LCK12                  GPIO_LCKR_LCK12_Msk
12371 #define GPIO_LCKR_LCK13_Pos              (13U)
12372 #define GPIO_LCKR_LCK13_Msk              (0x1UL << GPIO_LCKR_LCK13_Pos)         /*!< 0x00002000 */
12373 #define GPIO_LCKR_LCK13                  GPIO_LCKR_LCK13_Msk
12374 #define GPIO_LCKR_LCK14_Pos              (14U)
12375 #define GPIO_LCKR_LCK14_Msk              (0x1UL << GPIO_LCKR_LCK14_Pos)         /*!< 0x00004000 */
12376 #define GPIO_LCKR_LCK14                  GPIO_LCKR_LCK14_Msk
12377 #define GPIO_LCKR_LCK15_Pos              (15U)
12378 #define GPIO_LCKR_LCK15_Msk              (0x1UL << GPIO_LCKR_LCK15_Pos)         /*!< 0x00008000 */
12379 #define GPIO_LCKR_LCK15                  GPIO_LCKR_LCK15_Msk
12380 #define GPIO_LCKR_LCKK_Pos               (16U)
12381 #define GPIO_LCKR_LCKK_Msk               (0x1UL << GPIO_LCKR_LCKK_Pos)          /*!< 0x00010000 */
12382 #define GPIO_LCKR_LCKK                   GPIO_LCKR_LCKK_Msk
12383 /****************** Bit definition for GPIO_AFRL register *********************/
12384 #define GPIO_AFRL_AFSEL0_Pos             (0U)
12385 #define GPIO_AFRL_AFSEL0_Msk             (0xFUL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x0000000F */
12386 #define GPIO_AFRL_AFSEL0                 GPIO_AFRL_AFSEL0_Msk
12387 #define GPIO_AFRL_AFSEL0_0               (0x1UL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000001 */
12388 #define GPIO_AFRL_AFSEL0_1               (0x2UL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000002 */
12389 #define GPIO_AFRL_AFSEL0_2               (0x4UL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000004 */
12390 #define GPIO_AFRL_AFSEL0_3               (0x8UL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000008 */
12391 #define GPIO_AFRL_AFSEL1_Pos             (4U)
12392 #define GPIO_AFRL_AFSEL1_Msk             (0xFUL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x000000F0 */
12393 #define GPIO_AFRL_AFSEL1                 GPIO_AFRL_AFSEL1_Msk
12394 #define GPIO_AFRL_AFSEL1_0               (0x1UL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000010 */
12395 #define GPIO_AFRL_AFSEL1_1               (0x2UL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000020 */
12396 #define GPIO_AFRL_AFSEL1_2               (0x4UL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000040 */
12397 #define GPIO_AFRL_AFSEL1_3               (0x8UL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000080 */
12398 #define GPIO_AFRL_AFSEL2_Pos             (8U)
12399 #define GPIO_AFRL_AFSEL2_Msk             (0xFUL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000F00 */
12400 #define GPIO_AFRL_AFSEL2                 GPIO_AFRL_AFSEL2_Msk
12401 #define GPIO_AFRL_AFSEL2_0               (0x1UL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000100 */
12402 #define GPIO_AFRL_AFSEL2_1               (0x2UL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000200 */
12403 #define GPIO_AFRL_AFSEL2_2               (0x4UL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000400 */
12404 #define GPIO_AFRL_AFSEL2_3               (0x8UL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000800 */
12405 #define GPIO_AFRL_AFSEL3_Pos             (12U)
12406 #define GPIO_AFRL_AFSEL3_Msk             (0xFUL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x0000F000 */
12407 #define GPIO_AFRL_AFSEL3                 GPIO_AFRL_AFSEL3_Msk
12408 #define GPIO_AFRL_AFSEL3_0               (0x1UL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00001000 */
12409 #define GPIO_AFRL_AFSEL3_1               (0x2UL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00002000 */
12410 #define GPIO_AFRL_AFSEL3_2               (0x4UL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00004000 */
12411 #define GPIO_AFRL_AFSEL3_3               (0x8UL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00008000 */
12412 #define GPIO_AFRL_AFSEL4_Pos             (16U)
12413 #define GPIO_AFRL_AFSEL4_Msk             (0xFUL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x000F0000 */
12414 #define GPIO_AFRL_AFSEL4                 GPIO_AFRL_AFSEL4_Msk
12415 #define GPIO_AFRL_AFSEL4_0               (0x1UL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00010000 */
12416 #define GPIO_AFRL_AFSEL4_1               (0x2UL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00020000 */
12417 #define GPIO_AFRL_AFSEL4_2               (0x4UL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00040000 */
12418 #define GPIO_AFRL_AFSEL4_3               (0x8UL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00080000 */
12419 #define GPIO_AFRL_AFSEL5_Pos             (20U)
12420 #define GPIO_AFRL_AFSEL5_Msk             (0xFUL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00F00000 */
12421 #define GPIO_AFRL_AFSEL5                 GPIO_AFRL_AFSEL5_Msk
12422 #define GPIO_AFRL_AFSEL5_0               (0x1UL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00100000 */
12423 #define GPIO_AFRL_AFSEL5_1               (0x2UL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00200000 */
12424 #define GPIO_AFRL_AFSEL5_2               (0x4UL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00400000 */
12425 #define GPIO_AFRL_AFSEL5_3               (0x8UL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00800000 */
12426 #define GPIO_AFRL_AFSEL6_Pos             (24U)
12427 #define GPIO_AFRL_AFSEL6_Msk             (0xFUL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x0F000000 */
12428 #define GPIO_AFRL_AFSEL6                 GPIO_AFRL_AFSEL6_Msk
12429 #define GPIO_AFRL_AFSEL6_0               (0x1UL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x01000000 */
12430 #define GPIO_AFRL_AFSEL6_1               (0x2UL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x02000000 */
12431 #define GPIO_AFRL_AFSEL6_2               (0x4UL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x04000000 */
12432 #define GPIO_AFRL_AFSEL6_3               (0x8UL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x08000000 */
12433 #define GPIO_AFRL_AFSEL7_Pos             (28U)
12434 #define GPIO_AFRL_AFSEL7_Msk             (0xFUL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0xF0000000 */
12435 #define GPIO_AFRL_AFSEL7                 GPIO_AFRL_AFSEL7_Msk
12436 #define GPIO_AFRL_AFSEL7_0               (0x1UL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x10000000 */
12437 #define GPIO_AFRL_AFSEL7_1               (0x2UL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x20000000 */
12438 #define GPIO_AFRL_AFSEL7_2               (0x4UL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x40000000 */
12439 #define GPIO_AFRL_AFSEL7_3               (0x8UL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x80000000 */
12440 
12441 /* Legacy defines */
12442 #define GPIO_AFRL_AFRL0                  GPIO_AFRL_AFSEL0
12443 #define GPIO_AFRL_AFRL0_0                GPIO_AFRL_AFSEL0_0
12444 #define GPIO_AFRL_AFRL0_1                GPIO_AFRL_AFSEL0_1
12445 #define GPIO_AFRL_AFRL0_2                GPIO_AFRL_AFSEL0_2
12446 #define GPIO_AFRL_AFRL0_3                GPIO_AFRL_AFSEL0_3
12447 #define GPIO_AFRL_AFRL1                  GPIO_AFRL_AFSEL1
12448 #define GPIO_AFRL_AFRL1_0                GPIO_AFRL_AFSEL1_0
12449 #define GPIO_AFRL_AFRL1_1                GPIO_AFRL_AFSEL1_1
12450 #define GPIO_AFRL_AFRL1_2                GPIO_AFRL_AFSEL1_2
12451 #define GPIO_AFRL_AFRL1_3                GPIO_AFRL_AFSEL1_3
12452 #define GPIO_AFRL_AFRL2                  GPIO_AFRL_AFSEL2
12453 #define GPIO_AFRL_AFRL2_0                GPIO_AFRL_AFSEL2_0
12454 #define GPIO_AFRL_AFRL2_1                GPIO_AFRL_AFSEL2_1
12455 #define GPIO_AFRL_AFRL2_2                GPIO_AFRL_AFSEL2_2
12456 #define GPIO_AFRL_AFRL2_3                GPIO_AFRL_AFSEL2_3
12457 #define GPIO_AFRL_AFRL3                  GPIO_AFRL_AFSEL3
12458 #define GPIO_AFRL_AFRL3_0                GPIO_AFRL_AFSEL3_0
12459 #define GPIO_AFRL_AFRL3_1                GPIO_AFRL_AFSEL3_1
12460 #define GPIO_AFRL_AFRL3_2                GPIO_AFRL_AFSEL3_2
12461 #define GPIO_AFRL_AFRL3_3                GPIO_AFRL_AFSEL3_3
12462 #define GPIO_AFRL_AFRL4                  GPIO_AFRL_AFSEL4
12463 #define GPIO_AFRL_AFRL4_0                GPIO_AFRL_AFSEL4_0
12464 #define GPIO_AFRL_AFRL4_1                GPIO_AFRL_AFSEL4_1
12465 #define GPIO_AFRL_AFRL4_2                GPIO_AFRL_AFSEL4_2
12466 #define GPIO_AFRL_AFRL4_3                GPIO_AFRL_AFSEL4_3
12467 #define GPIO_AFRL_AFRL5                  GPIO_AFRL_AFSEL5
12468 #define GPIO_AFRL_AFRL5_0                GPIO_AFRL_AFSEL5_0
12469 #define GPIO_AFRL_AFRL5_1                GPIO_AFRL_AFSEL5_1
12470 #define GPIO_AFRL_AFRL5_2                GPIO_AFRL_AFSEL5_2
12471 #define GPIO_AFRL_AFRL5_3                GPIO_AFRL_AFSEL5_3
12472 #define GPIO_AFRL_AFRL6                  GPIO_AFRL_AFSEL6
12473 #define GPIO_AFRL_AFRL6_0                GPIO_AFRL_AFSEL6_0
12474 #define GPIO_AFRL_AFRL6_1                GPIO_AFRL_AFSEL6_1
12475 #define GPIO_AFRL_AFRL6_2                GPIO_AFRL_AFSEL6_2
12476 #define GPIO_AFRL_AFRL6_3                GPIO_AFRL_AFSEL6_3
12477 #define GPIO_AFRL_AFRL7                  GPIO_AFRL_AFSEL7
12478 #define GPIO_AFRL_AFRL7_0                GPIO_AFRL_AFSEL7_0
12479 #define GPIO_AFRL_AFRL7_1                GPIO_AFRL_AFSEL7_1
12480 #define GPIO_AFRL_AFRL7_2                GPIO_AFRL_AFSEL7_2
12481 #define GPIO_AFRL_AFRL7_3                GPIO_AFRL_AFSEL7_3
12482 
12483 /****************** Bit definition for GPIO_AFRH register *********************/
12484 #define GPIO_AFRH_AFSEL8_Pos             (0U)
12485 #define GPIO_AFRH_AFSEL8_Msk             (0xFUL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x0000000F */
12486 #define GPIO_AFRH_AFSEL8                 GPIO_AFRH_AFSEL8_Msk
12487 #define GPIO_AFRH_AFSEL8_0               (0x1UL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000001 */
12488 #define GPIO_AFRH_AFSEL8_1               (0x2UL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000002 */
12489 #define GPIO_AFRH_AFSEL8_2               (0x4UL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000004 */
12490 #define GPIO_AFRH_AFSEL8_3               (0x8UL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000008 */
12491 #define GPIO_AFRH_AFSEL9_Pos             (4U)
12492 #define GPIO_AFRH_AFSEL9_Msk             (0xFUL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x000000F0 */
12493 #define GPIO_AFRH_AFSEL9                 GPIO_AFRH_AFSEL9_Msk
12494 #define GPIO_AFRH_AFSEL9_0               (0x1UL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000010 */
12495 #define GPIO_AFRH_AFSEL9_1               (0x2UL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000020 */
12496 #define GPIO_AFRH_AFSEL9_2               (0x4UL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000040 */
12497 #define GPIO_AFRH_AFSEL9_3               (0x8UL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000080 */
12498 #define GPIO_AFRH_AFSEL10_Pos            (8U)
12499 #define GPIO_AFRH_AFSEL10_Msk            (0xFUL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000F00 */
12500 #define GPIO_AFRH_AFSEL10                GPIO_AFRH_AFSEL10_Msk
12501 #define GPIO_AFRH_AFSEL10_0              (0x1UL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000100 */
12502 #define GPIO_AFRH_AFSEL10_1              (0x2UL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000200 */
12503 #define GPIO_AFRH_AFSEL10_2              (0x4UL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000400 */
12504 #define GPIO_AFRH_AFSEL10_3              (0x8UL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000800 */
12505 #define GPIO_AFRH_AFSEL11_Pos            (12U)
12506 #define GPIO_AFRH_AFSEL11_Msk            (0xFUL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x0000F000 */
12507 #define GPIO_AFRH_AFSEL11                GPIO_AFRH_AFSEL11_Msk
12508 #define GPIO_AFRH_AFSEL11_0              (0x1UL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00001000 */
12509 #define GPIO_AFRH_AFSEL11_1              (0x2UL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00002000 */
12510 #define GPIO_AFRH_AFSEL11_2              (0x4UL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00004000 */
12511 #define GPIO_AFRH_AFSEL11_3              (0x8UL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00008000 */
12512 #define GPIO_AFRH_AFSEL12_Pos            (16U)
12513 #define GPIO_AFRH_AFSEL12_Msk            (0xFUL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x000F0000 */
12514 #define GPIO_AFRH_AFSEL12                GPIO_AFRH_AFSEL12_Msk
12515 #define GPIO_AFRH_AFSEL12_0              (0x1UL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00010000 */
12516 #define GPIO_AFRH_AFSEL12_1              (0x2UL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00020000 */
12517 #define GPIO_AFRH_AFSEL12_2              (0x4UL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00040000 */
12518 #define GPIO_AFRH_AFSEL12_3              (0x8UL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00080000 */
12519 #define GPIO_AFRH_AFSEL13_Pos            (20U)
12520 #define GPIO_AFRH_AFSEL13_Msk            (0xFUL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00F00000 */
12521 #define GPIO_AFRH_AFSEL13                GPIO_AFRH_AFSEL13_Msk
12522 #define GPIO_AFRH_AFSEL13_0              (0x1UL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00100000 */
12523 #define GPIO_AFRH_AFSEL13_1              (0x2UL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00200000 */
12524 #define GPIO_AFRH_AFSEL13_2              (0x4UL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00400000 */
12525 #define GPIO_AFRH_AFSEL13_3              (0x8UL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00800000 */
12526 #define GPIO_AFRH_AFSEL14_Pos            (24U)
12527 #define GPIO_AFRH_AFSEL14_Msk            (0xFUL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x0F000000 */
12528 #define GPIO_AFRH_AFSEL14                GPIO_AFRH_AFSEL14_Msk
12529 #define GPIO_AFRH_AFSEL14_0              (0x1UL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x01000000 */
12530 #define GPIO_AFRH_AFSEL14_1              (0x2UL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x02000000 */
12531 #define GPIO_AFRH_AFSEL14_2              (0x4UL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x04000000 */
12532 #define GPIO_AFRH_AFSEL14_3              (0x8UL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x08000000 */
12533 #define GPIO_AFRH_AFSEL15_Pos            (28U)
12534 #define GPIO_AFRH_AFSEL15_Msk            (0xFUL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0xF0000000 */
12535 #define GPIO_AFRH_AFSEL15                GPIO_AFRH_AFSEL15_Msk
12536 #define GPIO_AFRH_AFSEL15_0              (0x1UL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x10000000 */
12537 #define GPIO_AFRH_AFSEL15_1              (0x2UL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x20000000 */
12538 #define GPIO_AFRH_AFSEL15_2              (0x4UL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x40000000 */
12539 #define GPIO_AFRH_AFSEL15_3              (0x8UL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x80000000 */
12540 
12541 /* Legacy defines */
12542 #define GPIO_AFRH_AFRH0                  GPIO_AFRH_AFSEL8
12543 #define GPIO_AFRH_AFRH0_0                GPIO_AFRH_AFSEL8_0
12544 #define GPIO_AFRH_AFRH0_1                GPIO_AFRH_AFSEL8_1
12545 #define GPIO_AFRH_AFRH0_2                GPIO_AFRH_AFSEL8_2
12546 #define GPIO_AFRH_AFRH0_3                GPIO_AFRH_AFSEL8_3
12547 #define GPIO_AFRH_AFRH1                  GPIO_AFRH_AFSEL9
12548 #define GPIO_AFRH_AFRH1_0                GPIO_AFRH_AFSEL9_0
12549 #define GPIO_AFRH_AFRH1_1                GPIO_AFRH_AFSEL9_1
12550 #define GPIO_AFRH_AFRH1_2                GPIO_AFRH_AFSEL9_2
12551 #define GPIO_AFRH_AFRH1_3                GPIO_AFRH_AFSEL9_3
12552 #define GPIO_AFRH_AFRH2                  GPIO_AFRH_AFSEL10
12553 #define GPIO_AFRH_AFRH2_0                GPIO_AFRH_AFSEL10_0
12554 #define GPIO_AFRH_AFRH2_1                GPIO_AFRH_AFSEL10_1
12555 #define GPIO_AFRH_AFRH2_2                GPIO_AFRH_AFSEL10_2
12556 #define GPIO_AFRH_AFRH2_3                GPIO_AFRH_AFSEL10_3
12557 #define GPIO_AFRH_AFRH3                  GPIO_AFRH_AFSEL11
12558 #define GPIO_AFRH_AFRH3_0                GPIO_AFRH_AFSEL11_0
12559 #define GPIO_AFRH_AFRH3_1                GPIO_AFRH_AFSEL11_1
12560 #define GPIO_AFRH_AFRH3_2                GPIO_AFRH_AFSEL11_2
12561 #define GPIO_AFRH_AFRH3_3                GPIO_AFRH_AFSEL11_3
12562 #define GPIO_AFRH_AFRH4                  GPIO_AFRH_AFSEL12
12563 #define GPIO_AFRH_AFRH4_0                GPIO_AFRH_AFSEL12_0
12564 #define GPIO_AFRH_AFRH4_1                GPIO_AFRH_AFSEL12_1
12565 #define GPIO_AFRH_AFRH4_2                GPIO_AFRH_AFSEL12_2
12566 #define GPIO_AFRH_AFRH4_3                GPIO_AFRH_AFSEL12_3
12567 #define GPIO_AFRH_AFRH5                  GPIO_AFRH_AFSEL13
12568 #define GPIO_AFRH_AFRH5_0                GPIO_AFRH_AFSEL13_0
12569 #define GPIO_AFRH_AFRH5_1                GPIO_AFRH_AFSEL13_1
12570 #define GPIO_AFRH_AFRH5_2                GPIO_AFRH_AFSEL13_2
12571 #define GPIO_AFRH_AFRH5_3                GPIO_AFRH_AFSEL13_3
12572 #define GPIO_AFRH_AFRH6                  GPIO_AFRH_AFSEL14
12573 #define GPIO_AFRH_AFRH6_0                GPIO_AFRH_AFSEL14_0
12574 #define GPIO_AFRH_AFRH6_1                GPIO_AFRH_AFSEL14_1
12575 #define GPIO_AFRH_AFRH6_2                GPIO_AFRH_AFSEL14_2
12576 #define GPIO_AFRH_AFRH6_3                GPIO_AFRH_AFSEL14_3
12577 #define GPIO_AFRH_AFRH7                  GPIO_AFRH_AFSEL15
12578 #define GPIO_AFRH_AFRH7_0                GPIO_AFRH_AFSEL15_0
12579 #define GPIO_AFRH_AFRH7_1                GPIO_AFRH_AFSEL15_1
12580 #define GPIO_AFRH_AFRH7_2                GPIO_AFRH_AFSEL15_2
12581 #define GPIO_AFRH_AFRH7_3                GPIO_AFRH_AFSEL15_3
12582 
12583 
12584 /******************************************************************************/
12585 /*                                                                            */
12586 /*                      Inter-integrated Circuit Interface                    */
12587 /*                                                                            */
12588 /******************************************************************************/
12589 /*******************  Bit definition for I2C_CR1 register  ********************/
12590 #define I2C_CR1_PE_Pos            (0U)
12591 #define I2C_CR1_PE_Msk            (0x1UL << I2C_CR1_PE_Pos)                     /*!< 0x00000001 */
12592 #define I2C_CR1_PE                I2C_CR1_PE_Msk                               /*!<Peripheral Enable                             */
12593 #define I2C_CR1_SMBUS_Pos         (1U)
12594 #define I2C_CR1_SMBUS_Msk         (0x1UL << I2C_CR1_SMBUS_Pos)                  /*!< 0x00000002 */
12595 #define I2C_CR1_SMBUS             I2C_CR1_SMBUS_Msk                            /*!<SMBus Mode                                    */
12596 #define I2C_CR1_SMBTYPE_Pos       (3U)
12597 #define I2C_CR1_SMBTYPE_Msk       (0x1UL << I2C_CR1_SMBTYPE_Pos)                /*!< 0x00000008 */
12598 #define I2C_CR1_SMBTYPE           I2C_CR1_SMBTYPE_Msk                          /*!<SMBus Type                                    */
12599 #define I2C_CR1_ENARP_Pos         (4U)
12600 #define I2C_CR1_ENARP_Msk         (0x1UL << I2C_CR1_ENARP_Pos)                  /*!< 0x00000010 */
12601 #define I2C_CR1_ENARP             I2C_CR1_ENARP_Msk                            /*!<ARP Enable                                    */
12602 #define I2C_CR1_ENPEC_Pos         (5U)
12603 #define I2C_CR1_ENPEC_Msk         (0x1UL << I2C_CR1_ENPEC_Pos)                  /*!< 0x00000020 */
12604 #define I2C_CR1_ENPEC             I2C_CR1_ENPEC_Msk                            /*!<PEC Enable                                    */
12605 #define I2C_CR1_ENGC_Pos          (6U)
12606 #define I2C_CR1_ENGC_Msk          (0x1UL << I2C_CR1_ENGC_Pos)                   /*!< 0x00000040 */
12607 #define I2C_CR1_ENGC              I2C_CR1_ENGC_Msk                             /*!<General Call Enable                           */
12608 #define I2C_CR1_NOSTRETCH_Pos     (7U)
12609 #define I2C_CR1_NOSTRETCH_Msk     (0x1UL << I2C_CR1_NOSTRETCH_Pos)              /*!< 0x00000080 */
12610 #define I2C_CR1_NOSTRETCH         I2C_CR1_NOSTRETCH_Msk                        /*!<Clock Stretching Disable (Slave mode)         */
12611 #define I2C_CR1_START_Pos         (8U)
12612 #define I2C_CR1_START_Msk         (0x1UL << I2C_CR1_START_Pos)                  /*!< 0x00000100 */
12613 #define I2C_CR1_START             I2C_CR1_START_Msk                            /*!<Start Generation                              */
12614 #define I2C_CR1_STOP_Pos          (9U)
12615 #define I2C_CR1_STOP_Msk          (0x1UL << I2C_CR1_STOP_Pos)                   /*!< 0x00000200 */
12616 #define I2C_CR1_STOP              I2C_CR1_STOP_Msk                             /*!<Stop Generation                               */
12617 #define I2C_CR1_ACK_Pos           (10U)
12618 #define I2C_CR1_ACK_Msk           (0x1UL << I2C_CR1_ACK_Pos)                    /*!< 0x00000400 */
12619 #define I2C_CR1_ACK               I2C_CR1_ACK_Msk                              /*!<Acknowledge Enable                            */
12620 #define I2C_CR1_POS_Pos           (11U)
12621 #define I2C_CR1_POS_Msk           (0x1UL << I2C_CR1_POS_Pos)                    /*!< 0x00000800 */
12622 #define I2C_CR1_POS               I2C_CR1_POS_Msk                              /*!<Acknowledge/PEC Position (for data reception) */
12623 #define I2C_CR1_PEC_Pos           (12U)
12624 #define I2C_CR1_PEC_Msk           (0x1UL << I2C_CR1_PEC_Pos)                    /*!< 0x00001000 */
12625 #define I2C_CR1_PEC               I2C_CR1_PEC_Msk                              /*!<Packet Error Checking                         */
12626 #define I2C_CR1_ALERT_Pos         (13U)
12627 #define I2C_CR1_ALERT_Msk         (0x1UL << I2C_CR1_ALERT_Pos)                  /*!< 0x00002000 */
12628 #define I2C_CR1_ALERT             I2C_CR1_ALERT_Msk                            /*!<SMBus Alert                                   */
12629 #define I2C_CR1_SWRST_Pos         (15U)
12630 #define I2C_CR1_SWRST_Msk         (0x1UL << I2C_CR1_SWRST_Pos)                  /*!< 0x00008000 */
12631 #define I2C_CR1_SWRST             I2C_CR1_SWRST_Msk                            /*!<Software Reset                                */
12632 
12633 /*******************  Bit definition for I2C_CR2 register  ********************/
12634 #define I2C_CR2_FREQ_Pos          (0U)
12635 #define I2C_CR2_FREQ_Msk          (0x3FUL << I2C_CR2_FREQ_Pos)                  /*!< 0x0000003F */
12636 #define I2C_CR2_FREQ              I2C_CR2_FREQ_Msk                             /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */
12637 #define I2C_CR2_FREQ_0            (0x01UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000001 */
12638 #define I2C_CR2_FREQ_1            (0x02UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000002 */
12639 #define I2C_CR2_FREQ_2            (0x04UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000004 */
12640 #define I2C_CR2_FREQ_3            (0x08UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000008 */
12641 #define I2C_CR2_FREQ_4            (0x10UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000010 */
12642 #define I2C_CR2_FREQ_5            (0x20UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000020 */
12643 
12644 #define I2C_CR2_ITERREN_Pos       (8U)
12645 #define I2C_CR2_ITERREN_Msk       (0x1UL << I2C_CR2_ITERREN_Pos)                /*!< 0x00000100 */
12646 #define I2C_CR2_ITERREN           I2C_CR2_ITERREN_Msk                          /*!<Error Interrupt Enable  */
12647 #define I2C_CR2_ITEVTEN_Pos       (9U)
12648 #define I2C_CR2_ITEVTEN_Msk       (0x1UL << I2C_CR2_ITEVTEN_Pos)                /*!< 0x00000200 */
12649 #define I2C_CR2_ITEVTEN           I2C_CR2_ITEVTEN_Msk                          /*!<Event Interrupt Enable  */
12650 #define I2C_CR2_ITBUFEN_Pos       (10U)
12651 #define I2C_CR2_ITBUFEN_Msk       (0x1UL << I2C_CR2_ITBUFEN_Pos)                /*!< 0x00000400 */
12652 #define I2C_CR2_ITBUFEN           I2C_CR2_ITBUFEN_Msk                          /*!<Buffer Interrupt Enable */
12653 #define I2C_CR2_DMAEN_Pos         (11U)
12654 #define I2C_CR2_DMAEN_Msk         (0x1UL << I2C_CR2_DMAEN_Pos)                  /*!< 0x00000800 */
12655 #define I2C_CR2_DMAEN             I2C_CR2_DMAEN_Msk                            /*!<DMA Requests Enable     */
12656 #define I2C_CR2_LAST_Pos          (12U)
12657 #define I2C_CR2_LAST_Msk          (0x1UL << I2C_CR2_LAST_Pos)                   /*!< 0x00001000 */
12658 #define I2C_CR2_LAST              I2C_CR2_LAST_Msk                             /*!<DMA Last Transfer       */
12659 
12660 /*******************  Bit definition for I2C_OAR1 register  *******************/
12661 #define I2C_OAR1_ADD1_7           0x000000FEU                                  /*!<Interface Address */
12662 #define I2C_OAR1_ADD8_9           0x00000300U                                  /*!<Interface Address */
12663 
12664 #define I2C_OAR1_ADD0_Pos         (0U)
12665 #define I2C_OAR1_ADD0_Msk         (0x1UL << I2C_OAR1_ADD0_Pos)                  /*!< 0x00000001 */
12666 #define I2C_OAR1_ADD0             I2C_OAR1_ADD0_Msk                            /*!<Bit 0 */
12667 #define I2C_OAR1_ADD1_Pos         (1U)
12668 #define I2C_OAR1_ADD1_Msk         (0x1UL << I2C_OAR1_ADD1_Pos)                  /*!< 0x00000002 */
12669 #define I2C_OAR1_ADD1             I2C_OAR1_ADD1_Msk                            /*!<Bit 1 */
12670 #define I2C_OAR1_ADD2_Pos         (2U)
12671 #define I2C_OAR1_ADD2_Msk         (0x1UL << I2C_OAR1_ADD2_Pos)                  /*!< 0x00000004 */
12672 #define I2C_OAR1_ADD2             I2C_OAR1_ADD2_Msk                            /*!<Bit 2 */
12673 #define I2C_OAR1_ADD3_Pos         (3U)
12674 #define I2C_OAR1_ADD3_Msk         (0x1UL << I2C_OAR1_ADD3_Pos)                  /*!< 0x00000008 */
12675 #define I2C_OAR1_ADD3             I2C_OAR1_ADD3_Msk                            /*!<Bit 3 */
12676 #define I2C_OAR1_ADD4_Pos         (4U)
12677 #define I2C_OAR1_ADD4_Msk         (0x1UL << I2C_OAR1_ADD4_Pos)                  /*!< 0x00000010 */
12678 #define I2C_OAR1_ADD4             I2C_OAR1_ADD4_Msk                            /*!<Bit 4 */
12679 #define I2C_OAR1_ADD5_Pos         (5U)
12680 #define I2C_OAR1_ADD5_Msk         (0x1UL << I2C_OAR1_ADD5_Pos)                  /*!< 0x00000020 */
12681 #define I2C_OAR1_ADD5             I2C_OAR1_ADD5_Msk                            /*!<Bit 5 */
12682 #define I2C_OAR1_ADD6_Pos         (6U)
12683 #define I2C_OAR1_ADD6_Msk         (0x1UL << I2C_OAR1_ADD6_Pos)                  /*!< 0x00000040 */
12684 #define I2C_OAR1_ADD6             I2C_OAR1_ADD6_Msk                            /*!<Bit 6 */
12685 #define I2C_OAR1_ADD7_Pos         (7U)
12686 #define I2C_OAR1_ADD7_Msk         (0x1UL << I2C_OAR1_ADD7_Pos)                  /*!< 0x00000080 */
12687 #define I2C_OAR1_ADD7             I2C_OAR1_ADD7_Msk                            /*!<Bit 7 */
12688 #define I2C_OAR1_ADD8_Pos         (8U)
12689 #define I2C_OAR1_ADD8_Msk         (0x1UL << I2C_OAR1_ADD8_Pos)                  /*!< 0x00000100 */
12690 #define I2C_OAR1_ADD8             I2C_OAR1_ADD8_Msk                            /*!<Bit 8 */
12691 #define I2C_OAR1_ADD9_Pos         (9U)
12692 #define I2C_OAR1_ADD9_Msk         (0x1UL << I2C_OAR1_ADD9_Pos)                  /*!< 0x00000200 */
12693 #define I2C_OAR1_ADD9             I2C_OAR1_ADD9_Msk                            /*!<Bit 9 */
12694 
12695 #define I2C_OAR1_ADDMODE_Pos      (15U)
12696 #define I2C_OAR1_ADDMODE_Msk      (0x1UL << I2C_OAR1_ADDMODE_Pos)               /*!< 0x00008000 */
12697 #define I2C_OAR1_ADDMODE          I2C_OAR1_ADDMODE_Msk                         /*!<Addressing Mode (Slave mode) */
12698 
12699 /*******************  Bit definition for I2C_OAR2 register  *******************/
12700 #define I2C_OAR2_ENDUAL_Pos       (0U)
12701 #define I2C_OAR2_ENDUAL_Msk       (0x1UL << I2C_OAR2_ENDUAL_Pos)                /*!< 0x00000001 */
12702 #define I2C_OAR2_ENDUAL           I2C_OAR2_ENDUAL_Msk                          /*!<Dual addressing mode enable */
12703 #define I2C_OAR2_ADD2_Pos         (1U)
12704 #define I2C_OAR2_ADD2_Msk         (0x7FUL << I2C_OAR2_ADD2_Pos)                 /*!< 0x000000FE */
12705 #define I2C_OAR2_ADD2             I2C_OAR2_ADD2_Msk                            /*!<Interface address           */
12706 
12707 /********************  Bit definition for I2C_DR register  ********************/
12708 #define I2C_DR_DR_Pos             (0U)
12709 #define I2C_DR_DR_Msk             (0xFFUL << I2C_DR_DR_Pos)                     /*!< 0x000000FF */
12710 #define I2C_DR_DR                 I2C_DR_DR_Msk                                /*!<8-bit Data Register         */
12711 
12712 /*******************  Bit definition for I2C_SR1 register  ********************/
12713 #define I2C_SR1_SB_Pos            (0U)
12714 #define I2C_SR1_SB_Msk            (0x1UL << I2C_SR1_SB_Pos)                     /*!< 0x00000001 */
12715 #define I2C_SR1_SB                I2C_SR1_SB_Msk                               /*!<Start Bit (Master mode)                         */
12716 #define I2C_SR1_ADDR_Pos          (1U)
12717 #define I2C_SR1_ADDR_Msk          (0x1UL << I2C_SR1_ADDR_Pos)                   /*!< 0x00000002 */
12718 #define I2C_SR1_ADDR              I2C_SR1_ADDR_Msk                             /*!<Address sent (master mode)/matched (slave mode) */
12719 #define I2C_SR1_BTF_Pos           (2U)
12720 #define I2C_SR1_BTF_Msk           (0x1UL << I2C_SR1_BTF_Pos)                    /*!< 0x00000004 */
12721 #define I2C_SR1_BTF               I2C_SR1_BTF_Msk                              /*!<Byte Transfer Finished                          */
12722 #define I2C_SR1_ADD10_Pos         (3U)
12723 #define I2C_SR1_ADD10_Msk         (0x1UL << I2C_SR1_ADD10_Pos)                  /*!< 0x00000008 */
12724 #define I2C_SR1_ADD10             I2C_SR1_ADD10_Msk                            /*!<10-bit header sent (Master mode)                */
12725 #define I2C_SR1_STOPF_Pos         (4U)
12726 #define I2C_SR1_STOPF_Msk         (0x1UL << I2C_SR1_STOPF_Pos)                  /*!< 0x00000010 */
12727 #define I2C_SR1_STOPF             I2C_SR1_STOPF_Msk                            /*!<Stop detection (Slave mode)                     */
12728 #define I2C_SR1_RXNE_Pos          (6U)
12729 #define I2C_SR1_RXNE_Msk          (0x1UL << I2C_SR1_RXNE_Pos)                   /*!< 0x00000040 */
12730 #define I2C_SR1_RXNE              I2C_SR1_RXNE_Msk                             /*!<Data Register not Empty (receivers)             */
12731 #define I2C_SR1_TXE_Pos           (7U)
12732 #define I2C_SR1_TXE_Msk           (0x1UL << I2C_SR1_TXE_Pos)                    /*!< 0x00000080 */
12733 #define I2C_SR1_TXE               I2C_SR1_TXE_Msk                              /*!<Data Register Empty (transmitters)              */
12734 #define I2C_SR1_BERR_Pos          (8U)
12735 #define I2C_SR1_BERR_Msk          (0x1UL << I2C_SR1_BERR_Pos)                   /*!< 0x00000100 */
12736 #define I2C_SR1_BERR              I2C_SR1_BERR_Msk                             /*!<Bus Error                                       */
12737 #define I2C_SR1_ARLO_Pos          (9U)
12738 #define I2C_SR1_ARLO_Msk          (0x1UL << I2C_SR1_ARLO_Pos)                   /*!< 0x00000200 */
12739 #define I2C_SR1_ARLO              I2C_SR1_ARLO_Msk                             /*!<Arbitration Lost (master mode)                  */
12740 #define I2C_SR1_AF_Pos            (10U)
12741 #define I2C_SR1_AF_Msk            (0x1UL << I2C_SR1_AF_Pos)                     /*!< 0x00000400 */
12742 #define I2C_SR1_AF                I2C_SR1_AF_Msk                               /*!<Acknowledge Failure                             */
12743 #define I2C_SR1_OVR_Pos           (11U)
12744 #define I2C_SR1_OVR_Msk           (0x1UL << I2C_SR1_OVR_Pos)                    /*!< 0x00000800 */
12745 #define I2C_SR1_OVR               I2C_SR1_OVR_Msk                              /*!<Overrun/Underrun                                */
12746 #define I2C_SR1_PECERR_Pos        (12U)
12747 #define I2C_SR1_PECERR_Msk        (0x1UL << I2C_SR1_PECERR_Pos)                 /*!< 0x00001000 */
12748 #define I2C_SR1_PECERR            I2C_SR1_PECERR_Msk                           /*!<PEC Error in reception                          */
12749 #define I2C_SR1_TIMEOUT_Pos       (14U)
12750 #define I2C_SR1_TIMEOUT_Msk       (0x1UL << I2C_SR1_TIMEOUT_Pos)                /*!< 0x00004000 */
12751 #define I2C_SR1_TIMEOUT           I2C_SR1_TIMEOUT_Msk                          /*!<Timeout or Tlow Error                           */
12752 #define I2C_SR1_SMBALERT_Pos      (15U)
12753 #define I2C_SR1_SMBALERT_Msk      (0x1UL << I2C_SR1_SMBALERT_Pos)               /*!< 0x00008000 */
12754 #define I2C_SR1_SMBALERT          I2C_SR1_SMBALERT_Msk                         /*!<SMBus Alert                                     */
12755 
12756 /*******************  Bit definition for I2C_SR2 register  ********************/
12757 #define I2C_SR2_MSL_Pos           (0U)
12758 #define I2C_SR2_MSL_Msk           (0x1UL << I2C_SR2_MSL_Pos)                    /*!< 0x00000001 */
12759 #define I2C_SR2_MSL               I2C_SR2_MSL_Msk                              /*!<Master/Slave                                    */
12760 #define I2C_SR2_BUSY_Pos          (1U)
12761 #define I2C_SR2_BUSY_Msk          (0x1UL << I2C_SR2_BUSY_Pos)                   /*!< 0x00000002 */
12762 #define I2C_SR2_BUSY              I2C_SR2_BUSY_Msk                             /*!<Bus Busy                                        */
12763 #define I2C_SR2_TRA_Pos           (2U)
12764 #define I2C_SR2_TRA_Msk           (0x1UL << I2C_SR2_TRA_Pos)                    /*!< 0x00000004 */
12765 #define I2C_SR2_TRA               I2C_SR2_TRA_Msk                              /*!<Transmitter/Receiver                            */
12766 #define I2C_SR2_GENCALL_Pos       (4U)
12767 #define I2C_SR2_GENCALL_Msk       (0x1UL << I2C_SR2_GENCALL_Pos)                /*!< 0x00000010 */
12768 #define I2C_SR2_GENCALL           I2C_SR2_GENCALL_Msk                          /*!<General Call Address (Slave mode)               */
12769 #define I2C_SR2_SMBDEFAULT_Pos    (5U)
12770 #define I2C_SR2_SMBDEFAULT_Msk    (0x1UL << I2C_SR2_SMBDEFAULT_Pos)             /*!< 0x00000020 */
12771 #define I2C_SR2_SMBDEFAULT        I2C_SR2_SMBDEFAULT_Msk                       /*!<SMBus Device Default Address (Slave mode)       */
12772 #define I2C_SR2_SMBHOST_Pos       (6U)
12773 #define I2C_SR2_SMBHOST_Msk       (0x1UL << I2C_SR2_SMBHOST_Pos)                /*!< 0x00000040 */
12774 #define I2C_SR2_SMBHOST           I2C_SR2_SMBHOST_Msk                          /*!<SMBus Host Header (Slave mode)                  */
12775 #define I2C_SR2_DUALF_Pos         (7U)
12776 #define I2C_SR2_DUALF_Msk         (0x1UL << I2C_SR2_DUALF_Pos)                  /*!< 0x00000080 */
12777 #define I2C_SR2_DUALF             I2C_SR2_DUALF_Msk                            /*!<Dual Flag (Slave mode)                          */
12778 #define I2C_SR2_PEC_Pos           (8U)
12779 #define I2C_SR2_PEC_Msk           (0xFFUL << I2C_SR2_PEC_Pos)                   /*!< 0x0000FF00 */
12780 #define I2C_SR2_PEC               I2C_SR2_PEC_Msk                              /*!<Packet Error Checking Register                  */
12781 
12782 /*******************  Bit definition for I2C_CCR register  ********************/
12783 #define I2C_CCR_CCR_Pos           (0U)
12784 #define I2C_CCR_CCR_Msk           (0xFFFUL << I2C_CCR_CCR_Pos)                  /*!< 0x00000FFF */
12785 #define I2C_CCR_CCR               I2C_CCR_CCR_Msk                              /*!<Clock Control Register in Fast/Standard mode (Master mode) */
12786 #define I2C_CCR_DUTY_Pos          (14U)
12787 #define I2C_CCR_DUTY_Msk          (0x1UL << I2C_CCR_DUTY_Pos)                   /*!< 0x00004000 */
12788 #define I2C_CCR_DUTY              I2C_CCR_DUTY_Msk                             /*!<Fast Mode Duty Cycle                                       */
12789 #define I2C_CCR_FS_Pos            (15U)
12790 #define I2C_CCR_FS_Msk            (0x1UL << I2C_CCR_FS_Pos)                     /*!< 0x00008000 */
12791 #define I2C_CCR_FS                I2C_CCR_FS_Msk                               /*!<I2C Master Mode Selection                                  */
12792 
12793 /******************  Bit definition for I2C_TRISE register  *******************/
12794 #define I2C_TRISE_TRISE_Pos       (0U)
12795 #define I2C_TRISE_TRISE_Msk       (0x3FUL << I2C_TRISE_TRISE_Pos)               /*!< 0x0000003F */
12796 #define I2C_TRISE_TRISE           I2C_TRISE_TRISE_Msk                          /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
12797 
12798 /******************  Bit definition for I2C_FLTR register  *******************/
12799 #define I2C_FLTR_DNF_Pos          (0U)
12800 #define I2C_FLTR_DNF_Msk          (0xFUL << I2C_FLTR_DNF_Pos)                   /*!< 0x0000000F */
12801 #define I2C_FLTR_DNF              I2C_FLTR_DNF_Msk                             /*!<Digital Noise Filter */
12802 #define I2C_FLTR_ANOFF_Pos        (4U)
12803 #define I2C_FLTR_ANOFF_Msk        (0x1UL << I2C_FLTR_ANOFF_Pos)                 /*!< 0x00000010 */
12804 #define I2C_FLTR_ANOFF            I2C_FLTR_ANOFF_Msk                           /*!<Analog Noise Filter OFF */
12805 
12806 /******************************************************************************/
12807 /*                                                                            */
12808 /*                           Independent WATCHDOG                             */
12809 /*                                                                            */
12810 /******************************************************************************/
12811 /*******************  Bit definition for IWDG_KR register  ********************/
12812 #define IWDG_KR_KEY_Pos     (0U)
12813 #define IWDG_KR_KEY_Msk     (0xFFFFUL << IWDG_KR_KEY_Pos)                       /*!< 0x0000FFFF */
12814 #define IWDG_KR_KEY         IWDG_KR_KEY_Msk                                    /*!<Key value (write only, read 0000h)  */
12815 
12816 /*******************  Bit definition for IWDG_PR register  ********************/
12817 #define IWDG_PR_PR_Pos      (0U)
12818 #define IWDG_PR_PR_Msk      (0x7UL << IWDG_PR_PR_Pos)                           /*!< 0x00000007 */
12819 #define IWDG_PR_PR          IWDG_PR_PR_Msk                                     /*!<PR[2:0] (Prescaler divider)         */
12820 #define IWDG_PR_PR_0        (0x1UL << IWDG_PR_PR_Pos)                           /*!< 0x01 */
12821 #define IWDG_PR_PR_1        (0x2UL << IWDG_PR_PR_Pos)                           /*!< 0x02 */
12822 #define IWDG_PR_PR_2        (0x4UL << IWDG_PR_PR_Pos)                           /*!< 0x04 */
12823 
12824 /*******************  Bit definition for IWDG_RLR register  *******************/
12825 #define IWDG_RLR_RL_Pos     (0U)
12826 #define IWDG_RLR_RL_Msk     (0xFFFUL << IWDG_RLR_RL_Pos)                        /*!< 0x00000FFF */
12827 #define IWDG_RLR_RL         IWDG_RLR_RL_Msk                                    /*!<Watchdog counter reload value        */
12828 
12829 /*******************  Bit definition for IWDG_SR register  ********************/
12830 #define IWDG_SR_PVU_Pos     (0U)
12831 #define IWDG_SR_PVU_Msk     (0x1UL << IWDG_SR_PVU_Pos)                          /*!< 0x00000001 */
12832 #define IWDG_SR_PVU         IWDG_SR_PVU_Msk                                    /*!<Watchdog prescaler value update      */
12833 #define IWDG_SR_RVU_Pos     (1U)
12834 #define IWDG_SR_RVU_Msk     (0x1UL << IWDG_SR_RVU_Pos)                          /*!< 0x00000002 */
12835 #define IWDG_SR_RVU         IWDG_SR_RVU_Msk                                    /*!<Watchdog counter reload value update */
12836 
12837 
12838 /******************************************************************************/
12839 /*                                                                            */
12840 /*                      LCD-TFT Display Controller (LTDC)                     */
12841 /*                                                                            */
12842 /******************************************************************************/
12843 
12844 /********************  Bit definition for LTDC_SSCR register  *****************/
12845 
12846 #define LTDC_SSCR_VSH_Pos            (0U)
12847 #define LTDC_SSCR_VSH_Msk            (0x7FFUL << LTDC_SSCR_VSH_Pos)             /*!< 0x000007FF */
12848 #define LTDC_SSCR_VSH                LTDC_SSCR_VSH_Msk                         /*!< Vertical Synchronization Height */
12849 #define LTDC_SSCR_HSW_Pos            (16U)
12850 #define LTDC_SSCR_HSW_Msk            (0xFFFUL << LTDC_SSCR_HSW_Pos)             /*!< 0x0FFF0000 */
12851 #define LTDC_SSCR_HSW                LTDC_SSCR_HSW_Msk                         /*!< Horizontal Synchronization Width */
12852 
12853 /********************  Bit definition for LTDC_BPCR register  *****************/
12854 
12855 #define LTDC_BPCR_AVBP_Pos           (0U)
12856 #define LTDC_BPCR_AVBP_Msk           (0x7FFUL << LTDC_BPCR_AVBP_Pos)            /*!< 0x000007FF */
12857 #define LTDC_BPCR_AVBP               LTDC_BPCR_AVBP_Msk                        /*!< Accumulated Vertical Back Porch */
12858 #define LTDC_BPCR_AHBP_Pos           (16U)
12859 #define LTDC_BPCR_AHBP_Msk           (0xFFFUL << LTDC_BPCR_AHBP_Pos)            /*!< 0x0FFF0000 */
12860 #define LTDC_BPCR_AHBP               LTDC_BPCR_AHBP_Msk                        /*!< Accumulated Horizontal Back Porch */
12861 
12862 /********************  Bit definition for LTDC_AWCR register  *****************/
12863 
12864 #define LTDC_AWCR_AAH_Pos            (0U)
12865 #define LTDC_AWCR_AAH_Msk            (0x7FFUL << LTDC_AWCR_AAH_Pos)             /*!< 0x000007FF */
12866 #define LTDC_AWCR_AAH                LTDC_AWCR_AAH_Msk                         /*!< Accumulated Active heigh */
12867 #define LTDC_AWCR_AAW_Pos            (16U)
12868 #define LTDC_AWCR_AAW_Msk            (0xFFFUL << LTDC_AWCR_AAW_Pos)             /*!< 0x0FFF0000 */
12869 #define LTDC_AWCR_AAW                LTDC_AWCR_AAW_Msk                         /*!< Accumulated Active Width */
12870 
12871 /********************  Bit definition for LTDC_TWCR register  *****************/
12872 
12873 #define LTDC_TWCR_TOTALH_Pos         (0U)
12874 #define LTDC_TWCR_TOTALH_Msk         (0x7FFUL << LTDC_TWCR_TOTALH_Pos)          /*!< 0x000007FF */
12875 #define LTDC_TWCR_TOTALH             LTDC_TWCR_TOTALH_Msk                      /*!< Total Heigh */
12876 #define LTDC_TWCR_TOTALW_Pos         (16U)
12877 #define LTDC_TWCR_TOTALW_Msk         (0xFFFUL << LTDC_TWCR_TOTALW_Pos)          /*!< 0x0FFF0000 */
12878 #define LTDC_TWCR_TOTALW             LTDC_TWCR_TOTALW_Msk                      /*!< Total Width */
12879 
12880 /********************  Bit definition for LTDC_GCR register  ******************/
12881 
12882 #define LTDC_GCR_LTDCEN_Pos          (0U)
12883 #define LTDC_GCR_LTDCEN_Msk          (0x1UL << LTDC_GCR_LTDCEN_Pos)             /*!< 0x00000001 */
12884 #define LTDC_GCR_LTDCEN              LTDC_GCR_LTDCEN_Msk                       /*!< LCD-TFT controller enable bit */
12885 #define LTDC_GCR_DBW_Pos             (4U)
12886 #define LTDC_GCR_DBW_Msk             (0x7UL << LTDC_GCR_DBW_Pos)                /*!< 0x00000070 */
12887 #define LTDC_GCR_DBW                 LTDC_GCR_DBW_Msk                          /*!< Dither Blue Width */
12888 #define LTDC_GCR_DGW_Pos             (8U)
12889 #define LTDC_GCR_DGW_Msk             (0x7UL << LTDC_GCR_DGW_Pos)                /*!< 0x00000700 */
12890 #define LTDC_GCR_DGW                 LTDC_GCR_DGW_Msk                          /*!< Dither Green Width */
12891 #define LTDC_GCR_DRW_Pos             (12U)
12892 #define LTDC_GCR_DRW_Msk             (0x7UL << LTDC_GCR_DRW_Pos)                /*!< 0x00007000 */
12893 #define LTDC_GCR_DRW                 LTDC_GCR_DRW_Msk                          /*!< Dither Red Width */
12894 #define LTDC_GCR_DEN_Pos             (16U)
12895 #define LTDC_GCR_DEN_Msk             (0x1UL << LTDC_GCR_DEN_Pos)                /*!< 0x00010000 */
12896 #define LTDC_GCR_DEN                 LTDC_GCR_DEN_Msk                          /*!< Dither Enable */
12897 #define LTDC_GCR_PCPOL_Pos           (28U)
12898 #define LTDC_GCR_PCPOL_Msk           (0x1UL << LTDC_GCR_PCPOL_Pos)              /*!< 0x10000000 */
12899 #define LTDC_GCR_PCPOL               LTDC_GCR_PCPOL_Msk                        /*!< Pixel Clock Polarity */
12900 #define LTDC_GCR_DEPOL_Pos           (29U)
12901 #define LTDC_GCR_DEPOL_Msk           (0x1UL << LTDC_GCR_DEPOL_Pos)              /*!< 0x20000000 */
12902 #define LTDC_GCR_DEPOL               LTDC_GCR_DEPOL_Msk                        /*!< Data Enable Polarity */
12903 #define LTDC_GCR_VSPOL_Pos           (30U)
12904 #define LTDC_GCR_VSPOL_Msk           (0x1UL << LTDC_GCR_VSPOL_Pos)              /*!< 0x40000000 */
12905 #define LTDC_GCR_VSPOL               LTDC_GCR_VSPOL_Msk                        /*!< Vertical Synchronization Polarity */
12906 #define LTDC_GCR_HSPOL_Pos           (31U)
12907 #define LTDC_GCR_HSPOL_Msk           (0x1UL << LTDC_GCR_HSPOL_Pos)              /*!< 0x80000000 */
12908 #define LTDC_GCR_HSPOL               LTDC_GCR_HSPOL_Msk                        /*!< Horizontal Synchronization Polarity */
12909 
12910 /* Legacy defines */
12911 #define LTDC_GCR_DTEN                       LTDC_GCR_DEN
12912 
12913 /********************  Bit definition for LTDC_SRCR register  *****************/
12914 
12915 #define LTDC_SRCR_IMR_Pos            (0U)
12916 #define LTDC_SRCR_IMR_Msk            (0x1UL << LTDC_SRCR_IMR_Pos)               /*!< 0x00000001 */
12917 #define LTDC_SRCR_IMR                LTDC_SRCR_IMR_Msk                         /*!< Immediate Reload */
12918 #define LTDC_SRCR_VBR_Pos            (1U)
12919 #define LTDC_SRCR_VBR_Msk            (0x1UL << LTDC_SRCR_VBR_Pos)               /*!< 0x00000002 */
12920 #define LTDC_SRCR_VBR                LTDC_SRCR_VBR_Msk                         /*!< Vertical Blanking Reload */
12921 
12922 /********************  Bit definition for LTDC_BCCR register  *****************/
12923 
12924 #define LTDC_BCCR_BCBLUE_Pos         (0U)
12925 #define LTDC_BCCR_BCBLUE_Msk         (0xFFUL << LTDC_BCCR_BCBLUE_Pos)           /*!< 0x000000FF */
12926 #define LTDC_BCCR_BCBLUE             LTDC_BCCR_BCBLUE_Msk                      /*!< Background Blue value */
12927 #define LTDC_BCCR_BCGREEN_Pos        (8U)
12928 #define LTDC_BCCR_BCGREEN_Msk        (0xFFUL << LTDC_BCCR_BCGREEN_Pos)          /*!< 0x0000FF00 */
12929 #define LTDC_BCCR_BCGREEN            LTDC_BCCR_BCGREEN_Msk                     /*!< Background Green value */
12930 #define LTDC_BCCR_BCRED_Pos          (16U)
12931 #define LTDC_BCCR_BCRED_Msk          (0xFFUL << LTDC_BCCR_BCRED_Pos)            /*!< 0x00FF0000 */
12932 #define LTDC_BCCR_BCRED              LTDC_BCCR_BCRED_Msk                       /*!< Background Red value */
12933 
12934 /********************  Bit definition for LTDC_IER register  ******************/
12935 
12936 #define LTDC_IER_LIE_Pos             (0U)
12937 #define LTDC_IER_LIE_Msk             (0x1UL << LTDC_IER_LIE_Pos)                /*!< 0x00000001 */
12938 #define LTDC_IER_LIE                 LTDC_IER_LIE_Msk                          /*!< Line Interrupt Enable */
12939 #define LTDC_IER_FUIE_Pos            (1U)
12940 #define LTDC_IER_FUIE_Msk            (0x1UL << LTDC_IER_FUIE_Pos)               /*!< 0x00000002 */
12941 #define LTDC_IER_FUIE                LTDC_IER_FUIE_Msk                         /*!< FIFO Underrun Interrupt Enable */
12942 #define LTDC_IER_TERRIE_Pos          (2U)
12943 #define LTDC_IER_TERRIE_Msk          (0x1UL << LTDC_IER_TERRIE_Pos)             /*!< 0x00000004 */
12944 #define LTDC_IER_TERRIE              LTDC_IER_TERRIE_Msk                       /*!< Transfer Error Interrupt Enable */
12945 #define LTDC_IER_RRIE_Pos            (3U)
12946 #define LTDC_IER_RRIE_Msk            (0x1UL << LTDC_IER_RRIE_Pos)               /*!< 0x00000008 */
12947 #define LTDC_IER_RRIE                LTDC_IER_RRIE_Msk                         /*!< Register Reload interrupt enable */
12948 
12949 /********************  Bit definition for LTDC_ISR register  ******************/
12950 
12951 #define LTDC_ISR_LIF_Pos             (0U)
12952 #define LTDC_ISR_LIF_Msk             (0x1UL << LTDC_ISR_LIF_Pos)                /*!< 0x00000001 */
12953 #define LTDC_ISR_LIF                 LTDC_ISR_LIF_Msk                          /*!< Line Interrupt Flag */
12954 #define LTDC_ISR_FUIF_Pos            (1U)
12955 #define LTDC_ISR_FUIF_Msk            (0x1UL << LTDC_ISR_FUIF_Pos)               /*!< 0x00000002 */
12956 #define LTDC_ISR_FUIF                LTDC_ISR_FUIF_Msk                         /*!< FIFO Underrun Interrupt Flag */
12957 #define LTDC_ISR_TERRIF_Pos          (2U)
12958 #define LTDC_ISR_TERRIF_Msk          (0x1UL << LTDC_ISR_TERRIF_Pos)             /*!< 0x00000004 */
12959 #define LTDC_ISR_TERRIF              LTDC_ISR_TERRIF_Msk                       /*!< Transfer Error Interrupt Flag */
12960 #define LTDC_ISR_RRIF_Pos            (3U)
12961 #define LTDC_ISR_RRIF_Msk            (0x1UL << LTDC_ISR_RRIF_Pos)               /*!< 0x00000008 */
12962 #define LTDC_ISR_RRIF                LTDC_ISR_RRIF_Msk                         /*!< Register Reload interrupt Flag */
12963 
12964 /********************  Bit definition for LTDC_ICR register  ******************/
12965 
12966 #define LTDC_ICR_CLIF_Pos            (0U)
12967 #define LTDC_ICR_CLIF_Msk            (0x1UL << LTDC_ICR_CLIF_Pos)               /*!< 0x00000001 */
12968 #define LTDC_ICR_CLIF                LTDC_ICR_CLIF_Msk                         /*!< Clears the Line Interrupt Flag */
12969 #define LTDC_ICR_CFUIF_Pos           (1U)
12970 #define LTDC_ICR_CFUIF_Msk           (0x1UL << LTDC_ICR_CFUIF_Pos)              /*!< 0x00000002 */
12971 #define LTDC_ICR_CFUIF               LTDC_ICR_CFUIF_Msk                        /*!< Clears the FIFO Underrun Interrupt Flag */
12972 #define LTDC_ICR_CTERRIF_Pos         (2U)
12973 #define LTDC_ICR_CTERRIF_Msk         (0x1UL << LTDC_ICR_CTERRIF_Pos)            /*!< 0x00000004 */
12974 #define LTDC_ICR_CTERRIF             LTDC_ICR_CTERRIF_Msk                      /*!< Clears the Transfer Error Interrupt Flag */
12975 #define LTDC_ICR_CRRIF_Pos           (3U)
12976 #define LTDC_ICR_CRRIF_Msk           (0x1UL << LTDC_ICR_CRRIF_Pos)              /*!< 0x00000008 */
12977 #define LTDC_ICR_CRRIF               LTDC_ICR_CRRIF_Msk                        /*!< Clears Register Reload interrupt Flag */
12978 
12979 /********************  Bit definition for LTDC_LIPCR register  ****************/
12980 
12981 #define LTDC_LIPCR_LIPOS_Pos         (0U)
12982 #define LTDC_LIPCR_LIPOS_Msk         (0x7FFUL << LTDC_LIPCR_LIPOS_Pos)          /*!< 0x000007FF */
12983 #define LTDC_LIPCR_LIPOS             LTDC_LIPCR_LIPOS_Msk                      /*!< Line Interrupt Position */
12984 
12985 /********************  Bit definition for LTDC_CPSR register  *****************/
12986 
12987 #define LTDC_CPSR_CYPOS_Pos          (0U)
12988 #define LTDC_CPSR_CYPOS_Msk          (0xFFFFUL << LTDC_CPSR_CYPOS_Pos)          /*!< 0x0000FFFF */
12989 #define LTDC_CPSR_CYPOS              LTDC_CPSR_CYPOS_Msk                       /*!< Current Y Position */
12990 #define LTDC_CPSR_CXPOS_Pos          (16U)
12991 #define LTDC_CPSR_CXPOS_Msk          (0xFFFFUL << LTDC_CPSR_CXPOS_Pos)          /*!< 0xFFFF0000 */
12992 #define LTDC_CPSR_CXPOS              LTDC_CPSR_CXPOS_Msk                       /*!< Current X Position */
12993 
12994 /********************  Bit definition for LTDC_CDSR register  *****************/
12995 
12996 #define LTDC_CDSR_VDES_Pos           (0U)
12997 #define LTDC_CDSR_VDES_Msk           (0x1UL << LTDC_CDSR_VDES_Pos)              /*!< 0x00000001 */
12998 #define LTDC_CDSR_VDES               LTDC_CDSR_VDES_Msk                        /*!< Vertical Data Enable Status */
12999 #define LTDC_CDSR_HDES_Pos           (1U)
13000 #define LTDC_CDSR_HDES_Msk           (0x1UL << LTDC_CDSR_HDES_Pos)              /*!< 0x00000002 */
13001 #define LTDC_CDSR_HDES               LTDC_CDSR_HDES_Msk                        /*!< Horizontal Data Enable Status */
13002 #define LTDC_CDSR_VSYNCS_Pos         (2U)
13003 #define LTDC_CDSR_VSYNCS_Msk         (0x1UL << LTDC_CDSR_VSYNCS_Pos)            /*!< 0x00000004 */
13004 #define LTDC_CDSR_VSYNCS             LTDC_CDSR_VSYNCS_Msk                      /*!< Vertical Synchronization Status */
13005 #define LTDC_CDSR_HSYNCS_Pos         (3U)
13006 #define LTDC_CDSR_HSYNCS_Msk         (0x1UL << LTDC_CDSR_HSYNCS_Pos)            /*!< 0x00000008 */
13007 #define LTDC_CDSR_HSYNCS             LTDC_CDSR_HSYNCS_Msk                      /*!< Horizontal Synchronization Status */
13008 
13009 /********************  Bit definition for LTDC_LxCR register  *****************/
13010 
13011 #define LTDC_LxCR_LEN_Pos            (0U)
13012 #define LTDC_LxCR_LEN_Msk            (0x1UL << LTDC_LxCR_LEN_Pos)               /*!< 0x00000001 */
13013 #define LTDC_LxCR_LEN                LTDC_LxCR_LEN_Msk                         /*!< Layer Enable */
13014 #define LTDC_LxCR_COLKEN_Pos         (1U)
13015 #define LTDC_LxCR_COLKEN_Msk         (0x1UL << LTDC_LxCR_COLKEN_Pos)            /*!< 0x00000002 */
13016 #define LTDC_LxCR_COLKEN             LTDC_LxCR_COLKEN_Msk                      /*!< Color Keying Enable */
13017 #define LTDC_LxCR_CLUTEN_Pos         (4U)
13018 #define LTDC_LxCR_CLUTEN_Msk         (0x1UL << LTDC_LxCR_CLUTEN_Pos)            /*!< 0x00000010 */
13019 #define LTDC_LxCR_CLUTEN             LTDC_LxCR_CLUTEN_Msk                      /*!< Color Lockup Table Enable */
13020 
13021 /********************  Bit definition for LTDC_LxWHPCR register  **************/
13022 
13023 #define LTDC_LxWHPCR_WHSTPOS_Pos     (0U)
13024 #define LTDC_LxWHPCR_WHSTPOS_Msk     (0xFFFUL << LTDC_LxWHPCR_WHSTPOS_Pos)      /*!< 0x00000FFF */
13025 #define LTDC_LxWHPCR_WHSTPOS         LTDC_LxWHPCR_WHSTPOS_Msk                  /*!< Window Horizontal Start Position */
13026 #define LTDC_LxWHPCR_WHSPPOS_Pos     (16U)
13027 #define LTDC_LxWHPCR_WHSPPOS_Msk     (0xFFFFUL << LTDC_LxWHPCR_WHSPPOS_Pos)     /*!< 0xFFFF0000 */
13028 #define LTDC_LxWHPCR_WHSPPOS         LTDC_LxWHPCR_WHSPPOS_Msk                  /*!< Window Horizontal Stop Position */
13029 
13030 /********************  Bit definition for LTDC_LxWVPCR register  **************/
13031 
13032 #define LTDC_LxWVPCR_WVSTPOS_Pos     (0U)
13033 #define LTDC_LxWVPCR_WVSTPOS_Msk     (0xFFFUL << LTDC_LxWVPCR_WVSTPOS_Pos)      /*!< 0x00000FFF */
13034 #define LTDC_LxWVPCR_WVSTPOS         LTDC_LxWVPCR_WVSTPOS_Msk                  /*!< Window Vertical Start Position */
13035 #define LTDC_LxWVPCR_WVSPPOS_Pos     (16U)
13036 #define LTDC_LxWVPCR_WVSPPOS_Msk     (0xFFFFUL << LTDC_LxWVPCR_WVSPPOS_Pos)     /*!< 0xFFFF0000 */
13037 #define LTDC_LxWVPCR_WVSPPOS         LTDC_LxWVPCR_WVSPPOS_Msk                  /*!< Window Vertical Stop Position */
13038 
13039 /********************  Bit definition for LTDC_LxCKCR register  ***************/
13040 
13041 #define LTDC_LxCKCR_CKBLUE_Pos       (0U)
13042 #define LTDC_LxCKCR_CKBLUE_Msk       (0xFFUL << LTDC_LxCKCR_CKBLUE_Pos)         /*!< 0x000000FF */
13043 #define LTDC_LxCKCR_CKBLUE           LTDC_LxCKCR_CKBLUE_Msk                    /*!< Color Key Blue value */
13044 #define LTDC_LxCKCR_CKGREEN_Pos      (8U)
13045 #define LTDC_LxCKCR_CKGREEN_Msk      (0xFFUL << LTDC_LxCKCR_CKGREEN_Pos)        /*!< 0x0000FF00 */
13046 #define LTDC_LxCKCR_CKGREEN          LTDC_LxCKCR_CKGREEN_Msk                   /*!< Color Key Green value */
13047 #define LTDC_LxCKCR_CKRED_Pos        (16U)
13048 #define LTDC_LxCKCR_CKRED_Msk        (0xFFUL << LTDC_LxCKCR_CKRED_Pos)          /*!< 0x00FF0000 */
13049 #define LTDC_LxCKCR_CKRED            LTDC_LxCKCR_CKRED_Msk                     /*!< Color Key Red value */
13050 
13051 /********************  Bit definition for LTDC_LxPFCR register  ***************/
13052 
13053 #define LTDC_LxPFCR_PF_Pos           (0U)
13054 #define LTDC_LxPFCR_PF_Msk           (0x7UL << LTDC_LxPFCR_PF_Pos)              /*!< 0x00000007 */
13055 #define LTDC_LxPFCR_PF               LTDC_LxPFCR_PF_Msk                        /*!< Pixel Format */
13056 
13057 /********************  Bit definition for LTDC_LxCACR register  ***************/
13058 
13059 #define LTDC_LxCACR_CONSTA_Pos       (0U)
13060 #define LTDC_LxCACR_CONSTA_Msk       (0xFFUL << LTDC_LxCACR_CONSTA_Pos)         /*!< 0x000000FF */
13061 #define LTDC_LxCACR_CONSTA           LTDC_LxCACR_CONSTA_Msk                    /*!< Constant Alpha */
13062 
13063 /********************  Bit definition for LTDC_LxDCCR register  ***************/
13064 
13065 #define LTDC_LxDCCR_DCBLUE_Pos       (0U)
13066 #define LTDC_LxDCCR_DCBLUE_Msk       (0xFFUL << LTDC_LxDCCR_DCBLUE_Pos)         /*!< 0x000000FF */
13067 #define LTDC_LxDCCR_DCBLUE           LTDC_LxDCCR_DCBLUE_Msk                    /*!< Default Color Blue */
13068 #define LTDC_LxDCCR_DCGREEN_Pos      (8U)
13069 #define LTDC_LxDCCR_DCGREEN_Msk      (0xFFUL << LTDC_LxDCCR_DCGREEN_Pos)        /*!< 0x0000FF00 */
13070 #define LTDC_LxDCCR_DCGREEN          LTDC_LxDCCR_DCGREEN_Msk                   /*!< Default Color Green */
13071 #define LTDC_LxDCCR_DCRED_Pos        (16U)
13072 #define LTDC_LxDCCR_DCRED_Msk        (0xFFUL << LTDC_LxDCCR_DCRED_Pos)          /*!< 0x00FF0000 */
13073 #define LTDC_LxDCCR_DCRED            LTDC_LxDCCR_DCRED_Msk                     /*!< Default Color Red */
13074 #define LTDC_LxDCCR_DCALPHA_Pos      (24U)
13075 #define LTDC_LxDCCR_DCALPHA_Msk      (0xFFUL << LTDC_LxDCCR_DCALPHA_Pos)        /*!< 0xFF000000 */
13076 #define LTDC_LxDCCR_DCALPHA          LTDC_LxDCCR_DCALPHA_Msk                   /*!< Default Color Alpha */
13077 
13078 /********************  Bit definition for LTDC_LxBFCR register  ***************/
13079 
13080 #define LTDC_LxBFCR_BF2_Pos          (0U)
13081 #define LTDC_LxBFCR_BF2_Msk          (0x7UL << LTDC_LxBFCR_BF2_Pos)             /*!< 0x00000007 */
13082 #define LTDC_LxBFCR_BF2              LTDC_LxBFCR_BF2_Msk                       /*!< Blending Factor 2 */
13083 #define LTDC_LxBFCR_BF1_Pos          (8U)
13084 #define LTDC_LxBFCR_BF1_Msk          (0x7UL << LTDC_LxBFCR_BF1_Pos)             /*!< 0x00000700 */
13085 #define LTDC_LxBFCR_BF1              LTDC_LxBFCR_BF1_Msk                       /*!< Blending Factor 1 */
13086 
13087 /********************  Bit definition for LTDC_LxCFBAR register  **************/
13088 
13089 #define LTDC_LxCFBAR_CFBADD_Pos      (0U)
13090 #define LTDC_LxCFBAR_CFBADD_Msk      (0xFFFFFFFFUL << LTDC_LxCFBAR_CFBADD_Pos)  /*!< 0xFFFFFFFF */
13091 #define LTDC_LxCFBAR_CFBADD          LTDC_LxCFBAR_CFBADD_Msk                   /*!< Color Frame Buffer Start Address */
13092 
13093 /********************  Bit definition for LTDC_LxCFBLR register  **************/
13094 
13095 #define LTDC_LxCFBLR_CFBLL_Pos       (0U)
13096 #define LTDC_LxCFBLR_CFBLL_Msk       (0x1FFFUL << LTDC_LxCFBLR_CFBLL_Pos)       /*!< 0x00001FFF */
13097 #define LTDC_LxCFBLR_CFBLL           LTDC_LxCFBLR_CFBLL_Msk                    /*!< Color Frame Buffer Line Length */
13098 #define LTDC_LxCFBLR_CFBP_Pos        (16U)
13099 #define LTDC_LxCFBLR_CFBP_Msk        (0x1FFFUL << LTDC_LxCFBLR_CFBP_Pos)        /*!< 0x1FFF0000 */
13100 #define LTDC_LxCFBLR_CFBP            LTDC_LxCFBLR_CFBP_Msk                     /*!< Color Frame Buffer Pitch in bytes */
13101 
13102 /********************  Bit definition for LTDC_LxCFBLNR register  *************/
13103 
13104 #define LTDC_LxCFBLNR_CFBLNBR_Pos    (0U)
13105 #define LTDC_LxCFBLNR_CFBLNBR_Msk    (0x7FFUL << LTDC_LxCFBLNR_CFBLNBR_Pos)     /*!< 0x000007FF */
13106 #define LTDC_LxCFBLNR_CFBLNBR        LTDC_LxCFBLNR_CFBLNBR_Msk                 /*!< Frame Buffer Line Number */
13107 
13108 /********************  Bit definition for LTDC_LxCLUTWR register  *************/
13109 
13110 #define LTDC_LxCLUTWR_BLUE_Pos       (0U)
13111 #define LTDC_LxCLUTWR_BLUE_Msk       (0xFFUL << LTDC_LxCLUTWR_BLUE_Pos)         /*!< 0x000000FF */
13112 #define LTDC_LxCLUTWR_BLUE           LTDC_LxCLUTWR_BLUE_Msk                    /*!< Blue value */
13113 #define LTDC_LxCLUTWR_GREEN_Pos      (8U)
13114 #define LTDC_LxCLUTWR_GREEN_Msk      (0xFFUL << LTDC_LxCLUTWR_GREEN_Pos)        /*!< 0x0000FF00 */
13115 #define LTDC_LxCLUTWR_GREEN          LTDC_LxCLUTWR_GREEN_Msk                   /*!< Green value */
13116 #define LTDC_LxCLUTWR_RED_Pos        (16U)
13117 #define LTDC_LxCLUTWR_RED_Msk        (0xFFUL << LTDC_LxCLUTWR_RED_Pos)          /*!< 0x00FF0000 */
13118 #define LTDC_LxCLUTWR_RED            LTDC_LxCLUTWR_RED_Msk                     /*!< Red value */
13119 #define LTDC_LxCLUTWR_CLUTADD_Pos    (24U)
13120 #define LTDC_LxCLUTWR_CLUTADD_Msk    (0xFFUL << LTDC_LxCLUTWR_CLUTADD_Pos)      /*!< 0xFF000000 */
13121 #define LTDC_LxCLUTWR_CLUTADD        LTDC_LxCLUTWR_CLUTADD_Msk                 /*!< CLUT address */
13122 
13123 
13124 /******************************************************************************/
13125 /*                                                                            */
13126 /*                             Power Control                                  */
13127 /*                                                                            */
13128 /******************************************************************************/
13129 /********************  Bit definition for PWR_CR register  ********************/
13130 #define PWR_CR_LPDS_Pos        (0U)
13131 #define PWR_CR_LPDS_Msk        (0x1UL << PWR_CR_LPDS_Pos)                       /*!< 0x00000001 */
13132 #define PWR_CR_LPDS            PWR_CR_LPDS_Msk                                 /*!< Low-Power Deepsleep                 */
13133 #define PWR_CR_PDDS_Pos        (1U)
13134 #define PWR_CR_PDDS_Msk        (0x1UL << PWR_CR_PDDS_Pos)                       /*!< 0x00000002 */
13135 #define PWR_CR_PDDS            PWR_CR_PDDS_Msk                                 /*!< Power Down Deepsleep                */
13136 #define PWR_CR_CWUF_Pos        (2U)
13137 #define PWR_CR_CWUF_Msk        (0x1UL << PWR_CR_CWUF_Pos)                       /*!< 0x00000004 */
13138 #define PWR_CR_CWUF            PWR_CR_CWUF_Msk                                 /*!< Clear Wakeup Flag                   */
13139 #define PWR_CR_CSBF_Pos        (3U)
13140 #define PWR_CR_CSBF_Msk        (0x1UL << PWR_CR_CSBF_Pos)                       /*!< 0x00000008 */
13141 #define PWR_CR_CSBF            PWR_CR_CSBF_Msk                                 /*!< Clear Standby Flag                  */
13142 #define PWR_CR_PVDE_Pos        (4U)
13143 #define PWR_CR_PVDE_Msk        (0x1UL << PWR_CR_PVDE_Pos)                       /*!< 0x00000010 */
13144 #define PWR_CR_PVDE            PWR_CR_PVDE_Msk                                 /*!< Power Voltage Detector Enable       */
13145 
13146 #define PWR_CR_PLS_Pos         (5U)
13147 #define PWR_CR_PLS_Msk         (0x7UL << PWR_CR_PLS_Pos)                        /*!< 0x000000E0 */
13148 #define PWR_CR_PLS             PWR_CR_PLS_Msk                                  /*!< PLS[2:0] bits (PVD Level Selection) */
13149 #define PWR_CR_PLS_0           (0x1UL << PWR_CR_PLS_Pos)                        /*!< 0x00000020 */
13150 #define PWR_CR_PLS_1           (0x2UL << PWR_CR_PLS_Pos)                        /*!< 0x00000040 */
13151 #define PWR_CR_PLS_2           (0x4UL << PWR_CR_PLS_Pos)                        /*!< 0x00000080 */
13152 
13153 /*!< PVD level configuration */
13154 #define PWR_CR_PLS_LEV0        0x00000000U                                     /*!< PVD level 0 */
13155 #define PWR_CR_PLS_LEV1        0x00000020U                                     /*!< PVD level 1 */
13156 #define PWR_CR_PLS_LEV2        0x00000040U                                     /*!< PVD level 2 */
13157 #define PWR_CR_PLS_LEV3        0x00000060U                                     /*!< PVD level 3 */
13158 #define PWR_CR_PLS_LEV4        0x00000080U                                     /*!< PVD level 4 */
13159 #define PWR_CR_PLS_LEV5        0x000000A0U                                     /*!< PVD level 5 */
13160 #define PWR_CR_PLS_LEV6        0x000000C0U                                     /*!< PVD level 6 */
13161 #define PWR_CR_PLS_LEV7        0x000000E0U                                     /*!< PVD level 7 */
13162 #define PWR_CR_DBP_Pos         (8U)
13163 #define PWR_CR_DBP_Msk         (0x1UL << PWR_CR_DBP_Pos)                        /*!< 0x00000100 */
13164 #define PWR_CR_DBP             PWR_CR_DBP_Msk                                  /*!< Disable Backup Domain write protection                     */
13165 #define PWR_CR_FPDS_Pos        (9U)
13166 #define PWR_CR_FPDS_Msk        (0x1UL << PWR_CR_FPDS_Pos)                       /*!< 0x00000200 */
13167 #define PWR_CR_FPDS            PWR_CR_FPDS_Msk                                 /*!< Flash power down in Stop mode                              */
13168 #define PWR_CR_LPLVDS_Pos      (10U)
13169 #define PWR_CR_LPLVDS_Msk      (0x1UL << PWR_CR_LPLVDS_Pos)                     /*!< 0x00000400 */
13170 #define PWR_CR_LPLVDS          PWR_CR_LPLVDS_Msk                               /*!< Low-Power Regulator Low Voltage Scaling in Stop mode       */
13171 #define PWR_CR_MRLVDS_Pos      (11U)
13172 #define PWR_CR_MRLVDS_Msk      (0x1UL << PWR_CR_MRLVDS_Pos)                     /*!< 0x00000800 */
13173 #define PWR_CR_MRLVDS          PWR_CR_MRLVDS_Msk                               /*!< Main regulator Low Voltage Scaling in Stop mode            */
13174 #define PWR_CR_ADCDC1_Pos      (13U)
13175 #define PWR_CR_ADCDC1_Msk      (0x1UL << PWR_CR_ADCDC1_Pos)                     /*!< 0x00002000 */
13176 #define PWR_CR_ADCDC1          PWR_CR_ADCDC1_Msk                               /*!< Refer to AN4073 on how to use this bit                     */
13177 #define PWR_CR_VOS_Pos         (14U)
13178 #define PWR_CR_VOS_Msk         (0x3UL << PWR_CR_VOS_Pos)                        /*!< 0x0000C000 */
13179 #define PWR_CR_VOS             PWR_CR_VOS_Msk                                  /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
13180 #define PWR_CR_VOS_0           0x00004000U                                     /*!< Bit 0 */
13181 #define PWR_CR_VOS_1           0x00008000U                                     /*!< Bit 1 */
13182 #define PWR_CR_ODEN_Pos        (16U)
13183 #define PWR_CR_ODEN_Msk        (0x1UL << PWR_CR_ODEN_Pos)                       /*!< 0x00010000 */
13184 #define PWR_CR_ODEN            PWR_CR_ODEN_Msk                                 /*!< Over Drive enable                   */
13185 #define PWR_CR_ODSWEN_Pos      (17U)
13186 #define PWR_CR_ODSWEN_Msk      (0x1UL << PWR_CR_ODSWEN_Pos)                     /*!< 0x00020000 */
13187 #define PWR_CR_ODSWEN          PWR_CR_ODSWEN_Msk                               /*!< Over Drive switch enabled           */
13188 #define PWR_CR_UDEN_Pos        (18U)
13189 #define PWR_CR_UDEN_Msk        (0x3UL << PWR_CR_UDEN_Pos)                       /*!< 0x000C0000 */
13190 #define PWR_CR_UDEN            PWR_CR_UDEN_Msk                                 /*!< Under Drive enable in stop mode     */
13191 #define PWR_CR_UDEN_0          (0x1UL << PWR_CR_UDEN_Pos)                       /*!< 0x00040000 */
13192 #define PWR_CR_UDEN_1          (0x2UL << PWR_CR_UDEN_Pos)                       /*!< 0x00080000 */
13193 
13194 /* Legacy define */
13195 #define  PWR_CR_PMODE                        PWR_CR_VOS
13196 #define  PWR_CR_LPUDS                        PWR_CR_LPLVDS     /*!< Low-Power Regulator in deepsleep under-drive mode        */
13197 #define  PWR_CR_MRUDS                        PWR_CR_MRLVDS     /*!< Main regulator in deepsleep under-drive mode             */
13198 
13199 /*******************  Bit definition for PWR_CSR register  ********************/
13200 #define PWR_CSR_WUF_Pos        (0U)
13201 #define PWR_CSR_WUF_Msk        (0x1UL << PWR_CSR_WUF_Pos)                       /*!< 0x00000001 */
13202 #define PWR_CSR_WUF            PWR_CSR_WUF_Msk                                 /*!< Wakeup Flag                                      */
13203 #define PWR_CSR_SBF_Pos        (1U)
13204 #define PWR_CSR_SBF_Msk        (0x1UL << PWR_CSR_SBF_Pos)                       /*!< 0x00000002 */
13205 #define PWR_CSR_SBF            PWR_CSR_SBF_Msk                                 /*!< Standby Flag                                     */
13206 #define PWR_CSR_PVDO_Pos       (2U)
13207 #define PWR_CSR_PVDO_Msk       (0x1UL << PWR_CSR_PVDO_Pos)                      /*!< 0x00000004 */
13208 #define PWR_CSR_PVDO           PWR_CSR_PVDO_Msk                                /*!< PVD Output                                       */
13209 #define PWR_CSR_BRR_Pos        (3U)
13210 #define PWR_CSR_BRR_Msk        (0x1UL << PWR_CSR_BRR_Pos)                       /*!< 0x00000008 */
13211 #define PWR_CSR_BRR            PWR_CSR_BRR_Msk                                 /*!< Backup regulator ready                           */
13212 #define PWR_CSR_EWUP_Pos       (8U)
13213 #define PWR_CSR_EWUP_Msk       (0x1UL << PWR_CSR_EWUP_Pos)                      /*!< 0x00000100 */
13214 #define PWR_CSR_EWUP           PWR_CSR_EWUP_Msk                                /*!< Enable WKUP pin                                  */
13215 #define PWR_CSR_BRE_Pos        (9U)
13216 #define PWR_CSR_BRE_Msk        (0x1UL << PWR_CSR_BRE_Pos)                       /*!< 0x00000200 */
13217 #define PWR_CSR_BRE            PWR_CSR_BRE_Msk                                 /*!< Backup regulator enable                          */
13218 #define PWR_CSR_VOSRDY_Pos     (14U)
13219 #define PWR_CSR_VOSRDY_Msk     (0x1UL << PWR_CSR_VOSRDY_Pos)                    /*!< 0x00004000 */
13220 #define PWR_CSR_VOSRDY         PWR_CSR_VOSRDY_Msk                              /*!< Regulator voltage scaling output selection ready */
13221 #define PWR_CSR_ODRDY_Pos      (16U)
13222 #define PWR_CSR_ODRDY_Msk      (0x1UL << PWR_CSR_ODRDY_Pos)                     /*!< 0x00010000 */
13223 #define PWR_CSR_ODRDY          PWR_CSR_ODRDY_Msk                               /*!< Over Drive generator ready                       */
13224 #define PWR_CSR_ODSWRDY_Pos    (17U)
13225 #define PWR_CSR_ODSWRDY_Msk    (0x1UL << PWR_CSR_ODSWRDY_Pos)                   /*!< 0x00020000 */
13226 #define PWR_CSR_ODSWRDY        PWR_CSR_ODSWRDY_Msk                             /*!< Over Drive Switch ready                          */
13227 #define PWR_CSR_UDRDY_Pos      (18U)
13228 #define PWR_CSR_UDRDY_Msk      (0x3UL << PWR_CSR_UDRDY_Pos)                     /*!< 0x000C0000 */
13229 #define PWR_CSR_UDRDY          PWR_CSR_UDRDY_Msk                               /*!< Under Drive ready                                */
13230 /* Legacy define */
13231 #define  PWR_CSR_UDSWRDY                     PWR_CSR_UDRDY
13232 
13233 /* Legacy define */
13234 #define  PWR_CSR_REGRDY                      PWR_CSR_VOSRDY
13235 
13236 /******************************************************************************/
13237 /*                                                                            */
13238 /*                                    QUADSPI                                 */
13239 /*                                                                            */
13240 /******************************************************************************/
13241 /*****************  Bit definition for QUADSPI_CR register  *******************/
13242 #define QUADSPI_CR_EN_Pos                (0U)
13243 #define QUADSPI_CR_EN_Msk                (0x1UL << QUADSPI_CR_EN_Pos)           /*!< 0x00000001 */
13244 #define QUADSPI_CR_EN                    QUADSPI_CR_EN_Msk                     /*!< Enable                             */
13245 #define QUADSPI_CR_ABORT_Pos             (1U)
13246 #define QUADSPI_CR_ABORT_Msk             (0x1UL << QUADSPI_CR_ABORT_Pos)        /*!< 0x00000002 */
13247 #define QUADSPI_CR_ABORT                 QUADSPI_CR_ABORT_Msk                  /*!< Abort request                      */
13248 #define QUADSPI_CR_DMAEN_Pos             (2U)
13249 #define QUADSPI_CR_DMAEN_Msk             (0x1UL << QUADSPI_CR_DMAEN_Pos)        /*!< 0x00000004 */
13250 #define QUADSPI_CR_DMAEN                 QUADSPI_CR_DMAEN_Msk                  /*!< DMA Enable                         */
13251 #define QUADSPI_CR_TCEN_Pos              (3U)
13252 #define QUADSPI_CR_TCEN_Msk              (0x1UL << QUADSPI_CR_TCEN_Pos)         /*!< 0x00000008 */
13253 #define QUADSPI_CR_TCEN                  QUADSPI_CR_TCEN_Msk                   /*!< Timeout Counter Enable             */
13254 #define QUADSPI_CR_SSHIFT_Pos            (4U)
13255 #define QUADSPI_CR_SSHIFT_Msk            (0x1UL << QUADSPI_CR_SSHIFT_Pos)       /*!< 0x00000010 */
13256 #define QUADSPI_CR_SSHIFT                QUADSPI_CR_SSHIFT_Msk                 /*!< SSHIFT Sample Shift                */
13257 #define QUADSPI_CR_DFM_Pos               (6U)
13258 #define QUADSPI_CR_DFM_Msk               (0x1UL << QUADSPI_CR_DFM_Pos)          /*!< 0x00000040 */
13259 #define QUADSPI_CR_DFM                   QUADSPI_CR_DFM_Msk                    /*!< Dual Flash Mode                    */
13260 #define QUADSPI_CR_FSEL_Pos              (7U)
13261 #define QUADSPI_CR_FSEL_Msk              (0x1UL << QUADSPI_CR_FSEL_Pos)         /*!< 0x00000080 */
13262 #define QUADSPI_CR_FSEL                  QUADSPI_CR_FSEL_Msk                   /*!< Flash Select                       */
13263 #define QUADSPI_CR_FTHRES_Pos            (8U)
13264 #define QUADSPI_CR_FTHRES_Msk            (0x1FUL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00001F00 */
13265 #define QUADSPI_CR_FTHRES                QUADSPI_CR_FTHRES_Msk                 /*!< FTHRES[3:0] FIFO Level             */
13266 #define QUADSPI_CR_FTHRES_0              (0x01UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000100 */
13267 #define QUADSPI_CR_FTHRES_1              (0x02UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000200 */
13268 #define QUADSPI_CR_FTHRES_2              (0x04UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000400 */
13269 #define QUADSPI_CR_FTHRES_3              (0x08UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000800 */
13270 #define QUADSPI_CR_FTHRES_4              (0x10UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00001000 */
13271 #define QUADSPI_CR_TEIE_Pos              (16U)
13272 #define QUADSPI_CR_TEIE_Msk              (0x1UL << QUADSPI_CR_TEIE_Pos)         /*!< 0x00010000 */
13273 #define QUADSPI_CR_TEIE                  QUADSPI_CR_TEIE_Msk                   /*!< Transfer Error Interrupt Enable    */
13274 #define QUADSPI_CR_TCIE_Pos              (17U)
13275 #define QUADSPI_CR_TCIE_Msk              (0x1UL << QUADSPI_CR_TCIE_Pos)         /*!< 0x00020000 */
13276 #define QUADSPI_CR_TCIE                  QUADSPI_CR_TCIE_Msk                   /*!< Transfer Complete Interrupt Enable */
13277 #define QUADSPI_CR_FTIE_Pos              (18U)
13278 #define QUADSPI_CR_FTIE_Msk              (0x1UL << QUADSPI_CR_FTIE_Pos)         /*!< 0x00040000 */
13279 #define QUADSPI_CR_FTIE                  QUADSPI_CR_FTIE_Msk                   /*!< FIFO Threshold Interrupt Enable    */
13280 #define QUADSPI_CR_SMIE_Pos              (19U)
13281 #define QUADSPI_CR_SMIE_Msk              (0x1UL << QUADSPI_CR_SMIE_Pos)         /*!< 0x00080000 */
13282 #define QUADSPI_CR_SMIE                  QUADSPI_CR_SMIE_Msk                   /*!< Status Match Interrupt Enable      */
13283 #define QUADSPI_CR_TOIE_Pos              (20U)
13284 #define QUADSPI_CR_TOIE_Msk              (0x1UL << QUADSPI_CR_TOIE_Pos)         /*!< 0x00100000 */
13285 #define QUADSPI_CR_TOIE                  QUADSPI_CR_TOIE_Msk                   /*!< TimeOut Interrupt Enable           */
13286 #define QUADSPI_CR_APMS_Pos              (22U)
13287 #define QUADSPI_CR_APMS_Msk              (0x1UL << QUADSPI_CR_APMS_Pos)         /*!< 0x00400000 */
13288 #define QUADSPI_CR_APMS                  QUADSPI_CR_APMS_Msk                   /*!< Bit 1                              */
13289 #define QUADSPI_CR_PMM_Pos               (23U)
13290 #define QUADSPI_CR_PMM_Msk               (0x1UL << QUADSPI_CR_PMM_Pos)          /*!< 0x00800000 */
13291 #define QUADSPI_CR_PMM                   QUADSPI_CR_PMM_Msk                    /*!< Polling Match Mode                 */
13292 #define QUADSPI_CR_PRESCALER_Pos         (24U)
13293 #define QUADSPI_CR_PRESCALER_Msk         (0xFFUL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0xFF000000 */
13294 #define QUADSPI_CR_PRESCALER             QUADSPI_CR_PRESCALER_Msk              /*!< PRESCALER[7:0] Clock prescaler     */
13295 #define QUADSPI_CR_PRESCALER_0           (0x01UL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x01000000 */
13296 #define QUADSPI_CR_PRESCALER_1           (0x02UL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x02000000 */
13297 #define QUADSPI_CR_PRESCALER_2           (0x04UL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x04000000 */
13298 #define QUADSPI_CR_PRESCALER_3           (0x08UL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x08000000 */
13299 #define QUADSPI_CR_PRESCALER_4           (0x10UL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x10000000 */
13300 #define QUADSPI_CR_PRESCALER_5           (0x20UL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x20000000 */
13301 #define QUADSPI_CR_PRESCALER_6           (0x40UL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x40000000 */
13302 #define QUADSPI_CR_PRESCALER_7           (0x80UL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x80000000 */
13303 
13304 /*****************  Bit definition for QUADSPI_DCR register  ******************/
13305 #define QUADSPI_DCR_CKMODE_Pos           (0U)
13306 #define QUADSPI_DCR_CKMODE_Msk           (0x1UL << QUADSPI_DCR_CKMODE_Pos)      /*!< 0x00000001 */
13307 #define QUADSPI_DCR_CKMODE               QUADSPI_DCR_CKMODE_Msk                /*!< Mode 0 / Mode 3                 */
13308 #define QUADSPI_DCR_CSHT_Pos             (8U)
13309 #define QUADSPI_DCR_CSHT_Msk             (0x7UL << QUADSPI_DCR_CSHT_Pos)        /*!< 0x00000700 */
13310 #define QUADSPI_DCR_CSHT                 QUADSPI_DCR_CSHT_Msk                  /*!< CSHT[2:0]: ChipSelect High Time */
13311 #define QUADSPI_DCR_CSHT_0               (0x1UL << QUADSPI_DCR_CSHT_Pos)        /*!< 0x00000100 */
13312 #define QUADSPI_DCR_CSHT_1               (0x2UL << QUADSPI_DCR_CSHT_Pos)        /*!< 0x00000200 */
13313 #define QUADSPI_DCR_CSHT_2               (0x4UL << QUADSPI_DCR_CSHT_Pos)        /*!< 0x00000400 */
13314 #define QUADSPI_DCR_FSIZE_Pos            (16U)
13315 #define QUADSPI_DCR_FSIZE_Msk            (0x1FUL << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x001F0000 */
13316 #define QUADSPI_DCR_FSIZE                QUADSPI_DCR_FSIZE_Msk                 /*!< FSIZE[4:0]: Flash Size          */
13317 #define QUADSPI_DCR_FSIZE_0              (0x01UL << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x00010000 */
13318 #define QUADSPI_DCR_FSIZE_1              (0x02UL << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x00020000 */
13319 #define QUADSPI_DCR_FSIZE_2              (0x04UL << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x00040000 */
13320 #define QUADSPI_DCR_FSIZE_3              (0x08UL << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x00080000 */
13321 #define QUADSPI_DCR_FSIZE_4              (0x10UL << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x00100000 */
13322 
13323 /******************  Bit definition for QUADSPI_SR register  *******************/
13324 #define QUADSPI_SR_TEF_Pos               (0U)
13325 #define QUADSPI_SR_TEF_Msk               (0x1UL << QUADSPI_SR_TEF_Pos)          /*!< 0x00000001 */
13326 #define QUADSPI_SR_TEF                   QUADSPI_SR_TEF_Msk                    /*!< Transfer Error Flag    */
13327 #define QUADSPI_SR_TCF_Pos               (1U)
13328 #define QUADSPI_SR_TCF_Msk               (0x1UL << QUADSPI_SR_TCF_Pos)          /*!< 0x00000002 */
13329 #define QUADSPI_SR_TCF                   QUADSPI_SR_TCF_Msk                    /*!< Transfer Complete Flag */
13330 #define QUADSPI_SR_FTF_Pos               (2U)
13331 #define QUADSPI_SR_FTF_Msk               (0x1UL << QUADSPI_SR_FTF_Pos)          /*!< 0x00000004 */
13332 #define QUADSPI_SR_FTF                   QUADSPI_SR_FTF_Msk                    /*!< FIFO Threshlod Flag    */
13333 #define QUADSPI_SR_SMF_Pos               (3U)
13334 #define QUADSPI_SR_SMF_Msk               (0x1UL << QUADSPI_SR_SMF_Pos)          /*!< 0x00000008 */
13335 #define QUADSPI_SR_SMF                   QUADSPI_SR_SMF_Msk                    /*!< Status Match Flag      */
13336 #define QUADSPI_SR_TOF_Pos               (4U)
13337 #define QUADSPI_SR_TOF_Msk               (0x1UL << QUADSPI_SR_TOF_Pos)          /*!< 0x00000010 */
13338 #define QUADSPI_SR_TOF                   QUADSPI_SR_TOF_Msk                    /*!< Timeout Flag           */
13339 #define QUADSPI_SR_BUSY_Pos              (5U)
13340 #define QUADSPI_SR_BUSY_Msk              (0x1UL << QUADSPI_SR_BUSY_Pos)         /*!< 0x00000020 */
13341 #define QUADSPI_SR_BUSY                  QUADSPI_SR_BUSY_Msk                   /*!< Busy                   */
13342 #define QUADSPI_SR_FLEVEL_Pos            (8U)
13343 #define QUADSPI_SR_FLEVEL_Msk            (0x3FUL << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00003F00 */
13344 #define QUADSPI_SR_FLEVEL                QUADSPI_SR_FLEVEL_Msk                 /*!< FIFO Threshlod Flag    */
13345 #define QUADSPI_SR_FLEVEL_0              (0x01UL << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00000100 */
13346 #define QUADSPI_SR_FLEVEL_1              (0x02UL << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00000200 */
13347 #define QUADSPI_SR_FLEVEL_2              (0x04UL << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00000400 */
13348 #define QUADSPI_SR_FLEVEL_3              (0x08UL << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00000800 */
13349 #define QUADSPI_SR_FLEVEL_4              (0x10UL << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00001000 */
13350 #define QUADSPI_SR_FLEVEL_5              (0x20UL << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00002000 */
13351 
13352 /******************  Bit definition for QUADSPI_FCR register  ******************/
13353 #define QUADSPI_FCR_CTEF_Pos             (0U)
13354 #define QUADSPI_FCR_CTEF_Msk             (0x1UL << QUADSPI_FCR_CTEF_Pos)        /*!< 0x00000001 */
13355 #define QUADSPI_FCR_CTEF                 QUADSPI_FCR_CTEF_Msk                  /*!< Clear Transfer Error Flag    */
13356 #define QUADSPI_FCR_CTCF_Pos             (1U)
13357 #define QUADSPI_FCR_CTCF_Msk             (0x1UL << QUADSPI_FCR_CTCF_Pos)        /*!< 0x00000002 */
13358 #define QUADSPI_FCR_CTCF                 QUADSPI_FCR_CTCF_Msk                  /*!< Clear Transfer Complete Flag */
13359 #define QUADSPI_FCR_CSMF_Pos             (3U)
13360 #define QUADSPI_FCR_CSMF_Msk             (0x1UL << QUADSPI_FCR_CSMF_Pos)        /*!< 0x00000008 */
13361 #define QUADSPI_FCR_CSMF                 QUADSPI_FCR_CSMF_Msk                  /*!< Clear Status Match Flag      */
13362 #define QUADSPI_FCR_CTOF_Pos             (4U)
13363 #define QUADSPI_FCR_CTOF_Msk             (0x1UL << QUADSPI_FCR_CTOF_Pos)        /*!< 0x00000010 */
13364 #define QUADSPI_FCR_CTOF                 QUADSPI_FCR_CTOF_Msk                  /*!< Clear Timeout Flag           */
13365 
13366 /******************  Bit definition for QUADSPI_DLR register  ******************/
13367 #define QUADSPI_DLR_DL_Pos               (0U)
13368 #define QUADSPI_DLR_DL_Msk               (0xFFFFFFFFUL << QUADSPI_DLR_DL_Pos)   /*!< 0xFFFFFFFF */
13369 #define QUADSPI_DLR_DL                   QUADSPI_DLR_DL_Msk                    /*!< DL[31:0]: Data Length */
13370 
13371 /******************  Bit definition for QUADSPI_CCR register  ******************/
13372 #define QUADSPI_CCR_INSTRUCTION_Pos      (0U)
13373 #define QUADSPI_CCR_INSTRUCTION_Msk      (0xFFUL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */
13374 #define QUADSPI_CCR_INSTRUCTION          QUADSPI_CCR_INSTRUCTION_Msk           /*!< INSTRUCTION[7:0]: Instruction         */
13375 #define QUADSPI_CCR_INSTRUCTION_0        (0x01UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000001 */
13376 #define QUADSPI_CCR_INSTRUCTION_1        (0x02UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000002 */
13377 #define QUADSPI_CCR_INSTRUCTION_2        (0x04UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000004 */
13378 #define QUADSPI_CCR_INSTRUCTION_3        (0x08UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000008 */
13379 #define QUADSPI_CCR_INSTRUCTION_4        (0x10UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000010 */
13380 #define QUADSPI_CCR_INSTRUCTION_5        (0x20UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000020 */
13381 #define QUADSPI_CCR_INSTRUCTION_6        (0x40UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000040 */
13382 #define QUADSPI_CCR_INSTRUCTION_7        (0x80UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000080 */
13383 #define QUADSPI_CCR_IMODE_Pos            (8U)
13384 #define QUADSPI_CCR_IMODE_Msk            (0x3UL << QUADSPI_CCR_IMODE_Pos)       /*!< 0x00000300 */
13385 #define QUADSPI_CCR_IMODE                QUADSPI_CCR_IMODE_Msk                 /*!< IMODE[1:0]: Instruction Mode          */
13386 #define QUADSPI_CCR_IMODE_0              (0x1UL << QUADSPI_CCR_IMODE_Pos)       /*!< 0x00000100 */
13387 #define QUADSPI_CCR_IMODE_1              (0x2UL << QUADSPI_CCR_IMODE_Pos)       /*!< 0x00000200 */
13388 #define QUADSPI_CCR_ADMODE_Pos           (10U)
13389 #define QUADSPI_CCR_ADMODE_Msk           (0x3UL << QUADSPI_CCR_ADMODE_Pos)      /*!< 0x00000C00 */
13390 #define QUADSPI_CCR_ADMODE               QUADSPI_CCR_ADMODE_Msk                /*!< ADMODE[1:0]: Address Mode             */
13391 #define QUADSPI_CCR_ADMODE_0             (0x1UL << QUADSPI_CCR_ADMODE_Pos)      /*!< 0x00000400 */
13392 #define QUADSPI_CCR_ADMODE_1             (0x2UL << QUADSPI_CCR_ADMODE_Pos)      /*!< 0x00000800 */
13393 #define QUADSPI_CCR_ADSIZE_Pos           (12U)
13394 #define QUADSPI_CCR_ADSIZE_Msk           (0x3UL << QUADSPI_CCR_ADSIZE_Pos)      /*!< 0x00003000 */
13395 #define QUADSPI_CCR_ADSIZE               QUADSPI_CCR_ADSIZE_Msk                /*!< ADSIZE[1:0]: Address Size             */
13396 #define QUADSPI_CCR_ADSIZE_0             (0x1UL << QUADSPI_CCR_ADSIZE_Pos)      /*!< 0x00001000 */
13397 #define QUADSPI_CCR_ADSIZE_1             (0x2UL << QUADSPI_CCR_ADSIZE_Pos)      /*!< 0x00002000 */
13398 #define QUADSPI_CCR_ABMODE_Pos           (14U)
13399 #define QUADSPI_CCR_ABMODE_Msk           (0x3UL << QUADSPI_CCR_ABMODE_Pos)      /*!< 0x0000C000 */
13400 #define QUADSPI_CCR_ABMODE               QUADSPI_CCR_ABMODE_Msk                /*!< ABMODE[1:0]: Alternate Bytes Mode     */
13401 #define QUADSPI_CCR_ABMODE_0             (0x1UL << QUADSPI_CCR_ABMODE_Pos)      /*!< 0x00004000 */
13402 #define QUADSPI_CCR_ABMODE_1             (0x2UL << QUADSPI_CCR_ABMODE_Pos)      /*!< 0x00008000 */
13403 #define QUADSPI_CCR_ABSIZE_Pos           (16U)
13404 #define QUADSPI_CCR_ABSIZE_Msk           (0x3UL << QUADSPI_CCR_ABSIZE_Pos)      /*!< 0x00030000 */
13405 #define QUADSPI_CCR_ABSIZE               QUADSPI_CCR_ABSIZE_Msk                /*!< ABSIZE[1:0]: Instruction Mode         */
13406 #define QUADSPI_CCR_ABSIZE_0             (0x1UL << QUADSPI_CCR_ABSIZE_Pos)      /*!< 0x00010000 */
13407 #define QUADSPI_CCR_ABSIZE_1             (0x2UL << QUADSPI_CCR_ABSIZE_Pos)      /*!< 0x00020000 */
13408 #define QUADSPI_CCR_DCYC_Pos             (18U)
13409 #define QUADSPI_CCR_DCYC_Msk             (0x1FUL << QUADSPI_CCR_DCYC_Pos)       /*!< 0x007C0000 */
13410 #define QUADSPI_CCR_DCYC                 QUADSPI_CCR_DCYC_Msk                  /*!< DCYC[4:0]: Dummy Cycles               */
13411 #define QUADSPI_CCR_DCYC_0               (0x01UL << QUADSPI_CCR_DCYC_Pos)       /*!< 0x00040000 */
13412 #define QUADSPI_CCR_DCYC_1               (0x02UL << QUADSPI_CCR_DCYC_Pos)       /*!< 0x00080000 */
13413 #define QUADSPI_CCR_DCYC_2               (0x04UL << QUADSPI_CCR_DCYC_Pos)       /*!< 0x00100000 */
13414 #define QUADSPI_CCR_DCYC_3               (0x08UL << QUADSPI_CCR_DCYC_Pos)       /*!< 0x00200000 */
13415 #define QUADSPI_CCR_DCYC_4               (0x10UL << QUADSPI_CCR_DCYC_Pos)       /*!< 0x00400000 */
13416 #define QUADSPI_CCR_DMODE_Pos            (24U)
13417 #define QUADSPI_CCR_DMODE_Msk            (0x3UL << QUADSPI_CCR_DMODE_Pos)       /*!< 0x03000000 */
13418 #define QUADSPI_CCR_DMODE                QUADSPI_CCR_DMODE_Msk                 /*!< DMODE[1:0]: Data Mode                 */
13419 #define QUADSPI_CCR_DMODE_0              (0x1UL << QUADSPI_CCR_DMODE_Pos)       /*!< 0x01000000 */
13420 #define QUADSPI_CCR_DMODE_1              (0x2UL << QUADSPI_CCR_DMODE_Pos)       /*!< 0x02000000 */
13421 #define QUADSPI_CCR_FMODE_Pos            (26U)
13422 #define QUADSPI_CCR_FMODE_Msk            (0x3UL << QUADSPI_CCR_FMODE_Pos)       /*!< 0x0C000000 */
13423 #define QUADSPI_CCR_FMODE                QUADSPI_CCR_FMODE_Msk                 /*!< FMODE[1:0]: Functional Mode           */
13424 #define QUADSPI_CCR_FMODE_0              (0x1UL << QUADSPI_CCR_FMODE_Pos)       /*!< 0x04000000 */
13425 #define QUADSPI_CCR_FMODE_1              (0x2UL << QUADSPI_CCR_FMODE_Pos)       /*!< 0x08000000 */
13426 #define QUADSPI_CCR_SIOO_Pos             (28U)
13427 #define QUADSPI_CCR_SIOO_Msk             (0x1UL << QUADSPI_CCR_SIOO_Pos)        /*!< 0x10000000 */
13428 #define QUADSPI_CCR_SIOO                 QUADSPI_CCR_SIOO_Msk                  /*!< SIOO: Send Instruction Only Once Mode */
13429 #define QUADSPI_CCR_DHHC_Pos             (30U)
13430 #define QUADSPI_CCR_DHHC_Msk             (0x1UL << QUADSPI_CCR_DHHC_Pos)        /*!< 0x40000000 */
13431 #define QUADSPI_CCR_DHHC                 QUADSPI_CCR_DHHC_Msk                  /*!< DHHC: Delay Half Hclk Cycle           */
13432 #define QUADSPI_CCR_DDRM_Pos             (31U)
13433 #define QUADSPI_CCR_DDRM_Msk             (0x1UL << QUADSPI_CCR_DDRM_Pos)        /*!< 0x80000000 */
13434 #define QUADSPI_CCR_DDRM                 QUADSPI_CCR_DDRM_Msk                  /*!< DDRM: Double Data Rate Mode           */
13435 /******************  Bit definition for QUADSPI_AR register  *******************/
13436 #define QUADSPI_AR_ADDRESS_Pos           (0U)
13437 #define QUADSPI_AR_ADDRESS_Msk           (0xFFFFFFFFUL << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
13438 #define QUADSPI_AR_ADDRESS               QUADSPI_AR_ADDRESS_Msk                /*!< ADDRESS[31:0]: Address                */
13439 
13440 /******************  Bit definition for QUADSPI_ABR register  ******************/
13441 #define QUADSPI_ABR_ALTERNATE_Pos        (0U)
13442 #define QUADSPI_ABR_ALTERNATE_Msk        (0xFFFFFFFFUL << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
13443 #define QUADSPI_ABR_ALTERNATE            QUADSPI_ABR_ALTERNATE_Msk             /*!< ALTERNATE[31:0]: Alternate Bytes      */
13444 
13445 /******************  Bit definition for QUADSPI_DR register  *******************/
13446 #define QUADSPI_DR_DATA_Pos              (0U)
13447 #define QUADSPI_DR_DATA_Msk              (0xFFFFFFFFUL << QUADSPI_DR_DATA_Pos)  /*!< 0xFFFFFFFF */
13448 #define QUADSPI_DR_DATA                  QUADSPI_DR_DATA_Msk                   /*!< DATA[31:0]: Data                      */
13449 
13450 /******************  Bit definition for QUADSPI_PSMKR register  ****************/
13451 #define QUADSPI_PSMKR_MASK_Pos           (0U)
13452 #define QUADSPI_PSMKR_MASK_Msk           (0xFFFFFFFFUL << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */
13453 #define QUADSPI_PSMKR_MASK               QUADSPI_PSMKR_MASK_Msk                /*!< MASK[31:0]: Status Mask               */
13454 
13455 /******************  Bit definition for QUADSPI_PSMAR register  ****************/
13456 #define QUADSPI_PSMAR_MATCH_Pos          (0U)
13457 #define QUADSPI_PSMAR_MATCH_Msk          (0xFFFFFFFFUL << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */
13458 #define QUADSPI_PSMAR_MATCH              QUADSPI_PSMAR_MATCH_Msk               /*!< MATCH[31:0]: Status Match             */
13459 
13460 /******************  Bit definition for QUADSPI_PIR register  *****************/
13461 #define QUADSPI_PIR_INTERVAL_Pos         (0U)
13462 #define QUADSPI_PIR_INTERVAL_Msk         (0xFFFFUL << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */
13463 #define QUADSPI_PIR_INTERVAL             QUADSPI_PIR_INTERVAL_Msk              /*!< INTERVAL[15:0]: Polling Interval      */
13464 
13465 /******************  Bit definition for QUADSPI_LPTR register  *****************/
13466 #define QUADSPI_LPTR_TIMEOUT_Pos         (0U)
13467 #define QUADSPI_LPTR_TIMEOUT_Msk         (0xFFFFUL << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */
13468 #define QUADSPI_LPTR_TIMEOUT             QUADSPI_LPTR_TIMEOUT_Msk              /*!< TIMEOUT[15:0]: Timeout period         */
13469 
13470 /******************************************************************************/
13471 /*                                                                            */
13472 /*                         Reset and Clock Control                            */
13473 /*                                                                            */
13474 /******************************************************************************/
13475 /********************  Bit definition for RCC_CR register  ********************/
13476 #define RCC_CR_HSION_Pos                   (0U)
13477 #define RCC_CR_HSION_Msk                   (0x1UL << RCC_CR_HSION_Pos)          /*!< 0x00000001 */
13478 #define RCC_CR_HSION                       RCC_CR_HSION_Msk
13479 #define RCC_CR_HSIRDY_Pos                  (1U)
13480 #define RCC_CR_HSIRDY_Msk                  (0x1UL << RCC_CR_HSIRDY_Pos)         /*!< 0x00000002 */
13481 #define RCC_CR_HSIRDY                      RCC_CR_HSIRDY_Msk
13482 
13483 #define RCC_CR_HSITRIM_Pos                 (3U)
13484 #define RCC_CR_HSITRIM_Msk                 (0x1FUL << RCC_CR_HSITRIM_Pos)       /*!< 0x000000F8 */
13485 #define RCC_CR_HSITRIM                     RCC_CR_HSITRIM_Msk
13486 #define RCC_CR_HSITRIM_0                   (0x01UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000008 */
13487 #define RCC_CR_HSITRIM_1                   (0x02UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000010 */
13488 #define RCC_CR_HSITRIM_2                   (0x04UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000020 */
13489 #define RCC_CR_HSITRIM_3                   (0x08UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000040 */
13490 #define RCC_CR_HSITRIM_4                   (0x10UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000080 */
13491 
13492 #define RCC_CR_HSICAL_Pos                  (8U)
13493 #define RCC_CR_HSICAL_Msk                  (0xFFUL << RCC_CR_HSICAL_Pos)        /*!< 0x0000FF00 */
13494 #define RCC_CR_HSICAL                      RCC_CR_HSICAL_Msk
13495 #define RCC_CR_HSICAL_0                    (0x01UL << RCC_CR_HSICAL_Pos)        /*!< 0x00000100 */
13496 #define RCC_CR_HSICAL_1                    (0x02UL << RCC_CR_HSICAL_Pos)        /*!< 0x00000200 */
13497 #define RCC_CR_HSICAL_2                    (0x04UL << RCC_CR_HSICAL_Pos)        /*!< 0x00000400 */
13498 #define RCC_CR_HSICAL_3                    (0x08UL << RCC_CR_HSICAL_Pos)        /*!< 0x00000800 */
13499 #define RCC_CR_HSICAL_4                    (0x10UL << RCC_CR_HSICAL_Pos)        /*!< 0x00001000 */
13500 #define RCC_CR_HSICAL_5                    (0x20UL << RCC_CR_HSICAL_Pos)        /*!< 0x00002000 */
13501 #define RCC_CR_HSICAL_6                    (0x40UL << RCC_CR_HSICAL_Pos)        /*!< 0x00004000 */
13502 #define RCC_CR_HSICAL_7                    (0x80UL << RCC_CR_HSICAL_Pos)        /*!< 0x00008000 */
13503 
13504 #define RCC_CR_HSEON_Pos                   (16U)
13505 #define RCC_CR_HSEON_Msk                   (0x1UL << RCC_CR_HSEON_Pos)          /*!< 0x00010000 */
13506 #define RCC_CR_HSEON                       RCC_CR_HSEON_Msk
13507 #define RCC_CR_HSERDY_Pos                  (17U)
13508 #define RCC_CR_HSERDY_Msk                  (0x1UL << RCC_CR_HSERDY_Pos)         /*!< 0x00020000 */
13509 #define RCC_CR_HSERDY                      RCC_CR_HSERDY_Msk
13510 #define RCC_CR_HSEBYP_Pos                  (18U)
13511 #define RCC_CR_HSEBYP_Msk                  (0x1UL << RCC_CR_HSEBYP_Pos)         /*!< 0x00040000 */
13512 #define RCC_CR_HSEBYP                      RCC_CR_HSEBYP_Msk
13513 #define RCC_CR_CSSON_Pos                   (19U)
13514 #define RCC_CR_CSSON_Msk                   (0x1UL << RCC_CR_CSSON_Pos)          /*!< 0x00080000 */
13515 #define RCC_CR_CSSON                       RCC_CR_CSSON_Msk
13516 #define RCC_CR_PLLON_Pos                   (24U)
13517 #define RCC_CR_PLLON_Msk                   (0x1UL << RCC_CR_PLLON_Pos)          /*!< 0x01000000 */
13518 #define RCC_CR_PLLON                       RCC_CR_PLLON_Msk
13519 #define RCC_CR_PLLRDY_Pos                  (25U)
13520 #define RCC_CR_PLLRDY_Msk                  (0x1UL << RCC_CR_PLLRDY_Pos)         /*!< 0x02000000 */
13521 #define RCC_CR_PLLRDY                      RCC_CR_PLLRDY_Msk
13522 /*
13523  * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
13524  */
13525 #define RCC_PLLI2S_SUPPORT                                                     /*!< Support PLLI2S oscillator */
13526 
13527 #define RCC_CR_PLLI2SON_Pos                (26U)
13528 #define RCC_CR_PLLI2SON_Msk                (0x1UL << RCC_CR_PLLI2SON_Pos)       /*!< 0x04000000 */
13529 #define RCC_CR_PLLI2SON                    RCC_CR_PLLI2SON_Msk
13530 #define RCC_CR_PLLI2SRDY_Pos               (27U)
13531 #define RCC_CR_PLLI2SRDY_Msk               (0x1UL << RCC_CR_PLLI2SRDY_Pos)      /*!< 0x08000000 */
13532 #define RCC_CR_PLLI2SRDY                   RCC_CR_PLLI2SRDY_Msk
13533 /*
13534  * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
13535  */
13536 #define RCC_PLLSAI_SUPPORT                                                     /*!< Support PLLSAI oscillator */
13537 
13538 #define RCC_CR_PLLSAION_Pos                (28U)
13539 #define RCC_CR_PLLSAION_Msk                (0x1UL << RCC_CR_PLLSAION_Pos)       /*!< 0x10000000 */
13540 #define RCC_CR_PLLSAION                    RCC_CR_PLLSAION_Msk
13541 #define RCC_CR_PLLSAIRDY_Pos               (29U)
13542 #define RCC_CR_PLLSAIRDY_Msk               (0x1UL << RCC_CR_PLLSAIRDY_Pos)      /*!< 0x20000000 */
13543 #define RCC_CR_PLLSAIRDY                   RCC_CR_PLLSAIRDY_Msk
13544 
13545 /********************  Bit definition for RCC_PLLCFGR register  ***************/
13546 #define RCC_PLLCFGR_PLLM_Pos               (0U)
13547 #define RCC_PLLCFGR_PLLM_Msk               (0x3FUL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x0000003F */
13548 #define RCC_PLLCFGR_PLLM                   RCC_PLLCFGR_PLLM_Msk
13549 #define RCC_PLLCFGR_PLLM_0                 (0x01UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000001 */
13550 #define RCC_PLLCFGR_PLLM_1                 (0x02UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000002 */
13551 #define RCC_PLLCFGR_PLLM_2                 (0x04UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000004 */
13552 #define RCC_PLLCFGR_PLLM_3                 (0x08UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000008 */
13553 #define RCC_PLLCFGR_PLLM_4                 (0x10UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000010 */
13554 #define RCC_PLLCFGR_PLLM_5                 (0x20UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000020 */
13555 
13556 #define RCC_PLLCFGR_PLLN_Pos               (6U)
13557 #define RCC_PLLCFGR_PLLN_Msk               (0x1FFUL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00007FC0 */
13558 #define RCC_PLLCFGR_PLLN                   RCC_PLLCFGR_PLLN_Msk
13559 #define RCC_PLLCFGR_PLLN_0                 (0x001UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000040 */
13560 #define RCC_PLLCFGR_PLLN_1                 (0x002UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000080 */
13561 #define RCC_PLLCFGR_PLLN_2                 (0x004UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000100 */
13562 #define RCC_PLLCFGR_PLLN_3                 (0x008UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000200 */
13563 #define RCC_PLLCFGR_PLLN_4                 (0x010UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000400 */
13564 #define RCC_PLLCFGR_PLLN_5                 (0x020UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000800 */
13565 #define RCC_PLLCFGR_PLLN_6                 (0x040UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00001000 */
13566 #define RCC_PLLCFGR_PLLN_7                 (0x080UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00002000 */
13567 #define RCC_PLLCFGR_PLLN_8                 (0x100UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00004000 */
13568 
13569 #define RCC_PLLCFGR_PLLP_Pos               (16U)
13570 #define RCC_PLLCFGR_PLLP_Msk               (0x3UL << RCC_PLLCFGR_PLLP_Pos)      /*!< 0x00030000 */
13571 #define RCC_PLLCFGR_PLLP                   RCC_PLLCFGR_PLLP_Msk
13572 #define RCC_PLLCFGR_PLLP_0                 (0x1UL << RCC_PLLCFGR_PLLP_Pos)      /*!< 0x00010000 */
13573 #define RCC_PLLCFGR_PLLP_1                 (0x2UL << RCC_PLLCFGR_PLLP_Pos)      /*!< 0x00020000 */
13574 
13575 #define RCC_PLLCFGR_PLLSRC_Pos             (22U)
13576 #define RCC_PLLCFGR_PLLSRC_Msk             (0x1UL << RCC_PLLCFGR_PLLSRC_Pos)    /*!< 0x00400000 */
13577 #define RCC_PLLCFGR_PLLSRC                 RCC_PLLCFGR_PLLSRC_Msk
13578 #define RCC_PLLCFGR_PLLSRC_HSE_Pos         (22U)
13579 #define RCC_PLLCFGR_PLLSRC_HSE_Msk         (0x1UL << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */
13580 #define RCC_PLLCFGR_PLLSRC_HSE             RCC_PLLCFGR_PLLSRC_HSE_Msk
13581 #define RCC_PLLCFGR_PLLSRC_HSI             0x00000000U
13582 
13583 #define RCC_PLLCFGR_PLLQ_Pos               (24U)
13584 #define RCC_PLLCFGR_PLLQ_Msk               (0xFUL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x0F000000 */
13585 #define RCC_PLLCFGR_PLLQ                   RCC_PLLCFGR_PLLQ_Msk
13586 #define RCC_PLLCFGR_PLLQ_0                 (0x1UL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x01000000 */
13587 #define RCC_PLLCFGR_PLLQ_1                 (0x2UL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x02000000 */
13588 #define RCC_PLLCFGR_PLLQ_2                 (0x4UL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x04000000 */
13589 #define RCC_PLLCFGR_PLLQ_3                 (0x8UL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x08000000 */
13590 
13591 #define RCC_PLLCFGR_PLLR_Pos               (28U)
13592 #define RCC_PLLCFGR_PLLR_Msk               (0x7UL << RCC_PLLCFGR_PLLR_Pos)      /*!< 0x70000000 */
13593 #define RCC_PLLCFGR_PLLR                   RCC_PLLCFGR_PLLR_Msk
13594 #define RCC_PLLCFGR_PLLR_0                 (0x1UL << RCC_PLLCFGR_PLLR_Pos)      /*!< 0x10000000 */
13595 #define RCC_PLLCFGR_PLLR_1                 (0x2UL << RCC_PLLCFGR_PLLR_Pos)      /*!< 0x20000000 */
13596 #define RCC_PLLCFGR_PLLR_2                 (0x4UL << RCC_PLLCFGR_PLLR_Pos)      /*!< 0x40000000 */
13597 
13598 /********************  Bit definition for RCC_CFGR register  ******************/
13599 /*!< SW configuration */
13600 #define RCC_CFGR_SW_Pos                    (0U)
13601 #define RCC_CFGR_SW_Msk                    (0x3UL << RCC_CFGR_SW_Pos)           /*!< 0x00000003 */
13602 #define RCC_CFGR_SW                        RCC_CFGR_SW_Msk                     /*!< SW[1:0] bits (System clock Switch) */
13603 #define RCC_CFGR_SW_0                      (0x1UL << RCC_CFGR_SW_Pos)           /*!< 0x00000001 */
13604 #define RCC_CFGR_SW_1                      (0x2UL << RCC_CFGR_SW_Pos)           /*!< 0x00000002 */
13605 
13606 #define RCC_CFGR_SW_HSI                    0x00000000U                         /*!< HSI selected as system clock */
13607 #define RCC_CFGR_SW_HSE                    0x00000001U                         /*!< HSE selected as system clock */
13608 #define RCC_CFGR_SW_PLL                    0x00000002U                         /*!< PLL selected as system clock */
13609 
13610 /*!< SWS configuration */
13611 #define RCC_CFGR_SWS_Pos                   (2U)
13612 #define RCC_CFGR_SWS_Msk                   (0x3UL << RCC_CFGR_SWS_Pos)          /*!< 0x0000000C */
13613 #define RCC_CFGR_SWS                       RCC_CFGR_SWS_Msk                    /*!< SWS[1:0] bits (System Clock Switch Status) */
13614 #define RCC_CFGR_SWS_0                     (0x1UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000004 */
13615 #define RCC_CFGR_SWS_1                     (0x2UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000008 */
13616 
13617 #define RCC_CFGR_SWS_HSI                   0x00000000U                         /*!< HSI oscillator used as system clock        */
13618 #define RCC_CFGR_SWS_HSE                   0x00000004U                         /*!< HSE oscillator used as system clock        */
13619 #define RCC_CFGR_SWS_PLL                   0x00000008U                         /*!< PLL used as system clock                   */
13620 
13621 /*!< HPRE configuration */
13622 #define RCC_CFGR_HPRE_Pos                  (4U)
13623 #define RCC_CFGR_HPRE_Msk                  (0xFUL << RCC_CFGR_HPRE_Pos)         /*!< 0x000000F0 */
13624 #define RCC_CFGR_HPRE                      RCC_CFGR_HPRE_Msk                   /*!< HPRE[3:0] bits (AHB prescaler) */
13625 #define RCC_CFGR_HPRE_0                    (0x1UL << RCC_CFGR_HPRE_Pos)         /*!< 0x00000010 */
13626 #define RCC_CFGR_HPRE_1                    (0x2UL << RCC_CFGR_HPRE_Pos)         /*!< 0x00000020 */
13627 #define RCC_CFGR_HPRE_2                    (0x4UL << RCC_CFGR_HPRE_Pos)         /*!< 0x00000040 */
13628 #define RCC_CFGR_HPRE_3                    (0x8UL << RCC_CFGR_HPRE_Pos)         /*!< 0x00000080 */
13629 
13630 #define RCC_CFGR_HPRE_DIV1                 0x00000000U                         /*!< SYSCLK not divided    */
13631 #define RCC_CFGR_HPRE_DIV2                 0x00000080U                         /*!< SYSCLK divided by 2   */
13632 #define RCC_CFGR_HPRE_DIV4                 0x00000090U                         /*!< SYSCLK divided by 4   */
13633 #define RCC_CFGR_HPRE_DIV8                 0x000000A0U                         /*!< SYSCLK divided by 8   */
13634 #define RCC_CFGR_HPRE_DIV16                0x000000B0U                         /*!< SYSCLK divided by 16  */
13635 #define RCC_CFGR_HPRE_DIV64                0x000000C0U                         /*!< SYSCLK divided by 64  */
13636 #define RCC_CFGR_HPRE_DIV128               0x000000D0U                         /*!< SYSCLK divided by 128 */
13637 #define RCC_CFGR_HPRE_DIV256               0x000000E0U                         /*!< SYSCLK divided by 256 */
13638 #define RCC_CFGR_HPRE_DIV512               0x000000F0U                         /*!< SYSCLK divided by 512 */
13639 
13640 /*!< PPRE1 configuration */
13641 #define RCC_CFGR_PPRE1_Pos                 (10U)
13642 #define RCC_CFGR_PPRE1_Msk                 (0x7UL << RCC_CFGR_PPRE1_Pos)        /*!< 0x00001C00 */
13643 #define RCC_CFGR_PPRE1                     RCC_CFGR_PPRE1_Msk                  /*!< PRE1[2:0] bits (APB1 prescaler) */
13644 #define RCC_CFGR_PPRE1_0                   (0x1UL << RCC_CFGR_PPRE1_Pos)        /*!< 0x00000400 */
13645 #define RCC_CFGR_PPRE1_1                   (0x2UL << RCC_CFGR_PPRE1_Pos)        /*!< 0x00000800 */
13646 #define RCC_CFGR_PPRE1_2                   (0x4UL << RCC_CFGR_PPRE1_Pos)        /*!< 0x00001000 */
13647 
13648 #define RCC_CFGR_PPRE1_DIV1                0x00000000U                         /*!< HCLK not divided   */
13649 #define RCC_CFGR_PPRE1_DIV2                0x00001000U                         /*!< HCLK divided by 2  */
13650 #define RCC_CFGR_PPRE1_DIV4                0x00001400U                         /*!< HCLK divided by 4  */
13651 #define RCC_CFGR_PPRE1_DIV8                0x00001800U                         /*!< HCLK divided by 8  */
13652 #define RCC_CFGR_PPRE1_DIV16               0x00001C00U                         /*!< HCLK divided by 16 */
13653 
13654 /*!< PPRE2 configuration */
13655 #define RCC_CFGR_PPRE2_Pos                 (13U)
13656 #define RCC_CFGR_PPRE2_Msk                 (0x7UL << RCC_CFGR_PPRE2_Pos)        /*!< 0x0000E000 */
13657 #define RCC_CFGR_PPRE2                     RCC_CFGR_PPRE2_Msk                  /*!< PRE2[2:0] bits (APB2 prescaler) */
13658 #define RCC_CFGR_PPRE2_0                   (0x1UL << RCC_CFGR_PPRE2_Pos)        /*!< 0x00002000 */
13659 #define RCC_CFGR_PPRE2_1                   (0x2UL << RCC_CFGR_PPRE2_Pos)        /*!< 0x00004000 */
13660 #define RCC_CFGR_PPRE2_2                   (0x4UL << RCC_CFGR_PPRE2_Pos)        /*!< 0x00008000 */
13661 
13662 #define RCC_CFGR_PPRE2_DIV1                0x00000000U                         /*!< HCLK not divided   */
13663 #define RCC_CFGR_PPRE2_DIV2                0x00008000U                         /*!< HCLK divided by 2  */
13664 #define RCC_CFGR_PPRE2_DIV4                0x0000A000U                         /*!< HCLK divided by 4  */
13665 #define RCC_CFGR_PPRE2_DIV8                0x0000C000U                         /*!< HCLK divided by 8  */
13666 #define RCC_CFGR_PPRE2_DIV16               0x0000E000U                         /*!< HCLK divided by 16 */
13667 
13668 /*!< RTCPRE configuration */
13669 #define RCC_CFGR_RTCPRE_Pos                (16U)
13670 #define RCC_CFGR_RTCPRE_Msk                (0x1FUL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x001F0000 */
13671 #define RCC_CFGR_RTCPRE                    RCC_CFGR_RTCPRE_Msk
13672 #define RCC_CFGR_RTCPRE_0                  (0x01UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00010000 */
13673 #define RCC_CFGR_RTCPRE_1                  (0x02UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00020000 */
13674 #define RCC_CFGR_RTCPRE_2                  (0x04UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00040000 */
13675 #define RCC_CFGR_RTCPRE_3                  (0x08UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00080000 */
13676 #define RCC_CFGR_RTCPRE_4                  (0x10UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00100000 */
13677 
13678 /*!< MCO1 configuration */
13679 #define RCC_CFGR_MCO1_Pos                  (21U)
13680 #define RCC_CFGR_MCO1_Msk                  (0x3UL << RCC_CFGR_MCO1_Pos)         /*!< 0x00600000 */
13681 #define RCC_CFGR_MCO1                      RCC_CFGR_MCO1_Msk
13682 #define RCC_CFGR_MCO1_0                    (0x1UL << RCC_CFGR_MCO1_Pos)         /*!< 0x00200000 */
13683 #define RCC_CFGR_MCO1_1                    (0x2UL << RCC_CFGR_MCO1_Pos)         /*!< 0x00400000 */
13684 
13685 #define RCC_CFGR_I2SSRC_Pos                (23U)
13686 #define RCC_CFGR_I2SSRC_Msk                (0x1UL << RCC_CFGR_I2SSRC_Pos)       /*!< 0x00800000 */
13687 #define RCC_CFGR_I2SSRC                    RCC_CFGR_I2SSRC_Msk
13688 
13689 #define RCC_CFGR_MCO1PRE_Pos               (24U)
13690 #define RCC_CFGR_MCO1PRE_Msk               (0x7UL << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x07000000 */
13691 #define RCC_CFGR_MCO1PRE                   RCC_CFGR_MCO1PRE_Msk
13692 #define RCC_CFGR_MCO1PRE_0                 (0x1UL << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x01000000 */
13693 #define RCC_CFGR_MCO1PRE_1                 (0x2UL << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x02000000 */
13694 #define RCC_CFGR_MCO1PRE_2                 (0x4UL << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x04000000 */
13695 
13696 #define RCC_CFGR_MCO2PRE_Pos               (27U)
13697 #define RCC_CFGR_MCO2PRE_Msk               (0x7UL << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x38000000 */
13698 #define RCC_CFGR_MCO2PRE                   RCC_CFGR_MCO2PRE_Msk
13699 #define RCC_CFGR_MCO2PRE_0                 (0x1UL << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x08000000 */
13700 #define RCC_CFGR_MCO2PRE_1                 (0x2UL << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x10000000 */
13701 #define RCC_CFGR_MCO2PRE_2                 (0x4UL << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x20000000 */
13702 
13703 #define RCC_CFGR_MCO2_Pos                  (30U)
13704 #define RCC_CFGR_MCO2_Msk                  (0x3UL << RCC_CFGR_MCO2_Pos)         /*!< 0xC0000000 */
13705 #define RCC_CFGR_MCO2                      RCC_CFGR_MCO2_Msk
13706 #define RCC_CFGR_MCO2_0                    (0x1UL << RCC_CFGR_MCO2_Pos)         /*!< 0x40000000 */
13707 #define RCC_CFGR_MCO2_1                    (0x2UL << RCC_CFGR_MCO2_Pos)         /*!< 0x80000000 */
13708 
13709 /********************  Bit definition for RCC_CIR register  *******************/
13710 #define RCC_CIR_LSIRDYF_Pos                (0U)
13711 #define RCC_CIR_LSIRDYF_Msk                (0x1UL << RCC_CIR_LSIRDYF_Pos)       /*!< 0x00000001 */
13712 #define RCC_CIR_LSIRDYF                    RCC_CIR_LSIRDYF_Msk
13713 #define RCC_CIR_LSERDYF_Pos                (1U)
13714 #define RCC_CIR_LSERDYF_Msk                (0x1UL << RCC_CIR_LSERDYF_Pos)       /*!< 0x00000002 */
13715 #define RCC_CIR_LSERDYF                    RCC_CIR_LSERDYF_Msk
13716 #define RCC_CIR_HSIRDYF_Pos                (2U)
13717 #define RCC_CIR_HSIRDYF_Msk                (0x1UL << RCC_CIR_HSIRDYF_Pos)       /*!< 0x00000004 */
13718 #define RCC_CIR_HSIRDYF                    RCC_CIR_HSIRDYF_Msk
13719 #define RCC_CIR_HSERDYF_Pos                (3U)
13720 #define RCC_CIR_HSERDYF_Msk                (0x1UL << RCC_CIR_HSERDYF_Pos)       /*!< 0x00000008 */
13721 #define RCC_CIR_HSERDYF                    RCC_CIR_HSERDYF_Msk
13722 #define RCC_CIR_PLLRDYF_Pos                (4U)
13723 #define RCC_CIR_PLLRDYF_Msk                (0x1UL << RCC_CIR_PLLRDYF_Pos)       /*!< 0x00000010 */
13724 #define RCC_CIR_PLLRDYF                    RCC_CIR_PLLRDYF_Msk
13725 #define RCC_CIR_PLLI2SRDYF_Pos             (5U)
13726 #define RCC_CIR_PLLI2SRDYF_Msk             (0x1UL << RCC_CIR_PLLI2SRDYF_Pos)    /*!< 0x00000020 */
13727 #define RCC_CIR_PLLI2SRDYF                 RCC_CIR_PLLI2SRDYF_Msk
13728 
13729 #define RCC_CIR_PLLSAIRDYF_Pos             (6U)
13730 #define RCC_CIR_PLLSAIRDYF_Msk             (0x1UL << RCC_CIR_PLLSAIRDYF_Pos)    /*!< 0x00000040 */
13731 #define RCC_CIR_PLLSAIRDYF                 RCC_CIR_PLLSAIRDYF_Msk
13732 #define RCC_CIR_CSSF_Pos                   (7U)
13733 #define RCC_CIR_CSSF_Msk                   (0x1UL << RCC_CIR_CSSF_Pos)          /*!< 0x00000080 */
13734 #define RCC_CIR_CSSF                       RCC_CIR_CSSF_Msk
13735 #define RCC_CIR_LSIRDYIE_Pos               (8U)
13736 #define RCC_CIR_LSIRDYIE_Msk               (0x1UL << RCC_CIR_LSIRDYIE_Pos)      /*!< 0x00000100 */
13737 #define RCC_CIR_LSIRDYIE                   RCC_CIR_LSIRDYIE_Msk
13738 #define RCC_CIR_LSERDYIE_Pos               (9U)
13739 #define RCC_CIR_LSERDYIE_Msk               (0x1UL << RCC_CIR_LSERDYIE_Pos)      /*!< 0x00000200 */
13740 #define RCC_CIR_LSERDYIE                   RCC_CIR_LSERDYIE_Msk
13741 #define RCC_CIR_HSIRDYIE_Pos               (10U)
13742 #define RCC_CIR_HSIRDYIE_Msk               (0x1UL << RCC_CIR_HSIRDYIE_Pos)      /*!< 0x00000400 */
13743 #define RCC_CIR_HSIRDYIE                   RCC_CIR_HSIRDYIE_Msk
13744 #define RCC_CIR_HSERDYIE_Pos               (11U)
13745 #define RCC_CIR_HSERDYIE_Msk               (0x1UL << RCC_CIR_HSERDYIE_Pos)      /*!< 0x00000800 */
13746 #define RCC_CIR_HSERDYIE                   RCC_CIR_HSERDYIE_Msk
13747 #define RCC_CIR_PLLRDYIE_Pos               (12U)
13748 #define RCC_CIR_PLLRDYIE_Msk               (0x1UL << RCC_CIR_PLLRDYIE_Pos)      /*!< 0x00001000 */
13749 #define RCC_CIR_PLLRDYIE                   RCC_CIR_PLLRDYIE_Msk
13750 #define RCC_CIR_PLLI2SRDYIE_Pos            (13U)
13751 #define RCC_CIR_PLLI2SRDYIE_Msk            (0x1UL << RCC_CIR_PLLI2SRDYIE_Pos)   /*!< 0x00002000 */
13752 #define RCC_CIR_PLLI2SRDYIE                RCC_CIR_PLLI2SRDYIE_Msk
13753 
13754 #define RCC_CIR_PLLSAIRDYIE_Pos            (14U)
13755 #define RCC_CIR_PLLSAIRDYIE_Msk            (0x1UL << RCC_CIR_PLLSAIRDYIE_Pos)   /*!< 0x00004000 */
13756 #define RCC_CIR_PLLSAIRDYIE                RCC_CIR_PLLSAIRDYIE_Msk
13757 #define RCC_CIR_LSIRDYC_Pos                (16U)
13758 #define RCC_CIR_LSIRDYC_Msk                (0x1UL << RCC_CIR_LSIRDYC_Pos)       /*!< 0x00010000 */
13759 #define RCC_CIR_LSIRDYC                    RCC_CIR_LSIRDYC_Msk
13760 #define RCC_CIR_LSERDYC_Pos                (17U)
13761 #define RCC_CIR_LSERDYC_Msk                (0x1UL << RCC_CIR_LSERDYC_Pos)       /*!< 0x00020000 */
13762 #define RCC_CIR_LSERDYC                    RCC_CIR_LSERDYC_Msk
13763 #define RCC_CIR_HSIRDYC_Pos                (18U)
13764 #define RCC_CIR_HSIRDYC_Msk                (0x1UL << RCC_CIR_HSIRDYC_Pos)       /*!< 0x00040000 */
13765 #define RCC_CIR_HSIRDYC                    RCC_CIR_HSIRDYC_Msk
13766 #define RCC_CIR_HSERDYC_Pos                (19U)
13767 #define RCC_CIR_HSERDYC_Msk                (0x1UL << RCC_CIR_HSERDYC_Pos)       /*!< 0x00080000 */
13768 #define RCC_CIR_HSERDYC                    RCC_CIR_HSERDYC_Msk
13769 #define RCC_CIR_PLLRDYC_Pos                (20U)
13770 #define RCC_CIR_PLLRDYC_Msk                (0x1UL << RCC_CIR_PLLRDYC_Pos)       /*!< 0x00100000 */
13771 #define RCC_CIR_PLLRDYC                    RCC_CIR_PLLRDYC_Msk
13772 #define RCC_CIR_PLLI2SRDYC_Pos             (21U)
13773 #define RCC_CIR_PLLI2SRDYC_Msk             (0x1UL << RCC_CIR_PLLI2SRDYC_Pos)    /*!< 0x00200000 */
13774 #define RCC_CIR_PLLI2SRDYC                 RCC_CIR_PLLI2SRDYC_Msk
13775 #define RCC_CIR_PLLSAIRDYC_Pos             (22U)
13776 #define RCC_CIR_PLLSAIRDYC_Msk             (0x1UL << RCC_CIR_PLLSAIRDYC_Pos)    /*!< 0x00400000 */
13777 #define RCC_CIR_PLLSAIRDYC                 RCC_CIR_PLLSAIRDYC_Msk
13778 
13779 #define RCC_CIR_CSSC_Pos                   (23U)
13780 #define RCC_CIR_CSSC_Msk                   (0x1UL << RCC_CIR_CSSC_Pos)          /*!< 0x00800000 */
13781 #define RCC_CIR_CSSC                       RCC_CIR_CSSC_Msk
13782 
13783 /********************  Bit definition for RCC_AHB1RSTR register  **************/
13784 #define RCC_AHB1RSTR_GPIOARST_Pos          (0U)
13785 #define RCC_AHB1RSTR_GPIOARST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */
13786 #define RCC_AHB1RSTR_GPIOARST              RCC_AHB1RSTR_GPIOARST_Msk
13787 #define RCC_AHB1RSTR_GPIOBRST_Pos          (1U)
13788 #define RCC_AHB1RSTR_GPIOBRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
13789 #define RCC_AHB1RSTR_GPIOBRST              RCC_AHB1RSTR_GPIOBRST_Msk
13790 #define RCC_AHB1RSTR_GPIOCRST_Pos          (2U)
13791 #define RCC_AHB1RSTR_GPIOCRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
13792 #define RCC_AHB1RSTR_GPIOCRST              RCC_AHB1RSTR_GPIOCRST_Msk
13793 #define RCC_AHB1RSTR_GPIODRST_Pos          (3U)
13794 #define RCC_AHB1RSTR_GPIODRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIODRST_Pos) /*!< 0x00000008 */
13795 #define RCC_AHB1RSTR_GPIODRST              RCC_AHB1RSTR_GPIODRST_Msk
13796 #define RCC_AHB1RSTR_GPIOERST_Pos          (4U)
13797 #define RCC_AHB1RSTR_GPIOERST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOERST_Pos) /*!< 0x00000010 */
13798 #define RCC_AHB1RSTR_GPIOERST              RCC_AHB1RSTR_GPIOERST_Msk
13799 #define RCC_AHB1RSTR_GPIOFRST_Pos          (5U)
13800 #define RCC_AHB1RSTR_GPIOFRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOFRST_Pos) /*!< 0x00000020 */
13801 #define RCC_AHB1RSTR_GPIOFRST              RCC_AHB1RSTR_GPIOFRST_Msk
13802 #define RCC_AHB1RSTR_GPIOGRST_Pos          (6U)
13803 #define RCC_AHB1RSTR_GPIOGRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOGRST_Pos) /*!< 0x00000040 */
13804 #define RCC_AHB1RSTR_GPIOGRST              RCC_AHB1RSTR_GPIOGRST_Msk
13805 #define RCC_AHB1RSTR_GPIOHRST_Pos          (7U)
13806 #define RCC_AHB1RSTR_GPIOHRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
13807 #define RCC_AHB1RSTR_GPIOHRST              RCC_AHB1RSTR_GPIOHRST_Msk
13808 #define RCC_AHB1RSTR_GPIOIRST_Pos          (8U)
13809 #define RCC_AHB1RSTR_GPIOIRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOIRST_Pos) /*!< 0x00000100 */
13810 #define RCC_AHB1RSTR_GPIOIRST              RCC_AHB1RSTR_GPIOIRST_Msk
13811 #define RCC_AHB1RSTR_GPIOJRST_Pos          (9U)
13812 #define RCC_AHB1RSTR_GPIOJRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOJRST_Pos) /*!< 0x00000200 */
13813 #define RCC_AHB1RSTR_GPIOJRST              RCC_AHB1RSTR_GPIOJRST_Msk
13814 #define RCC_AHB1RSTR_GPIOKRST_Pos          (10U)
13815 #define RCC_AHB1RSTR_GPIOKRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOKRST_Pos) /*!< 0x00000400 */
13816 #define RCC_AHB1RSTR_GPIOKRST              RCC_AHB1RSTR_GPIOKRST_Msk
13817 #define RCC_AHB1RSTR_CRCRST_Pos            (12U)
13818 #define RCC_AHB1RSTR_CRCRST_Msk            (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)   /*!< 0x00001000 */
13819 #define RCC_AHB1RSTR_CRCRST                RCC_AHB1RSTR_CRCRST_Msk
13820 #define RCC_AHB1RSTR_DMA1RST_Pos           (21U)
13821 #define RCC_AHB1RSTR_DMA1RST_Msk           (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)  /*!< 0x00200000 */
13822 #define RCC_AHB1RSTR_DMA1RST               RCC_AHB1RSTR_DMA1RST_Msk
13823 #define RCC_AHB1RSTR_DMA2RST_Pos           (22U)
13824 #define RCC_AHB1RSTR_DMA2RST_Msk           (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)  /*!< 0x00400000 */
13825 #define RCC_AHB1RSTR_DMA2RST               RCC_AHB1RSTR_DMA2RST_Msk
13826 #define RCC_AHB1RSTR_DMA2DRST_Pos          (23U)
13827 #define RCC_AHB1RSTR_DMA2DRST_Msk          (0x1UL << RCC_AHB1RSTR_DMA2DRST_Pos) /*!< 0x00800000 */
13828 #define RCC_AHB1RSTR_DMA2DRST              RCC_AHB1RSTR_DMA2DRST_Msk
13829 #define RCC_AHB1RSTR_ETHMACRST_Pos         (25U)
13830 #define RCC_AHB1RSTR_ETHMACRST_Msk         (0x1UL << RCC_AHB1RSTR_ETHMACRST_Pos) /*!< 0x02000000 */
13831 #define RCC_AHB1RSTR_ETHMACRST             RCC_AHB1RSTR_ETHMACRST_Msk
13832 #define RCC_AHB1RSTR_OTGHRST_Pos           (29U)
13833 #define RCC_AHB1RSTR_OTGHRST_Msk           (0x1UL << RCC_AHB1RSTR_OTGHRST_Pos)  /*!< 0x20000000 */
13834 #define RCC_AHB1RSTR_OTGHRST               RCC_AHB1RSTR_OTGHRST_Msk
13835 
13836 /********************  Bit definition for RCC_AHB2RSTR register  **************/
13837 #define RCC_AHB2RSTR_DCMIRST_Pos           (0U)
13838 #define RCC_AHB2RSTR_DCMIRST_Msk           (0x1UL << RCC_AHB2RSTR_DCMIRST_Pos)  /*!< 0x00000001 */
13839 #define RCC_AHB2RSTR_DCMIRST               RCC_AHB2RSTR_DCMIRST_Msk
13840 #define RCC_AHB2RSTR_RNGRST_Pos            (6U)
13841 #define RCC_AHB2RSTR_RNGRST_Msk            (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)   /*!< 0x00000040 */
13842 #define RCC_AHB2RSTR_RNGRST                RCC_AHB2RSTR_RNGRST_Msk
13843 #define RCC_AHB2RSTR_OTGFSRST_Pos          (7U)
13844 #define RCC_AHB2RSTR_OTGFSRST_Msk          (0x1UL << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00000080 */
13845 #define RCC_AHB2RSTR_OTGFSRST              RCC_AHB2RSTR_OTGFSRST_Msk
13846 /********************  Bit definition for RCC_AHB3RSTR register  **************/
13847 #define RCC_AHB3RSTR_FMCRST_Pos            (0U)
13848 #define RCC_AHB3RSTR_FMCRST_Msk            (0x1UL << RCC_AHB3RSTR_FMCRST_Pos)   /*!< 0x00000001 */
13849 #define RCC_AHB3RSTR_FMCRST                RCC_AHB3RSTR_FMCRST_Msk
13850 #define RCC_AHB3RSTR_QSPIRST_Pos           (1U)
13851 #define RCC_AHB3RSTR_QSPIRST_Msk           (0x1UL << RCC_AHB3RSTR_QSPIRST_Pos)  /*!< 0x00000002 */
13852 #define RCC_AHB3RSTR_QSPIRST               RCC_AHB3RSTR_QSPIRST_Msk
13853 
13854 
13855 /********************  Bit definition for RCC_APB1RSTR register  **************/
13856 #define RCC_APB1RSTR_TIM2RST_Pos           (0U)
13857 #define RCC_APB1RSTR_TIM2RST_Msk           (0x1UL << RCC_APB1RSTR_TIM2RST_Pos)  /*!< 0x00000001 */
13858 #define RCC_APB1RSTR_TIM2RST               RCC_APB1RSTR_TIM2RST_Msk
13859 #define RCC_APB1RSTR_TIM3RST_Pos           (1U)
13860 #define RCC_APB1RSTR_TIM3RST_Msk           (0x1UL << RCC_APB1RSTR_TIM3RST_Pos)  /*!< 0x00000002 */
13861 #define RCC_APB1RSTR_TIM3RST               RCC_APB1RSTR_TIM3RST_Msk
13862 #define RCC_APB1RSTR_TIM4RST_Pos           (2U)
13863 #define RCC_APB1RSTR_TIM4RST_Msk           (0x1UL << RCC_APB1RSTR_TIM4RST_Pos)  /*!< 0x00000004 */
13864 #define RCC_APB1RSTR_TIM4RST               RCC_APB1RSTR_TIM4RST_Msk
13865 #define RCC_APB1RSTR_TIM5RST_Pos           (3U)
13866 #define RCC_APB1RSTR_TIM5RST_Msk           (0x1UL << RCC_APB1RSTR_TIM5RST_Pos)  /*!< 0x00000008 */
13867 #define RCC_APB1RSTR_TIM5RST               RCC_APB1RSTR_TIM5RST_Msk
13868 #define RCC_APB1RSTR_TIM6RST_Pos           (4U)
13869 #define RCC_APB1RSTR_TIM6RST_Msk           (0x1UL << RCC_APB1RSTR_TIM6RST_Pos)  /*!< 0x00000010 */
13870 #define RCC_APB1RSTR_TIM6RST               RCC_APB1RSTR_TIM6RST_Msk
13871 #define RCC_APB1RSTR_TIM7RST_Pos           (5U)
13872 #define RCC_APB1RSTR_TIM7RST_Msk           (0x1UL << RCC_APB1RSTR_TIM7RST_Pos)  /*!< 0x00000020 */
13873 #define RCC_APB1RSTR_TIM7RST               RCC_APB1RSTR_TIM7RST_Msk
13874 #define RCC_APB1RSTR_TIM12RST_Pos          (6U)
13875 #define RCC_APB1RSTR_TIM12RST_Msk          (0x1UL << RCC_APB1RSTR_TIM12RST_Pos) /*!< 0x00000040 */
13876 #define RCC_APB1RSTR_TIM12RST              RCC_APB1RSTR_TIM12RST_Msk
13877 #define RCC_APB1RSTR_TIM13RST_Pos          (7U)
13878 #define RCC_APB1RSTR_TIM13RST_Msk          (0x1UL << RCC_APB1RSTR_TIM13RST_Pos) /*!< 0x00000080 */
13879 #define RCC_APB1RSTR_TIM13RST              RCC_APB1RSTR_TIM13RST_Msk
13880 #define RCC_APB1RSTR_TIM14RST_Pos          (8U)
13881 #define RCC_APB1RSTR_TIM14RST_Msk          (0x1UL << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */
13882 #define RCC_APB1RSTR_TIM14RST              RCC_APB1RSTR_TIM14RST_Msk
13883 #define RCC_APB1RSTR_WWDGRST_Pos           (11U)
13884 #define RCC_APB1RSTR_WWDGRST_Msk           (0x1UL << RCC_APB1RSTR_WWDGRST_Pos)  /*!< 0x00000800 */
13885 #define RCC_APB1RSTR_WWDGRST               RCC_APB1RSTR_WWDGRST_Msk
13886 #define RCC_APB1RSTR_SPI2RST_Pos           (14U)
13887 #define RCC_APB1RSTR_SPI2RST_Msk           (0x1UL << RCC_APB1RSTR_SPI2RST_Pos)  /*!< 0x00004000 */
13888 #define RCC_APB1RSTR_SPI2RST               RCC_APB1RSTR_SPI2RST_Msk
13889 #define RCC_APB1RSTR_SPI3RST_Pos           (15U)
13890 #define RCC_APB1RSTR_SPI3RST_Msk           (0x1UL << RCC_APB1RSTR_SPI3RST_Pos)  /*!< 0x00008000 */
13891 #define RCC_APB1RSTR_SPI3RST               RCC_APB1RSTR_SPI3RST_Msk
13892 #define RCC_APB1RSTR_USART2RST_Pos         (17U)
13893 #define RCC_APB1RSTR_USART2RST_Msk         (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
13894 #define RCC_APB1RSTR_USART2RST             RCC_APB1RSTR_USART2RST_Msk
13895 #define RCC_APB1RSTR_USART3RST_Pos         (18U)
13896 #define RCC_APB1RSTR_USART3RST_Msk         (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
13897 #define RCC_APB1RSTR_USART3RST             RCC_APB1RSTR_USART3RST_Msk
13898 #define RCC_APB1RSTR_UART4RST_Pos          (19U)
13899 #define RCC_APB1RSTR_UART4RST_Msk          (0x1UL << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */
13900 #define RCC_APB1RSTR_UART4RST              RCC_APB1RSTR_UART4RST_Msk
13901 #define RCC_APB1RSTR_UART5RST_Pos          (20U)
13902 #define RCC_APB1RSTR_UART5RST_Msk          (0x1UL << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */
13903 #define RCC_APB1RSTR_UART5RST              RCC_APB1RSTR_UART5RST_Msk
13904 #define RCC_APB1RSTR_I2C1RST_Pos           (21U)
13905 #define RCC_APB1RSTR_I2C1RST_Msk           (0x1UL << RCC_APB1RSTR_I2C1RST_Pos)  /*!< 0x00200000 */
13906 #define RCC_APB1RSTR_I2C1RST               RCC_APB1RSTR_I2C1RST_Msk
13907 #define RCC_APB1RSTR_I2C2RST_Pos           (22U)
13908 #define RCC_APB1RSTR_I2C2RST_Msk           (0x1UL << RCC_APB1RSTR_I2C2RST_Pos)  /*!< 0x00400000 */
13909 #define RCC_APB1RSTR_I2C2RST               RCC_APB1RSTR_I2C2RST_Msk
13910 #define RCC_APB1RSTR_I2C3RST_Pos           (23U)
13911 #define RCC_APB1RSTR_I2C3RST_Msk           (0x1UL << RCC_APB1RSTR_I2C3RST_Pos)  /*!< 0x00800000 */
13912 #define RCC_APB1RSTR_I2C3RST               RCC_APB1RSTR_I2C3RST_Msk
13913 #define RCC_APB1RSTR_CAN1RST_Pos           (25U)
13914 #define RCC_APB1RSTR_CAN1RST_Msk           (0x1UL << RCC_APB1RSTR_CAN1RST_Pos)  /*!< 0x02000000 */
13915 #define RCC_APB1RSTR_CAN1RST               RCC_APB1RSTR_CAN1RST_Msk
13916 #define RCC_APB1RSTR_CAN2RST_Pos           (26U)
13917 #define RCC_APB1RSTR_CAN2RST_Msk           (0x1UL << RCC_APB1RSTR_CAN2RST_Pos)  /*!< 0x04000000 */
13918 #define RCC_APB1RSTR_CAN2RST               RCC_APB1RSTR_CAN2RST_Msk
13919 #define RCC_APB1RSTR_PWRRST_Pos            (28U)
13920 #define RCC_APB1RSTR_PWRRST_Msk            (0x1UL << RCC_APB1RSTR_PWRRST_Pos)   /*!< 0x10000000 */
13921 #define RCC_APB1RSTR_PWRRST                RCC_APB1RSTR_PWRRST_Msk
13922 #define RCC_APB1RSTR_DACRST_Pos            (29U)
13923 #define RCC_APB1RSTR_DACRST_Msk            (0x1UL << RCC_APB1RSTR_DACRST_Pos)   /*!< 0x20000000 */
13924 #define RCC_APB1RSTR_DACRST                RCC_APB1RSTR_DACRST_Msk
13925 #define RCC_APB1RSTR_UART7RST_Pos          (30U)
13926 #define RCC_APB1RSTR_UART7RST_Msk          (0x1UL << RCC_APB1RSTR_UART7RST_Pos) /*!< 0x40000000 */
13927 #define RCC_APB1RSTR_UART7RST              RCC_APB1RSTR_UART7RST_Msk
13928 #define RCC_APB1RSTR_UART8RST_Pos          (31U)
13929 #define RCC_APB1RSTR_UART8RST_Msk          (0x1UL << RCC_APB1RSTR_UART8RST_Pos) /*!< 0x80000000 */
13930 #define RCC_APB1RSTR_UART8RST              RCC_APB1RSTR_UART8RST_Msk
13931 
13932 /********************  Bit definition for RCC_APB2RSTR register  **************/
13933 #define RCC_APB2RSTR_TIM1RST_Pos           (0U)
13934 #define RCC_APB2RSTR_TIM1RST_Msk           (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)  /*!< 0x00000001 */
13935 #define RCC_APB2RSTR_TIM1RST               RCC_APB2RSTR_TIM1RST_Msk
13936 #define RCC_APB2RSTR_TIM8RST_Pos           (1U)
13937 #define RCC_APB2RSTR_TIM8RST_Msk           (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)  /*!< 0x00000002 */
13938 #define RCC_APB2RSTR_TIM8RST               RCC_APB2RSTR_TIM8RST_Msk
13939 #define RCC_APB2RSTR_USART1RST_Pos         (4U)
13940 #define RCC_APB2RSTR_USART1RST_Msk         (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
13941 #define RCC_APB2RSTR_USART1RST             RCC_APB2RSTR_USART1RST_Msk
13942 #define RCC_APB2RSTR_USART6RST_Pos         (5U)
13943 #define RCC_APB2RSTR_USART6RST_Msk         (0x1UL << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
13944 #define RCC_APB2RSTR_USART6RST             RCC_APB2RSTR_USART6RST_Msk
13945 #define RCC_APB2RSTR_ADCRST_Pos            (8U)
13946 #define RCC_APB2RSTR_ADCRST_Msk            (0x1UL << RCC_APB2RSTR_ADCRST_Pos)   /*!< 0x00000100 */
13947 #define RCC_APB2RSTR_ADCRST                RCC_APB2RSTR_ADCRST_Msk
13948 #define RCC_APB2RSTR_SDIORST_Pos           (11U)
13949 #define RCC_APB2RSTR_SDIORST_Msk           (0x1UL << RCC_APB2RSTR_SDIORST_Pos)  /*!< 0x00000800 */
13950 #define RCC_APB2RSTR_SDIORST               RCC_APB2RSTR_SDIORST_Msk
13951 #define RCC_APB2RSTR_SPI1RST_Pos           (12U)
13952 #define RCC_APB2RSTR_SPI1RST_Msk           (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)  /*!< 0x00001000 */
13953 #define RCC_APB2RSTR_SPI1RST               RCC_APB2RSTR_SPI1RST_Msk
13954 #define RCC_APB2RSTR_SPI4RST_Pos           (13U)
13955 #define RCC_APB2RSTR_SPI4RST_Msk           (0x1UL << RCC_APB2RSTR_SPI4RST_Pos)  /*!< 0x00002000 */
13956 #define RCC_APB2RSTR_SPI4RST               RCC_APB2RSTR_SPI4RST_Msk
13957 #define RCC_APB2RSTR_SYSCFGRST_Pos         (14U)
13958 #define RCC_APB2RSTR_SYSCFGRST_Msk         (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */
13959 #define RCC_APB2RSTR_SYSCFGRST             RCC_APB2RSTR_SYSCFGRST_Msk
13960 #define RCC_APB2RSTR_TIM9RST_Pos           (16U)
13961 #define RCC_APB2RSTR_TIM9RST_Msk           (0x1UL << RCC_APB2RSTR_TIM9RST_Pos)  /*!< 0x00010000 */
13962 #define RCC_APB2RSTR_TIM9RST               RCC_APB2RSTR_TIM9RST_Msk
13963 #define RCC_APB2RSTR_TIM10RST_Pos          (17U)
13964 #define RCC_APB2RSTR_TIM10RST_Msk          (0x1UL << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00020000 */
13965 #define RCC_APB2RSTR_TIM10RST              RCC_APB2RSTR_TIM10RST_Msk
13966 #define RCC_APB2RSTR_TIM11RST_Pos          (18U)
13967 #define RCC_APB2RSTR_TIM11RST_Msk          (0x1UL << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */
13968 #define RCC_APB2RSTR_TIM11RST              RCC_APB2RSTR_TIM11RST_Msk
13969 #define RCC_APB2RSTR_SPI5RST_Pos           (20U)
13970 #define RCC_APB2RSTR_SPI5RST_Msk           (0x1UL << RCC_APB2RSTR_SPI5RST_Pos)  /*!< 0x00100000 */
13971 #define RCC_APB2RSTR_SPI5RST               RCC_APB2RSTR_SPI5RST_Msk
13972 #define RCC_APB2RSTR_SPI6RST_Pos           (21U)
13973 #define RCC_APB2RSTR_SPI6RST_Msk           (0x1UL << RCC_APB2RSTR_SPI6RST_Pos)  /*!< 0x00200000 */
13974 #define RCC_APB2RSTR_SPI6RST               RCC_APB2RSTR_SPI6RST_Msk
13975 #define RCC_APB2RSTR_SAI1RST_Pos           (22U)
13976 #define RCC_APB2RSTR_SAI1RST_Msk           (0x1UL << RCC_APB2RSTR_SAI1RST_Pos)  /*!< 0x00400000 */
13977 #define RCC_APB2RSTR_SAI1RST               RCC_APB2RSTR_SAI1RST_Msk
13978 #define RCC_APB2RSTR_LTDCRST_Pos           (26U)
13979 #define RCC_APB2RSTR_LTDCRST_Msk           (0x1UL << RCC_APB2RSTR_LTDCRST_Pos)  /*!< 0x04000000 */
13980 #define RCC_APB2RSTR_LTDCRST               RCC_APB2RSTR_LTDCRST_Msk
13981 #define RCC_APB2RSTR_DSIRST_Pos            (27U)
13982 #define RCC_APB2RSTR_DSIRST_Msk            (0x1UL << RCC_APB2RSTR_DSIRST_Pos)   /*!< 0x08000000 */
13983 #define RCC_APB2RSTR_DSIRST                RCC_APB2RSTR_DSIRST_Msk
13984 
13985 /* Old SPI1RST bit definition, maintained for legacy purpose */
13986 #define  RCC_APB2RSTR_SPI1                   RCC_APB2RSTR_SPI1RST
13987 
13988 /********************  Bit definition for RCC_AHB1ENR register  ***************/
13989 #define RCC_AHB1ENR_GPIOAEN_Pos            (0U)
13990 #define RCC_AHB1ENR_GPIOAEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOAEN_Pos)   /*!< 0x00000001 */
13991 #define RCC_AHB1ENR_GPIOAEN                RCC_AHB1ENR_GPIOAEN_Msk
13992 #define RCC_AHB1ENR_GPIOBEN_Pos            (1U)
13993 #define RCC_AHB1ENR_GPIOBEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOBEN_Pos)   /*!< 0x00000002 */
13994 #define RCC_AHB1ENR_GPIOBEN                RCC_AHB1ENR_GPIOBEN_Msk
13995 #define RCC_AHB1ENR_GPIOCEN_Pos            (2U)
13996 #define RCC_AHB1ENR_GPIOCEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOCEN_Pos)   /*!< 0x00000004 */
13997 #define RCC_AHB1ENR_GPIOCEN                RCC_AHB1ENR_GPIOCEN_Msk
13998 #define RCC_AHB1ENR_GPIODEN_Pos            (3U)
13999 #define RCC_AHB1ENR_GPIODEN_Msk            (0x1UL << RCC_AHB1ENR_GPIODEN_Pos)   /*!< 0x00000008 */
14000 #define RCC_AHB1ENR_GPIODEN                RCC_AHB1ENR_GPIODEN_Msk
14001 #define RCC_AHB1ENR_GPIOEEN_Pos            (4U)
14002 #define RCC_AHB1ENR_GPIOEEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOEEN_Pos)   /*!< 0x00000010 */
14003 #define RCC_AHB1ENR_GPIOEEN                RCC_AHB1ENR_GPIOEEN_Msk
14004 #define RCC_AHB1ENR_GPIOFEN_Pos            (5U)
14005 #define RCC_AHB1ENR_GPIOFEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOFEN_Pos)   /*!< 0x00000020 */
14006 #define RCC_AHB1ENR_GPIOFEN                RCC_AHB1ENR_GPIOFEN_Msk
14007 #define RCC_AHB1ENR_GPIOGEN_Pos            (6U)
14008 #define RCC_AHB1ENR_GPIOGEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOGEN_Pos)   /*!< 0x00000040 */
14009 #define RCC_AHB1ENR_GPIOGEN                RCC_AHB1ENR_GPIOGEN_Msk
14010 #define RCC_AHB1ENR_GPIOHEN_Pos            (7U)
14011 #define RCC_AHB1ENR_GPIOHEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOHEN_Pos)   /*!< 0x00000080 */
14012 #define RCC_AHB1ENR_GPIOHEN                RCC_AHB1ENR_GPIOHEN_Msk
14013 #define RCC_AHB1ENR_GPIOIEN_Pos            (8U)
14014 #define RCC_AHB1ENR_GPIOIEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOIEN_Pos)   /*!< 0x00000100 */
14015 #define RCC_AHB1ENR_GPIOIEN                RCC_AHB1ENR_GPIOIEN_Msk
14016 #define RCC_AHB1ENR_GPIOJEN_Pos            (9U)
14017 #define RCC_AHB1ENR_GPIOJEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOJEN_Pos)   /*!< 0x00000200 */
14018 #define RCC_AHB1ENR_GPIOJEN                RCC_AHB1ENR_GPIOJEN_Msk
14019 #define RCC_AHB1ENR_GPIOKEN_Pos            (10U)
14020 #define RCC_AHB1ENR_GPIOKEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOKEN_Pos)   /*!< 0x00000400 */
14021 #define RCC_AHB1ENR_GPIOKEN                RCC_AHB1ENR_GPIOKEN_Msk
14022 #define RCC_AHB1ENR_CRCEN_Pos              (12U)
14023 #define RCC_AHB1ENR_CRCEN_Msk              (0x1UL << RCC_AHB1ENR_CRCEN_Pos)     /*!< 0x00001000 */
14024 #define RCC_AHB1ENR_CRCEN                  RCC_AHB1ENR_CRCEN_Msk
14025 #define RCC_AHB1ENR_BKPSRAMEN_Pos          (18U)
14026 #define RCC_AHB1ENR_BKPSRAMEN_Msk          (0x1UL << RCC_AHB1ENR_BKPSRAMEN_Pos) /*!< 0x00040000 */
14027 #define RCC_AHB1ENR_BKPSRAMEN              RCC_AHB1ENR_BKPSRAMEN_Msk
14028 #define RCC_AHB1ENR_CCMDATARAMEN_Pos       (20U)
14029 #define RCC_AHB1ENR_CCMDATARAMEN_Msk       (0x1UL << RCC_AHB1ENR_CCMDATARAMEN_Pos) /*!< 0x00100000 */
14030 #define RCC_AHB1ENR_CCMDATARAMEN           RCC_AHB1ENR_CCMDATARAMEN_Msk
14031 #define RCC_AHB1ENR_DMA1EN_Pos             (21U)
14032 #define RCC_AHB1ENR_DMA1EN_Msk             (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)    /*!< 0x00200000 */
14033 #define RCC_AHB1ENR_DMA1EN                 RCC_AHB1ENR_DMA1EN_Msk
14034 #define RCC_AHB1ENR_DMA2EN_Pos             (22U)
14035 #define RCC_AHB1ENR_DMA2EN_Msk             (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)    /*!< 0x00400000 */
14036 #define RCC_AHB1ENR_DMA2EN                 RCC_AHB1ENR_DMA2EN_Msk
14037 #define RCC_AHB1ENR_DMA2DEN_Pos            (23U)
14038 #define RCC_AHB1ENR_DMA2DEN_Msk            (0x1UL << RCC_AHB1ENR_DMA2DEN_Pos)   /*!< 0x00800000 */
14039 #define RCC_AHB1ENR_DMA2DEN                RCC_AHB1ENR_DMA2DEN_Msk
14040 #define RCC_AHB1ENR_ETHMACEN_Pos           (25U)
14041 #define RCC_AHB1ENR_ETHMACEN_Msk           (0x1UL << RCC_AHB1ENR_ETHMACEN_Pos)  /*!< 0x02000000 */
14042 #define RCC_AHB1ENR_ETHMACEN               RCC_AHB1ENR_ETHMACEN_Msk
14043 #define RCC_AHB1ENR_ETHMACTXEN_Pos         (26U)
14044 #define RCC_AHB1ENR_ETHMACTXEN_Msk         (0x1UL << RCC_AHB1ENR_ETHMACTXEN_Pos) /*!< 0x04000000 */
14045 #define RCC_AHB1ENR_ETHMACTXEN             RCC_AHB1ENR_ETHMACTXEN_Msk
14046 #define RCC_AHB1ENR_ETHMACRXEN_Pos         (27U)
14047 #define RCC_AHB1ENR_ETHMACRXEN_Msk         (0x1UL << RCC_AHB1ENR_ETHMACRXEN_Pos) /*!< 0x08000000 */
14048 #define RCC_AHB1ENR_ETHMACRXEN             RCC_AHB1ENR_ETHMACRXEN_Msk
14049 #define RCC_AHB1ENR_ETHMACPTPEN_Pos        (28U)
14050 #define RCC_AHB1ENR_ETHMACPTPEN_Msk        (0x1UL << RCC_AHB1ENR_ETHMACPTPEN_Pos) /*!< 0x10000000 */
14051 #define RCC_AHB1ENR_ETHMACPTPEN            RCC_AHB1ENR_ETHMACPTPEN_Msk
14052 #define RCC_AHB1ENR_OTGHSEN_Pos            (29U)
14053 #define RCC_AHB1ENR_OTGHSEN_Msk            (0x1UL << RCC_AHB1ENR_OTGHSEN_Pos)   /*!< 0x20000000 */
14054 #define RCC_AHB1ENR_OTGHSEN                RCC_AHB1ENR_OTGHSEN_Msk
14055 #define RCC_AHB1ENR_OTGHSULPIEN_Pos        (30U)
14056 #define RCC_AHB1ENR_OTGHSULPIEN_Msk        (0x1UL << RCC_AHB1ENR_OTGHSULPIEN_Pos) /*!< 0x40000000 */
14057 #define RCC_AHB1ENR_OTGHSULPIEN            RCC_AHB1ENR_OTGHSULPIEN_Msk
14058 /********************  Bit definition for RCC_AHB2ENR register  ***************/
14059 /*
14060  * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
14061  */
14062 #define RCC_AHB2_SUPPORT                   /*!< AHB2 Bus is supported */
14063 
14064 #define RCC_AHB2ENR_DCMIEN_Pos             (0U)
14065 #define RCC_AHB2ENR_DCMIEN_Msk             (0x1UL << RCC_AHB2ENR_DCMIEN_Pos)    /*!< 0x00000001 */
14066 #define RCC_AHB2ENR_DCMIEN                 RCC_AHB2ENR_DCMIEN_Msk
14067 #define RCC_AHB2ENR_RNGEN_Pos              (6U)
14068 #define RCC_AHB2ENR_RNGEN_Msk              (0x1UL << RCC_AHB2ENR_RNGEN_Pos)     /*!< 0x00000040 */
14069 #define RCC_AHB2ENR_RNGEN                  RCC_AHB2ENR_RNGEN_Msk
14070 #define RCC_AHB2ENR_OTGFSEN_Pos            (7U)
14071 #define RCC_AHB2ENR_OTGFSEN_Msk            (0x1UL << RCC_AHB2ENR_OTGFSEN_Pos)   /*!< 0x00000080 */
14072 #define RCC_AHB2ENR_OTGFSEN                RCC_AHB2ENR_OTGFSEN_Msk
14073 
14074 /********************  Bit definition for RCC_AHB3ENR register  ***************/
14075 /*
14076  * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
14077  */
14078 #define RCC_AHB3_SUPPORT                   /*!< AHB3 Bus is supported */
14079 
14080 #define RCC_AHB3ENR_FMCEN_Pos              (0U)
14081 #define RCC_AHB3ENR_FMCEN_Msk              (0x1UL << RCC_AHB3ENR_FMCEN_Pos)     /*!< 0x00000001 */
14082 #define RCC_AHB3ENR_FMCEN                  RCC_AHB3ENR_FMCEN_Msk
14083 #define RCC_AHB3ENR_QSPIEN_Pos             (1U)
14084 #define RCC_AHB3ENR_QSPIEN_Msk             (0x1UL << RCC_AHB3ENR_QSPIEN_Pos)    /*!< 0x00000002 */
14085 #define RCC_AHB3ENR_QSPIEN                 RCC_AHB3ENR_QSPIEN_Msk
14086 
14087 /********************  Bit definition for RCC_APB1ENR register  ***************/
14088 #define RCC_APB1ENR_TIM2EN_Pos             (0U)
14089 #define RCC_APB1ENR_TIM2EN_Msk             (0x1UL << RCC_APB1ENR_TIM2EN_Pos)    /*!< 0x00000001 */
14090 #define RCC_APB1ENR_TIM2EN                 RCC_APB1ENR_TIM2EN_Msk
14091 #define RCC_APB1ENR_TIM3EN_Pos             (1U)
14092 #define RCC_APB1ENR_TIM3EN_Msk             (0x1UL << RCC_APB1ENR_TIM3EN_Pos)    /*!< 0x00000002 */
14093 #define RCC_APB1ENR_TIM3EN                 RCC_APB1ENR_TIM3EN_Msk
14094 #define RCC_APB1ENR_TIM4EN_Pos             (2U)
14095 #define RCC_APB1ENR_TIM4EN_Msk             (0x1UL << RCC_APB1ENR_TIM4EN_Pos)    /*!< 0x00000004 */
14096 #define RCC_APB1ENR_TIM4EN                 RCC_APB1ENR_TIM4EN_Msk
14097 #define RCC_APB1ENR_TIM5EN_Pos             (3U)
14098 #define RCC_APB1ENR_TIM5EN_Msk             (0x1UL << RCC_APB1ENR_TIM5EN_Pos)    /*!< 0x00000008 */
14099 #define RCC_APB1ENR_TIM5EN                 RCC_APB1ENR_TIM5EN_Msk
14100 #define RCC_APB1ENR_TIM6EN_Pos             (4U)
14101 #define RCC_APB1ENR_TIM6EN_Msk             (0x1UL << RCC_APB1ENR_TIM6EN_Pos)    /*!< 0x00000010 */
14102 #define RCC_APB1ENR_TIM6EN                 RCC_APB1ENR_TIM6EN_Msk
14103 #define RCC_APB1ENR_TIM7EN_Pos             (5U)
14104 #define RCC_APB1ENR_TIM7EN_Msk             (0x1UL << RCC_APB1ENR_TIM7EN_Pos)    /*!< 0x00000020 */
14105 #define RCC_APB1ENR_TIM7EN                 RCC_APB1ENR_TIM7EN_Msk
14106 #define RCC_APB1ENR_TIM12EN_Pos            (6U)
14107 #define RCC_APB1ENR_TIM12EN_Msk            (0x1UL << RCC_APB1ENR_TIM12EN_Pos)   /*!< 0x00000040 */
14108 #define RCC_APB1ENR_TIM12EN                RCC_APB1ENR_TIM12EN_Msk
14109 #define RCC_APB1ENR_TIM13EN_Pos            (7U)
14110 #define RCC_APB1ENR_TIM13EN_Msk            (0x1UL << RCC_APB1ENR_TIM13EN_Pos)   /*!< 0x00000080 */
14111 #define RCC_APB1ENR_TIM13EN                RCC_APB1ENR_TIM13EN_Msk
14112 #define RCC_APB1ENR_TIM14EN_Pos            (8U)
14113 #define RCC_APB1ENR_TIM14EN_Msk            (0x1UL << RCC_APB1ENR_TIM14EN_Pos)   /*!< 0x00000100 */
14114 #define RCC_APB1ENR_TIM14EN                RCC_APB1ENR_TIM14EN_Msk
14115 #define RCC_APB1ENR_WWDGEN_Pos             (11U)
14116 #define RCC_APB1ENR_WWDGEN_Msk             (0x1UL << RCC_APB1ENR_WWDGEN_Pos)    /*!< 0x00000800 */
14117 #define RCC_APB1ENR_WWDGEN                 RCC_APB1ENR_WWDGEN_Msk
14118 #define RCC_APB1ENR_SPI2EN_Pos             (14U)
14119 #define RCC_APB1ENR_SPI2EN_Msk             (0x1UL << RCC_APB1ENR_SPI2EN_Pos)    /*!< 0x00004000 */
14120 #define RCC_APB1ENR_SPI2EN                 RCC_APB1ENR_SPI2EN_Msk
14121 #define RCC_APB1ENR_SPI3EN_Pos             (15U)
14122 #define RCC_APB1ENR_SPI3EN_Msk             (0x1UL << RCC_APB1ENR_SPI3EN_Pos)    /*!< 0x00008000 */
14123 #define RCC_APB1ENR_SPI3EN                 RCC_APB1ENR_SPI3EN_Msk
14124 #define RCC_APB1ENR_USART2EN_Pos           (17U)
14125 #define RCC_APB1ENR_USART2EN_Msk           (0x1UL << RCC_APB1ENR_USART2EN_Pos)  /*!< 0x00020000 */
14126 #define RCC_APB1ENR_USART2EN               RCC_APB1ENR_USART2EN_Msk
14127 #define RCC_APB1ENR_USART3EN_Pos           (18U)
14128 #define RCC_APB1ENR_USART3EN_Msk           (0x1UL << RCC_APB1ENR_USART3EN_Pos)  /*!< 0x00040000 */
14129 #define RCC_APB1ENR_USART3EN               RCC_APB1ENR_USART3EN_Msk
14130 #define RCC_APB1ENR_UART4EN_Pos            (19U)
14131 #define RCC_APB1ENR_UART4EN_Msk            (0x1UL << RCC_APB1ENR_UART4EN_Pos)   /*!< 0x00080000 */
14132 #define RCC_APB1ENR_UART4EN                RCC_APB1ENR_UART4EN_Msk
14133 #define RCC_APB1ENR_UART5EN_Pos            (20U)
14134 #define RCC_APB1ENR_UART5EN_Msk            (0x1UL << RCC_APB1ENR_UART5EN_Pos)   /*!< 0x00100000 */
14135 #define RCC_APB1ENR_UART5EN                RCC_APB1ENR_UART5EN_Msk
14136 #define RCC_APB1ENR_I2C1EN_Pos             (21U)
14137 #define RCC_APB1ENR_I2C1EN_Msk             (0x1UL << RCC_APB1ENR_I2C1EN_Pos)    /*!< 0x00200000 */
14138 #define RCC_APB1ENR_I2C1EN                 RCC_APB1ENR_I2C1EN_Msk
14139 #define RCC_APB1ENR_I2C2EN_Pos             (22U)
14140 #define RCC_APB1ENR_I2C2EN_Msk             (0x1UL << RCC_APB1ENR_I2C2EN_Pos)    /*!< 0x00400000 */
14141 #define RCC_APB1ENR_I2C2EN                 RCC_APB1ENR_I2C2EN_Msk
14142 #define RCC_APB1ENR_I2C3EN_Pos             (23U)
14143 #define RCC_APB1ENR_I2C3EN_Msk             (0x1UL << RCC_APB1ENR_I2C3EN_Pos)    /*!< 0x00800000 */
14144 #define RCC_APB1ENR_I2C3EN                 RCC_APB1ENR_I2C3EN_Msk
14145 #define RCC_APB1ENR_CAN1EN_Pos             (25U)
14146 #define RCC_APB1ENR_CAN1EN_Msk             (0x1UL << RCC_APB1ENR_CAN1EN_Pos)    /*!< 0x02000000 */
14147 #define RCC_APB1ENR_CAN1EN                 RCC_APB1ENR_CAN1EN_Msk
14148 #define RCC_APB1ENR_CAN2EN_Pos             (26U)
14149 #define RCC_APB1ENR_CAN2EN_Msk             (0x1UL << RCC_APB1ENR_CAN2EN_Pos)    /*!< 0x04000000 */
14150 #define RCC_APB1ENR_CAN2EN                 RCC_APB1ENR_CAN2EN_Msk
14151 #define RCC_APB1ENR_PWREN_Pos              (28U)
14152 #define RCC_APB1ENR_PWREN_Msk              (0x1UL << RCC_APB1ENR_PWREN_Pos)     /*!< 0x10000000 */
14153 #define RCC_APB1ENR_PWREN                  RCC_APB1ENR_PWREN_Msk
14154 #define RCC_APB1ENR_DACEN_Pos              (29U)
14155 #define RCC_APB1ENR_DACEN_Msk              (0x1UL << RCC_APB1ENR_DACEN_Pos)     /*!< 0x20000000 */
14156 #define RCC_APB1ENR_DACEN                  RCC_APB1ENR_DACEN_Msk
14157 #define RCC_APB1ENR_UART7EN_Pos            (30U)
14158 #define RCC_APB1ENR_UART7EN_Msk            (0x1UL << RCC_APB1ENR_UART7EN_Pos)   /*!< 0x40000000 */
14159 #define RCC_APB1ENR_UART7EN                RCC_APB1ENR_UART7EN_Msk
14160 #define RCC_APB1ENR_UART8EN_Pos            (31U)
14161 #define RCC_APB1ENR_UART8EN_Msk            (0x1UL << RCC_APB1ENR_UART8EN_Pos)   /*!< 0x80000000 */
14162 #define RCC_APB1ENR_UART8EN                RCC_APB1ENR_UART8EN_Msk
14163 
14164 /********************  Bit definition for RCC_APB2ENR register  ***************/
14165 #define RCC_APB2ENR_TIM1EN_Pos             (0U)
14166 #define RCC_APB2ENR_TIM1EN_Msk             (0x1UL << RCC_APB2ENR_TIM1EN_Pos)    /*!< 0x00000001 */
14167 #define RCC_APB2ENR_TIM1EN                 RCC_APB2ENR_TIM1EN_Msk
14168 #define RCC_APB2ENR_TIM8EN_Pos             (1U)
14169 #define RCC_APB2ENR_TIM8EN_Msk             (0x1UL << RCC_APB2ENR_TIM8EN_Pos)    /*!< 0x00000002 */
14170 #define RCC_APB2ENR_TIM8EN                 RCC_APB2ENR_TIM8EN_Msk
14171 #define RCC_APB2ENR_USART1EN_Pos           (4U)
14172 #define RCC_APB2ENR_USART1EN_Msk           (0x1UL << RCC_APB2ENR_USART1EN_Pos)  /*!< 0x00000010 */
14173 #define RCC_APB2ENR_USART1EN               RCC_APB2ENR_USART1EN_Msk
14174 #define RCC_APB2ENR_USART6EN_Pos           (5U)
14175 #define RCC_APB2ENR_USART6EN_Msk           (0x1UL << RCC_APB2ENR_USART6EN_Pos)  /*!< 0x00000020 */
14176 #define RCC_APB2ENR_USART6EN               RCC_APB2ENR_USART6EN_Msk
14177 #define RCC_APB2ENR_ADC1EN_Pos             (8U)
14178 #define RCC_APB2ENR_ADC1EN_Msk             (0x1UL << RCC_APB2ENR_ADC1EN_Pos)    /*!< 0x00000100 */
14179 #define RCC_APB2ENR_ADC1EN                 RCC_APB2ENR_ADC1EN_Msk
14180 #define RCC_APB2ENR_ADC2EN_Pos             (9U)
14181 #define RCC_APB2ENR_ADC2EN_Msk             (0x1UL << RCC_APB2ENR_ADC2EN_Pos)    /*!< 0x00000200 */
14182 #define RCC_APB2ENR_ADC2EN                 RCC_APB2ENR_ADC2EN_Msk
14183 #define RCC_APB2ENR_ADC3EN_Pos             (10U)
14184 #define RCC_APB2ENR_ADC3EN_Msk             (0x1UL << RCC_APB2ENR_ADC3EN_Pos)    /*!< 0x00000400 */
14185 #define RCC_APB2ENR_ADC3EN                 RCC_APB2ENR_ADC3EN_Msk
14186 #define RCC_APB2ENR_SDIOEN_Pos             (11U)
14187 #define RCC_APB2ENR_SDIOEN_Msk             (0x1UL << RCC_APB2ENR_SDIOEN_Pos)    /*!< 0x00000800 */
14188 #define RCC_APB2ENR_SDIOEN                 RCC_APB2ENR_SDIOEN_Msk
14189 #define RCC_APB2ENR_SPI1EN_Pos             (12U)
14190 #define RCC_APB2ENR_SPI1EN_Msk             (0x1UL << RCC_APB2ENR_SPI1EN_Pos)    /*!< 0x00001000 */
14191 #define RCC_APB2ENR_SPI1EN                 RCC_APB2ENR_SPI1EN_Msk
14192 #define RCC_APB2ENR_SPI4EN_Pos             (13U)
14193 #define RCC_APB2ENR_SPI4EN_Msk             (0x1UL << RCC_APB2ENR_SPI4EN_Pos)    /*!< 0x00002000 */
14194 #define RCC_APB2ENR_SPI4EN                 RCC_APB2ENR_SPI4EN_Msk
14195 #define RCC_APB2ENR_SYSCFGEN_Pos           (14U)
14196 #define RCC_APB2ENR_SYSCFGEN_Msk           (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)  /*!< 0x00004000 */
14197 #define RCC_APB2ENR_SYSCFGEN               RCC_APB2ENR_SYSCFGEN_Msk
14198 #define RCC_APB2ENR_TIM9EN_Pos             (16U)
14199 #define RCC_APB2ENR_TIM9EN_Msk             (0x1UL << RCC_APB2ENR_TIM9EN_Pos)    /*!< 0x00010000 */
14200 #define RCC_APB2ENR_TIM9EN                 RCC_APB2ENR_TIM9EN_Msk
14201 #define RCC_APB2ENR_TIM10EN_Pos            (17U)
14202 #define RCC_APB2ENR_TIM10EN_Msk            (0x1UL << RCC_APB2ENR_TIM10EN_Pos)   /*!< 0x00020000 */
14203 #define RCC_APB2ENR_TIM10EN                RCC_APB2ENR_TIM10EN_Msk
14204 #define RCC_APB2ENR_TIM11EN_Pos            (18U)
14205 #define RCC_APB2ENR_TIM11EN_Msk            (0x1UL << RCC_APB2ENR_TIM11EN_Pos)   /*!< 0x00040000 */
14206 #define RCC_APB2ENR_TIM11EN                RCC_APB2ENR_TIM11EN_Msk
14207 #define RCC_APB2ENR_SPI5EN_Pos             (20U)
14208 #define RCC_APB2ENR_SPI5EN_Msk             (0x1UL << RCC_APB2ENR_SPI5EN_Pos)    /*!< 0x00100000 */
14209 #define RCC_APB2ENR_SPI5EN                 RCC_APB2ENR_SPI5EN_Msk
14210 #define RCC_APB2ENR_SPI6EN_Pos             (21U)
14211 #define RCC_APB2ENR_SPI6EN_Msk             (0x1UL << RCC_APB2ENR_SPI6EN_Pos)    /*!< 0x00200000 */
14212 #define RCC_APB2ENR_SPI6EN                 RCC_APB2ENR_SPI6EN_Msk
14213 #define RCC_APB2ENR_SAI1EN_Pos             (22U)
14214 #define RCC_APB2ENR_SAI1EN_Msk             (0x1UL << RCC_APB2ENR_SAI1EN_Pos)    /*!< 0x00400000 */
14215 #define RCC_APB2ENR_SAI1EN                 RCC_APB2ENR_SAI1EN_Msk
14216 #define RCC_APB2ENR_LTDCEN_Pos             (26U)
14217 #define RCC_APB2ENR_LTDCEN_Msk             (0x1UL << RCC_APB2ENR_LTDCEN_Pos)    /*!< 0x04000000 */
14218 #define RCC_APB2ENR_LTDCEN                 RCC_APB2ENR_LTDCEN_Msk
14219 #define RCC_APB2ENR_DSIEN_Pos              (27U)
14220 #define RCC_APB2ENR_DSIEN_Msk              (0x1UL << RCC_APB2ENR_DSIEN_Pos)     /*!< 0x08000000 */
14221 #define RCC_APB2ENR_DSIEN                  RCC_APB2ENR_DSIEN_Msk
14222 
14223 /********************  Bit definition for RCC_AHB1LPENR register  *************/
14224 #define RCC_AHB1LPENR_GPIOALPEN_Pos        (0U)
14225 #define RCC_AHB1LPENR_GPIOALPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
14226 #define RCC_AHB1LPENR_GPIOALPEN            RCC_AHB1LPENR_GPIOALPEN_Msk
14227 #define RCC_AHB1LPENR_GPIOBLPEN_Pos        (1U)
14228 #define RCC_AHB1LPENR_GPIOBLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
14229 #define RCC_AHB1LPENR_GPIOBLPEN            RCC_AHB1LPENR_GPIOBLPEN_Msk
14230 #define RCC_AHB1LPENR_GPIOCLPEN_Pos        (2U)
14231 #define RCC_AHB1LPENR_GPIOCLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
14232 #define RCC_AHB1LPENR_GPIOCLPEN            RCC_AHB1LPENR_GPIOCLPEN_Msk
14233 #define RCC_AHB1LPENR_GPIODLPEN_Pos        (3U)
14234 #define RCC_AHB1LPENR_GPIODLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
14235 #define RCC_AHB1LPENR_GPIODLPEN            RCC_AHB1LPENR_GPIODLPEN_Msk
14236 #define RCC_AHB1LPENR_GPIOELPEN_Pos        (4U)
14237 #define RCC_AHB1LPENR_GPIOELPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
14238 #define RCC_AHB1LPENR_GPIOELPEN            RCC_AHB1LPENR_GPIOELPEN_Msk
14239 #define RCC_AHB1LPENR_GPIOFLPEN_Pos        (5U)
14240 #define RCC_AHB1LPENR_GPIOFLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */
14241 #define RCC_AHB1LPENR_GPIOFLPEN            RCC_AHB1LPENR_GPIOFLPEN_Msk
14242 #define RCC_AHB1LPENR_GPIOGLPEN_Pos        (6U)
14243 #define RCC_AHB1LPENR_GPIOGLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */
14244 #define RCC_AHB1LPENR_GPIOGLPEN            RCC_AHB1LPENR_GPIOGLPEN_Msk
14245 #define RCC_AHB1LPENR_GPIOHLPEN_Pos        (7U)
14246 #define RCC_AHB1LPENR_GPIOHLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */
14247 #define RCC_AHB1LPENR_GPIOHLPEN            RCC_AHB1LPENR_GPIOHLPEN_Msk
14248 #define RCC_AHB1LPENR_GPIOILPEN_Pos        (8U)
14249 #define RCC_AHB1LPENR_GPIOILPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOILPEN_Pos) /*!< 0x00000100 */
14250 #define RCC_AHB1LPENR_GPIOILPEN            RCC_AHB1LPENR_GPIOILPEN_Msk
14251 #define RCC_AHB1LPENR_GPIOJLPEN_Pos        (9U)
14252 #define RCC_AHB1LPENR_GPIOJLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOJLPEN_Pos) /*!< 0x00000200 */
14253 #define RCC_AHB1LPENR_GPIOJLPEN            RCC_AHB1LPENR_GPIOJLPEN_Msk
14254 #define RCC_AHB1LPENR_GPIOKLPEN_Pos        (10U)
14255 #define RCC_AHB1LPENR_GPIOKLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOKLPEN_Pos) /*!< 0x00000400 */
14256 #define RCC_AHB1LPENR_GPIOKLPEN            RCC_AHB1LPENR_GPIOKLPEN_Msk
14257 #define RCC_AHB1LPENR_CRCLPEN_Pos          (12U)
14258 #define RCC_AHB1LPENR_CRCLPEN_Msk          (0x1UL << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */
14259 #define RCC_AHB1LPENR_CRCLPEN              RCC_AHB1LPENR_CRCLPEN_Msk
14260 #define RCC_AHB1LPENR_FLITFLPEN_Pos        (15U)
14261 #define RCC_AHB1LPENR_FLITFLPEN_Msk        (0x1UL << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
14262 #define RCC_AHB1LPENR_FLITFLPEN            RCC_AHB1LPENR_FLITFLPEN_Msk
14263 #define RCC_AHB1LPENR_SRAM1LPEN_Pos        (16U)
14264 #define RCC_AHB1LPENR_SRAM1LPEN_Msk        (0x1UL << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */
14265 #define RCC_AHB1LPENR_SRAM1LPEN            RCC_AHB1LPENR_SRAM1LPEN_Msk
14266 #define RCC_AHB1LPENR_SRAM2LPEN_Pos        (17U)
14267 #define RCC_AHB1LPENR_SRAM2LPEN_Msk        (0x1UL << RCC_AHB1LPENR_SRAM2LPEN_Pos) /*!< 0x00020000 */
14268 #define RCC_AHB1LPENR_SRAM2LPEN            RCC_AHB1LPENR_SRAM2LPEN_Msk
14269 #define RCC_AHB1LPENR_BKPSRAMLPEN_Pos      (18U)
14270 #define RCC_AHB1LPENR_BKPSRAMLPEN_Msk      (0x1UL << RCC_AHB1LPENR_BKPSRAMLPEN_Pos) /*!< 0x00040000 */
14271 #define RCC_AHB1LPENR_BKPSRAMLPEN          RCC_AHB1LPENR_BKPSRAMLPEN_Msk
14272 #define RCC_AHB1LPENR_SRAM3LPEN_Pos        (19U)
14273 #define RCC_AHB1LPENR_SRAM3LPEN_Msk        (0x1UL << RCC_AHB1LPENR_SRAM3LPEN_Pos) /*!< 0x00080000 */
14274 #define RCC_AHB1LPENR_SRAM3LPEN            RCC_AHB1LPENR_SRAM3LPEN_Msk
14275 #define RCC_AHB1LPENR_DMA1LPEN_Pos         (21U)
14276 #define RCC_AHB1LPENR_DMA1LPEN_Msk         (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */
14277 #define RCC_AHB1LPENR_DMA1LPEN             RCC_AHB1LPENR_DMA1LPEN_Msk
14278 #define RCC_AHB1LPENR_DMA2LPEN_Pos         (22U)
14279 #define RCC_AHB1LPENR_DMA2LPEN_Msk         (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */
14280 #define RCC_AHB1LPENR_DMA2LPEN             RCC_AHB1LPENR_DMA2LPEN_Msk
14281 #define RCC_AHB1LPENR_DMA2DLPEN_Pos        (23U)
14282 #define RCC_AHB1LPENR_DMA2DLPEN_Msk        (0x1UL << RCC_AHB1LPENR_DMA2DLPEN_Pos) /*!< 0x00800000 */
14283 #define RCC_AHB1LPENR_DMA2DLPEN            RCC_AHB1LPENR_DMA2DLPEN_Msk
14284 
14285 #define RCC_AHB1LPENR_ETHMACLPEN_Pos       (25U)
14286 #define RCC_AHB1LPENR_ETHMACLPEN_Msk       (0x1UL << RCC_AHB1LPENR_ETHMACLPEN_Pos) /*!< 0x02000000 */
14287 #define RCC_AHB1LPENR_ETHMACLPEN           RCC_AHB1LPENR_ETHMACLPEN_Msk
14288 #define RCC_AHB1LPENR_ETHMACTXLPEN_Pos     (26U)
14289 #define RCC_AHB1LPENR_ETHMACTXLPEN_Msk     (0x1UL << RCC_AHB1LPENR_ETHMACTXLPEN_Pos) /*!< 0x04000000 */
14290 #define RCC_AHB1LPENR_ETHMACTXLPEN         RCC_AHB1LPENR_ETHMACTXLPEN_Msk
14291 #define RCC_AHB1LPENR_ETHMACRXLPEN_Pos     (27U)
14292 #define RCC_AHB1LPENR_ETHMACRXLPEN_Msk     (0x1UL << RCC_AHB1LPENR_ETHMACRXLPEN_Pos) /*!< 0x08000000 */
14293 #define RCC_AHB1LPENR_ETHMACRXLPEN         RCC_AHB1LPENR_ETHMACRXLPEN_Msk
14294 #define RCC_AHB1LPENR_ETHMACPTPLPEN_Pos    (28U)
14295 #define RCC_AHB1LPENR_ETHMACPTPLPEN_Msk    (0x1UL << RCC_AHB1LPENR_ETHMACPTPLPEN_Pos) /*!< 0x10000000 */
14296 #define RCC_AHB1LPENR_ETHMACPTPLPEN        RCC_AHB1LPENR_ETHMACPTPLPEN_Msk
14297 #define RCC_AHB1LPENR_OTGHSLPEN_Pos        (29U)
14298 #define RCC_AHB1LPENR_OTGHSLPEN_Msk        (0x1UL << RCC_AHB1LPENR_OTGHSLPEN_Pos) /*!< 0x20000000 */
14299 #define RCC_AHB1LPENR_OTGHSLPEN            RCC_AHB1LPENR_OTGHSLPEN_Msk
14300 #define RCC_AHB1LPENR_OTGHSULPILPEN_Pos    (30U)
14301 #define RCC_AHB1LPENR_OTGHSULPILPEN_Msk    (0x1UL << RCC_AHB1LPENR_OTGHSULPILPEN_Pos) /*!< 0x40000000 */
14302 #define RCC_AHB1LPENR_OTGHSULPILPEN        RCC_AHB1LPENR_OTGHSULPILPEN_Msk
14303 
14304 /********************  Bit definition for RCC_AHB2LPENR register  *************/
14305 #define RCC_AHB2LPENR_DCMILPEN_Pos         (0U)
14306 #define RCC_AHB2LPENR_DCMILPEN_Msk         (0x1UL << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */
14307 #define RCC_AHB2LPENR_DCMILPEN             RCC_AHB2LPENR_DCMILPEN_Msk
14308 #define RCC_AHB2LPENR_RNGLPEN_Pos          (6U)
14309 #define RCC_AHB2LPENR_RNGLPEN_Msk          (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */
14310 #define RCC_AHB2LPENR_RNGLPEN              RCC_AHB2LPENR_RNGLPEN_Msk
14311 #define RCC_AHB2LPENR_OTGFSLPEN_Pos        (7U)
14312 #define RCC_AHB2LPENR_OTGFSLPEN_Msk        (0x1UL << RCC_AHB2LPENR_OTGFSLPEN_Pos) /*!< 0x00000080 */
14313 #define RCC_AHB2LPENR_OTGFSLPEN            RCC_AHB2LPENR_OTGFSLPEN_Msk
14314 
14315 /********************  Bit definition for RCC_AHB3LPENR register  *************/
14316 #define RCC_AHB3LPENR_FMCLPEN_Pos          (0U)
14317 #define RCC_AHB3LPENR_FMCLPEN_Msk          (0x1UL << RCC_AHB3LPENR_FMCLPEN_Pos) /*!< 0x00000001 */
14318 #define RCC_AHB3LPENR_FMCLPEN              RCC_AHB3LPENR_FMCLPEN_Msk
14319 #define RCC_AHB3LPENR_QSPILPEN_Pos         (1U)
14320 #define RCC_AHB3LPENR_QSPILPEN_Msk         (0x1UL << RCC_AHB3LPENR_QSPILPEN_Pos) /*!< 0x00000002 */
14321 #define RCC_AHB3LPENR_QSPILPEN             RCC_AHB3LPENR_QSPILPEN_Msk
14322 
14323 /********************  Bit definition for RCC_APB1LPENR register  *************/
14324 #define RCC_APB1LPENR_TIM2LPEN_Pos         (0U)
14325 #define RCC_APB1LPENR_TIM2LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
14326 #define RCC_APB1LPENR_TIM2LPEN             RCC_APB1LPENR_TIM2LPEN_Msk
14327 #define RCC_APB1LPENR_TIM3LPEN_Pos         (1U)
14328 #define RCC_APB1LPENR_TIM3LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
14329 #define RCC_APB1LPENR_TIM3LPEN             RCC_APB1LPENR_TIM3LPEN_Msk
14330 #define RCC_APB1LPENR_TIM4LPEN_Pos         (2U)
14331 #define RCC_APB1LPENR_TIM4LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
14332 #define RCC_APB1LPENR_TIM4LPEN             RCC_APB1LPENR_TIM4LPEN_Msk
14333 #define RCC_APB1LPENR_TIM5LPEN_Pos         (3U)
14334 #define RCC_APB1LPENR_TIM5LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
14335 #define RCC_APB1LPENR_TIM5LPEN             RCC_APB1LPENR_TIM5LPEN_Msk
14336 #define RCC_APB1LPENR_TIM6LPEN_Pos         (4U)
14337 #define RCC_APB1LPENR_TIM6LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
14338 #define RCC_APB1LPENR_TIM6LPEN             RCC_APB1LPENR_TIM6LPEN_Msk
14339 #define RCC_APB1LPENR_TIM7LPEN_Pos         (5U)
14340 #define RCC_APB1LPENR_TIM7LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
14341 #define RCC_APB1LPENR_TIM7LPEN             RCC_APB1LPENR_TIM7LPEN_Msk
14342 #define RCC_APB1LPENR_TIM12LPEN_Pos        (6U)
14343 #define RCC_APB1LPENR_TIM12LPEN_Msk        (0x1UL << RCC_APB1LPENR_TIM12LPEN_Pos) /*!< 0x00000040 */
14344 #define RCC_APB1LPENR_TIM12LPEN            RCC_APB1LPENR_TIM12LPEN_Msk
14345 #define RCC_APB1LPENR_TIM13LPEN_Pos        (7U)
14346 #define RCC_APB1LPENR_TIM13LPEN_Msk        (0x1UL << RCC_APB1LPENR_TIM13LPEN_Pos) /*!< 0x00000080 */
14347 #define RCC_APB1LPENR_TIM13LPEN            RCC_APB1LPENR_TIM13LPEN_Msk
14348 #define RCC_APB1LPENR_TIM14LPEN_Pos        (8U)
14349 #define RCC_APB1LPENR_TIM14LPEN_Msk        (0x1UL << RCC_APB1LPENR_TIM14LPEN_Pos) /*!< 0x00000100 */
14350 #define RCC_APB1LPENR_TIM14LPEN            RCC_APB1LPENR_TIM14LPEN_Msk
14351 #define RCC_APB1LPENR_WWDGLPEN_Pos         (11U)
14352 #define RCC_APB1LPENR_WWDGLPEN_Msk         (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
14353 #define RCC_APB1LPENR_WWDGLPEN             RCC_APB1LPENR_WWDGLPEN_Msk
14354 #define RCC_APB1LPENR_SPI2LPEN_Pos         (14U)
14355 #define RCC_APB1LPENR_SPI2LPEN_Msk         (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
14356 #define RCC_APB1LPENR_SPI2LPEN             RCC_APB1LPENR_SPI2LPEN_Msk
14357 #define RCC_APB1LPENR_SPI3LPEN_Pos         (15U)
14358 #define RCC_APB1LPENR_SPI3LPEN_Msk         (0x1UL << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
14359 #define RCC_APB1LPENR_SPI3LPEN             RCC_APB1LPENR_SPI3LPEN_Msk
14360 #define RCC_APB1LPENR_USART2LPEN_Pos       (17U)
14361 #define RCC_APB1LPENR_USART2LPEN_Msk       (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
14362 #define RCC_APB1LPENR_USART2LPEN           RCC_APB1LPENR_USART2LPEN_Msk
14363 #define RCC_APB1LPENR_USART3LPEN_Pos       (18U)
14364 #define RCC_APB1LPENR_USART3LPEN_Msk       (0x1UL << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */
14365 #define RCC_APB1LPENR_USART3LPEN           RCC_APB1LPENR_USART3LPEN_Msk
14366 #define RCC_APB1LPENR_UART4LPEN_Pos        (19U)
14367 #define RCC_APB1LPENR_UART4LPEN_Msk        (0x1UL << RCC_APB1LPENR_UART4LPEN_Pos) /*!< 0x00080000 */
14368 #define RCC_APB1LPENR_UART4LPEN            RCC_APB1LPENR_UART4LPEN_Msk
14369 #define RCC_APB1LPENR_UART5LPEN_Pos        (20U)
14370 #define RCC_APB1LPENR_UART5LPEN_Msk        (0x1UL << RCC_APB1LPENR_UART5LPEN_Pos) /*!< 0x00100000 */
14371 #define RCC_APB1LPENR_UART5LPEN            RCC_APB1LPENR_UART5LPEN_Msk
14372 #define RCC_APB1LPENR_I2C1LPEN_Pos         (21U)
14373 #define RCC_APB1LPENR_I2C1LPEN_Msk         (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
14374 #define RCC_APB1LPENR_I2C1LPEN             RCC_APB1LPENR_I2C1LPEN_Msk
14375 #define RCC_APB1LPENR_I2C2LPEN_Pos         (22U)
14376 #define RCC_APB1LPENR_I2C2LPEN_Msk         (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
14377 #define RCC_APB1LPENR_I2C2LPEN             RCC_APB1LPENR_I2C2LPEN_Msk
14378 #define RCC_APB1LPENR_I2C3LPEN_Pos         (23U)
14379 #define RCC_APB1LPENR_I2C3LPEN_Msk         (0x1UL << RCC_APB1LPENR_I2C3LPEN_Pos) /*!< 0x00800000 */
14380 #define RCC_APB1LPENR_I2C3LPEN             RCC_APB1LPENR_I2C3LPEN_Msk
14381 #define RCC_APB1LPENR_CAN1LPEN_Pos         (25U)
14382 #define RCC_APB1LPENR_CAN1LPEN_Msk         (0x1UL << RCC_APB1LPENR_CAN1LPEN_Pos) /*!< 0x02000000 */
14383 #define RCC_APB1LPENR_CAN1LPEN             RCC_APB1LPENR_CAN1LPEN_Msk
14384 #define RCC_APB1LPENR_CAN2LPEN_Pos         (26U)
14385 #define RCC_APB1LPENR_CAN2LPEN_Msk         (0x1UL << RCC_APB1LPENR_CAN2LPEN_Pos) /*!< 0x04000000 */
14386 #define RCC_APB1LPENR_CAN2LPEN             RCC_APB1LPENR_CAN2LPEN_Msk
14387 #define RCC_APB1LPENR_PWRLPEN_Pos          (28U)
14388 #define RCC_APB1LPENR_PWRLPEN_Msk          (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
14389 #define RCC_APB1LPENR_PWRLPEN              RCC_APB1LPENR_PWRLPEN_Msk
14390 #define RCC_APB1LPENR_DACLPEN_Pos          (29U)
14391 #define RCC_APB1LPENR_DACLPEN_Msk          (0x1UL << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */
14392 #define RCC_APB1LPENR_DACLPEN              RCC_APB1LPENR_DACLPEN_Msk
14393 #define RCC_APB1LPENR_UART7LPEN_Pos        (30U)
14394 #define RCC_APB1LPENR_UART7LPEN_Msk        (0x1UL << RCC_APB1LPENR_UART7LPEN_Pos) /*!< 0x40000000 */
14395 #define RCC_APB1LPENR_UART7LPEN            RCC_APB1LPENR_UART7LPEN_Msk
14396 #define RCC_APB1LPENR_UART8LPEN_Pos        (31U)
14397 #define RCC_APB1LPENR_UART8LPEN_Msk        (0x1UL << RCC_APB1LPENR_UART8LPEN_Pos) /*!< 0x80000000 */
14398 #define RCC_APB1LPENR_UART8LPEN            RCC_APB1LPENR_UART8LPEN_Msk
14399 
14400 /********************  Bit definition for RCC_APB2LPENR register  *************/
14401 #define RCC_APB2LPENR_TIM1LPEN_Pos         (0U)
14402 #define RCC_APB2LPENR_TIM1LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
14403 #define RCC_APB2LPENR_TIM1LPEN             RCC_APB2LPENR_TIM1LPEN_Msk
14404 #define RCC_APB2LPENR_TIM8LPEN_Pos         (1U)
14405 #define RCC_APB2LPENR_TIM8LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */
14406 #define RCC_APB2LPENR_TIM8LPEN             RCC_APB2LPENR_TIM8LPEN_Msk
14407 #define RCC_APB2LPENR_USART1LPEN_Pos       (4U)
14408 #define RCC_APB2LPENR_USART1LPEN_Msk       (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
14409 #define RCC_APB2LPENR_USART1LPEN           RCC_APB2LPENR_USART1LPEN_Msk
14410 #define RCC_APB2LPENR_USART6LPEN_Pos       (5U)
14411 #define RCC_APB2LPENR_USART6LPEN_Msk       (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
14412 #define RCC_APB2LPENR_USART6LPEN           RCC_APB2LPENR_USART6LPEN_Msk
14413 #define RCC_APB2LPENR_ADC1LPEN_Pos         (8U)
14414 #define RCC_APB2LPENR_ADC1LPEN_Msk         (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */
14415 #define RCC_APB2LPENR_ADC1LPEN             RCC_APB2LPENR_ADC1LPEN_Msk
14416 #define RCC_APB2LPENR_ADC2LPEN_Pos         (9U)
14417 #define RCC_APB2LPENR_ADC2LPEN_Msk         (0x1UL << RCC_APB2LPENR_ADC2LPEN_Pos) /*!< 0x00000200 */
14418 #define RCC_APB2LPENR_ADC2LPEN             RCC_APB2LPENR_ADC2LPEN_Msk
14419 #define RCC_APB2LPENR_ADC3LPEN_Pos         (10U)
14420 #define RCC_APB2LPENR_ADC3LPEN_Msk         (0x1UL << RCC_APB2LPENR_ADC3LPEN_Pos) /*!< 0x00000400 */
14421 #define RCC_APB2LPENR_ADC3LPEN             RCC_APB2LPENR_ADC3LPEN_Msk
14422 #define RCC_APB2LPENR_SDIOLPEN_Pos         (11U)
14423 #define RCC_APB2LPENR_SDIOLPEN_Msk         (0x1UL << RCC_APB2LPENR_SDIOLPEN_Pos) /*!< 0x00000800 */
14424 #define RCC_APB2LPENR_SDIOLPEN             RCC_APB2LPENR_SDIOLPEN_Msk
14425 #define RCC_APB2LPENR_SPI1LPEN_Pos         (12U)
14426 #define RCC_APB2LPENR_SPI1LPEN_Msk         (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
14427 #define RCC_APB2LPENR_SPI1LPEN             RCC_APB2LPENR_SPI1LPEN_Msk
14428 #define RCC_APB2LPENR_SPI4LPEN_Pos         (13U)
14429 #define RCC_APB2LPENR_SPI4LPEN_Msk         (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */
14430 #define RCC_APB2LPENR_SPI4LPEN             RCC_APB2LPENR_SPI4LPEN_Msk
14431 #define RCC_APB2LPENR_SYSCFGLPEN_Pos       (14U)
14432 #define RCC_APB2LPENR_SYSCFGLPEN_Msk       (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */
14433 #define RCC_APB2LPENR_SYSCFGLPEN           RCC_APB2LPENR_SYSCFGLPEN_Msk
14434 #define RCC_APB2LPENR_TIM9LPEN_Pos         (16U)
14435 #define RCC_APB2LPENR_TIM9LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */
14436 #define RCC_APB2LPENR_TIM9LPEN             RCC_APB2LPENR_TIM9LPEN_Msk
14437 #define RCC_APB2LPENR_TIM10LPEN_Pos        (17U)
14438 #define RCC_APB2LPENR_TIM10LPEN_Msk        (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00020000 */
14439 #define RCC_APB2LPENR_TIM10LPEN            RCC_APB2LPENR_TIM10LPEN_Msk
14440 #define RCC_APB2LPENR_TIM11LPEN_Pos        (18U)
14441 #define RCC_APB2LPENR_TIM11LPEN_Msk        (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */
14442 #define RCC_APB2LPENR_TIM11LPEN            RCC_APB2LPENR_TIM11LPEN_Msk
14443 #define RCC_APB2LPENR_SPI5LPEN_Pos         (20U)
14444 #define RCC_APB2LPENR_SPI5LPEN_Msk         (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */
14445 #define RCC_APB2LPENR_SPI5LPEN             RCC_APB2LPENR_SPI5LPEN_Msk
14446 #define RCC_APB2LPENR_SPI6LPEN_Pos         (21U)
14447 #define RCC_APB2LPENR_SPI6LPEN_Msk         (0x1UL << RCC_APB2LPENR_SPI6LPEN_Pos) /*!< 0x00200000 */
14448 #define RCC_APB2LPENR_SPI6LPEN             RCC_APB2LPENR_SPI6LPEN_Msk
14449 #define RCC_APB2LPENR_SAI1LPEN_Pos         (22U)
14450 #define RCC_APB2LPENR_SAI1LPEN_Msk         (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */
14451 #define RCC_APB2LPENR_SAI1LPEN             RCC_APB2LPENR_SAI1LPEN_Msk
14452 #define RCC_APB2LPENR_LTDCLPEN_Pos         (26U)
14453 #define RCC_APB2LPENR_LTDCLPEN_Msk         (0x1UL << RCC_APB2LPENR_LTDCLPEN_Pos) /*!< 0x04000000 */
14454 #define RCC_APB2LPENR_LTDCLPEN             RCC_APB2LPENR_LTDCLPEN_Msk
14455 #define RCC_APB2LPENR_DSILPEN_Pos          (27U)
14456 #define RCC_APB2LPENR_DSILPEN_Msk          (0x1UL << RCC_APB2LPENR_DSILPEN_Pos) /*!< 0x08000000 */
14457 #define RCC_APB2LPENR_DSILPEN              RCC_APB2LPENR_DSILPEN_Msk
14458 
14459 /********************  Bit definition for RCC_BDCR register  ******************/
14460 #define RCC_BDCR_LSEON_Pos                 (0U)
14461 #define RCC_BDCR_LSEON_Msk                 (0x1UL << RCC_BDCR_LSEON_Pos)        /*!< 0x00000001 */
14462 #define RCC_BDCR_LSEON                     RCC_BDCR_LSEON_Msk
14463 #define RCC_BDCR_LSERDY_Pos                (1U)
14464 #define RCC_BDCR_LSERDY_Msk                (0x1UL << RCC_BDCR_LSERDY_Pos)       /*!< 0x00000002 */
14465 #define RCC_BDCR_LSERDY                    RCC_BDCR_LSERDY_Msk
14466 #define RCC_BDCR_LSEBYP_Pos                (2U)
14467 #define RCC_BDCR_LSEBYP_Msk                (0x1UL << RCC_BDCR_LSEBYP_Pos)       /*!< 0x00000004 */
14468 #define RCC_BDCR_LSEBYP                    RCC_BDCR_LSEBYP_Msk
14469 #define RCC_BDCR_LSEMOD_Pos                (3U)
14470 #define RCC_BDCR_LSEMOD_Msk                (0x1UL << RCC_BDCR_LSEMOD_Pos)       /*!< 0x00000008 */
14471 #define RCC_BDCR_LSEMOD                    RCC_BDCR_LSEMOD_Msk
14472 
14473 #define RCC_BDCR_RTCSEL_Pos                (8U)
14474 #define RCC_BDCR_RTCSEL_Msk                (0x3UL << RCC_BDCR_RTCSEL_Pos)       /*!< 0x00000300 */
14475 #define RCC_BDCR_RTCSEL                    RCC_BDCR_RTCSEL_Msk
14476 #define RCC_BDCR_RTCSEL_0                  (0x1UL << RCC_BDCR_RTCSEL_Pos)       /*!< 0x00000100 */
14477 #define RCC_BDCR_RTCSEL_1                  (0x2UL << RCC_BDCR_RTCSEL_Pos)       /*!< 0x00000200 */
14478 
14479 #define RCC_BDCR_RTCEN_Pos                 (15U)
14480 #define RCC_BDCR_RTCEN_Msk                 (0x1UL << RCC_BDCR_RTCEN_Pos)        /*!< 0x00008000 */
14481 #define RCC_BDCR_RTCEN                     RCC_BDCR_RTCEN_Msk
14482 #define RCC_BDCR_BDRST_Pos                 (16U)
14483 #define RCC_BDCR_BDRST_Msk                 (0x1UL << RCC_BDCR_BDRST_Pos)        /*!< 0x00010000 */
14484 #define RCC_BDCR_BDRST                     RCC_BDCR_BDRST_Msk
14485 
14486 /********************  Bit definition for RCC_CSR register  *******************/
14487 #define RCC_CSR_LSION_Pos                  (0U)
14488 #define RCC_CSR_LSION_Msk                  (0x1UL << RCC_CSR_LSION_Pos)         /*!< 0x00000001 */
14489 #define RCC_CSR_LSION                      RCC_CSR_LSION_Msk
14490 #define RCC_CSR_LSIRDY_Pos                 (1U)
14491 #define RCC_CSR_LSIRDY_Msk                 (0x1UL << RCC_CSR_LSIRDY_Pos)        /*!< 0x00000002 */
14492 #define RCC_CSR_LSIRDY                     RCC_CSR_LSIRDY_Msk
14493 #define RCC_CSR_RMVF_Pos                   (24U)
14494 #define RCC_CSR_RMVF_Msk                   (0x1UL << RCC_CSR_RMVF_Pos)          /*!< 0x01000000 */
14495 #define RCC_CSR_RMVF                       RCC_CSR_RMVF_Msk
14496 #define RCC_CSR_BORRSTF_Pos                (25U)
14497 #define RCC_CSR_BORRSTF_Msk                (0x1UL << RCC_CSR_BORRSTF_Pos)       /*!< 0x02000000 */
14498 #define RCC_CSR_BORRSTF                    RCC_CSR_BORRSTF_Msk
14499 #define RCC_CSR_PINRSTF_Pos                (26U)
14500 #define RCC_CSR_PINRSTF_Msk                (0x1UL << RCC_CSR_PINRSTF_Pos)       /*!< 0x04000000 */
14501 #define RCC_CSR_PINRSTF                    RCC_CSR_PINRSTF_Msk
14502 #define RCC_CSR_PORRSTF_Pos                (27U)
14503 #define RCC_CSR_PORRSTF_Msk                (0x1UL << RCC_CSR_PORRSTF_Pos)       /*!< 0x08000000 */
14504 #define RCC_CSR_PORRSTF                    RCC_CSR_PORRSTF_Msk
14505 #define RCC_CSR_SFTRSTF_Pos                (28U)
14506 #define RCC_CSR_SFTRSTF_Msk                (0x1UL << RCC_CSR_SFTRSTF_Pos)       /*!< 0x10000000 */
14507 #define RCC_CSR_SFTRSTF                    RCC_CSR_SFTRSTF_Msk
14508 #define RCC_CSR_IWDGRSTF_Pos               (29U)
14509 #define RCC_CSR_IWDGRSTF_Msk               (0x1UL << RCC_CSR_IWDGRSTF_Pos)      /*!< 0x20000000 */
14510 #define RCC_CSR_IWDGRSTF                   RCC_CSR_IWDGRSTF_Msk
14511 #define RCC_CSR_WWDGRSTF_Pos               (30U)
14512 #define RCC_CSR_WWDGRSTF_Msk               (0x1UL << RCC_CSR_WWDGRSTF_Pos)      /*!< 0x40000000 */
14513 #define RCC_CSR_WWDGRSTF                   RCC_CSR_WWDGRSTF_Msk
14514 #define RCC_CSR_LPWRRSTF_Pos               (31U)
14515 #define RCC_CSR_LPWRRSTF_Msk               (0x1UL << RCC_CSR_LPWRRSTF_Pos)      /*!< 0x80000000 */
14516 #define RCC_CSR_LPWRRSTF                   RCC_CSR_LPWRRSTF_Msk
14517 /* Legacy defines */
14518 #define RCC_CSR_PADRSTF                    RCC_CSR_PINRSTF
14519 #define RCC_CSR_WDGRSTF                    RCC_CSR_IWDGRSTF
14520 
14521 /********************  Bit definition for RCC_SSCGR register  *****************/
14522 #define RCC_SSCGR_MODPER_Pos               (0U)
14523 #define RCC_SSCGR_MODPER_Msk               (0x1FFFUL << RCC_SSCGR_MODPER_Pos)   /*!< 0x00001FFF */
14524 #define RCC_SSCGR_MODPER                   RCC_SSCGR_MODPER_Msk
14525 #define RCC_SSCGR_INCSTEP_Pos              (13U)
14526 #define RCC_SSCGR_INCSTEP_Msk              (0x7FFFUL << RCC_SSCGR_INCSTEP_Pos)  /*!< 0x0FFFE000 */
14527 #define RCC_SSCGR_INCSTEP                  RCC_SSCGR_INCSTEP_Msk
14528 #define RCC_SSCGR_SPREADSEL_Pos            (30U)
14529 #define RCC_SSCGR_SPREADSEL_Msk            (0x1UL << RCC_SSCGR_SPREADSEL_Pos)   /*!< 0x40000000 */
14530 #define RCC_SSCGR_SPREADSEL                RCC_SSCGR_SPREADSEL_Msk
14531 #define RCC_SSCGR_SSCGEN_Pos               (31U)
14532 #define RCC_SSCGR_SSCGEN_Msk               (0x1UL << RCC_SSCGR_SSCGEN_Pos)      /*!< 0x80000000 */
14533 #define RCC_SSCGR_SSCGEN                   RCC_SSCGR_SSCGEN_Msk
14534 
14535 /********************  Bit definition for RCC_PLLI2SCFGR register  ************/
14536 #define RCC_PLLI2SCFGR_PLLI2SN_Pos         (6U)
14537 #define RCC_PLLI2SCFGR_PLLI2SN_Msk         (0x1FFUL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00007FC0 */
14538 #define RCC_PLLI2SCFGR_PLLI2SN             RCC_PLLI2SCFGR_PLLI2SN_Msk
14539 #define RCC_PLLI2SCFGR_PLLI2SN_0           (0x001UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000040 */
14540 #define RCC_PLLI2SCFGR_PLLI2SN_1           (0x002UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000080 */
14541 #define RCC_PLLI2SCFGR_PLLI2SN_2           (0x004UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000100 */
14542 #define RCC_PLLI2SCFGR_PLLI2SN_3           (0x008UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000200 */
14543 #define RCC_PLLI2SCFGR_PLLI2SN_4           (0x010UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000400 */
14544 #define RCC_PLLI2SCFGR_PLLI2SN_5           (0x020UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000800 */
14545 #define RCC_PLLI2SCFGR_PLLI2SN_6           (0x040UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00001000 */
14546 #define RCC_PLLI2SCFGR_PLLI2SN_7           (0x080UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00002000 */
14547 #define RCC_PLLI2SCFGR_PLLI2SN_8           (0x100UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00004000 */
14548 
14549 #define RCC_PLLI2SCFGR_PLLI2SQ_Pos         (24U)
14550 #define RCC_PLLI2SCFGR_PLLI2SQ_Msk         (0xFUL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x0F000000 */
14551 #define RCC_PLLI2SCFGR_PLLI2SQ             RCC_PLLI2SCFGR_PLLI2SQ_Msk
14552 #define RCC_PLLI2SCFGR_PLLI2SQ_0           (0x1UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x01000000 */
14553 #define RCC_PLLI2SCFGR_PLLI2SQ_1           (0x2UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x02000000 */
14554 #define RCC_PLLI2SCFGR_PLLI2SQ_2           (0x4UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x04000000 */
14555 #define RCC_PLLI2SCFGR_PLLI2SQ_3           (0x8UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x08000000 */
14556 #define RCC_PLLI2SCFGR_PLLI2SR_Pos         (28U)
14557 #define RCC_PLLI2SCFGR_PLLI2SR_Msk         (0x7UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x70000000 */
14558 #define RCC_PLLI2SCFGR_PLLI2SR             RCC_PLLI2SCFGR_PLLI2SR_Msk
14559 #define RCC_PLLI2SCFGR_PLLI2SR_0           (0x1UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x10000000 */
14560 #define RCC_PLLI2SCFGR_PLLI2SR_1           (0x2UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x20000000 */
14561 #define RCC_PLLI2SCFGR_PLLI2SR_2           (0x4UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x40000000 */
14562 
14563 /********************  Bit definition for RCC_PLLSAICFGR register  ************/
14564 #define RCC_PLLSAICFGR_PLLSAIN_Pos         (6U)
14565 #define RCC_PLLSAICFGR_PLLSAIN_Msk         (0x1FFUL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00007FC0 */
14566 #define RCC_PLLSAICFGR_PLLSAIN             RCC_PLLSAICFGR_PLLSAIN_Msk
14567 #define RCC_PLLSAICFGR_PLLSAIN_0           (0x001UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000040 */
14568 #define RCC_PLLSAICFGR_PLLSAIN_1           (0x002UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000080 */
14569 #define RCC_PLLSAICFGR_PLLSAIN_2           (0x004UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000100 */
14570 #define RCC_PLLSAICFGR_PLLSAIN_3           (0x008UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000200 */
14571 #define RCC_PLLSAICFGR_PLLSAIN_4           (0x010UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000400 */
14572 #define RCC_PLLSAICFGR_PLLSAIN_5           (0x020UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000800 */
14573 #define RCC_PLLSAICFGR_PLLSAIN_6           (0x040UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00001000 */
14574 #define RCC_PLLSAICFGR_PLLSAIN_7           (0x080UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00002000 */
14575 #define RCC_PLLSAICFGR_PLLSAIN_8           (0x100UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00004000 */
14576 
14577 #define RCC_PLLSAICFGR_PLLSAIP_Pos         (16U)
14578 #define RCC_PLLSAICFGR_PLLSAIP_Msk         (0x3UL << RCC_PLLSAICFGR_PLLSAIP_Pos) /*!< 0x00030000 */
14579 #define RCC_PLLSAICFGR_PLLSAIP             RCC_PLLSAICFGR_PLLSAIP_Msk
14580 #define RCC_PLLSAICFGR_PLLSAIP_0           (0x1UL << RCC_PLLSAICFGR_PLLSAIP_Pos) /*!< 0x00010000 */
14581 #define RCC_PLLSAICFGR_PLLSAIP_1           (0x2UL << RCC_PLLSAICFGR_PLLSAIP_Pos) /*!< 0x00020000 */
14582 
14583 #define RCC_PLLSAICFGR_PLLSAIQ_Pos         (24U)
14584 #define RCC_PLLSAICFGR_PLLSAIQ_Msk         (0xFUL << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x0F000000 */
14585 #define RCC_PLLSAICFGR_PLLSAIQ             RCC_PLLSAICFGR_PLLSAIQ_Msk
14586 #define RCC_PLLSAICFGR_PLLSAIQ_0           (0x1UL << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x01000000 */
14587 #define RCC_PLLSAICFGR_PLLSAIQ_1           (0x2UL << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x02000000 */
14588 #define RCC_PLLSAICFGR_PLLSAIQ_2           (0x4UL << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x04000000 */
14589 #define RCC_PLLSAICFGR_PLLSAIQ_3           (0x8UL << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x08000000 */
14590 
14591 #define RCC_PLLSAICFGR_PLLSAIR_Pos         (28U)
14592 #define RCC_PLLSAICFGR_PLLSAIR_Msk         (0x7UL << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x70000000 */
14593 #define RCC_PLLSAICFGR_PLLSAIR             RCC_PLLSAICFGR_PLLSAIR_Msk
14594 #define RCC_PLLSAICFGR_PLLSAIR_0           (0x1UL << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x10000000 */
14595 #define RCC_PLLSAICFGR_PLLSAIR_1           (0x2UL << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x20000000 */
14596 #define RCC_PLLSAICFGR_PLLSAIR_2           (0x4UL << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x40000000 */
14597 
14598 /********************  Bit definition for RCC_DCKCFGR register  ***************/
14599 #define RCC_DCKCFGR_PLLI2SDIVQ_Pos        (0U)
14600 #define RCC_DCKCFGR_PLLI2SDIVQ_Msk        (0x1FUL << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x0000001F */
14601 #define RCC_DCKCFGR_PLLI2SDIVQ            RCC_DCKCFGR_PLLI2SDIVQ_Msk
14602 #define RCC_DCKCFGR_PLLI2SDIVQ_0          (0x01UL << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000001 */
14603 #define RCC_DCKCFGR_PLLI2SDIVQ_1          (0x02UL << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000002 */
14604 #define RCC_DCKCFGR_PLLI2SDIVQ_2          (0x04UL << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000004 */
14605 #define RCC_DCKCFGR_PLLI2SDIVQ_3          (0x08UL << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000008 */
14606 #define RCC_DCKCFGR_PLLI2SDIVQ_4          (0x10UL << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000010 */
14607 
14608 #define RCC_DCKCFGR_PLLSAIDIVQ_Pos        (8U)
14609 #define RCC_DCKCFGR_PLLSAIDIVQ_Msk        (0x1FUL << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00001F00 */
14610 #define RCC_DCKCFGR_PLLSAIDIVQ            RCC_DCKCFGR_PLLSAIDIVQ_Msk
14611 #define RCC_DCKCFGR_PLLSAIDIVQ_0          (0x01UL << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000100 */
14612 #define RCC_DCKCFGR_PLLSAIDIVQ_1          (0x02UL << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000200 */
14613 #define RCC_DCKCFGR_PLLSAIDIVQ_2          (0x04UL << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000400 */
14614 #define RCC_DCKCFGR_PLLSAIDIVQ_3          (0x08UL << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000800 */
14615 #define RCC_DCKCFGR_PLLSAIDIVQ_4          (0x10UL << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00001000 */
14616 #define RCC_DCKCFGR_PLLSAIDIVR_Pos        (16U)
14617 #define RCC_DCKCFGR_PLLSAIDIVR_Msk        (0x3UL << RCC_DCKCFGR_PLLSAIDIVR_Pos) /*!< 0x00030000 */
14618 #define RCC_DCKCFGR_PLLSAIDIVR            RCC_DCKCFGR_PLLSAIDIVR_Msk
14619 #define RCC_DCKCFGR_PLLSAIDIVR_0          (0x1UL << RCC_DCKCFGR_PLLSAIDIVR_Pos) /*!< 0x00010000 */
14620 #define RCC_DCKCFGR_PLLSAIDIVR_1          (0x2UL << RCC_DCKCFGR_PLLSAIDIVR_Pos) /*!< 0x00020000 */
14621 
14622 #define RCC_DCKCFGR_SAI1ASRC_Pos           (20U)
14623 #define RCC_DCKCFGR_SAI1ASRC_Msk           (0x3UL << RCC_DCKCFGR_SAI1ASRC_Pos)  /*!< 0x00300000 */
14624 #define RCC_DCKCFGR_SAI1ASRC               RCC_DCKCFGR_SAI1ASRC_Msk
14625 #define RCC_DCKCFGR_SAI1ASRC_0             (0x1UL << RCC_DCKCFGR_SAI1ASRC_Pos)  /*!< 0x00100000 */
14626 #define RCC_DCKCFGR_SAI1ASRC_1             (0x2UL << RCC_DCKCFGR_SAI1ASRC_Pos)  /*!< 0x00200000 */
14627 #define RCC_DCKCFGR_SAI1BSRC_Pos           (22U)
14628 #define RCC_DCKCFGR_SAI1BSRC_Msk           (0x3UL << RCC_DCKCFGR_SAI1BSRC_Pos)  /*!< 0x00C00000 */
14629 #define RCC_DCKCFGR_SAI1BSRC               RCC_DCKCFGR_SAI1BSRC_Msk
14630 #define RCC_DCKCFGR_SAI1BSRC_0             (0x1UL << RCC_DCKCFGR_SAI1BSRC_Pos)  /*!< 0x00400000 */
14631 #define RCC_DCKCFGR_SAI1BSRC_1             (0x2UL << RCC_DCKCFGR_SAI1BSRC_Pos)  /*!< 0x00800000 */
14632 #define RCC_DCKCFGR_TIMPRE_Pos             (24U)
14633 #define RCC_DCKCFGR_TIMPRE_Msk             (0x1UL << RCC_DCKCFGR_TIMPRE_Pos)    /*!< 0x01000000 */
14634 #define RCC_DCKCFGR_TIMPRE                 RCC_DCKCFGR_TIMPRE_Msk
14635 #define RCC_DCKCFGR_CK48MSEL_Pos           (27U)
14636 #define RCC_DCKCFGR_CK48MSEL_Msk           (0x1UL << RCC_DCKCFGR_CK48MSEL_Pos)  /*!< 0x08000000 */
14637 #define RCC_DCKCFGR_CK48MSEL               RCC_DCKCFGR_CK48MSEL_Msk
14638 #define RCC_DCKCFGR_SDIOSEL_Pos            (28U)
14639 #define RCC_DCKCFGR_SDIOSEL_Msk            (0x1UL << RCC_DCKCFGR_SDIOSEL_Pos)   /*!< 0x10000000 */
14640 #define RCC_DCKCFGR_SDIOSEL                RCC_DCKCFGR_SDIOSEL_Msk
14641 #define RCC_DCKCFGR_DSISEL_Pos             (29U)
14642 #define RCC_DCKCFGR_DSISEL_Msk             (0x1UL << RCC_DCKCFGR_DSISEL_Pos)    /*!< 0x20000000 */
14643 #define RCC_DCKCFGR_DSISEL                 RCC_DCKCFGR_DSISEL_Msk
14644 
14645 
14646 /******************************************************************************/
14647 /*                                                                            */
14648 /*                                    RNG                                     */
14649 /*                                                                            */
14650 /******************************************************************************/
14651 /********************  Bits definition for RNG_CR register  *******************/
14652 #define RNG_CR_RNGEN_Pos    (2U)
14653 #define RNG_CR_RNGEN_Msk    (0x1UL << RNG_CR_RNGEN_Pos)                         /*!< 0x00000004 */
14654 #define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk
14655 #define RNG_CR_IE_Pos       (3U)
14656 #define RNG_CR_IE_Msk       (0x1UL << RNG_CR_IE_Pos)                            /*!< 0x00000008 */
14657 #define RNG_CR_IE           RNG_CR_IE_Msk
14658 
14659 /********************  Bits definition for RNG_SR register  *******************/
14660 #define RNG_SR_DRDY_Pos     (0U)
14661 #define RNG_SR_DRDY_Msk     (0x1UL << RNG_SR_DRDY_Pos)                          /*!< 0x00000001 */
14662 #define RNG_SR_DRDY         RNG_SR_DRDY_Msk
14663 #define RNG_SR_CECS_Pos     (1U)
14664 #define RNG_SR_CECS_Msk     (0x1UL << RNG_SR_CECS_Pos)                          /*!< 0x00000002 */
14665 #define RNG_SR_CECS         RNG_SR_CECS_Msk
14666 #define RNG_SR_SECS_Pos     (2U)
14667 #define RNG_SR_SECS_Msk     (0x1UL << RNG_SR_SECS_Pos)                          /*!< 0x00000004 */
14668 #define RNG_SR_SECS         RNG_SR_SECS_Msk
14669 #define RNG_SR_CEIS_Pos     (5U)
14670 #define RNG_SR_CEIS_Msk     (0x1UL << RNG_SR_CEIS_Pos)                          /*!< 0x00000020 */
14671 #define RNG_SR_CEIS         RNG_SR_CEIS_Msk
14672 #define RNG_SR_SEIS_Pos     (6U)
14673 #define RNG_SR_SEIS_Msk     (0x1UL << RNG_SR_SEIS_Pos)                          /*!< 0x00000040 */
14674 #define RNG_SR_SEIS         RNG_SR_SEIS_Msk
14675 
14676 /******************************************************************************/
14677 /*                                                                            */
14678 /*                           Real-Time Clock (RTC)                            */
14679 /*                                                                            */
14680 /******************************************************************************/
14681 /*
14682  * @brief Specific device feature definitions  (not present on all devices in the STM32F4 serie)
14683  */
14684 #define RTC_TAMPER2_SUPPORT  /*!< TAMPER 2 feature support */
14685 #define RTC_AF2_SUPPORT /*!< RTC Alternate Function 2 mapping support */
14686 /********************  Bits definition for RTC_TR register  *******************/
14687 #define RTC_TR_PM_Pos                 (22U)
14688 #define RTC_TR_PM_Msk                 (0x1UL << RTC_TR_PM_Pos)                  /*!< 0x00400000 */
14689 #define RTC_TR_PM                     RTC_TR_PM_Msk
14690 #define RTC_TR_HT_Pos                 (20U)
14691 #define RTC_TR_HT_Msk                 (0x3UL << RTC_TR_HT_Pos)                  /*!< 0x00300000 */
14692 #define RTC_TR_HT                     RTC_TR_HT_Msk
14693 #define RTC_TR_HT_0                   (0x1UL << RTC_TR_HT_Pos)                  /*!< 0x00100000 */
14694 #define RTC_TR_HT_1                   (0x2UL << RTC_TR_HT_Pos)                  /*!< 0x00200000 */
14695 #define RTC_TR_HU_Pos                 (16U)
14696 #define RTC_TR_HU_Msk                 (0xFUL << RTC_TR_HU_Pos)                  /*!< 0x000F0000 */
14697 #define RTC_TR_HU                     RTC_TR_HU_Msk
14698 #define RTC_TR_HU_0                   (0x1UL << RTC_TR_HU_Pos)                  /*!< 0x00010000 */
14699 #define RTC_TR_HU_1                   (0x2UL << RTC_TR_HU_Pos)                  /*!< 0x00020000 */
14700 #define RTC_TR_HU_2                   (0x4UL << RTC_TR_HU_Pos)                  /*!< 0x00040000 */
14701 #define RTC_TR_HU_3                   (0x8UL << RTC_TR_HU_Pos)                  /*!< 0x00080000 */
14702 #define RTC_TR_MNT_Pos                (12U)
14703 #define RTC_TR_MNT_Msk                (0x7UL << RTC_TR_MNT_Pos)                 /*!< 0x00007000 */
14704 #define RTC_TR_MNT                    RTC_TR_MNT_Msk
14705 #define RTC_TR_MNT_0                  (0x1UL << RTC_TR_MNT_Pos)                 /*!< 0x00001000 */
14706 #define RTC_TR_MNT_1                  (0x2UL << RTC_TR_MNT_Pos)                 /*!< 0x00002000 */
14707 #define RTC_TR_MNT_2                  (0x4UL << RTC_TR_MNT_Pos)                 /*!< 0x00004000 */
14708 #define RTC_TR_MNU_Pos                (8U)
14709 #define RTC_TR_MNU_Msk                (0xFUL << RTC_TR_MNU_Pos)                 /*!< 0x00000F00 */
14710 #define RTC_TR_MNU                    RTC_TR_MNU_Msk
14711 #define RTC_TR_MNU_0                  (0x1UL << RTC_TR_MNU_Pos)                 /*!< 0x00000100 */
14712 #define RTC_TR_MNU_1                  (0x2UL << RTC_TR_MNU_Pos)                 /*!< 0x00000200 */
14713 #define RTC_TR_MNU_2                  (0x4UL << RTC_TR_MNU_Pos)                 /*!< 0x00000400 */
14714 #define RTC_TR_MNU_3                  (0x8UL << RTC_TR_MNU_Pos)                 /*!< 0x00000800 */
14715 #define RTC_TR_ST_Pos                 (4U)
14716 #define RTC_TR_ST_Msk                 (0x7UL << RTC_TR_ST_Pos)                  /*!< 0x00000070 */
14717 #define RTC_TR_ST                     RTC_TR_ST_Msk
14718 #define RTC_TR_ST_0                   (0x1UL << RTC_TR_ST_Pos)                  /*!< 0x00000010 */
14719 #define RTC_TR_ST_1                   (0x2UL << RTC_TR_ST_Pos)                  /*!< 0x00000020 */
14720 #define RTC_TR_ST_2                   (0x4UL << RTC_TR_ST_Pos)                  /*!< 0x00000040 */
14721 #define RTC_TR_SU_Pos                 (0U)
14722 #define RTC_TR_SU_Msk                 (0xFUL << RTC_TR_SU_Pos)                  /*!< 0x0000000F */
14723 #define RTC_TR_SU                     RTC_TR_SU_Msk
14724 #define RTC_TR_SU_0                   (0x1UL << RTC_TR_SU_Pos)                  /*!< 0x00000001 */
14725 #define RTC_TR_SU_1                   (0x2UL << RTC_TR_SU_Pos)                  /*!< 0x00000002 */
14726 #define RTC_TR_SU_2                   (0x4UL << RTC_TR_SU_Pos)                  /*!< 0x00000004 */
14727 #define RTC_TR_SU_3                   (0x8UL << RTC_TR_SU_Pos)                  /*!< 0x00000008 */
14728 
14729 /********************  Bits definition for RTC_DR register  *******************/
14730 #define RTC_DR_YT_Pos                 (20U)
14731 #define RTC_DR_YT_Msk                 (0xFUL << RTC_DR_YT_Pos)                  /*!< 0x00F00000 */
14732 #define RTC_DR_YT                     RTC_DR_YT_Msk
14733 #define RTC_DR_YT_0                   (0x1UL << RTC_DR_YT_Pos)                  /*!< 0x00100000 */
14734 #define RTC_DR_YT_1                   (0x2UL << RTC_DR_YT_Pos)                  /*!< 0x00200000 */
14735 #define RTC_DR_YT_2                   (0x4UL << RTC_DR_YT_Pos)                  /*!< 0x00400000 */
14736 #define RTC_DR_YT_3                   (0x8UL << RTC_DR_YT_Pos)                  /*!< 0x00800000 */
14737 #define RTC_DR_YU_Pos                 (16U)
14738 #define RTC_DR_YU_Msk                 (0xFUL << RTC_DR_YU_Pos)                  /*!< 0x000F0000 */
14739 #define RTC_DR_YU                     RTC_DR_YU_Msk
14740 #define RTC_DR_YU_0                   (0x1UL << RTC_DR_YU_Pos)                  /*!< 0x00010000 */
14741 #define RTC_DR_YU_1                   (0x2UL << RTC_DR_YU_Pos)                  /*!< 0x00020000 */
14742 #define RTC_DR_YU_2                   (0x4UL << RTC_DR_YU_Pos)                  /*!< 0x00040000 */
14743 #define RTC_DR_YU_3                   (0x8UL << RTC_DR_YU_Pos)                  /*!< 0x00080000 */
14744 #define RTC_DR_WDU_Pos                (13U)
14745 #define RTC_DR_WDU_Msk                (0x7UL << RTC_DR_WDU_Pos)                 /*!< 0x0000E000 */
14746 #define RTC_DR_WDU                    RTC_DR_WDU_Msk
14747 #define RTC_DR_WDU_0                  (0x1UL << RTC_DR_WDU_Pos)                 /*!< 0x00002000 */
14748 #define RTC_DR_WDU_1                  (0x2UL << RTC_DR_WDU_Pos)                 /*!< 0x00004000 */
14749 #define RTC_DR_WDU_2                  (0x4UL << RTC_DR_WDU_Pos)                 /*!< 0x00008000 */
14750 #define RTC_DR_MT_Pos                 (12U)
14751 #define RTC_DR_MT_Msk                 (0x1UL << RTC_DR_MT_Pos)                  /*!< 0x00001000 */
14752 #define RTC_DR_MT                     RTC_DR_MT_Msk
14753 #define RTC_DR_MU_Pos                 (8U)
14754 #define RTC_DR_MU_Msk                 (0xFUL << RTC_DR_MU_Pos)                  /*!< 0x00000F00 */
14755 #define RTC_DR_MU                     RTC_DR_MU_Msk
14756 #define RTC_DR_MU_0                   (0x1UL << RTC_DR_MU_Pos)                  /*!< 0x00000100 */
14757 #define RTC_DR_MU_1                   (0x2UL << RTC_DR_MU_Pos)                  /*!< 0x00000200 */
14758 #define RTC_DR_MU_2                   (0x4UL << RTC_DR_MU_Pos)                  /*!< 0x00000400 */
14759 #define RTC_DR_MU_3                   (0x8UL << RTC_DR_MU_Pos)                  /*!< 0x00000800 */
14760 #define RTC_DR_DT_Pos                 (4U)
14761 #define RTC_DR_DT_Msk                 (0x3UL << RTC_DR_DT_Pos)                  /*!< 0x00000030 */
14762 #define RTC_DR_DT                     RTC_DR_DT_Msk
14763 #define RTC_DR_DT_0                   (0x1UL << RTC_DR_DT_Pos)                  /*!< 0x00000010 */
14764 #define RTC_DR_DT_1                   (0x2UL << RTC_DR_DT_Pos)                  /*!< 0x00000020 */
14765 #define RTC_DR_DU_Pos                 (0U)
14766 #define RTC_DR_DU_Msk                 (0xFUL << RTC_DR_DU_Pos)                  /*!< 0x0000000F */
14767 #define RTC_DR_DU                     RTC_DR_DU_Msk
14768 #define RTC_DR_DU_0                   (0x1UL << RTC_DR_DU_Pos)                  /*!< 0x00000001 */
14769 #define RTC_DR_DU_1                   (0x2UL << RTC_DR_DU_Pos)                  /*!< 0x00000002 */
14770 #define RTC_DR_DU_2                   (0x4UL << RTC_DR_DU_Pos)                  /*!< 0x00000004 */
14771 #define RTC_DR_DU_3                   (0x8UL << RTC_DR_DU_Pos)                  /*!< 0x00000008 */
14772 
14773 /********************  Bits definition for RTC_CR register  *******************/
14774 #define RTC_CR_COE_Pos                (23U)
14775 #define RTC_CR_COE_Msk                (0x1UL << RTC_CR_COE_Pos)                 /*!< 0x00800000 */
14776 #define RTC_CR_COE                    RTC_CR_COE_Msk
14777 #define RTC_CR_OSEL_Pos               (21U)
14778 #define RTC_CR_OSEL_Msk               (0x3UL << RTC_CR_OSEL_Pos)                /*!< 0x00600000 */
14779 #define RTC_CR_OSEL                   RTC_CR_OSEL_Msk
14780 #define RTC_CR_OSEL_0                 (0x1UL << RTC_CR_OSEL_Pos)                /*!< 0x00200000 */
14781 #define RTC_CR_OSEL_1                 (0x2UL << RTC_CR_OSEL_Pos)                /*!< 0x00400000 */
14782 #define RTC_CR_POL_Pos                (20U)
14783 #define RTC_CR_POL_Msk                (0x1UL << RTC_CR_POL_Pos)                 /*!< 0x00100000 */
14784 #define RTC_CR_POL                    RTC_CR_POL_Msk
14785 #define RTC_CR_COSEL_Pos              (19U)
14786 #define RTC_CR_COSEL_Msk              (0x1UL << RTC_CR_COSEL_Pos)               /*!< 0x00080000 */
14787 #define RTC_CR_COSEL                  RTC_CR_COSEL_Msk
14788 #define RTC_CR_BKP_Pos                 (18U)
14789 #define RTC_CR_BKP_Msk                 (0x1UL << RTC_CR_BKP_Pos)                /*!< 0x00040000 */
14790 #define RTC_CR_BKP                     RTC_CR_BKP_Msk
14791 #define RTC_CR_SUB1H_Pos              (17U)
14792 #define RTC_CR_SUB1H_Msk              (0x1UL << RTC_CR_SUB1H_Pos)               /*!< 0x00020000 */
14793 #define RTC_CR_SUB1H                  RTC_CR_SUB1H_Msk
14794 #define RTC_CR_ADD1H_Pos              (16U)
14795 #define RTC_CR_ADD1H_Msk              (0x1UL << RTC_CR_ADD1H_Pos)               /*!< 0x00010000 */
14796 #define RTC_CR_ADD1H                  RTC_CR_ADD1H_Msk
14797 #define RTC_CR_TSIE_Pos               (15U)
14798 #define RTC_CR_TSIE_Msk               (0x1UL << RTC_CR_TSIE_Pos)                /*!< 0x00008000 */
14799 #define RTC_CR_TSIE                   RTC_CR_TSIE_Msk
14800 #define RTC_CR_WUTIE_Pos              (14U)
14801 #define RTC_CR_WUTIE_Msk              (0x1UL << RTC_CR_WUTIE_Pos)               /*!< 0x00004000 */
14802 #define RTC_CR_WUTIE                  RTC_CR_WUTIE_Msk
14803 #define RTC_CR_ALRBIE_Pos             (13U)
14804 #define RTC_CR_ALRBIE_Msk             (0x1UL << RTC_CR_ALRBIE_Pos)              /*!< 0x00002000 */
14805 #define RTC_CR_ALRBIE                 RTC_CR_ALRBIE_Msk
14806 #define RTC_CR_ALRAIE_Pos             (12U)
14807 #define RTC_CR_ALRAIE_Msk             (0x1UL << RTC_CR_ALRAIE_Pos)              /*!< 0x00001000 */
14808 #define RTC_CR_ALRAIE                 RTC_CR_ALRAIE_Msk
14809 #define RTC_CR_TSE_Pos                (11U)
14810 #define RTC_CR_TSE_Msk                (0x1UL << RTC_CR_TSE_Pos)                 /*!< 0x00000800 */
14811 #define RTC_CR_TSE                    RTC_CR_TSE_Msk
14812 #define RTC_CR_WUTE_Pos               (10U)
14813 #define RTC_CR_WUTE_Msk               (0x1UL << RTC_CR_WUTE_Pos)                /*!< 0x00000400 */
14814 #define RTC_CR_WUTE                   RTC_CR_WUTE_Msk
14815 #define RTC_CR_ALRBE_Pos              (9U)
14816 #define RTC_CR_ALRBE_Msk              (0x1UL << RTC_CR_ALRBE_Pos)               /*!< 0x00000200 */
14817 #define RTC_CR_ALRBE                  RTC_CR_ALRBE_Msk
14818 #define RTC_CR_ALRAE_Pos              (8U)
14819 #define RTC_CR_ALRAE_Msk              (0x1UL << RTC_CR_ALRAE_Pos)               /*!< 0x00000100 */
14820 #define RTC_CR_ALRAE                  RTC_CR_ALRAE_Msk
14821 #define RTC_CR_DCE_Pos                (7U)
14822 #define RTC_CR_DCE_Msk                (0x1UL << RTC_CR_DCE_Pos)                 /*!< 0x00000080 */
14823 #define RTC_CR_DCE                    RTC_CR_DCE_Msk
14824 #define RTC_CR_FMT_Pos                (6U)
14825 #define RTC_CR_FMT_Msk                (0x1UL << RTC_CR_FMT_Pos)                 /*!< 0x00000040 */
14826 #define RTC_CR_FMT                    RTC_CR_FMT_Msk
14827 #define RTC_CR_BYPSHAD_Pos            (5U)
14828 #define RTC_CR_BYPSHAD_Msk            (0x1UL << RTC_CR_BYPSHAD_Pos)             /*!< 0x00000020 */
14829 #define RTC_CR_BYPSHAD                RTC_CR_BYPSHAD_Msk
14830 #define RTC_CR_REFCKON_Pos            (4U)
14831 #define RTC_CR_REFCKON_Msk            (0x1UL << RTC_CR_REFCKON_Pos)             /*!< 0x00000010 */
14832 #define RTC_CR_REFCKON                RTC_CR_REFCKON_Msk
14833 #define RTC_CR_TSEDGE_Pos             (3U)
14834 #define RTC_CR_TSEDGE_Msk             (0x1UL << RTC_CR_TSEDGE_Pos)              /*!< 0x00000008 */
14835 #define RTC_CR_TSEDGE                 RTC_CR_TSEDGE_Msk
14836 #define RTC_CR_WUCKSEL_Pos            (0U)
14837 #define RTC_CR_WUCKSEL_Msk            (0x7UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000007 */
14838 #define RTC_CR_WUCKSEL                RTC_CR_WUCKSEL_Msk
14839 #define RTC_CR_WUCKSEL_0              (0x1UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000001 */
14840 #define RTC_CR_WUCKSEL_1              (0x2UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000002 */
14841 #define RTC_CR_WUCKSEL_2              (0x4UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000004 */
14842 
14843 /* Legacy defines */
14844 #define RTC_CR_BCK                     RTC_CR_BKP
14845 
14846 /********************  Bits definition for RTC_ISR register  ******************/
14847 #define RTC_ISR_RECALPF_Pos           (16U)
14848 #define RTC_ISR_RECALPF_Msk           (0x1UL << RTC_ISR_RECALPF_Pos)            /*!< 0x00010000 */
14849 #define RTC_ISR_RECALPF               RTC_ISR_RECALPF_Msk
14850 #define RTC_ISR_TAMP1F_Pos            (13U)
14851 #define RTC_ISR_TAMP1F_Msk            (0x1UL << RTC_ISR_TAMP1F_Pos)             /*!< 0x00002000 */
14852 #define RTC_ISR_TAMP1F                RTC_ISR_TAMP1F_Msk
14853 #define RTC_ISR_TAMP2F_Pos            (14U)
14854 #define RTC_ISR_TAMP2F_Msk            (0x1UL << RTC_ISR_TAMP2F_Pos)             /*!< 0x00004000 */
14855 #define RTC_ISR_TAMP2F                RTC_ISR_TAMP2F_Msk
14856 #define RTC_ISR_TSOVF_Pos             (12U)
14857 #define RTC_ISR_TSOVF_Msk             (0x1UL << RTC_ISR_TSOVF_Pos)              /*!< 0x00001000 */
14858 #define RTC_ISR_TSOVF                 RTC_ISR_TSOVF_Msk
14859 #define RTC_ISR_TSF_Pos               (11U)
14860 #define RTC_ISR_TSF_Msk               (0x1UL << RTC_ISR_TSF_Pos)                /*!< 0x00000800 */
14861 #define RTC_ISR_TSF                   RTC_ISR_TSF_Msk
14862 #define RTC_ISR_WUTF_Pos              (10U)
14863 #define RTC_ISR_WUTF_Msk              (0x1UL << RTC_ISR_WUTF_Pos)               /*!< 0x00000400 */
14864 #define RTC_ISR_WUTF                  RTC_ISR_WUTF_Msk
14865 #define RTC_ISR_ALRBF_Pos             (9U)
14866 #define RTC_ISR_ALRBF_Msk             (0x1UL << RTC_ISR_ALRBF_Pos)              /*!< 0x00000200 */
14867 #define RTC_ISR_ALRBF                 RTC_ISR_ALRBF_Msk
14868 #define RTC_ISR_ALRAF_Pos             (8U)
14869 #define RTC_ISR_ALRAF_Msk             (0x1UL << RTC_ISR_ALRAF_Pos)              /*!< 0x00000100 */
14870 #define RTC_ISR_ALRAF                 RTC_ISR_ALRAF_Msk
14871 #define RTC_ISR_INIT_Pos              (7U)
14872 #define RTC_ISR_INIT_Msk              (0x1UL << RTC_ISR_INIT_Pos)               /*!< 0x00000080 */
14873 #define RTC_ISR_INIT                  RTC_ISR_INIT_Msk
14874 #define RTC_ISR_INITF_Pos             (6U)
14875 #define RTC_ISR_INITF_Msk             (0x1UL << RTC_ISR_INITF_Pos)              /*!< 0x00000040 */
14876 #define RTC_ISR_INITF                 RTC_ISR_INITF_Msk
14877 #define RTC_ISR_RSF_Pos               (5U)
14878 #define RTC_ISR_RSF_Msk               (0x1UL << RTC_ISR_RSF_Pos)                /*!< 0x00000020 */
14879 #define RTC_ISR_RSF                   RTC_ISR_RSF_Msk
14880 #define RTC_ISR_INITS_Pos             (4U)
14881 #define RTC_ISR_INITS_Msk             (0x1UL << RTC_ISR_INITS_Pos)              /*!< 0x00000010 */
14882 #define RTC_ISR_INITS                 RTC_ISR_INITS_Msk
14883 #define RTC_ISR_SHPF_Pos              (3U)
14884 #define RTC_ISR_SHPF_Msk              (0x1UL << RTC_ISR_SHPF_Pos)               /*!< 0x00000008 */
14885 #define RTC_ISR_SHPF                  RTC_ISR_SHPF_Msk
14886 #define RTC_ISR_WUTWF_Pos             (2U)
14887 #define RTC_ISR_WUTWF_Msk             (0x1UL << RTC_ISR_WUTWF_Pos)              /*!< 0x00000004 */
14888 #define RTC_ISR_WUTWF                 RTC_ISR_WUTWF_Msk
14889 #define RTC_ISR_ALRBWF_Pos            (1U)
14890 #define RTC_ISR_ALRBWF_Msk            (0x1UL << RTC_ISR_ALRBWF_Pos)             /*!< 0x00000002 */
14891 #define RTC_ISR_ALRBWF                RTC_ISR_ALRBWF_Msk
14892 #define RTC_ISR_ALRAWF_Pos            (0U)
14893 #define RTC_ISR_ALRAWF_Msk            (0x1UL << RTC_ISR_ALRAWF_Pos)             /*!< 0x00000001 */
14894 #define RTC_ISR_ALRAWF                RTC_ISR_ALRAWF_Msk
14895 
14896 /********************  Bits definition for RTC_PRER register  *****************/
14897 #define RTC_PRER_PREDIV_A_Pos         (16U)
14898 #define RTC_PRER_PREDIV_A_Msk         (0x7FUL << RTC_PRER_PREDIV_A_Pos)         /*!< 0x007F0000 */
14899 #define RTC_PRER_PREDIV_A             RTC_PRER_PREDIV_A_Msk
14900 #define RTC_PRER_PREDIV_S_Pos         (0U)
14901 #define RTC_PRER_PREDIV_S_Msk         (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)       /*!< 0x00007FFF */
14902 #define RTC_PRER_PREDIV_S             RTC_PRER_PREDIV_S_Msk
14903 
14904 /********************  Bits definition for RTC_WUTR register  *****************/
14905 #define RTC_WUTR_WUT_Pos              (0U)
14906 #define RTC_WUTR_WUT_Msk              (0xFFFFUL << RTC_WUTR_WUT_Pos)            /*!< 0x0000FFFF */
14907 #define RTC_WUTR_WUT                  RTC_WUTR_WUT_Msk
14908 
14909 /********************  Bits definition for RTC_CALIBR register  ***************/
14910 #define RTC_CALIBR_DCS_Pos            (7U)
14911 #define RTC_CALIBR_DCS_Msk            (0x1UL << RTC_CALIBR_DCS_Pos)             /*!< 0x00000080 */
14912 #define RTC_CALIBR_DCS                RTC_CALIBR_DCS_Msk
14913 #define RTC_CALIBR_DC_Pos             (0U)
14914 #define RTC_CALIBR_DC_Msk             (0x1FUL << RTC_CALIBR_DC_Pos)             /*!< 0x0000001F */
14915 #define RTC_CALIBR_DC                 RTC_CALIBR_DC_Msk
14916 
14917 /********************  Bits definition for RTC_ALRMAR register  ***************/
14918 #define RTC_ALRMAR_MSK4_Pos           (31U)
14919 #define RTC_ALRMAR_MSK4_Msk           (0x1UL << RTC_ALRMAR_MSK4_Pos)            /*!< 0x80000000 */
14920 #define RTC_ALRMAR_MSK4               RTC_ALRMAR_MSK4_Msk
14921 #define RTC_ALRMAR_WDSEL_Pos          (30U)
14922 #define RTC_ALRMAR_WDSEL_Msk          (0x1UL << RTC_ALRMAR_WDSEL_Pos)           /*!< 0x40000000 */
14923 #define RTC_ALRMAR_WDSEL              RTC_ALRMAR_WDSEL_Msk
14924 #define RTC_ALRMAR_DT_Pos             (28U)
14925 #define RTC_ALRMAR_DT_Msk             (0x3UL << RTC_ALRMAR_DT_Pos)              /*!< 0x30000000 */
14926 #define RTC_ALRMAR_DT                 RTC_ALRMAR_DT_Msk
14927 #define RTC_ALRMAR_DT_0               (0x1UL << RTC_ALRMAR_DT_Pos)              /*!< 0x10000000 */
14928 #define RTC_ALRMAR_DT_1               (0x2UL << RTC_ALRMAR_DT_Pos)              /*!< 0x20000000 */
14929 #define RTC_ALRMAR_DU_Pos             (24U)
14930 #define RTC_ALRMAR_DU_Msk             (0xFUL << RTC_ALRMAR_DU_Pos)              /*!< 0x0F000000 */
14931 #define RTC_ALRMAR_DU                 RTC_ALRMAR_DU_Msk
14932 #define RTC_ALRMAR_DU_0               (0x1UL << RTC_ALRMAR_DU_Pos)              /*!< 0x01000000 */
14933 #define RTC_ALRMAR_DU_1               (0x2UL << RTC_ALRMAR_DU_Pos)              /*!< 0x02000000 */
14934 #define RTC_ALRMAR_DU_2               (0x4UL << RTC_ALRMAR_DU_Pos)              /*!< 0x04000000 */
14935 #define RTC_ALRMAR_DU_3               (0x8UL << RTC_ALRMAR_DU_Pos)              /*!< 0x08000000 */
14936 #define RTC_ALRMAR_MSK3_Pos           (23U)
14937 #define RTC_ALRMAR_MSK3_Msk           (0x1UL << RTC_ALRMAR_MSK3_Pos)            /*!< 0x00800000 */
14938 #define RTC_ALRMAR_MSK3               RTC_ALRMAR_MSK3_Msk
14939 #define RTC_ALRMAR_PM_Pos             (22U)
14940 #define RTC_ALRMAR_PM_Msk             (0x1UL << RTC_ALRMAR_PM_Pos)              /*!< 0x00400000 */
14941 #define RTC_ALRMAR_PM                 RTC_ALRMAR_PM_Msk
14942 #define RTC_ALRMAR_HT_Pos             (20U)
14943 #define RTC_ALRMAR_HT_Msk             (0x3UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00300000 */
14944 #define RTC_ALRMAR_HT                 RTC_ALRMAR_HT_Msk
14945 #define RTC_ALRMAR_HT_0               (0x1UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00100000 */
14946 #define RTC_ALRMAR_HT_1               (0x2UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00200000 */
14947 #define RTC_ALRMAR_HU_Pos             (16U)
14948 #define RTC_ALRMAR_HU_Msk             (0xFUL << RTC_ALRMAR_HU_Pos)              /*!< 0x000F0000 */
14949 #define RTC_ALRMAR_HU                 RTC_ALRMAR_HU_Msk
14950 #define RTC_ALRMAR_HU_0               (0x1UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00010000 */
14951 #define RTC_ALRMAR_HU_1               (0x2UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00020000 */
14952 #define RTC_ALRMAR_HU_2               (0x4UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00040000 */
14953 #define RTC_ALRMAR_HU_3               (0x8UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00080000 */
14954 #define RTC_ALRMAR_MSK2_Pos           (15U)
14955 #define RTC_ALRMAR_MSK2_Msk           (0x1UL << RTC_ALRMAR_MSK2_Pos)            /*!< 0x00008000 */
14956 #define RTC_ALRMAR_MSK2               RTC_ALRMAR_MSK2_Msk
14957 #define RTC_ALRMAR_MNT_Pos            (12U)
14958 #define RTC_ALRMAR_MNT_Msk            (0x7UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00007000 */
14959 #define RTC_ALRMAR_MNT                RTC_ALRMAR_MNT_Msk
14960 #define RTC_ALRMAR_MNT_0              (0x1UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00001000 */
14961 #define RTC_ALRMAR_MNT_1              (0x2UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00002000 */
14962 #define RTC_ALRMAR_MNT_2              (0x4UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00004000 */
14963 #define RTC_ALRMAR_MNU_Pos            (8U)
14964 #define RTC_ALRMAR_MNU_Msk            (0xFUL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000F00 */
14965 #define RTC_ALRMAR_MNU                RTC_ALRMAR_MNU_Msk
14966 #define RTC_ALRMAR_MNU_0              (0x1UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000100 */
14967 #define RTC_ALRMAR_MNU_1              (0x2UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000200 */
14968 #define RTC_ALRMAR_MNU_2              (0x4UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000400 */
14969 #define RTC_ALRMAR_MNU_3              (0x8UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000800 */
14970 #define RTC_ALRMAR_MSK1_Pos           (7U)
14971 #define RTC_ALRMAR_MSK1_Msk           (0x1UL << RTC_ALRMAR_MSK1_Pos)            /*!< 0x00000080 */
14972 #define RTC_ALRMAR_MSK1               RTC_ALRMAR_MSK1_Msk
14973 #define RTC_ALRMAR_ST_Pos             (4U)
14974 #define RTC_ALRMAR_ST_Msk             (0x7UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000070 */
14975 #define RTC_ALRMAR_ST                 RTC_ALRMAR_ST_Msk
14976 #define RTC_ALRMAR_ST_0               (0x1UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000010 */
14977 #define RTC_ALRMAR_ST_1               (0x2UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000020 */
14978 #define RTC_ALRMAR_ST_2               (0x4UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000040 */
14979 #define RTC_ALRMAR_SU_Pos             (0U)
14980 #define RTC_ALRMAR_SU_Msk             (0xFUL << RTC_ALRMAR_SU_Pos)              /*!< 0x0000000F */
14981 #define RTC_ALRMAR_SU                 RTC_ALRMAR_SU_Msk
14982 #define RTC_ALRMAR_SU_0               (0x1UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000001 */
14983 #define RTC_ALRMAR_SU_1               (0x2UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000002 */
14984 #define RTC_ALRMAR_SU_2               (0x4UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000004 */
14985 #define RTC_ALRMAR_SU_3               (0x8UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000008 */
14986 
14987 /********************  Bits definition for RTC_ALRMBR register  ***************/
14988 #define RTC_ALRMBR_MSK4_Pos           (31U)
14989 #define RTC_ALRMBR_MSK4_Msk           (0x1UL << RTC_ALRMBR_MSK4_Pos)            /*!< 0x80000000 */
14990 #define RTC_ALRMBR_MSK4               RTC_ALRMBR_MSK4_Msk
14991 #define RTC_ALRMBR_WDSEL_Pos          (30U)
14992 #define RTC_ALRMBR_WDSEL_Msk          (0x1UL << RTC_ALRMBR_WDSEL_Pos)           /*!< 0x40000000 */
14993 #define RTC_ALRMBR_WDSEL              RTC_ALRMBR_WDSEL_Msk
14994 #define RTC_ALRMBR_DT_Pos             (28U)
14995 #define RTC_ALRMBR_DT_Msk             (0x3UL << RTC_ALRMBR_DT_Pos)              /*!< 0x30000000 */
14996 #define RTC_ALRMBR_DT                 RTC_ALRMBR_DT_Msk
14997 #define RTC_ALRMBR_DT_0               (0x1UL << RTC_ALRMBR_DT_Pos)              /*!< 0x10000000 */
14998 #define RTC_ALRMBR_DT_1               (0x2UL << RTC_ALRMBR_DT_Pos)              /*!< 0x20000000 */
14999 #define RTC_ALRMBR_DU_Pos             (24U)
15000 #define RTC_ALRMBR_DU_Msk             (0xFUL << RTC_ALRMBR_DU_Pos)              /*!< 0x0F000000 */
15001 #define RTC_ALRMBR_DU                 RTC_ALRMBR_DU_Msk
15002 #define RTC_ALRMBR_DU_0               (0x1UL << RTC_ALRMBR_DU_Pos)              /*!< 0x01000000 */
15003 #define RTC_ALRMBR_DU_1               (0x2UL << RTC_ALRMBR_DU_Pos)              /*!< 0x02000000 */
15004 #define RTC_ALRMBR_DU_2               (0x4UL << RTC_ALRMBR_DU_Pos)              /*!< 0x04000000 */
15005 #define RTC_ALRMBR_DU_3               (0x8UL << RTC_ALRMBR_DU_Pos)              /*!< 0x08000000 */
15006 #define RTC_ALRMBR_MSK3_Pos           (23U)
15007 #define RTC_ALRMBR_MSK3_Msk           (0x1UL << RTC_ALRMBR_MSK3_Pos)            /*!< 0x00800000 */
15008 #define RTC_ALRMBR_MSK3               RTC_ALRMBR_MSK3_Msk
15009 #define RTC_ALRMBR_PM_Pos             (22U)
15010 #define RTC_ALRMBR_PM_Msk             (0x1UL << RTC_ALRMBR_PM_Pos)              /*!< 0x00400000 */
15011 #define RTC_ALRMBR_PM                 RTC_ALRMBR_PM_Msk
15012 #define RTC_ALRMBR_HT_Pos             (20U)
15013 #define RTC_ALRMBR_HT_Msk             (0x3UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00300000 */
15014 #define RTC_ALRMBR_HT                 RTC_ALRMBR_HT_Msk
15015 #define RTC_ALRMBR_HT_0               (0x1UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00100000 */
15016 #define RTC_ALRMBR_HT_1               (0x2UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00200000 */
15017 #define RTC_ALRMBR_HU_Pos             (16U)
15018 #define RTC_ALRMBR_HU_Msk             (0xFUL << RTC_ALRMBR_HU_Pos)              /*!< 0x000F0000 */
15019 #define RTC_ALRMBR_HU                 RTC_ALRMBR_HU_Msk
15020 #define RTC_ALRMBR_HU_0               (0x1UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00010000 */
15021 #define RTC_ALRMBR_HU_1               (0x2UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00020000 */
15022 #define RTC_ALRMBR_HU_2               (0x4UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00040000 */
15023 #define RTC_ALRMBR_HU_3               (0x8UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00080000 */
15024 #define RTC_ALRMBR_MSK2_Pos           (15U)
15025 #define RTC_ALRMBR_MSK2_Msk           (0x1UL << RTC_ALRMBR_MSK2_Pos)            /*!< 0x00008000 */
15026 #define RTC_ALRMBR_MSK2               RTC_ALRMBR_MSK2_Msk
15027 #define RTC_ALRMBR_MNT_Pos            (12U)
15028 #define RTC_ALRMBR_MNT_Msk            (0x7UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00007000 */
15029 #define RTC_ALRMBR_MNT                RTC_ALRMBR_MNT_Msk
15030 #define RTC_ALRMBR_MNT_0              (0x1UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00001000 */
15031 #define RTC_ALRMBR_MNT_1              (0x2UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00002000 */
15032 #define RTC_ALRMBR_MNT_2              (0x4UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00004000 */
15033 #define RTC_ALRMBR_MNU_Pos            (8U)
15034 #define RTC_ALRMBR_MNU_Msk            (0xFUL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000F00 */
15035 #define RTC_ALRMBR_MNU                RTC_ALRMBR_MNU_Msk
15036 #define RTC_ALRMBR_MNU_0              (0x1UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000100 */
15037 #define RTC_ALRMBR_MNU_1              (0x2UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000200 */
15038 #define RTC_ALRMBR_MNU_2              (0x4UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000400 */
15039 #define RTC_ALRMBR_MNU_3              (0x8UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000800 */
15040 #define RTC_ALRMBR_MSK1_Pos           (7U)
15041 #define RTC_ALRMBR_MSK1_Msk           (0x1UL << RTC_ALRMBR_MSK1_Pos)            /*!< 0x00000080 */
15042 #define RTC_ALRMBR_MSK1               RTC_ALRMBR_MSK1_Msk
15043 #define RTC_ALRMBR_ST_Pos             (4U)
15044 #define RTC_ALRMBR_ST_Msk             (0x7UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000070 */
15045 #define RTC_ALRMBR_ST                 RTC_ALRMBR_ST_Msk
15046 #define RTC_ALRMBR_ST_0               (0x1UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000010 */
15047 #define RTC_ALRMBR_ST_1               (0x2UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000020 */
15048 #define RTC_ALRMBR_ST_2               (0x4UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000040 */
15049 #define RTC_ALRMBR_SU_Pos             (0U)
15050 #define RTC_ALRMBR_SU_Msk             (0xFUL << RTC_ALRMBR_SU_Pos)              /*!< 0x0000000F */
15051 #define RTC_ALRMBR_SU                 RTC_ALRMBR_SU_Msk
15052 #define RTC_ALRMBR_SU_0               (0x1UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000001 */
15053 #define RTC_ALRMBR_SU_1               (0x2UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000002 */
15054 #define RTC_ALRMBR_SU_2               (0x4UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000004 */
15055 #define RTC_ALRMBR_SU_3               (0x8UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000008 */
15056 
15057 /********************  Bits definition for RTC_WPR register  ******************/
15058 #define RTC_WPR_KEY_Pos               (0U)
15059 #define RTC_WPR_KEY_Msk               (0xFFUL << RTC_WPR_KEY_Pos)               /*!< 0x000000FF */
15060 #define RTC_WPR_KEY                   RTC_WPR_KEY_Msk
15061 
15062 /********************  Bits definition for RTC_SSR register  ******************/
15063 #define RTC_SSR_SS_Pos                (0U)
15064 #define RTC_SSR_SS_Msk                (0xFFFFUL << RTC_SSR_SS_Pos)              /*!< 0x0000FFFF */
15065 #define RTC_SSR_SS                    RTC_SSR_SS_Msk
15066 
15067 /********************  Bits definition for RTC_SHIFTR register  ***************/
15068 #define RTC_SHIFTR_SUBFS_Pos          (0U)
15069 #define RTC_SHIFTR_SUBFS_Msk          (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)        /*!< 0x00007FFF */
15070 #define RTC_SHIFTR_SUBFS              RTC_SHIFTR_SUBFS_Msk
15071 #define RTC_SHIFTR_ADD1S_Pos          (31U)
15072 #define RTC_SHIFTR_ADD1S_Msk          (0x1UL << RTC_SHIFTR_ADD1S_Pos)           /*!< 0x80000000 */
15073 #define RTC_SHIFTR_ADD1S              RTC_SHIFTR_ADD1S_Msk
15074 
15075 /********************  Bits definition for RTC_TSTR register  *****************/
15076 #define RTC_TSTR_PM_Pos               (22U)
15077 #define RTC_TSTR_PM_Msk               (0x1UL << RTC_TSTR_PM_Pos)                /*!< 0x00400000 */
15078 #define RTC_TSTR_PM                   RTC_TSTR_PM_Msk
15079 #define RTC_TSTR_HT_Pos               (20U)
15080 #define RTC_TSTR_HT_Msk               (0x3UL << RTC_TSTR_HT_Pos)                /*!< 0x00300000 */
15081 #define RTC_TSTR_HT                   RTC_TSTR_HT_Msk
15082 #define RTC_TSTR_HT_0                 (0x1UL << RTC_TSTR_HT_Pos)                /*!< 0x00100000 */
15083 #define RTC_TSTR_HT_1                 (0x2UL << RTC_TSTR_HT_Pos)                /*!< 0x00200000 */
15084 #define RTC_TSTR_HU_Pos               (16U)
15085 #define RTC_TSTR_HU_Msk               (0xFUL << RTC_TSTR_HU_Pos)                /*!< 0x000F0000 */
15086 #define RTC_TSTR_HU                   RTC_TSTR_HU_Msk
15087 #define RTC_TSTR_HU_0                 (0x1UL << RTC_TSTR_HU_Pos)                /*!< 0x00010000 */
15088 #define RTC_TSTR_HU_1                 (0x2UL << RTC_TSTR_HU_Pos)                /*!< 0x00020000 */
15089 #define RTC_TSTR_HU_2                 (0x4UL << RTC_TSTR_HU_Pos)                /*!< 0x00040000 */
15090 #define RTC_TSTR_HU_3                 (0x8UL << RTC_TSTR_HU_Pos)                /*!< 0x00080000 */
15091 #define RTC_TSTR_MNT_Pos              (12U)
15092 #define RTC_TSTR_MNT_Msk              (0x7UL << RTC_TSTR_MNT_Pos)               /*!< 0x00007000 */
15093 #define RTC_TSTR_MNT                  RTC_TSTR_MNT_Msk
15094 #define RTC_TSTR_MNT_0                (0x1UL << RTC_TSTR_MNT_Pos)               /*!< 0x00001000 */
15095 #define RTC_TSTR_MNT_1                (0x2UL << RTC_TSTR_MNT_Pos)               /*!< 0x00002000 */
15096 #define RTC_TSTR_MNT_2                (0x4UL << RTC_TSTR_MNT_Pos)               /*!< 0x00004000 */
15097 #define RTC_TSTR_MNU_Pos              (8U)
15098 #define RTC_TSTR_MNU_Msk              (0xFUL << RTC_TSTR_MNU_Pos)               /*!< 0x00000F00 */
15099 #define RTC_TSTR_MNU                  RTC_TSTR_MNU_Msk
15100 #define RTC_TSTR_MNU_0                (0x1UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000100 */
15101 #define RTC_TSTR_MNU_1                (0x2UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000200 */
15102 #define RTC_TSTR_MNU_2                (0x4UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000400 */
15103 #define RTC_TSTR_MNU_3                (0x8UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000800 */
15104 #define RTC_TSTR_ST_Pos               (4U)
15105 #define RTC_TSTR_ST_Msk               (0x7UL << RTC_TSTR_ST_Pos)                /*!< 0x00000070 */
15106 #define RTC_TSTR_ST                   RTC_TSTR_ST_Msk
15107 #define RTC_TSTR_ST_0                 (0x1UL << RTC_TSTR_ST_Pos)                /*!< 0x00000010 */
15108 #define RTC_TSTR_ST_1                 (0x2UL << RTC_TSTR_ST_Pos)                /*!< 0x00000020 */
15109 #define RTC_TSTR_ST_2                 (0x4UL << RTC_TSTR_ST_Pos)                /*!< 0x00000040 */
15110 #define RTC_TSTR_SU_Pos               (0U)
15111 #define RTC_TSTR_SU_Msk               (0xFUL << RTC_TSTR_SU_Pos)                /*!< 0x0000000F */
15112 #define RTC_TSTR_SU                   RTC_TSTR_SU_Msk
15113 #define RTC_TSTR_SU_0                 (0x1UL << RTC_TSTR_SU_Pos)                /*!< 0x00000001 */
15114 #define RTC_TSTR_SU_1                 (0x2UL << RTC_TSTR_SU_Pos)                /*!< 0x00000002 */
15115 #define RTC_TSTR_SU_2                 (0x4UL << RTC_TSTR_SU_Pos)                /*!< 0x00000004 */
15116 #define RTC_TSTR_SU_3                 (0x8UL << RTC_TSTR_SU_Pos)                /*!< 0x00000008 */
15117 
15118 /********************  Bits definition for RTC_TSDR register  *****************/
15119 #define RTC_TSDR_WDU_Pos              (13U)
15120 #define RTC_TSDR_WDU_Msk              (0x7UL << RTC_TSDR_WDU_Pos)               /*!< 0x0000E000 */
15121 #define RTC_TSDR_WDU                  RTC_TSDR_WDU_Msk
15122 #define RTC_TSDR_WDU_0                (0x1UL << RTC_TSDR_WDU_Pos)               /*!< 0x00002000 */
15123 #define RTC_TSDR_WDU_1                (0x2UL << RTC_TSDR_WDU_Pos)               /*!< 0x00004000 */
15124 #define RTC_TSDR_WDU_2                (0x4UL << RTC_TSDR_WDU_Pos)               /*!< 0x00008000 */
15125 #define RTC_TSDR_MT_Pos               (12U)
15126 #define RTC_TSDR_MT_Msk               (0x1UL << RTC_TSDR_MT_Pos)                /*!< 0x00001000 */
15127 #define RTC_TSDR_MT                   RTC_TSDR_MT_Msk
15128 #define RTC_TSDR_MU_Pos               (8U)
15129 #define RTC_TSDR_MU_Msk               (0xFUL << RTC_TSDR_MU_Pos)                /*!< 0x00000F00 */
15130 #define RTC_TSDR_MU                   RTC_TSDR_MU_Msk
15131 #define RTC_TSDR_MU_0                 (0x1UL << RTC_TSDR_MU_Pos)                /*!< 0x00000100 */
15132 #define RTC_TSDR_MU_1                 (0x2UL << RTC_TSDR_MU_Pos)                /*!< 0x00000200 */
15133 #define RTC_TSDR_MU_2                 (0x4UL << RTC_TSDR_MU_Pos)                /*!< 0x00000400 */
15134 #define RTC_TSDR_MU_3                 (0x8UL << RTC_TSDR_MU_Pos)                /*!< 0x00000800 */
15135 #define RTC_TSDR_DT_Pos               (4U)
15136 #define RTC_TSDR_DT_Msk               (0x3UL << RTC_TSDR_DT_Pos)                /*!< 0x00000030 */
15137 #define RTC_TSDR_DT                   RTC_TSDR_DT_Msk
15138 #define RTC_TSDR_DT_0                 (0x1UL << RTC_TSDR_DT_Pos)                /*!< 0x00000010 */
15139 #define RTC_TSDR_DT_1                 (0x2UL << RTC_TSDR_DT_Pos)                /*!< 0x00000020 */
15140 #define RTC_TSDR_DU_Pos               (0U)
15141 #define RTC_TSDR_DU_Msk               (0xFUL << RTC_TSDR_DU_Pos)                /*!< 0x0000000F */
15142 #define RTC_TSDR_DU                   RTC_TSDR_DU_Msk
15143 #define RTC_TSDR_DU_0                 (0x1UL << RTC_TSDR_DU_Pos)                /*!< 0x00000001 */
15144 #define RTC_TSDR_DU_1                 (0x2UL << RTC_TSDR_DU_Pos)                /*!< 0x00000002 */
15145 #define RTC_TSDR_DU_2                 (0x4UL << RTC_TSDR_DU_Pos)                /*!< 0x00000004 */
15146 #define RTC_TSDR_DU_3                 (0x8UL << RTC_TSDR_DU_Pos)                /*!< 0x00000008 */
15147 
15148 /********************  Bits definition for RTC_TSSSR register  ****************/
15149 #define RTC_TSSSR_SS_Pos              (0U)
15150 #define RTC_TSSSR_SS_Msk              (0xFFFFUL << RTC_TSSSR_SS_Pos)            /*!< 0x0000FFFF */
15151 #define RTC_TSSSR_SS                  RTC_TSSSR_SS_Msk
15152 
15153 /********************  Bits definition for RTC_CAL register  *****************/
15154 #define RTC_CALR_CALP_Pos             (15U)
15155 #define RTC_CALR_CALP_Msk             (0x1UL << RTC_CALR_CALP_Pos)              /*!< 0x00008000 */
15156 #define RTC_CALR_CALP                 RTC_CALR_CALP_Msk
15157 #define RTC_CALR_CALW8_Pos            (14U)
15158 #define RTC_CALR_CALW8_Msk            (0x1UL << RTC_CALR_CALW8_Pos)             /*!< 0x00004000 */
15159 #define RTC_CALR_CALW8                RTC_CALR_CALW8_Msk
15160 #define RTC_CALR_CALW16_Pos           (13U)
15161 #define RTC_CALR_CALW16_Msk           (0x1UL << RTC_CALR_CALW16_Pos)            /*!< 0x00002000 */
15162 #define RTC_CALR_CALW16               RTC_CALR_CALW16_Msk
15163 #define RTC_CALR_CALM_Pos             (0U)
15164 #define RTC_CALR_CALM_Msk             (0x1FFUL << RTC_CALR_CALM_Pos)            /*!< 0x000001FF */
15165 #define RTC_CALR_CALM                 RTC_CALR_CALM_Msk
15166 #define RTC_CALR_CALM_0               (0x001UL << RTC_CALR_CALM_Pos)            /*!< 0x00000001 */
15167 #define RTC_CALR_CALM_1               (0x002UL << RTC_CALR_CALM_Pos)            /*!< 0x00000002 */
15168 #define RTC_CALR_CALM_2               (0x004UL << RTC_CALR_CALM_Pos)            /*!< 0x00000004 */
15169 #define RTC_CALR_CALM_3               (0x008UL << RTC_CALR_CALM_Pos)            /*!< 0x00000008 */
15170 #define RTC_CALR_CALM_4               (0x010UL << RTC_CALR_CALM_Pos)            /*!< 0x00000010 */
15171 #define RTC_CALR_CALM_5               (0x020UL << RTC_CALR_CALM_Pos)            /*!< 0x00000020 */
15172 #define RTC_CALR_CALM_6               (0x040UL << RTC_CALR_CALM_Pos)            /*!< 0x00000040 */
15173 #define RTC_CALR_CALM_7               (0x080UL << RTC_CALR_CALM_Pos)            /*!< 0x00000080 */
15174 #define RTC_CALR_CALM_8               (0x100UL << RTC_CALR_CALM_Pos)            /*!< 0x00000100 */
15175 
15176 /********************  Bits definition for RTC_TAFCR register  ****************/
15177 #define RTC_TAFCR_ALARMOUTTYPE_Pos    (18U)
15178 #define RTC_TAFCR_ALARMOUTTYPE_Msk    (0x1UL << RTC_TAFCR_ALARMOUTTYPE_Pos)     /*!< 0x00040000 */
15179 #define RTC_TAFCR_ALARMOUTTYPE        RTC_TAFCR_ALARMOUTTYPE_Msk
15180 #define RTC_TAFCR_TSINSEL_Pos         (17U)
15181 #define RTC_TAFCR_TSINSEL_Msk         (0x1UL << RTC_TAFCR_TSINSEL_Pos)          /*!< 0x00020000 */
15182 #define RTC_TAFCR_TSINSEL             RTC_TAFCR_TSINSEL_Msk
15183 #define RTC_TAFCR_TAMP1INSEL_Pos      (16U)
15184 #define RTC_TAFCR_TAMP1INSEL_Msk      (0x1UL << RTC_TAFCR_TAMP1INSEL_Pos)        /*!< 0x00010000 */
15185 #define RTC_TAFCR_TAMP1INSEL          RTC_TAFCR_TAMP1INSEL_Msk
15186 #define RTC_TAFCR_TAMPPUDIS_Pos       (15U)
15187 #define RTC_TAFCR_TAMPPUDIS_Msk       (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos)        /*!< 0x00008000 */
15188 #define RTC_TAFCR_TAMPPUDIS           RTC_TAFCR_TAMPPUDIS_Msk
15189 #define RTC_TAFCR_TAMPPRCH_Pos        (13U)
15190 #define RTC_TAFCR_TAMPPRCH_Msk        (0x3UL << RTC_TAFCR_TAMPPRCH_Pos)         /*!< 0x00006000 */
15191 #define RTC_TAFCR_TAMPPRCH            RTC_TAFCR_TAMPPRCH_Msk
15192 #define RTC_TAFCR_TAMPPRCH_0          (0x1UL << RTC_TAFCR_TAMPPRCH_Pos)         /*!< 0x00002000 */
15193 #define RTC_TAFCR_TAMPPRCH_1          (0x2UL << RTC_TAFCR_TAMPPRCH_Pos)         /*!< 0x00004000 */
15194 #define RTC_TAFCR_TAMPFLT_Pos         (11U)
15195 #define RTC_TAFCR_TAMPFLT_Msk         (0x3UL << RTC_TAFCR_TAMPFLT_Pos)          /*!< 0x00001800 */
15196 #define RTC_TAFCR_TAMPFLT             RTC_TAFCR_TAMPFLT_Msk
15197 #define RTC_TAFCR_TAMPFLT_0           (0x1UL << RTC_TAFCR_TAMPFLT_Pos)          /*!< 0x00000800 */
15198 #define RTC_TAFCR_TAMPFLT_1           (0x2UL << RTC_TAFCR_TAMPFLT_Pos)          /*!< 0x00001000 */
15199 #define RTC_TAFCR_TAMPFREQ_Pos        (8U)
15200 #define RTC_TAFCR_TAMPFREQ_Msk        (0x7UL << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000700 */
15201 #define RTC_TAFCR_TAMPFREQ            RTC_TAFCR_TAMPFREQ_Msk
15202 #define RTC_TAFCR_TAMPFREQ_0          (0x1UL << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000100 */
15203 #define RTC_TAFCR_TAMPFREQ_1          (0x2UL << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000200 */
15204 #define RTC_TAFCR_TAMPFREQ_2          (0x4UL << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000400 */
15205 #define RTC_TAFCR_TAMPTS_Pos          (7U)
15206 #define RTC_TAFCR_TAMPTS_Msk          (0x1UL << RTC_TAFCR_TAMPTS_Pos)           /*!< 0x00000080 */
15207 #define RTC_TAFCR_TAMPTS              RTC_TAFCR_TAMPTS_Msk
15208 #define RTC_TAFCR_TAMP2TRG_Pos        (4U)
15209 #define RTC_TAFCR_TAMP2TRG_Msk        (0x1UL << RTC_TAFCR_TAMP2TRG_Pos)         /*!< 0x00000010 */
15210 #define RTC_TAFCR_TAMP2TRG            RTC_TAFCR_TAMP2TRG_Msk
15211 #define RTC_TAFCR_TAMP2E_Pos          (3U)
15212 #define RTC_TAFCR_TAMP2E_Msk          (0x1UL << RTC_TAFCR_TAMP2E_Pos)           /*!< 0x00000008 */
15213 #define RTC_TAFCR_TAMP2E              RTC_TAFCR_TAMP2E_Msk
15214 #define RTC_TAFCR_TAMPIE_Pos          (2U)
15215 #define RTC_TAFCR_TAMPIE_Msk          (0x1UL << RTC_TAFCR_TAMPIE_Pos)           /*!< 0x00000004 */
15216 #define RTC_TAFCR_TAMPIE              RTC_TAFCR_TAMPIE_Msk
15217 #define RTC_TAFCR_TAMP1TRG_Pos        (1U)
15218 #define RTC_TAFCR_TAMP1TRG_Msk        (0x1UL << RTC_TAFCR_TAMP1TRG_Pos)         /*!< 0x00000002 */
15219 #define RTC_TAFCR_TAMP1TRG            RTC_TAFCR_TAMP1TRG_Msk
15220 #define RTC_TAFCR_TAMP1E_Pos          (0U)
15221 #define RTC_TAFCR_TAMP1E_Msk          (0x1UL << RTC_TAFCR_TAMP1E_Pos)           /*!< 0x00000001 */
15222 #define RTC_TAFCR_TAMP1E              RTC_TAFCR_TAMP1E_Msk
15223 
15224 /* Legacy defines */
15225 #define RTC_TAFCR_TAMPINSEL           RTC_TAFCR_TAMP1INSEL
15226 
15227 /********************  Bits definition for RTC_ALRMASSR register  *************/
15228 #define RTC_ALRMASSR_MASKSS_Pos       (24U)
15229 #define RTC_ALRMASSR_MASKSS_Msk       (0xFUL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x0F000000 */
15230 #define RTC_ALRMASSR_MASKSS           RTC_ALRMASSR_MASKSS_Msk
15231 #define RTC_ALRMASSR_MASKSS_0         (0x1UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x01000000 */
15232 #define RTC_ALRMASSR_MASKSS_1         (0x2UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x02000000 */
15233 #define RTC_ALRMASSR_MASKSS_2         (0x4UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x04000000 */
15234 #define RTC_ALRMASSR_MASKSS_3         (0x8UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x08000000 */
15235 #define RTC_ALRMASSR_SS_Pos           (0U)
15236 #define RTC_ALRMASSR_SS_Msk           (0x7FFFUL << RTC_ALRMASSR_SS_Pos)         /*!< 0x00007FFF */
15237 #define RTC_ALRMASSR_SS               RTC_ALRMASSR_SS_Msk
15238 
15239 /********************  Bits definition for RTC_ALRMBSSR register  *************/
15240 #define RTC_ALRMBSSR_MASKSS_Pos       (24U)
15241 #define RTC_ALRMBSSR_MASKSS_Msk       (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x0F000000 */
15242 #define RTC_ALRMBSSR_MASKSS           RTC_ALRMBSSR_MASKSS_Msk
15243 #define RTC_ALRMBSSR_MASKSS_0         (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x01000000 */
15244 #define RTC_ALRMBSSR_MASKSS_1         (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x02000000 */
15245 #define RTC_ALRMBSSR_MASKSS_2         (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x04000000 */
15246 #define RTC_ALRMBSSR_MASKSS_3         (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x08000000 */
15247 #define RTC_ALRMBSSR_SS_Pos           (0U)
15248 #define RTC_ALRMBSSR_SS_Msk           (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)         /*!< 0x00007FFF */
15249 #define RTC_ALRMBSSR_SS               RTC_ALRMBSSR_SS_Msk
15250 
15251 /********************  Bits definition for RTC_BKP0R register  ****************/
15252 #define RTC_BKP0R_Pos                 (0U)
15253 #define RTC_BKP0R_Msk                 (0xFFFFFFFFUL << RTC_BKP0R_Pos)           /*!< 0xFFFFFFFF */
15254 #define RTC_BKP0R                     RTC_BKP0R_Msk
15255 
15256 /********************  Bits definition for RTC_BKP1R register  ****************/
15257 #define RTC_BKP1R_Pos                 (0U)
15258 #define RTC_BKP1R_Msk                 (0xFFFFFFFFUL << RTC_BKP1R_Pos)           /*!< 0xFFFFFFFF */
15259 #define RTC_BKP1R                     RTC_BKP1R_Msk
15260 
15261 /********************  Bits definition for RTC_BKP2R register  ****************/
15262 #define RTC_BKP2R_Pos                 (0U)
15263 #define RTC_BKP2R_Msk                 (0xFFFFFFFFUL << RTC_BKP2R_Pos)           /*!< 0xFFFFFFFF */
15264 #define RTC_BKP2R                     RTC_BKP2R_Msk
15265 
15266 /********************  Bits definition for RTC_BKP3R register  ****************/
15267 #define RTC_BKP3R_Pos                 (0U)
15268 #define RTC_BKP3R_Msk                 (0xFFFFFFFFUL << RTC_BKP3R_Pos)           /*!< 0xFFFFFFFF */
15269 #define RTC_BKP3R                     RTC_BKP3R_Msk
15270 
15271 /********************  Bits definition for RTC_BKP4R register  ****************/
15272 #define RTC_BKP4R_Pos                 (0U)
15273 #define RTC_BKP4R_Msk                 (0xFFFFFFFFUL << RTC_BKP4R_Pos)           /*!< 0xFFFFFFFF */
15274 #define RTC_BKP4R                     RTC_BKP4R_Msk
15275 
15276 /********************  Bits definition for RTC_BKP5R register  ****************/
15277 #define RTC_BKP5R_Pos                 (0U)
15278 #define RTC_BKP5R_Msk                 (0xFFFFFFFFUL << RTC_BKP5R_Pos)           /*!< 0xFFFFFFFF */
15279 #define RTC_BKP5R                     RTC_BKP5R_Msk
15280 
15281 /********************  Bits definition for RTC_BKP6R register  ****************/
15282 #define RTC_BKP6R_Pos                 (0U)
15283 #define RTC_BKP6R_Msk                 (0xFFFFFFFFUL << RTC_BKP6R_Pos)           /*!< 0xFFFFFFFF */
15284 #define RTC_BKP6R                     RTC_BKP6R_Msk
15285 
15286 /********************  Bits definition for RTC_BKP7R register  ****************/
15287 #define RTC_BKP7R_Pos                 (0U)
15288 #define RTC_BKP7R_Msk                 (0xFFFFFFFFUL << RTC_BKP7R_Pos)           /*!< 0xFFFFFFFF */
15289 #define RTC_BKP7R                     RTC_BKP7R_Msk
15290 
15291 /********************  Bits definition for RTC_BKP8R register  ****************/
15292 #define RTC_BKP8R_Pos                 (0U)
15293 #define RTC_BKP8R_Msk                 (0xFFFFFFFFUL << RTC_BKP8R_Pos)           /*!< 0xFFFFFFFF */
15294 #define RTC_BKP8R                     RTC_BKP8R_Msk
15295 
15296 /********************  Bits definition for RTC_BKP9R register  ****************/
15297 #define RTC_BKP9R_Pos                 (0U)
15298 #define RTC_BKP9R_Msk                 (0xFFFFFFFFUL << RTC_BKP9R_Pos)           /*!< 0xFFFFFFFF */
15299 #define RTC_BKP9R                     RTC_BKP9R_Msk
15300 
15301 /********************  Bits definition for RTC_BKP10R register  ***************/
15302 #define RTC_BKP10R_Pos                (0U)
15303 #define RTC_BKP10R_Msk                (0xFFFFFFFFUL << RTC_BKP10R_Pos)          /*!< 0xFFFFFFFF */
15304 #define RTC_BKP10R                    RTC_BKP10R_Msk
15305 
15306 /********************  Bits definition for RTC_BKP11R register  ***************/
15307 #define RTC_BKP11R_Pos                (0U)
15308 #define RTC_BKP11R_Msk                (0xFFFFFFFFUL << RTC_BKP11R_Pos)          /*!< 0xFFFFFFFF */
15309 #define RTC_BKP11R                    RTC_BKP11R_Msk
15310 
15311 /********************  Bits definition for RTC_BKP12R register  ***************/
15312 #define RTC_BKP12R_Pos                (0U)
15313 #define RTC_BKP12R_Msk                (0xFFFFFFFFUL << RTC_BKP12R_Pos)          /*!< 0xFFFFFFFF */
15314 #define RTC_BKP12R                    RTC_BKP12R_Msk
15315 
15316 /********************  Bits definition for RTC_BKP13R register  ***************/
15317 #define RTC_BKP13R_Pos                (0U)
15318 #define RTC_BKP13R_Msk                (0xFFFFFFFFUL << RTC_BKP13R_Pos)          /*!< 0xFFFFFFFF */
15319 #define RTC_BKP13R                    RTC_BKP13R_Msk
15320 
15321 /********************  Bits definition for RTC_BKP14R register  ***************/
15322 #define RTC_BKP14R_Pos                (0U)
15323 #define RTC_BKP14R_Msk                (0xFFFFFFFFUL << RTC_BKP14R_Pos)          /*!< 0xFFFFFFFF */
15324 #define RTC_BKP14R                    RTC_BKP14R_Msk
15325 
15326 /********************  Bits definition for RTC_BKP15R register  ***************/
15327 #define RTC_BKP15R_Pos                (0U)
15328 #define RTC_BKP15R_Msk                (0xFFFFFFFFUL << RTC_BKP15R_Pos)          /*!< 0xFFFFFFFF */
15329 #define RTC_BKP15R                    RTC_BKP15R_Msk
15330 
15331 /********************  Bits definition for RTC_BKP16R register  ***************/
15332 #define RTC_BKP16R_Pos                (0U)
15333 #define RTC_BKP16R_Msk                (0xFFFFFFFFUL << RTC_BKP16R_Pos)          /*!< 0xFFFFFFFF */
15334 #define RTC_BKP16R                    RTC_BKP16R_Msk
15335 
15336 /********************  Bits definition for RTC_BKP17R register  ***************/
15337 #define RTC_BKP17R_Pos                (0U)
15338 #define RTC_BKP17R_Msk                (0xFFFFFFFFUL << RTC_BKP17R_Pos)          /*!< 0xFFFFFFFF */
15339 #define RTC_BKP17R                    RTC_BKP17R_Msk
15340 
15341 /********************  Bits definition for RTC_BKP18R register  ***************/
15342 #define RTC_BKP18R_Pos                (0U)
15343 #define RTC_BKP18R_Msk                (0xFFFFFFFFUL << RTC_BKP18R_Pos)          /*!< 0xFFFFFFFF */
15344 #define RTC_BKP18R                    RTC_BKP18R_Msk
15345 
15346 /********************  Bits definition for RTC_BKP19R register  ***************/
15347 #define RTC_BKP19R_Pos                (0U)
15348 #define RTC_BKP19R_Msk                (0xFFFFFFFFUL << RTC_BKP19R_Pos)          /*!< 0xFFFFFFFF */
15349 #define RTC_BKP19R                    RTC_BKP19R_Msk
15350 
15351 /******************** Number of backup registers ******************************/
15352 #define RTC_BKP_NUMBER                       0x000000014U
15353 
15354 /******************************************************************************/
15355 /*                                                                            */
15356 /*                          Serial Audio Interface                            */
15357 /*                                                                            */
15358 /******************************************************************************/
15359 /********************  Bit definition for SAI_GCR register  *******************/
15360 #define SAI_GCR_SYNCIN_Pos         (0U)
15361 #define SAI_GCR_SYNCIN_Msk         (0x3UL << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000003 */
15362 #define SAI_GCR_SYNCIN             SAI_GCR_SYNCIN_Msk                          /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */
15363 #define SAI_GCR_SYNCIN_0           (0x1UL << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000001 */
15364 #define SAI_GCR_SYNCIN_1           (0x2UL << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000002 */
15365 
15366 #define SAI_GCR_SYNCOUT_Pos        (4U)
15367 #define SAI_GCR_SYNCOUT_Msk        (0x3UL << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000030 */
15368 #define SAI_GCR_SYNCOUT            SAI_GCR_SYNCOUT_Msk                         /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
15369 #define SAI_GCR_SYNCOUT_0          (0x1UL << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000010 */
15370 #define SAI_GCR_SYNCOUT_1          (0x2UL << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000020 */
15371 
15372 /*******************  Bit definition for SAI_xCR1 register  *******************/
15373 #define SAI_xCR1_MODE_Pos          (0U)
15374 #define SAI_xCR1_MODE_Msk          (0x3UL << SAI_xCR1_MODE_Pos)                 /*!< 0x00000003 */
15375 #define SAI_xCR1_MODE              SAI_xCR1_MODE_Msk                           /*!<MODE[1:0] bits (Audio Block Mode)           */
15376 #define SAI_xCR1_MODE_0            (0x1UL << SAI_xCR1_MODE_Pos)                 /*!< 0x00000001 */
15377 #define SAI_xCR1_MODE_1            (0x2UL << SAI_xCR1_MODE_Pos)                 /*!< 0x00000002 */
15378 
15379 #define SAI_xCR1_PRTCFG_Pos        (2U)
15380 #define SAI_xCR1_PRTCFG_Msk        (0x3UL << SAI_xCR1_PRTCFG_Pos)               /*!< 0x0000000C */
15381 #define SAI_xCR1_PRTCFG            SAI_xCR1_PRTCFG_Msk                         /*!<PRTCFG[1:0] bits (Protocol Configuration)   */
15382 #define SAI_xCR1_PRTCFG_0          (0x1UL << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000004 */
15383 #define SAI_xCR1_PRTCFG_1          (0x2UL << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000008 */
15384 
15385 #define SAI_xCR1_DS_Pos            (5U)
15386 #define SAI_xCR1_DS_Msk            (0x7UL << SAI_xCR1_DS_Pos)                   /*!< 0x000000E0 */
15387 #define SAI_xCR1_DS                SAI_xCR1_DS_Msk                             /*!<DS[1:0] bits (Data Size) */
15388 #define SAI_xCR1_DS_0              (0x1UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000020 */
15389 #define SAI_xCR1_DS_1              (0x2UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000040 */
15390 #define SAI_xCR1_DS_2              (0x4UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000080 */
15391 
15392 #define SAI_xCR1_LSBFIRST_Pos      (8U)
15393 #define SAI_xCR1_LSBFIRST_Msk      (0x1UL << SAI_xCR1_LSBFIRST_Pos)             /*!< 0x00000100 */
15394 #define SAI_xCR1_LSBFIRST          SAI_xCR1_LSBFIRST_Msk                       /*!<LSB First Configuration  */
15395 #define SAI_xCR1_CKSTR_Pos         (9U)
15396 #define SAI_xCR1_CKSTR_Msk         (0x1UL << SAI_xCR1_CKSTR_Pos)                /*!< 0x00000200 */
15397 #define SAI_xCR1_CKSTR             SAI_xCR1_CKSTR_Msk                          /*!<ClocK STRobing edge      */
15398 
15399 #define SAI_xCR1_SYNCEN_Pos        (10U)
15400 #define SAI_xCR1_SYNCEN_Msk        (0x3UL << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000C00 */
15401 #define SAI_xCR1_SYNCEN            SAI_xCR1_SYNCEN_Msk                         /*!<SYNCEN[1:0](SYNChronization ENable) */
15402 #define SAI_xCR1_SYNCEN_0          (0x1UL << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000400 */
15403 #define SAI_xCR1_SYNCEN_1          (0x2UL << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000800 */
15404 
15405 #define SAI_xCR1_MONO_Pos          (12U)
15406 #define SAI_xCR1_MONO_Msk          (0x1UL << SAI_xCR1_MONO_Pos)                 /*!< 0x00001000 */
15407 #define SAI_xCR1_MONO              SAI_xCR1_MONO_Msk                           /*!<Mono mode                  */
15408 #define SAI_xCR1_OUTDRIV_Pos       (13U)
15409 #define SAI_xCR1_OUTDRIV_Msk       (0x1UL << SAI_xCR1_OUTDRIV_Pos)              /*!< 0x00002000 */
15410 #define SAI_xCR1_OUTDRIV           SAI_xCR1_OUTDRIV_Msk                        /*!<Output Drive               */
15411 #define SAI_xCR1_SAIEN_Pos         (16U)
15412 #define SAI_xCR1_SAIEN_Msk         (0x1UL << SAI_xCR1_SAIEN_Pos)                /*!< 0x00010000 */
15413 #define SAI_xCR1_SAIEN             SAI_xCR1_SAIEN_Msk                          /*!<Audio Block enable         */
15414 #define SAI_xCR1_DMAEN_Pos         (17U)
15415 #define SAI_xCR1_DMAEN_Msk         (0x1UL << SAI_xCR1_DMAEN_Pos)                /*!< 0x00020000 */
15416 #define SAI_xCR1_DMAEN             SAI_xCR1_DMAEN_Msk                          /*!<DMA enable                 */
15417 #define SAI_xCR1_NODIV_Pos         (19U)
15418 #define SAI_xCR1_NODIV_Msk         (0x1UL << SAI_xCR1_NODIV_Pos)                /*!< 0x00080000 */
15419 #define SAI_xCR1_NODIV             SAI_xCR1_NODIV_Msk                          /*!<No Divider Configuration   */
15420 
15421 #define SAI_xCR1_MCKDIV_Pos        (20U)
15422 #define SAI_xCR1_MCKDIV_Msk        (0xFUL << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00F00000 */
15423 #define SAI_xCR1_MCKDIV            SAI_xCR1_MCKDIV_Msk                         /*!<MCKDIV[3:0] (Master ClocK Divider)  */
15424 #define SAI_xCR1_MCKDIV_0          (0x1UL << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00100000 */
15425 #define SAI_xCR1_MCKDIV_1          (0x2UL << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00200000 */
15426 #define SAI_xCR1_MCKDIV_2          (0x4UL << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00400000 */
15427 #define SAI_xCR1_MCKDIV_3          (0x8UL << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00800000 */
15428 
15429 /*******************  Bit definition for SAI_xCR2 register  *******************/
15430 #define SAI_xCR2_FTH_Pos           (0U)
15431 #define SAI_xCR2_FTH_Msk           (0x7UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000007 */
15432 #define SAI_xCR2_FTH               SAI_xCR2_FTH_Msk                            /*!<FTH[2:0](Fifo THreshold)  */
15433 #define SAI_xCR2_FTH_0             (0x1UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000001 */
15434 #define SAI_xCR2_FTH_1             (0x2UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000002 */
15435 #define SAI_xCR2_FTH_2             (0x4UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000004 */
15436 
15437 #define SAI_xCR2_FFLUSH_Pos        (3U)
15438 #define SAI_xCR2_FFLUSH_Msk        (0x1UL << SAI_xCR2_FFLUSH_Pos)               /*!< 0x00000008 */
15439 #define SAI_xCR2_FFLUSH            SAI_xCR2_FFLUSH_Msk                         /*!<Fifo FLUSH                       */
15440 #define SAI_xCR2_TRIS_Pos          (4U)
15441 #define SAI_xCR2_TRIS_Msk          (0x1UL << SAI_xCR2_TRIS_Pos)                 /*!< 0x00000010 */
15442 #define SAI_xCR2_TRIS              SAI_xCR2_TRIS_Msk                           /*!<TRIState Management on data line */
15443 #define SAI_xCR2_MUTE_Pos          (5U)
15444 #define SAI_xCR2_MUTE_Msk          (0x1UL << SAI_xCR2_MUTE_Pos)                 /*!< 0x00000020 */
15445 #define SAI_xCR2_MUTE              SAI_xCR2_MUTE_Msk                           /*!<Mute mode                        */
15446 #define SAI_xCR2_MUTEVAL_Pos       (6U)
15447 #define SAI_xCR2_MUTEVAL_Msk       (0x1UL << SAI_xCR2_MUTEVAL_Pos)              /*!< 0x00000040 */
15448 #define SAI_xCR2_MUTEVAL           SAI_xCR2_MUTEVAL_Msk                        /*!<Muate value                      */
15449 
15450 #define SAI_xCR2_MUTECNT_Pos       (7U)
15451 #define SAI_xCR2_MUTECNT_Msk       (0x3FUL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00001F80 */
15452 #define SAI_xCR2_MUTECNT           SAI_xCR2_MUTECNT_Msk                        /*!<MUTECNT[5:0] (MUTE counter) */
15453 #define SAI_xCR2_MUTECNT_0         (0x01UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000080 */
15454 #define SAI_xCR2_MUTECNT_1         (0x02UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000100 */
15455 #define SAI_xCR2_MUTECNT_2         (0x04UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000200 */
15456 #define SAI_xCR2_MUTECNT_3         (0x08UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000400 */
15457 #define SAI_xCR2_MUTECNT_4         (0x10UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000800 */
15458 #define SAI_xCR2_MUTECNT_5         (0x20UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00001000 */
15459 
15460 #define SAI_xCR2_CPL_Pos           (13U)
15461 #define SAI_xCR2_CPL_Msk           (0x1UL << SAI_xCR2_CPL_Pos)                  /*!< 0x00002000 */
15462 #define SAI_xCR2_CPL               SAI_xCR2_CPL_Msk                            /*!< Complement Bit             */
15463 
15464 #define SAI_xCR2_COMP_Pos          (14U)
15465 #define SAI_xCR2_COMP_Msk          (0x3UL << SAI_xCR2_COMP_Pos)                 /*!< 0x0000C000 */
15466 #define SAI_xCR2_COMP              SAI_xCR2_COMP_Msk                           /*!<COMP[1:0] (Companding mode) */
15467 #define SAI_xCR2_COMP_0            (0x1UL << SAI_xCR2_COMP_Pos)                 /*!< 0x00004000 */
15468 #define SAI_xCR2_COMP_1            (0x2UL << SAI_xCR2_COMP_Pos)                 /*!< 0x00008000 */
15469 
15470 /******************  Bit definition for SAI_xFRCR register  *******************/
15471 #define SAI_xFRCR_FRL_Pos          (0U)
15472 #define SAI_xFRCR_FRL_Msk          (0xFFUL << SAI_xFRCR_FRL_Pos)                /*!< 0x000000FF */
15473 #define SAI_xFRCR_FRL              SAI_xFRCR_FRL_Msk                           /*!<FRL[7:0](Frame length)  */
15474 #define SAI_xFRCR_FRL_0            (0x01UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000001 */
15475 #define SAI_xFRCR_FRL_1            (0x02UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000002 */
15476 #define SAI_xFRCR_FRL_2            (0x04UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000004 */
15477 #define SAI_xFRCR_FRL_3            (0x08UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000008 */
15478 #define SAI_xFRCR_FRL_4            (0x10UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000010 */
15479 #define SAI_xFRCR_FRL_5            (0x20UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000020 */
15480 #define SAI_xFRCR_FRL_6            (0x40UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000040 */
15481 #define SAI_xFRCR_FRL_7            (0x80UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000080 */
15482 
15483 #define SAI_xFRCR_FSALL_Pos        (8U)
15484 #define SAI_xFRCR_FSALL_Msk        (0x7FUL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00007F00 */
15485 #define SAI_xFRCR_FSALL            SAI_xFRCR_FSALL_Msk                         /*!<FRL[6:0] (Frame synchronization active level length)  */
15486 #define SAI_xFRCR_FSALL_0          (0x01UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000100 */
15487 #define SAI_xFRCR_FSALL_1          (0x02UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000200 */
15488 #define SAI_xFRCR_FSALL_2          (0x04UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000400 */
15489 #define SAI_xFRCR_FSALL_3          (0x08UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000800 */
15490 #define SAI_xFRCR_FSALL_4          (0x10UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00001000 */
15491 #define SAI_xFRCR_FSALL_5          (0x20UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00002000 */
15492 #define SAI_xFRCR_FSALL_6          (0x40UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00004000 */
15493 
15494 #define SAI_xFRCR_FSDEF_Pos        (16U)
15495 #define SAI_xFRCR_FSDEF_Msk        (0x1UL << SAI_xFRCR_FSDEF_Pos)               /*!< 0x00010000 */
15496 #define SAI_xFRCR_FSDEF            SAI_xFRCR_FSDEF_Msk                         /*!< Frame Synchronization Definition */
15497 #define SAI_xFRCR_FSPOL_Pos        (17U)
15498 #define SAI_xFRCR_FSPOL_Msk        (0x1UL << SAI_xFRCR_FSPOL_Pos)               /*!< 0x00020000 */
15499 #define SAI_xFRCR_FSPOL            SAI_xFRCR_FSPOL_Msk                         /*!<Frame Synchronization POLarity    */
15500 #define SAI_xFRCR_FSOFF_Pos        (18U)
15501 #define SAI_xFRCR_FSOFF_Msk        (0x1UL << SAI_xFRCR_FSOFF_Pos)               /*!< 0x00040000 */
15502 #define SAI_xFRCR_FSOFF            SAI_xFRCR_FSOFF_Msk                         /*!<Frame Synchronization OFFset      */
15503 /* Legacy defines */
15504 #define  SAI_xFRCR_FSPO                   SAI_xFRCR_FSPOL
15505 
15506 /******************  Bit definition for SAI_xSLOTR register  *******************/
15507 #define SAI_xSLOTR_FBOFF_Pos       (0U)
15508 #define SAI_xSLOTR_FBOFF_Msk       (0x1FUL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x0000001F */
15509 #define SAI_xSLOTR_FBOFF           SAI_xSLOTR_FBOFF_Msk                        /*!<FRL[4:0](First Bit Offset)  */
15510 #define SAI_xSLOTR_FBOFF_0         (0x01UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000001 */
15511 #define SAI_xSLOTR_FBOFF_1         (0x02UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000002 */
15512 #define SAI_xSLOTR_FBOFF_2         (0x04UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000004 */
15513 #define SAI_xSLOTR_FBOFF_3         (0x08UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000008 */
15514 #define SAI_xSLOTR_FBOFF_4         (0x10UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000010 */
15515 
15516 #define SAI_xSLOTR_SLOTSZ_Pos      (6U)
15517 #define SAI_xSLOTR_SLOTSZ_Msk      (0x3UL << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x000000C0 */
15518 #define SAI_xSLOTR_SLOTSZ          SAI_xSLOTR_SLOTSZ_Msk                       /*!<SLOTSZ[1:0] (Slot size)  */
15519 #define SAI_xSLOTR_SLOTSZ_0        (0x1UL << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000040 */
15520 #define SAI_xSLOTR_SLOTSZ_1        (0x2UL << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000080 */
15521 
15522 #define SAI_xSLOTR_NBSLOT_Pos      (8U)
15523 #define SAI_xSLOTR_NBSLOT_Msk      (0xFUL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000F00 */
15524 #define SAI_xSLOTR_NBSLOT          SAI_xSLOTR_NBSLOT_Msk                       /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */
15525 #define SAI_xSLOTR_NBSLOT_0        (0x1UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000100 */
15526 #define SAI_xSLOTR_NBSLOT_1        (0x2UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000200 */
15527 #define SAI_xSLOTR_NBSLOT_2        (0x4UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000400 */
15528 #define SAI_xSLOTR_NBSLOT_3        (0x8UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000800 */
15529 
15530 #define SAI_xSLOTR_SLOTEN_Pos      (16U)
15531 #define SAI_xSLOTR_SLOTEN_Msk      (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos)          /*!< 0xFFFF0000 */
15532 #define SAI_xSLOTR_SLOTEN          SAI_xSLOTR_SLOTEN_Msk                       /*!<SLOTEN[15:0] (Slot Enable)  */
15533 
15534 /*******************  Bit definition for SAI_xIMR register  *******************/
15535 #define SAI_xIMR_OVRUDRIE_Pos      (0U)
15536 #define SAI_xIMR_OVRUDRIE_Msk      (0x1UL << SAI_xIMR_OVRUDRIE_Pos)             /*!< 0x00000001 */
15537 #define SAI_xIMR_OVRUDRIE          SAI_xIMR_OVRUDRIE_Msk                       /*!<Overrun underrun interrupt enable                              */
15538 #define SAI_xIMR_MUTEDETIE_Pos     (1U)
15539 #define SAI_xIMR_MUTEDETIE_Msk     (0x1UL << SAI_xIMR_MUTEDETIE_Pos)            /*!< 0x00000002 */
15540 #define SAI_xIMR_MUTEDETIE         SAI_xIMR_MUTEDETIE_Msk                      /*!<Mute detection interrupt enable                                */
15541 #define SAI_xIMR_WCKCFGIE_Pos      (2U)
15542 #define SAI_xIMR_WCKCFGIE_Msk      (0x1UL << SAI_xIMR_WCKCFGIE_Pos)             /*!< 0x00000004 */
15543 #define SAI_xIMR_WCKCFGIE          SAI_xIMR_WCKCFGIE_Msk                       /*!<Wrong Clock Configuration interrupt enable                     */
15544 #define SAI_xIMR_FREQIE_Pos        (3U)
15545 #define SAI_xIMR_FREQIE_Msk        (0x1UL << SAI_xIMR_FREQIE_Pos)               /*!< 0x00000008 */
15546 #define SAI_xIMR_FREQIE            SAI_xIMR_FREQIE_Msk                         /*!<FIFO request interrupt enable                                  */
15547 #define SAI_xIMR_CNRDYIE_Pos       (4U)
15548 #define SAI_xIMR_CNRDYIE_Msk       (0x1UL << SAI_xIMR_CNRDYIE_Pos)              /*!< 0x00000010 */
15549 #define SAI_xIMR_CNRDYIE           SAI_xIMR_CNRDYIE_Msk                        /*!<Codec not ready interrupt enable                               */
15550 #define SAI_xIMR_AFSDETIE_Pos      (5U)
15551 #define SAI_xIMR_AFSDETIE_Msk      (0x1UL << SAI_xIMR_AFSDETIE_Pos)             /*!< 0x00000020 */
15552 #define SAI_xIMR_AFSDETIE          SAI_xIMR_AFSDETIE_Msk                       /*!<Anticipated frame synchronization detection interrupt enable   */
15553 #define SAI_xIMR_LFSDETIE_Pos      (6U)
15554 #define SAI_xIMR_LFSDETIE_Msk      (0x1UL << SAI_xIMR_LFSDETIE_Pos)             /*!< 0x00000040 */
15555 #define SAI_xIMR_LFSDETIE          SAI_xIMR_LFSDETIE_Msk                       /*!<Late frame synchronization detection interrupt enable          */
15556 
15557 /********************  Bit definition for SAI_xSR register  *******************/
15558 #define SAI_xSR_OVRUDR_Pos         (0U)
15559 #define SAI_xSR_OVRUDR_Msk         (0x1UL << SAI_xSR_OVRUDR_Pos)                /*!< 0x00000001 */
15560 #define SAI_xSR_OVRUDR             SAI_xSR_OVRUDR_Msk                          /*!<Overrun underrun                               */
15561 #define SAI_xSR_MUTEDET_Pos        (1U)
15562 #define SAI_xSR_MUTEDET_Msk        (0x1UL << SAI_xSR_MUTEDET_Pos)               /*!< 0x00000002 */
15563 #define SAI_xSR_MUTEDET            SAI_xSR_MUTEDET_Msk                         /*!<Mute detection                                 */
15564 #define SAI_xSR_WCKCFG_Pos         (2U)
15565 #define SAI_xSR_WCKCFG_Msk         (0x1UL << SAI_xSR_WCKCFG_Pos)                /*!< 0x00000004 */
15566 #define SAI_xSR_WCKCFG             SAI_xSR_WCKCFG_Msk                          /*!<Wrong Clock Configuration                      */
15567 #define SAI_xSR_FREQ_Pos           (3U)
15568 #define SAI_xSR_FREQ_Msk           (0x1UL << SAI_xSR_FREQ_Pos)                  /*!< 0x00000008 */
15569 #define SAI_xSR_FREQ               SAI_xSR_FREQ_Msk                            /*!<FIFO request                                   */
15570 #define SAI_xSR_CNRDY_Pos          (4U)
15571 #define SAI_xSR_CNRDY_Msk          (0x1UL << SAI_xSR_CNRDY_Pos)                 /*!< 0x00000010 */
15572 #define SAI_xSR_CNRDY              SAI_xSR_CNRDY_Msk                           /*!<Codec not ready                                */
15573 #define SAI_xSR_AFSDET_Pos         (5U)
15574 #define SAI_xSR_AFSDET_Msk         (0x1UL << SAI_xSR_AFSDET_Pos)                /*!< 0x00000020 */
15575 #define SAI_xSR_AFSDET             SAI_xSR_AFSDET_Msk                          /*!<Anticipated frame synchronization detection    */
15576 #define SAI_xSR_LFSDET_Pos         (6U)
15577 #define SAI_xSR_LFSDET_Msk         (0x1UL << SAI_xSR_LFSDET_Pos)                /*!< 0x00000040 */
15578 #define SAI_xSR_LFSDET             SAI_xSR_LFSDET_Msk                          /*!<Late frame synchronization detection           */
15579 
15580 #define SAI_xSR_FLVL_Pos           (16U)
15581 #define SAI_xSR_FLVL_Msk           (0x7UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00070000 */
15582 #define SAI_xSR_FLVL               SAI_xSR_FLVL_Msk                            /*!<FLVL[2:0] (FIFO Level Threshold)               */
15583 #define SAI_xSR_FLVL_0             (0x1UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00010000 */
15584 #define SAI_xSR_FLVL_1             (0x2UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00020000 */
15585 #define SAI_xSR_FLVL_2             (0x4UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00040000 */
15586 
15587 /******************  Bit definition for SAI_xCLRFR register  ******************/
15588 #define SAI_xCLRFR_COVRUDR_Pos     (0U)
15589 #define SAI_xCLRFR_COVRUDR_Msk     (0x1UL << SAI_xCLRFR_COVRUDR_Pos)            /*!< 0x00000001 */
15590 #define SAI_xCLRFR_COVRUDR         SAI_xCLRFR_COVRUDR_Msk                      /*!<Clear Overrun underrun                               */
15591 #define SAI_xCLRFR_CMUTEDET_Pos    (1U)
15592 #define SAI_xCLRFR_CMUTEDET_Msk    (0x1UL << SAI_xCLRFR_CMUTEDET_Pos)           /*!< 0x00000002 */
15593 #define SAI_xCLRFR_CMUTEDET        SAI_xCLRFR_CMUTEDET_Msk                     /*!<Clear Mute detection                                 */
15594 #define SAI_xCLRFR_CWCKCFG_Pos     (2U)
15595 #define SAI_xCLRFR_CWCKCFG_Msk     (0x1UL << SAI_xCLRFR_CWCKCFG_Pos)            /*!< 0x00000004 */
15596 #define SAI_xCLRFR_CWCKCFG         SAI_xCLRFR_CWCKCFG_Msk                      /*!<Clear Wrong Clock Configuration                      */
15597 #define SAI_xCLRFR_CFREQ_Pos       (3U)
15598 #define SAI_xCLRFR_CFREQ_Msk       (0x1UL << SAI_xCLRFR_CFREQ_Pos)              /*!< 0x00000008 */
15599 #define SAI_xCLRFR_CFREQ           SAI_xCLRFR_CFREQ_Msk                        /*!<Clear FIFO request                                   */
15600 #define SAI_xCLRFR_CCNRDY_Pos      (4U)
15601 #define SAI_xCLRFR_CCNRDY_Msk      (0x1UL << SAI_xCLRFR_CCNRDY_Pos)             /*!< 0x00000010 */
15602 #define SAI_xCLRFR_CCNRDY          SAI_xCLRFR_CCNRDY_Msk                       /*!<Clear Codec not ready                                */
15603 #define SAI_xCLRFR_CAFSDET_Pos     (5U)
15604 #define SAI_xCLRFR_CAFSDET_Msk     (0x1UL << SAI_xCLRFR_CAFSDET_Pos)            /*!< 0x00000020 */
15605 #define SAI_xCLRFR_CAFSDET         SAI_xCLRFR_CAFSDET_Msk                      /*!<Clear Anticipated frame synchronization detection    */
15606 #define SAI_xCLRFR_CLFSDET_Pos     (6U)
15607 #define SAI_xCLRFR_CLFSDET_Msk     (0x1UL << SAI_xCLRFR_CLFSDET_Pos)            /*!< 0x00000040 */
15608 #define SAI_xCLRFR_CLFSDET         SAI_xCLRFR_CLFSDET_Msk                      /*!<Clear Late frame synchronization detection           */
15609 
15610 /******************  Bit definition for SAI_xDR register  ******************/
15611 #define SAI_xDR_DATA_Pos           (0U)
15612 #define SAI_xDR_DATA_Msk           (0xFFFFFFFFUL << SAI_xDR_DATA_Pos)           /*!< 0xFFFFFFFF */
15613 #define SAI_xDR_DATA               SAI_xDR_DATA_Msk
15614 
15615 
15616 /******************************************************************************/
15617 /*                                                                            */
15618 /*                          SD host Interface                                 */
15619 /*                                                                            */
15620 /******************************************************************************/
15621 /******************  Bit definition for SDIO_POWER register  ******************/
15622 #define SDIO_POWER_PWRCTRL_Pos         (0U)
15623 #define SDIO_POWER_PWRCTRL_Msk         (0x3UL << SDIO_POWER_PWRCTRL_Pos)        /*!< 0x00000003 */
15624 #define SDIO_POWER_PWRCTRL             SDIO_POWER_PWRCTRL_Msk                  /*!<PWRCTRL[1:0] bits (Power supply control bits) */
15625 #define SDIO_POWER_PWRCTRL_0           (0x1UL << SDIO_POWER_PWRCTRL_Pos)        /*!< 0x01 */
15626 #define SDIO_POWER_PWRCTRL_1           (0x2UL << SDIO_POWER_PWRCTRL_Pos)        /*!< 0x02 */
15627 
15628 /******************  Bit definition for SDIO_CLKCR register  ******************/
15629 #define SDIO_CLKCR_CLKDIV_Pos          (0U)
15630 #define SDIO_CLKCR_CLKDIV_Msk          (0xFFUL << SDIO_CLKCR_CLKDIV_Pos)        /*!< 0x000000FF */
15631 #define SDIO_CLKCR_CLKDIV              SDIO_CLKCR_CLKDIV_Msk                   /*!<Clock divide factor             */
15632 #define SDIO_CLKCR_CLKEN_Pos           (8U)
15633 #define SDIO_CLKCR_CLKEN_Msk           (0x1UL << SDIO_CLKCR_CLKEN_Pos)          /*!< 0x00000100 */
15634 #define SDIO_CLKCR_CLKEN               SDIO_CLKCR_CLKEN_Msk                    /*!<Clock enable bit                */
15635 #define SDIO_CLKCR_PWRSAV_Pos          (9U)
15636 #define SDIO_CLKCR_PWRSAV_Msk          (0x1UL << SDIO_CLKCR_PWRSAV_Pos)         /*!< 0x00000200 */
15637 #define SDIO_CLKCR_PWRSAV              SDIO_CLKCR_PWRSAV_Msk                   /*!<Power saving configuration bit  */
15638 #define SDIO_CLKCR_BYPASS_Pos          (10U)
15639 #define SDIO_CLKCR_BYPASS_Msk          (0x1UL << SDIO_CLKCR_BYPASS_Pos)         /*!< 0x00000400 */
15640 #define SDIO_CLKCR_BYPASS              SDIO_CLKCR_BYPASS_Msk                   /*!<Clock divider bypass enable bit */
15641 
15642 #define SDIO_CLKCR_WIDBUS_Pos          (11U)
15643 #define SDIO_CLKCR_WIDBUS_Msk          (0x3UL << SDIO_CLKCR_WIDBUS_Pos)         /*!< 0x00001800 */
15644 #define SDIO_CLKCR_WIDBUS              SDIO_CLKCR_WIDBUS_Msk                   /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
15645 #define SDIO_CLKCR_WIDBUS_0            (0x1UL << SDIO_CLKCR_WIDBUS_Pos)         /*!< 0x0800 */
15646 #define SDIO_CLKCR_WIDBUS_1            (0x2UL << SDIO_CLKCR_WIDBUS_Pos)         /*!< 0x1000 */
15647 
15648 #define SDIO_CLKCR_NEGEDGE_Pos         (13U)
15649 #define SDIO_CLKCR_NEGEDGE_Msk         (0x1UL << SDIO_CLKCR_NEGEDGE_Pos)        /*!< 0x00002000 */
15650 #define SDIO_CLKCR_NEGEDGE             SDIO_CLKCR_NEGEDGE_Msk                  /*!<SDIO_CK dephasing selection bit */
15651 #define SDIO_CLKCR_HWFC_EN_Pos         (14U)
15652 #define SDIO_CLKCR_HWFC_EN_Msk         (0x1UL << SDIO_CLKCR_HWFC_EN_Pos)        /*!< 0x00004000 */
15653 #define SDIO_CLKCR_HWFC_EN             SDIO_CLKCR_HWFC_EN_Msk                  /*!<HW Flow Control enable          */
15654 
15655 /*******************  Bit definition for SDIO_ARG register  *******************/
15656 #define SDIO_ARG_CMDARG_Pos            (0U)
15657 #define SDIO_ARG_CMDARG_Msk            (0xFFFFFFFFUL << SDIO_ARG_CMDARG_Pos)    /*!< 0xFFFFFFFF */
15658 #define SDIO_ARG_CMDARG                SDIO_ARG_CMDARG_Msk                     /*!<Command argument */
15659 
15660 /*******************  Bit definition for SDIO_CMD register  *******************/
15661 #define SDIO_CMD_CMDINDEX_Pos          (0U)
15662 #define SDIO_CMD_CMDINDEX_Msk          (0x3FUL << SDIO_CMD_CMDINDEX_Pos)        /*!< 0x0000003F */
15663 #define SDIO_CMD_CMDINDEX              SDIO_CMD_CMDINDEX_Msk                   /*!<Command Index                               */
15664 
15665 #define SDIO_CMD_WAITRESP_Pos          (6U)
15666 #define SDIO_CMD_WAITRESP_Msk          (0x3UL << SDIO_CMD_WAITRESP_Pos)         /*!< 0x000000C0 */
15667 #define SDIO_CMD_WAITRESP              SDIO_CMD_WAITRESP_Msk                   /*!<WAITRESP[1:0] bits (Wait for response bits) */
15668 #define SDIO_CMD_WAITRESP_0            (0x1UL << SDIO_CMD_WAITRESP_Pos)         /*!< 0x0040 */
15669 #define SDIO_CMD_WAITRESP_1            (0x2UL << SDIO_CMD_WAITRESP_Pos)         /*!< 0x0080 */
15670 
15671 #define SDIO_CMD_WAITINT_Pos           (8U)
15672 #define SDIO_CMD_WAITINT_Msk           (0x1UL << SDIO_CMD_WAITINT_Pos)          /*!< 0x00000100 */
15673 #define SDIO_CMD_WAITINT               SDIO_CMD_WAITINT_Msk                    /*!<CPSM Waits for Interrupt Request                               */
15674 #define SDIO_CMD_WAITPEND_Pos          (9U)
15675 #define SDIO_CMD_WAITPEND_Msk          (0x1UL << SDIO_CMD_WAITPEND_Pos)         /*!< 0x00000200 */
15676 #define SDIO_CMD_WAITPEND              SDIO_CMD_WAITPEND_Msk                   /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
15677 #define SDIO_CMD_CPSMEN_Pos            (10U)
15678 #define SDIO_CMD_CPSMEN_Msk            (0x1UL << SDIO_CMD_CPSMEN_Pos)           /*!< 0x00000400 */
15679 #define SDIO_CMD_CPSMEN                SDIO_CMD_CPSMEN_Msk                     /*!<Command path state machine (CPSM) Enable bit                   */
15680 #define SDIO_CMD_SDIOSUSPEND_Pos       (11U)
15681 #define SDIO_CMD_SDIOSUSPEND_Msk       (0x1UL << SDIO_CMD_SDIOSUSPEND_Pos)      /*!< 0x00000800 */
15682 #define SDIO_CMD_SDIOSUSPEND           SDIO_CMD_SDIOSUSPEND_Msk                /*!<SD I/O suspend command                                         */
15683 
15684 /*****************  Bit definition for SDIO_RESPCMD register  *****************/
15685 #define SDIO_RESPCMD_RESPCMD_Pos       (0U)
15686 #define SDIO_RESPCMD_RESPCMD_Msk       (0x3FUL << SDIO_RESPCMD_RESPCMD_Pos)     /*!< 0x0000003F */
15687 #define SDIO_RESPCMD_RESPCMD           SDIO_RESPCMD_RESPCMD_Msk                /*!<Response command index */
15688 
15689 /******************  Bit definition for SDIO_RESP0 register  ******************/
15690 #define SDIO_RESP0_CARDSTATUS0_Pos     (0U)
15691 #define SDIO_RESP0_CARDSTATUS0_Msk     (0xFFFFFFFFUL << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
15692 #define SDIO_RESP0_CARDSTATUS0         SDIO_RESP0_CARDSTATUS0_Msk              /*!<Card Status */
15693 
15694 /******************  Bit definition for SDIO_RESP1 register  ******************/
15695 #define SDIO_RESP1_CARDSTATUS1_Pos     (0U)
15696 #define SDIO_RESP1_CARDSTATUS1_Msk     (0xFFFFFFFFUL << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
15697 #define SDIO_RESP1_CARDSTATUS1         SDIO_RESP1_CARDSTATUS1_Msk              /*!<Card Status */
15698 
15699 /******************  Bit definition for SDIO_RESP2 register  ******************/
15700 #define SDIO_RESP2_CARDSTATUS2_Pos     (0U)
15701 #define SDIO_RESP2_CARDSTATUS2_Msk     (0xFFFFFFFFUL << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
15702 #define SDIO_RESP2_CARDSTATUS2         SDIO_RESP2_CARDSTATUS2_Msk              /*!<Card Status */
15703 
15704 /******************  Bit definition for SDIO_RESP3 register  ******************/
15705 #define SDIO_RESP3_CARDSTATUS3_Pos     (0U)
15706 #define SDIO_RESP3_CARDSTATUS3_Msk     (0xFFFFFFFFUL << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
15707 #define SDIO_RESP3_CARDSTATUS3         SDIO_RESP3_CARDSTATUS3_Msk              /*!<Card Status */
15708 
15709 /******************  Bit definition for SDIO_RESP4 register  ******************/
15710 #define SDIO_RESP4_CARDSTATUS4_Pos     (0U)
15711 #define SDIO_RESP4_CARDSTATUS4_Msk     (0xFFFFFFFFUL << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
15712 #define SDIO_RESP4_CARDSTATUS4         SDIO_RESP4_CARDSTATUS4_Msk              /*!<Card Status */
15713 
15714 /******************  Bit definition for SDIO_DTIMER register  *****************/
15715 #define SDIO_DTIMER_DATATIME_Pos       (0U)
15716 #define SDIO_DTIMER_DATATIME_Msk       (0xFFFFFFFFUL << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
15717 #define SDIO_DTIMER_DATATIME           SDIO_DTIMER_DATATIME_Msk                /*!<Data timeout period. */
15718 
15719 /******************  Bit definition for SDIO_DLEN register  *******************/
15720 #define SDIO_DLEN_DATALENGTH_Pos       (0U)
15721 #define SDIO_DLEN_DATALENGTH_Msk       (0x1FFFFFFUL << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
15722 #define SDIO_DLEN_DATALENGTH           SDIO_DLEN_DATALENGTH_Msk                /*!<Data length value    */
15723 
15724 /******************  Bit definition for SDIO_DCTRL register  ******************/
15725 #define SDIO_DCTRL_DTEN_Pos            (0U)
15726 #define SDIO_DCTRL_DTEN_Msk            (0x1UL << SDIO_DCTRL_DTEN_Pos)           /*!< 0x00000001 */
15727 #define SDIO_DCTRL_DTEN                SDIO_DCTRL_DTEN_Msk                     /*!<Data transfer enabled bit         */
15728 #define SDIO_DCTRL_DTDIR_Pos           (1U)
15729 #define SDIO_DCTRL_DTDIR_Msk           (0x1UL << SDIO_DCTRL_DTDIR_Pos)          /*!< 0x00000002 */
15730 #define SDIO_DCTRL_DTDIR               SDIO_DCTRL_DTDIR_Msk                    /*!<Data transfer direction selection */
15731 #define SDIO_DCTRL_DTMODE_Pos          (2U)
15732 #define SDIO_DCTRL_DTMODE_Msk          (0x1UL << SDIO_DCTRL_DTMODE_Pos)         /*!< 0x00000004 */
15733 #define SDIO_DCTRL_DTMODE              SDIO_DCTRL_DTMODE_Msk                   /*!<Data transfer mode selection      */
15734 #define SDIO_DCTRL_DMAEN_Pos           (3U)
15735 #define SDIO_DCTRL_DMAEN_Msk           (0x1UL << SDIO_DCTRL_DMAEN_Pos)          /*!< 0x00000008 */
15736 #define SDIO_DCTRL_DMAEN               SDIO_DCTRL_DMAEN_Msk                    /*!<DMA enabled bit                   */
15737 
15738 #define SDIO_DCTRL_DBLOCKSIZE_Pos      (4U)
15739 #define SDIO_DCTRL_DBLOCKSIZE_Msk      (0xFUL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x000000F0 */
15740 #define SDIO_DCTRL_DBLOCKSIZE          SDIO_DCTRL_DBLOCKSIZE_Msk               /*!<DBLOCKSIZE[3:0] bits (Data block size) */
15741 #define SDIO_DCTRL_DBLOCKSIZE_0        (0x1UL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0010 */
15742 #define SDIO_DCTRL_DBLOCKSIZE_1        (0x2UL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0020 */
15743 #define SDIO_DCTRL_DBLOCKSIZE_2        (0x4UL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0040 */
15744 #define SDIO_DCTRL_DBLOCKSIZE_3        (0x8UL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0080 */
15745 
15746 #define SDIO_DCTRL_RWSTART_Pos         (8U)
15747 #define SDIO_DCTRL_RWSTART_Msk         (0x1UL << SDIO_DCTRL_RWSTART_Pos)        /*!< 0x00000100 */
15748 #define SDIO_DCTRL_RWSTART             SDIO_DCTRL_RWSTART_Msk                  /*!<Read wait start         */
15749 #define SDIO_DCTRL_RWSTOP_Pos          (9U)
15750 #define SDIO_DCTRL_RWSTOP_Msk          (0x1UL << SDIO_DCTRL_RWSTOP_Pos)         /*!< 0x00000200 */
15751 #define SDIO_DCTRL_RWSTOP              SDIO_DCTRL_RWSTOP_Msk                   /*!<Read wait stop          */
15752 #define SDIO_DCTRL_RWMOD_Pos           (10U)
15753 #define SDIO_DCTRL_RWMOD_Msk           (0x1UL << SDIO_DCTRL_RWMOD_Pos)          /*!< 0x00000400 */
15754 #define SDIO_DCTRL_RWMOD               SDIO_DCTRL_RWMOD_Msk                    /*!<Read wait mode          */
15755 #define SDIO_DCTRL_SDIOEN_Pos          (11U)
15756 #define SDIO_DCTRL_SDIOEN_Msk          (0x1UL << SDIO_DCTRL_SDIOEN_Pos)         /*!< 0x00000800 */
15757 #define SDIO_DCTRL_SDIOEN              SDIO_DCTRL_SDIOEN_Msk                   /*!<SD I/O enable functions */
15758 
15759 /******************  Bit definition for SDIO_DCOUNT register  *****************/
15760 #define SDIO_DCOUNT_DATACOUNT_Pos      (0U)
15761 #define SDIO_DCOUNT_DATACOUNT_Msk      (0x1FFFFFFUL << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
15762 #define SDIO_DCOUNT_DATACOUNT          SDIO_DCOUNT_DATACOUNT_Msk               /*!<Data count value */
15763 
15764 /******************  Bit definition for SDIO_STA register  ********************/
15765 #define SDIO_STA_CCRCFAIL_Pos          (0U)
15766 #define SDIO_STA_CCRCFAIL_Msk          (0x1UL << SDIO_STA_CCRCFAIL_Pos)         /*!< 0x00000001 */
15767 #define SDIO_STA_CCRCFAIL              SDIO_STA_CCRCFAIL_Msk                   /*!<Command response received (CRC check failed)  */
15768 #define SDIO_STA_DCRCFAIL_Pos          (1U)
15769 #define SDIO_STA_DCRCFAIL_Msk          (0x1UL << SDIO_STA_DCRCFAIL_Pos)         /*!< 0x00000002 */
15770 #define SDIO_STA_DCRCFAIL              SDIO_STA_DCRCFAIL_Msk                   /*!<Data block sent/received (CRC check failed)   */
15771 #define SDIO_STA_CTIMEOUT_Pos          (2U)
15772 #define SDIO_STA_CTIMEOUT_Msk          (0x1UL << SDIO_STA_CTIMEOUT_Pos)         /*!< 0x00000004 */
15773 #define SDIO_STA_CTIMEOUT              SDIO_STA_CTIMEOUT_Msk                   /*!<Command response timeout                      */
15774 #define SDIO_STA_DTIMEOUT_Pos          (3U)
15775 #define SDIO_STA_DTIMEOUT_Msk          (0x1UL << SDIO_STA_DTIMEOUT_Pos)         /*!< 0x00000008 */
15776 #define SDIO_STA_DTIMEOUT              SDIO_STA_DTIMEOUT_Msk                   /*!<Data timeout                                  */
15777 #define SDIO_STA_TXUNDERR_Pos          (4U)
15778 #define SDIO_STA_TXUNDERR_Msk          (0x1UL << SDIO_STA_TXUNDERR_Pos)         /*!< 0x00000010 */
15779 #define SDIO_STA_TXUNDERR              SDIO_STA_TXUNDERR_Msk                   /*!<Transmit FIFO underrun error                  */
15780 #define SDIO_STA_RXOVERR_Pos           (5U)
15781 #define SDIO_STA_RXOVERR_Msk           (0x1UL << SDIO_STA_RXOVERR_Pos)          /*!< 0x00000020 */
15782 #define SDIO_STA_RXOVERR               SDIO_STA_RXOVERR_Msk                    /*!<Received FIFO overrun error                   */
15783 #define SDIO_STA_CMDREND_Pos           (6U)
15784 #define SDIO_STA_CMDREND_Msk           (0x1UL << SDIO_STA_CMDREND_Pos)          /*!< 0x00000040 */
15785 #define SDIO_STA_CMDREND               SDIO_STA_CMDREND_Msk                    /*!<Command response received (CRC check passed)  */
15786 #define SDIO_STA_CMDSENT_Pos           (7U)
15787 #define SDIO_STA_CMDSENT_Msk           (0x1UL << SDIO_STA_CMDSENT_Pos)          /*!< 0x00000080 */
15788 #define SDIO_STA_CMDSENT               SDIO_STA_CMDSENT_Msk                    /*!<Command sent (no response required)           */
15789 #define SDIO_STA_DATAEND_Pos           (8U)
15790 #define SDIO_STA_DATAEND_Msk           (0x1UL << SDIO_STA_DATAEND_Pos)          /*!< 0x00000100 */
15791 #define SDIO_STA_DATAEND               SDIO_STA_DATAEND_Msk                    /*!<Data end (data counter, SDIDCOUNT, is zero)   */
15792 #define SDIO_STA_DBCKEND_Pos           (10U)
15793 #define SDIO_STA_DBCKEND_Msk           (0x1UL << SDIO_STA_DBCKEND_Pos)          /*!< 0x00000400 */
15794 #define SDIO_STA_DBCKEND               SDIO_STA_DBCKEND_Msk                    /*!<Data block sent/received (CRC check passed)   */
15795 #define SDIO_STA_CMDACT_Pos            (11U)
15796 #define SDIO_STA_CMDACT_Msk            (0x1UL << SDIO_STA_CMDACT_Pos)           /*!< 0x00000800 */
15797 #define SDIO_STA_CMDACT                SDIO_STA_CMDACT_Msk                     /*!<Command transfer in progress                  */
15798 #define SDIO_STA_TXACT_Pos             (12U)
15799 #define SDIO_STA_TXACT_Msk             (0x1UL << SDIO_STA_TXACT_Pos)            /*!< 0x00001000 */
15800 #define SDIO_STA_TXACT                 SDIO_STA_TXACT_Msk                      /*!<Data transmit in progress                     */
15801 #define SDIO_STA_RXACT_Pos             (13U)
15802 #define SDIO_STA_RXACT_Msk             (0x1UL << SDIO_STA_RXACT_Pos)            /*!< 0x00002000 */
15803 #define SDIO_STA_RXACT                 SDIO_STA_RXACT_Msk                      /*!<Data receive in progress                      */
15804 #define SDIO_STA_TXFIFOHE_Pos          (14U)
15805 #define SDIO_STA_TXFIFOHE_Msk          (0x1UL << SDIO_STA_TXFIFOHE_Pos)         /*!< 0x00004000 */
15806 #define SDIO_STA_TXFIFOHE              SDIO_STA_TXFIFOHE_Msk                   /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
15807 #define SDIO_STA_RXFIFOHF_Pos          (15U)
15808 #define SDIO_STA_RXFIFOHF_Msk          (0x1UL << SDIO_STA_RXFIFOHF_Pos)         /*!< 0x00008000 */
15809 #define SDIO_STA_RXFIFOHF              SDIO_STA_RXFIFOHF_Msk                   /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
15810 #define SDIO_STA_TXFIFOF_Pos           (16U)
15811 #define SDIO_STA_TXFIFOF_Msk           (0x1UL << SDIO_STA_TXFIFOF_Pos)          /*!< 0x00010000 */
15812 #define SDIO_STA_TXFIFOF               SDIO_STA_TXFIFOF_Msk                    /*!<Transmit FIFO full                            */
15813 #define SDIO_STA_RXFIFOF_Pos           (17U)
15814 #define SDIO_STA_RXFIFOF_Msk           (0x1UL << SDIO_STA_RXFIFOF_Pos)          /*!< 0x00020000 */
15815 #define SDIO_STA_RXFIFOF               SDIO_STA_RXFIFOF_Msk                    /*!<Receive FIFO full                             */
15816 #define SDIO_STA_TXFIFOE_Pos           (18U)
15817 #define SDIO_STA_TXFIFOE_Msk           (0x1UL << SDIO_STA_TXFIFOE_Pos)          /*!< 0x00040000 */
15818 #define SDIO_STA_TXFIFOE               SDIO_STA_TXFIFOE_Msk                    /*!<Transmit FIFO empty                           */
15819 #define SDIO_STA_RXFIFOE_Pos           (19U)
15820 #define SDIO_STA_RXFIFOE_Msk           (0x1UL << SDIO_STA_RXFIFOE_Pos)          /*!< 0x00080000 */
15821 #define SDIO_STA_RXFIFOE               SDIO_STA_RXFIFOE_Msk                    /*!<Receive FIFO empty                            */
15822 #define SDIO_STA_TXDAVL_Pos            (20U)
15823 #define SDIO_STA_TXDAVL_Msk            (0x1UL << SDIO_STA_TXDAVL_Pos)           /*!< 0x00100000 */
15824 #define SDIO_STA_TXDAVL                SDIO_STA_TXDAVL_Msk                     /*!<Data available in transmit FIFO               */
15825 #define SDIO_STA_RXDAVL_Pos            (21U)
15826 #define SDIO_STA_RXDAVL_Msk            (0x1UL << SDIO_STA_RXDAVL_Pos)           /*!< 0x00200000 */
15827 #define SDIO_STA_RXDAVL                SDIO_STA_RXDAVL_Msk                     /*!<Data available in receive FIFO                */
15828 #define SDIO_STA_SDIOIT_Pos            (22U)
15829 #define SDIO_STA_SDIOIT_Msk            (0x1UL << SDIO_STA_SDIOIT_Pos)           /*!< 0x00400000 */
15830 #define SDIO_STA_SDIOIT                SDIO_STA_SDIOIT_Msk                     /*!<SDIO interrupt received                       */
15831 
15832 /*******************  Bit definition for SDIO_ICR register  *******************/
15833 #define SDIO_ICR_CCRCFAILC_Pos         (0U)
15834 #define SDIO_ICR_CCRCFAILC_Msk         (0x1UL << SDIO_ICR_CCRCFAILC_Pos)        /*!< 0x00000001 */
15835 #define SDIO_ICR_CCRCFAILC             SDIO_ICR_CCRCFAILC_Msk                  /*!<CCRCFAIL flag clear bit */
15836 #define SDIO_ICR_DCRCFAILC_Pos         (1U)
15837 #define SDIO_ICR_DCRCFAILC_Msk         (0x1UL << SDIO_ICR_DCRCFAILC_Pos)        /*!< 0x00000002 */
15838 #define SDIO_ICR_DCRCFAILC             SDIO_ICR_DCRCFAILC_Msk                  /*!<DCRCFAIL flag clear bit */
15839 #define SDIO_ICR_CTIMEOUTC_Pos         (2U)
15840 #define SDIO_ICR_CTIMEOUTC_Msk         (0x1UL << SDIO_ICR_CTIMEOUTC_Pos)        /*!< 0x00000004 */
15841 #define SDIO_ICR_CTIMEOUTC             SDIO_ICR_CTIMEOUTC_Msk                  /*!<CTIMEOUT flag clear bit */
15842 #define SDIO_ICR_DTIMEOUTC_Pos         (3U)
15843 #define SDIO_ICR_DTIMEOUTC_Msk         (0x1UL << SDIO_ICR_DTIMEOUTC_Pos)        /*!< 0x00000008 */
15844 #define SDIO_ICR_DTIMEOUTC             SDIO_ICR_DTIMEOUTC_Msk                  /*!<DTIMEOUT flag clear bit */
15845 #define SDIO_ICR_TXUNDERRC_Pos         (4U)
15846 #define SDIO_ICR_TXUNDERRC_Msk         (0x1UL << SDIO_ICR_TXUNDERRC_Pos)        /*!< 0x00000010 */
15847 #define SDIO_ICR_TXUNDERRC             SDIO_ICR_TXUNDERRC_Msk                  /*!<TXUNDERR flag clear bit */
15848 #define SDIO_ICR_RXOVERRC_Pos          (5U)
15849 #define SDIO_ICR_RXOVERRC_Msk          (0x1UL << SDIO_ICR_RXOVERRC_Pos)         /*!< 0x00000020 */
15850 #define SDIO_ICR_RXOVERRC              SDIO_ICR_RXOVERRC_Msk                   /*!<RXOVERR flag clear bit  */
15851 #define SDIO_ICR_CMDRENDC_Pos          (6U)
15852 #define SDIO_ICR_CMDRENDC_Msk          (0x1UL << SDIO_ICR_CMDRENDC_Pos)         /*!< 0x00000040 */
15853 #define SDIO_ICR_CMDRENDC              SDIO_ICR_CMDRENDC_Msk                   /*!<CMDREND flag clear bit  */
15854 #define SDIO_ICR_CMDSENTC_Pos          (7U)
15855 #define SDIO_ICR_CMDSENTC_Msk          (0x1UL << SDIO_ICR_CMDSENTC_Pos)         /*!< 0x00000080 */
15856 #define SDIO_ICR_CMDSENTC              SDIO_ICR_CMDSENTC_Msk                   /*!<CMDSENT flag clear bit  */
15857 #define SDIO_ICR_DATAENDC_Pos          (8U)
15858 #define SDIO_ICR_DATAENDC_Msk          (0x1UL << SDIO_ICR_DATAENDC_Pos)         /*!< 0x00000100 */
15859 #define SDIO_ICR_DATAENDC              SDIO_ICR_DATAENDC_Msk                   /*!<DATAEND flag clear bit  */
15860 #define SDIO_ICR_DBCKENDC_Pos          (10U)
15861 #define SDIO_ICR_DBCKENDC_Msk          (0x1UL << SDIO_ICR_DBCKENDC_Pos)         /*!< 0x00000400 */
15862 #define SDIO_ICR_DBCKENDC              SDIO_ICR_DBCKENDC_Msk                   /*!<DBCKEND flag clear bit  */
15863 #define SDIO_ICR_SDIOITC_Pos           (22U)
15864 #define SDIO_ICR_SDIOITC_Msk           (0x1UL << SDIO_ICR_SDIOITC_Pos)          /*!< 0x00400000 */
15865 #define SDIO_ICR_SDIOITC               SDIO_ICR_SDIOITC_Msk                    /*!<SDIOIT flag clear bit   */
15866 
15867 /******************  Bit definition for SDIO_MASK register  *******************/
15868 #define SDIO_MASK_CCRCFAILIE_Pos       (0U)
15869 #define SDIO_MASK_CCRCFAILIE_Msk       (0x1UL << SDIO_MASK_CCRCFAILIE_Pos)      /*!< 0x00000001 */
15870 #define SDIO_MASK_CCRCFAILIE           SDIO_MASK_CCRCFAILIE_Msk                /*!<Command CRC Fail Interrupt Enable          */
15871 #define SDIO_MASK_DCRCFAILIE_Pos       (1U)
15872 #define SDIO_MASK_DCRCFAILIE_Msk       (0x1UL << SDIO_MASK_DCRCFAILIE_Pos)      /*!< 0x00000002 */
15873 #define SDIO_MASK_DCRCFAILIE           SDIO_MASK_DCRCFAILIE_Msk                /*!<Data CRC Fail Interrupt Enable             */
15874 #define SDIO_MASK_CTIMEOUTIE_Pos       (2U)
15875 #define SDIO_MASK_CTIMEOUTIE_Msk       (0x1UL << SDIO_MASK_CTIMEOUTIE_Pos)      /*!< 0x00000004 */
15876 #define SDIO_MASK_CTIMEOUTIE           SDIO_MASK_CTIMEOUTIE_Msk                /*!<Command TimeOut Interrupt Enable           */
15877 #define SDIO_MASK_DTIMEOUTIE_Pos       (3U)
15878 #define SDIO_MASK_DTIMEOUTIE_Msk       (0x1UL << SDIO_MASK_DTIMEOUTIE_Pos)      /*!< 0x00000008 */
15879 #define SDIO_MASK_DTIMEOUTIE           SDIO_MASK_DTIMEOUTIE_Msk                /*!<Data TimeOut Interrupt Enable              */
15880 #define SDIO_MASK_TXUNDERRIE_Pos       (4U)
15881 #define SDIO_MASK_TXUNDERRIE_Msk       (0x1UL << SDIO_MASK_TXUNDERRIE_Pos)      /*!< 0x00000010 */
15882 #define SDIO_MASK_TXUNDERRIE           SDIO_MASK_TXUNDERRIE_Msk                /*!<Tx FIFO UnderRun Error Interrupt Enable    */
15883 #define SDIO_MASK_RXOVERRIE_Pos        (5U)
15884 #define SDIO_MASK_RXOVERRIE_Msk        (0x1UL << SDIO_MASK_RXOVERRIE_Pos)       /*!< 0x00000020 */
15885 #define SDIO_MASK_RXOVERRIE            SDIO_MASK_RXOVERRIE_Msk                 /*!<Rx FIFO OverRun Error Interrupt Enable     */
15886 #define SDIO_MASK_CMDRENDIE_Pos        (6U)
15887 #define SDIO_MASK_CMDRENDIE_Msk        (0x1UL << SDIO_MASK_CMDRENDIE_Pos)       /*!< 0x00000040 */
15888 #define SDIO_MASK_CMDRENDIE            SDIO_MASK_CMDRENDIE_Msk                 /*!<Command Response Received Interrupt Enable */
15889 #define SDIO_MASK_CMDSENTIE_Pos        (7U)
15890 #define SDIO_MASK_CMDSENTIE_Msk        (0x1UL << SDIO_MASK_CMDSENTIE_Pos)       /*!< 0x00000080 */
15891 #define SDIO_MASK_CMDSENTIE            SDIO_MASK_CMDSENTIE_Msk                 /*!<Command Sent Interrupt Enable              */
15892 #define SDIO_MASK_DATAENDIE_Pos        (8U)
15893 #define SDIO_MASK_DATAENDIE_Msk        (0x1UL << SDIO_MASK_DATAENDIE_Pos)       /*!< 0x00000100 */
15894 #define SDIO_MASK_DATAENDIE            SDIO_MASK_DATAENDIE_Msk                 /*!<Data End Interrupt Enable                  */
15895 #define SDIO_MASK_DBCKENDIE_Pos        (10U)
15896 #define SDIO_MASK_DBCKENDIE_Msk        (0x1UL << SDIO_MASK_DBCKENDIE_Pos)       /*!< 0x00000400 */
15897 #define SDIO_MASK_DBCKENDIE            SDIO_MASK_DBCKENDIE_Msk                 /*!<Data Block End Interrupt Enable            */
15898 #define SDIO_MASK_CMDACTIE_Pos         (11U)
15899 #define SDIO_MASK_CMDACTIE_Msk         (0x1UL << SDIO_MASK_CMDACTIE_Pos)        /*!< 0x00000800 */
15900 #define SDIO_MASK_CMDACTIE             SDIO_MASK_CMDACTIE_Msk                  /*!<CCommand Acting Interrupt Enable           */
15901 #define SDIO_MASK_TXACTIE_Pos          (12U)
15902 #define SDIO_MASK_TXACTIE_Msk          (0x1UL << SDIO_MASK_TXACTIE_Pos)         /*!< 0x00001000 */
15903 #define SDIO_MASK_TXACTIE              SDIO_MASK_TXACTIE_Msk                   /*!<Data Transmit Acting Interrupt Enable      */
15904 #define SDIO_MASK_RXACTIE_Pos          (13U)
15905 #define SDIO_MASK_RXACTIE_Msk          (0x1UL << SDIO_MASK_RXACTIE_Pos)         /*!< 0x00002000 */
15906 #define SDIO_MASK_RXACTIE              SDIO_MASK_RXACTIE_Msk                   /*!<Data receive acting interrupt enabled      */
15907 #define SDIO_MASK_TXFIFOHEIE_Pos       (14U)
15908 #define SDIO_MASK_TXFIFOHEIE_Msk       (0x1UL << SDIO_MASK_TXFIFOHEIE_Pos)      /*!< 0x00004000 */
15909 #define SDIO_MASK_TXFIFOHEIE           SDIO_MASK_TXFIFOHEIE_Msk                /*!<Tx FIFO Half Empty interrupt Enable        */
15910 #define SDIO_MASK_RXFIFOHFIE_Pos       (15U)
15911 #define SDIO_MASK_RXFIFOHFIE_Msk       (0x1UL << SDIO_MASK_RXFIFOHFIE_Pos)      /*!< 0x00008000 */
15912 #define SDIO_MASK_RXFIFOHFIE           SDIO_MASK_RXFIFOHFIE_Msk                /*!<Rx FIFO Half Full interrupt Enable         */
15913 #define SDIO_MASK_TXFIFOFIE_Pos        (16U)
15914 #define SDIO_MASK_TXFIFOFIE_Msk        (0x1UL << SDIO_MASK_TXFIFOFIE_Pos)       /*!< 0x00010000 */
15915 #define SDIO_MASK_TXFIFOFIE            SDIO_MASK_TXFIFOFIE_Msk                 /*!<Tx FIFO Full interrupt Enable              */
15916 #define SDIO_MASK_RXFIFOFIE_Pos        (17U)
15917 #define SDIO_MASK_RXFIFOFIE_Msk        (0x1UL << SDIO_MASK_RXFIFOFIE_Pos)       /*!< 0x00020000 */
15918 #define SDIO_MASK_RXFIFOFIE            SDIO_MASK_RXFIFOFIE_Msk                 /*!<Rx FIFO Full interrupt Enable              */
15919 #define SDIO_MASK_TXFIFOEIE_Pos        (18U)
15920 #define SDIO_MASK_TXFIFOEIE_Msk        (0x1UL << SDIO_MASK_TXFIFOEIE_Pos)       /*!< 0x00040000 */
15921 #define SDIO_MASK_TXFIFOEIE            SDIO_MASK_TXFIFOEIE_Msk                 /*!<Tx FIFO Empty interrupt Enable             */
15922 #define SDIO_MASK_RXFIFOEIE_Pos        (19U)
15923 #define SDIO_MASK_RXFIFOEIE_Msk        (0x1UL << SDIO_MASK_RXFIFOEIE_Pos)       /*!< 0x00080000 */
15924 #define SDIO_MASK_RXFIFOEIE            SDIO_MASK_RXFIFOEIE_Msk                 /*!<Rx FIFO Empty interrupt Enable             */
15925 #define SDIO_MASK_TXDAVLIE_Pos         (20U)
15926 #define SDIO_MASK_TXDAVLIE_Msk         (0x1UL << SDIO_MASK_TXDAVLIE_Pos)        /*!< 0x00100000 */
15927 #define SDIO_MASK_TXDAVLIE             SDIO_MASK_TXDAVLIE_Msk                  /*!<Data available in Tx FIFO interrupt Enable */
15928 #define SDIO_MASK_RXDAVLIE_Pos         (21U)
15929 #define SDIO_MASK_RXDAVLIE_Msk         (0x1UL << SDIO_MASK_RXDAVLIE_Pos)        /*!< 0x00200000 */
15930 #define SDIO_MASK_RXDAVLIE             SDIO_MASK_RXDAVLIE_Msk                  /*!<Data available in Rx FIFO interrupt Enable */
15931 #define SDIO_MASK_SDIOITIE_Pos         (22U)
15932 #define SDIO_MASK_SDIOITIE_Msk         (0x1UL << SDIO_MASK_SDIOITIE_Pos)        /*!< 0x00400000 */
15933 #define SDIO_MASK_SDIOITIE             SDIO_MASK_SDIOITIE_Msk                  /*!<SDIO Mode Interrupt Received interrupt Enable */
15934 
15935 /*****************  Bit definition for SDIO_FIFOCNT register  *****************/
15936 #define SDIO_FIFOCNT_FIFOCOUNT_Pos     (0U)
15937 #define SDIO_FIFOCNT_FIFOCOUNT_Msk     (0xFFFFFFUL << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
15938 #define SDIO_FIFOCNT_FIFOCOUNT         SDIO_FIFOCNT_FIFOCOUNT_Msk              /*!<Remaining number of words to be written to or read from the FIFO */
15939 
15940 /******************  Bit definition for SDIO_FIFO register  *******************/
15941 #define SDIO_FIFO_FIFODATA_Pos         (0U)
15942 #define SDIO_FIFO_FIFODATA_Msk         (0xFFFFFFFFUL << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
15943 #define SDIO_FIFO_FIFODATA             SDIO_FIFO_FIFODATA_Msk                  /*!<Receive and transmit FIFO data */
15944 
15945 /******************************************************************************/
15946 /*                                                                            */
15947 /*                        Serial Peripheral Interface                         */
15948 /*                                                                            */
15949 /******************************************************************************/
15950 #define SPI_I2S_FULLDUPLEX_SUPPORT                                             /*!< I2S Full-Duplex support */
15951 
15952 /*******************  Bit definition for SPI_CR1 register  ********************/
15953 #define SPI_CR1_CPHA_Pos            (0U)
15954 #define SPI_CR1_CPHA_Msk            (0x1UL << SPI_CR1_CPHA_Pos)                 /*!< 0x00000001 */
15955 #define SPI_CR1_CPHA                SPI_CR1_CPHA_Msk                           /*!<Clock Phase      */
15956 #define SPI_CR1_CPOL_Pos            (1U)
15957 #define SPI_CR1_CPOL_Msk            (0x1UL << SPI_CR1_CPOL_Pos)                 /*!< 0x00000002 */
15958 #define SPI_CR1_CPOL                SPI_CR1_CPOL_Msk                           /*!<Clock Polarity   */
15959 #define SPI_CR1_MSTR_Pos            (2U)
15960 #define SPI_CR1_MSTR_Msk            (0x1UL << SPI_CR1_MSTR_Pos)                 /*!< 0x00000004 */
15961 #define SPI_CR1_MSTR                SPI_CR1_MSTR_Msk                           /*!<Master Selection */
15962 
15963 #define SPI_CR1_BR_Pos              (3U)
15964 #define SPI_CR1_BR_Msk              (0x7UL << SPI_CR1_BR_Pos)                   /*!< 0x00000038 */
15965 #define SPI_CR1_BR                  SPI_CR1_BR_Msk                             /*!<BR[2:0] bits (Baud Rate Control) */
15966 #define SPI_CR1_BR_0                (0x1UL << SPI_CR1_BR_Pos)                   /*!< 0x00000008 */
15967 #define SPI_CR1_BR_1                (0x2UL << SPI_CR1_BR_Pos)                   /*!< 0x00000010 */
15968 #define SPI_CR1_BR_2                (0x4UL << SPI_CR1_BR_Pos)                   /*!< 0x00000020 */
15969 
15970 #define SPI_CR1_SPE_Pos             (6U)
15971 #define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                  /*!< 0x00000040 */
15972 #define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!<SPI Enable                          */
15973 #define SPI_CR1_LSBFIRST_Pos        (7U)
15974 #define SPI_CR1_LSBFIRST_Msk        (0x1UL << SPI_CR1_LSBFIRST_Pos)             /*!< 0x00000080 */
15975 #define SPI_CR1_LSBFIRST            SPI_CR1_LSBFIRST_Msk                       /*!<Frame Format                        */
15976 #define SPI_CR1_SSI_Pos             (8U)
15977 #define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                  /*!< 0x00000100 */
15978 #define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!<Internal slave select               */
15979 #define SPI_CR1_SSM_Pos             (9U)
15980 #define SPI_CR1_SSM_Msk             (0x1UL << SPI_CR1_SSM_Pos)                  /*!< 0x00000200 */
15981 #define SPI_CR1_SSM                 SPI_CR1_SSM_Msk                            /*!<Software slave management           */
15982 #define SPI_CR1_RXONLY_Pos          (10U)
15983 #define SPI_CR1_RXONLY_Msk          (0x1UL << SPI_CR1_RXONLY_Pos)               /*!< 0x00000400 */
15984 #define SPI_CR1_RXONLY              SPI_CR1_RXONLY_Msk                         /*!<Receive only                        */
15985 #define SPI_CR1_DFF_Pos             (11U)
15986 #define SPI_CR1_DFF_Msk             (0x1UL << SPI_CR1_DFF_Pos)                  /*!< 0x00000800 */
15987 #define SPI_CR1_DFF                 SPI_CR1_DFF_Msk                            /*!<Data Frame Format                   */
15988 #define SPI_CR1_CRCNEXT_Pos         (12U)
15989 #define SPI_CR1_CRCNEXT_Msk         (0x1UL << SPI_CR1_CRCNEXT_Pos)              /*!< 0x00001000 */
15990 #define SPI_CR1_CRCNEXT             SPI_CR1_CRCNEXT_Msk                        /*!<Transmit CRC next                   */
15991 #define SPI_CR1_CRCEN_Pos           (13U)
15992 #define SPI_CR1_CRCEN_Msk           (0x1UL << SPI_CR1_CRCEN_Pos)                /*!< 0x00002000 */
15993 #define SPI_CR1_CRCEN               SPI_CR1_CRCEN_Msk                          /*!<Hardware CRC calculation enable     */
15994 #define SPI_CR1_BIDIOE_Pos          (14U)
15995 #define SPI_CR1_BIDIOE_Msk          (0x1UL << SPI_CR1_BIDIOE_Pos)               /*!< 0x00004000 */
15996 #define SPI_CR1_BIDIOE              SPI_CR1_BIDIOE_Msk                         /*!<Output enable in bidirectional mode */
15997 #define SPI_CR1_BIDIMODE_Pos        (15U)
15998 #define SPI_CR1_BIDIMODE_Msk        (0x1UL << SPI_CR1_BIDIMODE_Pos)             /*!< 0x00008000 */
15999 #define SPI_CR1_BIDIMODE            SPI_CR1_BIDIMODE_Msk                       /*!<Bidirectional data mode enable      */
16000 
16001 /*******************  Bit definition for SPI_CR2 register  ********************/
16002 #define SPI_CR2_RXDMAEN_Pos         (0U)
16003 #define SPI_CR2_RXDMAEN_Msk         (0x1UL << SPI_CR2_RXDMAEN_Pos)              /*!< 0x00000001 */
16004 #define SPI_CR2_RXDMAEN             SPI_CR2_RXDMAEN_Msk                        /*!<Rx Buffer DMA Enable                 */
16005 #define SPI_CR2_TXDMAEN_Pos         (1U)
16006 #define SPI_CR2_TXDMAEN_Msk         (0x1UL << SPI_CR2_TXDMAEN_Pos)              /*!< 0x00000002 */
16007 #define SPI_CR2_TXDMAEN             SPI_CR2_TXDMAEN_Msk                        /*!<Tx Buffer DMA Enable                 */
16008 #define SPI_CR2_SSOE_Pos            (2U)
16009 #define SPI_CR2_SSOE_Msk            (0x1UL << SPI_CR2_SSOE_Pos)                 /*!< 0x00000004 */
16010 #define SPI_CR2_SSOE                SPI_CR2_SSOE_Msk                           /*!<SS Output Enable                     */
16011 #define SPI_CR2_FRF_Pos             (4U)
16012 #define SPI_CR2_FRF_Msk             (0x1UL << SPI_CR2_FRF_Pos)                  /*!< 0x00000010 */
16013 #define SPI_CR2_FRF                 SPI_CR2_FRF_Msk                            /*!<Frame Format                         */
16014 #define SPI_CR2_ERRIE_Pos           (5U)
16015 #define SPI_CR2_ERRIE_Msk           (0x1UL << SPI_CR2_ERRIE_Pos)                /*!< 0x00000020 */
16016 #define SPI_CR2_ERRIE               SPI_CR2_ERRIE_Msk                          /*!<Error Interrupt Enable               */
16017 #define SPI_CR2_RXNEIE_Pos          (6U)
16018 #define SPI_CR2_RXNEIE_Msk          (0x1UL << SPI_CR2_RXNEIE_Pos)               /*!< 0x00000040 */
16019 #define SPI_CR2_RXNEIE              SPI_CR2_RXNEIE_Msk                         /*!<RX buffer Not Empty Interrupt Enable */
16020 #define SPI_CR2_TXEIE_Pos           (7U)
16021 #define SPI_CR2_TXEIE_Msk           (0x1UL << SPI_CR2_TXEIE_Pos)                /*!< 0x00000080 */
16022 #define SPI_CR2_TXEIE               SPI_CR2_TXEIE_Msk                          /*!<Tx buffer Empty Interrupt Enable     */
16023 
16024 /********************  Bit definition for SPI_SR register  ********************/
16025 #define SPI_SR_RXNE_Pos             (0U)
16026 #define SPI_SR_RXNE_Msk             (0x1UL << SPI_SR_RXNE_Pos)                  /*!< 0x00000001 */
16027 #define SPI_SR_RXNE                 SPI_SR_RXNE_Msk                            /*!<Receive buffer Not Empty */
16028 #define SPI_SR_TXE_Pos              (1U)
16029 #define SPI_SR_TXE_Msk              (0x1UL << SPI_SR_TXE_Pos)                   /*!< 0x00000002 */
16030 #define SPI_SR_TXE                  SPI_SR_TXE_Msk                             /*!<Transmit buffer Empty    */
16031 #define SPI_SR_CHSIDE_Pos           (2U)
16032 #define SPI_SR_CHSIDE_Msk           (0x1UL << SPI_SR_CHSIDE_Pos)                /*!< 0x00000004 */
16033 #define SPI_SR_CHSIDE               SPI_SR_CHSIDE_Msk                          /*!<Channel side             */
16034 #define SPI_SR_UDR_Pos              (3U)
16035 #define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                   /*!< 0x00000008 */
16036 #define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!<Underrun flag            */
16037 #define SPI_SR_CRCERR_Pos           (4U)
16038 #define SPI_SR_CRCERR_Msk           (0x1UL << SPI_SR_CRCERR_Pos)                /*!< 0x00000010 */
16039 #define SPI_SR_CRCERR               SPI_SR_CRCERR_Msk                          /*!<CRC Error flag           */
16040 #define SPI_SR_MODF_Pos             (5U)
16041 #define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                  /*!< 0x00000020 */
16042 #define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!<Mode fault               */
16043 #define SPI_SR_OVR_Pos              (6U)
16044 #define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                   /*!< 0x00000040 */
16045 #define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!<Overrun flag             */
16046 #define SPI_SR_BSY_Pos              (7U)
16047 #define SPI_SR_BSY_Msk              (0x1UL << SPI_SR_BSY_Pos)                   /*!< 0x00000080 */
16048 #define SPI_SR_BSY                  SPI_SR_BSY_Msk                             /*!<Busy flag                */
16049 #define SPI_SR_FRE_Pos              (8U)
16050 #define SPI_SR_FRE_Msk              (0x1UL << SPI_SR_FRE_Pos)                   /*!< 0x00000100 */
16051 #define SPI_SR_FRE                  SPI_SR_FRE_Msk                             /*!<Frame format error flag  */
16052 
16053 /********************  Bit definition for SPI_DR register  ********************/
16054 #define SPI_DR_DR_Pos               (0U)
16055 #define SPI_DR_DR_Msk               (0xFFFFUL << SPI_DR_DR_Pos)                 /*!< 0x0000FFFF */
16056 #define SPI_DR_DR                   SPI_DR_DR_Msk                              /*!<Data Register           */
16057 
16058 /*******************  Bit definition for SPI_CRCPR register  ******************/
16059 #define SPI_CRCPR_CRCPOLY_Pos       (0U)
16060 #define SPI_CRCPR_CRCPOLY_Msk       (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)         /*!< 0x0000FFFF */
16061 #define SPI_CRCPR_CRCPOLY           SPI_CRCPR_CRCPOLY_Msk                      /*!<CRC polynomial register */
16062 
16063 /******************  Bit definition for SPI_RXCRCR register  ******************/
16064 #define SPI_RXCRCR_RXCRC_Pos        (0U)
16065 #define SPI_RXCRCR_RXCRC_Msk        (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)          /*!< 0x0000FFFF */
16066 #define SPI_RXCRCR_RXCRC            SPI_RXCRCR_RXCRC_Msk                       /*!<Rx CRC Register         */
16067 
16068 /******************  Bit definition for SPI_TXCRCR register  ******************/
16069 #define SPI_TXCRCR_TXCRC_Pos        (0U)
16070 #define SPI_TXCRCR_TXCRC_Msk        (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)          /*!< 0x0000FFFF */
16071 #define SPI_TXCRCR_TXCRC            SPI_TXCRCR_TXCRC_Msk                       /*!<Tx CRC Register         */
16072 
16073 /******************  Bit definition for SPI_I2SCFGR register  *****************/
16074 #define SPI_I2SCFGR_CHLEN_Pos       (0U)
16075 #define SPI_I2SCFGR_CHLEN_Msk       (0x1UL << SPI_I2SCFGR_CHLEN_Pos)            /*!< 0x00000001 */
16076 #define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */
16077 
16078 #define SPI_I2SCFGR_DATLEN_Pos      (1U)
16079 #define SPI_I2SCFGR_DATLEN_Msk      (0x3UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000006 */
16080 #define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] bits (Data length to be transferred)  */
16081 #define SPI_I2SCFGR_DATLEN_0        (0x1UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000002 */
16082 #define SPI_I2SCFGR_DATLEN_1        (0x2UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000004 */
16083 
16084 #define SPI_I2SCFGR_CKPOL_Pos       (3U)
16085 #define SPI_I2SCFGR_CKPOL_Msk       (0x1UL << SPI_I2SCFGR_CKPOL_Pos)            /*!< 0x00000008 */
16086 #define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<steady state clock polarity               */
16087 
16088 #define SPI_I2SCFGR_I2SSTD_Pos      (4U)
16089 #define SPI_I2SCFGR_I2SSTD_Msk      (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000030 */
16090 #define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] bits (I2S standard selection) */
16091 #define SPI_I2SCFGR_I2SSTD_0        (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000010 */
16092 #define SPI_I2SCFGR_I2SSTD_1        (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000020 */
16093 
16094 #define SPI_I2SCFGR_PCMSYNC_Pos     (7U)
16095 #define SPI_I2SCFGR_PCMSYNC_Msk     (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)          /*!< 0x00000080 */
16096 #define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization                 */
16097 
16098 #define SPI_I2SCFGR_I2SCFG_Pos      (8U)
16099 #define SPI_I2SCFGR_I2SCFG_Msk      (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000300 */
16100 #define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[1:0] bits (I2S configuration mode) */
16101 #define SPI_I2SCFGR_I2SCFG_0        (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000100 */
16102 #define SPI_I2SCFGR_I2SCFG_1        (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000200 */
16103 
16104 #define SPI_I2SCFGR_I2SE_Pos        (10U)
16105 #define SPI_I2SCFGR_I2SE_Msk        (0x1UL << SPI_I2SCFGR_I2SE_Pos)             /*!< 0x00000400 */
16106 #define SPI_I2SCFGR_I2SE            SPI_I2SCFGR_I2SE_Msk                       /*!<I2S Enable         */
16107 #define SPI_I2SCFGR_I2SMOD_Pos      (11U)
16108 #define SPI_I2SCFGR_I2SMOD_Msk      (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)           /*!< 0x00000800 */
16109 #define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */
16110 #define SPI_I2SCFGR_ASTRTEN_Pos     (12U)
16111 #define SPI_I2SCFGR_ASTRTEN_Msk     (0x1UL << SPI_I2SCFGR_ASTRTEN_Pos)          /*!< 0x00001000 */
16112 #define SPI_I2SCFGR_ASTRTEN         SPI_I2SCFGR_ASTRTEN_Msk                    /*!<Asynchronous start enable */
16113 
16114 /******************  Bit definition for SPI_I2SPR register  *******************/
16115 #define SPI_I2SPR_I2SDIV_Pos        (0U)
16116 #define SPI_I2SPR_I2SDIV_Msk        (0xFFUL << SPI_I2SPR_I2SDIV_Pos)            /*!< 0x000000FF */
16117 #define SPI_I2SPR_I2SDIV            SPI_I2SPR_I2SDIV_Msk                       /*!<I2S Linear prescaler         */
16118 #define SPI_I2SPR_ODD_Pos           (8U)
16119 #define SPI_I2SPR_ODD_Msk           (0x1UL << SPI_I2SPR_ODD_Pos)                /*!< 0x00000100 */
16120 #define SPI_I2SPR_ODD               SPI_I2SPR_ODD_Msk                          /*!<Odd factor for the prescaler */
16121 #define SPI_I2SPR_MCKOE_Pos         (9U)
16122 #define SPI_I2SPR_MCKOE_Msk         (0x1UL << SPI_I2SPR_MCKOE_Pos)              /*!< 0x00000200 */
16123 #define SPI_I2SPR_MCKOE             SPI_I2SPR_MCKOE_Msk                        /*!<Master Clock Output Enable   */
16124 
16125 /******************************************************************************/
16126 /*                                                                            */
16127 /*                                 SYSCFG                                     */
16128 /*                                                                            */
16129 /******************************************************************************/
16130 /******************  Bit definition for SYSCFG_MEMRMP register  ***************/
16131 #define SYSCFG_MEMRMP_MEM_MODE_Pos           (0U)
16132 #define SYSCFG_MEMRMP_MEM_MODE_Msk           (0x7UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000007 */
16133 #define SYSCFG_MEMRMP_MEM_MODE               SYSCFG_MEMRMP_MEM_MODE_Msk        /*!< SYSCFG_Memory Remap Config */
16134 #define SYSCFG_MEMRMP_MEM_MODE_0             (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
16135 #define SYSCFG_MEMRMP_MEM_MODE_1             (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
16136 #define SYSCFG_MEMRMP_MEM_MODE_2             (0x4UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000004 */
16137 #define SYSCFG_MEMRMP_UFB_MODE_Pos           (8U)
16138 #define SYSCFG_MEMRMP_UFB_MODE_Msk           (0x1UL << SYSCFG_MEMRMP_UFB_MODE_Pos) /*!< 0x00000100 */
16139 #define SYSCFG_MEMRMP_UFB_MODE               SYSCFG_MEMRMP_UFB_MODE_Msk        /*!< User Flash Bank mode    */
16140 #define SYSCFG_MEMRMP_SWP_FMC_Pos            (10U)
16141 #define SYSCFG_MEMRMP_SWP_FMC_Msk            (0x3UL << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000C00 */
16142 #define SYSCFG_MEMRMP_SWP_FMC                SYSCFG_MEMRMP_SWP_FMC_Msk         /*!< FMC memory mapping swap */
16143 #define SYSCFG_MEMRMP_SWP_FMC_0              (0x1UL << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000400 */
16144 /* Legacy Defines */
16145 #define SYSCFG_SWP_FMC                  SYSCFG_MEMRMP_SWP_FMC
16146 /******************  Bit definition for SYSCFG_PMC register  ******************/
16147 #define SYSCFG_PMC_ADCxDC2_Pos               (16U)
16148 #define SYSCFG_PMC_ADCxDC2_Msk               (0x7UL << SYSCFG_PMC_ADCxDC2_Pos)  /*!< 0x00070000 */
16149 #define SYSCFG_PMC_ADCxDC2                   SYSCFG_PMC_ADCxDC2_Msk            /*!< Refer to AN4073 on how to use this bit  */
16150 #define SYSCFG_PMC_ADC1DC2_Pos               (16U)
16151 #define SYSCFG_PMC_ADC1DC2_Msk               (0x1UL << SYSCFG_PMC_ADC1DC2_Pos)  /*!< 0x00010000 */
16152 #define SYSCFG_PMC_ADC1DC2                   SYSCFG_PMC_ADC1DC2_Msk            /*!< Refer to AN4073 on how to use this bit  */
16153 #define SYSCFG_PMC_ADC2DC2_Pos               (17U)
16154 #define SYSCFG_PMC_ADC2DC2_Msk               (0x1UL << SYSCFG_PMC_ADC2DC2_Pos)  /*!< 0x00020000 */
16155 #define SYSCFG_PMC_ADC2DC2                   SYSCFG_PMC_ADC2DC2_Msk            /*!< Refer to AN4073 on how to use this bit  */
16156 #define SYSCFG_PMC_ADC3DC2_Pos               (18U)
16157 #define SYSCFG_PMC_ADC3DC2_Msk               (0x1UL << SYSCFG_PMC_ADC3DC2_Pos)  /*!< 0x00040000 */
16158 #define SYSCFG_PMC_ADC3DC2                   SYSCFG_PMC_ADC3DC2_Msk            /*!< Refer to AN4073 on how to use this bit  */
16159 #define SYSCFG_PMC_MII_RMII_SEL_Pos          (23U)
16160 #define SYSCFG_PMC_MII_RMII_SEL_Msk          (0x1UL << SYSCFG_PMC_MII_RMII_SEL_Pos) /*!< 0x00800000 */
16161 #define SYSCFG_PMC_MII_RMII_SEL              SYSCFG_PMC_MII_RMII_SEL_Msk       /*!<Ethernet PHY interface selection */
16162 
16163 /*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
16164 #define SYSCFG_EXTICR1_EXTI0_Pos             (0U)
16165 #define SYSCFG_EXTICR1_EXTI0_Msk             (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
16166 #define SYSCFG_EXTICR1_EXTI0                 SYSCFG_EXTICR1_EXTI0_Msk          /*!<EXTI 0 configuration */
16167 #define SYSCFG_EXTICR1_EXTI1_Pos             (4U)
16168 #define SYSCFG_EXTICR1_EXTI1_Msk             (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
16169 #define SYSCFG_EXTICR1_EXTI1                 SYSCFG_EXTICR1_EXTI1_Msk          /*!<EXTI 1 configuration */
16170 #define SYSCFG_EXTICR1_EXTI2_Pos             (8U)
16171 #define SYSCFG_EXTICR1_EXTI2_Msk             (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
16172 #define SYSCFG_EXTICR1_EXTI2                 SYSCFG_EXTICR1_EXTI2_Msk          /*!<EXTI 2 configuration */
16173 #define SYSCFG_EXTICR1_EXTI3_Pos             (12U)
16174 #define SYSCFG_EXTICR1_EXTI3_Msk             (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
16175 #define SYSCFG_EXTICR1_EXTI3                 SYSCFG_EXTICR1_EXTI3_Msk          /*!<EXTI 3 configuration */
16176 /**
16177   * @brief   EXTI0 configuration
16178   */
16179 #define SYSCFG_EXTICR1_EXTI0_PA              0x0000U                           /*!<PA[0] pin */
16180 #define SYSCFG_EXTICR1_EXTI0_PB              0x0001U                           /*!<PB[0] pin */
16181 #define SYSCFG_EXTICR1_EXTI0_PC              0x0002U                           /*!<PC[0] pin */
16182 #define SYSCFG_EXTICR1_EXTI0_PD              0x0003U                           /*!<PD[0] pin */
16183 #define SYSCFG_EXTICR1_EXTI0_PE              0x0004U                           /*!<PE[0] pin */
16184 #define SYSCFG_EXTICR1_EXTI0_PF              0x0005U                           /*!<PF[0] pin */
16185 #define SYSCFG_EXTICR1_EXTI0_PG              0x0006U                           /*!<PG[0] pin */
16186 #define SYSCFG_EXTICR1_EXTI0_PH              0x0007U                           /*!<PH[0] pin */
16187 #define SYSCFG_EXTICR1_EXTI0_PI              0x0008U                           /*!<PI[0] pin */
16188 #define SYSCFG_EXTICR1_EXTI0_PJ              0x0009U                           /*!<PJ[0] pin */
16189 #define SYSCFG_EXTICR1_EXTI0_PK              0x000AU                           /*!<PK[0] pin */
16190 
16191 /**
16192   * @brief   EXTI1 configuration
16193   */
16194 #define SYSCFG_EXTICR1_EXTI1_PA              0x0000U                           /*!<PA[1] pin */
16195 #define SYSCFG_EXTICR1_EXTI1_PB              0x0010U                           /*!<PB[1] pin */
16196 #define SYSCFG_EXTICR1_EXTI1_PC              0x0020U                           /*!<PC[1] pin */
16197 #define SYSCFG_EXTICR1_EXTI1_PD              0x0030U                           /*!<PD[1] pin */
16198 #define SYSCFG_EXTICR1_EXTI1_PE              0x0040U                           /*!<PE[1] pin */
16199 #define SYSCFG_EXTICR1_EXTI1_PF              0x0050U                           /*!<PF[1] pin */
16200 #define SYSCFG_EXTICR1_EXTI1_PG              0x0060U                           /*!<PG[1] pin */
16201 #define SYSCFG_EXTICR1_EXTI1_PH              0x0070U                           /*!<PH[1] pin */
16202 #define SYSCFG_EXTICR1_EXTI1_PI              0x0080U                           /*!<PI[1] pin */
16203 #define SYSCFG_EXTICR1_EXTI1_PJ              0x0090U                           /*!<PJ[1] pin */
16204 #define SYSCFG_EXTICR1_EXTI1_PK              0x00A0U                           /*!<PK[1] pin */
16205 
16206 /**
16207   * @brief   EXTI2 configuration
16208   */
16209 #define SYSCFG_EXTICR1_EXTI2_PA              0x0000U                           /*!<PA[2] pin */
16210 #define SYSCFG_EXTICR1_EXTI2_PB              0x0100U                           /*!<PB[2] pin */
16211 #define SYSCFG_EXTICR1_EXTI2_PC              0x0200U                           /*!<PC[2] pin */
16212 #define SYSCFG_EXTICR1_EXTI2_PD              0x0300U                           /*!<PD[2] pin */
16213 #define SYSCFG_EXTICR1_EXTI2_PE              0x0400U                           /*!<PE[2] pin */
16214 #define SYSCFG_EXTICR1_EXTI2_PF              0x0500U                           /*!<PF[2] pin */
16215 #define SYSCFG_EXTICR1_EXTI2_PG              0x0600U                           /*!<PG[2] pin */
16216 #define SYSCFG_EXTICR1_EXTI2_PH              0x0700U                           /*!<PH[2] pin */
16217 #define SYSCFG_EXTICR1_EXTI2_PI              0x0800U                           /*!<PI[2] pin */
16218 #define SYSCFG_EXTICR1_EXTI2_PJ              0x0900U                           /*!<PJ[2] pin */
16219 #define SYSCFG_EXTICR1_EXTI2_PK              0x0A00U                           /*!<PK[2] pin */
16220 
16221 /**
16222   * @brief   EXTI3 configuration
16223   */
16224 #define SYSCFG_EXTICR1_EXTI3_PA              0x0000U                           /*!<PA[3] pin */
16225 #define SYSCFG_EXTICR1_EXTI3_PB              0x1000U                           /*!<PB[3] pin */
16226 #define SYSCFG_EXTICR1_EXTI3_PC              0x2000U                           /*!<PC[3] pin */
16227 #define SYSCFG_EXTICR1_EXTI3_PD              0x3000U                           /*!<PD[3] pin */
16228 #define SYSCFG_EXTICR1_EXTI3_PE              0x4000U                           /*!<PE[3] pin */
16229 #define SYSCFG_EXTICR1_EXTI3_PF              0x5000U                           /*!<PF[3] pin */
16230 #define SYSCFG_EXTICR1_EXTI3_PG              0x6000U                           /*!<PG[3] pin */
16231 #define SYSCFG_EXTICR1_EXTI3_PH              0x7000U                           /*!<PH[3] pin */
16232 #define SYSCFG_EXTICR1_EXTI3_PI              0x8000U                           /*!<PI[3] pin */
16233 #define SYSCFG_EXTICR1_EXTI3_PJ              0x9000U                           /*!<PJ[3] pin */
16234 #define SYSCFG_EXTICR1_EXTI3_PK              0xA000U                           /*!<PK[3] pin */
16235 
16236 /*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
16237 #define SYSCFG_EXTICR2_EXTI4_Pos             (0U)
16238 #define SYSCFG_EXTICR2_EXTI4_Msk             (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
16239 #define SYSCFG_EXTICR2_EXTI4                 SYSCFG_EXTICR2_EXTI4_Msk          /*!<EXTI 4 configuration */
16240 #define SYSCFG_EXTICR2_EXTI5_Pos             (4U)
16241 #define SYSCFG_EXTICR2_EXTI5_Msk             (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
16242 #define SYSCFG_EXTICR2_EXTI5                 SYSCFG_EXTICR2_EXTI5_Msk          /*!<EXTI 5 configuration */
16243 #define SYSCFG_EXTICR2_EXTI6_Pos             (8U)
16244 #define SYSCFG_EXTICR2_EXTI6_Msk             (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
16245 #define SYSCFG_EXTICR2_EXTI6                 SYSCFG_EXTICR2_EXTI6_Msk          /*!<EXTI 6 configuration */
16246 #define SYSCFG_EXTICR2_EXTI7_Pos             (12U)
16247 #define SYSCFG_EXTICR2_EXTI7_Msk             (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
16248 #define SYSCFG_EXTICR2_EXTI7                 SYSCFG_EXTICR2_EXTI7_Msk          /*!<EXTI 7 configuration */
16249 
16250 /**
16251   * @brief   EXTI4 configuration
16252   */
16253 #define SYSCFG_EXTICR2_EXTI4_PA              0x0000U                           /*!<PA[4] pin */
16254 #define SYSCFG_EXTICR2_EXTI4_PB              0x0001U                           /*!<PB[4] pin */
16255 #define SYSCFG_EXTICR2_EXTI4_PC              0x0002U                           /*!<PC[4] pin */
16256 #define SYSCFG_EXTICR2_EXTI4_PD              0x0003U                           /*!<PD[4] pin */
16257 #define SYSCFG_EXTICR2_EXTI4_PE              0x0004U                           /*!<PE[4] pin */
16258 #define SYSCFG_EXTICR2_EXTI4_PF              0x0005U                           /*!<PF[4] pin */
16259 #define SYSCFG_EXTICR2_EXTI4_PG              0x0006U                           /*!<PG[4] pin */
16260 #define SYSCFG_EXTICR2_EXTI4_PH              0x0007U                           /*!<PH[4] pin */
16261 #define SYSCFG_EXTICR2_EXTI4_PI              0x0008U                           /*!<PI[4] pin */
16262 #define SYSCFG_EXTICR2_EXTI4_PJ              0x0009U                           /*!<PJ[4] pin */
16263 #define SYSCFG_EXTICR2_EXTI4_PK              0x000AU                           /*!<PK[4] pin */
16264 
16265 /**
16266   * @brief   EXTI5 configuration
16267   */
16268 #define SYSCFG_EXTICR2_EXTI5_PA              0x0000U                           /*!<PA[5] pin */
16269 #define SYSCFG_EXTICR2_EXTI5_PB              0x0010U                           /*!<PB[5] pin */
16270 #define SYSCFG_EXTICR2_EXTI5_PC              0x0020U                           /*!<PC[5] pin */
16271 #define SYSCFG_EXTICR2_EXTI5_PD              0x0030U                           /*!<PD[5] pin */
16272 #define SYSCFG_EXTICR2_EXTI5_PE              0x0040U                           /*!<PE[5] pin */
16273 #define SYSCFG_EXTICR2_EXTI5_PF              0x0050U                           /*!<PF[5] pin */
16274 #define SYSCFG_EXTICR2_EXTI5_PG              0x0060U                           /*!<PG[5] pin */
16275 #define SYSCFG_EXTICR2_EXTI5_PH              0x0070U                           /*!<PH[5] pin */
16276 #define SYSCFG_EXTICR2_EXTI5_PI              0x0080U                           /*!<PI[5] pin */
16277 #define SYSCFG_EXTICR2_EXTI5_PJ              0x0090U                           /*!<PJ[5] pin */
16278 #define SYSCFG_EXTICR2_EXTI5_PK              0x00A0U                           /*!<PK[5] pin */
16279 
16280 /**
16281   * @brief   EXTI6 configuration
16282   */
16283 #define SYSCFG_EXTICR2_EXTI6_PA              0x0000U                           /*!<PA[6] pin */
16284 #define SYSCFG_EXTICR2_EXTI6_PB              0x0100U                           /*!<PB[6] pin */
16285 #define SYSCFG_EXTICR2_EXTI6_PC              0x0200U                           /*!<PC[6] pin */
16286 #define SYSCFG_EXTICR2_EXTI6_PD              0x0300U                           /*!<PD[6] pin */
16287 #define SYSCFG_EXTICR2_EXTI6_PE              0x0400U                           /*!<PE[6] pin */
16288 #define SYSCFG_EXTICR2_EXTI6_PF              0x0500U                           /*!<PF[6] pin */
16289 #define SYSCFG_EXTICR2_EXTI6_PG              0x0600U                           /*!<PG[6] pin */
16290 #define SYSCFG_EXTICR2_EXTI6_PH              0x0700U                           /*!<PH[6] pin */
16291 #define SYSCFG_EXTICR2_EXTI6_PI              0x0800U                           /*!<PI[6] pin */
16292 #define SYSCFG_EXTICR2_EXTI6_PJ              0x0900U                           /*!<PJ[6] pin */
16293 #define SYSCFG_EXTICR2_EXTI6_PK              0x0A00U                           /*!<PK[6] pin */
16294 
16295 /**
16296   * @brief   EXTI7 configuration
16297   */
16298 #define SYSCFG_EXTICR2_EXTI7_PA              0x0000U                           /*!<PA[7] pin */
16299 #define SYSCFG_EXTICR2_EXTI7_PB              0x1000U                           /*!<PB[7] pin */
16300 #define SYSCFG_EXTICR2_EXTI7_PC              0x2000U                           /*!<PC[7] pin */
16301 #define SYSCFG_EXTICR2_EXTI7_PD              0x3000U                           /*!<PD[7] pin */
16302 #define SYSCFG_EXTICR2_EXTI7_PE              0x4000U                           /*!<PE[7] pin */
16303 #define SYSCFG_EXTICR2_EXTI7_PF              0x5000U                           /*!<PF[7] pin */
16304 #define SYSCFG_EXTICR2_EXTI7_PG              0x6000U                           /*!<PG[7] pin */
16305 #define SYSCFG_EXTICR2_EXTI7_PH              0x7000U                           /*!<PH[7] pin */
16306 #define SYSCFG_EXTICR2_EXTI7_PI              0x8000U                           /*!<PI[7] pin */
16307 #define SYSCFG_EXTICR2_EXTI7_PJ              0x9000U                           /*!<PJ[7] pin */
16308 #define SYSCFG_EXTICR2_EXTI7_PK              0xA000U                           /*!<PK[7] pin */
16309 
16310 /*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
16311 #define SYSCFG_EXTICR3_EXTI8_Pos             (0U)
16312 #define SYSCFG_EXTICR3_EXTI8_Msk             (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
16313 #define SYSCFG_EXTICR3_EXTI8                 SYSCFG_EXTICR3_EXTI8_Msk          /*!<EXTI 8 configuration */
16314 #define SYSCFG_EXTICR3_EXTI9_Pos             (4U)
16315 #define SYSCFG_EXTICR3_EXTI9_Msk             (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
16316 #define SYSCFG_EXTICR3_EXTI9                 SYSCFG_EXTICR3_EXTI9_Msk          /*!<EXTI 9 configuration */
16317 #define SYSCFG_EXTICR3_EXTI10_Pos            (8U)
16318 #define SYSCFG_EXTICR3_EXTI10_Msk            (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
16319 #define SYSCFG_EXTICR3_EXTI10                SYSCFG_EXTICR3_EXTI10_Msk         /*!<EXTI 10 configuration */
16320 #define SYSCFG_EXTICR3_EXTI11_Pos            (12U)
16321 #define SYSCFG_EXTICR3_EXTI11_Msk            (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
16322 #define SYSCFG_EXTICR3_EXTI11                SYSCFG_EXTICR3_EXTI11_Msk         /*!<EXTI 11 configuration */
16323 
16324 /**
16325   * @brief   EXTI8 configuration
16326   */
16327 #define SYSCFG_EXTICR3_EXTI8_PA              0x0000U                           /*!<PA[8] pin */
16328 #define SYSCFG_EXTICR3_EXTI8_PB              0x0001U                           /*!<PB[8] pin */
16329 #define SYSCFG_EXTICR3_EXTI8_PC              0x0002U                           /*!<PC[8] pin */
16330 #define SYSCFG_EXTICR3_EXTI8_PD              0x0003U                           /*!<PD[8] pin */
16331 #define SYSCFG_EXTICR3_EXTI8_PE              0x0004U                           /*!<PE[8] pin */
16332 #define SYSCFG_EXTICR3_EXTI8_PF              0x0005U                           /*!<PF[8] pin */
16333 #define SYSCFG_EXTICR3_EXTI8_PG              0x0006U                           /*!<PG[8] pin */
16334 #define SYSCFG_EXTICR3_EXTI8_PH              0x0007U                           /*!<PH[8] pin */
16335 #define SYSCFG_EXTICR3_EXTI8_PI              0x0008U                           /*!<PI[8] pin */
16336 #define SYSCFG_EXTICR3_EXTI8_PJ              0x0009U                           /*!<PJ[8] pin */
16337 
16338 /**
16339   * @brief   EXTI9 configuration
16340   */
16341 #define SYSCFG_EXTICR3_EXTI9_PA              0x0000U                           /*!<PA[9] pin */
16342 #define SYSCFG_EXTICR3_EXTI9_PB              0x0010U                           /*!<PB[9] pin */
16343 #define SYSCFG_EXTICR3_EXTI9_PC              0x0020U                           /*!<PC[9] pin */
16344 #define SYSCFG_EXTICR3_EXTI9_PD              0x0030U                           /*!<PD[9] pin */
16345 #define SYSCFG_EXTICR3_EXTI9_PE              0x0040U                           /*!<PE[9] pin */
16346 #define SYSCFG_EXTICR3_EXTI9_PF              0x0050U                           /*!<PF[9] pin */
16347 #define SYSCFG_EXTICR3_EXTI9_PG              0x0060U                           /*!<PG[9] pin */
16348 #define SYSCFG_EXTICR3_EXTI9_PH              0x0070U                           /*!<PH[9] pin */
16349 #define SYSCFG_EXTICR3_EXTI9_PI              0x0080U                           /*!<PI[9] pin */
16350 #define SYSCFG_EXTICR3_EXTI9_PJ              0x0090U                           /*!<PJ[9] pin */
16351 
16352 /**
16353   * @brief   EXTI10 configuration
16354   */
16355 #define SYSCFG_EXTICR3_EXTI10_PA             0x0000U                           /*!<PA[10] pin */
16356 #define SYSCFG_EXTICR3_EXTI10_PB             0x0100U                           /*!<PB[10] pin */
16357 #define SYSCFG_EXTICR3_EXTI10_PC             0x0200U                           /*!<PC[10] pin */
16358 #define SYSCFG_EXTICR3_EXTI10_PD             0x0300U                           /*!<PD[10] pin */
16359 #define SYSCFG_EXTICR3_EXTI10_PE             0x0400U                           /*!<PE[10] pin */
16360 #define SYSCFG_EXTICR3_EXTI10_PF             0x0500U                           /*!<PF[10] pin */
16361 #define SYSCFG_EXTICR3_EXTI10_PG             0x0600U                           /*!<PG[10] pin */
16362 #define SYSCFG_EXTICR3_EXTI10_PH             0x0700U                           /*!<PH[10] pin */
16363 #define SYSCFG_EXTICR3_EXTI10_PI             0x0800U                           /*!<PI[10] pin */
16364 #define SYSCFG_EXTICR3_EXTI10_PJ             0x0900U                           /*!<PJ[10] pin */
16365 
16366 /**
16367   * @brief   EXTI11 configuration
16368   */
16369 #define SYSCFG_EXTICR3_EXTI11_PA             0x0000U                           /*!<PA[11] pin */
16370 #define SYSCFG_EXTICR3_EXTI11_PB             0x1000U                           /*!<PB[11] pin */
16371 #define SYSCFG_EXTICR3_EXTI11_PC             0x2000U                           /*!<PC[11] pin */
16372 #define SYSCFG_EXTICR3_EXTI11_PD             0x3000U                           /*!<PD[11] pin */
16373 #define SYSCFG_EXTICR3_EXTI11_PE             0x4000U                           /*!<PE[11] pin */
16374 #define SYSCFG_EXTICR3_EXTI11_PF             0x5000U                           /*!<PF[11] pin */
16375 #define SYSCFG_EXTICR3_EXTI11_PG             0x6000U                           /*!<PG[11] pin */
16376 #define SYSCFG_EXTICR3_EXTI11_PH             0x7000U                           /*!<PH[11] pin */
16377 #define SYSCFG_EXTICR3_EXTI11_PI             0x8000U                           /*!<PI[11] pin */
16378 #define SYSCFG_EXTICR3_EXTI11_PJ             0x9000U                           /*!<PJ[11] pin */
16379 
16380 
16381 /*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
16382 #define SYSCFG_EXTICR4_EXTI12_Pos            (0U)
16383 #define SYSCFG_EXTICR4_EXTI12_Msk            (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
16384 #define SYSCFG_EXTICR4_EXTI12                SYSCFG_EXTICR4_EXTI12_Msk         /*!<EXTI 12 configuration */
16385 #define SYSCFG_EXTICR4_EXTI13_Pos            (4U)
16386 #define SYSCFG_EXTICR4_EXTI13_Msk            (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
16387 #define SYSCFG_EXTICR4_EXTI13                SYSCFG_EXTICR4_EXTI13_Msk         /*!<EXTI 13 configuration */
16388 #define SYSCFG_EXTICR4_EXTI14_Pos            (8U)
16389 #define SYSCFG_EXTICR4_EXTI14_Msk            (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
16390 #define SYSCFG_EXTICR4_EXTI14                SYSCFG_EXTICR4_EXTI14_Msk         /*!<EXTI 14 configuration */
16391 #define SYSCFG_EXTICR4_EXTI15_Pos            (12U)
16392 #define SYSCFG_EXTICR4_EXTI15_Msk            (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
16393 #define SYSCFG_EXTICR4_EXTI15                SYSCFG_EXTICR4_EXTI15_Msk         /*!<EXTI 15 configuration */
16394 
16395 /**
16396   * @brief   EXTI12 configuration
16397   */
16398 #define SYSCFG_EXTICR4_EXTI12_PA             0x0000U                           /*!<PA[12] pin */
16399 #define SYSCFG_EXTICR4_EXTI12_PB             0x0001U                           /*!<PB[12] pin */
16400 #define SYSCFG_EXTICR4_EXTI12_PC             0x0002U                           /*!<PC[12] pin */
16401 #define SYSCFG_EXTICR4_EXTI12_PD             0x0003U                           /*!<PD[12] pin */
16402 #define SYSCFG_EXTICR4_EXTI12_PE             0x0004U                           /*!<PE[12] pin */
16403 #define SYSCFG_EXTICR4_EXTI12_PF             0x0005U                           /*!<PF[12] pin */
16404 #define SYSCFG_EXTICR4_EXTI12_PG             0x0006U                           /*!<PG[12] pin */
16405 #define SYSCFG_EXTICR4_EXTI12_PH             0x0007U                           /*!<PH[12] pin */
16406 #define SYSCFG_EXTICR4_EXTI12_PI             0x0008U                           /*!<PI[12] pin */
16407 #define SYSCFG_EXTICR4_EXTI12_PJ             0x0009U                           /*!<PJ[12] pin */
16408 
16409 /**
16410   * @brief   EXTI13 configuration
16411   */
16412 #define SYSCFG_EXTICR4_EXTI13_PA             0x0000U                           /*!<PA[13] pin */
16413 #define SYSCFG_EXTICR4_EXTI13_PB             0x0010U                           /*!<PB[13] pin */
16414 #define SYSCFG_EXTICR4_EXTI13_PC             0x0020U                           /*!<PC[13] pin */
16415 #define SYSCFG_EXTICR4_EXTI13_PD             0x0030U                           /*!<PD[13] pin */
16416 #define SYSCFG_EXTICR4_EXTI13_PE             0x0040U                           /*!<PE[13] pin */
16417 #define SYSCFG_EXTICR4_EXTI13_PF             0x0050U                           /*!<PF[13] pin */
16418 #define SYSCFG_EXTICR4_EXTI13_PG             0x0060U                           /*!<PG[13] pin */
16419 #define SYSCFG_EXTICR4_EXTI13_PH             0x0070U                           /*!<PH[13] pin */
16420 #define SYSCFG_EXTICR4_EXTI13_PI             0x0008U                           /*!<PI[13] pin */
16421 #define SYSCFG_EXTICR4_EXTI13_PJ             0x0009U                           /*!<PJ[13] pin */
16422 
16423 /**
16424   * @brief   EXTI14 configuration
16425   */
16426 #define SYSCFG_EXTICR4_EXTI14_PA             0x0000U                           /*!<PA[14] pin */
16427 #define SYSCFG_EXTICR4_EXTI14_PB             0x0100U                           /*!<PB[14] pin */
16428 #define SYSCFG_EXTICR4_EXTI14_PC             0x0200U                           /*!<PC[14] pin */
16429 #define SYSCFG_EXTICR4_EXTI14_PD             0x0300U                           /*!<PD[14] pin */
16430 #define SYSCFG_EXTICR4_EXTI14_PE             0x0400U                           /*!<PE[14] pin */
16431 #define SYSCFG_EXTICR4_EXTI14_PF             0x0500U                           /*!<PF[14] pin */
16432 #define SYSCFG_EXTICR4_EXTI14_PG             0x0600U                           /*!<PG[14] pin */
16433 #define SYSCFG_EXTICR4_EXTI14_PH             0x0700U                           /*!<PH[14] pin */
16434 #define SYSCFG_EXTICR4_EXTI14_PI             0x0800U                           /*!<PI[14] pin */
16435 #define SYSCFG_EXTICR4_EXTI14_PJ             0x0900U                           /*!<PJ[14] pin */
16436 
16437 /**
16438   * @brief   EXTI15 configuration
16439   */
16440 #define SYSCFG_EXTICR4_EXTI15_PA             0x0000U                           /*!<PA[15] pin */
16441 #define SYSCFG_EXTICR4_EXTI15_PB             0x1000U                           /*!<PB[15] pin */
16442 #define SYSCFG_EXTICR4_EXTI15_PC             0x2000U                           /*!<PC[15] pin */
16443 #define SYSCFG_EXTICR4_EXTI15_PD             0x3000U                           /*!<PD[15] pin */
16444 #define SYSCFG_EXTICR4_EXTI15_PE             0x4000U                           /*!<PE[15] pin */
16445 #define SYSCFG_EXTICR4_EXTI15_PF             0x5000U                           /*!<PF[15] pin */
16446 #define SYSCFG_EXTICR4_EXTI15_PG             0x6000U                           /*!<PG[15] pin */
16447 #define SYSCFG_EXTICR4_EXTI15_PH             0x7000U                           /*!<PH[15] pin */
16448 #define SYSCFG_EXTICR4_EXTI15_PI             0x8000U                           /*!<PI[15] pin */
16449 #define SYSCFG_EXTICR4_EXTI15_PJ             0x9000U                           /*!<PJ[15] pin */
16450 
16451 /******************  Bit definition for SYSCFG_CMPCR register  ****************/
16452 #define SYSCFG_CMPCR_CMP_PD_Pos              (0U)
16453 #define SYSCFG_CMPCR_CMP_PD_Msk              (0x1UL << SYSCFG_CMPCR_CMP_PD_Pos) /*!< 0x00000001 */
16454 #define SYSCFG_CMPCR_CMP_PD                  SYSCFG_CMPCR_CMP_PD_Msk           /*!<Compensation cell ready flag */
16455 #define SYSCFG_CMPCR_READY_Pos               (8U)
16456 #define SYSCFG_CMPCR_READY_Msk               (0x1UL << SYSCFG_CMPCR_READY_Pos)  /*!< 0x00000100 */
16457 #define SYSCFG_CMPCR_READY                   SYSCFG_CMPCR_READY_Msk            /*!<Compensation cell power-down */
16458 
16459 /******************************************************************************/
16460 /*                                                                            */
16461 /*                                    TIM                                     */
16462 /*                                                                            */
16463 /******************************************************************************/
16464 /*******************  Bit definition for TIM_CR1 register  ********************/
16465 #define TIM_CR1_CEN_Pos           (0U)
16466 #define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                    /*!< 0x00000001 */
16467 #define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable        */
16468 #define TIM_CR1_UDIS_Pos          (1U)
16469 #define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                   /*!< 0x00000002 */
16470 #define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable        */
16471 #define TIM_CR1_URS_Pos           (2U)
16472 #define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                    /*!< 0x00000004 */
16473 #define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
16474 #define TIM_CR1_OPM_Pos           (3U)
16475 #define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                    /*!< 0x00000008 */
16476 #define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode        */
16477 #define TIM_CR1_DIR_Pos           (4U)
16478 #define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                    /*!< 0x00000010 */
16479 #define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction             */
16480 
16481 #define TIM_CR1_CMS_Pos           (5U)
16482 #define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000060 */
16483 #define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
16484 #define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                    /*!< 0x0020 */
16485 #define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                    /*!< 0x0040 */
16486 
16487 #define TIM_CR1_ARPE_Pos          (7U)
16488 #define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                   /*!< 0x00000080 */
16489 #define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable     */
16490 
16491 #define TIM_CR1_CKD_Pos           (8U)
16492 #define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000300 */
16493 #define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
16494 #define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                    /*!< 0x0100 */
16495 #define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                    /*!< 0x0200 */
16496 
16497 /*******************  Bit definition for TIM_CR2 register  ********************/
16498 #define TIM_CR2_CCPC_Pos          (0U)
16499 #define TIM_CR2_CCPC_Msk          (0x1UL << TIM_CR2_CCPC_Pos)                   /*!< 0x00000001 */
16500 #define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control        */
16501 #define TIM_CR2_CCUS_Pos          (2U)
16502 #define TIM_CR2_CCUS_Msk          (0x1UL << TIM_CR2_CCUS_Pos)                   /*!< 0x00000004 */
16503 #define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */
16504 #define TIM_CR2_CCDS_Pos          (3U)
16505 #define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                   /*!< 0x00000008 */
16506 #define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection            */
16507 
16508 #define TIM_CR2_MMS_Pos           (4U)
16509 #define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000070 */
16510 #define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */
16511 #define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                    /*!< 0x0010 */
16512 #define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                    /*!< 0x0020 */
16513 #define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                    /*!< 0x0040 */
16514 
16515 #define TIM_CR2_TI1S_Pos          (7U)
16516 #define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                   /*!< 0x00000080 */
16517 #define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
16518 #define TIM_CR2_OIS1_Pos          (8U)
16519 #define TIM_CR2_OIS1_Msk          (0x1UL << TIM_CR2_OIS1_Pos)                   /*!< 0x00000100 */
16520 #define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output)  */
16521 #define TIM_CR2_OIS1N_Pos         (9U)
16522 #define TIM_CR2_OIS1N_Msk         (0x1UL << TIM_CR2_OIS1N_Pos)                  /*!< 0x00000200 */
16523 #define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */
16524 #define TIM_CR2_OIS2_Pos          (10U)
16525 #define TIM_CR2_OIS2_Msk          (0x1UL << TIM_CR2_OIS2_Pos)                   /*!< 0x00000400 */
16526 #define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output)  */
16527 #define TIM_CR2_OIS2N_Pos         (11U)
16528 #define TIM_CR2_OIS2N_Msk         (0x1UL << TIM_CR2_OIS2N_Pos)                  /*!< 0x00000800 */
16529 #define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */
16530 #define TIM_CR2_OIS3_Pos          (12U)
16531 #define TIM_CR2_OIS3_Msk          (0x1UL << TIM_CR2_OIS3_Pos)                   /*!< 0x00001000 */
16532 #define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output)  */
16533 #define TIM_CR2_OIS3N_Pos         (13U)
16534 #define TIM_CR2_OIS3N_Msk         (0x1UL << TIM_CR2_OIS3N_Pos)                  /*!< 0x00002000 */
16535 #define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */
16536 #define TIM_CR2_OIS4_Pos          (14U)
16537 #define TIM_CR2_OIS4_Msk          (0x1UL << TIM_CR2_OIS4_Pos)                   /*!< 0x00004000 */
16538 #define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output)  */
16539 
16540 /*******************  Bit definition for TIM_SMCR register  *******************/
16541 #define TIM_SMCR_SMS_Pos          (0U)
16542 #define TIM_SMCR_SMS_Msk          (0x7UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000007 */
16543 #define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection)    */
16544 #define TIM_SMCR_SMS_0            (0x1UL << TIM_SMCR_SMS_Pos)                   /*!< 0x0001 */
16545 #define TIM_SMCR_SMS_1            (0x2UL << TIM_SMCR_SMS_Pos)                   /*!< 0x0002 */
16546 #define TIM_SMCR_SMS_2            (0x4UL << TIM_SMCR_SMS_Pos)                   /*!< 0x0004 */
16547 
16548 #define TIM_SMCR_TS_Pos           (4U)
16549 #define TIM_SMCR_TS_Msk           (0x7UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000070 */
16550 #define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection)        */
16551 #define TIM_SMCR_TS_0             (0x1UL << TIM_SMCR_TS_Pos)                    /*!< 0x0010 */
16552 #define TIM_SMCR_TS_1             (0x2UL << TIM_SMCR_TS_Pos)                    /*!< 0x0020 */
16553 #define TIM_SMCR_TS_2             (0x4UL << TIM_SMCR_TS_Pos)                    /*!< 0x0040 */
16554 
16555 #define TIM_SMCR_MSM_Pos          (7U)
16556 #define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                   /*!< 0x00000080 */
16557 #define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode                       */
16558 
16559 #define TIM_SMCR_ETF_Pos          (8U)
16560 #define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000F00 */
16561 #define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
16562 #define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                   /*!< 0x0100 */
16563 #define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                   /*!< 0x0200 */
16564 #define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                   /*!< 0x0400 */
16565 #define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                   /*!< 0x0800 */
16566 
16567 #define TIM_SMCR_ETPS_Pos         (12U)
16568 #define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00003000 */
16569 #define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
16570 #define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x1000 */
16571 #define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x2000 */
16572 
16573 #define TIM_SMCR_ECE_Pos          (14U)
16574 #define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                   /*!< 0x00004000 */
16575 #define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable     */
16576 #define TIM_SMCR_ETP_Pos          (15U)
16577 #define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                   /*!< 0x00008000 */
16578 #define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
16579 
16580 /*******************  Bit definition for TIM_DIER register  *******************/
16581 #define TIM_DIER_UIE_Pos          (0U)
16582 #define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                   /*!< 0x00000001 */
16583 #define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
16584 #define TIM_DIER_CC1IE_Pos        (1U)
16585 #define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                 /*!< 0x00000002 */
16586 #define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable   */
16587 #define TIM_DIER_CC2IE_Pos        (2U)
16588 #define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                 /*!< 0x00000004 */
16589 #define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable   */
16590 #define TIM_DIER_CC3IE_Pos        (3U)
16591 #define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                 /*!< 0x00000008 */
16592 #define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable   */
16593 #define TIM_DIER_CC4IE_Pos        (4U)
16594 #define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                 /*!< 0x00000010 */
16595 #define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable   */
16596 #define TIM_DIER_COMIE_Pos        (5U)
16597 #define TIM_DIER_COMIE_Msk        (0x1UL << TIM_DIER_COMIE_Pos)                 /*!< 0x00000020 */
16598 #define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable                 */
16599 #define TIM_DIER_TIE_Pos          (6U)
16600 #define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                   /*!< 0x00000040 */
16601 #define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable             */
16602 #define TIM_DIER_BIE_Pos          (7U)
16603 #define TIM_DIER_BIE_Msk          (0x1UL << TIM_DIER_BIE_Pos)                   /*!< 0x00000080 */
16604 #define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable               */
16605 #define TIM_DIER_UDE_Pos          (8U)
16606 #define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                   /*!< 0x00000100 */
16607 #define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable            */
16608 #define TIM_DIER_CC1DE_Pos        (9U)
16609 #define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                 /*!< 0x00000200 */
16610 #define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
16611 #define TIM_DIER_CC2DE_Pos        (10U)
16612 #define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                 /*!< 0x00000400 */
16613 #define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
16614 #define TIM_DIER_CC3DE_Pos        (11U)
16615 #define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                 /*!< 0x00000800 */
16616 #define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
16617 #define TIM_DIER_CC4DE_Pos        (12U)
16618 #define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                 /*!< 0x00001000 */
16619 #define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
16620 #define TIM_DIER_COMDE_Pos        (13U)
16621 #define TIM_DIER_COMDE_Msk        (0x1UL << TIM_DIER_COMDE_Pos)                 /*!< 0x00002000 */
16622 #define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable               */
16623 #define TIM_DIER_TDE_Pos          (14U)
16624 #define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                   /*!< 0x00004000 */
16625 #define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable           */
16626 
16627 /********************  Bit definition for TIM_SR register  ********************/
16628 #define TIM_SR_UIF_Pos            (0U)
16629 #define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                     /*!< 0x00000001 */
16630 #define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag              */
16631 #define TIM_SR_CC1IF_Pos          (1U)
16632 #define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                   /*!< 0x00000002 */
16633 #define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag   */
16634 #define TIM_SR_CC2IF_Pos          (2U)
16635 #define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                   /*!< 0x00000004 */
16636 #define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag   */
16637 #define TIM_SR_CC3IF_Pos          (3U)
16638 #define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                   /*!< 0x00000008 */
16639 #define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag   */
16640 #define TIM_SR_CC4IF_Pos          (4U)
16641 #define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                   /*!< 0x00000010 */
16642 #define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag   */
16643 #define TIM_SR_COMIF_Pos          (5U)
16644 #define TIM_SR_COMIF_Msk          (0x1UL << TIM_SR_COMIF_Pos)                   /*!< 0x00000020 */
16645 #define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag                 */
16646 #define TIM_SR_TIF_Pos            (6U)
16647 #define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                     /*!< 0x00000040 */
16648 #define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag             */
16649 #define TIM_SR_BIF_Pos            (7U)
16650 #define TIM_SR_BIF_Msk            (0x1UL << TIM_SR_BIF_Pos)                     /*!< 0x00000080 */
16651 #define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag               */
16652 #define TIM_SR_CC1OF_Pos          (9U)
16653 #define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                   /*!< 0x00000200 */
16654 #define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
16655 #define TIM_SR_CC2OF_Pos          (10U)
16656 #define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                   /*!< 0x00000400 */
16657 #define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
16658 #define TIM_SR_CC3OF_Pos          (11U)
16659 #define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                   /*!< 0x00000800 */
16660 #define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
16661 #define TIM_SR_CC4OF_Pos          (12U)
16662 #define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                   /*!< 0x00001000 */
16663 #define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
16664 
16665 /*******************  Bit definition for TIM_EGR register  ********************/
16666 #define TIM_EGR_UG_Pos            (0U)
16667 #define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                     /*!< 0x00000001 */
16668 #define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation                         */
16669 #define TIM_EGR_CC1G_Pos          (1U)
16670 #define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                   /*!< 0x00000002 */
16671 #define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation              */
16672 #define TIM_EGR_CC2G_Pos          (2U)
16673 #define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                   /*!< 0x00000004 */
16674 #define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation              */
16675 #define TIM_EGR_CC3G_Pos          (3U)
16676 #define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                   /*!< 0x00000008 */
16677 #define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation              */
16678 #define TIM_EGR_CC4G_Pos          (4U)
16679 #define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                   /*!< 0x00000010 */
16680 #define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation              */
16681 #define TIM_EGR_COMG_Pos          (5U)
16682 #define TIM_EGR_COMG_Msk          (0x1UL << TIM_EGR_COMG_Pos)                   /*!< 0x00000020 */
16683 #define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */
16684 #define TIM_EGR_TG_Pos            (6U)
16685 #define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                     /*!< 0x00000040 */
16686 #define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation                        */
16687 #define TIM_EGR_BG_Pos            (7U)
16688 #define TIM_EGR_BG_Msk            (0x1UL << TIM_EGR_BG_Pos)                     /*!< 0x00000080 */
16689 #define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation                          */
16690 
16691 /******************  Bit definition for TIM_CCMR1 register  *******************/
16692 #define TIM_CCMR1_CC1S_Pos        (0U)
16693 #define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000003 */
16694 #define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
16695 #define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x0001 */
16696 #define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x0002 */
16697 
16698 #define TIM_CCMR1_OC1FE_Pos       (2U)
16699 #define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)                /*!< 0x00000004 */
16700 #define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable                 */
16701 #define TIM_CCMR1_OC1PE_Pos       (3U)
16702 #define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)                /*!< 0x00000008 */
16703 #define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable              */
16704 
16705 #define TIM_CCMR1_OC1M_Pos        (4U)
16706 #define TIM_CCMR1_OC1M_Msk        (0x7UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000070 */
16707 #define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
16708 #define TIM_CCMR1_OC1M_0          (0x1UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x0010 */
16709 #define TIM_CCMR1_OC1M_1          (0x2UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x0020 */
16710 #define TIM_CCMR1_OC1M_2          (0x4UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x0040 */
16711 
16712 #define TIM_CCMR1_OC1CE_Pos       (7U)
16713 #define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)                /*!< 0x00000080 */
16714 #define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable                 */
16715 
16716 #define TIM_CCMR1_CC2S_Pos        (8U)
16717 #define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000300 */
16718 #define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
16719 #define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x0100 */
16720 #define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x0200 */
16721 
16722 #define TIM_CCMR1_OC2FE_Pos       (10U)
16723 #define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)                /*!< 0x00000400 */
16724 #define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable                 */
16725 #define TIM_CCMR1_OC2PE_Pos       (11U)
16726 #define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)                /*!< 0x00000800 */
16727 #define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable              */
16728 
16729 #define TIM_CCMR1_OC2M_Pos        (12U)
16730 #define TIM_CCMR1_OC2M_Msk        (0x7UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00007000 */
16731 #define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */
16732 #define TIM_CCMR1_OC2M_0          (0x1UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x1000 */
16733 #define TIM_CCMR1_OC2M_1          (0x2UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x2000 */
16734 #define TIM_CCMR1_OC2M_2          (0x4UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x4000 */
16735 
16736 #define TIM_CCMR1_OC2CE_Pos       (15U)
16737 #define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)                /*!< 0x00008000 */
16738 #define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
16739 
16740 /*----------------------------------------------------------------------------*/
16741 
16742 #define TIM_CCMR1_IC1PSC_Pos      (2U)
16743 #define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0000000C */
16744 #define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
16745 #define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0004 */
16746 #define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0008 */
16747 
16748 #define TIM_CCMR1_IC1F_Pos        (4U)
16749 #define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x000000F0 */
16750 #define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
16751 #define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0010 */
16752 #define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0020 */
16753 #define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0040 */
16754 #define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0080 */
16755 
16756 #define TIM_CCMR1_IC2PSC_Pos      (10U)
16757 #define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000C00 */
16758 #define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
16759 #define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x0400 */
16760 #define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x0800 */
16761 
16762 #define TIM_CCMR1_IC2F_Pos        (12U)
16763 #define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x0000F000 */
16764 #define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
16765 #define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x1000 */
16766 #define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x2000 */
16767 #define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x4000 */
16768 #define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x8000 */
16769 
16770 /******************  Bit definition for TIM_CCMR2 register  *******************/
16771 #define TIM_CCMR2_CC3S_Pos        (0U)
16772 #define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000003 */
16773 #define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
16774 #define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x0001 */
16775 #define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x0002 */
16776 
16777 #define TIM_CCMR2_OC3FE_Pos       (2U)
16778 #define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)                /*!< 0x00000004 */
16779 #define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable           */
16780 #define TIM_CCMR2_OC3PE_Pos       (3U)
16781 #define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)                /*!< 0x00000008 */
16782 #define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable        */
16783 
16784 #define TIM_CCMR2_OC3M_Pos        (4U)
16785 #define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000070 */
16786 #define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
16787 #define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x0010 */
16788 #define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x0020 */
16789 #define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x0040 */
16790 
16791 #define TIM_CCMR2_OC3CE_Pos       (7U)
16792 #define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)                /*!< 0x00000080 */
16793 #define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
16794 
16795 #define TIM_CCMR2_CC4S_Pos        (8U)
16796 #define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000300 */
16797 #define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
16798 #define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x0100 */
16799 #define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x0200 */
16800 
16801 #define TIM_CCMR2_OC4FE_Pos       (10U)
16802 #define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)                /*!< 0x00000400 */
16803 #define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable    */
16804 #define TIM_CCMR2_OC4PE_Pos       (11U)
16805 #define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)                /*!< 0x00000800 */
16806 #define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
16807 
16808 #define TIM_CCMR2_OC4M_Pos        (12U)
16809 #define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00007000 */
16810 #define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
16811 #define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x1000 */
16812 #define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x2000 */
16813 #define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x4000 */
16814 
16815 #define TIM_CCMR2_OC4CE_Pos       (15U)
16816 #define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)                /*!< 0x00008000 */
16817 #define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
16818 
16819 /*----------------------------------------------------------------------------*/
16820 
16821 #define TIM_CCMR2_IC3PSC_Pos      (2U)
16822 #define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0000000C */
16823 #define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
16824 #define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0004 */
16825 #define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0008 */
16826 
16827 #define TIM_CCMR2_IC3F_Pos        (4U)
16828 #define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x000000F0 */
16829 #define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
16830 #define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0010 */
16831 #define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0020 */
16832 #define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0040 */
16833 #define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0080 */
16834 
16835 #define TIM_CCMR2_IC4PSC_Pos      (10U)
16836 #define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000C00 */
16837 #define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
16838 #define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x0400 */
16839 #define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x0800 */
16840 
16841 #define TIM_CCMR2_IC4F_Pos        (12U)
16842 #define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x0000F000 */
16843 #define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
16844 #define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x1000 */
16845 #define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x2000 */
16846 #define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x4000 */
16847 #define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x8000 */
16848 
16849 /*******************  Bit definition for TIM_CCER register  *******************/
16850 #define TIM_CCER_CC1E_Pos         (0U)
16851 #define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                  /*!< 0x00000001 */
16852 #define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable                 */
16853 #define TIM_CCER_CC1P_Pos         (1U)
16854 #define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                  /*!< 0x00000002 */
16855 #define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity               */
16856 #define TIM_CCER_CC1NE_Pos        (2U)
16857 #define TIM_CCER_CC1NE_Msk        (0x1UL << TIM_CCER_CC1NE_Pos)                 /*!< 0x00000004 */
16858 #define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable   */
16859 #define TIM_CCER_CC1NP_Pos        (3U)
16860 #define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                 /*!< 0x00000008 */
16861 #define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
16862 #define TIM_CCER_CC2E_Pos         (4U)
16863 #define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                  /*!< 0x00000010 */
16864 #define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable                 */
16865 #define TIM_CCER_CC2P_Pos         (5U)
16866 #define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                  /*!< 0x00000020 */
16867 #define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity               */
16868 #define TIM_CCER_CC2NE_Pos        (6U)
16869 #define TIM_CCER_CC2NE_Msk        (0x1UL << TIM_CCER_CC2NE_Pos)                 /*!< 0x00000040 */
16870 #define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable   */
16871 #define TIM_CCER_CC2NP_Pos        (7U)
16872 #define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                 /*!< 0x00000080 */
16873 #define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
16874 #define TIM_CCER_CC3E_Pos         (8U)
16875 #define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                  /*!< 0x00000100 */
16876 #define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable                 */
16877 #define TIM_CCER_CC3P_Pos         (9U)
16878 #define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                  /*!< 0x00000200 */
16879 #define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity               */
16880 #define TIM_CCER_CC3NE_Pos        (10U)
16881 #define TIM_CCER_CC3NE_Msk        (0x1UL << TIM_CCER_CC3NE_Pos)                 /*!< 0x00000400 */
16882 #define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable   */
16883 #define TIM_CCER_CC3NP_Pos        (11U)
16884 #define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                 /*!< 0x00000800 */
16885 #define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
16886 #define TIM_CCER_CC4E_Pos         (12U)
16887 #define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                  /*!< 0x00001000 */
16888 #define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable                 */
16889 #define TIM_CCER_CC4P_Pos         (13U)
16890 #define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                  /*!< 0x00002000 */
16891 #define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity               */
16892 #define TIM_CCER_CC4NP_Pos        (15U)
16893 #define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                 /*!< 0x00008000 */
16894 #define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
16895 
16896 /*******************  Bit definition for TIM_CNT register  ********************/
16897 #define TIM_CNT_CNT_Pos           (0U)
16898 #define TIM_CNT_CNT_Msk           (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)                 /*!< 0xFFFFFFFF */
16899 #define TIM_CNT_CNT               TIM_CNT_CNT_Msk                                  /*!<Counter Value            */
16900 
16901 /*******************  Bit definition for TIM_PSC register  ********************/
16902 #define TIM_PSC_PSC_Pos           (0U)
16903 #define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                 /*!< 0x0000FFFF */
16904 #define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value          */
16905 
16906 /*******************  Bit definition for TIM_ARR register  ********************/
16907 #define TIM_ARR_ARR_Pos           (0U)
16908 #define TIM_ARR_ARR_Msk           (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)             /*!< 0xFFFFFFFF */
16909 #define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */
16910 
16911 /*******************  Bit definition for TIM_RCR register  ********************/
16912 #define TIM_RCR_REP_Pos           (0U)
16913 #define TIM_RCR_REP_Msk           (0xFFUL << TIM_RCR_REP_Pos)                   /*!< 0x000000FF */
16914 #define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */
16915 
16916 /*******************  Bit definition for TIM_CCR1 register  *******************/
16917 #define TIM_CCR1_CCR1_Pos         (0U)
16918 #define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)               /*!< 0x0000FFFF */
16919 #define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value  */
16920 
16921 /*******************  Bit definition for TIM_CCR2 register  *******************/
16922 #define TIM_CCR2_CCR2_Pos         (0U)
16923 #define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)               /*!< 0x0000FFFF */
16924 #define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value  */
16925 
16926 /*******************  Bit definition for TIM_CCR3 register  *******************/
16927 #define TIM_CCR3_CCR3_Pos         (0U)
16928 #define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)               /*!< 0x0000FFFF */
16929 #define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value  */
16930 
16931 /*******************  Bit definition for TIM_CCR4 register  *******************/
16932 #define TIM_CCR4_CCR4_Pos         (0U)
16933 #define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)               /*!< 0x0000FFFF */
16934 #define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value  */
16935 
16936 /*******************  Bit definition for TIM_BDTR register  *******************/
16937 #define TIM_BDTR_DTG_Pos          (0U)
16938 #define TIM_BDTR_DTG_Msk          (0xFFUL << TIM_BDTR_DTG_Pos)                  /*!< 0x000000FF */
16939 #define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
16940 #define TIM_BDTR_DTG_0            (0x01UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0001 */
16941 #define TIM_BDTR_DTG_1            (0x02UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0002 */
16942 #define TIM_BDTR_DTG_2            (0x04UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0004 */
16943 #define TIM_BDTR_DTG_3            (0x08UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0008 */
16944 #define TIM_BDTR_DTG_4            (0x10UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0010 */
16945 #define TIM_BDTR_DTG_5            (0x20UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0020 */
16946 #define TIM_BDTR_DTG_6            (0x40UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0040 */
16947 #define TIM_BDTR_DTG_7            (0x80UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0080 */
16948 
16949 #define TIM_BDTR_LOCK_Pos         (8U)
16950 #define TIM_BDTR_LOCK_Msk         (0x3UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000300 */
16951 #define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */
16952 #define TIM_BDTR_LOCK_0           (0x1UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x0100 */
16953 #define TIM_BDTR_LOCK_1           (0x2UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x0200 */
16954 
16955 #define TIM_BDTR_OSSI_Pos         (10U)
16956 #define TIM_BDTR_OSSI_Msk         (0x1UL << TIM_BDTR_OSSI_Pos)                  /*!< 0x00000400 */
16957 #define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */
16958 #define TIM_BDTR_OSSR_Pos         (11U)
16959 #define TIM_BDTR_OSSR_Msk         (0x1UL << TIM_BDTR_OSSR_Pos)                  /*!< 0x00000800 */
16960 #define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode  */
16961 #define TIM_BDTR_BKE_Pos          (12U)
16962 #define TIM_BDTR_BKE_Msk          (0x1UL << TIM_BDTR_BKE_Pos)                   /*!< 0x00001000 */
16963 #define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable                      */
16964 #define TIM_BDTR_BKP_Pos          (13U)
16965 #define TIM_BDTR_BKP_Msk          (0x1UL << TIM_BDTR_BKP_Pos)                   /*!< 0x00002000 */
16966 #define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity                    */
16967 #define TIM_BDTR_AOE_Pos          (14U)
16968 #define TIM_BDTR_AOE_Msk          (0x1UL << TIM_BDTR_AOE_Pos)                   /*!< 0x00004000 */
16969 #define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable           */
16970 #define TIM_BDTR_MOE_Pos          (15U)
16971 #define TIM_BDTR_MOE_Msk          (0x1UL << TIM_BDTR_MOE_Pos)                   /*!< 0x00008000 */
16972 #define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable                */
16973 
16974 /*******************  Bit definition for TIM_DCR register  ********************/
16975 #define TIM_DCR_DBA_Pos           (0U)
16976 #define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                   /*!< 0x0000001F */
16977 #define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
16978 #define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                   /*!< 0x0001 */
16979 #define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                   /*!< 0x0002 */
16980 #define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                   /*!< 0x0004 */
16981 #define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                   /*!< 0x0008 */
16982 #define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                   /*!< 0x0010 */
16983 
16984 #define TIM_DCR_DBL_Pos           (8U)
16985 #define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                   /*!< 0x00001F00 */
16986 #define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
16987 #define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                   /*!< 0x0100 */
16988 #define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                   /*!< 0x0200 */
16989 #define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                   /*!< 0x0400 */
16990 #define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                   /*!< 0x0800 */
16991 #define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                   /*!< 0x1000 */
16992 
16993 /*******************  Bit definition for TIM_DMAR register  *******************/
16994 #define TIM_DMAR_DMAB_Pos         (0U)
16995 #define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)               /*!< 0x0000FFFF */
16996 #define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses                    */
16997 
16998 /*******************  Bit definition for TIM_OR register  *********************/
16999 #define TIM_OR_TI1_RMP_Pos        (0U)
17000 #define TIM_OR_TI1_RMP_Msk        (0x3UL << TIM_OR_TI1_RMP_Pos)                 /*!< 0x00000003 */
17001 #define TIM_OR_TI1_RMP            TIM_OR_TI1_RMP_Msk                           /*!< TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap) */
17002 #define TIM_OR_TI1_RMP_0          (0x1UL << TIM_OR_TI1_RMP_Pos)                 /*!< 0x00000001 */
17003 #define TIM_OR_TI1_RMP_1          (0x2UL << TIM_OR_TI1_RMP_Pos)                 /*!< 0x00000002 */
17004 
17005 #define TIM_OR_TI4_RMP_Pos        (6U)
17006 #define TIM_OR_TI4_RMP_Msk        (0x3UL << TIM_OR_TI4_RMP_Pos)                 /*!< 0x000000C0 */
17007 #define TIM_OR_TI4_RMP            TIM_OR_TI4_RMP_Msk                           /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */
17008 #define TIM_OR_TI4_RMP_0          (0x1UL << TIM_OR_TI4_RMP_Pos)                 /*!< 0x0040 */
17009 #define TIM_OR_TI4_RMP_1          (0x2UL << TIM_OR_TI4_RMP_Pos)                 /*!< 0x0080 */
17010 #define TIM_OR_ITR1_RMP_Pos       (10U)
17011 #define TIM_OR_ITR1_RMP_Msk       (0x3UL << TIM_OR_ITR1_RMP_Pos)                /*!< 0x00000C00 */
17012 #define TIM_OR_ITR1_RMP           TIM_OR_ITR1_RMP_Msk                          /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
17013 #define TIM_OR_ITR1_RMP_0         (0x1UL << TIM_OR_ITR1_RMP_Pos)                /*!< 0x0400 */
17014 #define TIM_OR_ITR1_RMP_1         (0x2UL << TIM_OR_ITR1_RMP_Pos)                /*!< 0x0800 */
17015 
17016 
17017 /******************************************************************************/
17018 /*                                                                            */
17019 /*         Universal Synchronous Asynchronous Receiver Transmitter            */
17020 /*                                                                            */
17021 /******************************************************************************/
17022 /*******************  Bit definition for USART_SR register  *******************/
17023 #define USART_SR_PE_Pos               (0U)
17024 #define USART_SR_PE_Msk               (0x1UL << USART_SR_PE_Pos)                /*!< 0x00000001 */
17025 #define USART_SR_PE                   USART_SR_PE_Msk                          /*!<Parity Error                 */
17026 #define USART_SR_FE_Pos               (1U)
17027 #define USART_SR_FE_Msk               (0x1UL << USART_SR_FE_Pos)                /*!< 0x00000002 */
17028 #define USART_SR_FE                   USART_SR_FE_Msk                          /*!<Framing Error                */
17029 #define USART_SR_NE_Pos               (2U)
17030 #define USART_SR_NE_Msk               (0x1UL << USART_SR_NE_Pos)                /*!< 0x00000004 */
17031 #define USART_SR_NE                   USART_SR_NE_Msk                          /*!<Noise Error Flag             */
17032 #define USART_SR_ORE_Pos              (3U)
17033 #define USART_SR_ORE_Msk              (0x1UL << USART_SR_ORE_Pos)               /*!< 0x00000008 */
17034 #define USART_SR_ORE                  USART_SR_ORE_Msk                         /*!<OverRun Error                */
17035 #define USART_SR_IDLE_Pos             (4U)
17036 #define USART_SR_IDLE_Msk             (0x1UL << USART_SR_IDLE_Pos)              /*!< 0x00000010 */
17037 #define USART_SR_IDLE                 USART_SR_IDLE_Msk                        /*!<IDLE line detected           */
17038 #define USART_SR_RXNE_Pos             (5U)
17039 #define USART_SR_RXNE_Msk             (0x1UL << USART_SR_RXNE_Pos)              /*!< 0x00000020 */
17040 #define USART_SR_RXNE                 USART_SR_RXNE_Msk                        /*!<Read Data Register Not Empty */
17041 #define USART_SR_TC_Pos               (6U)
17042 #define USART_SR_TC_Msk               (0x1UL << USART_SR_TC_Pos)                /*!< 0x00000040 */
17043 #define USART_SR_TC                   USART_SR_TC_Msk                          /*!<Transmission Complete        */
17044 #define USART_SR_TXE_Pos              (7U)
17045 #define USART_SR_TXE_Msk              (0x1UL << USART_SR_TXE_Pos)               /*!< 0x00000080 */
17046 #define USART_SR_TXE                  USART_SR_TXE_Msk                         /*!<Transmit Data Register Empty */
17047 #define USART_SR_LBD_Pos              (8U)
17048 #define USART_SR_LBD_Msk              (0x1UL << USART_SR_LBD_Pos)               /*!< 0x00000100 */
17049 #define USART_SR_LBD                  USART_SR_LBD_Msk                         /*!<LIN Break Detection Flag     */
17050 #define USART_SR_CTS_Pos              (9U)
17051 #define USART_SR_CTS_Msk              (0x1UL << USART_SR_CTS_Pos)               /*!< 0x00000200 */
17052 #define USART_SR_CTS                  USART_SR_CTS_Msk                         /*!<CTS Flag                     */
17053 
17054 /*******************  Bit definition for USART_DR register  *******************/
17055 #define USART_DR_DR_Pos               (0U)
17056 #define USART_DR_DR_Msk               (0x1FFUL << USART_DR_DR_Pos)              /*!< 0x000001FF */
17057 #define USART_DR_DR                   USART_DR_DR_Msk                          /*!<Data value */
17058 
17059 /******************  Bit definition for USART_BRR register  *******************/
17060 #define USART_BRR_DIV_Fraction_Pos    (0U)
17061 #define USART_BRR_DIV_Fraction_Msk    (0xFUL << USART_BRR_DIV_Fraction_Pos)     /*!< 0x0000000F */
17062 #define USART_BRR_DIV_Fraction        USART_BRR_DIV_Fraction_Msk               /*!<Fraction of USARTDIV */
17063 #define USART_BRR_DIV_Mantissa_Pos    (4U)
17064 #define USART_BRR_DIV_Mantissa_Msk    (0xFFFUL << USART_BRR_DIV_Mantissa_Pos)   /*!< 0x0000FFF0 */
17065 #define USART_BRR_DIV_Mantissa        USART_BRR_DIV_Mantissa_Msk               /*!<Mantissa of USARTDIV */
17066 
17067 /******************  Bit definition for USART_CR1 register  *******************/
17068 #define USART_CR1_SBK_Pos             (0U)
17069 #define USART_CR1_SBK_Msk             (0x1UL << USART_CR1_SBK_Pos)              /*!< 0x00000001 */
17070 #define USART_CR1_SBK                 USART_CR1_SBK_Msk                        /*!<Send Break                             */
17071 #define USART_CR1_RWU_Pos             (1U)
17072 #define USART_CR1_RWU_Msk             (0x1UL << USART_CR1_RWU_Pos)              /*!< 0x00000002 */
17073 #define USART_CR1_RWU                 USART_CR1_RWU_Msk                        /*!<Receiver wakeup                        */
17074 #define USART_CR1_RE_Pos              (2U)
17075 #define USART_CR1_RE_Msk              (0x1UL << USART_CR1_RE_Pos)               /*!< 0x00000004 */
17076 #define USART_CR1_RE                  USART_CR1_RE_Msk                         /*!<Receiver Enable                        */
17077 #define USART_CR1_TE_Pos              (3U)
17078 #define USART_CR1_TE_Msk              (0x1UL << USART_CR1_TE_Pos)               /*!< 0x00000008 */
17079 #define USART_CR1_TE                  USART_CR1_TE_Msk                         /*!<Transmitter Enable                     */
17080 #define USART_CR1_IDLEIE_Pos          (4U)
17081 #define USART_CR1_IDLEIE_Msk          (0x1UL << USART_CR1_IDLEIE_Pos)           /*!< 0x00000010 */
17082 #define USART_CR1_IDLEIE              USART_CR1_IDLEIE_Msk                     /*!<IDLE Interrupt Enable                  */
17083 #define USART_CR1_RXNEIE_Pos          (5U)
17084 #define USART_CR1_RXNEIE_Msk          (0x1UL << USART_CR1_RXNEIE_Pos)           /*!< 0x00000020 */
17085 #define USART_CR1_RXNEIE              USART_CR1_RXNEIE_Msk                     /*!<RXNE Interrupt Enable                  */
17086 #define USART_CR1_TCIE_Pos            (6U)
17087 #define USART_CR1_TCIE_Msk            (0x1UL << USART_CR1_TCIE_Pos)             /*!< 0x00000040 */
17088 #define USART_CR1_TCIE                USART_CR1_TCIE_Msk                       /*!<Transmission Complete Interrupt Enable */
17089 #define USART_CR1_TXEIE_Pos           (7U)
17090 #define USART_CR1_TXEIE_Msk           (0x1UL << USART_CR1_TXEIE_Pos)            /*!< 0x00000080 */
17091 #define USART_CR1_TXEIE               USART_CR1_TXEIE_Msk                      /*!<TXE Interrupt Enable                   */
17092 #define USART_CR1_PEIE_Pos            (8U)
17093 #define USART_CR1_PEIE_Msk            (0x1UL << USART_CR1_PEIE_Pos)             /*!< 0x00000100 */
17094 #define USART_CR1_PEIE                USART_CR1_PEIE_Msk                       /*!<PE Interrupt Enable                    */
17095 #define USART_CR1_PS_Pos              (9U)
17096 #define USART_CR1_PS_Msk              (0x1UL << USART_CR1_PS_Pos)               /*!< 0x00000200 */
17097 #define USART_CR1_PS                  USART_CR1_PS_Msk                         /*!<Parity Selection                       */
17098 #define USART_CR1_PCE_Pos             (10U)
17099 #define USART_CR1_PCE_Msk             (0x1UL << USART_CR1_PCE_Pos)              /*!< 0x00000400 */
17100 #define USART_CR1_PCE                 USART_CR1_PCE_Msk                        /*!<Parity Control Enable                  */
17101 #define USART_CR1_WAKE_Pos            (11U)
17102 #define USART_CR1_WAKE_Msk            (0x1UL << USART_CR1_WAKE_Pos)             /*!< 0x00000800 */
17103 #define USART_CR1_WAKE                USART_CR1_WAKE_Msk                       /*!<Wakeup method                          */
17104 #define USART_CR1_M_Pos               (12U)
17105 #define USART_CR1_M_Msk               (0x1UL << USART_CR1_M_Pos)                /*!< 0x00001000 */
17106 #define USART_CR1_M                   USART_CR1_M_Msk                          /*!<Word length                            */
17107 #define USART_CR1_UE_Pos              (13U)
17108 #define USART_CR1_UE_Msk              (0x1UL << USART_CR1_UE_Pos)               /*!< 0x00002000 */
17109 #define USART_CR1_UE                  USART_CR1_UE_Msk                         /*!<USART Enable                           */
17110 #define USART_CR1_OVER8_Pos           (15U)
17111 #define USART_CR1_OVER8_Msk           (0x1UL << USART_CR1_OVER8_Pos)            /*!< 0x00008000 */
17112 #define USART_CR1_OVER8               USART_CR1_OVER8_Msk                      /*!<USART Oversampling by 8 enable         */
17113 
17114 /******************  Bit definition for USART_CR2 register  *******************/
17115 #define USART_CR2_ADD_Pos             (0U)
17116 #define USART_CR2_ADD_Msk             (0xFUL << USART_CR2_ADD_Pos)              /*!< 0x0000000F */
17117 #define USART_CR2_ADD                 USART_CR2_ADD_Msk                        /*!<Address of the USART node            */
17118 #define USART_CR2_LBDL_Pos            (5U)
17119 #define USART_CR2_LBDL_Msk            (0x1UL << USART_CR2_LBDL_Pos)             /*!< 0x00000020 */
17120 #define USART_CR2_LBDL                USART_CR2_LBDL_Msk                       /*!<LIN Break Detection Length           */
17121 #define USART_CR2_LBDIE_Pos           (6U)
17122 #define USART_CR2_LBDIE_Msk           (0x1UL << USART_CR2_LBDIE_Pos)            /*!< 0x00000040 */
17123 #define USART_CR2_LBDIE               USART_CR2_LBDIE_Msk                      /*!<LIN Break Detection Interrupt Enable */
17124 #define USART_CR2_LBCL_Pos            (8U)
17125 #define USART_CR2_LBCL_Msk            (0x1UL << USART_CR2_LBCL_Pos)             /*!< 0x00000100 */
17126 #define USART_CR2_LBCL                USART_CR2_LBCL_Msk                       /*!<Last Bit Clock pulse                 */
17127 #define USART_CR2_CPHA_Pos            (9U)
17128 #define USART_CR2_CPHA_Msk            (0x1UL << USART_CR2_CPHA_Pos)             /*!< 0x00000200 */
17129 #define USART_CR2_CPHA                USART_CR2_CPHA_Msk                       /*!<Clock Phase                          */
17130 #define USART_CR2_CPOL_Pos            (10U)
17131 #define USART_CR2_CPOL_Msk            (0x1UL << USART_CR2_CPOL_Pos)             /*!< 0x00000400 */
17132 #define USART_CR2_CPOL                USART_CR2_CPOL_Msk                       /*!<Clock Polarity                       */
17133 #define USART_CR2_CLKEN_Pos           (11U)
17134 #define USART_CR2_CLKEN_Msk           (0x1UL << USART_CR2_CLKEN_Pos)            /*!< 0x00000800 */
17135 #define USART_CR2_CLKEN               USART_CR2_CLKEN_Msk                      /*!<Clock Enable                         */
17136 
17137 #define USART_CR2_STOP_Pos            (12U)
17138 #define USART_CR2_STOP_Msk            (0x3UL << USART_CR2_STOP_Pos)             /*!< 0x00003000 */
17139 #define USART_CR2_STOP                USART_CR2_STOP_Msk                       /*!<STOP[1:0] bits (STOP bits) */
17140 #define USART_CR2_STOP_0              (0x1UL << USART_CR2_STOP_Pos)             /*!< 0x1000 */
17141 #define USART_CR2_STOP_1              (0x2UL << USART_CR2_STOP_Pos)             /*!< 0x2000 */
17142 
17143 #define USART_CR2_LINEN_Pos           (14U)
17144 #define USART_CR2_LINEN_Msk           (0x1UL << USART_CR2_LINEN_Pos)            /*!< 0x00004000 */
17145 #define USART_CR2_LINEN               USART_CR2_LINEN_Msk                      /*!<LIN mode enable */
17146 
17147 /******************  Bit definition for USART_CR3 register  *******************/
17148 #define USART_CR3_EIE_Pos             (0U)
17149 #define USART_CR3_EIE_Msk             (0x1UL << USART_CR3_EIE_Pos)              /*!< 0x00000001 */
17150 #define USART_CR3_EIE                 USART_CR3_EIE_Msk                        /*!<Error Interrupt Enable      */
17151 #define USART_CR3_IREN_Pos            (1U)
17152 #define USART_CR3_IREN_Msk            (0x1UL << USART_CR3_IREN_Pos)             /*!< 0x00000002 */
17153 #define USART_CR3_IREN                USART_CR3_IREN_Msk                       /*!<IrDA mode Enable            */
17154 #define USART_CR3_IRLP_Pos            (2U)
17155 #define USART_CR3_IRLP_Msk            (0x1UL << USART_CR3_IRLP_Pos)             /*!< 0x00000004 */
17156 #define USART_CR3_IRLP                USART_CR3_IRLP_Msk                       /*!<IrDA Low-Power              */
17157 #define USART_CR3_HDSEL_Pos           (3U)
17158 #define USART_CR3_HDSEL_Msk           (0x1UL << USART_CR3_HDSEL_Pos)            /*!< 0x00000008 */
17159 #define USART_CR3_HDSEL               USART_CR3_HDSEL_Msk                      /*!<Half-Duplex Selection       */
17160 #define USART_CR3_NACK_Pos            (4U)
17161 #define USART_CR3_NACK_Msk            (0x1UL << USART_CR3_NACK_Pos)             /*!< 0x00000010 */
17162 #define USART_CR3_NACK                USART_CR3_NACK_Msk                       /*!<Smartcard NACK enable       */
17163 #define USART_CR3_SCEN_Pos            (5U)
17164 #define USART_CR3_SCEN_Msk            (0x1UL << USART_CR3_SCEN_Pos)             /*!< 0x00000020 */
17165 #define USART_CR3_SCEN                USART_CR3_SCEN_Msk                       /*!<Smartcard mode enable       */
17166 #define USART_CR3_DMAR_Pos            (6U)
17167 #define USART_CR3_DMAR_Msk            (0x1UL << USART_CR3_DMAR_Pos)             /*!< 0x00000040 */
17168 #define USART_CR3_DMAR                USART_CR3_DMAR_Msk                       /*!<DMA Enable Receiver         */
17169 #define USART_CR3_DMAT_Pos            (7U)
17170 #define USART_CR3_DMAT_Msk            (0x1UL << USART_CR3_DMAT_Pos)             /*!< 0x00000080 */
17171 #define USART_CR3_DMAT                USART_CR3_DMAT_Msk                       /*!<DMA Enable Transmitter      */
17172 #define USART_CR3_RTSE_Pos            (8U)
17173 #define USART_CR3_RTSE_Msk            (0x1UL << USART_CR3_RTSE_Pos)             /*!< 0x00000100 */
17174 #define USART_CR3_RTSE                USART_CR3_RTSE_Msk                       /*!<RTS Enable                  */
17175 #define USART_CR3_CTSE_Pos            (9U)
17176 #define USART_CR3_CTSE_Msk            (0x1UL << USART_CR3_CTSE_Pos)             /*!< 0x00000200 */
17177 #define USART_CR3_CTSE                USART_CR3_CTSE_Msk                       /*!<CTS Enable                  */
17178 #define USART_CR3_CTSIE_Pos           (10U)
17179 #define USART_CR3_CTSIE_Msk           (0x1UL << USART_CR3_CTSIE_Pos)            /*!< 0x00000400 */
17180 #define USART_CR3_CTSIE               USART_CR3_CTSIE_Msk                      /*!<CTS Interrupt Enable        */
17181 #define USART_CR3_ONEBIT_Pos          (11U)
17182 #define USART_CR3_ONEBIT_Msk          (0x1UL << USART_CR3_ONEBIT_Pos)           /*!< 0x00000800 */
17183 #define USART_CR3_ONEBIT              USART_CR3_ONEBIT_Msk                     /*!<USART One bit method enable */
17184 
17185 /******************  Bit definition for USART_GTPR register  ******************/
17186 #define USART_GTPR_PSC_Pos            (0U)
17187 #define USART_GTPR_PSC_Msk            (0xFFUL << USART_GTPR_PSC_Pos)            /*!< 0x000000FF */
17188 #define USART_GTPR_PSC                USART_GTPR_PSC_Msk                       /*!<PSC[7:0] bits (Prescaler value) */
17189 #define USART_GTPR_PSC_0              (0x01UL << USART_GTPR_PSC_Pos)            /*!< 0x0001 */
17190 #define USART_GTPR_PSC_1              (0x02UL << USART_GTPR_PSC_Pos)            /*!< 0x0002 */
17191 #define USART_GTPR_PSC_2              (0x04UL << USART_GTPR_PSC_Pos)            /*!< 0x0004 */
17192 #define USART_GTPR_PSC_3              (0x08UL << USART_GTPR_PSC_Pos)            /*!< 0x0008 */
17193 #define USART_GTPR_PSC_4              (0x10UL << USART_GTPR_PSC_Pos)            /*!< 0x0010 */
17194 #define USART_GTPR_PSC_5              (0x20UL << USART_GTPR_PSC_Pos)            /*!< 0x0020 */
17195 #define USART_GTPR_PSC_6              (0x40UL << USART_GTPR_PSC_Pos)            /*!< 0x0040 */
17196 #define USART_GTPR_PSC_7              (0x80UL << USART_GTPR_PSC_Pos)            /*!< 0x0080 */
17197 
17198 #define USART_GTPR_GT_Pos             (8U)
17199 #define USART_GTPR_GT_Msk             (0xFFUL << USART_GTPR_GT_Pos)             /*!< 0x0000FF00 */
17200 #define USART_GTPR_GT                 USART_GTPR_GT_Msk                        /*!<Guard time value */
17201 
17202 /******************************************************************************/
17203 /*                                                                            */
17204 /*                            Window WATCHDOG                                 */
17205 /*                                                                            */
17206 /******************************************************************************/
17207 /*******************  Bit definition for WWDG_CR register  ********************/
17208 #define WWDG_CR_T_Pos           (0U)
17209 #define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                       /*!< 0x0000007F */
17210 #define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
17211 #define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                       /*!< 0x01 */
17212 #define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                       /*!< 0x02 */
17213 #define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                       /*!< 0x04 */
17214 #define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                       /*!< 0x08 */
17215 #define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                       /*!< 0x10 */
17216 #define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                       /*!< 0x20 */
17217 #define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                       /*!< 0x40 */
17218 /* Legacy defines */
17219 #define  WWDG_CR_T0                          WWDG_CR_T_0
17220 #define  WWDG_CR_T1                          WWDG_CR_T_1
17221 #define  WWDG_CR_T2                          WWDG_CR_T_2
17222 #define  WWDG_CR_T3                          WWDG_CR_T_3
17223 #define  WWDG_CR_T4                          WWDG_CR_T_4
17224 #define  WWDG_CR_T5                          WWDG_CR_T_5
17225 #define  WWDG_CR_T6                          WWDG_CR_T_6
17226 
17227 #define WWDG_CR_WDGA_Pos        (7U)
17228 #define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                     /*!< 0x00000080 */
17229 #define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */
17230 
17231 /*******************  Bit definition for WWDG_CFR register  *******************/
17232 #define WWDG_CFR_W_Pos          (0U)
17233 #define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                      /*!< 0x0000007F */
17234 #define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */
17235 #define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                      /*!< 0x0001 */
17236 #define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                      /*!< 0x0002 */
17237 #define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                      /*!< 0x0004 */
17238 #define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                      /*!< 0x0008 */
17239 #define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                      /*!< 0x0010 */
17240 #define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                      /*!< 0x0020 */
17241 #define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                      /*!< 0x0040 */
17242 /* Legacy defines */
17243 #define  WWDG_CFR_W0                         WWDG_CFR_W_0
17244 #define  WWDG_CFR_W1                         WWDG_CFR_W_1
17245 #define  WWDG_CFR_W2                         WWDG_CFR_W_2
17246 #define  WWDG_CFR_W3                         WWDG_CFR_W_3
17247 #define  WWDG_CFR_W4                         WWDG_CFR_W_4
17248 #define  WWDG_CFR_W5                         WWDG_CFR_W_5
17249 #define  WWDG_CFR_W6                         WWDG_CFR_W_6
17250 
17251 #define WWDG_CFR_WDGTB_Pos      (7U)
17252 #define WWDG_CFR_WDGTB_Msk      (0x3UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000180 */
17253 #define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[1:0] bits (Timer Base) */
17254 #define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x0080 */
17255 #define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x0100 */
17256 /* Legacy defines */
17257 #define  WWDG_CFR_WDGTB0                     WWDG_CFR_WDGTB_0
17258 #define  WWDG_CFR_WDGTB1                     WWDG_CFR_WDGTB_1
17259 
17260 #define WWDG_CFR_EWI_Pos        (9U)
17261 #define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                     /*!< 0x00000200 */
17262 #define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */
17263 
17264 /*******************  Bit definition for WWDG_SR register  ********************/
17265 #define WWDG_SR_EWIF_Pos        (0U)
17266 #define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                     /*!< 0x00000001 */
17267 #define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */
17268 
17269 
17270 /******************************************************************************/
17271 /*                                                                            */
17272 /*                                DBG                                         */
17273 /*                                                                            */
17274 /******************************************************************************/
17275 /********************  Bit definition for DBGMCU_IDCODE register  *************/
17276 #define DBGMCU_IDCODE_DEV_ID_Pos                     (0U)
17277 #define DBGMCU_IDCODE_DEV_ID_Msk                     (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
17278 #define DBGMCU_IDCODE_DEV_ID                         DBGMCU_IDCODE_DEV_ID_Msk
17279 #define DBGMCU_IDCODE_REV_ID_Pos                     (16U)
17280 #define DBGMCU_IDCODE_REV_ID_Msk                     (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
17281 #define DBGMCU_IDCODE_REV_ID                         DBGMCU_IDCODE_REV_ID_Msk
17282 
17283 /********************  Bit definition for DBGMCU_CR register  *****************/
17284 #define DBGMCU_CR_DBG_SLEEP_Pos                      (0U)
17285 #define DBGMCU_CR_DBG_SLEEP_Msk                      (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
17286 #define DBGMCU_CR_DBG_SLEEP                          DBGMCU_CR_DBG_SLEEP_Msk
17287 #define DBGMCU_CR_DBG_STOP_Pos                       (1U)
17288 #define DBGMCU_CR_DBG_STOP_Msk                       (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
17289 #define DBGMCU_CR_DBG_STOP                           DBGMCU_CR_DBG_STOP_Msk
17290 #define DBGMCU_CR_DBG_STANDBY_Pos                    (2U)
17291 #define DBGMCU_CR_DBG_STANDBY_Msk                    (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
17292 #define DBGMCU_CR_DBG_STANDBY                        DBGMCU_CR_DBG_STANDBY_Msk
17293 #define DBGMCU_CR_TRACE_IOEN_Pos                     (5U)
17294 #define DBGMCU_CR_TRACE_IOEN_Msk                     (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
17295 #define DBGMCU_CR_TRACE_IOEN                         DBGMCU_CR_TRACE_IOEN_Msk
17296 
17297 #define DBGMCU_CR_TRACE_MODE_Pos                     (6U)
17298 #define DBGMCU_CR_TRACE_MODE_Msk                     (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
17299 #define DBGMCU_CR_TRACE_MODE                         DBGMCU_CR_TRACE_MODE_Msk
17300 #define DBGMCU_CR_TRACE_MODE_0                       (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
17301 #define DBGMCU_CR_TRACE_MODE_1                       (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
17302 
17303 /********************  Bit definition for DBGMCU_APB1_FZ register  ************/
17304 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos             (0U)
17305 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
17306 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP                 DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
17307 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos             (1U)
17308 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
17309 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP                 DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
17310 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos             (2U)
17311 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
17312 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP                 DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
17313 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos             (3U)
17314 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
17315 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP                 DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
17316 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos             (4U)
17317 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
17318 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP                 DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
17319 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos             (5U)
17320 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
17321 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP                 DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
17322 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos            (6U)
17323 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk            (0x1UL << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */
17324 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP                DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk
17325 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos            (7U)
17326 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk            (0x1UL << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos) /*!< 0x00000080 */
17327 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP                DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk
17328 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos            (8U)
17329 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk            (0x1UL << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */
17330 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP                DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk
17331 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos              (10U)
17332 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk              (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
17333 #define DBGMCU_APB1_FZ_DBG_RTC_STOP                  DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
17334 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos             (11U)
17335 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
17336 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP                 DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
17337 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos             (12U)
17338 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
17339 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP                 DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
17340 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos    (21U)
17341 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
17342 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
17343 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos    (22U)
17344 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
17345 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
17346 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos    (23U)
17347 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) /*!< 0x00800000 */
17348 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk
17349 #define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos    (24U)
17350 #define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos) /*!< 0x01000000 */
17351 #define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk
17352 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos             (25U)
17353 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos) /*!< 0x02000000 */
17354 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP                 DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk
17355 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos             (26U)
17356 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos) /*!< 0x04000000 */
17357 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP                 DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk
17358 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
17359 #define  DBGMCU_APB1_FZ_DBG_IWDEG_STOP           DBGMCU_APB1_FZ_DBG_IWDG_STOP
17360 
17361 /********************  Bit definition for DBGMCU_APB2_FZ register  ************/
17362 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos             (0U)
17363 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk             (0x1UL << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */
17364 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP                 DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
17365 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos             (1U)
17366 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk             (0x1UL << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos) /*!< 0x00000002 */
17367 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP                 DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk
17368 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos             (16U)
17369 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk             (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */
17370 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP                 DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
17371 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos            (17U)
17372 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk            (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00020000 */
17373 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP                DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk
17374 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos            (18U)
17375 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk            (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */
17376 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP                DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
17377 
17378 /******************************************************************************/
17379 /*                                                                            */
17380 /*                Ethernet MAC Registers bits definitions                     */
17381 /*                                                                            */
17382 /******************************************************************************/
17383 /* Bit definition for Ethernet MAC Control Register register */
17384 #define ETH_MACCR_WD_Pos                              (23U)
17385 #define ETH_MACCR_WD_Msk                              (0x1UL << ETH_MACCR_WD_Pos) /*!< 0x00800000 */
17386 #define ETH_MACCR_WD                                  ETH_MACCR_WD_Msk         /* Watchdog disable */
17387 #define ETH_MACCR_JD_Pos                              (22U)
17388 #define ETH_MACCR_JD_Msk                              (0x1UL << ETH_MACCR_JD_Pos) /*!< 0x00400000 */
17389 #define ETH_MACCR_JD                                  ETH_MACCR_JD_Msk         /* Jabber disable */
17390 #define ETH_MACCR_IFG_Pos                             (17U)
17391 #define ETH_MACCR_IFG_Msk                             (0x7UL << ETH_MACCR_IFG_Pos) /*!< 0x000E0000 */
17392 #define ETH_MACCR_IFG                                 ETH_MACCR_IFG_Msk        /* Inter-frame gap */
17393 #define ETH_MACCR_IFG_96Bit                           0x00000000U              /* Minimum IFG between frames during transmission is 96Bit */
17394 #define ETH_MACCR_IFG_88Bit                           0x00020000U              /* Minimum IFG between frames during transmission is 88Bit */
17395 #define ETH_MACCR_IFG_80Bit                           0x00040000U              /* Minimum IFG between frames during transmission is 80Bit */
17396 #define ETH_MACCR_IFG_72Bit                           0x00060000U              /* Minimum IFG between frames during transmission is 72Bit */
17397 #define ETH_MACCR_IFG_64Bit                           0x00080000U              /* Minimum IFG between frames during transmission is 64Bit */
17398 #define ETH_MACCR_IFG_56Bit                           0x000A0000U              /* Minimum IFG between frames during transmission is 56Bit */
17399 #define ETH_MACCR_IFG_48Bit                           0x000C0000U              /* Minimum IFG between frames during transmission is 48Bit */
17400 #define ETH_MACCR_IFG_40Bit                           0x000E0000U              /* Minimum IFG between frames during transmission is 40Bit */
17401 #define ETH_MACCR_CSD_Pos                             (16U)
17402 #define ETH_MACCR_CSD_Msk                             (0x1UL << ETH_MACCR_CSD_Pos) /*!< 0x00010000 */
17403 #define ETH_MACCR_CSD                                 ETH_MACCR_CSD_Msk        /* Carrier sense disable (during transmission) */
17404 #define ETH_MACCR_FES_Pos                             (14U)
17405 #define ETH_MACCR_FES_Msk                             (0x1UL << ETH_MACCR_FES_Pos) /*!< 0x00004000 */
17406 #define ETH_MACCR_FES                                 ETH_MACCR_FES_Msk        /* Fast ethernet speed */
17407 #define ETH_MACCR_ROD_Pos                             (13U)
17408 #define ETH_MACCR_ROD_Msk                             (0x1UL << ETH_MACCR_ROD_Pos) /*!< 0x00002000 */
17409 #define ETH_MACCR_ROD                                 ETH_MACCR_ROD_Msk        /* Receive own disable */
17410 #define ETH_MACCR_LM_Pos                              (12U)
17411 #define ETH_MACCR_LM_Msk                              (0x1UL << ETH_MACCR_LM_Pos) /*!< 0x00001000 */
17412 #define ETH_MACCR_LM                                  ETH_MACCR_LM_Msk         /* loopback mode */
17413 #define ETH_MACCR_DM_Pos                              (11U)
17414 #define ETH_MACCR_DM_Msk                              (0x1UL << ETH_MACCR_DM_Pos) /*!< 0x00000800 */
17415 #define ETH_MACCR_DM                                  ETH_MACCR_DM_Msk         /* Duplex mode */
17416 #define ETH_MACCR_IPCO_Pos                            (10U)
17417 #define ETH_MACCR_IPCO_Msk                            (0x1UL << ETH_MACCR_IPCO_Pos) /*!< 0x00000400 */
17418 #define ETH_MACCR_IPCO                                ETH_MACCR_IPCO_Msk       /* IP Checksum offload */
17419 #define ETH_MACCR_RD_Pos                              (9U)
17420 #define ETH_MACCR_RD_Msk                              (0x1UL << ETH_MACCR_RD_Pos) /*!< 0x00000200 */
17421 #define ETH_MACCR_RD                                  ETH_MACCR_RD_Msk         /* Retry disable */
17422 #define ETH_MACCR_APCS_Pos                            (7U)
17423 #define ETH_MACCR_APCS_Msk                            (0x1UL << ETH_MACCR_APCS_Pos) /*!< 0x00000080 */
17424 #define ETH_MACCR_APCS                                ETH_MACCR_APCS_Msk       /* Automatic Pad/CRC stripping */
17425 #define ETH_MACCR_BL_Pos                              (5U)
17426 #define ETH_MACCR_BL_Msk                              (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */
17427 #define ETH_MACCR_BL                                  ETH_MACCR_BL_Msk         /* Back-off limit: random integer number (r) of slot time delays before rescheduling
17428                                                        a transmission attempt during retries after a collision: 0 =< r <2^k */
17429 #define ETH_MACCR_BL_10                               0x00000000U              /* k = min (n, 10) */
17430 #define ETH_MACCR_BL_8                                0x00000020U              /* k = min (n, 8) */
17431 #define ETH_MACCR_BL_4                                0x00000040U              /* k = min (n, 4) */
17432 #define ETH_MACCR_BL_1                                0x00000060U              /* k = min (n, 1) */
17433 #define ETH_MACCR_DC_Pos                              (4U)
17434 #define ETH_MACCR_DC_Msk                              (0x1UL << ETH_MACCR_DC_Pos) /*!< 0x00000010 */
17435 #define ETH_MACCR_DC                                  ETH_MACCR_DC_Msk         /* Defferal check */
17436 #define ETH_MACCR_TE_Pos                              (3U)
17437 #define ETH_MACCR_TE_Msk                              (0x1UL << ETH_MACCR_TE_Pos) /*!< 0x00000008 */
17438 #define ETH_MACCR_TE                                  ETH_MACCR_TE_Msk         /* Transmitter enable */
17439 #define ETH_MACCR_RE_Pos                              (2U)
17440 #define ETH_MACCR_RE_Msk                              (0x1UL << ETH_MACCR_RE_Pos) /*!< 0x00000004 */
17441 #define ETH_MACCR_RE                                  ETH_MACCR_RE_Msk         /* Receiver enable */
17442 
17443 /* Bit definition for Ethernet MAC Frame Filter Register */
17444 #define ETH_MACFFR_RA_Pos                             (31U)
17445 #define ETH_MACFFR_RA_Msk                             (0x1UL << ETH_MACFFR_RA_Pos) /*!< 0x80000000 */
17446 #define ETH_MACFFR_RA                                 ETH_MACFFR_RA_Msk        /* Receive all */
17447 #define ETH_MACFFR_HPF_Pos                            (10U)
17448 #define ETH_MACFFR_HPF_Msk                            (0x1UL << ETH_MACFFR_HPF_Pos) /*!< 0x00000400 */
17449 #define ETH_MACFFR_HPF                                ETH_MACFFR_HPF_Msk       /* Hash or perfect filter */
17450 #define ETH_MACFFR_SAF_Pos                            (9U)
17451 #define ETH_MACFFR_SAF_Msk                            (0x1UL << ETH_MACFFR_SAF_Pos) /*!< 0x00000200 */
17452 #define ETH_MACFFR_SAF                                ETH_MACFFR_SAF_Msk       /* Source address filter enable */
17453 #define ETH_MACFFR_SAIF_Pos                           (8U)
17454 #define ETH_MACFFR_SAIF_Msk                           (0x1UL << ETH_MACFFR_SAIF_Pos) /*!< 0x00000100 */
17455 #define ETH_MACFFR_SAIF                               ETH_MACFFR_SAIF_Msk      /* SA inverse filtering */
17456 #define ETH_MACFFR_PCF_Pos                            (6U)
17457 #define ETH_MACFFR_PCF_Msk                            (0x3UL << ETH_MACFFR_PCF_Pos) /*!< 0x000000C0 */
17458 #define ETH_MACFFR_PCF                                ETH_MACFFR_PCF_Msk       /* Pass control frames: 3 cases */
17459 #define ETH_MACFFR_PCF_BlockAll_Pos                   (6U)
17460 #define ETH_MACFFR_PCF_BlockAll_Msk                   (0x1UL << ETH_MACFFR_PCF_BlockAll_Pos) /*!< 0x00000040 */
17461 #define ETH_MACFFR_PCF_BlockAll                       ETH_MACFFR_PCF_BlockAll_Msk /* MAC filters all control frames from reaching the application */
17462 #define ETH_MACFFR_PCF_ForwardAll_Pos                 (7U)
17463 #define ETH_MACFFR_PCF_ForwardAll_Msk                 (0x1UL << ETH_MACFFR_PCF_ForwardAll_Pos) /*!< 0x00000080 */
17464 #define ETH_MACFFR_PCF_ForwardAll                     ETH_MACFFR_PCF_ForwardAll_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */
17465 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos    (6U)
17466 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk    (0x3UL << ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos) /*!< 0x000000C0 */
17467 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter        ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk /* MAC forwards control frames that pass the Address Filter. */
17468 #define ETH_MACFFR_BFD_Pos                            (5U)
17469 #define ETH_MACFFR_BFD_Msk                            (0x1UL << ETH_MACFFR_BFD_Pos) /*!< 0x00000020 */
17470 #define ETH_MACFFR_BFD                                ETH_MACFFR_BFD_Msk       /* Broadcast frame disable */
17471 #define ETH_MACFFR_PAM_Pos                            (4U)
17472 #define ETH_MACFFR_PAM_Msk                            (0x1UL << ETH_MACFFR_PAM_Pos) /*!< 0x00000010 */
17473 #define ETH_MACFFR_PAM                                ETH_MACFFR_PAM_Msk       /* Pass all mutlicast */
17474 #define ETH_MACFFR_DAIF_Pos                           (3U)
17475 #define ETH_MACFFR_DAIF_Msk                           (0x1UL << ETH_MACFFR_DAIF_Pos) /*!< 0x00000008 */
17476 #define ETH_MACFFR_DAIF                               ETH_MACFFR_DAIF_Msk      /* DA Inverse filtering */
17477 #define ETH_MACFFR_HM_Pos                             (2U)
17478 #define ETH_MACFFR_HM_Msk                             (0x1UL << ETH_MACFFR_HM_Pos) /*!< 0x00000004 */
17479 #define ETH_MACFFR_HM                                 ETH_MACFFR_HM_Msk        /* Hash multicast */
17480 #define ETH_MACFFR_HU_Pos                             (1U)
17481 #define ETH_MACFFR_HU_Msk                             (0x1UL << ETH_MACFFR_HU_Pos) /*!< 0x00000002 */
17482 #define ETH_MACFFR_HU                                 ETH_MACFFR_HU_Msk        /* Hash unicast */
17483 #define ETH_MACFFR_PM_Pos                             (0U)
17484 #define ETH_MACFFR_PM_Msk                             (0x1UL << ETH_MACFFR_PM_Pos) /*!< 0x00000001 */
17485 #define ETH_MACFFR_PM                                 ETH_MACFFR_PM_Msk        /* Promiscuous mode */
17486 
17487 /* Bit definition for Ethernet MAC Hash Table High Register */
17488 #define ETH_MACHTHR_HTH_Pos                           (0U)
17489 #define ETH_MACHTHR_HTH_Msk                           (0xFFFFFFFFUL << ETH_MACHTHR_HTH_Pos) /*!< 0xFFFFFFFF */
17490 #define ETH_MACHTHR_HTH                               ETH_MACHTHR_HTH_Msk      /* Hash table high */
17491 
17492 /* Bit definition for Ethernet MAC Hash Table Low Register */
17493 #define ETH_MACHTLR_HTL_Pos                           (0U)
17494 #define ETH_MACHTLR_HTL_Msk                           (0xFFFFFFFFUL << ETH_MACHTLR_HTL_Pos) /*!< 0xFFFFFFFF */
17495 #define ETH_MACHTLR_HTL                               ETH_MACHTLR_HTL_Msk      /* Hash table low */
17496 
17497 /* Bit definition for Ethernet MAC MII Address Register */
17498 #define ETH_MACMIIAR_PA_Pos                           (11U)
17499 #define ETH_MACMIIAR_PA_Msk                           (0x1FUL << ETH_MACMIIAR_PA_Pos) /*!< 0x0000F800 */
17500 #define ETH_MACMIIAR_PA                               ETH_MACMIIAR_PA_Msk      /* Physical layer address */
17501 #define ETH_MACMIIAR_MR_Pos                           (6U)
17502 #define ETH_MACMIIAR_MR_Msk                           (0x1FUL << ETH_MACMIIAR_MR_Pos) /*!< 0x000007C0 */
17503 #define ETH_MACMIIAR_MR                               ETH_MACMIIAR_MR_Msk      /* MII register in the selected PHY */
17504 #define ETH_MACMIIAR_CR_Pos                           (2U)
17505 #define ETH_MACMIIAR_CR_Msk                           (0x7UL << ETH_MACMIIAR_CR_Pos) /*!< 0x0000001C */
17506 #define ETH_MACMIIAR_CR                               ETH_MACMIIAR_CR_Msk      /* CR clock range: 6 cases */
17507 #define ETH_MACMIIAR_CR_Div42                         0x00000000U              /* HCLK:60-100 MHz; MDC clock= HCLK/42   */
17508 #define ETH_MACMIIAR_CR_Div62_Pos                     (2U)
17509 #define ETH_MACMIIAR_CR_Div62_Msk                     (0x1UL << ETH_MACMIIAR_CR_Div62_Pos) /*!< 0x00000004 */
17510 #define ETH_MACMIIAR_CR_Div62                         ETH_MACMIIAR_CR_Div62_Msk /* HCLK:100-150 MHz; MDC clock= HCLK/62  */
17511 #define ETH_MACMIIAR_CR_Div16_Pos                     (3U)
17512 #define ETH_MACMIIAR_CR_Div16_Msk                     (0x1UL << ETH_MACMIIAR_CR_Div16_Pos) /*!< 0x00000008 */
17513 #define ETH_MACMIIAR_CR_Div16                         ETH_MACMIIAR_CR_Div16_Msk /* HCLK:20-35 MHz; MDC clock= HCLK/16    */
17514 #define ETH_MACMIIAR_CR_Div26_Pos                     (2U)
17515 #define ETH_MACMIIAR_CR_Div26_Msk                     (0x3UL << ETH_MACMIIAR_CR_Div26_Pos) /*!< 0x0000000C */
17516 #define ETH_MACMIIAR_CR_Div26                         ETH_MACMIIAR_CR_Div26_Msk /* HCLK:35-60 MHz; MDC clock= HCLK/26    */
17517 #define ETH_MACMIIAR_CR_Div102_Pos                    (4U)
17518 #define ETH_MACMIIAR_CR_Div102_Msk                    (0x1UL << ETH_MACMIIAR_CR_Div102_Pos) /*!< 0x00000010 */
17519 #define ETH_MACMIIAR_CR_Div102                        ETH_MACMIIAR_CR_Div102_Msk /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
17520 #define ETH_MACMIIAR_MW_Pos                           (1U)
17521 #define ETH_MACMIIAR_MW_Msk                           (0x1UL << ETH_MACMIIAR_MW_Pos) /*!< 0x00000002 */
17522 #define ETH_MACMIIAR_MW                               ETH_MACMIIAR_MW_Msk      /* MII write */
17523 #define ETH_MACMIIAR_MB_Pos                           (0U)
17524 #define ETH_MACMIIAR_MB_Msk                           (0x1UL << ETH_MACMIIAR_MB_Pos) /*!< 0x00000001 */
17525 #define ETH_MACMIIAR_MB                               ETH_MACMIIAR_MB_Msk      /* MII busy  */
17526 
17527 /* Bit definition for Ethernet MAC MII Data Register */
17528 #define ETH_MACMIIDR_MD_Pos                           (0U)
17529 #define ETH_MACMIIDR_MD_Msk                           (0xFFFFUL << ETH_MACMIIDR_MD_Pos) /*!< 0x0000FFFF */
17530 #define ETH_MACMIIDR_MD                               ETH_MACMIIDR_MD_Msk      /* MII data: read/write data from/to PHY */
17531 
17532 /* Bit definition for Ethernet MAC Flow Control Register */
17533 #define ETH_MACFCR_PT_Pos                             (16U)
17534 #define ETH_MACFCR_PT_Msk                             (0xFFFFUL << ETH_MACFCR_PT_Pos) /*!< 0xFFFF0000 */
17535 #define ETH_MACFCR_PT                                 ETH_MACFCR_PT_Msk        /* Pause time */
17536 #define ETH_MACFCR_ZQPD_Pos                           (7U)
17537 #define ETH_MACFCR_ZQPD_Msk                           (0x1UL << ETH_MACFCR_ZQPD_Pos) /*!< 0x00000080 */
17538 #define ETH_MACFCR_ZQPD                               ETH_MACFCR_ZQPD_Msk      /* Zero-quanta pause disable */
17539 #define ETH_MACFCR_PLT_Pos                            (4U)
17540 #define ETH_MACFCR_PLT_Msk                            (0x3UL << ETH_MACFCR_PLT_Pos) /*!< 0x00000030 */
17541 #define ETH_MACFCR_PLT                                ETH_MACFCR_PLT_Msk       /* Pause low threshold: 4 cases */
17542 #define ETH_MACFCR_PLT_Minus4                         0x00000000U              /* Pause time minus 4 slot times   */
17543 #define ETH_MACFCR_PLT_Minus28_Pos                    (4U)
17544 #define ETH_MACFCR_PLT_Minus28_Msk                    (0x1UL << ETH_MACFCR_PLT_Minus28_Pos) /*!< 0x00000010 */
17545 #define ETH_MACFCR_PLT_Minus28                        ETH_MACFCR_PLT_Minus28_Msk /* Pause time minus 28 slot times  */
17546 #define ETH_MACFCR_PLT_Minus144_Pos                   (5U)
17547 #define ETH_MACFCR_PLT_Minus144_Msk                   (0x1UL << ETH_MACFCR_PLT_Minus144_Pos) /*!< 0x00000020 */
17548 #define ETH_MACFCR_PLT_Minus144                       ETH_MACFCR_PLT_Minus144_Msk /* Pause time minus 144 slot times */
17549 #define ETH_MACFCR_PLT_Minus256_Pos                   (4U)
17550 #define ETH_MACFCR_PLT_Minus256_Msk                   (0x3UL << ETH_MACFCR_PLT_Minus256_Pos) /*!< 0x00000030 */
17551 #define ETH_MACFCR_PLT_Minus256                       ETH_MACFCR_PLT_Minus256_Msk /* Pause time minus 256 slot times */
17552 #define ETH_MACFCR_UPFD_Pos                           (3U)
17553 #define ETH_MACFCR_UPFD_Msk                           (0x1UL << ETH_MACFCR_UPFD_Pos) /*!< 0x00000008 */
17554 #define ETH_MACFCR_UPFD                               ETH_MACFCR_UPFD_Msk      /* Unicast pause frame detect */
17555 #define ETH_MACFCR_RFCE_Pos                           (2U)
17556 #define ETH_MACFCR_RFCE_Msk                           (0x1UL << ETH_MACFCR_RFCE_Pos) /*!< 0x00000004 */
17557 #define ETH_MACFCR_RFCE                               ETH_MACFCR_RFCE_Msk      /* Receive flow control enable */
17558 #define ETH_MACFCR_TFCE_Pos                           (1U)
17559 #define ETH_MACFCR_TFCE_Msk                           (0x1UL << ETH_MACFCR_TFCE_Pos) /*!< 0x00000002 */
17560 #define ETH_MACFCR_TFCE                               ETH_MACFCR_TFCE_Msk      /* Transmit flow control enable */
17561 #define ETH_MACFCR_FCBBPA_Pos                         (0U)
17562 #define ETH_MACFCR_FCBBPA_Msk                         (0x1UL << ETH_MACFCR_FCBBPA_Pos) /*!< 0x00000001 */
17563 #define ETH_MACFCR_FCBBPA                             ETH_MACFCR_FCBBPA_Msk    /* Flow control busy/backpressure activate */
17564 
17565 /* Bit definition for Ethernet MAC VLAN Tag Register */
17566 #define ETH_MACVLANTR_VLANTC_Pos                      (16U)
17567 #define ETH_MACVLANTR_VLANTC_Msk                      (0x1UL << ETH_MACVLANTR_VLANTC_Pos) /*!< 0x00010000 */
17568 #define ETH_MACVLANTR_VLANTC                          ETH_MACVLANTR_VLANTC_Msk /* 12-bit VLAN tag comparison */
17569 #define ETH_MACVLANTR_VLANTI_Pos                      (0U)
17570 #define ETH_MACVLANTR_VLANTI_Msk                      (0xFFFFUL << ETH_MACVLANTR_VLANTI_Pos) /*!< 0x0000FFFF */
17571 #define ETH_MACVLANTR_VLANTI                          ETH_MACVLANTR_VLANTI_Msk /* VLAN tag identifier (for receive frames) */
17572 
17573 /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
17574 #define ETH_MACRWUFFR_D_Pos                           (0U)
17575 #define ETH_MACRWUFFR_D_Msk                           (0xFFFFFFFFUL << ETH_MACRWUFFR_D_Pos) /*!< 0xFFFFFFFF */
17576 #define ETH_MACRWUFFR_D                               ETH_MACRWUFFR_D_Msk      /* Wake-up frame filter register data */
17577 /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
17578    Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
17579 /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
17580    Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
17581    Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
17582    Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
17583    Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
17584                               RSVD - Filter1 Command - RSVD - Filter0 Command
17585    Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
17586    Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
17587    Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
17588 
17589 /* Bit definition for Ethernet MAC PMT Control and Status Register */
17590 #define ETH_MACPMTCSR_WFFRPR_Pos                      (31U)
17591 #define ETH_MACPMTCSR_WFFRPR_Msk                      (0x1UL << ETH_MACPMTCSR_WFFRPR_Pos) /*!< 0x80000000 */
17592 #define ETH_MACPMTCSR_WFFRPR                          ETH_MACPMTCSR_WFFRPR_Msk /* Wake-Up Frame Filter Register Pointer Reset */
17593 #define ETH_MACPMTCSR_GU_Pos                          (9U)
17594 #define ETH_MACPMTCSR_GU_Msk                          (0x1UL << ETH_MACPMTCSR_GU_Pos) /*!< 0x00000200 */
17595 #define ETH_MACPMTCSR_GU                              ETH_MACPMTCSR_GU_Msk     /* Global Unicast                              */
17596 #define ETH_MACPMTCSR_WFR_Pos                         (6U)
17597 #define ETH_MACPMTCSR_WFR_Msk                         (0x1UL << ETH_MACPMTCSR_WFR_Pos) /*!< 0x00000040 */
17598 #define ETH_MACPMTCSR_WFR                             ETH_MACPMTCSR_WFR_Msk    /* Wake-Up Frame Received                      */
17599 #define ETH_MACPMTCSR_MPR_Pos                         (5U)
17600 #define ETH_MACPMTCSR_MPR_Msk                         (0x1UL << ETH_MACPMTCSR_MPR_Pos) /*!< 0x00000020 */
17601 #define ETH_MACPMTCSR_MPR                             ETH_MACPMTCSR_MPR_Msk    /* Magic Packet Received                       */
17602 #define ETH_MACPMTCSR_WFE_Pos                         (2U)
17603 #define ETH_MACPMTCSR_WFE_Msk                         (0x1UL << ETH_MACPMTCSR_WFE_Pos) /*!< 0x00000004 */
17604 #define ETH_MACPMTCSR_WFE                             ETH_MACPMTCSR_WFE_Msk    /* Wake-Up Frame Enable                        */
17605 #define ETH_MACPMTCSR_MPE_Pos                         (1U)
17606 #define ETH_MACPMTCSR_MPE_Msk                         (0x1UL << ETH_MACPMTCSR_MPE_Pos) /*!< 0x00000002 */
17607 #define ETH_MACPMTCSR_MPE                             ETH_MACPMTCSR_MPE_Msk    /* Magic Packet Enable                         */
17608 #define ETH_MACPMTCSR_PD_Pos                          (0U)
17609 #define ETH_MACPMTCSR_PD_Msk                          (0x1UL << ETH_MACPMTCSR_PD_Pos) /*!< 0x00000001 */
17610 #define ETH_MACPMTCSR_PD                              ETH_MACPMTCSR_PD_Msk     /* Power Down                                  */
17611 
17612 /* Bit definition for Ethernet MAC debug Register */
17613 #define ETH_MACDBGR_TFF_Pos                           (25U)
17614 #define ETH_MACDBGR_TFF_Msk                           (0x1UL << ETH_MACDBGR_TFF_Pos) /*!< 0x02000000 */
17615 #define ETH_MACDBGR_TFF                               ETH_MACDBGR_TFF_Msk      /* Tx FIFO full                                                            */
17616 #define ETH_MACDBGR_TFNE_Pos                          (24U)
17617 #define ETH_MACDBGR_TFNE_Msk                          (0x1UL << ETH_MACDBGR_TFNE_Pos) /*!< 0x01000000 */
17618 #define ETH_MACDBGR_TFNE                              ETH_MACDBGR_TFNE_Msk     /* Tx FIFO not empty                                                       */
17619 #define ETH_MACDBGR_TFWA_Pos                          (22U)
17620 #define ETH_MACDBGR_TFWA_Msk                          (0x1UL << ETH_MACDBGR_TFWA_Pos) /*!< 0x00400000 */
17621 #define ETH_MACDBGR_TFWA                              ETH_MACDBGR_TFWA_Msk     /* Tx FIFO write active                                                    */
17622 #define ETH_MACDBGR_TFRS_Pos                          (20U)
17623 #define ETH_MACDBGR_TFRS_Msk                          (0x3UL << ETH_MACDBGR_TFRS_Pos) /*!< 0x00300000 */
17624 #define ETH_MACDBGR_TFRS                              ETH_MACDBGR_TFRS_Msk     /* Tx FIFO read status mask                                                */
17625 #define ETH_MACDBGR_TFRS_WRITING_Pos                  (20U)
17626 #define ETH_MACDBGR_TFRS_WRITING_Msk                  (0x3UL << ETH_MACDBGR_TFRS_WRITING_Pos) /*!< 0x00300000 */
17627 #define ETH_MACDBGR_TFRS_WRITING                      ETH_MACDBGR_TFRS_WRITING_Msk /* Writing the received TxStatus or flushing the TxFIFO                    */
17628 #define ETH_MACDBGR_TFRS_WAITING_Pos                  (21U)
17629 #define ETH_MACDBGR_TFRS_WAITING_Msk                  (0x1UL << ETH_MACDBGR_TFRS_WAITING_Pos) /*!< 0x00200000 */
17630 #define ETH_MACDBGR_TFRS_WAITING                      ETH_MACDBGR_TFRS_WAITING_Msk /* Waiting for TxStatus from MAC transmitter                               */
17631 #define ETH_MACDBGR_TFRS_READ_Pos                     (20U)
17632 #define ETH_MACDBGR_TFRS_READ_Msk                     (0x1UL << ETH_MACDBGR_TFRS_READ_Pos) /*!< 0x00100000 */
17633 #define ETH_MACDBGR_TFRS_READ                         ETH_MACDBGR_TFRS_READ_Msk /* Read state (transferring data to the MAC transmitter)                   */
17634 #define ETH_MACDBGR_TFRS_IDLE                         0x00000000U              /* Idle state                                                              */
17635 #define ETH_MACDBGR_MTP_Pos                           (19U)
17636 #define ETH_MACDBGR_MTP_Msk                           (0x1UL << ETH_MACDBGR_MTP_Pos) /*!< 0x00080000 */
17637 #define ETH_MACDBGR_MTP                               ETH_MACDBGR_MTP_Msk      /* MAC transmitter in pause                                                */
17638 #define ETH_MACDBGR_MTFCS_Pos                         (17U)
17639 #define ETH_MACDBGR_MTFCS_Msk                         (0x3UL << ETH_MACDBGR_MTFCS_Pos) /*!< 0x00060000 */
17640 #define ETH_MACDBGR_MTFCS                             ETH_MACDBGR_MTFCS_Msk    /* MAC transmit frame controller status mask                               */
17641 #define ETH_MACDBGR_MTFCS_TRANSFERRING_Pos            (17U)
17642 #define ETH_MACDBGR_MTFCS_TRANSFERRING_Msk            (0x3UL << ETH_MACDBGR_MTFCS_TRANSFERRING_Pos) /*!< 0x00060000 */
17643 #define ETH_MACDBGR_MTFCS_TRANSFERRING                ETH_MACDBGR_MTFCS_TRANSFERRING_Msk /* Transferring input frame for transmission                               */
17644 #define ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos           (18U)
17645 #define ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk           (0x1UL << ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos) /*!< 0x00040000 */
17646 #define ETH_MACDBGR_MTFCS_GENERATINGPCF               ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk /* Generating and transmitting a Pause control frame (in full duplex mode) */
17647 #define ETH_MACDBGR_MTFCS_WAITING_Pos                 (17U)
17648 #define ETH_MACDBGR_MTFCS_WAITING_Msk                 (0x1UL << ETH_MACDBGR_MTFCS_WAITING_Pos) /*!< 0x00020000 */
17649 #define ETH_MACDBGR_MTFCS_WAITING                     ETH_MACDBGR_MTFCS_WAITING_Msk /* Waiting for Status of previous frame or IFG/backoff period to be over   */
17650 #define ETH_MACDBGR_MTFCS_IDLE                        0x00000000U              /* Idle                                                                    */
17651 #define ETH_MACDBGR_MMTEA_Pos                         (16U)
17652 #define ETH_MACDBGR_MMTEA_Msk                         (0x1UL << ETH_MACDBGR_MMTEA_Pos) /*!< 0x00010000 */
17653 #define ETH_MACDBGR_MMTEA                             ETH_MACDBGR_MMTEA_Msk    /* MAC MII transmit engine active                                          */
17654 #define ETH_MACDBGR_RFFL_Pos                          (8U)
17655 #define ETH_MACDBGR_RFFL_Msk                          (0x3UL << ETH_MACDBGR_RFFL_Pos) /*!< 0x00000300 */
17656 #define ETH_MACDBGR_RFFL                              ETH_MACDBGR_RFFL_Msk     /* Rx FIFO fill level mask                                                 */
17657 #define ETH_MACDBGR_RFFL_FULL_Pos                     (8U)
17658 #define ETH_MACDBGR_RFFL_FULL_Msk                     (0x3UL << ETH_MACDBGR_RFFL_FULL_Pos) /*!< 0x00000300 */
17659 #define ETH_MACDBGR_RFFL_FULL                         ETH_MACDBGR_RFFL_FULL_Msk /* RxFIFO full                                                             */
17660 #define ETH_MACDBGR_RFFL_ABOVEFCT_Pos                 (9U)
17661 #define ETH_MACDBGR_RFFL_ABOVEFCT_Msk                 (0x1UL << ETH_MACDBGR_RFFL_ABOVEFCT_Pos) /*!< 0x00000200 */
17662 #define ETH_MACDBGR_RFFL_ABOVEFCT                     ETH_MACDBGR_RFFL_ABOVEFCT_Msk /* RxFIFO fill-level above flow-control activate threshold                 */
17663 #define ETH_MACDBGR_RFFL_BELOWFCT_Pos                 (8U)
17664 #define ETH_MACDBGR_RFFL_BELOWFCT_Msk                 (0x1UL << ETH_MACDBGR_RFFL_BELOWFCT_Pos) /*!< 0x00000100 */
17665 #define ETH_MACDBGR_RFFL_BELOWFCT                     ETH_MACDBGR_RFFL_BELOWFCT_Msk /* RxFIFO fill-level below flow-control de-activate threshold              */
17666 #define ETH_MACDBGR_RFFL_EMPTY                        0x00000000U              /* RxFIFO empty                                                            */
17667 #define ETH_MACDBGR_RFRCS_Pos                         (5U)
17668 #define ETH_MACDBGR_RFRCS_Msk                         (0x3UL << ETH_MACDBGR_RFRCS_Pos) /*!< 0x00000060 */
17669 #define ETH_MACDBGR_RFRCS                             ETH_MACDBGR_RFRCS_Msk    /* Rx FIFO read controller status mask                                     */
17670 #define ETH_MACDBGR_RFRCS_FLUSHING_Pos                (5U)
17671 #define ETH_MACDBGR_RFRCS_FLUSHING_Msk                (0x3UL << ETH_MACDBGR_RFRCS_FLUSHING_Pos) /*!< 0x00000060 */
17672 #define ETH_MACDBGR_RFRCS_FLUSHING                    ETH_MACDBGR_RFRCS_FLUSHING_Msk /* Flushing the frame data and status                                      */
17673 #define ETH_MACDBGR_RFRCS_STATUSREADING_Pos           (6U)
17674 #define ETH_MACDBGR_RFRCS_STATUSREADING_Msk           (0x1UL << ETH_MACDBGR_RFRCS_STATUSREADING_Pos) /*!< 0x00000040 */
17675 #define ETH_MACDBGR_RFRCS_STATUSREADING               ETH_MACDBGR_RFRCS_STATUSREADING_Msk /* Reading frame status (or time-stamp)                                    */
17676 #define ETH_MACDBGR_RFRCS_DATAREADING_Pos             (5U)
17677 #define ETH_MACDBGR_RFRCS_DATAREADING_Msk             (0x1UL << ETH_MACDBGR_RFRCS_DATAREADING_Pos) /*!< 0x00000020 */
17678 #define ETH_MACDBGR_RFRCS_DATAREADING                 ETH_MACDBGR_RFRCS_DATAREADING_Msk /* Reading frame data                                                      */
17679 #define ETH_MACDBGR_RFRCS_IDLE                        0x00000000U              /* IDLE state                                                              */
17680 #define ETH_MACDBGR_RFWRA_Pos                         (4U)
17681 #define ETH_MACDBGR_RFWRA_Msk                         (0x1UL << ETH_MACDBGR_RFWRA_Pos) /*!< 0x00000010 */
17682 #define ETH_MACDBGR_RFWRA                             ETH_MACDBGR_RFWRA_Msk    /* Rx FIFO write controller active                                         */
17683 #define ETH_MACDBGR_MSFRWCS_Pos                       (1U)
17684 #define ETH_MACDBGR_MSFRWCS_Msk                       (0x3UL << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000006 */
17685 #define ETH_MACDBGR_MSFRWCS                           ETH_MACDBGR_MSFRWCS_Msk  /* MAC small FIFO read / write controllers status  mask                    */
17686 #define ETH_MACDBGR_MSFRWCS_1                         (0x2UL << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000004 */
17687 #define ETH_MACDBGR_MSFRWCS_0                         (0x1UL << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000002 */
17688 #define ETH_MACDBGR_MMRPEA_Pos                        (0U)
17689 #define ETH_MACDBGR_MMRPEA_Msk                        (0x1UL << ETH_MACDBGR_MMRPEA_Pos) /*!< 0x00000001 */
17690 #define ETH_MACDBGR_MMRPEA                            ETH_MACDBGR_MMRPEA_Msk   /* MAC MII receive protocol engine active                                  */
17691 
17692 /* Bit definition for Ethernet MAC Status Register */
17693 #define ETH_MACSR_TSTS_Pos                            (9U)
17694 #define ETH_MACSR_TSTS_Msk                            (0x1UL << ETH_MACSR_TSTS_Pos) /*!< 0x00000200 */
17695 #define ETH_MACSR_TSTS                                ETH_MACSR_TSTS_Msk       /* Time stamp trigger status */
17696 #define ETH_MACSR_MMCTS_Pos                           (6U)
17697 #define ETH_MACSR_MMCTS_Msk                           (0x1UL << ETH_MACSR_MMCTS_Pos) /*!< 0x00000040 */
17698 #define ETH_MACSR_MMCTS                               ETH_MACSR_MMCTS_Msk      /* MMC transmit status       */
17699 #define ETH_MACSR_MMMCRS_Pos                          (5U)
17700 #define ETH_MACSR_MMMCRS_Msk                          (0x1UL << ETH_MACSR_MMMCRS_Pos) /*!< 0x00000020 */
17701 #define ETH_MACSR_MMMCRS                              ETH_MACSR_MMMCRS_Msk     /* MMC receive status        */
17702 #define ETH_MACSR_MMCS_Pos                            (4U)
17703 #define ETH_MACSR_MMCS_Msk                            (0x1UL << ETH_MACSR_MMCS_Pos) /*!< 0x00000010 */
17704 #define ETH_MACSR_MMCS                                ETH_MACSR_MMCS_Msk       /* MMC status                */
17705 #define ETH_MACSR_PMTS_Pos                            (3U)
17706 #define ETH_MACSR_PMTS_Msk                            (0x1UL << ETH_MACSR_PMTS_Pos) /*!< 0x00000008 */
17707 #define ETH_MACSR_PMTS                                ETH_MACSR_PMTS_Msk       /* PMT status                */
17708 
17709 /* Bit definition for Ethernet MAC Interrupt Mask Register */
17710 #define ETH_MACIMR_TSTIM_Pos                          (9U)
17711 #define ETH_MACIMR_TSTIM_Msk                          (0x1UL << ETH_MACIMR_TSTIM_Pos) /*!< 0x00000200 */
17712 #define ETH_MACIMR_TSTIM                              ETH_MACIMR_TSTIM_Msk     /* Time stamp trigger interrupt mask */
17713 #define ETH_MACIMR_PMTIM_Pos                          (3U)
17714 #define ETH_MACIMR_PMTIM_Msk                          (0x1UL << ETH_MACIMR_PMTIM_Pos) /*!< 0x00000008 */
17715 #define ETH_MACIMR_PMTIM                              ETH_MACIMR_PMTIM_Msk     /* PMT interrupt mask                */
17716 
17717 /* Bit definition for Ethernet MAC Address0 High Register */
17718 #define ETH_MACA0HR_MACA0H_Pos                        (0U)
17719 #define ETH_MACA0HR_MACA0H_Msk                        (0xFFFFUL << ETH_MACA0HR_MACA0H_Pos) /*!< 0x0000FFFF */
17720 #define ETH_MACA0HR_MACA0H                            ETH_MACA0HR_MACA0H_Msk   /* MAC address0 high */
17721 
17722 /* Bit definition for Ethernet MAC Address0 Low Register */
17723 #define ETH_MACA0LR_MACA0L_Pos                        (0U)
17724 #define ETH_MACA0LR_MACA0L_Msk                        (0xFFFFFFFFUL << ETH_MACA0LR_MACA0L_Pos) /*!< 0xFFFFFFFF */
17725 #define ETH_MACA0LR_MACA0L                            ETH_MACA0LR_MACA0L_Msk   /* MAC address0 low */
17726 
17727 /* Bit definition for Ethernet MAC Address1 High Register */
17728 #define ETH_MACA1HR_AE_Pos                            (31U)
17729 #define ETH_MACA1HR_AE_Msk                            (0x1UL << ETH_MACA1HR_AE_Pos) /*!< 0x80000000 */
17730 #define ETH_MACA1HR_AE                                ETH_MACA1HR_AE_Msk       /* Address enable */
17731 #define ETH_MACA1HR_SA_Pos                            (30U)
17732 #define ETH_MACA1HR_SA_Msk                            (0x1UL << ETH_MACA1HR_SA_Pos) /*!< 0x40000000 */
17733 #define ETH_MACA1HR_SA                                ETH_MACA1HR_SA_Msk       /* Source address */
17734 #define ETH_MACA1HR_MBC_Pos                           (24U)
17735 #define ETH_MACA1HR_MBC_Msk                           (0x3FUL << ETH_MACA1HR_MBC_Pos) /*!< 0x3F000000 */
17736 #define ETH_MACA1HR_MBC                               ETH_MACA1HR_MBC_Msk      /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
17737 #define ETH_MACA1HR_MBC_HBits15_8                     0x20000000U              /* Mask MAC Address high reg bits [15:8] */
17738 #define ETH_MACA1HR_MBC_HBits7_0                      0x10000000U              /* Mask MAC Address high reg bits [7:0]  */
17739 #define ETH_MACA1HR_MBC_LBits31_24                    0x08000000U              /* Mask MAC Address low reg bits [31:24] */
17740 #define ETH_MACA1HR_MBC_LBits23_16                    0x04000000U              /* Mask MAC Address low reg bits [23:16] */
17741 #define ETH_MACA1HR_MBC_LBits15_8                     0x02000000U              /* Mask MAC Address low reg bits [15:8]  */
17742 #define ETH_MACA1HR_MBC_LBits7_0                      0x01000000U              /* Mask MAC Address low reg bits [7:0]   */
17743 #define ETH_MACA1HR_MACA1H_Pos                        (0U)
17744 #define ETH_MACA1HR_MACA1H_Msk                        (0xFFFFUL << ETH_MACA1HR_MACA1H_Pos) /*!< 0x0000FFFF */
17745 #define ETH_MACA1HR_MACA1H                            ETH_MACA1HR_MACA1H_Msk   /* MAC address1 high */
17746 
17747 /* Bit definition for Ethernet MAC Address1 Low Register */
17748 #define ETH_MACA1LR_MACA1L_Pos                        (0U)
17749 #define ETH_MACA1LR_MACA1L_Msk                        (0xFFFFFFFFUL << ETH_MACA1LR_MACA1L_Pos) /*!< 0xFFFFFFFF */
17750 #define ETH_MACA1LR_MACA1L                            ETH_MACA1LR_MACA1L_Msk   /* MAC address1 low */
17751 
17752 /* Bit definition for Ethernet MAC Address2 High Register */
17753 #define ETH_MACA2HR_AE_Pos                            (31U)
17754 #define ETH_MACA2HR_AE_Msk                            (0x1UL << ETH_MACA2HR_AE_Pos) /*!< 0x80000000 */
17755 #define ETH_MACA2HR_AE                                ETH_MACA2HR_AE_Msk       /* Address enable */
17756 #define ETH_MACA2HR_SA_Pos                            (30U)
17757 #define ETH_MACA2HR_SA_Msk                            (0x1UL << ETH_MACA2HR_SA_Pos) /*!< 0x40000000 */
17758 #define ETH_MACA2HR_SA                                ETH_MACA2HR_SA_Msk       /* Source address */
17759 #define ETH_MACA2HR_MBC_Pos                           (24U)
17760 #define ETH_MACA2HR_MBC_Msk                           (0x3FUL << ETH_MACA2HR_MBC_Pos) /*!< 0x3F000000 */
17761 #define ETH_MACA2HR_MBC                               ETH_MACA2HR_MBC_Msk      /* Mask byte control */
17762 #define ETH_MACA2HR_MBC_HBits15_8                     0x20000000U              /* Mask MAC Address high reg bits [15:8] */
17763 #define ETH_MACA2HR_MBC_HBits7_0                      0x10000000U              /* Mask MAC Address high reg bits [7:0]  */
17764 #define ETH_MACA2HR_MBC_LBits31_24                    0x08000000U              /* Mask MAC Address low reg bits [31:24] */
17765 #define ETH_MACA2HR_MBC_LBits23_16                    0x04000000U              /* Mask MAC Address low reg bits [23:16] */
17766 #define ETH_MACA2HR_MBC_LBits15_8                     0x02000000U              /* Mask MAC Address low reg bits [15:8]  */
17767 #define ETH_MACA2HR_MBC_LBits7_0                      0x01000000U              /* Mask MAC Address low reg bits [70]    */
17768 #define ETH_MACA2HR_MACA2H_Pos                        (0U)
17769 #define ETH_MACA2HR_MACA2H_Msk                        (0xFFFFUL << ETH_MACA2HR_MACA2H_Pos) /*!< 0x0000FFFF */
17770 #define ETH_MACA2HR_MACA2H                            ETH_MACA2HR_MACA2H_Msk   /* MAC address1 high */
17771 
17772 /* Bit definition for Ethernet MAC Address2 Low Register */
17773 #define ETH_MACA2LR_MACA2L_Pos                        (0U)
17774 #define ETH_MACA2LR_MACA2L_Msk                        (0xFFFFFFFFUL << ETH_MACA2LR_MACA2L_Pos) /*!< 0xFFFFFFFF */
17775 #define ETH_MACA2LR_MACA2L                            ETH_MACA2LR_MACA2L_Msk   /* MAC address2 low */
17776 
17777 /* Bit definition for Ethernet MAC Address3 High Register */
17778 #define ETH_MACA3HR_AE_Pos                            (31U)
17779 #define ETH_MACA3HR_AE_Msk                            (0x1UL << ETH_MACA3HR_AE_Pos) /*!< 0x80000000 */
17780 #define ETH_MACA3HR_AE                                ETH_MACA3HR_AE_Msk       /* Address enable */
17781 #define ETH_MACA3HR_SA_Pos                            (30U)
17782 #define ETH_MACA3HR_SA_Msk                            (0x1UL << ETH_MACA3HR_SA_Pos) /*!< 0x40000000 */
17783 #define ETH_MACA3HR_SA                                ETH_MACA3HR_SA_Msk       /* Source address */
17784 #define ETH_MACA3HR_MBC_Pos                           (24U)
17785 #define ETH_MACA3HR_MBC_Msk                           (0x3FUL << ETH_MACA3HR_MBC_Pos) /*!< 0x3F000000 */
17786 #define ETH_MACA3HR_MBC                               ETH_MACA3HR_MBC_Msk      /* Mask byte control */
17787 #define ETH_MACA3HR_MBC_HBits15_8                     0x20000000U              /* Mask MAC Address high reg bits [15:8] */
17788 #define ETH_MACA3HR_MBC_HBits7_0                      0x10000000U              /* Mask MAC Address high reg bits [7:0]  */
17789 #define ETH_MACA3HR_MBC_LBits31_24                    0x08000000U              /* Mask MAC Address low reg bits [31:24] */
17790 #define ETH_MACA3HR_MBC_LBits23_16                    0x04000000U              /* Mask MAC Address low reg bits [23:16] */
17791 #define ETH_MACA3HR_MBC_LBits15_8                     0x02000000U              /* Mask MAC Address low reg bits [15:8]  */
17792 #define ETH_MACA3HR_MBC_LBits7_0                      0x01000000U              /* Mask MAC Address low reg bits [70]    */
17793 #define ETH_MACA3HR_MACA3H_Pos                        (0U)
17794 #define ETH_MACA3HR_MACA3H_Msk                        (0xFFFFUL << ETH_MACA3HR_MACA3H_Pos) /*!< 0x0000FFFF */
17795 #define ETH_MACA3HR_MACA3H                            ETH_MACA3HR_MACA3H_Msk   /* MAC address3 high */
17796 
17797 /* Bit definition for Ethernet MAC Address3 Low Register */
17798 #define ETH_MACA3LR_MACA3L_Pos                        (0U)
17799 #define ETH_MACA3LR_MACA3L_Msk                        (0xFFFFFFFFUL << ETH_MACA3LR_MACA3L_Pos) /*!< 0xFFFFFFFF */
17800 #define ETH_MACA3LR_MACA3L                            ETH_MACA3LR_MACA3L_Msk   /* MAC address3 low */
17801 
17802 /******************************************************************************/
17803 /*                Ethernet MMC Registers bits definition                      */
17804 /******************************************************************************/
17805 
17806 /* Bit definition for Ethernet MMC Contol Register */
17807 #define ETH_MMCCR_MCFHP_Pos                           (5U)
17808 #define ETH_MMCCR_MCFHP_Msk                           (0x1UL << ETH_MMCCR_MCFHP_Pos) /*!< 0x00000020 */
17809 #define ETH_MMCCR_MCFHP                               ETH_MMCCR_MCFHP_Msk      /* MMC counter Full-Half preset */
17810 #define ETH_MMCCR_MCP_Pos                             (4U)
17811 #define ETH_MMCCR_MCP_Msk                             (0x1UL << ETH_MMCCR_MCP_Pos) /*!< 0x00000010 */
17812 #define ETH_MMCCR_MCP                                 ETH_MMCCR_MCP_Msk        /* MMC counter preset           */
17813 #define ETH_MMCCR_MCF_Pos                             (3U)
17814 #define ETH_MMCCR_MCF_Msk                             (0x1UL << ETH_MMCCR_MCF_Pos) /*!< 0x00000008 */
17815 #define ETH_MMCCR_MCF                                 ETH_MMCCR_MCF_Msk        /* MMC Counter Freeze           */
17816 #define ETH_MMCCR_ROR_Pos                             (2U)
17817 #define ETH_MMCCR_ROR_Msk                             (0x1UL << ETH_MMCCR_ROR_Pos) /*!< 0x00000004 */
17818 #define ETH_MMCCR_ROR                                 ETH_MMCCR_ROR_Msk        /* Reset on Read                */
17819 #define ETH_MMCCR_CSR_Pos                             (1U)
17820 #define ETH_MMCCR_CSR_Msk                             (0x1UL << ETH_MMCCR_CSR_Pos) /*!< 0x00000002 */
17821 #define ETH_MMCCR_CSR                                 ETH_MMCCR_CSR_Msk        /* Counter Stop Rollover        */
17822 #define ETH_MMCCR_CR_Pos                              (0U)
17823 #define ETH_MMCCR_CR_Msk                              (0x1UL << ETH_MMCCR_CR_Pos) /*!< 0x00000001 */
17824 #define ETH_MMCCR_CR                                  ETH_MMCCR_CR_Msk         /* Counters Reset               */
17825 
17826 /* Bit definition for Ethernet MMC Receive Interrupt Register */
17827 #define ETH_MMCRIR_RGUFS_Pos                          (17U)
17828 #define ETH_MMCRIR_RGUFS_Msk                          (0x1UL << ETH_MMCRIR_RGUFS_Pos) /*!< 0x00020000 */
17829 #define ETH_MMCRIR_RGUFS                              ETH_MMCRIR_RGUFS_Msk     /* Set when Rx good unicast frames counter reaches half the maximum value */
17830 #define ETH_MMCRIR_RFAES_Pos                          (6U)
17831 #define ETH_MMCRIR_RFAES_Msk                          (0x1UL << ETH_MMCRIR_RFAES_Pos) /*!< 0x00000040 */
17832 #define ETH_MMCRIR_RFAES                              ETH_MMCRIR_RFAES_Msk     /* Set when Rx alignment error counter reaches half the maximum value */
17833 #define ETH_MMCRIR_RFCES_Pos                          (5U)
17834 #define ETH_MMCRIR_RFCES_Msk                          (0x1UL << ETH_MMCRIR_RFCES_Pos) /*!< 0x00000020 */
17835 #define ETH_MMCRIR_RFCES                              ETH_MMCRIR_RFCES_Msk     /* Set when Rx crc error counter reaches half the maximum value */
17836 
17837 /* Bit definition for Ethernet MMC Transmit Interrupt Register */
17838 #define ETH_MMCTIR_TGFS_Pos                           (21U)
17839 #define ETH_MMCTIR_TGFS_Msk                           (0x1UL << ETH_MMCTIR_TGFS_Pos) /*!< 0x00200000 */
17840 #define ETH_MMCTIR_TGFS                               ETH_MMCTIR_TGFS_Msk      /* Set when Tx good frame count counter reaches half the maximum value */
17841 #define ETH_MMCTIR_TGFMSCS_Pos                        (15U)
17842 #define ETH_MMCTIR_TGFMSCS_Msk                        (0x1UL << ETH_MMCTIR_TGFMSCS_Pos) /*!< 0x00008000 */
17843 #define ETH_MMCTIR_TGFMSCS                            ETH_MMCTIR_TGFMSCS_Msk   /* Set when Tx good multi col counter reaches half the maximum value */
17844 #define ETH_MMCTIR_TGFSCS_Pos                         (14U)
17845 #define ETH_MMCTIR_TGFSCS_Msk                         (0x1UL << ETH_MMCTIR_TGFSCS_Pos) /*!< 0x00004000 */
17846 #define ETH_MMCTIR_TGFSCS                             ETH_MMCTIR_TGFSCS_Msk    /* Set when Tx good single col counter reaches half the maximum value */
17847 
17848 /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
17849 #define ETH_MMCRIMR_RGUFM_Pos                         (17U)
17850 #define ETH_MMCRIMR_RGUFM_Msk                         (0x1UL << ETH_MMCRIMR_RGUFM_Pos) /*!< 0x00020000 */
17851 #define ETH_MMCRIMR_RGUFM                             ETH_MMCRIMR_RGUFM_Msk    /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
17852 #define ETH_MMCRIMR_RFAEM_Pos                         (6U)
17853 #define ETH_MMCRIMR_RFAEM_Msk                         (0x1UL << ETH_MMCRIMR_RFAEM_Pos) /*!< 0x00000040 */
17854 #define ETH_MMCRIMR_RFAEM                             ETH_MMCRIMR_RFAEM_Msk    /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
17855 #define ETH_MMCRIMR_RFCEM_Pos                         (5U)
17856 #define ETH_MMCRIMR_RFCEM_Msk                         (0x1UL << ETH_MMCRIMR_RFCEM_Pos) /*!< 0x00000020 */
17857 #define ETH_MMCRIMR_RFCEM                             ETH_MMCRIMR_RFCEM_Msk    /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
17858 
17859 /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
17860 #define ETH_MMCTIMR_TGFM_Pos                          (21U)
17861 #define ETH_MMCTIMR_TGFM_Msk                          (0x1UL << ETH_MMCTIMR_TGFM_Pos) /*!< 0x00200000 */
17862 #define ETH_MMCTIMR_TGFM                              ETH_MMCTIMR_TGFM_Msk     /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
17863 #define ETH_MMCTIMR_TGFMSCM_Pos                       (15U)
17864 #define ETH_MMCTIMR_TGFMSCM_Msk                       (0x1UL << ETH_MMCTIMR_TGFMSCM_Pos) /*!< 0x00008000 */
17865 #define ETH_MMCTIMR_TGFMSCM                           ETH_MMCTIMR_TGFMSCM_Msk  /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
17866 #define ETH_MMCTIMR_TGFSCM_Pos                        (14U)
17867 #define ETH_MMCTIMR_TGFSCM_Msk                        (0x1UL << ETH_MMCTIMR_TGFSCM_Pos) /*!< 0x00004000 */
17868 #define ETH_MMCTIMR_TGFSCM                            ETH_MMCTIMR_TGFSCM_Msk   /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
17869 
17870 /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
17871 #define ETH_MMCTGFSCCR_TGFSCC_Pos                     (0U)
17872 #define ETH_MMCTGFSCCR_TGFSCC_Msk                     (0xFFFFFFFFUL << ETH_MMCTGFSCCR_TGFSCC_Pos) /*!< 0xFFFFFFFF */
17873 #define ETH_MMCTGFSCCR_TGFSCC                         ETH_MMCTGFSCCR_TGFSCC_Msk /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
17874 
17875 /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
17876 #define ETH_MMCTGFMSCCR_TGFMSCC_Pos                   (0U)
17877 #define ETH_MMCTGFMSCCR_TGFMSCC_Msk                   (0xFFFFFFFFUL << ETH_MMCTGFMSCCR_TGFMSCC_Pos) /*!< 0xFFFFFFFF */
17878 #define ETH_MMCTGFMSCCR_TGFMSCC                       ETH_MMCTGFMSCCR_TGFMSCC_Msk /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
17879 
17880 /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
17881 #define ETH_MMCTGFCR_TGFC_Pos                         (0U)
17882 #define ETH_MMCTGFCR_TGFC_Msk                         (0xFFFFFFFFUL << ETH_MMCTGFCR_TGFC_Pos) /*!< 0xFFFFFFFF */
17883 #define ETH_MMCTGFCR_TGFC                             ETH_MMCTGFCR_TGFC_Msk    /* Number of good frames transmitted. */
17884 
17885 /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
17886 #define ETH_MMCRFCECR_RFCEC_Pos                       (0U)
17887 #define ETH_MMCRFCECR_RFCEC_Msk                       (0xFFFFFFFFUL << ETH_MMCRFCECR_RFCEC_Pos) /*!< 0xFFFFFFFF */
17888 #define ETH_MMCRFCECR_RFCEC                           ETH_MMCRFCECR_RFCEC_Msk  /* Number of frames received with CRC error. */
17889 
17890 /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
17891 #define ETH_MMCRFAECR_RFAEC_Pos                       (0U)
17892 #define ETH_MMCRFAECR_RFAEC_Msk                       (0xFFFFFFFFUL << ETH_MMCRFAECR_RFAEC_Pos) /*!< 0xFFFFFFFF */
17893 #define ETH_MMCRFAECR_RFAEC                           ETH_MMCRFAECR_RFAEC_Msk  /* Number of frames received with alignment (dribble) error */
17894 
17895 /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
17896 #define ETH_MMCRGUFCR_RGUFC_Pos                       (0U)
17897 #define ETH_MMCRGUFCR_RGUFC_Msk                       (0xFFFFFFFFUL << ETH_MMCRGUFCR_RGUFC_Pos) /*!< 0xFFFFFFFF */
17898 #define ETH_MMCRGUFCR_RGUFC                           ETH_MMCRGUFCR_RGUFC_Msk  /* Number of good unicast frames received. */
17899 
17900 /******************************************************************************/
17901 /*               Ethernet PTP Registers bits definition                       */
17902 /******************************************************************************/
17903 
17904 /* Bit definition for Ethernet PTP Time Stamp Contol Register */
17905 #define ETH_PTPTSCR_TSCNT_Pos                         (16U)
17906 #define ETH_PTPTSCR_TSCNT_Msk                         (0x3UL << ETH_PTPTSCR_TSCNT_Pos) /*!< 0x00030000 */
17907 #define ETH_PTPTSCR_TSCNT                             ETH_PTPTSCR_TSCNT_Msk    /* Time stamp clock node type */
17908 #define ETH_PTPTSSR_TSSMRME_Pos                       (15U)
17909 #define ETH_PTPTSSR_TSSMRME_Msk                       (0x1UL << ETH_PTPTSSR_TSSMRME_Pos) /*!< 0x00008000 */
17910 #define ETH_PTPTSSR_TSSMRME                           ETH_PTPTSSR_TSSMRME_Msk  /* Time stamp snapshot for message relevant to master enable */
17911 #define ETH_PTPTSSR_TSSEME_Pos                        (14U)
17912 #define ETH_PTPTSSR_TSSEME_Msk                        (0x1UL << ETH_PTPTSSR_TSSEME_Pos) /*!< 0x00004000 */
17913 #define ETH_PTPTSSR_TSSEME                            ETH_PTPTSSR_TSSEME_Msk   /* Time stamp snapshot for event message enable */
17914 #define ETH_PTPTSSR_TSSIPV4FE_Pos                     (13U)
17915 #define ETH_PTPTSSR_TSSIPV4FE_Msk                     (0x1UL << ETH_PTPTSSR_TSSIPV4FE_Pos) /*!< 0x00002000 */
17916 #define ETH_PTPTSSR_TSSIPV4FE                         ETH_PTPTSSR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */
17917 #define ETH_PTPTSSR_TSSIPV6FE_Pos                     (12U)
17918 #define ETH_PTPTSSR_TSSIPV6FE_Msk                     (0x1UL << ETH_PTPTSSR_TSSIPV6FE_Pos) /*!< 0x00001000 */
17919 #define ETH_PTPTSSR_TSSIPV6FE                         ETH_PTPTSSR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */
17920 #define ETH_PTPTSSR_TSSPTPOEFE_Pos                    (11U)
17921 #define ETH_PTPTSSR_TSSPTPOEFE_Msk                    (0x1UL << ETH_PTPTSSR_TSSPTPOEFE_Pos) /*!< 0x00000800 */
17922 #define ETH_PTPTSSR_TSSPTPOEFE                        ETH_PTPTSSR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */
17923 #define ETH_PTPTSSR_TSPTPPSV2E_Pos                    (10U)
17924 #define ETH_PTPTSSR_TSPTPPSV2E_Msk                    (0x1UL << ETH_PTPTSSR_TSPTPPSV2E_Pos) /*!< 0x00000400 */
17925 #define ETH_PTPTSSR_TSPTPPSV2E                        ETH_PTPTSSR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */
17926 #define ETH_PTPTSSR_TSSSR_Pos                         (9U)
17927 #define ETH_PTPTSSR_TSSSR_Msk                         (0x1UL << ETH_PTPTSSR_TSSSR_Pos) /*!< 0x00000200 */
17928 #define ETH_PTPTSSR_TSSSR                             ETH_PTPTSSR_TSSSR_Msk    /* Time stamp Sub-seconds rollover */
17929 #define ETH_PTPTSSR_TSSARFE_Pos                       (8U)
17930 #define ETH_PTPTSSR_TSSARFE_Msk                       (0x1UL << ETH_PTPTSSR_TSSARFE_Pos) /*!< 0x00000100 */
17931 #define ETH_PTPTSSR_TSSARFE                           ETH_PTPTSSR_TSSARFE_Msk  /* Time stamp snapshot for all received frames enable */
17932 
17933 #define ETH_PTPTSCR_TSARU_Pos                         (5U)
17934 #define ETH_PTPTSCR_TSARU_Msk                         (0x1UL << ETH_PTPTSCR_TSARU_Pos) /*!< 0x00000020 */
17935 #define ETH_PTPTSCR_TSARU                             ETH_PTPTSCR_TSARU_Msk    /* Addend register update */
17936 #define ETH_PTPTSCR_TSITE_Pos                         (4U)
17937 #define ETH_PTPTSCR_TSITE_Msk                         (0x1UL << ETH_PTPTSCR_TSITE_Pos) /*!< 0x00000010 */
17938 #define ETH_PTPTSCR_TSITE                             ETH_PTPTSCR_TSITE_Msk    /* Time stamp interrupt trigger enable */
17939 #define ETH_PTPTSCR_TSSTU_Pos                         (3U)
17940 #define ETH_PTPTSCR_TSSTU_Msk                         (0x1UL << ETH_PTPTSCR_TSSTU_Pos) /*!< 0x00000008 */
17941 #define ETH_PTPTSCR_TSSTU                             ETH_PTPTSCR_TSSTU_Msk    /* Time stamp update */
17942 #define ETH_PTPTSCR_TSSTI_Pos                         (2U)
17943 #define ETH_PTPTSCR_TSSTI_Msk                         (0x1UL << ETH_PTPTSCR_TSSTI_Pos) /*!< 0x00000004 */
17944 #define ETH_PTPTSCR_TSSTI                             ETH_PTPTSCR_TSSTI_Msk    /* Time stamp initialize */
17945 #define ETH_PTPTSCR_TSFCU_Pos                         (1U)
17946 #define ETH_PTPTSCR_TSFCU_Msk                         (0x1UL << ETH_PTPTSCR_TSFCU_Pos) /*!< 0x00000002 */
17947 #define ETH_PTPTSCR_TSFCU                             ETH_PTPTSCR_TSFCU_Msk    /* Time stamp fine or coarse update */
17948 #define ETH_PTPTSCR_TSE_Pos                           (0U)
17949 #define ETH_PTPTSCR_TSE_Msk                           (0x1UL << ETH_PTPTSCR_TSE_Pos) /*!< 0x00000001 */
17950 #define ETH_PTPTSCR_TSE                               ETH_PTPTSCR_TSE_Msk      /* Time stamp enable */
17951 
17952 /* Bit definition for Ethernet PTP Sub-Second Increment Register */
17953 #define ETH_PTPSSIR_STSSI_Pos                         (0U)
17954 #define ETH_PTPSSIR_STSSI_Msk                         (0xFFUL << ETH_PTPSSIR_STSSI_Pos) /*!< 0x000000FF */
17955 #define ETH_PTPSSIR_STSSI                             ETH_PTPSSIR_STSSI_Msk    /* System time Sub-second increment value */
17956 
17957 /* Bit definition for Ethernet PTP Time Stamp High Register */
17958 #define ETH_PTPTSHR_STS_Pos                           (0U)
17959 #define ETH_PTPTSHR_STS_Msk                           (0xFFFFFFFFUL << ETH_PTPTSHR_STS_Pos) /*!< 0xFFFFFFFF */
17960 #define ETH_PTPTSHR_STS                               ETH_PTPTSHR_STS_Msk      /* System Time second */
17961 
17962 /* Bit definition for Ethernet PTP Time Stamp Low Register */
17963 #define ETH_PTPTSLR_STPNS_Pos                         (31U)
17964 #define ETH_PTPTSLR_STPNS_Msk                         (0x1UL << ETH_PTPTSLR_STPNS_Pos) /*!< 0x80000000 */
17965 #define ETH_PTPTSLR_STPNS                             ETH_PTPTSLR_STPNS_Msk    /* System Time Positive or negative time */
17966 #define ETH_PTPTSLR_STSS_Pos                          (0U)
17967 #define ETH_PTPTSLR_STSS_Msk                          (0x7FFFFFFFUL << ETH_PTPTSLR_STSS_Pos) /*!< 0x7FFFFFFF */
17968 #define ETH_PTPTSLR_STSS                              ETH_PTPTSLR_STSS_Msk     /* System Time sub-seconds */
17969 
17970 /* Bit definition for Ethernet PTP Time Stamp High Update Register */
17971 #define ETH_PTPTSHUR_TSUS_Pos                         (0U)
17972 #define ETH_PTPTSHUR_TSUS_Msk                         (0xFFFFFFFFUL << ETH_PTPTSHUR_TSUS_Pos) /*!< 0xFFFFFFFF */
17973 #define ETH_PTPTSHUR_TSUS                             ETH_PTPTSHUR_TSUS_Msk    /* Time stamp update seconds */
17974 
17975 /* Bit definition for Ethernet PTP Time Stamp Low Update Register */
17976 #define ETH_PTPTSLUR_TSUPNS_Pos                       (31U)
17977 #define ETH_PTPTSLUR_TSUPNS_Msk                       (0x1UL << ETH_PTPTSLUR_TSUPNS_Pos) /*!< 0x80000000 */
17978 #define ETH_PTPTSLUR_TSUPNS                           ETH_PTPTSLUR_TSUPNS_Msk  /* Time stamp update Positive or negative time */
17979 #define ETH_PTPTSLUR_TSUSS_Pos                        (0U)
17980 #define ETH_PTPTSLUR_TSUSS_Msk                        (0x7FFFFFFFUL << ETH_PTPTSLUR_TSUSS_Pos) /*!< 0x7FFFFFFF */
17981 #define ETH_PTPTSLUR_TSUSS                            ETH_PTPTSLUR_TSUSS_Msk   /* Time stamp update sub-seconds */
17982 
17983 /* Bit definition for Ethernet PTP Time Stamp Addend Register */
17984 #define ETH_PTPTSAR_TSA_Pos                           (0U)
17985 #define ETH_PTPTSAR_TSA_Msk                           (0xFFFFFFFFUL << ETH_PTPTSAR_TSA_Pos) /*!< 0xFFFFFFFF */
17986 #define ETH_PTPTSAR_TSA                               ETH_PTPTSAR_TSA_Msk      /* Time stamp addend */
17987 
17988 /* Bit definition for Ethernet PTP Target Time High Register */
17989 #define ETH_PTPTTHR_TTSH_Pos                          (0U)
17990 #define ETH_PTPTTHR_TTSH_Msk                          (0xFFFFFFFFUL << ETH_PTPTTHR_TTSH_Pos) /*!< 0xFFFFFFFF */
17991 #define ETH_PTPTTHR_TTSH                              ETH_PTPTTHR_TTSH_Msk     /* Target time stamp high */
17992 
17993 /* Bit definition for Ethernet PTP Target Time Low Register */
17994 #define ETH_PTPTTLR_TTSL_Pos                          (0U)
17995 #define ETH_PTPTTLR_TTSL_Msk                          (0xFFFFFFFFUL << ETH_PTPTTLR_TTSL_Pos) /*!< 0xFFFFFFFF */
17996 #define ETH_PTPTTLR_TTSL                              ETH_PTPTTLR_TTSL_Msk     /* Target time stamp low */
17997 
17998 /* Bit definition for Ethernet PTP Time Stamp Status Register */
17999 #define ETH_PTPTSSR_TSTTR_Pos                         (5U)
18000 #define ETH_PTPTSSR_TSTTR_Msk                         (0x1UL << ETH_PTPTSSR_TSTTR_Pos) /*!< 0x00000020 */
18001 #define ETH_PTPTSSR_TSTTR                             ETH_PTPTSSR_TSTTR_Msk    /* Time stamp target time reached */
18002 #define ETH_PTPTSSR_TSSO_Pos                          (4U)
18003 #define ETH_PTPTSSR_TSSO_Msk                          (0x1UL << ETH_PTPTSSR_TSSO_Pos) /*!< 0x00000010 */
18004 #define ETH_PTPTSSR_TSSO                              ETH_PTPTSSR_TSSO_Msk     /* Time stamp seconds overflow */
18005 
18006 /******************************************************************************/
18007 /*                 Ethernet DMA Registers bits definition                     */
18008 /******************************************************************************/
18009 
18010 /* Bit definition for Ethernet DMA Bus Mode Register */
18011 #define ETH_DMABMR_AAB_Pos                            (25U)
18012 #define ETH_DMABMR_AAB_Msk                            (0x1UL << ETH_DMABMR_AAB_Pos) /*!< 0x02000000 */
18013 #define ETH_DMABMR_AAB                                ETH_DMABMR_AAB_Msk       /* Address-Aligned beats */
18014 #define ETH_DMABMR_FPM_Pos                            (24U)
18015 #define ETH_DMABMR_FPM_Msk                            (0x1UL << ETH_DMABMR_FPM_Pos) /*!< 0x01000000 */
18016 #define ETH_DMABMR_FPM                                ETH_DMABMR_FPM_Msk       /* 4xPBL mode */
18017 #define ETH_DMABMR_USP_Pos                            (23U)
18018 #define ETH_DMABMR_USP_Msk                            (0x1UL << ETH_DMABMR_USP_Pos) /*!< 0x00800000 */
18019 #define ETH_DMABMR_USP                                ETH_DMABMR_USP_Msk       /* Use separate PBL */
18020 #define ETH_DMABMR_RDP_Pos                            (17U)
18021 #define ETH_DMABMR_RDP_Msk                            (0x3FUL << ETH_DMABMR_RDP_Pos) /*!< 0x007E0000 */
18022 #define ETH_DMABMR_RDP                                ETH_DMABMR_RDP_Msk       /* RxDMA PBL */
18023 #define ETH_DMABMR_RDP_1Beat                          0x00020000U              /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
18024 #define ETH_DMABMR_RDP_2Beat                          0x00040000U              /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
18025 #define ETH_DMABMR_RDP_4Beat                          0x00080000U              /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
18026 #define ETH_DMABMR_RDP_8Beat                          0x00100000U              /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
18027 #define ETH_DMABMR_RDP_16Beat                         0x00200000U              /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
18028 #define ETH_DMABMR_RDP_32Beat                         0x00400000U              /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
18029 #define ETH_DMABMR_RDP_4xPBL_4Beat                    0x01020000U              /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
18030 #define ETH_DMABMR_RDP_4xPBL_8Beat                    0x01040000U              /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
18031 #define ETH_DMABMR_RDP_4xPBL_16Beat                   0x01080000U              /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
18032 #define ETH_DMABMR_RDP_4xPBL_32Beat                   0x01100000U              /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
18033 #define ETH_DMABMR_RDP_4xPBL_64Beat                   0x01200000U              /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
18034 #define ETH_DMABMR_RDP_4xPBL_128Beat                  0x01400000U              /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
18035 #define ETH_DMABMR_FB_Pos                             (16U)
18036 #define ETH_DMABMR_FB_Msk                             (0x1UL << ETH_DMABMR_FB_Pos) /*!< 0x00010000 */
18037 #define ETH_DMABMR_FB                                 ETH_DMABMR_FB_Msk        /* Fixed Burst */
18038 #define ETH_DMABMR_RTPR_Pos                           (14U)
18039 #define ETH_DMABMR_RTPR_Msk                           (0x3UL << ETH_DMABMR_RTPR_Pos) /*!< 0x0000C000 */
18040 #define ETH_DMABMR_RTPR                               ETH_DMABMR_RTPR_Msk      /* Rx Tx priority ratio */
18041 #define ETH_DMABMR_RTPR_1_1                           0x00000000U              /* Rx Tx priority ratio */
18042 #define ETH_DMABMR_RTPR_2_1                           0x00004000U              /* Rx Tx priority ratio */
18043 #define ETH_DMABMR_RTPR_3_1                           0x00008000U              /* Rx Tx priority ratio */
18044 #define ETH_DMABMR_RTPR_4_1                           0x0000C000U              /* Rx Tx priority ratio */
18045 #define ETH_DMABMR_PBL_Pos                            (8U)
18046 #define ETH_DMABMR_PBL_Msk                            (0x3FUL << ETH_DMABMR_PBL_Pos) /*!< 0x00003F00 */
18047 #define ETH_DMABMR_PBL                                ETH_DMABMR_PBL_Msk       /* Programmable burst length */
18048 #define ETH_DMABMR_PBL_1Beat                          0x00000100U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
18049 #define ETH_DMABMR_PBL_2Beat                          0x00000200U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
18050 #define ETH_DMABMR_PBL_4Beat                          0x00000400U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
18051 #define ETH_DMABMR_PBL_8Beat                          0x00000800U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
18052 #define ETH_DMABMR_PBL_16Beat                         0x00001000U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
18053 #define ETH_DMABMR_PBL_32Beat                         0x00002000U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
18054 #define ETH_DMABMR_PBL_4xPBL_4Beat                    0x01000100U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
18055 #define ETH_DMABMR_PBL_4xPBL_8Beat                    0x01000200U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
18056 #define ETH_DMABMR_PBL_4xPBL_16Beat                   0x01000400U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
18057 #define ETH_DMABMR_PBL_4xPBL_32Beat                   0x01000800U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
18058 #define ETH_DMABMR_PBL_4xPBL_64Beat                   0x01001000U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
18059 #define ETH_DMABMR_PBL_4xPBL_128Beat                  0x01002000U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
18060 #define ETH_DMABMR_EDE_Pos                            (7U)
18061 #define ETH_DMABMR_EDE_Msk                            (0x1UL << ETH_DMABMR_EDE_Pos) /*!< 0x00000080 */
18062 #define ETH_DMABMR_EDE                                ETH_DMABMR_EDE_Msk       /* Enhanced Descriptor Enable */
18063 #define ETH_DMABMR_DSL_Pos                            (2U)
18064 #define ETH_DMABMR_DSL_Msk                            (0x1FUL << ETH_DMABMR_DSL_Pos) /*!< 0x0000007C */
18065 #define ETH_DMABMR_DSL                                ETH_DMABMR_DSL_Msk       /* Descriptor Skip Length */
18066 #define ETH_DMABMR_DA_Pos                             (1U)
18067 #define ETH_DMABMR_DA_Msk                             (0x1UL << ETH_DMABMR_DA_Pos) /*!< 0x00000002 */
18068 #define ETH_DMABMR_DA                                 ETH_DMABMR_DA_Msk        /* DMA arbitration scheme */
18069 #define ETH_DMABMR_SR_Pos                             (0U)
18070 #define ETH_DMABMR_SR_Msk                             (0x1UL << ETH_DMABMR_SR_Pos) /*!< 0x00000001 */
18071 #define ETH_DMABMR_SR                                 ETH_DMABMR_SR_Msk        /* Software reset */
18072 
18073 /* Bit definition for Ethernet DMA Transmit Poll Demand Register */
18074 #define ETH_DMATPDR_TPD_Pos                           (0U)
18075 #define ETH_DMATPDR_TPD_Msk                           (0xFFFFFFFFUL << ETH_DMATPDR_TPD_Pos) /*!< 0xFFFFFFFF */
18076 #define ETH_DMATPDR_TPD                               ETH_DMATPDR_TPD_Msk      /* Transmit poll demand */
18077 
18078 /* Bit definition for Ethernet DMA Receive Poll Demand Register */
18079 #define ETH_DMARPDR_RPD_Pos                           (0U)
18080 #define ETH_DMARPDR_RPD_Msk                           (0xFFFFFFFFUL << ETH_DMARPDR_RPD_Pos) /*!< 0xFFFFFFFF */
18081 #define ETH_DMARPDR_RPD                               ETH_DMARPDR_RPD_Msk      /* Receive poll demand  */
18082 
18083 /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
18084 #define ETH_DMARDLAR_SRL_Pos                          (0U)
18085 #define ETH_DMARDLAR_SRL_Msk                          (0xFFFFFFFFUL << ETH_DMARDLAR_SRL_Pos) /*!< 0xFFFFFFFF */
18086 #define ETH_DMARDLAR_SRL                              ETH_DMARDLAR_SRL_Msk     /* Start of receive list */
18087 
18088 /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
18089 #define ETH_DMATDLAR_STL_Pos                          (0U)
18090 #define ETH_DMATDLAR_STL_Msk                          (0xFFFFFFFFUL << ETH_DMATDLAR_STL_Pos) /*!< 0xFFFFFFFF */
18091 #define ETH_DMATDLAR_STL                              ETH_DMATDLAR_STL_Msk     /* Start of transmit list */
18092 
18093 /* Bit definition for Ethernet DMA Status Register */
18094 #define ETH_DMASR_TSTS_Pos                            (29U)
18095 #define ETH_DMASR_TSTS_Msk                            (0x1UL << ETH_DMASR_TSTS_Pos) /*!< 0x20000000 */
18096 #define ETH_DMASR_TSTS                                ETH_DMASR_TSTS_Msk       /* Time-stamp trigger status */
18097 #define ETH_DMASR_PMTS_Pos                            (28U)
18098 #define ETH_DMASR_PMTS_Msk                            (0x1UL << ETH_DMASR_PMTS_Pos) /*!< 0x10000000 */
18099 #define ETH_DMASR_PMTS                                ETH_DMASR_PMTS_Msk       /* PMT status */
18100 #define ETH_DMASR_MMCS_Pos                            (27U)
18101 #define ETH_DMASR_MMCS_Msk                            (0x1UL << ETH_DMASR_MMCS_Pos) /*!< 0x08000000 */
18102 #define ETH_DMASR_MMCS                                ETH_DMASR_MMCS_Msk       /* MMC status */
18103 #define ETH_DMASR_EBS_Pos                             (23U)
18104 #define ETH_DMASR_EBS_Msk                             (0x7UL << ETH_DMASR_EBS_Pos) /*!< 0x03800000 */
18105 #define ETH_DMASR_EBS                                 ETH_DMASR_EBS_Msk        /* Error bits status */
18106   /* combination with EBS[2:0] for GetFlagStatus function */
18107 #define ETH_DMASR_EBS_DescAccess_Pos                  (25U)
18108 #define ETH_DMASR_EBS_DescAccess_Msk                  (0x1UL << ETH_DMASR_EBS_DescAccess_Pos) /*!< 0x02000000 */
18109 #define ETH_DMASR_EBS_DescAccess                      ETH_DMASR_EBS_DescAccess_Msk /* Error bits 0-data buffer, 1-desc. access */
18110 #define ETH_DMASR_EBS_ReadTransf_Pos                  (24U)
18111 #define ETH_DMASR_EBS_ReadTransf_Msk                  (0x1UL << ETH_DMASR_EBS_ReadTransf_Pos) /*!< 0x01000000 */
18112 #define ETH_DMASR_EBS_ReadTransf                      ETH_DMASR_EBS_ReadTransf_Msk /* Error bits 0-write trnsf, 1-read transfr */
18113 #define ETH_DMASR_EBS_DataTransfTx_Pos                (23U)
18114 #define ETH_DMASR_EBS_DataTransfTx_Msk                (0x1UL << ETH_DMASR_EBS_DataTransfTx_Pos) /*!< 0x00800000 */
18115 #define ETH_DMASR_EBS_DataTransfTx                    ETH_DMASR_EBS_DataTransfTx_Msk /* Error bits 0-Rx DMA, 1-Tx DMA */
18116 #define ETH_DMASR_TPS_Pos                             (20U)
18117 #define ETH_DMASR_TPS_Msk                             (0x7UL << ETH_DMASR_TPS_Pos) /*!< 0x00700000 */
18118 #define ETH_DMASR_TPS                                 ETH_DMASR_TPS_Msk        /* Transmit process state */
18119 #define ETH_DMASR_TPS_Stopped                         0x00000000U              /* Stopped - Reset or Stop Tx Command issued  */
18120 #define ETH_DMASR_TPS_Fetching_Pos                    (20U)
18121 #define ETH_DMASR_TPS_Fetching_Msk                    (0x1UL << ETH_DMASR_TPS_Fetching_Pos) /*!< 0x00100000 */
18122 #define ETH_DMASR_TPS_Fetching                        ETH_DMASR_TPS_Fetching_Msk /* Running - fetching the Tx descriptor */
18123 #define ETH_DMASR_TPS_Waiting_Pos                     (21U)
18124 #define ETH_DMASR_TPS_Waiting_Msk                     (0x1UL << ETH_DMASR_TPS_Waiting_Pos) /*!< 0x00200000 */
18125 #define ETH_DMASR_TPS_Waiting                         ETH_DMASR_TPS_Waiting_Msk /* Running - waiting for status */
18126 #define ETH_DMASR_TPS_Reading_Pos                     (20U)
18127 #define ETH_DMASR_TPS_Reading_Msk                     (0x3UL << ETH_DMASR_TPS_Reading_Pos) /*!< 0x00300000 */
18128 #define ETH_DMASR_TPS_Reading                         ETH_DMASR_TPS_Reading_Msk /* Running - reading the data from host memory */
18129 #define ETH_DMASR_TPS_Suspended_Pos                   (21U)
18130 #define ETH_DMASR_TPS_Suspended_Msk                   (0x3UL << ETH_DMASR_TPS_Suspended_Pos) /*!< 0x00600000 */
18131 #define ETH_DMASR_TPS_Suspended                       ETH_DMASR_TPS_Suspended_Msk /* Suspended - Tx Descriptor unavailable */
18132 #define ETH_DMASR_TPS_Closing_Pos                     (20U)
18133 #define ETH_DMASR_TPS_Closing_Msk                     (0x7UL << ETH_DMASR_TPS_Closing_Pos) /*!< 0x00700000 */
18134 #define ETH_DMASR_TPS_Closing                         ETH_DMASR_TPS_Closing_Msk /* Running - closing Rx descriptor */
18135 #define ETH_DMASR_RPS_Pos                             (17U)
18136 #define ETH_DMASR_RPS_Msk                             (0x7UL << ETH_DMASR_RPS_Pos) /*!< 0x000E0000 */
18137 #define ETH_DMASR_RPS                                 ETH_DMASR_RPS_Msk        /* Receive process state */
18138 #define ETH_DMASR_RPS_Stopped                         0x00000000U              /* Stopped - Reset or Stop Rx Command issued */
18139 #define ETH_DMASR_RPS_Fetching_Pos                    (17U)
18140 #define ETH_DMASR_RPS_Fetching_Msk                    (0x1UL << ETH_DMASR_RPS_Fetching_Pos) /*!< 0x00020000 */
18141 #define ETH_DMASR_RPS_Fetching                        ETH_DMASR_RPS_Fetching_Msk /* Running - fetching the Rx descriptor */
18142 #define ETH_DMASR_RPS_Waiting_Pos                     (17U)
18143 #define ETH_DMASR_RPS_Waiting_Msk                     (0x3UL << ETH_DMASR_RPS_Waiting_Pos) /*!< 0x00060000 */
18144 #define ETH_DMASR_RPS_Waiting                         ETH_DMASR_RPS_Waiting_Msk /* Running - waiting for packet */
18145 #define ETH_DMASR_RPS_Suspended_Pos                   (19U)
18146 #define ETH_DMASR_RPS_Suspended_Msk                   (0x1UL << ETH_DMASR_RPS_Suspended_Pos) /*!< 0x00080000 */
18147 #define ETH_DMASR_RPS_Suspended                       ETH_DMASR_RPS_Suspended_Msk /* Suspended - Rx Descriptor unavailable */
18148 #define ETH_DMASR_RPS_Closing_Pos                     (17U)
18149 #define ETH_DMASR_RPS_Closing_Msk                     (0x5UL << ETH_DMASR_RPS_Closing_Pos) /*!< 0x000A0000 */
18150 #define ETH_DMASR_RPS_Closing                         ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */
18151 #define ETH_DMASR_RPS_Queuing_Pos                     (17U)
18152 #define ETH_DMASR_RPS_Queuing_Msk                     (0x7UL << ETH_DMASR_RPS_Queuing_Pos) /*!< 0x000E0000 */
18153 #define ETH_DMASR_RPS_Queuing                         ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the receive frame into host memory */
18154 #define ETH_DMASR_NIS_Pos                             (16U)
18155 #define ETH_DMASR_NIS_Msk                             (0x1UL << ETH_DMASR_NIS_Pos) /*!< 0x00010000 */
18156 #define ETH_DMASR_NIS                                 ETH_DMASR_NIS_Msk        /* Normal interrupt summary */
18157 #define ETH_DMASR_AIS_Pos                             (15U)
18158 #define ETH_DMASR_AIS_Msk                             (0x1UL << ETH_DMASR_AIS_Pos) /*!< 0x00008000 */
18159 #define ETH_DMASR_AIS                                 ETH_DMASR_AIS_Msk        /* Abnormal interrupt summary */
18160 #define ETH_DMASR_ERS_Pos                             (14U)
18161 #define ETH_DMASR_ERS_Msk                             (0x1UL << ETH_DMASR_ERS_Pos) /*!< 0x00004000 */
18162 #define ETH_DMASR_ERS                                 ETH_DMASR_ERS_Msk        /* Early receive status */
18163 #define ETH_DMASR_FBES_Pos                            (13U)
18164 #define ETH_DMASR_FBES_Msk                            (0x1UL << ETH_DMASR_FBES_Pos) /*!< 0x00002000 */
18165 #define ETH_DMASR_FBES                                ETH_DMASR_FBES_Msk       /* Fatal bus error status */
18166 #define ETH_DMASR_ETS_Pos                             (10U)
18167 #define ETH_DMASR_ETS_Msk                             (0x1UL << ETH_DMASR_ETS_Pos) /*!< 0x00000400 */
18168 #define ETH_DMASR_ETS                                 ETH_DMASR_ETS_Msk        /* Early transmit status */
18169 #define ETH_DMASR_RWTS_Pos                            (9U)
18170 #define ETH_DMASR_RWTS_Msk                            (0x1UL << ETH_DMASR_RWTS_Pos) /*!< 0x00000200 */
18171 #define ETH_DMASR_RWTS                                ETH_DMASR_RWTS_Msk       /* Receive watchdog timeout status */
18172 #define ETH_DMASR_RPSS_Pos                            (8U)
18173 #define ETH_DMASR_RPSS_Msk                            (0x1UL << ETH_DMASR_RPSS_Pos) /*!< 0x00000100 */
18174 #define ETH_DMASR_RPSS                                ETH_DMASR_RPSS_Msk       /* Receive process stopped status */
18175 #define ETH_DMASR_RBUS_Pos                            (7U)
18176 #define ETH_DMASR_RBUS_Msk                            (0x1UL << ETH_DMASR_RBUS_Pos) /*!< 0x00000080 */
18177 #define ETH_DMASR_RBUS                                ETH_DMASR_RBUS_Msk       /* Receive buffer unavailable status */
18178 #define ETH_DMASR_RS_Pos                              (6U)
18179 #define ETH_DMASR_RS_Msk                              (0x1UL << ETH_DMASR_RS_Pos) /*!< 0x00000040 */
18180 #define ETH_DMASR_RS                                  ETH_DMASR_RS_Msk         /* Receive status */
18181 #define ETH_DMASR_TUS_Pos                             (5U)
18182 #define ETH_DMASR_TUS_Msk                             (0x1UL << ETH_DMASR_TUS_Pos) /*!< 0x00000020 */
18183 #define ETH_DMASR_TUS                                 ETH_DMASR_TUS_Msk        /* Transmit underflow status */
18184 #define ETH_DMASR_ROS_Pos                             (4U)
18185 #define ETH_DMASR_ROS_Msk                             (0x1UL << ETH_DMASR_ROS_Pos) /*!< 0x00000010 */
18186 #define ETH_DMASR_ROS                                 ETH_DMASR_ROS_Msk        /* Receive overflow status */
18187 #define ETH_DMASR_TJTS_Pos                            (3U)
18188 #define ETH_DMASR_TJTS_Msk                            (0x1UL << ETH_DMASR_TJTS_Pos) /*!< 0x00000008 */
18189 #define ETH_DMASR_TJTS                                ETH_DMASR_TJTS_Msk       /* Transmit jabber timeout status */
18190 #define ETH_DMASR_TBUS_Pos                            (2U)
18191 #define ETH_DMASR_TBUS_Msk                            (0x1UL << ETH_DMASR_TBUS_Pos) /*!< 0x00000004 */
18192 #define ETH_DMASR_TBUS                                ETH_DMASR_TBUS_Msk       /* Transmit buffer unavailable status */
18193 #define ETH_DMASR_TPSS_Pos                            (1U)
18194 #define ETH_DMASR_TPSS_Msk                            (0x1UL << ETH_DMASR_TPSS_Pos) /*!< 0x00000002 */
18195 #define ETH_DMASR_TPSS                                ETH_DMASR_TPSS_Msk       /* Transmit process stopped status */
18196 #define ETH_DMASR_TS_Pos                              (0U)
18197 #define ETH_DMASR_TS_Msk                              (0x1UL << ETH_DMASR_TS_Pos) /*!< 0x00000001 */
18198 #define ETH_DMASR_TS                                  ETH_DMASR_TS_Msk         /* Transmit status */
18199 
18200 /* Bit definition for Ethernet DMA Operation Mode Register */
18201 #define ETH_DMAOMR_DTCEFD_Pos                         (26U)
18202 #define ETH_DMAOMR_DTCEFD_Msk                         (0x1UL << ETH_DMAOMR_DTCEFD_Pos) /*!< 0x04000000 */
18203 #define ETH_DMAOMR_DTCEFD                             ETH_DMAOMR_DTCEFD_Msk    /* Disable Dropping of TCP/IP checksum error frames */
18204 #define ETH_DMAOMR_RSF_Pos                            (25U)
18205 #define ETH_DMAOMR_RSF_Msk                            (0x1UL << ETH_DMAOMR_RSF_Pos) /*!< 0x02000000 */
18206 #define ETH_DMAOMR_RSF                                ETH_DMAOMR_RSF_Msk       /* Receive store and forward */
18207 #define ETH_DMAOMR_DFRF_Pos                           (24U)
18208 #define ETH_DMAOMR_DFRF_Msk                           (0x1UL << ETH_DMAOMR_DFRF_Pos) /*!< 0x01000000 */
18209 #define ETH_DMAOMR_DFRF                               ETH_DMAOMR_DFRF_Msk      /* Disable flushing of received frames */
18210 #define ETH_DMAOMR_TSF_Pos                            (21U)
18211 #define ETH_DMAOMR_TSF_Msk                            (0x1UL << ETH_DMAOMR_TSF_Pos) /*!< 0x00200000 */
18212 #define ETH_DMAOMR_TSF                                ETH_DMAOMR_TSF_Msk       /* Transmit store and forward */
18213 #define ETH_DMAOMR_FTF_Pos                            (20U)
18214 #define ETH_DMAOMR_FTF_Msk                            (0x1UL << ETH_DMAOMR_FTF_Pos) /*!< 0x00100000 */
18215 #define ETH_DMAOMR_FTF                                ETH_DMAOMR_FTF_Msk       /* Flush transmit FIFO */
18216 #define ETH_DMAOMR_TTC_Pos                            (14U)
18217 #define ETH_DMAOMR_TTC_Msk                            (0x7UL << ETH_DMAOMR_TTC_Pos) /*!< 0x0001C000 */
18218 #define ETH_DMAOMR_TTC                                ETH_DMAOMR_TTC_Msk       /* Transmit threshold control */
18219 #define ETH_DMAOMR_TTC_64Bytes                        0x00000000U              /* threshold level of the MTL Transmit FIFO is 64 Bytes */
18220 #define ETH_DMAOMR_TTC_128Bytes                       0x00004000U              /* threshold level of the MTL Transmit FIFO is 128 Bytes */
18221 #define ETH_DMAOMR_TTC_192Bytes                       0x00008000U              /* threshold level of the MTL Transmit FIFO is 192 Bytes */
18222 #define ETH_DMAOMR_TTC_256Bytes                       0x0000C000U              /* threshold level of the MTL Transmit FIFO is 256 Bytes */
18223 #define ETH_DMAOMR_TTC_40Bytes                        0x00010000U              /* threshold level of the MTL Transmit FIFO is 40 Bytes */
18224 #define ETH_DMAOMR_TTC_32Bytes                        0x00014000U              /* threshold level of the MTL Transmit FIFO is 32 Bytes */
18225 #define ETH_DMAOMR_TTC_24Bytes                        0x00018000U              /* threshold level of the MTL Transmit FIFO is 24 Bytes */
18226 #define ETH_DMAOMR_TTC_16Bytes                        0x0001C000U              /* threshold level of the MTL Transmit FIFO is 16 Bytes */
18227 #define ETH_DMAOMR_ST_Pos                             (13U)
18228 #define ETH_DMAOMR_ST_Msk                             (0x1UL << ETH_DMAOMR_ST_Pos) /*!< 0x00002000 */
18229 #define ETH_DMAOMR_ST                                 ETH_DMAOMR_ST_Msk        /* Start/stop transmission command */
18230 #define ETH_DMAOMR_FEF_Pos                            (7U)
18231 #define ETH_DMAOMR_FEF_Msk                            (0x1UL << ETH_DMAOMR_FEF_Pos) /*!< 0x00000080 */
18232 #define ETH_DMAOMR_FEF                                ETH_DMAOMR_FEF_Msk       /* Forward error frames */
18233 #define ETH_DMAOMR_FUGF_Pos                           (6U)
18234 #define ETH_DMAOMR_FUGF_Msk                           (0x1UL << ETH_DMAOMR_FUGF_Pos) /*!< 0x00000040 */
18235 #define ETH_DMAOMR_FUGF                               ETH_DMAOMR_FUGF_Msk      /* Forward undersized good frames */
18236 #define ETH_DMAOMR_RTC_Pos                            (3U)
18237 #define ETH_DMAOMR_RTC_Msk                            (0x3UL << ETH_DMAOMR_RTC_Pos) /*!< 0x00000018 */
18238 #define ETH_DMAOMR_RTC                                ETH_DMAOMR_RTC_Msk       /* receive threshold control */
18239 #define ETH_DMAOMR_RTC_64Bytes                        0x00000000U              /* threshold level of the MTL Receive FIFO is 64 Bytes */
18240 #define ETH_DMAOMR_RTC_32Bytes                        0x00000008U              /* threshold level of the MTL Receive FIFO is 32 Bytes */
18241 #define ETH_DMAOMR_RTC_96Bytes                        0x00000010U              /* threshold level of the MTL Receive FIFO is 96 Bytes */
18242 #define ETH_DMAOMR_RTC_128Bytes                       0x00000018U              /* threshold level of the MTL Receive FIFO is 128 Bytes */
18243 #define ETH_DMAOMR_OSF_Pos                            (2U)
18244 #define ETH_DMAOMR_OSF_Msk                            (0x1UL << ETH_DMAOMR_OSF_Pos) /*!< 0x00000004 */
18245 #define ETH_DMAOMR_OSF                                ETH_DMAOMR_OSF_Msk       /* operate on second frame */
18246 #define ETH_DMAOMR_SR_Pos                             (1U)
18247 #define ETH_DMAOMR_SR_Msk                             (0x1UL << ETH_DMAOMR_SR_Pos) /*!< 0x00000002 */
18248 #define ETH_DMAOMR_SR                                 ETH_DMAOMR_SR_Msk        /* Start/stop receive */
18249 
18250 /* Bit definition for Ethernet DMA Interrupt Enable Register */
18251 #define ETH_DMAIER_NISE_Pos                           (16U)
18252 #define ETH_DMAIER_NISE_Msk                           (0x1UL << ETH_DMAIER_NISE_Pos) /*!< 0x00010000 */
18253 #define ETH_DMAIER_NISE                               ETH_DMAIER_NISE_Msk      /* Normal interrupt summary enable */
18254 #define ETH_DMAIER_AISE_Pos                           (15U)
18255 #define ETH_DMAIER_AISE_Msk                           (0x1UL << ETH_DMAIER_AISE_Pos) /*!< 0x00008000 */
18256 #define ETH_DMAIER_AISE                               ETH_DMAIER_AISE_Msk      /* Abnormal interrupt summary enable */
18257 #define ETH_DMAIER_ERIE_Pos                           (14U)
18258 #define ETH_DMAIER_ERIE_Msk                           (0x1UL << ETH_DMAIER_ERIE_Pos) /*!< 0x00004000 */
18259 #define ETH_DMAIER_ERIE                               ETH_DMAIER_ERIE_Msk      /* Early receive interrupt enable */
18260 #define ETH_DMAIER_FBEIE_Pos                          (13U)
18261 #define ETH_DMAIER_FBEIE_Msk                          (0x1UL << ETH_DMAIER_FBEIE_Pos) /*!< 0x00002000 */
18262 #define ETH_DMAIER_FBEIE                              ETH_DMAIER_FBEIE_Msk     /* Fatal bus error interrupt enable */
18263 #define ETH_DMAIER_ETIE_Pos                           (10U)
18264 #define ETH_DMAIER_ETIE_Msk                           (0x1UL << ETH_DMAIER_ETIE_Pos) /*!< 0x00000400 */
18265 #define ETH_DMAIER_ETIE                               ETH_DMAIER_ETIE_Msk      /* Early transmit interrupt enable */
18266 #define ETH_DMAIER_RWTIE_Pos                          (9U)
18267 #define ETH_DMAIER_RWTIE_Msk                          (0x1UL << ETH_DMAIER_RWTIE_Pos) /*!< 0x00000200 */
18268 #define ETH_DMAIER_RWTIE                              ETH_DMAIER_RWTIE_Msk     /* Receive watchdog timeout interrupt enable */
18269 #define ETH_DMAIER_RPSIE_Pos                          (8U)
18270 #define ETH_DMAIER_RPSIE_Msk                          (0x1UL << ETH_DMAIER_RPSIE_Pos) /*!< 0x00000100 */
18271 #define ETH_DMAIER_RPSIE                              ETH_DMAIER_RPSIE_Msk     /* Receive process stopped interrupt enable */
18272 #define ETH_DMAIER_RBUIE_Pos                          (7U)
18273 #define ETH_DMAIER_RBUIE_Msk                          (0x1UL << ETH_DMAIER_RBUIE_Pos) /*!< 0x00000080 */
18274 #define ETH_DMAIER_RBUIE                              ETH_DMAIER_RBUIE_Msk     /* Receive buffer unavailable interrupt enable */
18275 #define ETH_DMAIER_RIE_Pos                            (6U)
18276 #define ETH_DMAIER_RIE_Msk                            (0x1UL << ETH_DMAIER_RIE_Pos) /*!< 0x00000040 */
18277 #define ETH_DMAIER_RIE                                ETH_DMAIER_RIE_Msk       /* Receive interrupt enable */
18278 #define ETH_DMAIER_TUIE_Pos                           (5U)
18279 #define ETH_DMAIER_TUIE_Msk                           (0x1UL << ETH_DMAIER_TUIE_Pos) /*!< 0x00000020 */
18280 #define ETH_DMAIER_TUIE                               ETH_DMAIER_TUIE_Msk      /* Transmit Underflow interrupt enable */
18281 #define ETH_DMAIER_ROIE_Pos                           (4U)
18282 #define ETH_DMAIER_ROIE_Msk                           (0x1UL << ETH_DMAIER_ROIE_Pos) /*!< 0x00000010 */
18283 #define ETH_DMAIER_ROIE                               ETH_DMAIER_ROIE_Msk      /* Receive Overflow interrupt enable */
18284 #define ETH_DMAIER_TJTIE_Pos                          (3U)
18285 #define ETH_DMAIER_TJTIE_Msk                          (0x1UL << ETH_DMAIER_TJTIE_Pos) /*!< 0x00000008 */
18286 #define ETH_DMAIER_TJTIE                              ETH_DMAIER_TJTIE_Msk     /* Transmit jabber timeout interrupt enable */
18287 #define ETH_DMAIER_TBUIE_Pos                          (2U)
18288 #define ETH_DMAIER_TBUIE_Msk                          (0x1UL << ETH_DMAIER_TBUIE_Pos) /*!< 0x00000004 */
18289 #define ETH_DMAIER_TBUIE                              ETH_DMAIER_TBUIE_Msk     /* Transmit buffer unavailable interrupt enable */
18290 #define ETH_DMAIER_TPSIE_Pos                          (1U)
18291 #define ETH_DMAIER_TPSIE_Msk                          (0x1UL << ETH_DMAIER_TPSIE_Pos) /*!< 0x00000002 */
18292 #define ETH_DMAIER_TPSIE                              ETH_DMAIER_TPSIE_Msk     /* Transmit process stopped interrupt enable */
18293 #define ETH_DMAIER_TIE_Pos                            (0U)
18294 #define ETH_DMAIER_TIE_Msk                            (0x1UL << ETH_DMAIER_TIE_Pos) /*!< 0x00000001 */
18295 #define ETH_DMAIER_TIE                                ETH_DMAIER_TIE_Msk       /* Transmit interrupt enable */
18296 
18297 /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
18298 #define ETH_DMAMFBOCR_OFOC_Pos                        (28U)
18299 #define ETH_DMAMFBOCR_OFOC_Msk                        (0x1UL << ETH_DMAMFBOCR_OFOC_Pos) /*!< 0x10000000 */
18300 #define ETH_DMAMFBOCR_OFOC                            ETH_DMAMFBOCR_OFOC_Msk   /* Overflow bit for FIFO overflow counter */
18301 #define ETH_DMAMFBOCR_MFA_Pos                         (17U)
18302 #define ETH_DMAMFBOCR_MFA_Msk                         (0x7FFUL << ETH_DMAMFBOCR_MFA_Pos) /*!< 0x0FFE0000 */
18303 #define ETH_DMAMFBOCR_MFA                             ETH_DMAMFBOCR_MFA_Msk    /* Number of frames missed by the application */
18304 #define ETH_DMAMFBOCR_OMFC_Pos                        (16U)
18305 #define ETH_DMAMFBOCR_OMFC_Msk                        (0x1UL << ETH_DMAMFBOCR_OMFC_Pos) /*!< 0x00010000 */
18306 #define ETH_DMAMFBOCR_OMFC                            ETH_DMAMFBOCR_OMFC_Msk   /* Overflow bit for missed frame counter */
18307 #define ETH_DMAMFBOCR_MFC_Pos                         (0U)
18308 #define ETH_DMAMFBOCR_MFC_Msk                         (0xFFFFUL << ETH_DMAMFBOCR_MFC_Pos) /*!< 0x0000FFFF */
18309 #define ETH_DMAMFBOCR_MFC                             ETH_DMAMFBOCR_MFC_Msk    /* Number of frames missed by the controller */
18310 
18311 /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
18312 #define ETH_DMACHTDR_HTDAP_Pos                        (0U)
18313 #define ETH_DMACHTDR_HTDAP_Msk                        (0xFFFFFFFFUL << ETH_DMACHTDR_HTDAP_Pos) /*!< 0xFFFFFFFF */
18314 #define ETH_DMACHTDR_HTDAP                            ETH_DMACHTDR_HTDAP_Msk   /* Host transmit descriptor address pointer */
18315 
18316 /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
18317 #define ETH_DMACHRDR_HRDAP_Pos                        (0U)
18318 #define ETH_DMACHRDR_HRDAP_Msk                        (0xFFFFFFFFUL << ETH_DMACHRDR_HRDAP_Pos) /*!< 0xFFFFFFFF */
18319 #define ETH_DMACHRDR_HRDAP                            ETH_DMACHRDR_HRDAP_Msk   /* Host receive descriptor address pointer */
18320 
18321 /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
18322 #define ETH_DMACHTBAR_HTBAP_Pos                       (0U)
18323 #define ETH_DMACHTBAR_HTBAP_Msk                       (0xFFFFFFFFUL << ETH_DMACHTBAR_HTBAP_Pos) /*!< 0xFFFFFFFF */
18324 #define ETH_DMACHTBAR_HTBAP                           ETH_DMACHTBAR_HTBAP_Msk  /* Host transmit buffer address pointer */
18325 
18326 /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
18327 #define ETH_DMACHRBAR_HRBAP_Pos                       (0U)
18328 #define ETH_DMACHRBAR_HRBAP_Msk                       (0xFFFFFFFFUL << ETH_DMACHRBAR_HRBAP_Pos) /*!< 0xFFFFFFFF */
18329 #define ETH_DMACHRBAR_HRBAP                           ETH_DMACHRBAR_HRBAP_Msk  /* Host receive buffer address pointer */
18330 
18331 /******************************************************************************/
18332 /*                                                                            */
18333 /*                                       USB_OTG                              */
18334 /*                                                                            */
18335 /******************************************************************************/
18336 /********************  Bit definition for USB_OTG_GOTGCTL register  ***********/
18337 #define USB_OTG_GOTGCTL_SRQSCS_Pos               (0U)
18338 #define USB_OTG_GOTGCTL_SRQSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
18339 #define USB_OTG_GOTGCTL_SRQSCS                   USB_OTG_GOTGCTL_SRQSCS_Msk    /*!< Session request success */
18340 #define USB_OTG_GOTGCTL_SRQ_Pos                  (1U)
18341 #define USB_OTG_GOTGCTL_SRQ_Msk                  (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
18342 #define USB_OTG_GOTGCTL_SRQ                      USB_OTG_GOTGCTL_SRQ_Msk       /*!< Session request */
18343 #define USB_OTG_GOTGCTL_VBVALOEN_Pos             (2U)
18344 #define USB_OTG_GOTGCTL_VBVALOEN_Msk             (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */
18345 #define USB_OTG_GOTGCTL_VBVALOEN                 USB_OTG_GOTGCTL_VBVALOEN_Msk  /*!< VBUS valid override enable */
18346 #define USB_OTG_GOTGCTL_VBVALOVAL_Pos            (3U)
18347 #define USB_OTG_GOTGCTL_VBVALOVAL_Msk            (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */
18348 #define USB_OTG_GOTGCTL_VBVALOVAL                USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */
18349 #define USB_OTG_GOTGCTL_AVALOEN_Pos              (4U)
18350 #define USB_OTG_GOTGCTL_AVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */
18351 #define USB_OTG_GOTGCTL_AVALOEN                  USB_OTG_GOTGCTL_AVALOEN_Msk   /*!< A-peripheral session valid override enable */
18352 #define USB_OTG_GOTGCTL_AVALOVAL_Pos             (5U)
18353 #define USB_OTG_GOTGCTL_AVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */
18354 #define USB_OTG_GOTGCTL_AVALOVAL                 USB_OTG_GOTGCTL_AVALOVAL_Msk  /*!< A-peripheral session valid override value */
18355 #define USB_OTG_GOTGCTL_BVALOEN_Pos              (6U)
18356 #define USB_OTG_GOTGCTL_BVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */
18357 #define USB_OTG_GOTGCTL_BVALOEN                  USB_OTG_GOTGCTL_BVALOEN_Msk   /*!< B-peripheral session valid override enable */
18358 #define USB_OTG_GOTGCTL_BVALOVAL_Pos             (7U)
18359 #define USB_OTG_GOTGCTL_BVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */
18360 #define USB_OTG_GOTGCTL_BVALOVAL                 USB_OTG_GOTGCTL_BVALOVAL_Msk  /*!< B-peripheral session valid override value  */
18361 #define USB_OTG_GOTGCTL_HNGSCS_Pos               (8U)
18362 #define USB_OTG_GOTGCTL_HNGSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
18363 #define USB_OTG_GOTGCTL_HNGSCS                   USB_OTG_GOTGCTL_HNGSCS_Msk    /*!< Host set HNP enable */
18364 #define USB_OTG_GOTGCTL_HNPRQ_Pos                (9U)
18365 #define USB_OTG_GOTGCTL_HNPRQ_Msk                (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
18366 #define USB_OTG_GOTGCTL_HNPRQ                    USB_OTG_GOTGCTL_HNPRQ_Msk     /*!< HNP request */
18367 #define USB_OTG_GOTGCTL_HSHNPEN_Pos              (10U)
18368 #define USB_OTG_GOTGCTL_HSHNPEN_Msk              (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
18369 #define USB_OTG_GOTGCTL_HSHNPEN                  USB_OTG_GOTGCTL_HSHNPEN_Msk   /*!< Host set HNP enable */
18370 #define USB_OTG_GOTGCTL_DHNPEN_Pos               (11U)
18371 #define USB_OTG_GOTGCTL_DHNPEN_Msk               (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
18372 #define USB_OTG_GOTGCTL_DHNPEN                   USB_OTG_GOTGCTL_DHNPEN_Msk    /*!< Device HNP enabled */
18373 #define USB_OTG_GOTGCTL_EHEN_Pos                 (12U)
18374 #define USB_OTG_GOTGCTL_EHEN_Msk                 (0x1UL << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */
18375 #define USB_OTG_GOTGCTL_EHEN                     USB_OTG_GOTGCTL_EHEN_Msk      /*!< Embedded host enable */
18376 #define USB_OTG_GOTGCTL_CIDSTS_Pos               (16U)
18377 #define USB_OTG_GOTGCTL_CIDSTS_Msk               (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
18378 #define USB_OTG_GOTGCTL_CIDSTS                   USB_OTG_GOTGCTL_CIDSTS_Msk    /*!< Connector ID status */
18379 #define USB_OTG_GOTGCTL_DBCT_Pos                 (17U)
18380 #define USB_OTG_GOTGCTL_DBCT_Msk                 (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
18381 #define USB_OTG_GOTGCTL_DBCT                     USB_OTG_GOTGCTL_DBCT_Msk      /*!< Long/short debounce time */
18382 #define USB_OTG_GOTGCTL_ASVLD_Pos                (18U)
18383 #define USB_OTG_GOTGCTL_ASVLD_Msk                (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
18384 #define USB_OTG_GOTGCTL_ASVLD                    USB_OTG_GOTGCTL_ASVLD_Msk     /*!< A-session valid  */
18385 #define USB_OTG_GOTGCTL_BSESVLD_Pos              (19U)
18386 #define USB_OTG_GOTGCTL_BSESVLD_Msk              (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */
18387 #define USB_OTG_GOTGCTL_BSESVLD                  USB_OTG_GOTGCTL_BSESVLD_Msk   /*!< B-session valid */
18388 #define USB_OTG_GOTGCTL_OTGVER_Pos               (20U)
18389 #define USB_OTG_GOTGCTL_OTGVER_Msk               (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
18390 #define USB_OTG_GOTGCTL_OTGVER                   USB_OTG_GOTGCTL_OTGVER_Msk    /*!< OTG version  */
18391 
18392 /********************  Bit definition forUSB_OTG_HCFG register  ********************/
18393 
18394 #define USB_OTG_HCFG_FSLSPCS_Pos                 (0U)
18395 #define USB_OTG_HCFG_FSLSPCS_Msk                 (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
18396 #define USB_OTG_HCFG_FSLSPCS                     USB_OTG_HCFG_FSLSPCS_Msk      /*!< FS/LS PHY clock select  */
18397 #define USB_OTG_HCFG_FSLSPCS_0                   (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
18398 #define USB_OTG_HCFG_FSLSPCS_1                   (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
18399 #define USB_OTG_HCFG_FSLSS_Pos                   (2U)
18400 #define USB_OTG_HCFG_FSLSS_Msk                   (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
18401 #define USB_OTG_HCFG_FSLSS                       USB_OTG_HCFG_FSLSS_Msk        /*!< FS- and LS-only support */
18402 
18403 /********************  Bit definition for USB_OTG_DCFG register  ********************/
18404 
18405 #define USB_OTG_DCFG_DSPD_Pos                    (0U)
18406 #define USB_OTG_DCFG_DSPD_Msk                    (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
18407 #define USB_OTG_DCFG_DSPD                        USB_OTG_DCFG_DSPD_Msk         /*!< Device speed */
18408 #define USB_OTG_DCFG_DSPD_0                      (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
18409 #define USB_OTG_DCFG_DSPD_1                      (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
18410 #define USB_OTG_DCFG_NZLSOHSK_Pos                (2U)
18411 #define USB_OTG_DCFG_NZLSOHSK_Msk                (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
18412 #define USB_OTG_DCFG_NZLSOHSK                    USB_OTG_DCFG_NZLSOHSK_Msk     /*!< Nonzero-length status OUT handshake */
18413 
18414 #define USB_OTG_DCFG_DAD_Pos                     (4U)
18415 #define USB_OTG_DCFG_DAD_Msk                     (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
18416 #define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk          /*!< Device address */
18417 #define USB_OTG_DCFG_DAD_0                       (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
18418 #define USB_OTG_DCFG_DAD_1                       (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
18419 #define USB_OTG_DCFG_DAD_2                       (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
18420 #define USB_OTG_DCFG_DAD_3                       (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
18421 #define USB_OTG_DCFG_DAD_4                       (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
18422 #define USB_OTG_DCFG_DAD_5                       (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
18423 #define USB_OTG_DCFG_DAD_6                       (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
18424 
18425 #define USB_OTG_DCFG_PFIVL_Pos                   (11U)
18426 #define USB_OTG_DCFG_PFIVL_Msk                   (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
18427 #define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk        /*!< Periodic (micro)frame interval */
18428 #define USB_OTG_DCFG_PFIVL_0                     (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
18429 #define USB_OTG_DCFG_PFIVL_1                     (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
18430 
18431 #define USB_OTG_DCFG_XCVRDLY_Pos                 (14U)
18432 #define USB_OTG_DCFG_XCVRDLY_Msk                 (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */
18433 #define USB_OTG_DCFG_XCVRDLY                     USB_OTG_DCFG_XCVRDLY_Msk        /*!< Transceiver delay */
18434 
18435 #define USB_OTG_DCFG_ERRATIM_Pos                 (15U)
18436 #define USB_OTG_DCFG_ERRATIM_Msk                 (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */
18437 #define USB_OTG_DCFG_ERRATIM                     USB_OTG_DCFG_ERRATIM_Msk        /*!< Erratic error interrupt mask */
18438 
18439 #define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)
18440 #define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
18441 #define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk    /*!< Periodic scheduling interval */
18442 #define USB_OTG_DCFG_PERSCHIVL_0                 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
18443 #define USB_OTG_DCFG_PERSCHIVL_1                 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
18444 
18445 /********************  Bit definition for USB_OTG_PCGCR register  ********************/
18446 #define USB_OTG_PCGCR_STPPCLK_Pos                (0U)
18447 #define USB_OTG_PCGCR_STPPCLK_Msk                (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
18448 #define USB_OTG_PCGCR_STPPCLK                    USB_OTG_PCGCR_STPPCLK_Msk     /*!< Stop PHY clock */
18449 #define USB_OTG_PCGCR_GATEHCLK_Pos               (1U)
18450 #define USB_OTG_PCGCR_GATEHCLK_Msk               (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
18451 #define USB_OTG_PCGCR_GATEHCLK                   USB_OTG_PCGCR_GATEHCLK_Msk    /*!< Gate HCLK */
18452 #define USB_OTG_PCGCR_PHYSUSP_Pos                (4U)
18453 #define USB_OTG_PCGCR_PHYSUSP_Msk                (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
18454 #define USB_OTG_PCGCR_PHYSUSP                    USB_OTG_PCGCR_PHYSUSP_Msk     /*!< PHY suspended */
18455 
18456 /********************  Bit definition for USB_OTG_GOTGINT register  ********************/
18457 #define USB_OTG_GOTGINT_SEDET_Pos                (2U)
18458 #define USB_OTG_GOTGINT_SEDET_Msk                (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
18459 #define USB_OTG_GOTGINT_SEDET                    USB_OTG_GOTGINT_SEDET_Msk     /*!< Session end detected                   */
18460 #define USB_OTG_GOTGINT_SRSSCHG_Pos              (8U)
18461 #define USB_OTG_GOTGINT_SRSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
18462 #define USB_OTG_GOTGINT_SRSSCHG                  USB_OTG_GOTGINT_SRSSCHG_Msk   /*!< Session request success status change  */
18463 #define USB_OTG_GOTGINT_HNSSCHG_Pos              (9U)
18464 #define USB_OTG_GOTGINT_HNSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
18465 #define USB_OTG_GOTGINT_HNSSCHG                  USB_OTG_GOTGINT_HNSSCHG_Msk   /*!< Host negotiation success status change */
18466 #define USB_OTG_GOTGINT_HNGDET_Pos               (17U)
18467 #define USB_OTG_GOTGINT_HNGDET_Msk               (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
18468 #define USB_OTG_GOTGINT_HNGDET                   USB_OTG_GOTGINT_HNGDET_Msk    /*!< Host negotiation detected              */
18469 #define USB_OTG_GOTGINT_ADTOCHG_Pos              (18U)
18470 #define USB_OTG_GOTGINT_ADTOCHG_Msk              (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
18471 #define USB_OTG_GOTGINT_ADTOCHG                  USB_OTG_GOTGINT_ADTOCHG_Msk   /*!< A-device timeout change                */
18472 #define USB_OTG_GOTGINT_DBCDNE_Pos               (19U)
18473 #define USB_OTG_GOTGINT_DBCDNE_Msk               (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
18474 #define USB_OTG_GOTGINT_DBCDNE                   USB_OTG_GOTGINT_DBCDNE_Msk    /*!< Debounce done                          */
18475 #define USB_OTG_GOTGINT_IDCHNG_Pos               (20U)
18476 #define USB_OTG_GOTGINT_IDCHNG_Msk               (0x1UL << USB_OTG_GOTGINT_IDCHNG_Pos) /*!< 0x00100000 */
18477 #define USB_OTG_GOTGINT_IDCHNG                   USB_OTG_GOTGINT_IDCHNG_Msk    /*!< Change in ID pin input value           */
18478 
18479 /********************  Bit definition for USB_OTG_DCTL register  ********************/
18480 #define USB_OTG_DCTL_RWUSIG_Pos                  (0U)
18481 #define USB_OTG_DCTL_RWUSIG_Msk                  (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
18482 #define USB_OTG_DCTL_RWUSIG                      USB_OTG_DCTL_RWUSIG_Msk       /*!< Remote wakeup signaling */
18483 #define USB_OTG_DCTL_SDIS_Pos                    (1U)
18484 #define USB_OTG_DCTL_SDIS_Msk                    (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
18485 #define USB_OTG_DCTL_SDIS                        USB_OTG_DCTL_SDIS_Msk         /*!< Soft disconnect         */
18486 #define USB_OTG_DCTL_GINSTS_Pos                  (2U)
18487 #define USB_OTG_DCTL_GINSTS_Msk                  (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
18488 #define USB_OTG_DCTL_GINSTS                      USB_OTG_DCTL_GINSTS_Msk       /*!< Global IN NAK status    */
18489 #define USB_OTG_DCTL_GONSTS_Pos                  (3U)
18490 #define USB_OTG_DCTL_GONSTS_Msk                  (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
18491 #define USB_OTG_DCTL_GONSTS                      USB_OTG_DCTL_GONSTS_Msk       /*!< Global OUT NAK status   */
18492 
18493 #define USB_OTG_DCTL_TCTL_Pos                    (4U)
18494 #define USB_OTG_DCTL_TCTL_Msk                    (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
18495 #define USB_OTG_DCTL_TCTL                        USB_OTG_DCTL_TCTL_Msk         /*!< Test control */
18496 #define USB_OTG_DCTL_TCTL_0                      (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
18497 #define USB_OTG_DCTL_TCTL_1                      (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
18498 #define USB_OTG_DCTL_TCTL_2                      (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
18499 #define USB_OTG_DCTL_SGINAK_Pos                  (7U)
18500 #define USB_OTG_DCTL_SGINAK_Msk                  (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
18501 #define USB_OTG_DCTL_SGINAK                      USB_OTG_DCTL_SGINAK_Msk       /*!< Set global IN NAK         */
18502 #define USB_OTG_DCTL_CGINAK_Pos                  (8U)
18503 #define USB_OTG_DCTL_CGINAK_Msk                  (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
18504 #define USB_OTG_DCTL_CGINAK                      USB_OTG_DCTL_CGINAK_Msk       /*!< Clear global IN NAK       */
18505 #define USB_OTG_DCTL_SGONAK_Pos                  (9U)
18506 #define USB_OTG_DCTL_SGONAK_Msk                  (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
18507 #define USB_OTG_DCTL_SGONAK                      USB_OTG_DCTL_SGONAK_Msk       /*!< Set global OUT NAK        */
18508 #define USB_OTG_DCTL_CGONAK_Pos                  (10U)
18509 #define USB_OTG_DCTL_CGONAK_Msk                  (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
18510 #define USB_OTG_DCTL_CGONAK                      USB_OTG_DCTL_CGONAK_Msk       /*!< Clear global OUT NAK      */
18511 #define USB_OTG_DCTL_POPRGDNE_Pos                (11U)
18512 #define USB_OTG_DCTL_POPRGDNE_Msk                (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
18513 #define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */
18514 
18515 /********************  Bit definition for USB_OTG_HFIR register  ********************/
18516 #define USB_OTG_HFIR_FRIVL_Pos                   (0U)
18517 #define USB_OTG_HFIR_FRIVL_Msk                   (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
18518 #define USB_OTG_HFIR_FRIVL                       USB_OTG_HFIR_FRIVL_Msk        /*!< Frame interval */
18519 
18520 /********************  Bit definition for USB_OTG_HFNUM register  ********************/
18521 #define USB_OTG_HFNUM_FRNUM_Pos                  (0U)
18522 #define USB_OTG_HFNUM_FRNUM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
18523 #define USB_OTG_HFNUM_FRNUM                      USB_OTG_HFNUM_FRNUM_Msk       /*!< Frame number         */
18524 #define USB_OTG_HFNUM_FTREM_Pos                  (16U)
18525 #define USB_OTG_HFNUM_FTREM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
18526 #define USB_OTG_HFNUM_FTREM                      USB_OTG_HFNUM_FTREM_Msk       /*!< Frame time remaining */
18527 
18528 /********************  Bit definition for USB_OTG_DSTS register  ********************/
18529 #define USB_OTG_DSTS_SUSPSTS_Pos                 (0U)
18530 #define USB_OTG_DSTS_SUSPSTS_Msk                 (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
18531 #define USB_OTG_DSTS_SUSPSTS                     USB_OTG_DSTS_SUSPSTS_Msk      /*!< Suspend status   */
18532 
18533 #define USB_OTG_DSTS_ENUMSPD_Pos                 (1U)
18534 #define USB_OTG_DSTS_ENUMSPD_Msk                 (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
18535 #define USB_OTG_DSTS_ENUMSPD                     USB_OTG_DSTS_ENUMSPD_Msk      /*!< Enumerated speed */
18536 #define USB_OTG_DSTS_ENUMSPD_0                   (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
18537 #define USB_OTG_DSTS_ENUMSPD_1                   (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
18538 #define USB_OTG_DSTS_EERR_Pos                    (3U)
18539 #define USB_OTG_DSTS_EERR_Msk                    (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
18540 #define USB_OTG_DSTS_EERR                        USB_OTG_DSTS_EERR_Msk         /*!< Erratic error     */
18541 #define USB_OTG_DSTS_FNSOF_Pos                   (8U)
18542 #define USB_OTG_DSTS_FNSOF_Msk                   (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
18543 #define USB_OTG_DSTS_FNSOF                       USB_OTG_DSTS_FNSOF_Msk        /*!< Frame number of the received SOF */
18544 
18545 /********************  Bit definition for USB_OTG_GAHBCFG register  ********************/
18546 #define USB_OTG_GAHBCFG_GINT_Pos                 (0U)
18547 #define USB_OTG_GAHBCFG_GINT_Msk                 (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
18548 #define USB_OTG_GAHBCFG_GINT                     USB_OTG_GAHBCFG_GINT_Msk      /*!< Global interrupt mask */
18549 #define USB_OTG_GAHBCFG_HBSTLEN_Pos              (1U)
18550 #define USB_OTG_GAHBCFG_HBSTLEN_Msk              (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
18551 #define USB_OTG_GAHBCFG_HBSTLEN                  USB_OTG_GAHBCFG_HBSTLEN_Msk   /*!< Burst length/type */
18552 #define USB_OTG_GAHBCFG_HBSTLEN_0                (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
18553 #define USB_OTG_GAHBCFG_HBSTLEN_1                (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
18554 #define USB_OTG_GAHBCFG_HBSTLEN_2                (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
18555 #define USB_OTG_GAHBCFG_HBSTLEN_3                (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
18556 #define USB_OTG_GAHBCFG_HBSTLEN_4                (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
18557 #define USB_OTG_GAHBCFG_DMAEN_Pos                (5U)
18558 #define USB_OTG_GAHBCFG_DMAEN_Msk                (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
18559 #define USB_OTG_GAHBCFG_DMAEN                    USB_OTG_GAHBCFG_DMAEN_Msk     /*!< DMA enable */
18560 #define USB_OTG_GAHBCFG_TXFELVL_Pos              (7U)
18561 #define USB_OTG_GAHBCFG_TXFELVL_Msk              (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
18562 #define USB_OTG_GAHBCFG_TXFELVL                  USB_OTG_GAHBCFG_TXFELVL_Msk   /*!< TxFIFO empty level */
18563 #define USB_OTG_GAHBCFG_PTXFELVL_Pos             (8U)
18564 #define USB_OTG_GAHBCFG_PTXFELVL_Msk             (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
18565 #define USB_OTG_GAHBCFG_PTXFELVL                 USB_OTG_GAHBCFG_PTXFELVL_Msk  /*!< Periodic TxFIFO empty level */
18566 
18567 /********************  Bit definition for USB_OTG_GUSBCFG register  ********************/
18568 
18569 #define USB_OTG_GUSBCFG_TOCAL_Pos                (0U)
18570 #define USB_OTG_GUSBCFG_TOCAL_Msk                (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
18571 #define USB_OTG_GUSBCFG_TOCAL                    USB_OTG_GUSBCFG_TOCAL_Msk     /*!< FS timeout calibration */
18572 #define USB_OTG_GUSBCFG_TOCAL_0                  (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
18573 #define USB_OTG_GUSBCFG_TOCAL_1                  (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
18574 #define USB_OTG_GUSBCFG_TOCAL_2                  (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
18575 #define USB_OTG_GUSBCFG_PHYSEL_Pos               (6U)
18576 #define USB_OTG_GUSBCFG_PHYSEL_Msk               (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
18577 #define USB_OTG_GUSBCFG_PHYSEL                   USB_OTG_GUSBCFG_PHYSEL_Msk    /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
18578 #define USB_OTG_GUSBCFG_SRPCAP_Pos               (8U)
18579 #define USB_OTG_GUSBCFG_SRPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
18580 #define USB_OTG_GUSBCFG_SRPCAP                   USB_OTG_GUSBCFG_SRPCAP_Msk    /*!< SRP-capable */
18581 #define USB_OTG_GUSBCFG_HNPCAP_Pos               (9U)
18582 #define USB_OTG_GUSBCFG_HNPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
18583 #define USB_OTG_GUSBCFG_HNPCAP                   USB_OTG_GUSBCFG_HNPCAP_Msk    /*!< HNP-capable */
18584 #define USB_OTG_GUSBCFG_TRDT_Pos                 (10U)
18585 #define USB_OTG_GUSBCFG_TRDT_Msk                 (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
18586 #define USB_OTG_GUSBCFG_TRDT                     USB_OTG_GUSBCFG_TRDT_Msk      /*!< USB turnaround time */
18587 #define USB_OTG_GUSBCFG_TRDT_0                   (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
18588 #define USB_OTG_GUSBCFG_TRDT_1                   (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
18589 #define USB_OTG_GUSBCFG_TRDT_2                   (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
18590 #define USB_OTG_GUSBCFG_TRDT_3                   (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
18591 #define USB_OTG_GUSBCFG_PHYLPCS_Pos              (15U)
18592 #define USB_OTG_GUSBCFG_PHYLPCS_Msk              (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
18593 #define USB_OTG_GUSBCFG_PHYLPCS                  USB_OTG_GUSBCFG_PHYLPCS_Msk   /*!< PHY Low-power clock select */
18594 #define USB_OTG_GUSBCFG_ULPIFSLS_Pos             (17U)
18595 #define USB_OTG_GUSBCFG_ULPIFSLS_Msk             (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
18596 #define USB_OTG_GUSBCFG_ULPIFSLS                 USB_OTG_GUSBCFG_ULPIFSLS_Msk  /*!< ULPI FS/LS select               */
18597 #define USB_OTG_GUSBCFG_ULPIAR_Pos               (18U)
18598 #define USB_OTG_GUSBCFG_ULPIAR_Msk               (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
18599 #define USB_OTG_GUSBCFG_ULPIAR                   USB_OTG_GUSBCFG_ULPIAR_Msk    /*!< ULPI Auto-resume                */
18600 #define USB_OTG_GUSBCFG_ULPICSM_Pos              (19U)
18601 #define USB_OTG_GUSBCFG_ULPICSM_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
18602 #define USB_OTG_GUSBCFG_ULPICSM                  USB_OTG_GUSBCFG_ULPICSM_Msk   /*!< ULPI Clock SuspendM             */
18603 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos           (20U)
18604 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
18605 #define USB_OTG_GUSBCFG_ULPIEVBUSD               USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive        */
18606 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos           (21U)
18607 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
18608 #define USB_OTG_GUSBCFG_ULPIEVBUSI               USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator    */
18609 #define USB_OTG_GUSBCFG_TSDPS_Pos                (22U)
18610 #define USB_OTG_GUSBCFG_TSDPS_Msk                (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
18611 #define USB_OTG_GUSBCFG_TSDPS                    USB_OTG_GUSBCFG_TSDPS_Msk     /*!< TermSel DLine pulsing selection */
18612 #define USB_OTG_GUSBCFG_PCCI_Pos                 (23U)
18613 #define USB_OTG_GUSBCFG_PCCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
18614 #define USB_OTG_GUSBCFG_PCCI                     USB_OTG_GUSBCFG_PCCI_Msk      /*!< Indicator complement            */
18615 #define USB_OTG_GUSBCFG_PTCI_Pos                 (24U)
18616 #define USB_OTG_GUSBCFG_PTCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
18617 #define USB_OTG_GUSBCFG_PTCI                     USB_OTG_GUSBCFG_PTCI_Msk      /*!< Indicator pass through          */
18618 #define USB_OTG_GUSBCFG_ULPIIPD_Pos              (25U)
18619 #define USB_OTG_GUSBCFG_ULPIIPD_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
18620 #define USB_OTG_GUSBCFG_ULPIIPD                  USB_OTG_GUSBCFG_ULPIIPD_Msk   /*!< ULPI interface protect disable  */
18621 #define USB_OTG_GUSBCFG_FHMOD_Pos                (29U)
18622 #define USB_OTG_GUSBCFG_FHMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
18623 #define USB_OTG_GUSBCFG_FHMOD                    USB_OTG_GUSBCFG_FHMOD_Msk     /*!< Forced host mode                */
18624 #define USB_OTG_GUSBCFG_FDMOD_Pos                (30U)
18625 #define USB_OTG_GUSBCFG_FDMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
18626 #define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode          */
18627 #define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)
18628 #define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
18629 #define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet               */
18630 
18631 /********************  Bit definition for USB_OTG_GRSTCTL register  ********************/
18632 #define USB_OTG_GRSTCTL_CSRST_Pos                (0U)
18633 #define USB_OTG_GRSTCTL_CSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
18634 #define USB_OTG_GRSTCTL_CSRST                    USB_OTG_GRSTCTL_CSRST_Msk     /*!< Core soft reset          */
18635 #define USB_OTG_GRSTCTL_HSRST_Pos                (1U)
18636 #define USB_OTG_GRSTCTL_HSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
18637 #define USB_OTG_GRSTCTL_HSRST                    USB_OTG_GRSTCTL_HSRST_Msk     /*!< HCLK soft reset          */
18638 #define USB_OTG_GRSTCTL_FCRST_Pos                (2U)
18639 #define USB_OTG_GRSTCTL_FCRST_Msk                (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
18640 #define USB_OTG_GRSTCTL_FCRST                    USB_OTG_GRSTCTL_FCRST_Msk     /*!< Host frame counter reset */
18641 #define USB_OTG_GRSTCTL_RXFFLSH_Pos              (4U)
18642 #define USB_OTG_GRSTCTL_RXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
18643 #define USB_OTG_GRSTCTL_RXFFLSH                  USB_OTG_GRSTCTL_RXFFLSH_Msk   /*!< RxFIFO flush             */
18644 #define USB_OTG_GRSTCTL_TXFFLSH_Pos              (5U)
18645 #define USB_OTG_GRSTCTL_TXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
18646 #define USB_OTG_GRSTCTL_TXFFLSH                  USB_OTG_GRSTCTL_TXFFLSH_Msk   /*!< TxFIFO flush             */
18647 
18648 
18649 #define USB_OTG_GRSTCTL_TXFNUM_Pos               (6U)
18650 #define USB_OTG_GRSTCTL_TXFNUM_Msk               (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
18651 #define USB_OTG_GRSTCTL_TXFNUM                   USB_OTG_GRSTCTL_TXFNUM_Msk    /*!< TxFIFO number */
18652 #define USB_OTG_GRSTCTL_TXFNUM_0                 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
18653 #define USB_OTG_GRSTCTL_TXFNUM_1                 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
18654 #define USB_OTG_GRSTCTL_TXFNUM_2                 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
18655 #define USB_OTG_GRSTCTL_TXFNUM_3                 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
18656 #define USB_OTG_GRSTCTL_TXFNUM_4                 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
18657 #define USB_OTG_GRSTCTL_DMAREQ_Pos               (30U)
18658 #define USB_OTG_GRSTCTL_DMAREQ_Msk               (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
18659 #define USB_OTG_GRSTCTL_DMAREQ                   USB_OTG_GRSTCTL_DMAREQ_Msk    /*!< DMA request signal */
18660 #define USB_OTG_GRSTCTL_AHBIDL_Pos               (31U)
18661 #define USB_OTG_GRSTCTL_AHBIDL_Msk               (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
18662 #define USB_OTG_GRSTCTL_AHBIDL                   USB_OTG_GRSTCTL_AHBIDL_Msk    /*!< AHB master idle */
18663 
18664 /********************  Bit definition for USB_OTG_DIEPMSK register  ********************/
18665 #define USB_OTG_DIEPMSK_XFRCM_Pos                (0U)
18666 #define USB_OTG_DIEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
18667 #define USB_OTG_DIEPMSK_XFRCM                    USB_OTG_DIEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask                 */
18668 #define USB_OTG_DIEPMSK_EPDM_Pos                 (1U)
18669 #define USB_OTG_DIEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
18670 #define USB_OTG_DIEPMSK_EPDM                     USB_OTG_DIEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask                  */
18671 #define USB_OTG_DIEPMSK_TOM_Pos                  (3U)
18672 #define USB_OTG_DIEPMSK_TOM_Msk                  (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
18673 #define USB_OTG_DIEPMSK_TOM                      USB_OTG_DIEPMSK_TOM_Msk       /*!< Timeout condition mask (nonisochronous endpoints) */
18674 #define USB_OTG_DIEPMSK_ITTXFEMSK_Pos            (4U)
18675 #define USB_OTG_DIEPMSK_ITTXFEMSK_Msk            (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
18676 #define USB_OTG_DIEPMSK_ITTXFEMSK                USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */
18677 #define USB_OTG_DIEPMSK_INEPNMM_Pos              (5U)
18678 #define USB_OTG_DIEPMSK_INEPNMM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
18679 #define USB_OTG_DIEPMSK_INEPNMM                  USB_OTG_DIEPMSK_INEPNMM_Msk   /*!< IN token received with EP mismatch mask           */
18680 #define USB_OTG_DIEPMSK_INEPNEM_Pos              (6U)
18681 #define USB_OTG_DIEPMSK_INEPNEM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
18682 #define USB_OTG_DIEPMSK_INEPNEM                  USB_OTG_DIEPMSK_INEPNEM_Msk   /*!< IN endpoint NAK effective mask                    */
18683 #define USB_OTG_DIEPMSK_TXFURM_Pos               (8U)
18684 #define USB_OTG_DIEPMSK_TXFURM_Msk               (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
18685 #define USB_OTG_DIEPMSK_TXFURM                   USB_OTG_DIEPMSK_TXFURM_Msk    /*!< FIFO underrun mask                                */
18686 #define USB_OTG_DIEPMSK_BIM_Pos                  (9U)
18687 #define USB_OTG_DIEPMSK_BIM_Msk                  (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
18688 #define USB_OTG_DIEPMSK_BIM                      USB_OTG_DIEPMSK_BIM_Msk       /*!< BNA interrupt mask                                */
18689 
18690 /********************  Bit definition for USB_OTG_HPTXSTS register  ********************/
18691 #define USB_OTG_HPTXSTS_PTXFSAVL_Pos             (0U)
18692 #define USB_OTG_HPTXSTS_PTXFSAVL_Msk             (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
18693 #define USB_OTG_HPTXSTS_PTXFSAVL                 USB_OTG_HPTXSTS_PTXFSAVL_Msk  /*!< Periodic transmit data FIFO space available     */
18694 #define USB_OTG_HPTXSTS_PTXQSAV_Pos              (16U)
18695 #define USB_OTG_HPTXSTS_PTXQSAV_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
18696 #define USB_OTG_HPTXSTS_PTXQSAV                  USB_OTG_HPTXSTS_PTXQSAV_Msk   /*!< Periodic transmit request queue space available */
18697 #define USB_OTG_HPTXSTS_PTXQSAV_0                (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
18698 #define USB_OTG_HPTXSTS_PTXQSAV_1                (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
18699 #define USB_OTG_HPTXSTS_PTXQSAV_2                (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
18700 #define USB_OTG_HPTXSTS_PTXQSAV_3                (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
18701 #define USB_OTG_HPTXSTS_PTXQSAV_4                (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
18702 #define USB_OTG_HPTXSTS_PTXQSAV_5                (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
18703 #define USB_OTG_HPTXSTS_PTXQSAV_6                (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
18704 #define USB_OTG_HPTXSTS_PTXQSAV_7                (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
18705 
18706 #define USB_OTG_HPTXSTS_PTXQTOP_Pos              (24U)
18707 #define USB_OTG_HPTXSTS_PTXQTOP_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
18708 #define USB_OTG_HPTXSTS_PTXQTOP                  USB_OTG_HPTXSTS_PTXQTOP_Msk   /*!< Top of the periodic transmit request queue */
18709 #define USB_OTG_HPTXSTS_PTXQTOP_0                (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
18710 #define USB_OTG_HPTXSTS_PTXQTOP_1                (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
18711 #define USB_OTG_HPTXSTS_PTXQTOP_2                (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
18712 #define USB_OTG_HPTXSTS_PTXQTOP_3                (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
18713 #define USB_OTG_HPTXSTS_PTXQTOP_4                (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
18714 #define USB_OTG_HPTXSTS_PTXQTOP_5                (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
18715 #define USB_OTG_HPTXSTS_PTXQTOP_6                (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
18716 #define USB_OTG_HPTXSTS_PTXQTOP_7                (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
18717 
18718 /********************  Bit definition for USB_OTG_HAINT register  ********************/
18719 #define USB_OTG_HAINT_HAINT_Pos                  (0U)
18720 #define USB_OTG_HAINT_HAINT_Msk                  (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
18721 #define USB_OTG_HAINT_HAINT                      USB_OTG_HAINT_HAINT_Msk       /*!< Channel interrupts */
18722 
18723 /********************  Bit definition for USB_OTG_DOEPMSK register  ********************/
18724 #define USB_OTG_DOEPMSK_XFRCM_Pos                (0U)
18725 #define USB_OTG_DOEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
18726 #define USB_OTG_DOEPMSK_XFRCM                    USB_OTG_DOEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask              */
18727 #define USB_OTG_DOEPMSK_EPDM_Pos                 (1U)
18728 #define USB_OTG_DOEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
18729 #define USB_OTG_DOEPMSK_EPDM                     USB_OTG_DOEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask               */
18730 #define USB_OTG_DOEPMSK_AHBERRM_Pos              (2U)
18731 #define USB_OTG_DOEPMSK_AHBERRM_Msk              (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */
18732 #define USB_OTG_DOEPMSK_AHBERRM                  USB_OTG_DOEPMSK_AHBERRM_Msk   /*!< OUT transaction AHB Error interrupt mask       */
18733 #define USB_OTG_DOEPMSK_STUPM_Pos                (3U)
18734 #define USB_OTG_DOEPMSK_STUPM_Msk                (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
18735 #define USB_OTG_DOEPMSK_STUPM                    USB_OTG_DOEPMSK_STUPM_Msk     /*!< SETUP phase done mask                          */
18736 #define USB_OTG_DOEPMSK_OTEPDM_Pos               (4U)
18737 #define USB_OTG_DOEPMSK_OTEPDM_Msk               (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
18738 #define USB_OTG_DOEPMSK_OTEPDM                   USB_OTG_DOEPMSK_OTEPDM_Msk    /*!< OUT token received when endpoint disabled mask */
18739 #define USB_OTG_DOEPMSK_OTEPSPRM_Pos             (5U)
18740 #define USB_OTG_DOEPMSK_OTEPSPRM_Msk             (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */
18741 #define USB_OTG_DOEPMSK_OTEPSPRM                 USB_OTG_DOEPMSK_OTEPSPRM_Msk  /*!< Status Phase Received mask                     */
18742 #define USB_OTG_DOEPMSK_B2BSTUP_Pos              (6U)
18743 #define USB_OTG_DOEPMSK_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
18744 #define USB_OTG_DOEPMSK_B2BSTUP                  USB_OTG_DOEPMSK_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received mask       */
18745 #define USB_OTG_DOEPMSK_OPEM_Pos                 (8U)
18746 #define USB_OTG_DOEPMSK_OPEM_Msk                 (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
18747 #define USB_OTG_DOEPMSK_OPEM                     USB_OTG_DOEPMSK_OPEM_Msk      /*!< OUT packet error mask                          */
18748 #define USB_OTG_DOEPMSK_BOIM_Pos                 (9U)
18749 #define USB_OTG_DOEPMSK_BOIM_Msk                 (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
18750 #define USB_OTG_DOEPMSK_BOIM                     USB_OTG_DOEPMSK_BOIM_Msk      /*!< BNA interrupt mask                             */
18751 #define USB_OTG_DOEPMSK_BERRM_Pos                (12U)
18752 #define USB_OTG_DOEPMSK_BERRM_Msk                (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */
18753 #define USB_OTG_DOEPMSK_BERRM                    USB_OTG_DOEPMSK_BERRM_Msk      /*!< Babble error interrupt mask                   */
18754 #define USB_OTG_DOEPMSK_NAKM_Pos                 (13U)
18755 #define USB_OTG_DOEPMSK_NAKM_Msk                 (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */
18756 #define USB_OTG_DOEPMSK_NAKM                     USB_OTG_DOEPMSK_NAKM_Msk      /*!< OUT Packet NAK interrupt mask                  */
18757 #define USB_OTG_DOEPMSK_NYETM_Pos                (14U)
18758 #define USB_OTG_DOEPMSK_NYETM_Msk                (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */
18759 #define USB_OTG_DOEPMSK_NYETM                    USB_OTG_DOEPMSK_NYETM_Msk     /*!< NYET interrupt mask                            */
18760 /********************  Bit definition for USB_OTG_GINTSTS register  ********************/
18761 #define USB_OTG_GINTSTS_CMOD_Pos                 (0U)
18762 #define USB_OTG_GINTSTS_CMOD_Msk                 (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
18763 #define USB_OTG_GINTSTS_CMOD                     USB_OTG_GINTSTS_CMOD_Msk      /*!< Current mode of operation                      */
18764 #define USB_OTG_GINTSTS_MMIS_Pos                 (1U)
18765 #define USB_OTG_GINTSTS_MMIS_Msk                 (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
18766 #define USB_OTG_GINTSTS_MMIS                     USB_OTG_GINTSTS_MMIS_Msk      /*!< Mode mismatch interrupt                        */
18767 #define USB_OTG_GINTSTS_OTGINT_Pos               (2U)
18768 #define USB_OTG_GINTSTS_OTGINT_Msk               (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
18769 #define USB_OTG_GINTSTS_OTGINT                   USB_OTG_GINTSTS_OTGINT_Msk    /*!< OTG interrupt                                  */
18770 #define USB_OTG_GINTSTS_SOF_Pos                  (3U)
18771 #define USB_OTG_GINTSTS_SOF_Msk                  (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
18772 #define USB_OTG_GINTSTS_SOF                      USB_OTG_GINTSTS_SOF_Msk       /*!< Start of frame                                 */
18773 #define USB_OTG_GINTSTS_RXFLVL_Pos               (4U)
18774 #define USB_OTG_GINTSTS_RXFLVL_Msk               (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
18775 #define USB_OTG_GINTSTS_RXFLVL                   USB_OTG_GINTSTS_RXFLVL_Msk    /*!< RxFIFO nonempty                                */
18776 #define USB_OTG_GINTSTS_NPTXFE_Pos               (5U)
18777 #define USB_OTG_GINTSTS_NPTXFE_Msk               (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
18778 #define USB_OTG_GINTSTS_NPTXFE                   USB_OTG_GINTSTS_NPTXFE_Msk    /*!< Nonperiodic TxFIFO empty                       */
18779 #define USB_OTG_GINTSTS_GINAKEFF_Pos             (6U)
18780 #define USB_OTG_GINTSTS_GINAKEFF_Msk             (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
18781 #define USB_OTG_GINTSTS_GINAKEFF                 USB_OTG_GINTSTS_GINAKEFF_Msk  /*!< Global IN nonperiodic NAK effective            */
18782 #define USB_OTG_GINTSTS_BOUTNAKEFF_Pos           (7U)
18783 #define USB_OTG_GINTSTS_BOUTNAKEFF_Msk           (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
18784 #define USB_OTG_GINTSTS_BOUTNAKEFF               USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective                       */
18785 #define USB_OTG_GINTSTS_ESUSP_Pos                (10U)
18786 #define USB_OTG_GINTSTS_ESUSP_Msk                (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
18787 #define USB_OTG_GINTSTS_ESUSP                    USB_OTG_GINTSTS_ESUSP_Msk     /*!< Early suspend                                  */
18788 #define USB_OTG_GINTSTS_USBSUSP_Pos              (11U)
18789 #define USB_OTG_GINTSTS_USBSUSP_Msk              (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
18790 #define USB_OTG_GINTSTS_USBSUSP                  USB_OTG_GINTSTS_USBSUSP_Msk   /*!< USB suspend                                    */
18791 #define USB_OTG_GINTSTS_USBRST_Pos               (12U)
18792 #define USB_OTG_GINTSTS_USBRST_Msk               (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
18793 #define USB_OTG_GINTSTS_USBRST                   USB_OTG_GINTSTS_USBRST_Msk    /*!< USB reset                                      */
18794 #define USB_OTG_GINTSTS_ENUMDNE_Pos              (13U)
18795 #define USB_OTG_GINTSTS_ENUMDNE_Msk              (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
18796 #define USB_OTG_GINTSTS_ENUMDNE                  USB_OTG_GINTSTS_ENUMDNE_Msk   /*!< Enumeration done                               */
18797 #define USB_OTG_GINTSTS_ISOODRP_Pos              (14U)
18798 #define USB_OTG_GINTSTS_ISOODRP_Msk              (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
18799 #define USB_OTG_GINTSTS_ISOODRP                  USB_OTG_GINTSTS_ISOODRP_Msk   /*!< Isochronous OUT packet dropped interrupt       */
18800 #define USB_OTG_GINTSTS_EOPF_Pos                 (15U)
18801 #define USB_OTG_GINTSTS_EOPF_Msk                 (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
18802 #define USB_OTG_GINTSTS_EOPF                     USB_OTG_GINTSTS_EOPF_Msk      /*!< End of periodic frame interrupt                */
18803 #define USB_OTG_GINTSTS_IEPINT_Pos               (18U)
18804 #define USB_OTG_GINTSTS_IEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
18805 #define USB_OTG_GINTSTS_IEPINT                   USB_OTG_GINTSTS_IEPINT_Msk    /*!< IN endpoint interrupt                          */
18806 #define USB_OTG_GINTSTS_OEPINT_Pos               (19U)
18807 #define USB_OTG_GINTSTS_OEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
18808 #define USB_OTG_GINTSTS_OEPINT                   USB_OTG_GINTSTS_OEPINT_Msk    /*!< OUT endpoint interrupt                         */
18809 #define USB_OTG_GINTSTS_IISOIXFR_Pos             (20U)
18810 #define USB_OTG_GINTSTS_IISOIXFR_Msk             (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
18811 #define USB_OTG_GINTSTS_IISOIXFR                 USB_OTG_GINTSTS_IISOIXFR_Msk  /*!< Incomplete isochronous IN transfer             */
18812 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos    (21U)
18813 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk    (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
18814 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT        USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer                   */
18815 #define USB_OTG_GINTSTS_DATAFSUSP_Pos            (22U)
18816 #define USB_OTG_GINTSTS_DATAFSUSP_Msk            (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
18817 #define USB_OTG_GINTSTS_DATAFSUSP                USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended                           */
18818 #define USB_OTG_GINTSTS_RSTDET_Pos               (23U)
18819 #define USB_OTG_GINTSTS_RSTDET_Msk               (0x1UL << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */
18820 #define USB_OTG_GINTSTS_RSTDET                   USB_OTG_GINTSTS_RSTDET_Msk    /*!< Reset detected interrupt                       */
18821 #define USB_OTG_GINTSTS_HPRTINT_Pos              (24U)
18822 #define USB_OTG_GINTSTS_HPRTINT_Msk              (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
18823 #define USB_OTG_GINTSTS_HPRTINT                  USB_OTG_GINTSTS_HPRTINT_Msk   /*!< Host port interrupt                            */
18824 #define USB_OTG_GINTSTS_HCINT_Pos                (25U)
18825 #define USB_OTG_GINTSTS_HCINT_Msk                (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
18826 #define USB_OTG_GINTSTS_HCINT                    USB_OTG_GINTSTS_HCINT_Msk     /*!< Host channels interrupt                        */
18827 #define USB_OTG_GINTSTS_PTXFE_Pos                (26U)
18828 #define USB_OTG_GINTSTS_PTXFE_Msk                (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
18829 #define USB_OTG_GINTSTS_PTXFE                    USB_OTG_GINTSTS_PTXFE_Msk     /*!< Periodic TxFIFO empty                          */
18830 #define USB_OTG_GINTSTS_LPMINT_Pos               (27U)
18831 #define USB_OTG_GINTSTS_LPMINT_Msk               (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */
18832 #define USB_OTG_GINTSTS_LPMINT                   USB_OTG_GINTSTS_LPMINT_Msk    /*!< LPM interrupt                                  */
18833 #define USB_OTG_GINTSTS_CIDSCHG_Pos              (28U)
18834 #define USB_OTG_GINTSTS_CIDSCHG_Msk              (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
18835 #define USB_OTG_GINTSTS_CIDSCHG                  USB_OTG_GINTSTS_CIDSCHG_Msk   /*!< Connector ID status change                     */
18836 #define USB_OTG_GINTSTS_DISCINT_Pos              (29U)
18837 #define USB_OTG_GINTSTS_DISCINT_Msk              (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
18838 #define USB_OTG_GINTSTS_DISCINT                  USB_OTG_GINTSTS_DISCINT_Msk   /*!< Disconnect detected interrupt                  */
18839 #define USB_OTG_GINTSTS_SRQINT_Pos               (30U)
18840 #define USB_OTG_GINTSTS_SRQINT_Msk               (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
18841 #define USB_OTG_GINTSTS_SRQINT                   USB_OTG_GINTSTS_SRQINT_Msk    /*!< Session request/new session detected interrupt */
18842 #define USB_OTG_GINTSTS_WKUINT_Pos               (31U)
18843 #define USB_OTG_GINTSTS_WKUINT_Msk               (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
18844 #define USB_OTG_GINTSTS_WKUINT                   USB_OTG_GINTSTS_WKUINT_Msk    /*!< Resume/remote wakeup detected interrupt        */
18845 
18846 /********************  Bit definition for USB_OTG_GINTMSK register  ********************/
18847 #define USB_OTG_GINTMSK_MMISM_Pos                (1U)
18848 #define USB_OTG_GINTMSK_MMISM_Msk                (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
18849 #define USB_OTG_GINTMSK_MMISM                    USB_OTG_GINTMSK_MMISM_Msk     /*!< Mode mismatch interrupt mask                        */
18850 #define USB_OTG_GINTMSK_OTGINT_Pos               (2U)
18851 #define USB_OTG_GINTMSK_OTGINT_Msk               (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
18852 #define USB_OTG_GINTMSK_OTGINT                   USB_OTG_GINTMSK_OTGINT_Msk    /*!< OTG interrupt mask                                  */
18853 #define USB_OTG_GINTMSK_SOFM_Pos                 (3U)
18854 #define USB_OTG_GINTMSK_SOFM_Msk                 (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
18855 #define USB_OTG_GINTMSK_SOFM                     USB_OTG_GINTMSK_SOFM_Msk      /*!< Start of frame mask                                 */
18856 #define USB_OTG_GINTMSK_RXFLVLM_Pos              (4U)
18857 #define USB_OTG_GINTMSK_RXFLVLM_Msk              (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
18858 #define USB_OTG_GINTMSK_RXFLVLM                  USB_OTG_GINTMSK_RXFLVLM_Msk   /*!< Receive FIFO nonempty mask                          */
18859 #define USB_OTG_GINTMSK_NPTXFEM_Pos              (5U)
18860 #define USB_OTG_GINTMSK_NPTXFEM_Msk              (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
18861 #define USB_OTG_GINTMSK_NPTXFEM                  USB_OTG_GINTMSK_NPTXFEM_Msk   /*!< Nonperiodic TxFIFO empty mask                       */
18862 #define USB_OTG_GINTMSK_GINAKEFFM_Pos            (6U)
18863 #define USB_OTG_GINTMSK_GINAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
18864 #define USB_OTG_GINTMSK_GINAKEFFM                USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask            */
18865 #define USB_OTG_GINTMSK_GONAKEFFM_Pos            (7U)
18866 #define USB_OTG_GINTMSK_GONAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
18867 #define USB_OTG_GINTMSK_GONAKEFFM                USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask                       */
18868 #define USB_OTG_GINTMSK_ESUSPM_Pos               (10U)
18869 #define USB_OTG_GINTMSK_ESUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
18870 #define USB_OTG_GINTMSK_ESUSPM                   USB_OTG_GINTMSK_ESUSPM_Msk    /*!< Early suspend mask                                  */
18871 #define USB_OTG_GINTMSK_USBSUSPM_Pos             (11U)
18872 #define USB_OTG_GINTMSK_USBSUSPM_Msk             (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
18873 #define USB_OTG_GINTMSK_USBSUSPM                 USB_OTG_GINTMSK_USBSUSPM_Msk  /*!< USB suspend mask                                    */
18874 #define USB_OTG_GINTMSK_USBRST_Pos               (12U)
18875 #define USB_OTG_GINTMSK_USBRST_Msk               (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
18876 #define USB_OTG_GINTMSK_USBRST                   USB_OTG_GINTMSK_USBRST_Msk    /*!< USB reset mask                                      */
18877 #define USB_OTG_GINTMSK_ENUMDNEM_Pos             (13U)
18878 #define USB_OTG_GINTMSK_ENUMDNEM_Msk             (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
18879 #define USB_OTG_GINTMSK_ENUMDNEM                 USB_OTG_GINTMSK_ENUMDNEM_Msk  /*!< Enumeration done mask                               */
18880 #define USB_OTG_GINTMSK_ISOODRPM_Pos             (14U)
18881 #define USB_OTG_GINTMSK_ISOODRPM_Msk             (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
18882 #define USB_OTG_GINTMSK_ISOODRPM                 USB_OTG_GINTMSK_ISOODRPM_Msk  /*!< Isochronous OUT packet dropped interrupt mask       */
18883 #define USB_OTG_GINTMSK_EOPFM_Pos                (15U)
18884 #define USB_OTG_GINTMSK_EOPFM_Msk                (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
18885 #define USB_OTG_GINTMSK_EOPFM                    USB_OTG_GINTMSK_EOPFM_Msk     /*!< End of periodic frame interrupt mask                */
18886 #define USB_OTG_GINTMSK_EPMISM_Pos               (17U)
18887 #define USB_OTG_GINTMSK_EPMISM_Msk               (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
18888 #define USB_OTG_GINTMSK_EPMISM                   USB_OTG_GINTMSK_EPMISM_Msk    /*!< Endpoint mismatch interrupt mask                    */
18889 #define USB_OTG_GINTMSK_IEPINT_Pos               (18U)
18890 #define USB_OTG_GINTMSK_IEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
18891 #define USB_OTG_GINTMSK_IEPINT                   USB_OTG_GINTMSK_IEPINT_Msk    /*!< IN endpoints interrupt mask                         */
18892 #define USB_OTG_GINTMSK_OEPINT_Pos               (19U)
18893 #define USB_OTG_GINTMSK_OEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
18894 #define USB_OTG_GINTMSK_OEPINT                   USB_OTG_GINTMSK_OEPINT_Msk    /*!< OUT endpoints interrupt mask                        */
18895 #define USB_OTG_GINTMSK_IISOIXFRM_Pos            (20U)
18896 #define USB_OTG_GINTMSK_IISOIXFRM_Msk            (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
18897 #define USB_OTG_GINTMSK_IISOIXFRM                USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask             */
18898 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos      (21U)
18899 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk      (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
18900 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM          USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask                   */
18901 #define USB_OTG_GINTMSK_FSUSPM_Pos               (22U)
18902 #define USB_OTG_GINTMSK_FSUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
18903 #define USB_OTG_GINTMSK_FSUSPM                   USB_OTG_GINTMSK_FSUSPM_Msk    /*!< Data fetch suspended mask                           */
18904 #define USB_OTG_GINTMSK_RSTDEM_Pos               (23U)
18905 #define USB_OTG_GINTMSK_RSTDEM_Msk               (0x1UL << USB_OTG_GINTMSK_RSTDEM_Pos) /*!< 0x00800000 */
18906 #define USB_OTG_GINTMSK_RSTDEM                   USB_OTG_GINTMSK_RSTDEM_Msk    /*!< Reset detected interrupt mask                      */
18907 #define USB_OTG_GINTMSK_PRTIM_Pos                (24U)
18908 #define USB_OTG_GINTMSK_PRTIM_Msk                (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
18909 #define USB_OTG_GINTMSK_PRTIM                    USB_OTG_GINTMSK_PRTIM_Msk     /*!< Host port interrupt mask                            */
18910 #define USB_OTG_GINTMSK_HCIM_Pos                 (25U)
18911 #define USB_OTG_GINTMSK_HCIM_Msk                 (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
18912 #define USB_OTG_GINTMSK_HCIM                     USB_OTG_GINTMSK_HCIM_Msk      /*!< Host channels interrupt mask                        */
18913 #define USB_OTG_GINTMSK_PTXFEM_Pos               (26U)
18914 #define USB_OTG_GINTMSK_PTXFEM_Msk               (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
18915 #define USB_OTG_GINTMSK_PTXFEM                   USB_OTG_GINTMSK_PTXFEM_Msk    /*!< Periodic TxFIFO empty mask                          */
18916 #define USB_OTG_GINTMSK_LPMINTM_Pos              (27U)
18917 #define USB_OTG_GINTMSK_LPMINTM_Msk              (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */
18918 #define USB_OTG_GINTMSK_LPMINTM                  USB_OTG_GINTMSK_LPMINTM_Msk   /*!< LPM interrupt Mask                                  */
18919 #define USB_OTG_GINTMSK_CIDSCHGM_Pos             (28U)
18920 #define USB_OTG_GINTMSK_CIDSCHGM_Msk             (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
18921 #define USB_OTG_GINTMSK_CIDSCHGM                 USB_OTG_GINTMSK_CIDSCHGM_Msk  /*!< Connector ID status change mask                     */
18922 #define USB_OTG_GINTMSK_DISCINT_Pos              (29U)
18923 #define USB_OTG_GINTMSK_DISCINT_Msk              (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
18924 #define USB_OTG_GINTMSK_DISCINT                  USB_OTG_GINTMSK_DISCINT_Msk   /*!< Disconnect detected interrupt mask                  */
18925 #define USB_OTG_GINTMSK_SRQIM_Pos                (30U)
18926 #define USB_OTG_GINTMSK_SRQIM_Msk                (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
18927 #define USB_OTG_GINTMSK_SRQIM                    USB_OTG_GINTMSK_SRQIM_Msk     /*!< Session request/new session detected interrupt mask */
18928 #define USB_OTG_GINTMSK_WUIM_Pos                 (31U)
18929 #define USB_OTG_GINTMSK_WUIM_Msk                 (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
18930 #define USB_OTG_GINTMSK_WUIM                     USB_OTG_GINTMSK_WUIM_Msk      /*!< Resume/remote wakeup detected interrupt mask        */
18931 
18932 /********************  Bit definition for USB_OTG_DAINT register  ********************/
18933 #define USB_OTG_DAINT_IEPINT_Pos                 (0U)
18934 #define USB_OTG_DAINT_IEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
18935 #define USB_OTG_DAINT_IEPINT                     USB_OTG_DAINT_IEPINT_Msk      /*!< IN endpoint interrupt bits  */
18936 #define USB_OTG_DAINT_OEPINT_Pos                 (16U)
18937 #define USB_OTG_DAINT_OEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
18938 #define USB_OTG_DAINT_OEPINT                     USB_OTG_DAINT_OEPINT_Msk      /*!< OUT endpoint interrupt bits */
18939 
18940 /********************  Bit definition for USB_OTG_HAINTMSK register  ********************/
18941 #define USB_OTG_HAINTMSK_HAINTM_Pos              (0U)
18942 #define USB_OTG_HAINTMSK_HAINTM_Msk              (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
18943 #define USB_OTG_HAINTMSK_HAINTM                  USB_OTG_HAINTMSK_HAINTM_Msk   /*!< Channel interrupt mask */
18944 
18945 /********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
18946 #define USB_OTG_GRXSTSP_EPNUM_Pos                (0U)
18947 #define USB_OTG_GRXSTSP_EPNUM_Msk                (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
18948 #define USB_OTG_GRXSTSP_EPNUM                    USB_OTG_GRXSTSP_EPNUM_Msk     /*!< IN EP interrupt mask bits  */
18949 #define USB_OTG_GRXSTSP_BCNT_Pos                 (4U)
18950 #define USB_OTG_GRXSTSP_BCNT_Msk                 (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
18951 #define USB_OTG_GRXSTSP_BCNT                     USB_OTG_GRXSTSP_BCNT_Msk      /*!< OUT EP interrupt mask bits */
18952 #define USB_OTG_GRXSTSP_DPID_Pos                 (15U)
18953 #define USB_OTG_GRXSTSP_DPID_Msk                 (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
18954 #define USB_OTG_GRXSTSP_DPID                     USB_OTG_GRXSTSP_DPID_Msk      /*!< OUT EP interrupt mask bits */
18955 #define USB_OTG_GRXSTSP_PKTSTS_Pos               (17U)
18956 #define USB_OTG_GRXSTSP_PKTSTS_Msk               (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
18957 #define USB_OTG_GRXSTSP_PKTSTS                   USB_OTG_GRXSTSP_PKTSTS_Msk    /*!< OUT EP interrupt mask bits */
18958 
18959 /********************  Bit definition for USB_OTG_DAINTMSK register  ********************/
18960 #define USB_OTG_DAINTMSK_IEPM_Pos                (0U)
18961 #define USB_OTG_DAINTMSK_IEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
18962 #define USB_OTG_DAINTMSK_IEPM                    USB_OTG_DAINTMSK_IEPM_Msk     /*!< IN EP interrupt mask bits */
18963 #define USB_OTG_DAINTMSK_OEPM_Pos                (16U)
18964 #define USB_OTG_DAINTMSK_OEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
18965 #define USB_OTG_DAINTMSK_OEPM                    USB_OTG_DAINTMSK_OEPM_Msk     /*!< OUT EP interrupt mask bits */
18966 
18967 /********************  Bit definition for USB_OTG_GRXFSIZ register  ********************/
18968 #define USB_OTG_GRXFSIZ_RXFD_Pos                 (0U)
18969 #define USB_OTG_GRXFSIZ_RXFD_Msk                 (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
18970 #define USB_OTG_GRXFSIZ_RXFD                     USB_OTG_GRXFSIZ_RXFD_Msk      /*!< RxFIFO depth */
18971 
18972 /********************  Bit definition for USB_OTG_DVBUSDIS register  ********************/
18973 #define USB_OTG_DVBUSDIS_VBUSDT_Pos              (0U)
18974 #define USB_OTG_DVBUSDIS_VBUSDT_Msk              (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
18975 #define USB_OTG_DVBUSDIS_VBUSDT                  USB_OTG_DVBUSDIS_VBUSDT_Msk   /*!< Device VBUS discharge time */
18976 
18977 /********************  Bit definition for OTG register  ********************/
18978 #define USB_OTG_NPTXFSA_Pos                      (0U)
18979 #define USB_OTG_NPTXFSA_Msk                      (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
18980 #define USB_OTG_NPTXFSA                          USB_OTG_NPTXFSA_Msk           /*!< Nonperiodic transmit RAM start address */
18981 #define USB_OTG_NPTXFD_Pos                       (16U)
18982 #define USB_OTG_NPTXFD_Msk                       (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
18983 #define USB_OTG_NPTXFD                           USB_OTG_NPTXFD_Msk            /*!< Nonperiodic TxFIFO depth               */
18984 #define USB_OTG_TX0FSA_Pos                       (0U)
18985 #define USB_OTG_TX0FSA_Msk                       (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
18986 #define USB_OTG_TX0FSA                           USB_OTG_TX0FSA_Msk            /*!< Endpoint 0 transmit RAM start address  */
18987 #define USB_OTG_TX0FD_Pos                        (16U)
18988 #define USB_OTG_TX0FD_Msk                        (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
18989 #define USB_OTG_TX0FD                            USB_OTG_TX0FD_Msk             /*!< Endpoint 0 TxFIFO depth                */
18990 
18991 /********************  Bit definition forUSB_OTG_DVBUSPULSE register  ********************/
18992 #define USB_OTG_DVBUSPULSE_DVBUSP_Pos            (0U)
18993 #define USB_OTG_DVBUSPULSE_DVBUSP_Msk            (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
18994 #define USB_OTG_DVBUSPULSE_DVBUSP                USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
18995 
18996 /********************  Bit definition for USB_OTG_GNPTXSTS register  ********************/
18997 #define USB_OTG_GNPTXSTS_NPTXFSAV_Pos            (0U)
18998 #define USB_OTG_GNPTXSTS_NPTXFSAV_Msk            (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
18999 #define USB_OTG_GNPTXSTS_NPTXFSAV                USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
19000 
19001 #define USB_OTG_GNPTXSTS_NPTQXSAV_Pos            (16U)
19002 #define USB_OTG_GNPTXSTS_NPTQXSAV_Msk            (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
19003 #define USB_OTG_GNPTXSTS_NPTQXSAV                USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
19004 #define USB_OTG_GNPTXSTS_NPTQXSAV_0              (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
19005 #define USB_OTG_GNPTXSTS_NPTQXSAV_1              (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
19006 #define USB_OTG_GNPTXSTS_NPTQXSAV_2              (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
19007 #define USB_OTG_GNPTXSTS_NPTQXSAV_3              (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
19008 #define USB_OTG_GNPTXSTS_NPTQXSAV_4              (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
19009 #define USB_OTG_GNPTXSTS_NPTQXSAV_5              (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
19010 #define USB_OTG_GNPTXSTS_NPTQXSAV_6              (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
19011 #define USB_OTG_GNPTXSTS_NPTQXSAV_7              (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
19012 
19013 #define USB_OTG_GNPTXSTS_NPTXQTOP_Pos            (24U)
19014 #define USB_OTG_GNPTXSTS_NPTXQTOP_Msk            (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
19015 #define USB_OTG_GNPTXSTS_NPTXQTOP                USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
19016 #define USB_OTG_GNPTXSTS_NPTXQTOP_0              (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
19017 #define USB_OTG_GNPTXSTS_NPTXQTOP_1              (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
19018 #define USB_OTG_GNPTXSTS_NPTXQTOP_2              (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
19019 #define USB_OTG_GNPTXSTS_NPTXQTOP_3              (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
19020 #define USB_OTG_GNPTXSTS_NPTXQTOP_4              (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
19021 #define USB_OTG_GNPTXSTS_NPTXQTOP_5              (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
19022 #define USB_OTG_GNPTXSTS_NPTXQTOP_6              (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
19023 
19024 /********************  Bit definition for USB_OTG_DTHRCTL register  ********************/
19025 #define USB_OTG_DTHRCTL_NONISOTHREN_Pos          (0U)
19026 #define USB_OTG_DTHRCTL_NONISOTHREN_Msk          (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
19027 #define USB_OTG_DTHRCTL_NONISOTHREN              USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
19028 #define USB_OTG_DTHRCTL_ISOTHREN_Pos             (1U)
19029 #define USB_OTG_DTHRCTL_ISOTHREN_Msk             (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
19030 #define USB_OTG_DTHRCTL_ISOTHREN                 USB_OTG_DTHRCTL_ISOTHREN_Msk  /*!< ISO IN endpoint threshold enable */
19031 
19032 #define USB_OTG_DTHRCTL_TXTHRLEN_Pos             (2U)
19033 #define USB_OTG_DTHRCTL_TXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
19034 #define USB_OTG_DTHRCTL_TXTHRLEN                 USB_OTG_DTHRCTL_TXTHRLEN_Msk  /*!< Transmit threshold length */
19035 #define USB_OTG_DTHRCTL_TXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
19036 #define USB_OTG_DTHRCTL_TXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
19037 #define USB_OTG_DTHRCTL_TXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
19038 #define USB_OTG_DTHRCTL_TXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
19039 #define USB_OTG_DTHRCTL_TXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
19040 #define USB_OTG_DTHRCTL_TXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
19041 #define USB_OTG_DTHRCTL_TXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
19042 #define USB_OTG_DTHRCTL_TXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
19043 #define USB_OTG_DTHRCTL_TXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
19044 #define USB_OTG_DTHRCTL_RXTHREN_Pos              (16U)
19045 #define USB_OTG_DTHRCTL_RXTHREN_Msk              (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
19046 #define USB_OTG_DTHRCTL_RXTHREN                  USB_OTG_DTHRCTL_RXTHREN_Msk   /*!< Receive threshold enable */
19047 
19048 #define USB_OTG_DTHRCTL_RXTHRLEN_Pos             (17U)
19049 #define USB_OTG_DTHRCTL_RXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
19050 #define USB_OTG_DTHRCTL_RXTHRLEN                 USB_OTG_DTHRCTL_RXTHRLEN_Msk  /*!< Receive threshold length */
19051 #define USB_OTG_DTHRCTL_RXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
19052 #define USB_OTG_DTHRCTL_RXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
19053 #define USB_OTG_DTHRCTL_RXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
19054 #define USB_OTG_DTHRCTL_RXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
19055 #define USB_OTG_DTHRCTL_RXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
19056 #define USB_OTG_DTHRCTL_RXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
19057 #define USB_OTG_DTHRCTL_RXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
19058 #define USB_OTG_DTHRCTL_RXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
19059 #define USB_OTG_DTHRCTL_RXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
19060 #define USB_OTG_DTHRCTL_ARPEN_Pos                (27U)
19061 #define USB_OTG_DTHRCTL_ARPEN_Msk                (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
19062 #define USB_OTG_DTHRCTL_ARPEN                    USB_OTG_DTHRCTL_ARPEN_Msk     /*!< Arbiter parking enable */
19063 
19064 /********************  Bit definition for USB_OTG_DIEPEMPMSK register  ********************/
19065 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos         (0U)
19066 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk         (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
19067 #define USB_OTG_DIEPEMPMSK_INEPTXFEM             USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
19068 
19069 /********************  Bit definition for USB_OTG_DEACHINT register  ********************/
19070 #define USB_OTG_DEACHINT_IEP1INT_Pos             (1U)
19071 #define USB_OTG_DEACHINT_IEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
19072 #define USB_OTG_DEACHINT_IEP1INT                 USB_OTG_DEACHINT_IEP1INT_Msk  /*!< IN endpoint 1interrupt bit   */
19073 #define USB_OTG_DEACHINT_OEP1INT_Pos             (17U)
19074 #define USB_OTG_DEACHINT_OEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
19075 #define USB_OTG_DEACHINT_OEP1INT                 USB_OTG_DEACHINT_OEP1INT_Msk  /*!< OUT endpoint 1 interrupt bit */
19076 
19077 /********************  Bit definition for USB_OTG_GCCFG register  ********************/
19078 #define USB_OTG_GCCFG_PWRDWN_Pos                 (16U)
19079 #define USB_OTG_GCCFG_PWRDWN_Msk                 (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
19080 #define USB_OTG_GCCFG_PWRDWN                     USB_OTG_GCCFG_PWRDWN_Msk      /*!< Power down */
19081 #define USB_OTG_GCCFG_VBDEN_Pos                  (21U)
19082 #define USB_OTG_GCCFG_VBDEN_Msk                  (0x1UL << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */
19083 #define USB_OTG_GCCFG_VBDEN                      USB_OTG_GCCFG_VBDEN_Msk       /*!< USB VBUS Detection Enable */
19084 
19085 /********************  Bit definition forUSB_OTG_DEACHINTMSK register  ********************/
19086 #define USB_OTG_DEACHINTMSK_IEP1INTM_Pos         (1U)
19087 #define USB_OTG_DEACHINTMSK_IEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
19088 #define USB_OTG_DEACHINTMSK_IEP1INTM             USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit  */
19089 #define USB_OTG_DEACHINTMSK_OEP1INTM_Pos         (17U)
19090 #define USB_OTG_DEACHINTMSK_OEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
19091 #define USB_OTG_DEACHINTMSK_OEP1INTM             USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
19092 
19093 /********************  Bit definition for USB_OTG_CID register  ********************/
19094 #define USB_OTG_CID_PRODUCT_ID_Pos               (0U)
19095 #define USB_OTG_CID_PRODUCT_ID_Msk               (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
19096 #define USB_OTG_CID_PRODUCT_ID                   USB_OTG_CID_PRODUCT_ID_Msk    /*!< Product ID field */
19097 
19098 /********************  Bit definition for USB_OTG_GLPMCFG register  ********************/
19099 #define USB_OTG_GLPMCFG_LPMEN_Pos                (0U)
19100 #define USB_OTG_GLPMCFG_LPMEN_Msk                (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */
19101 #define USB_OTG_GLPMCFG_LPMEN                    USB_OTG_GLPMCFG_LPMEN_Msk     /*!< LPM support enable                                     */
19102 #define USB_OTG_GLPMCFG_LPMACK_Pos               (1U)
19103 #define USB_OTG_GLPMCFG_LPMACK_Msk               (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */
19104 #define USB_OTG_GLPMCFG_LPMACK                   USB_OTG_GLPMCFG_LPMACK_Msk    /*!< LPM Token acknowledge enable                           */
19105 #define USB_OTG_GLPMCFG_BESL_Pos                 (2U)
19106 #define USB_OTG_GLPMCFG_BESL_Msk                 (0xFUL << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */
19107 #define USB_OTG_GLPMCFG_BESL                     USB_OTG_GLPMCFG_BESL_Msk      /*!< BESL value received with last ACKed LPM Token          */
19108 #define USB_OTG_GLPMCFG_REMWAKE_Pos              (6U)
19109 #define USB_OTG_GLPMCFG_REMWAKE_Msk              (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */
19110 #define USB_OTG_GLPMCFG_REMWAKE                  USB_OTG_GLPMCFG_REMWAKE_Msk   /*!< bRemoteWake value received with last ACKed LPM Token   */
19111 #define USB_OTG_GLPMCFG_L1SSEN_Pos               (7U)
19112 #define USB_OTG_GLPMCFG_L1SSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */
19113 #define USB_OTG_GLPMCFG_L1SSEN                   USB_OTG_GLPMCFG_L1SSEN_Msk    /*!< L1 shallow sleep enable                                */
19114 #define USB_OTG_GLPMCFG_BESLTHRS_Pos             (8U)
19115 #define USB_OTG_GLPMCFG_BESLTHRS_Msk             (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */
19116 #define USB_OTG_GLPMCFG_BESLTHRS                 USB_OTG_GLPMCFG_BESLTHRS_Msk  /*!< BESL threshold                                         */
19117 #define USB_OTG_GLPMCFG_L1DSEN_Pos               (12U)
19118 #define USB_OTG_GLPMCFG_L1DSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */
19119 #define USB_OTG_GLPMCFG_L1DSEN                   USB_OTG_GLPMCFG_L1DSEN_Msk    /*!< L1 deep sleep enable                                   */
19120 #define USB_OTG_GLPMCFG_LPMRSP_Pos               (13U)
19121 #define USB_OTG_GLPMCFG_LPMRSP_Msk               (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */
19122 #define USB_OTG_GLPMCFG_LPMRSP                   USB_OTG_GLPMCFG_LPMRSP_Msk    /*!< LPM response                                           */
19123 #define USB_OTG_GLPMCFG_SLPSTS_Pos               (15U)
19124 #define USB_OTG_GLPMCFG_SLPSTS_Msk               (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */
19125 #define USB_OTG_GLPMCFG_SLPSTS                   USB_OTG_GLPMCFG_SLPSTS_Msk    /*!< Port sleep status                                      */
19126 #define USB_OTG_GLPMCFG_L1RSMOK_Pos              (16U)
19127 #define USB_OTG_GLPMCFG_L1RSMOK_Msk              (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */
19128 #define USB_OTG_GLPMCFG_L1RSMOK                  USB_OTG_GLPMCFG_L1RSMOK_Msk   /*!< Sleep State Resume OK                                  */
19129 #define USB_OTG_GLPMCFG_LPMCHIDX_Pos             (17U)
19130 #define USB_OTG_GLPMCFG_LPMCHIDX_Msk             (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */
19131 #define USB_OTG_GLPMCFG_LPMCHIDX                 USB_OTG_GLPMCFG_LPMCHIDX_Msk  /*!< LPM Channel Index                                      */
19132 #define USB_OTG_GLPMCFG_LPMRCNT_Pos              (21U)
19133 #define USB_OTG_GLPMCFG_LPMRCNT_Msk              (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */
19134 #define USB_OTG_GLPMCFG_LPMRCNT                  USB_OTG_GLPMCFG_LPMRCNT_Msk   /*!< LPM retry count                                        */
19135 #define USB_OTG_GLPMCFG_SNDLPM_Pos               (24U)
19136 #define USB_OTG_GLPMCFG_SNDLPM_Msk               (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */
19137 #define USB_OTG_GLPMCFG_SNDLPM                   USB_OTG_GLPMCFG_SNDLPM_Msk    /*!< Send LPM transaction                                   */
19138 #define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos           (25U)
19139 #define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk           (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */
19140 #define USB_OTG_GLPMCFG_LPMRCNTSTS               USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status                                 */
19141 #define USB_OTG_GLPMCFG_ENBESL_Pos               (28U)
19142 #define USB_OTG_GLPMCFG_ENBESL_Msk               (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */
19143 #define USB_OTG_GLPMCFG_ENBESL                   USB_OTG_GLPMCFG_ENBESL_Msk    /*!< Enable best effort service latency                     */
19144 
19145 /********************  Bit definition for USB_OTG_DIEPEACHMSK1 register  ********************/
19146 #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos           (0U)
19147 #define USB_OTG_DIEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
19148 #define USB_OTG_DIEPEACHMSK1_XFRCM               USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask                 */
19149 #define USB_OTG_DIEPEACHMSK1_EPDM_Pos            (1U)
19150 #define USB_OTG_DIEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
19151 #define USB_OTG_DIEPEACHMSK1_EPDM                USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask                  */
19152 #define USB_OTG_DIEPEACHMSK1_TOM_Pos             (3U)
19153 #define USB_OTG_DIEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
19154 #define USB_OTG_DIEPEACHMSK1_TOM                 USB_OTG_DIEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask (nonisochronous endpoints) */
19155 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos       (4U)
19156 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
19157 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK           USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */
19158 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos         (5U)
19159 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
19160 #define USB_OTG_DIEPEACHMSK1_INEPNMM             USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask           */
19161 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos         (6U)
19162 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
19163 #define USB_OTG_DIEPEACHMSK1_INEPNEM             USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask                    */
19164 #define USB_OTG_DIEPEACHMSK1_TXFURM_Pos          (8U)
19165 #define USB_OTG_DIEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
19166 #define USB_OTG_DIEPEACHMSK1_TXFURM              USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask                                */
19167 #define USB_OTG_DIEPEACHMSK1_BIM_Pos             (9U)
19168 #define USB_OTG_DIEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
19169 #define USB_OTG_DIEPEACHMSK1_BIM                 USB_OTG_DIEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask                                */
19170 #define USB_OTG_DIEPEACHMSK1_NAKM_Pos            (13U)
19171 #define USB_OTG_DIEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
19172 #define USB_OTG_DIEPEACHMSK1_NAKM                USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask                                */
19173 
19174 /********************  Bit definition for USB_OTG_HPRT register  ********************/
19175 #define USB_OTG_HPRT_PCSTS_Pos                   (0U)
19176 #define USB_OTG_HPRT_PCSTS_Msk                   (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
19177 #define USB_OTG_HPRT_PCSTS                       USB_OTG_HPRT_PCSTS_Msk        /*!< Port connect status        */
19178 #define USB_OTG_HPRT_PCDET_Pos                   (1U)
19179 #define USB_OTG_HPRT_PCDET_Msk                   (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
19180 #define USB_OTG_HPRT_PCDET                       USB_OTG_HPRT_PCDET_Msk        /*!< Port connect detected      */
19181 #define USB_OTG_HPRT_PENA_Pos                    (2U)
19182 #define USB_OTG_HPRT_PENA_Msk                    (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
19183 #define USB_OTG_HPRT_PENA                        USB_OTG_HPRT_PENA_Msk         /*!< Port enable                */
19184 #define USB_OTG_HPRT_PENCHNG_Pos                 (3U)
19185 #define USB_OTG_HPRT_PENCHNG_Msk                 (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
19186 #define USB_OTG_HPRT_PENCHNG                     USB_OTG_HPRT_PENCHNG_Msk      /*!< Port enable/disable change */
19187 #define USB_OTG_HPRT_POCA_Pos                    (4U)
19188 #define USB_OTG_HPRT_POCA_Msk                    (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
19189 #define USB_OTG_HPRT_POCA                        USB_OTG_HPRT_POCA_Msk         /*!< Port overcurrent active    */
19190 #define USB_OTG_HPRT_POCCHNG_Pos                 (5U)
19191 #define USB_OTG_HPRT_POCCHNG_Msk                 (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
19192 #define USB_OTG_HPRT_POCCHNG                     USB_OTG_HPRT_POCCHNG_Msk      /*!< Port overcurrent change    */
19193 #define USB_OTG_HPRT_PRES_Pos                    (6U)
19194 #define USB_OTG_HPRT_PRES_Msk                    (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
19195 #define USB_OTG_HPRT_PRES                        USB_OTG_HPRT_PRES_Msk         /*!< Port resume                */
19196 #define USB_OTG_HPRT_PSUSP_Pos                   (7U)
19197 #define USB_OTG_HPRT_PSUSP_Msk                   (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
19198 #define USB_OTG_HPRT_PSUSP                       USB_OTG_HPRT_PSUSP_Msk        /*!< Port suspend               */
19199 #define USB_OTG_HPRT_PRST_Pos                    (8U)
19200 #define USB_OTG_HPRT_PRST_Msk                    (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
19201 #define USB_OTG_HPRT_PRST                        USB_OTG_HPRT_PRST_Msk         /*!< Port reset                 */
19202 
19203 #define USB_OTG_HPRT_PLSTS_Pos                   (10U)
19204 #define USB_OTG_HPRT_PLSTS_Msk                   (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
19205 #define USB_OTG_HPRT_PLSTS                       USB_OTG_HPRT_PLSTS_Msk        /*!< Port line status           */
19206 #define USB_OTG_HPRT_PLSTS_0                     (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
19207 #define USB_OTG_HPRT_PLSTS_1                     (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
19208 #define USB_OTG_HPRT_PPWR_Pos                    (12U)
19209 #define USB_OTG_HPRT_PPWR_Msk                    (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
19210 #define USB_OTG_HPRT_PPWR                        USB_OTG_HPRT_PPWR_Msk         /*!< Port power                 */
19211 
19212 #define USB_OTG_HPRT_PTCTL_Pos                   (13U)
19213 #define USB_OTG_HPRT_PTCTL_Msk                   (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
19214 #define USB_OTG_HPRT_PTCTL                       USB_OTG_HPRT_PTCTL_Msk        /*!< Port test control          */
19215 #define USB_OTG_HPRT_PTCTL_0                     (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
19216 #define USB_OTG_HPRT_PTCTL_1                     (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
19217 #define USB_OTG_HPRT_PTCTL_2                     (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
19218 #define USB_OTG_HPRT_PTCTL_3                     (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
19219 
19220 #define USB_OTG_HPRT_PSPD_Pos                    (17U)
19221 #define USB_OTG_HPRT_PSPD_Msk                    (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
19222 #define USB_OTG_HPRT_PSPD                        USB_OTG_HPRT_PSPD_Msk         /*!< Port speed                 */
19223 #define USB_OTG_HPRT_PSPD_0                      (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
19224 #define USB_OTG_HPRT_PSPD_1                      (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
19225 
19226 /********************  Bit definition for USB_OTG_DOEPEACHMSK1 register  ********************/
19227 #define USB_OTG_DOEPEACHMSK1_XFRCM_Pos           (0U)
19228 #define USB_OTG_DOEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
19229 #define USB_OTG_DOEPEACHMSK1_XFRCM               USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask         */
19230 #define USB_OTG_DOEPEACHMSK1_EPDM_Pos            (1U)
19231 #define USB_OTG_DOEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
19232 #define USB_OTG_DOEPEACHMSK1_EPDM                USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask          */
19233 #define USB_OTG_DOEPEACHMSK1_TOM_Pos             (3U)
19234 #define USB_OTG_DOEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
19235 #define USB_OTG_DOEPEACHMSK1_TOM                 USB_OTG_DOEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask                    */
19236 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos       (4U)
19237 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
19238 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK           USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask  */
19239 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos         (5U)
19240 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
19241 #define USB_OTG_DOEPEACHMSK1_INEPNMM             USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask   */
19242 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos         (6U)
19243 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
19244 #define USB_OTG_DOEPEACHMSK1_INEPNEM             USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask            */
19245 #define USB_OTG_DOEPEACHMSK1_TXFURM_Pos          (8U)
19246 #define USB_OTG_DOEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
19247 #define USB_OTG_DOEPEACHMSK1_TXFURM              USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask                     */
19248 #define USB_OTG_DOEPEACHMSK1_BIM_Pos             (9U)
19249 #define USB_OTG_DOEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
19250 #define USB_OTG_DOEPEACHMSK1_BIM                 USB_OTG_DOEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask                        */
19251 #define USB_OTG_DOEPEACHMSK1_BERRM_Pos           (12U)
19252 #define USB_OTG_DOEPEACHMSK1_BERRM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
19253 #define USB_OTG_DOEPEACHMSK1_BERRM               USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask               */
19254 #define USB_OTG_DOEPEACHMSK1_NAKM_Pos            (13U)
19255 #define USB_OTG_DOEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
19256 #define USB_OTG_DOEPEACHMSK1_NAKM                USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask                        */
19257 #define USB_OTG_DOEPEACHMSK1_NYETM_Pos           (14U)
19258 #define USB_OTG_DOEPEACHMSK1_NYETM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
19259 #define USB_OTG_DOEPEACHMSK1_NYETM               USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask                       */
19260 
19261 /********************  Bit definition for USB_OTG_HPTXFSIZ register  ********************/
19262 #define USB_OTG_HPTXFSIZ_PTXSA_Pos               (0U)
19263 #define USB_OTG_HPTXFSIZ_PTXSA_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
19264 #define USB_OTG_HPTXFSIZ_PTXSA                   USB_OTG_HPTXFSIZ_PTXSA_Msk    /*!< Host periodic TxFIFO start address            */
19265 #define USB_OTG_HPTXFSIZ_PTXFD_Pos               (16U)
19266 #define USB_OTG_HPTXFSIZ_PTXFD_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
19267 #define USB_OTG_HPTXFSIZ_PTXFD                   USB_OTG_HPTXFSIZ_PTXFD_Msk    /*!< Host periodic TxFIFO depth                    */
19268 
19269 /********************  Bit definition for USB_OTG_DIEPCTL register  ********************/
19270 #define USB_OTG_DIEPCTL_MPSIZ_Pos                (0U)
19271 #define USB_OTG_DIEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
19272 #define USB_OTG_DIEPCTL_MPSIZ                    USB_OTG_DIEPCTL_MPSIZ_Msk     /*!< Maximum packet size              */
19273 #define USB_OTG_DIEPCTL_USBAEP_Pos               (15U)
19274 #define USB_OTG_DIEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
19275 #define USB_OTG_DIEPCTL_USBAEP                   USB_OTG_DIEPCTL_USBAEP_Msk    /*!< USB active endpoint              */
19276 #define USB_OTG_DIEPCTL_EONUM_DPID_Pos           (16U)
19277 #define USB_OTG_DIEPCTL_EONUM_DPID_Msk           (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
19278 #define USB_OTG_DIEPCTL_EONUM_DPID               USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame                   */
19279 #define USB_OTG_DIEPCTL_NAKSTS_Pos               (17U)
19280 #define USB_OTG_DIEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
19281 #define USB_OTG_DIEPCTL_NAKSTS                   USB_OTG_DIEPCTL_NAKSTS_Msk    /*!< NAK status                       */
19282 
19283 #define USB_OTG_DIEPCTL_EPTYP_Pos                (18U)
19284 #define USB_OTG_DIEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
19285 #define USB_OTG_DIEPCTL_EPTYP                    USB_OTG_DIEPCTL_EPTYP_Msk     /*!< Endpoint type                    */
19286 #define USB_OTG_DIEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
19287 #define USB_OTG_DIEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
19288 #define USB_OTG_DIEPCTL_STALL_Pos                (21U)
19289 #define USB_OTG_DIEPCTL_STALL_Msk                (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
19290 #define USB_OTG_DIEPCTL_STALL                    USB_OTG_DIEPCTL_STALL_Msk     /*!< STALL handshake                  */
19291 
19292 #define USB_OTG_DIEPCTL_TXFNUM_Pos               (22U)
19293 #define USB_OTG_DIEPCTL_TXFNUM_Msk               (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
19294 #define USB_OTG_DIEPCTL_TXFNUM                   USB_OTG_DIEPCTL_TXFNUM_Msk    /*!< TxFIFO number                    */
19295 #define USB_OTG_DIEPCTL_TXFNUM_0                 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
19296 #define USB_OTG_DIEPCTL_TXFNUM_1                 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
19297 #define USB_OTG_DIEPCTL_TXFNUM_2                 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
19298 #define USB_OTG_DIEPCTL_TXFNUM_3                 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
19299 #define USB_OTG_DIEPCTL_CNAK_Pos                 (26U)
19300 #define USB_OTG_DIEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
19301 #define USB_OTG_DIEPCTL_CNAK                     USB_OTG_DIEPCTL_CNAK_Msk      /*!< Clear NAK                        */
19302 #define USB_OTG_DIEPCTL_SNAK_Pos                 (27U)
19303 #define USB_OTG_DIEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
19304 #define USB_OTG_DIEPCTL_SNAK                     USB_OTG_DIEPCTL_SNAK_Msk      /*!< Set NAK */
19305 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos       (28U)
19306 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
19307 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM           USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID                    */
19308 #define USB_OTG_DIEPCTL_SODDFRM_Pos              (29U)
19309 #define USB_OTG_DIEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
19310 #define USB_OTG_DIEPCTL_SODDFRM                  USB_OTG_DIEPCTL_SODDFRM_Msk   /*!< Set odd frame                    */
19311 #define USB_OTG_DIEPCTL_EPDIS_Pos                (30U)
19312 #define USB_OTG_DIEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
19313 #define USB_OTG_DIEPCTL_EPDIS                    USB_OTG_DIEPCTL_EPDIS_Msk     /*!< Endpoint disable                 */
19314 #define USB_OTG_DIEPCTL_EPENA_Pos                (31U)
19315 #define USB_OTG_DIEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
19316 #define USB_OTG_DIEPCTL_EPENA                    USB_OTG_DIEPCTL_EPENA_Msk     /*!< Endpoint enable                  */
19317 
19318 /********************  Bit definition for USB_OTG_HCCHAR register  ********************/
19319 #define USB_OTG_HCCHAR_MPSIZ_Pos                 (0U)
19320 #define USB_OTG_HCCHAR_MPSIZ_Msk                 (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
19321 #define USB_OTG_HCCHAR_MPSIZ                     USB_OTG_HCCHAR_MPSIZ_Msk      /*!< Maximum packet size */
19322 
19323 #define USB_OTG_HCCHAR_EPNUM_Pos                 (11U)
19324 #define USB_OTG_HCCHAR_EPNUM_Msk                 (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
19325 #define USB_OTG_HCCHAR_EPNUM                     USB_OTG_HCCHAR_EPNUM_Msk      /*!< Endpoint number */
19326 #define USB_OTG_HCCHAR_EPNUM_0                   (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
19327 #define USB_OTG_HCCHAR_EPNUM_1                   (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
19328 #define USB_OTG_HCCHAR_EPNUM_2                   (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
19329 #define USB_OTG_HCCHAR_EPNUM_3                   (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
19330 #define USB_OTG_HCCHAR_EPDIR_Pos                 (15U)
19331 #define USB_OTG_HCCHAR_EPDIR_Msk                 (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
19332 #define USB_OTG_HCCHAR_EPDIR                     USB_OTG_HCCHAR_EPDIR_Msk      /*!< Endpoint direction */
19333 #define USB_OTG_HCCHAR_LSDEV_Pos                 (17U)
19334 #define USB_OTG_HCCHAR_LSDEV_Msk                 (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
19335 #define USB_OTG_HCCHAR_LSDEV                     USB_OTG_HCCHAR_LSDEV_Msk      /*!< Low-speed device */
19336 
19337 #define USB_OTG_HCCHAR_EPTYP_Pos                 (18U)
19338 #define USB_OTG_HCCHAR_EPTYP_Msk                 (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
19339 #define USB_OTG_HCCHAR_EPTYP                     USB_OTG_HCCHAR_EPTYP_Msk      /*!< Endpoint type */
19340 #define USB_OTG_HCCHAR_EPTYP_0                   (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
19341 #define USB_OTG_HCCHAR_EPTYP_1                   (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
19342 
19343 #define USB_OTG_HCCHAR_MC_Pos                    (20U)
19344 #define USB_OTG_HCCHAR_MC_Msk                    (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
19345 #define USB_OTG_HCCHAR_MC                        USB_OTG_HCCHAR_MC_Msk         /*!< Multi Count (MC) / Error Count (EC) */
19346 #define USB_OTG_HCCHAR_MC_0                      (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
19347 #define USB_OTG_HCCHAR_MC_1                      (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
19348 
19349 #define USB_OTG_HCCHAR_DAD_Pos                   (22U)
19350 #define USB_OTG_HCCHAR_DAD_Msk                   (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
19351 #define USB_OTG_HCCHAR_DAD                       USB_OTG_HCCHAR_DAD_Msk        /*!< Device address */
19352 #define USB_OTG_HCCHAR_DAD_0                     (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
19353 #define USB_OTG_HCCHAR_DAD_1                     (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
19354 #define USB_OTG_HCCHAR_DAD_2                     (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
19355 #define USB_OTG_HCCHAR_DAD_3                     (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
19356 #define USB_OTG_HCCHAR_DAD_4                     (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
19357 #define USB_OTG_HCCHAR_DAD_5                     (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
19358 #define USB_OTG_HCCHAR_DAD_6                     (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
19359 #define USB_OTG_HCCHAR_ODDFRM_Pos                (29U)
19360 #define USB_OTG_HCCHAR_ODDFRM_Msk                (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
19361 #define USB_OTG_HCCHAR_ODDFRM                    USB_OTG_HCCHAR_ODDFRM_Msk     /*!< Odd frame */
19362 #define USB_OTG_HCCHAR_CHDIS_Pos                 (30U)
19363 #define USB_OTG_HCCHAR_CHDIS_Msk                 (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
19364 #define USB_OTG_HCCHAR_CHDIS                     USB_OTG_HCCHAR_CHDIS_Msk      /*!< Channel disable */
19365 #define USB_OTG_HCCHAR_CHENA_Pos                 (31U)
19366 #define USB_OTG_HCCHAR_CHENA_Msk                 (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
19367 #define USB_OTG_HCCHAR_CHENA                     USB_OTG_HCCHAR_CHENA_Msk      /*!< Channel enable */
19368 
19369 /********************  Bit definition for USB_OTG_HCSPLT register  ********************/
19370 
19371 #define USB_OTG_HCSPLT_PRTADDR_Pos               (0U)
19372 #define USB_OTG_HCSPLT_PRTADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
19373 #define USB_OTG_HCSPLT_PRTADDR                   USB_OTG_HCSPLT_PRTADDR_Msk    /*!< Port address */
19374 #define USB_OTG_HCSPLT_PRTADDR_0                 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
19375 #define USB_OTG_HCSPLT_PRTADDR_1                 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
19376 #define USB_OTG_HCSPLT_PRTADDR_2                 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
19377 #define USB_OTG_HCSPLT_PRTADDR_3                 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
19378 #define USB_OTG_HCSPLT_PRTADDR_4                 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
19379 #define USB_OTG_HCSPLT_PRTADDR_5                 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
19380 #define USB_OTG_HCSPLT_PRTADDR_6                 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
19381 
19382 #define USB_OTG_HCSPLT_HUBADDR_Pos               (7U)
19383 #define USB_OTG_HCSPLT_HUBADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
19384 #define USB_OTG_HCSPLT_HUBADDR                   USB_OTG_HCSPLT_HUBADDR_Msk    /*!< Hub address */
19385 #define USB_OTG_HCSPLT_HUBADDR_0                 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
19386 #define USB_OTG_HCSPLT_HUBADDR_1                 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
19387 #define USB_OTG_HCSPLT_HUBADDR_2                 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
19388 #define USB_OTG_HCSPLT_HUBADDR_3                 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
19389 #define USB_OTG_HCSPLT_HUBADDR_4                 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
19390 #define USB_OTG_HCSPLT_HUBADDR_5                 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
19391 #define USB_OTG_HCSPLT_HUBADDR_6                 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
19392 
19393 #define USB_OTG_HCSPLT_XACTPOS_Pos               (14U)
19394 #define USB_OTG_HCSPLT_XACTPOS_Msk               (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
19395 #define USB_OTG_HCSPLT_XACTPOS                   USB_OTG_HCSPLT_XACTPOS_Msk    /*!< XACTPOS */
19396 #define USB_OTG_HCSPLT_XACTPOS_0                 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
19397 #define USB_OTG_HCSPLT_XACTPOS_1                 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
19398 #define USB_OTG_HCSPLT_COMPLSPLT_Pos             (16U)
19399 #define USB_OTG_HCSPLT_COMPLSPLT_Msk             (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
19400 #define USB_OTG_HCSPLT_COMPLSPLT                 USB_OTG_HCSPLT_COMPLSPLT_Msk  /*!< Do complete split */
19401 #define USB_OTG_HCSPLT_SPLITEN_Pos               (31U)
19402 #define USB_OTG_HCSPLT_SPLITEN_Msk               (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
19403 #define USB_OTG_HCSPLT_SPLITEN                   USB_OTG_HCSPLT_SPLITEN_Msk    /*!< Split enable */
19404 
19405 /********************  Bit definition for USB_OTG_HCINT register  ********************/
19406 #define USB_OTG_HCINT_XFRC_Pos                   (0U)
19407 #define USB_OTG_HCINT_XFRC_Msk                   (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
19408 #define USB_OTG_HCINT_XFRC                       USB_OTG_HCINT_XFRC_Msk        /*!< Transfer completed */
19409 #define USB_OTG_HCINT_CHH_Pos                    (1U)
19410 #define USB_OTG_HCINT_CHH_Msk                    (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
19411 #define USB_OTG_HCINT_CHH                        USB_OTG_HCINT_CHH_Msk         /*!< Channel halted */
19412 #define USB_OTG_HCINT_AHBERR_Pos                 (2U)
19413 #define USB_OTG_HCINT_AHBERR_Msk                 (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
19414 #define USB_OTG_HCINT_AHBERR                     USB_OTG_HCINT_AHBERR_Msk      /*!< AHB error */
19415 #define USB_OTG_HCINT_STALL_Pos                  (3U)
19416 #define USB_OTG_HCINT_STALL_Msk                  (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
19417 #define USB_OTG_HCINT_STALL                      USB_OTG_HCINT_STALL_Msk       /*!< STALL response received interrupt */
19418 #define USB_OTG_HCINT_NAK_Pos                    (4U)
19419 #define USB_OTG_HCINT_NAK_Msk                    (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
19420 #define USB_OTG_HCINT_NAK                        USB_OTG_HCINT_NAK_Msk         /*!< NAK response received interrupt */
19421 #define USB_OTG_HCINT_ACK_Pos                    (5U)
19422 #define USB_OTG_HCINT_ACK_Msk                    (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
19423 #define USB_OTG_HCINT_ACK                        USB_OTG_HCINT_ACK_Msk         /*!< ACK response received/transmitted interrupt */
19424 #define USB_OTG_HCINT_NYET_Pos                   (6U)
19425 #define USB_OTG_HCINT_NYET_Msk                   (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
19426 #define USB_OTG_HCINT_NYET                       USB_OTG_HCINT_NYET_Msk        /*!< Response received interrupt */
19427 #define USB_OTG_HCINT_TXERR_Pos                  (7U)
19428 #define USB_OTG_HCINT_TXERR_Msk                  (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
19429 #define USB_OTG_HCINT_TXERR                      USB_OTG_HCINT_TXERR_Msk       /*!< Transaction error */
19430 #define USB_OTG_HCINT_BBERR_Pos                  (8U)
19431 #define USB_OTG_HCINT_BBERR_Msk                  (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
19432 #define USB_OTG_HCINT_BBERR                      USB_OTG_HCINT_BBERR_Msk       /*!< Babble error */
19433 #define USB_OTG_HCINT_FRMOR_Pos                  (9U)
19434 #define USB_OTG_HCINT_FRMOR_Msk                  (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
19435 #define USB_OTG_HCINT_FRMOR                      USB_OTG_HCINT_FRMOR_Msk       /*!< Frame overrun */
19436 #define USB_OTG_HCINT_DTERR_Pos                  (10U)
19437 #define USB_OTG_HCINT_DTERR_Msk                  (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
19438 #define USB_OTG_HCINT_DTERR                      USB_OTG_HCINT_DTERR_Msk       /*!< Data toggle error */
19439 
19440 /********************  Bit definition for USB_OTG_DIEPINT register  ********************/
19441 #define USB_OTG_DIEPINT_XFRC_Pos                 (0U)
19442 #define USB_OTG_DIEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
19443 #define USB_OTG_DIEPINT_XFRC                     USB_OTG_DIEPINT_XFRC_Msk      /*!< Transfer completed interrupt */
19444 #define USB_OTG_DIEPINT_EPDISD_Pos               (1U)
19445 #define USB_OTG_DIEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
19446 #define USB_OTG_DIEPINT_EPDISD                   USB_OTG_DIEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */
19447 #define USB_OTG_DIEPINT_AHBERR_Pos               (2U)
19448 #define USB_OTG_DIEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */
19449 #define USB_OTG_DIEPINT_AHBERR                   USB_OTG_DIEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an IN transaction */
19450 #define USB_OTG_DIEPINT_TOC_Pos                  (3U)
19451 #define USB_OTG_DIEPINT_TOC_Msk                  (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
19452 #define USB_OTG_DIEPINT_TOC                      USB_OTG_DIEPINT_TOC_Msk       /*!< Timeout condition */
19453 #define USB_OTG_DIEPINT_ITTXFE_Pos               (4U)
19454 #define USB_OTG_DIEPINT_ITTXFE_Msk               (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
19455 #define USB_OTG_DIEPINT_ITTXFE                   USB_OTG_DIEPINT_ITTXFE_Msk    /*!< IN token received when TxFIFO is empty */
19456 #define USB_OTG_DIEPINT_INEPNM_Pos               (5U)
19457 #define USB_OTG_DIEPINT_INEPNM_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000004 */
19458 #define USB_OTG_DIEPINT_INEPNM                   USB_OTG_DIEPINT_INEPNM_Msk   /*!< IN token received with EP mismatch */
19459 #define USB_OTG_DIEPINT_INEPNE_Pos               (6U)
19460 #define USB_OTG_DIEPINT_INEPNE_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
19461 #define USB_OTG_DIEPINT_INEPNE                   USB_OTG_DIEPINT_INEPNE_Msk    /*!< IN endpoint NAK effective */
19462 #define USB_OTG_DIEPINT_TXFE_Pos                 (7U)
19463 #define USB_OTG_DIEPINT_TXFE_Msk                 (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
19464 #define USB_OTG_DIEPINT_TXFE                     USB_OTG_DIEPINT_TXFE_Msk      /*!< Transmit FIFO empty */
19465 #define USB_OTG_DIEPINT_TXFIFOUDRN_Pos           (8U)
19466 #define USB_OTG_DIEPINT_TXFIFOUDRN_Msk           (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
19467 #define USB_OTG_DIEPINT_TXFIFOUDRN               USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
19468 #define USB_OTG_DIEPINT_BNA_Pos                  (9U)
19469 #define USB_OTG_DIEPINT_BNA_Msk                  (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
19470 #define USB_OTG_DIEPINT_BNA                      USB_OTG_DIEPINT_BNA_Msk       /*!< Buffer not available interrupt */
19471 #define USB_OTG_DIEPINT_PKTDRPSTS_Pos            (11U)
19472 #define USB_OTG_DIEPINT_PKTDRPSTS_Msk            (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
19473 #define USB_OTG_DIEPINT_PKTDRPSTS                USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
19474 #define USB_OTG_DIEPINT_BERR_Pos                 (12U)
19475 #define USB_OTG_DIEPINT_BERR_Msk                 (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
19476 #define USB_OTG_DIEPINT_BERR                     USB_OTG_DIEPINT_BERR_Msk      /*!< Babble error interrupt */
19477 #define USB_OTG_DIEPINT_NAK_Pos                  (13U)
19478 #define USB_OTG_DIEPINT_NAK_Msk                  (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
19479 #define USB_OTG_DIEPINT_NAK                      USB_OTG_DIEPINT_NAK_Msk       /*!< NAK interrupt */
19480 
19481 /********************  Bit definition forUSB_OTG_HCINTMSK register  ********************/
19482 #define USB_OTG_HCINTMSK_XFRCM_Pos               (0U)
19483 #define USB_OTG_HCINTMSK_XFRCM_Msk               (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
19484 #define USB_OTG_HCINTMSK_XFRCM                   USB_OTG_HCINTMSK_XFRCM_Msk    /*!< Transfer completed mask */
19485 #define USB_OTG_HCINTMSK_CHHM_Pos                (1U)
19486 #define USB_OTG_HCINTMSK_CHHM_Msk                (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
19487 #define USB_OTG_HCINTMSK_CHHM                    USB_OTG_HCINTMSK_CHHM_Msk     /*!< Channel halted mask */
19488 #define USB_OTG_HCINTMSK_AHBERR_Pos              (2U)
19489 #define USB_OTG_HCINTMSK_AHBERR_Msk              (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
19490 #define USB_OTG_HCINTMSK_AHBERR                  USB_OTG_HCINTMSK_AHBERR_Msk   /*!< AHB error */
19491 #define USB_OTG_HCINTMSK_STALLM_Pos              (3U)
19492 #define USB_OTG_HCINTMSK_STALLM_Msk              (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
19493 #define USB_OTG_HCINTMSK_STALLM                  USB_OTG_HCINTMSK_STALLM_Msk   /*!< STALL response received interrupt mask */
19494 #define USB_OTG_HCINTMSK_NAKM_Pos                (4U)
19495 #define USB_OTG_HCINTMSK_NAKM_Msk                (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
19496 #define USB_OTG_HCINTMSK_NAKM                    USB_OTG_HCINTMSK_NAKM_Msk     /*!< NAK response received interrupt mask */
19497 #define USB_OTG_HCINTMSK_ACKM_Pos                (5U)
19498 #define USB_OTG_HCINTMSK_ACKM_Msk                (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
19499 #define USB_OTG_HCINTMSK_ACKM                    USB_OTG_HCINTMSK_ACKM_Msk     /*!< ACK response received/transmitted interrupt mask */
19500 #define USB_OTG_HCINTMSK_NYET_Pos                (6U)
19501 #define USB_OTG_HCINTMSK_NYET_Msk                (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
19502 #define USB_OTG_HCINTMSK_NYET                    USB_OTG_HCINTMSK_NYET_Msk     /*!< response received interrupt mask */
19503 #define USB_OTG_HCINTMSK_TXERRM_Pos              (7U)
19504 #define USB_OTG_HCINTMSK_TXERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
19505 #define USB_OTG_HCINTMSK_TXERRM                  USB_OTG_HCINTMSK_TXERRM_Msk   /*!< Transaction error mask */
19506 #define USB_OTG_HCINTMSK_BBERRM_Pos              (8U)
19507 #define USB_OTG_HCINTMSK_BBERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
19508 #define USB_OTG_HCINTMSK_BBERRM                  USB_OTG_HCINTMSK_BBERRM_Msk   /*!< Babble error mask */
19509 #define USB_OTG_HCINTMSK_FRMORM_Pos              (9U)
19510 #define USB_OTG_HCINTMSK_FRMORM_Msk              (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
19511 #define USB_OTG_HCINTMSK_FRMORM                  USB_OTG_HCINTMSK_FRMORM_Msk   /*!< Frame overrun mask */
19512 #define USB_OTG_HCINTMSK_DTERRM_Pos              (10U)
19513 #define USB_OTG_HCINTMSK_DTERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
19514 #define USB_OTG_HCINTMSK_DTERRM                  USB_OTG_HCINTMSK_DTERRM_Msk   /*!< Data toggle error mask */
19515 
19516 /********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
19517 
19518 #define USB_OTG_DIEPTSIZ_XFRSIZ_Pos              (0U)
19519 #define USB_OTG_DIEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
19520 #define USB_OTG_DIEPTSIZ_XFRSIZ                  USB_OTG_DIEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */
19521 #define USB_OTG_DIEPTSIZ_PKTCNT_Pos              (19U)
19522 #define USB_OTG_DIEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
19523 #define USB_OTG_DIEPTSIZ_PKTCNT                  USB_OTG_DIEPTSIZ_PKTCNT_Msk   /*!< Packet count */
19524 #define USB_OTG_DIEPTSIZ_MULCNT_Pos              (29U)
19525 #define USB_OTG_DIEPTSIZ_MULCNT_Msk              (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
19526 #define USB_OTG_DIEPTSIZ_MULCNT                  USB_OTG_DIEPTSIZ_MULCNT_Msk   /*!< Packet count */
19527 /********************  Bit definition for USB_OTG_HCTSIZ register  ********************/
19528 #define USB_OTG_HCTSIZ_XFRSIZ_Pos                (0U)
19529 #define USB_OTG_HCTSIZ_XFRSIZ_Msk                (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
19530 #define USB_OTG_HCTSIZ_XFRSIZ                    USB_OTG_HCTSIZ_XFRSIZ_Msk     /*!< Transfer size */
19531 #define USB_OTG_HCTSIZ_PKTCNT_Pos                (19U)
19532 #define USB_OTG_HCTSIZ_PKTCNT_Msk                (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
19533 #define USB_OTG_HCTSIZ_PKTCNT                    USB_OTG_HCTSIZ_PKTCNT_Msk     /*!< Packet count */
19534 #define USB_OTG_HCTSIZ_DOPING_Pos                (31U)
19535 #define USB_OTG_HCTSIZ_DOPING_Msk                (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
19536 #define USB_OTG_HCTSIZ_DOPING                    USB_OTG_HCTSIZ_DOPING_Msk     /*!< Do PING */
19537 #define USB_OTG_HCTSIZ_DPID_Pos                  (29U)
19538 #define USB_OTG_HCTSIZ_DPID_Msk                  (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
19539 #define USB_OTG_HCTSIZ_DPID                      USB_OTG_HCTSIZ_DPID_Msk       /*!< Data PID */
19540 #define USB_OTG_HCTSIZ_DPID_0                    (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
19541 #define USB_OTG_HCTSIZ_DPID_1                    (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
19542 
19543 /********************  Bit definition for USB_OTG_DIEPDMA register  ********************/
19544 #define USB_OTG_DIEPDMA_DMAADDR_Pos              (0U)
19545 #define USB_OTG_DIEPDMA_DMAADDR_Msk              (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
19546 #define USB_OTG_DIEPDMA_DMAADDR                  USB_OTG_DIEPDMA_DMAADDR_Msk   /*!< DMA address */
19547 
19548 /********************  Bit definition for USB_OTG_HCDMA register  ********************/
19549 #define USB_OTG_HCDMA_DMAADDR_Pos                (0U)
19550 #define USB_OTG_HCDMA_DMAADDR_Msk                (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
19551 #define USB_OTG_HCDMA_DMAADDR                    USB_OTG_HCDMA_DMAADDR_Msk     /*!< DMA address */
19552 
19553 /********************  Bit definition for USB_OTG_DTXFSTS register  ********************/
19554 #define USB_OTG_DTXFSTS_INEPTFSAV_Pos            (0U)
19555 #define USB_OTG_DTXFSTS_INEPTFSAV_Msk            (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
19556 #define USB_OTG_DTXFSTS_INEPTFSAV                USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
19557 
19558 /********************  Bit definition for USB_OTG_DIEPTXF register  ********************/
19559 #define USB_OTG_DIEPTXF_INEPTXSA_Pos             (0U)
19560 #define USB_OTG_DIEPTXF_INEPTXSA_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
19561 #define USB_OTG_DIEPTXF_INEPTXSA                 USB_OTG_DIEPTXF_INEPTXSA_Msk  /*!< IN endpoint FIFOx transmit RAM start address */
19562 #define USB_OTG_DIEPTXF_INEPTXFD_Pos             (16U)
19563 #define USB_OTG_DIEPTXF_INEPTXFD_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
19564 #define USB_OTG_DIEPTXF_INEPTXFD                 USB_OTG_DIEPTXF_INEPTXFD_Msk  /*!< IN endpoint TxFIFO depth */
19565 
19566 /********************  Bit definition for USB_OTG_DOEPCTL register  ********************/
19567 
19568 #define USB_OTG_DOEPCTL_MPSIZ_Pos                (0U)
19569 #define USB_OTG_DOEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
19570 #define USB_OTG_DOEPCTL_MPSIZ                    USB_OTG_DOEPCTL_MPSIZ_Msk     /*!< Maximum packet size */          /*!<Bit 1 */
19571 #define USB_OTG_DOEPCTL_USBAEP_Pos               (15U)
19572 #define USB_OTG_DOEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
19573 #define USB_OTG_DOEPCTL_USBAEP                   USB_OTG_DOEPCTL_USBAEP_Msk    /*!< USB active endpoint */
19574 #define USB_OTG_DOEPCTL_NAKSTS_Pos               (17U)
19575 #define USB_OTG_DOEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
19576 #define USB_OTG_DOEPCTL_NAKSTS                   USB_OTG_DOEPCTL_NAKSTS_Msk    /*!< NAK status */
19577 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos       (28U)
19578 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
19579 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM           USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
19580 #define USB_OTG_DOEPCTL_SODDFRM_Pos              (29U)
19581 #define USB_OTG_DOEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
19582 #define USB_OTG_DOEPCTL_SODDFRM                  USB_OTG_DOEPCTL_SODDFRM_Msk   /*!< Set odd frame */
19583 #define USB_OTG_DOEPCTL_EPTYP_Pos                (18U)
19584 #define USB_OTG_DOEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
19585 #define USB_OTG_DOEPCTL_EPTYP                    USB_OTG_DOEPCTL_EPTYP_Msk     /*!< Endpoint type */
19586 #define USB_OTG_DOEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
19587 #define USB_OTG_DOEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
19588 #define USB_OTG_DOEPCTL_SNPM_Pos                 (20U)
19589 #define USB_OTG_DOEPCTL_SNPM_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
19590 #define USB_OTG_DOEPCTL_SNPM                     USB_OTG_DOEPCTL_SNPM_Msk      /*!< Snoop mode */
19591 #define USB_OTG_DOEPCTL_STALL_Pos                (21U)
19592 #define USB_OTG_DOEPCTL_STALL_Msk                (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
19593 #define USB_OTG_DOEPCTL_STALL                    USB_OTG_DOEPCTL_STALL_Msk     /*!< STALL handshake */
19594 #define USB_OTG_DOEPCTL_CNAK_Pos                 (26U)
19595 #define USB_OTG_DOEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
19596 #define USB_OTG_DOEPCTL_CNAK                     USB_OTG_DOEPCTL_CNAK_Msk      /*!< Clear NAK */
19597 #define USB_OTG_DOEPCTL_SNAK_Pos                 (27U)
19598 #define USB_OTG_DOEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
19599 #define USB_OTG_DOEPCTL_SNAK                     USB_OTG_DOEPCTL_SNAK_Msk      /*!< Set NAK */
19600 #define USB_OTG_DOEPCTL_EPDIS_Pos                (30U)
19601 #define USB_OTG_DOEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
19602 #define USB_OTG_DOEPCTL_EPDIS                    USB_OTG_DOEPCTL_EPDIS_Msk     /*!< Endpoint disable */
19603 #define USB_OTG_DOEPCTL_EPENA_Pos                (31U)
19604 #define USB_OTG_DOEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
19605 #define USB_OTG_DOEPCTL_EPENA                    USB_OTG_DOEPCTL_EPENA_Msk     /*!< Endpoint enable */
19606 
19607 /********************  Bit definition for USB_OTG_DOEPINT register  ********************/
19608 #define USB_OTG_DOEPINT_XFRC_Pos                 (0U)
19609 #define USB_OTG_DOEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
19610 #define USB_OTG_DOEPINT_XFRC                     USB_OTG_DOEPINT_XFRC_Msk      /*!< Transfer completed interrupt */
19611 #define USB_OTG_DOEPINT_EPDISD_Pos               (1U)
19612 #define USB_OTG_DOEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
19613 #define USB_OTG_DOEPINT_EPDISD                   USB_OTG_DOEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */
19614 #define USB_OTG_DOEPINT_AHBERR_Pos               (2U)
19615 #define USB_OTG_DOEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */
19616 #define USB_OTG_DOEPINT_AHBERR                   USB_OTG_DOEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an OUT transaction */
19617 #define USB_OTG_DOEPINT_STUP_Pos                 (3U)
19618 #define USB_OTG_DOEPINT_STUP_Msk                 (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
19619 #define USB_OTG_DOEPINT_STUP                     USB_OTG_DOEPINT_STUP_Msk      /*!< SETUP phase done */
19620 #define USB_OTG_DOEPINT_OTEPDIS_Pos              (4U)
19621 #define USB_OTG_DOEPINT_OTEPDIS_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
19622 #define USB_OTG_DOEPINT_OTEPDIS                  USB_OTG_DOEPINT_OTEPDIS_Msk   /*!< OUT token received when endpoint disabled */
19623 #define USB_OTG_DOEPINT_OTEPSPR_Pos              (5U)
19624 #define USB_OTG_DOEPINT_OTEPSPR_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */
19625 #define USB_OTG_DOEPINT_OTEPSPR                  USB_OTG_DOEPINT_OTEPSPR_Msk   /*!< Status Phase Received For Control Write */
19626 #define USB_OTG_DOEPINT_B2BSTUP_Pos              (6U)
19627 #define USB_OTG_DOEPINT_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
19628 #define USB_OTG_DOEPINT_B2BSTUP                  USB_OTG_DOEPINT_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received */
19629 #define USB_OTG_DOEPINT_OUTPKTERR_Pos            (8U)
19630 #define USB_OTG_DOEPINT_OUTPKTERR_Msk            (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */
19631 #define USB_OTG_DOEPINT_OUTPKTERR                USB_OTG_DOEPINT_OUTPKTERR_Msk   /*!< OUT packet error */
19632 #define USB_OTG_DOEPINT_NAK_Pos                  (13U)
19633 #define USB_OTG_DOEPINT_NAK_Msk                  (0x1UL << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */
19634 #define USB_OTG_DOEPINT_NAK                      USB_OTG_DOEPINT_NAK_Msk   /*!< NAK Packet is transmitted by the device */
19635 #define USB_OTG_DOEPINT_NYET_Pos                 (14U)
19636 #define USB_OTG_DOEPINT_NYET_Msk                 (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
19637 #define USB_OTG_DOEPINT_NYET                     USB_OTG_DOEPINT_NYET_Msk      /*!< NYET interrupt */
19638 #define USB_OTG_DOEPINT_STPKTRX_Pos              (15U)
19639 #define USB_OTG_DOEPINT_STPKTRX_Msk              (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */
19640 #define USB_OTG_DOEPINT_STPKTRX                  USB_OTG_DOEPINT_STPKTRX_Msk   /*!< Setup Packet Received */
19641 /********************  Bit definition for USB_OTG_DOEPTSIZ register  ********************/
19642 
19643 #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos              (0U)
19644 #define USB_OTG_DOEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
19645 #define USB_OTG_DOEPTSIZ_XFRSIZ                  USB_OTG_DOEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */
19646 #define USB_OTG_DOEPTSIZ_PKTCNT_Pos              (19U)
19647 #define USB_OTG_DOEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
19648 #define USB_OTG_DOEPTSIZ_PKTCNT                  USB_OTG_DOEPTSIZ_PKTCNT_Msk   /*!< Packet count */
19649 
19650 #define USB_OTG_DOEPTSIZ_STUPCNT_Pos             (29U)
19651 #define USB_OTG_DOEPTSIZ_STUPCNT_Msk             (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
19652 #define USB_OTG_DOEPTSIZ_STUPCNT                 USB_OTG_DOEPTSIZ_STUPCNT_Msk  /*!< SETUP packet count */
19653 #define USB_OTG_DOEPTSIZ_STUPCNT_0               (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
19654 #define USB_OTG_DOEPTSIZ_STUPCNT_1               (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
19655 
19656 /********************  Bit definition for PCGCCTL register  ********************/
19657 #define USB_OTG_PCGCCTL_STOPCLK_Pos              (0U)
19658 #define USB_OTG_PCGCCTL_STOPCLK_Msk              (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
19659 #define USB_OTG_PCGCCTL_STOPCLK                  USB_OTG_PCGCCTL_STOPCLK_Msk   /*!< SETUP packet count */
19660 #define USB_OTG_PCGCCTL_GATECLK_Pos              (1U)
19661 #define USB_OTG_PCGCCTL_GATECLK_Msk              (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
19662 #define USB_OTG_PCGCCTL_GATECLK                  USB_OTG_PCGCCTL_GATECLK_Msk   /*!<Bit 0 */
19663 #define USB_OTG_PCGCCTL_PHYSUSP_Pos              (4U)
19664 #define USB_OTG_PCGCCTL_PHYSUSP_Msk              (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
19665 #define USB_OTG_PCGCCTL_PHYSUSP                  USB_OTG_PCGCCTL_PHYSUSP_Msk   /*!<Bit 1 */
19666 
19667 /* Legacy define */
19668 /********************  Bit definition for OTG register  ********************/
19669 #define USB_OTG_CHNUM_Pos                        (0U)
19670 #define USB_OTG_CHNUM_Msk                        (0xFUL << USB_OTG_CHNUM_Pos)   /*!< 0x0000000F */
19671 #define USB_OTG_CHNUM                            USB_OTG_CHNUM_Msk             /*!< Channel number */
19672 #define USB_OTG_CHNUM_0                          (0x1UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000001 */
19673 #define USB_OTG_CHNUM_1                          (0x2UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000002 */
19674 #define USB_OTG_CHNUM_2                          (0x4UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000004 */
19675 #define USB_OTG_CHNUM_3                          (0x8UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000008 */
19676 #define USB_OTG_BCNT_Pos                         (4U)
19677 #define USB_OTG_BCNT_Msk                         (0x7FFUL << USB_OTG_BCNT_Pos)  /*!< 0x00007FF0 */
19678 #define USB_OTG_BCNT                             USB_OTG_BCNT_Msk              /*!< Byte count */
19679 
19680 #define USB_OTG_DPID_Pos                         (15U)
19681 #define USB_OTG_DPID_Msk                         (0x3UL << USB_OTG_DPID_Pos)    /*!< 0x00018000 */
19682 #define USB_OTG_DPID                             USB_OTG_DPID_Msk              /*!< Data PID */
19683 #define USB_OTG_DPID_0                           (0x1UL << USB_OTG_DPID_Pos)    /*!< 0x00008000 */
19684 #define USB_OTG_DPID_1                           (0x2UL << USB_OTG_DPID_Pos)    /*!< 0x00010000 */
19685 
19686 #define USB_OTG_PKTSTS_Pos                       (17U)
19687 #define USB_OTG_PKTSTS_Msk                       (0xFUL << USB_OTG_PKTSTS_Pos)  /*!< 0x001E0000 */
19688 #define USB_OTG_PKTSTS                           USB_OTG_PKTSTS_Msk            /*!< Packet status */
19689 #define USB_OTG_PKTSTS_0                         (0x1UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00020000 */
19690 #define USB_OTG_PKTSTS_1                         (0x2UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00040000 */
19691 #define USB_OTG_PKTSTS_2                         (0x4UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00080000 */
19692 #define USB_OTG_PKTSTS_3                         (0x8UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00100000 */
19693 
19694 #define USB_OTG_EPNUM_Pos                        (0U)
19695 #define USB_OTG_EPNUM_Msk                        (0xFUL << USB_OTG_EPNUM_Pos)   /*!< 0x0000000F */
19696 #define USB_OTG_EPNUM                            USB_OTG_EPNUM_Msk             /*!< Endpoint number */
19697 #define USB_OTG_EPNUM_0                          (0x1UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000001 */
19698 #define USB_OTG_EPNUM_1                          (0x2UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000002 */
19699 #define USB_OTG_EPNUM_2                          (0x4UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000004 */
19700 #define USB_OTG_EPNUM_3                          (0x8UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000008 */
19701 
19702 #define USB_OTG_FRMNUM_Pos                       (21U)
19703 #define USB_OTG_FRMNUM_Msk                       (0xFUL << USB_OTG_FRMNUM_Pos)  /*!< 0x01E00000 */
19704 #define USB_OTG_FRMNUM                           USB_OTG_FRMNUM_Msk            /*!< Frame number */
19705 #define USB_OTG_FRMNUM_0                         (0x1UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00200000 */
19706 #define USB_OTG_FRMNUM_1                         (0x2UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00400000 */
19707 #define USB_OTG_FRMNUM_2                         (0x4UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00800000 */
19708 #define USB_OTG_FRMNUM_3                         (0x8UL << USB_OTG_FRMNUM_Pos)  /*!< 0x01000000 */
19709 /**
19710   * @}
19711   */
19712 
19713 /**
19714   * @}
19715   */
19716 
19717 /** @addtogroup Exported_macros
19718   * @{
19719   */
19720 
19721 /******************************* ADC Instances ********************************/
19722 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
19723                                        ((INSTANCE) == ADC2) || \
19724                                        ((INSTANCE) == ADC3))
19725 
19726 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
19727 
19728 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)
19729 
19730 /******************************* CAN Instances ********************************/
19731 #define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
19732                                        ((INSTANCE) == CAN2))
19733 /******************************* CRC Instances ********************************/
19734 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
19735 
19736 /******************************* DAC Instances ********************************/
19737 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
19738 
19739 /******************************* DCMI Instances *******************************/
19740 #define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
19741 
19742 /******************************* DMA2D Instances *******************************/
19743 #define IS_DMA2D_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMA2D)
19744 
19745 /******************************** DMA Instances *******************************/
19746 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
19747                                               ((INSTANCE) == DMA1_Stream1) || \
19748                                               ((INSTANCE) == DMA1_Stream2) || \
19749                                               ((INSTANCE) == DMA1_Stream3) || \
19750                                               ((INSTANCE) == DMA1_Stream4) || \
19751                                               ((INSTANCE) == DMA1_Stream5) || \
19752                                               ((INSTANCE) == DMA1_Stream6) || \
19753                                               ((INSTANCE) == DMA1_Stream7) || \
19754                                               ((INSTANCE) == DMA2_Stream0) || \
19755                                               ((INSTANCE) == DMA2_Stream1) || \
19756                                               ((INSTANCE) == DMA2_Stream2) || \
19757                                               ((INSTANCE) == DMA2_Stream3) || \
19758                                               ((INSTANCE) == DMA2_Stream4) || \
19759                                               ((INSTANCE) == DMA2_Stream5) || \
19760                                               ((INSTANCE) == DMA2_Stream6) || \
19761                                               ((INSTANCE) == DMA2_Stream7))
19762 
19763 /******************************* GPIO Instances *******************************/
19764 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
19765                                         ((INSTANCE) == GPIOB) || \
19766                                         ((INSTANCE) == GPIOC) || \
19767                                         ((INSTANCE) == GPIOD) || \
19768                                         ((INSTANCE) == GPIOE) || \
19769                                         ((INSTANCE) == GPIOF) || \
19770                                         ((INSTANCE) == GPIOG) || \
19771                                         ((INSTANCE) == GPIOH) || \
19772                                         ((INSTANCE) == GPIOI) || \
19773                                         ((INSTANCE) == GPIOJ) || \
19774                                         ((INSTANCE) == GPIOK))
19775 
19776 /******************************** I2C Instances *******************************/
19777 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
19778                                        ((INSTANCE) == I2C2) || \
19779                                        ((INSTANCE) == I2C3))
19780 
19781 /******************************* SMBUS Instances ******************************/
19782 #define IS_SMBUS_ALL_INSTANCE         IS_I2C_ALL_INSTANCE
19783 
19784 /******************************** I2S Instances *******************************/
19785 
19786 #define IS_I2S_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == SPI2) || \
19787                                        ((INSTANCE) == SPI3))
19788 
19789 /*************************** I2S Extended Instances ***************************/
19790 #define IS_I2S_EXT_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2S2ext)|| \
19791                                            ((INSTANCE) == I2S3ext))
19792 /* Legacy Defines */
19793 #define IS_I2S_ALL_INSTANCE_EXT    IS_I2S_EXT_ALL_INSTANCE
19794 
19795 /****************************** LTDC Instances ********************************/
19796 #define IS_LTDC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == LTDC)
19797 /******************************* RNG Instances ********************************/
19798 #define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)
19799 
19800 /****************************** RTC Instances *********************************/
19801 #define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
19802 
19803 /******************************* SAI Instances ********************************/
19804 #define IS_SAI_ALL_INSTANCE(PERIPH) (((PERIPH) == SAI1_Block_A) || \
19805                                      ((PERIPH) == SAI1_Block_B))
19806 /* Legacy define */
19807 
19808 #define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
19809 
19810 /******************************** SPI Instances *******************************/
19811 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1)  || \
19812                                        ((INSTANCE) == SPI2)  || \
19813                                        ((INSTANCE) == SPI3)  || \
19814                                        ((INSTANCE) == SPI4)  || \
19815                                        ((INSTANCE) == SPI5)  || \
19816                                        ((INSTANCE) == SPI6))
19817 
19818 
19819 /****************** TIM Instances : All supported instances *******************/
19820 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)  || \
19821                                     ((INSTANCE) == TIM2) || \
19822                                     ((INSTANCE) == TIM3) || \
19823                                     ((INSTANCE) == TIM4) || \
19824                                     ((INSTANCE) == TIM5) || \
19825                                     ((INSTANCE) == TIM6) || \
19826                                     ((INSTANCE) == TIM7) || \
19827                                     ((INSTANCE) == TIM8) || \
19828                                     ((INSTANCE) == TIM9) || \
19829                                     ((INSTANCE) == TIM10)|| \
19830                                     ((INSTANCE) == TIM11)|| \
19831                                     ((INSTANCE) == TIM12)|| \
19832                                     ((INSTANCE) == TIM13)|| \
19833                                     ((INSTANCE) == TIM14))
19834 
19835 /************* TIM Instances : at least 1 capture/compare channel *************/
19836 #define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
19837                                          ((INSTANCE) == TIM2)  || \
19838                                          ((INSTANCE) == TIM3)  || \
19839                                          ((INSTANCE) == TIM4)  || \
19840                                          ((INSTANCE) == TIM5)  || \
19841                                          ((INSTANCE) == TIM8)  || \
19842                                          ((INSTANCE) == TIM9)  || \
19843                                          ((INSTANCE) == TIM10) || \
19844                                          ((INSTANCE) == TIM11) || \
19845                                          ((INSTANCE) == TIM12) || \
19846                                          ((INSTANCE) == TIM13) || \
19847                                          ((INSTANCE) == TIM14))
19848 
19849 /************ TIM Instances : at least 2 capture/compare channels *************/
19850 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
19851                                        ((INSTANCE) == TIM2) || \
19852                                        ((INSTANCE) == TIM3) || \
19853                                        ((INSTANCE) == TIM4) || \
19854                                        ((INSTANCE) == TIM5) || \
19855                                        ((INSTANCE) == TIM8) || \
19856                                        ((INSTANCE) == TIM9) || \
19857                                        ((INSTANCE) == TIM12))
19858 
19859 /************ TIM Instances : at least 3 capture/compare channels *************/
19860 #define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \
19861                                          ((INSTANCE) == TIM2) || \
19862                                          ((INSTANCE) == TIM3) || \
19863                                          ((INSTANCE) == TIM4) || \
19864                                          ((INSTANCE) == TIM5) || \
19865                                          ((INSTANCE) == TIM8))
19866 
19867 /************ TIM Instances : at least 4 capture/compare channels *************/
19868 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
19869                                        ((INSTANCE) == TIM2) || \
19870                                        ((INSTANCE) == TIM3) || \
19871                                        ((INSTANCE) == TIM4) || \
19872                                        ((INSTANCE) == TIM5) || \
19873                                        ((INSTANCE) == TIM8))
19874 
19875 /******************** TIM Instances : Advanced-control timers *****************/
19876 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
19877                                            ((INSTANCE) == TIM8))
19878 
19879 /******************* TIM Instances : Timer input XOR function *****************/
19880 #define IS_TIM_XOR_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \
19881                                          ((INSTANCE) == TIM2) || \
19882                                          ((INSTANCE) == TIM3) || \
19883                                          ((INSTANCE) == TIM4) || \
19884                                          ((INSTANCE) == TIM5) || \
19885                                          ((INSTANCE) == TIM8))
19886 
19887 /****************** TIM Instances : DMA requests generation (UDE) *************/
19888 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
19889                                        ((INSTANCE) == TIM2) || \
19890                                        ((INSTANCE) == TIM3) || \
19891                                        ((INSTANCE) == TIM4) || \
19892                                        ((INSTANCE) == TIM5) || \
19893                                        ((INSTANCE) == TIM6) || \
19894                                        ((INSTANCE) == TIM7) || \
19895                                        ((INSTANCE) == TIM8))
19896 
19897 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
19898 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
19899                                           ((INSTANCE) == TIM2) || \
19900                                           ((INSTANCE) == TIM3) || \
19901                                           ((INSTANCE) == TIM4) || \
19902                                           ((INSTANCE) == TIM5) || \
19903                                           ((INSTANCE) == TIM8))
19904 
19905 /************ TIM Instances : DMA requests generation (COMDE) *****************/
19906 #define IS_TIM_CCDMA_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
19907                                           ((INSTANCE) == TIM2) || \
19908                                           ((INSTANCE) == TIM3) || \
19909                                           ((INSTANCE) == TIM4) || \
19910                                           ((INSTANCE) == TIM5) || \
19911                                           ((INSTANCE) == TIM8))
19912 
19913 /******************** TIM Instances : DMA burst feature ***********************/
19914 #define IS_TIM_DMABURST_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
19915                                              ((INSTANCE) == TIM2) || \
19916                                              ((INSTANCE) == TIM3) || \
19917                                              ((INSTANCE) == TIM4) || \
19918                                              ((INSTANCE) == TIM5) || \
19919                                              ((INSTANCE) == TIM8))
19920 
19921 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
19922 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)  || \
19923                                           ((INSTANCE) == TIM2)  || \
19924                                           ((INSTANCE) == TIM3)  || \
19925                                           ((INSTANCE) == TIM4)  || \
19926                                           ((INSTANCE) == TIM5)  || \
19927                                           ((INSTANCE) == TIM6)  || \
19928                                           ((INSTANCE) == TIM7)  || \
19929                                           ((INSTANCE) == TIM8))
19930 
19931 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
19932 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
19933                                          ((INSTANCE) == TIM2) || \
19934                                          ((INSTANCE) == TIM3) || \
19935                                          ((INSTANCE) == TIM4) || \
19936                                          ((INSTANCE) == TIM5) || \
19937                                          ((INSTANCE) == TIM8) || \
19938                                          ((INSTANCE) == TIM9) || \
19939                                          ((INSTANCE) == TIM12))
19940 /********************** TIM Instances : 32 bit Counter ************************/
19941 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
19942                                               ((INSTANCE) == TIM5))
19943 
19944 /***************** TIM Instances : external trigger input availabe ************/
19945 #define IS_TIM_ETR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
19946                                         ((INSTANCE) == TIM2) || \
19947                                         ((INSTANCE) == TIM3) || \
19948                                         ((INSTANCE) == TIM4) || \
19949                                         ((INSTANCE) == TIM5) || \
19950                                         ((INSTANCE) == TIM8))
19951 
19952 /****************** TIM Instances : remapping capability **********************/
19953 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
19954                                          ((INSTANCE) == TIM5)  || \
19955                                          ((INSTANCE) == TIM11))
19956 
19957 /******************* TIM Instances : output(s) available **********************/
19958 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
19959     ((((INSTANCE) == TIM1) &&                  \
19960      (((CHANNEL) == TIM_CHANNEL_1) ||          \
19961       ((CHANNEL) == TIM_CHANNEL_2) ||          \
19962       ((CHANNEL) == TIM_CHANNEL_3) ||          \
19963       ((CHANNEL) == TIM_CHANNEL_4)))           \
19964     ||                                         \
19965     (((INSTANCE) == TIM2) &&                   \
19966      (((CHANNEL) == TIM_CHANNEL_1) ||          \
19967       ((CHANNEL) == TIM_CHANNEL_2) ||          \
19968       ((CHANNEL) == TIM_CHANNEL_3) ||          \
19969       ((CHANNEL) == TIM_CHANNEL_4)))           \
19970     ||                                         \
19971     (((INSTANCE) == TIM3) &&                   \
19972      (((CHANNEL) == TIM_CHANNEL_1) ||          \
19973       ((CHANNEL) == TIM_CHANNEL_2) ||          \
19974       ((CHANNEL) == TIM_CHANNEL_3) ||          \
19975       ((CHANNEL) == TIM_CHANNEL_4)))           \
19976     ||                                         \
19977     (((INSTANCE) == TIM4) &&                   \
19978      (((CHANNEL) == TIM_CHANNEL_1) ||          \
19979       ((CHANNEL) == TIM_CHANNEL_2) ||          \
19980       ((CHANNEL) == TIM_CHANNEL_3) ||          \
19981       ((CHANNEL) == TIM_CHANNEL_4)))           \
19982     ||                                         \
19983     (((INSTANCE) == TIM5) &&                   \
19984      (((CHANNEL) == TIM_CHANNEL_1) ||          \
19985       ((CHANNEL) == TIM_CHANNEL_2) ||          \
19986       ((CHANNEL) == TIM_CHANNEL_3) ||          \
19987       ((CHANNEL) == TIM_CHANNEL_4)))           \
19988     ||                                         \
19989     (((INSTANCE) == TIM8) &&                   \
19990      (((CHANNEL) == TIM_CHANNEL_1) ||          \
19991       ((CHANNEL) == TIM_CHANNEL_2) ||          \
19992       ((CHANNEL) == TIM_CHANNEL_3) ||          \
19993       ((CHANNEL) == TIM_CHANNEL_4)))           \
19994     ||                                         \
19995     (((INSTANCE) == TIM9) &&                   \
19996      (((CHANNEL) == TIM_CHANNEL_1) ||          \
19997       ((CHANNEL) == TIM_CHANNEL_2)))           \
19998     ||                                         \
19999     (((INSTANCE) == TIM10) &&                  \
20000      (((CHANNEL) == TIM_CHANNEL_1)))           \
20001     ||                                         \
20002     (((INSTANCE) == TIM11) &&                  \
20003      (((CHANNEL) == TIM_CHANNEL_1)))           \
20004     ||                                         \
20005     (((INSTANCE) == TIM12) &&                  \
20006      (((CHANNEL) == TIM_CHANNEL_1) ||          \
20007       ((CHANNEL) == TIM_CHANNEL_2)))           \
20008     ||                                         \
20009     (((INSTANCE) == TIM13) &&                  \
20010      (((CHANNEL) == TIM_CHANNEL_1)))           \
20011     ||                                         \
20012     (((INSTANCE) == TIM14) &&                  \
20013      (((CHANNEL) == TIM_CHANNEL_1))))
20014 
20015 /************ TIM Instances : complementary output(s) available ***************/
20016 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
20017    ((((INSTANCE) == TIM1) &&                    \
20018      (((CHANNEL) == TIM_CHANNEL_1) ||           \
20019       ((CHANNEL) == TIM_CHANNEL_2) ||           \
20020       ((CHANNEL) == TIM_CHANNEL_3)))            \
20021     ||                                          \
20022     (((INSTANCE) == TIM8) &&                    \
20023      (((CHANNEL) == TIM_CHANNEL_1) ||           \
20024       ((CHANNEL) == TIM_CHANNEL_2) ||           \
20025       ((CHANNEL) == TIM_CHANNEL_3))))
20026 
20027 /****************** TIM Instances : supporting counting mode selection ********/
20028 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
20029                                                         ((INSTANCE) == TIM2) || \
20030                                                         ((INSTANCE) == TIM3) || \
20031                                                         ((INSTANCE) == TIM4) || \
20032                                                         ((INSTANCE) == TIM5) || \
20033                                                         ((INSTANCE) == TIM8))
20034 
20035 /****************** TIM Instances : supporting clock division *****************/
20036 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)  || \
20037                                                   ((INSTANCE) == TIM2) || \
20038                                                   ((INSTANCE) == TIM3) || \
20039                                                   ((INSTANCE) == TIM4) || \
20040                                                   ((INSTANCE) == TIM5) || \
20041                                                   ((INSTANCE) == TIM8) || \
20042                                                   ((INSTANCE) == TIM9) || \
20043                                                   ((INSTANCE) == TIM10)|| \
20044                                                   ((INSTANCE) == TIM11)|| \
20045                                                   ((INSTANCE) == TIM12)|| \
20046                                                   ((INSTANCE) == TIM13)|| \
20047                                                   ((INSTANCE) == TIM14))
20048 
20049 /****************** TIM Instances : supporting commutation event generation ***/
20050 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)|| \
20051                                                      ((INSTANCE) == TIM8))
20052 
20053 
20054 /****************** TIM Instances : supporting OCxREF clear *******************/
20055 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)        (((INSTANCE) == TIM1) || \
20056                                                        ((INSTANCE) == TIM2) || \
20057                                                        ((INSTANCE) == TIM3) || \
20058                                                        ((INSTANCE) == TIM4) || \
20059                                                        ((INSTANCE) == TIM5) || \
20060                                                        ((INSTANCE) == TIM8))
20061 
20062 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
20063 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20064                                                         ((INSTANCE) == TIM2) || \
20065                                                         ((INSTANCE) == TIM3) || \
20066                                                         ((INSTANCE) == TIM4) || \
20067                                                         ((INSTANCE) == TIM5) || \
20068                                                         ((INSTANCE) == TIM8) || \
20069                                                         ((INSTANCE) == TIM9) || \
20070                                                         ((INSTANCE) == TIM12))
20071 
20072 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
20073 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20074                                                         ((INSTANCE) == TIM2) || \
20075                                                         ((INSTANCE) == TIM3) || \
20076                                                         ((INSTANCE) == TIM4) || \
20077                                                         ((INSTANCE) == TIM5) || \
20078                                                         ((INSTANCE) == TIM8))
20079 
20080 /****** TIM Instances : supporting external clock mode 1 for TIX inputs ******/
20081 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1) || \
20082                                                         ((INSTANCE) == TIM2) || \
20083                                                         ((INSTANCE) == TIM3) || \
20084                                                         ((INSTANCE) == TIM4) || \
20085                                                         ((INSTANCE) == TIM5) || \
20086                                                         ((INSTANCE) == TIM8) || \
20087                                                         ((INSTANCE) == TIM9) || \
20088                                                         ((INSTANCE) == TIM12))
20089 
20090 /********** TIM Instances : supporting internal trigger inputs(ITRX) *********/
20091 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1) || \
20092                                                         ((INSTANCE) == TIM2) || \
20093                                                         ((INSTANCE) == TIM3) || \
20094                                                         ((INSTANCE) == TIM4) || \
20095                                                         ((INSTANCE) == TIM5) || \
20096                                                         ((INSTANCE) == TIM8) || \
20097                                                         ((INSTANCE) == TIM9) || \
20098                                                         ((INSTANCE) == TIM12))
20099 
20100 /****************** TIM Instances : supporting repetition counter *************/
20101 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
20102                                                        ((INSTANCE) == TIM8))
20103 
20104 /****************** TIM Instances : supporting encoder interface **************/
20105 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
20106                                                       ((INSTANCE) == TIM2) || \
20107                                                       ((INSTANCE) == TIM3) || \
20108                                                       ((INSTANCE) == TIM4) || \
20109                                                       ((INSTANCE) == TIM5) || \
20110                                                       ((INSTANCE) == TIM8) || \
20111                                                       ((INSTANCE) == TIM9) || \
20112                                                       ((INSTANCE) == TIM12))
20113 /****************** TIM Instances : supporting Hall sensor interface **********/
20114 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
20115                                                           ((INSTANCE) == TIM2) || \
20116                                                           ((INSTANCE) == TIM3) || \
20117                                                           ((INSTANCE) == TIM4) || \
20118                                                           ((INSTANCE) == TIM5) || \
20119                                                           ((INSTANCE) == TIM8))
20120 /****************** TIM Instances : supporting the break function *************/
20121 #define IS_TIM_BREAK_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
20122                                           ((INSTANCE) == TIM8))
20123 
20124 /******************** USART Instances : Synchronous mode **********************/
20125 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
20126                                      ((INSTANCE) == USART2) || \
20127                                      ((INSTANCE) == USART3) || \
20128                                      ((INSTANCE) == USART6))
20129 
20130 /******************** UART Instances : Half-Duplex mode **********************/
20131 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
20132                                                ((INSTANCE) == USART2) || \
20133                                                ((INSTANCE) == USART3) || \
20134                                                ((INSTANCE) == UART4)  || \
20135                                                ((INSTANCE) == UART5)  || \
20136                                                ((INSTANCE) == USART6) || \
20137                                                ((INSTANCE) == UART7)  || \
20138                                                ((INSTANCE) == UART8))
20139 
20140 /* Legacy defines */
20141 #define IS_UART_INSTANCE          IS_UART_HALFDUPLEX_INSTANCE
20142 
20143 /****************** UART Instances : Hardware Flow control ********************/
20144 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
20145                                            ((INSTANCE) == USART2) || \
20146                                            ((INSTANCE) == USART3) || \
20147                                            ((INSTANCE) == USART6))
20148 /******************** UART Instances : LIN mode **********************/
20149 #define IS_UART_LIN_INSTANCE          IS_UART_HALFDUPLEX_INSTANCE
20150 
20151 /********************* UART Instances : Smart card mode ***********************/
20152 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
20153                                          ((INSTANCE) == USART2) || \
20154                                          ((INSTANCE) == USART3) || \
20155                                          ((INSTANCE) == USART6))
20156 
20157 /*********************** UART Instances : IRDA mode ***************************/
20158 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
20159                                     ((INSTANCE) == USART2) || \
20160                                     ((INSTANCE) == USART3) || \
20161                                     ((INSTANCE) == UART4)  || \
20162                                     ((INSTANCE) == UART5)  || \
20163                                     ((INSTANCE) == USART6) || \
20164                                     ((INSTANCE) == UART7)  || \
20165                                     ((INSTANCE) == UART8))
20166 
20167 /*********************** PCD Instances ****************************************/
20168 #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
20169                                        ((INSTANCE) == USB_OTG_HS))
20170 
20171 /*********************** HCD Instances ****************************************/
20172 #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
20173                                        ((INSTANCE) == USB_OTG_HS))
20174 
20175 /****************************** SDIO Instances ********************************/
20176 #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
20177 
20178 /****************************** IWDG Instances ********************************/
20179 #define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
20180 
20181 /****************************** WWDG Instances ********************************/
20182 #define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
20183 
20184 
20185 /****************************** QSPI Instances ********************************/
20186 #define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
20187 /****************************** USB Exported Constants ************************/
20188 #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR                12U
20189 #define USB_OTG_FS_MAX_IN_ENDPOINTS                    6U    /* Including EP0 */
20190 #define USB_OTG_FS_MAX_OUT_ENDPOINTS                   6U    /* Including EP0 */
20191 #define USB_OTG_FS_TOTAL_FIFO_SIZE                     1280U /* in Bytes */
20192 #define USB_OTG_HS_HOST_MAX_CHANNEL_NBR                16U
20193 #define USB_OTG_HS_MAX_IN_ENDPOINTS                    9U    /* Including EP0 */
20194 #define USB_OTG_HS_MAX_OUT_ENDPOINTS                   9U    /* Including EP0 */
20195 #define USB_OTG_HS_TOTAL_FIFO_SIZE                     4096U /* in Bytes */
20196 
20197 /*
20198  * @brief Specific devices reset values definitions
20199  */
20200 #define RCC_PLLCFGR_RST_VALUE              0x24003010U
20201 #define RCC_PLLI2SCFGR_RST_VALUE           0x24003000U
20202 #define RCC_PLLSAICFGR_RST_VALUE           0x24003000U
20203 
20204 #define RCC_MAX_FREQUENCY           180000000U         /*!< Max frequency of family in Hz*/
20205 #define RCC_MAX_FREQUENCY_SCALE1    RCC_MAX_FREQUENCY  /*!< Maximum frequency for system clock at power scale1, in Hz */
20206 #define RCC_MAX_FREQUENCY_SCALE2    168000000U         /*!< Maximum frequency for system clock at power scale2, in Hz */
20207 #define RCC_MAX_FREQUENCY_SCALE3    120000000U         /*!< Maximum frequency for system clock at power scale3, in Hz */
20208 #define RCC_PLLVCO_OUTPUT_MIN       192000000U       /*!< Frequency min for PLLVCO output, in Hz */
20209 #define RCC_PLLVCO_INPUT_MIN           950000U       /*!< Frequency min for PLLVCO input, in Hz  */
20210 #define RCC_PLLVCO_INPUT_MAX          2100000U       /*!< Frequency max for PLLVCO input, in Hz  */
20211 #define RCC_PLLVCO_OUTPUT_MAX       432000000U       /*!< Frequency max for PLLVCO output, in Hz */
20212 
20213 #define RCC_PLLN_MIN_VALUE                 50U
20214 #define RCC_PLLN_MAX_VALUE                432U
20215 
20216 #define FLASH_SCALE1_LATENCY1_FREQ   30000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 1  */
20217 #define FLASH_SCALE1_LATENCY2_FREQ   60000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 1  */
20218 #define FLASH_SCALE1_LATENCY3_FREQ   90000000U      /*!< HCLK frequency to set FLASH latency 3 in power scale 1  */
20219 #define FLASH_SCALE1_LATENCY4_FREQ   120000000U     /*!< HCLK frequency to set FLASH latency 4 in power scale 1  */
20220 #define FLASH_SCALE1_LATENCY5_FREQ   150000000U     /*!< HCLK frequency to set FLASH latency 5 in power scale 1  */
20221 
20222 #define FLASH_SCALE2_LATENCY1_FREQ   30000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 2  */
20223 #define FLASH_SCALE2_LATENCY2_FREQ   60000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 2  */
20224 #define FLASH_SCALE2_LATENCY3_FREQ   90000000U      /*!< HCLK frequency to set FLASH latency 3 in power scale 2  */
20225 #define FLASH_SCALE2_LATENCY4_FREQ   12000000U      /*!< HCLK frequency to set FLASH latency 4 in power scale 2  */
20226 #define FLASH_SCALE2_LATENCY5_FREQ   150000000U     /*!< HCLK frequency to set FLASH latency 5 in power scale 2  */
20227 
20228 #define FLASH_SCALE3_LATENCY1_FREQ   30000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 3  */
20229 #define FLASH_SCALE3_LATENCY2_FREQ   60000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 3  */
20230 #define FLASH_SCALE3_LATENCY3_FREQ   90000000U      /*!< HCLK frequency to set FLASH latency 3 in power scale 3  */
20231 
20232 /******************************************************************************/
20233 /*  For a painless codes migration between the STM32F4xx device product       */
20234 /*  lines, the aliases defined below are put in place to overcome the         */
20235 /*  differences in the interrupt handlers and IRQn definitions.               */
20236 /*  No need to update developed interrupt code when moving across             */
20237 /*  product lines within the same STM32F4 Family                              */
20238 /******************************************************************************/
20239 /* Aliases for __IRQn */
20240 #define FSMC_IRQn              FMC_IRQn
20241 
20242 /* Aliases for __IRQHandler */
20243 #define FSMC_IRQHandler        FMC_IRQHandler
20244 
20245 /**
20246   * @}
20247   */
20248 
20249 /**
20250   * @}
20251   */
20252 
20253 /**
20254   * @}
20255   */
20256 
20257 #ifdef __cplusplus
20258 }
20259 #endif /* __cplusplus */
20260 
20261 #endif /* __STM32F469xx_H */
20262 
20263 
20264 
20265 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
20266