1 /**
2 ******************************************************************************
3 * @file stm32f4xx_ll_dma.h
4 * @author MCD Application Team
5 * @brief Header file of DMA LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef __STM32F4xx_LL_DMA_H
22 #define __STM32F4xx_LL_DMA_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32f4xx.h"
30
31 /** @addtogroup STM32F4xx_LL_Driver
32 * @{
33 */
34
35 #if defined (DMA1) || defined (DMA2)
36
37 /** @defgroup DMA_LL DMA
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 /** @defgroup DMA_LL_Private_Variables DMA Private Variables
44 * @{
45 */
46 /* Array used to get the DMA stream register offset versus stream index LL_DMA_STREAM_x */
47 static const uint8_t STREAM_OFFSET_TAB[] =
48 {
49 (uint8_t)(DMA1_Stream0_BASE - DMA1_BASE),
50 (uint8_t)(DMA1_Stream1_BASE - DMA1_BASE),
51 (uint8_t)(DMA1_Stream2_BASE - DMA1_BASE),
52 (uint8_t)(DMA1_Stream3_BASE - DMA1_BASE),
53 (uint8_t)(DMA1_Stream4_BASE - DMA1_BASE),
54 (uint8_t)(DMA1_Stream5_BASE - DMA1_BASE),
55 (uint8_t)(DMA1_Stream6_BASE - DMA1_BASE),
56 (uint8_t)(DMA1_Stream7_BASE - DMA1_BASE)
57 };
58
59 /**
60 * @}
61 */
62
63 /* Private constants ---------------------------------------------------------*/
64 /** @defgroup DMA_LL_Private_Constants DMA Private Constants
65 * @{
66 */
67 /**
68 * @}
69 */
70
71
72 /* Private macros ------------------------------------------------------------*/
73 /* Exported types ------------------------------------------------------------*/
74 #if defined(USE_FULL_LL_DRIVER)
75 /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
76 * @{
77 */
78 typedef struct
79 {
80 uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
81 or as Source base address in case of memory to memory transfer direction.
82
83 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
84
85 uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
86 or as Destination base address in case of memory to memory transfer direction.
87
88 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
89
90 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
91 from memory to memory or from peripheral to memory.
92 This parameter can be a value of @ref DMA_LL_EC_DIRECTION
93
94 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
95
96 uint32_t Mode; /*!< Specifies the normal or circular operation mode.
97 This parameter can be a value of @ref DMA_LL_EC_MODE
98 @note The circular buffer mode cannot be used if the memory to memory
99 data transfer direction is configured on the selected Stream
100
101 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
102
103 uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
104 is incremented or not.
105 This parameter can be a value of @ref DMA_LL_EC_PERIPH
106
107 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
108
109 uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
110 is incremented or not.
111 This parameter can be a value of @ref DMA_LL_EC_MEMORY
112
113 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
114
115 uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
116 in case of memory to memory transfer direction.
117 This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
118
119 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
120
121 uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
122 in case of memory to memory transfer direction.
123 This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
124
125 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
126
127 uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
128 The data unit is equal to the source buffer configuration set in PeripheralSize
129 or MemorySize parameters depending in the transfer direction.
130 This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
131
132 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
133
134 uint32_t Channel; /*!< Specifies the peripheral channel.
135 This parameter can be a value of @ref DMA_LL_EC_CHANNEL
136
137 This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelSelection(). */
138
139 uint32_t Priority; /*!< Specifies the channel priority level.
140 This parameter can be a value of @ref DMA_LL_EC_PRIORITY
141
142 This feature can be modified afterwards using unitary function @ref LL_DMA_SetStreamPriorityLevel(). */
143
144 uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
145 This parameter can be a value of @ref DMA_LL_FIFOMODE
146 @note The Direct mode (FIFO mode disabled) cannot be used if the
147 memory-to-memory data transfer is configured on the selected stream
148
149 This feature can be modified afterwards using unitary functions @ref LL_DMA_EnableFifoMode() or @ref LL_DMA_EnableFifoMode() . */
150
151 uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level.
152 This parameter can be a value of @ref DMA_LL_EC_FIFOTHRESHOLD
153
154 This feature can be modified afterwards using unitary function @ref LL_DMA_SetFIFOThreshold(). */
155
156 uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
157 It specifies the amount of data to be transferred in a single non interruptible
158 transaction.
159 This parameter can be a value of @ref DMA_LL_EC_MBURST
160 @note The burst mode is possible only if the address Increment mode is enabled.
161
162 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryBurstxfer(). */
163
164 uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
165 It specifies the amount of data to be transferred in a single non interruptible
166 transaction.
167 This parameter can be a value of @ref DMA_LL_EC_PBURST
168 @note The burst mode is possible only if the address Increment mode is enabled.
169
170 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphBurstxfer(). */
171
172 } LL_DMA_InitTypeDef;
173 /**
174 * @}
175 */
176 #endif /*USE_FULL_LL_DRIVER*/
177 /* Exported constants --------------------------------------------------------*/
178 /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
179 * @{
180 */
181
182 /** @defgroup DMA_LL_EC_STREAM STREAM
183 * @{
184 */
185 #define LL_DMA_STREAM_0 0x00000000U
186 #define LL_DMA_STREAM_1 0x00000001U
187 #define LL_DMA_STREAM_2 0x00000002U
188 #define LL_DMA_STREAM_3 0x00000003U
189 #define LL_DMA_STREAM_4 0x00000004U
190 #define LL_DMA_STREAM_5 0x00000005U
191 #define LL_DMA_STREAM_6 0x00000006U
192 #define LL_DMA_STREAM_7 0x00000007U
193 #define LL_DMA_STREAM_ALL 0xFFFF0000U
194 /**
195 * @}
196 */
197
198 /** @defgroup DMA_LL_EC_DIRECTION DIRECTION
199 * @{
200 */
201 #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
202 #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_SxCR_DIR_0 /*!< Memory to peripheral direction */
203 #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_SxCR_DIR_1 /*!< Memory to memory direction */
204 /**
205 * @}
206 */
207
208 /** @defgroup DMA_LL_EC_MODE MODE
209 * @{
210 */
211 #define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */
212 #define LL_DMA_MODE_CIRCULAR DMA_SxCR_CIRC /*!< Circular Mode */
213 #define LL_DMA_MODE_PFCTRL DMA_SxCR_PFCTRL /*!< Peripheral flow control mode */
214 /**
215 * @}
216 */
217
218 /** @defgroup DMA_LL_EC_DOUBLEBUFFER_MODE DOUBLEBUFFER MODE
219 * @{
220 */
221 #define LL_DMA_DOUBLEBUFFER_MODE_DISABLE 0x00000000U /*!< Disable double buffering mode */
222 #define LL_DMA_DOUBLEBUFFER_MODE_ENABLE DMA_SxCR_DBM /*!< Enable double buffering mode */
223 /**
224 * @}
225 */
226
227 /** @defgroup DMA_LL_EC_PERIPH PERIPH
228 * @{
229 */
230 #define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */
231 #define LL_DMA_PERIPH_INCREMENT DMA_SxCR_PINC /*!< Peripheral increment mode Enable */
232 /**
233 * @}
234 */
235
236 /** @defgroup DMA_LL_EC_MEMORY MEMORY
237 * @{
238 */
239 #define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */
240 #define LL_DMA_MEMORY_INCREMENT DMA_SxCR_MINC /*!< Memory increment mode Enable */
241 /**
242 * @}
243 */
244
245 /** @defgroup DMA_LL_EC_PDATAALIGN PDATAALIGN
246 * @{
247 */
248 #define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */
249 #define LL_DMA_PDATAALIGN_HALFWORD DMA_SxCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */
250 #define LL_DMA_PDATAALIGN_WORD DMA_SxCR_PSIZE_1 /*!< Peripheral data alignment : Word */
251 /**
252 * @}
253 */
254
255 /** @defgroup DMA_LL_EC_MDATAALIGN MDATAALIGN
256 * @{
257 */
258 #define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */
259 #define LL_DMA_MDATAALIGN_HALFWORD DMA_SxCR_MSIZE_0 /*!< Memory data alignment : HalfWord */
260 #define LL_DMA_MDATAALIGN_WORD DMA_SxCR_MSIZE_1 /*!< Memory data alignment : Word */
261 /**
262 * @}
263 */
264
265 /** @defgroup DMA_LL_EC_OFFSETSIZE OFFSETSIZE
266 * @{
267 */
268 #define LL_DMA_OFFSETSIZE_PSIZE 0x00000000U /*!< Peripheral increment offset size is linked to the PSIZE */
269 #define LL_DMA_OFFSETSIZE_FIXEDTO4 DMA_SxCR_PINCOS /*!< Peripheral increment offset size is fixed to 4 (32-bit alignment) */
270 /**
271 * @}
272 */
273
274 /** @defgroup DMA_LL_EC_PRIORITY PRIORITY
275 * @{
276 */
277 #define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */
278 #define LL_DMA_PRIORITY_MEDIUM DMA_SxCR_PL_0 /*!< Priority level : Medium */
279 #define LL_DMA_PRIORITY_HIGH DMA_SxCR_PL_1 /*!< Priority level : High */
280 #define LL_DMA_PRIORITY_VERYHIGH DMA_SxCR_PL /*!< Priority level : Very_High */
281 /**
282 * @}
283 */
284
285 /** @defgroup DMA_LL_EC_CHANNEL CHANNEL
286 * @{
287 */
288 #define LL_DMA_CHANNEL_0 0x00000000U /* Select Channel0 of DMA Instance */
289 #define LL_DMA_CHANNEL_1 DMA_SxCR_CHSEL_0 /* Select Channel1 of DMA Instance */
290 #define LL_DMA_CHANNEL_2 DMA_SxCR_CHSEL_1 /* Select Channel2 of DMA Instance */
291 #define LL_DMA_CHANNEL_3 (DMA_SxCR_CHSEL_0 | DMA_SxCR_CHSEL_1) /* Select Channel3 of DMA Instance */
292 #define LL_DMA_CHANNEL_4 DMA_SxCR_CHSEL_2 /* Select Channel4 of DMA Instance */
293 #define LL_DMA_CHANNEL_5 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_0) /* Select Channel5 of DMA Instance */
294 #define LL_DMA_CHANNEL_6 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1) /* Select Channel6 of DMA Instance */
295 #define LL_DMA_CHANNEL_7 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0) /* Select Channel7 of DMA Instance */
296 /**
297 * @}
298 */
299
300 /** @defgroup DMA_LL_EC_MBURST MBURST
301 * @{
302 */
303 #define LL_DMA_MBURST_SINGLE 0x00000000U /*!< Memory burst single transfer configuration */
304 #define LL_DMA_MBURST_INC4 DMA_SxCR_MBURST_0 /*!< Memory burst of 4 beats transfer configuration */
305 #define LL_DMA_MBURST_INC8 DMA_SxCR_MBURST_1 /*!< Memory burst of 8 beats transfer configuration */
306 #define LL_DMA_MBURST_INC16 (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1) /*!< Memory burst of 16 beats transfer configuration */
307 /**
308 * @}
309 */
310
311 /** @defgroup DMA_LL_EC_PBURST PBURST
312 * @{
313 */
314 #define LL_DMA_PBURST_SINGLE 0x00000000U /*!< Peripheral burst single transfer configuration */
315 #define LL_DMA_PBURST_INC4 DMA_SxCR_PBURST_0 /*!< Peripheral burst of 4 beats transfer configuration */
316 #define LL_DMA_PBURST_INC8 DMA_SxCR_PBURST_1 /*!< Peripheral burst of 8 beats transfer configuration */
317 #define LL_DMA_PBURST_INC16 (DMA_SxCR_PBURST_0 | DMA_SxCR_PBURST_1) /*!< Peripheral burst of 16 beats transfer configuration */
318 /**
319 * @}
320 */
321
322 /** @defgroup DMA_LL_FIFOMODE DMA_LL_FIFOMODE
323 * @{
324 */
325 #define LL_DMA_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable (direct mode is enabled) */
326 #define LL_DMA_FIFOMODE_ENABLE DMA_SxFCR_DMDIS /*!< FIFO mode enable */
327 /**
328 * @}
329 */
330
331 /** @defgroup DMA_LL_EC_FIFOSTATUS_0 FIFOSTATUS 0
332 * @{
333 */
334 #define LL_DMA_FIFOSTATUS_0_25 0x00000000U /*!< 0 < fifo_level < 1/4 */
335 #define LL_DMA_FIFOSTATUS_25_50 DMA_SxFCR_FS_0 /*!< 1/4 < fifo_level < 1/2 */
336 #define LL_DMA_FIFOSTATUS_50_75 DMA_SxFCR_FS_1 /*!< 1/2 < fifo_level < 3/4 */
337 #define LL_DMA_FIFOSTATUS_75_100 (DMA_SxFCR_FS_1 | DMA_SxFCR_FS_0) /*!< 3/4 < fifo_level < full */
338 #define LL_DMA_FIFOSTATUS_EMPTY DMA_SxFCR_FS_2 /*!< FIFO is empty */
339 #define LL_DMA_FIFOSTATUS_FULL (DMA_SxFCR_FS_2 | DMA_SxFCR_FS_0) /*!< FIFO is full */
340 /**
341 * @}
342 */
343
344 /** @defgroup DMA_LL_EC_FIFOTHRESHOLD FIFOTHRESHOLD
345 * @{
346 */
347 #define LL_DMA_FIFOTHRESHOLD_1_4 0x00000000U /*!< FIFO threshold 1 quart full configuration */
348 #define LL_DMA_FIFOTHRESHOLD_1_2 DMA_SxFCR_FTH_0 /*!< FIFO threshold half full configuration */
349 #define LL_DMA_FIFOTHRESHOLD_3_4 DMA_SxFCR_FTH_1 /*!< FIFO threshold 3 quarts full configuration */
350 #define LL_DMA_FIFOTHRESHOLD_FULL DMA_SxFCR_FTH /*!< FIFO threshold full configuration */
351 /**
352 * @}
353 */
354
355 /** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM
356 * @{
357 */
358 #define LL_DMA_CURRENTTARGETMEM0 0x00000000U /*!< Set CurrentTarget Memory to Memory 0 */
359 #define LL_DMA_CURRENTTARGETMEM1 DMA_SxCR_CT /*!< Set CurrentTarget Memory to Memory 1 */
360 /**
361 * @}
362 */
363
364 /**
365 * @}
366 */
367
368 /* Exported macro ------------------------------------------------------------*/
369 /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
370 * @{
371 */
372
373 /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
374 * @{
375 */
376 /**
377 * @brief Write a value in DMA register
378 * @param __INSTANCE__ DMA Instance
379 * @param __REG__ Register to be written
380 * @param __VALUE__ Value to be written in the register
381 * @retval None
382 */
383 #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
384
385 /**
386 * @brief Read a value in DMA register
387 * @param __INSTANCE__ DMA Instance
388 * @param __REG__ Register to be read
389 * @retval Register value
390 */
391 #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
392 /**
393 * @}
394 */
395
396 /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxStreamy
397 * @{
398 */
399 /**
400 * @brief Convert DMAx_Streamy into DMAx
401 * @param __STREAM_INSTANCE__ DMAx_Streamy
402 * @retval DMAx
403 */
404 #define __LL_DMA_GET_INSTANCE(__STREAM_INSTANCE__) \
405 (((uint32_t)(__STREAM_INSTANCE__) > ((uint32_t)DMA1_Stream7)) ? DMA2 : DMA1)
406
407 /**
408 * @brief Convert DMAx_Streamy into LL_DMA_STREAM_y
409 * @param __STREAM_INSTANCE__ DMAx_Streamy
410 * @retval LL_DMA_CHANNEL_y
411 */
412 #define __LL_DMA_GET_STREAM(__STREAM_INSTANCE__) \
413 (((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream0)) ? LL_DMA_STREAM_0 : \
414 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream0)) ? LL_DMA_STREAM_0 : \
415 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream1)) ? LL_DMA_STREAM_1 : \
416 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream1)) ? LL_DMA_STREAM_1 : \
417 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream2)) ? LL_DMA_STREAM_2 : \
418 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream2)) ? LL_DMA_STREAM_2 : \
419 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream3)) ? LL_DMA_STREAM_3 : \
420 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream3)) ? LL_DMA_STREAM_3 : \
421 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream4)) ? LL_DMA_STREAM_4 : \
422 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream4)) ? LL_DMA_STREAM_4 : \
423 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream5)) ? LL_DMA_STREAM_5 : \
424 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream5)) ? LL_DMA_STREAM_5 : \
425 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream6)) ? LL_DMA_STREAM_6 : \
426 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream6)) ? LL_DMA_STREAM_6 : \
427 LL_DMA_STREAM_7)
428
429 /**
430 * @brief Convert DMA Instance DMAx and LL_DMA_STREAM_y into DMAx_Streamy
431 * @param __DMA_INSTANCE__ DMAx
432 * @param __STREAM__ LL_DMA_STREAM_y
433 * @retval DMAx_Streamy
434 */
435 #define __LL_DMA_GET_STREAM_INSTANCE(__DMA_INSTANCE__, __STREAM__) \
436 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA1_Stream0 : \
437 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA2_Stream0 : \
438 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA1_Stream1 : \
439 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA2_Stream1 : \
440 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA1_Stream2 : \
441 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA2_Stream2 : \
442 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA1_Stream3 : \
443 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA2_Stream3 : \
444 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA1_Stream4 : \
445 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA2_Stream4 : \
446 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA1_Stream5 : \
447 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA2_Stream5 : \
448 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA1_Stream6 : \
449 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA2_Stream6 : \
450 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_7))) ? DMA1_Stream7 : \
451 DMA2_Stream7)
452
453 /**
454 * @}
455 */
456
457 /**
458 * @}
459 */
460
461
462 /* Exported functions --------------------------------------------------------*/
463 /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
464 * @{
465 */
466
467 /** @defgroup DMA_LL_EF_Configuration Configuration
468 * @{
469 */
470 /**
471 * @brief Enable DMA stream.
472 * @rmtoll CR EN LL_DMA_EnableStream
473 * @param DMAx DMAx Instance
474 * @param Stream This parameter can be one of the following values:
475 * @arg @ref LL_DMA_STREAM_0
476 * @arg @ref LL_DMA_STREAM_1
477 * @arg @ref LL_DMA_STREAM_2
478 * @arg @ref LL_DMA_STREAM_3
479 * @arg @ref LL_DMA_STREAM_4
480 * @arg @ref LL_DMA_STREAM_5
481 * @arg @ref LL_DMA_STREAM_6
482 * @arg @ref LL_DMA_STREAM_7
483 * @retval None
484 */
LL_DMA_EnableStream(DMA_TypeDef * DMAx,uint32_t Stream)485 __STATIC_INLINE void LL_DMA_EnableStream(DMA_TypeDef *DMAx, uint32_t Stream)
486 {
487 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN);
488 }
489
490 /**
491 * @brief Disable DMA stream.
492 * @rmtoll CR EN LL_DMA_DisableStream
493 * @param DMAx DMAx Instance
494 * @param Stream This parameter can be one of the following values:
495 * @arg @ref LL_DMA_STREAM_0
496 * @arg @ref LL_DMA_STREAM_1
497 * @arg @ref LL_DMA_STREAM_2
498 * @arg @ref LL_DMA_STREAM_3
499 * @arg @ref LL_DMA_STREAM_4
500 * @arg @ref LL_DMA_STREAM_5
501 * @arg @ref LL_DMA_STREAM_6
502 * @arg @ref LL_DMA_STREAM_7
503 * @retval None
504 */
LL_DMA_DisableStream(DMA_TypeDef * DMAx,uint32_t Stream)505 __STATIC_INLINE void LL_DMA_DisableStream(DMA_TypeDef *DMAx, uint32_t Stream)
506 {
507 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN);
508 }
509
510 /**
511 * @brief Check if DMA stream is enabled or disabled.
512 * @rmtoll CR EN LL_DMA_IsEnabledStream
513 * @param DMAx DMAx Instance
514 * @param Stream This parameter can be one of the following values:
515 * @arg @ref LL_DMA_STREAM_0
516 * @arg @ref LL_DMA_STREAM_1
517 * @arg @ref LL_DMA_STREAM_2
518 * @arg @ref LL_DMA_STREAM_3
519 * @arg @ref LL_DMA_STREAM_4
520 * @arg @ref LL_DMA_STREAM_5
521 * @arg @ref LL_DMA_STREAM_6
522 * @arg @ref LL_DMA_STREAM_7
523 * @retval State of bit (1 or 0).
524 */
LL_DMA_IsEnabledStream(DMA_TypeDef * DMAx,uint32_t Stream)525 __STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(DMA_TypeDef *DMAx, uint32_t Stream)
526 {
527 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN) == (DMA_SxCR_EN));
528 }
529
530 /**
531 * @brief Configure all parameters linked to DMA transfer.
532 * @rmtoll CR DIR LL_DMA_ConfigTransfer\n
533 * CR CIRC LL_DMA_ConfigTransfer\n
534 * CR PINC LL_DMA_ConfigTransfer\n
535 * CR MINC LL_DMA_ConfigTransfer\n
536 * CR PSIZE LL_DMA_ConfigTransfer\n
537 * CR MSIZE LL_DMA_ConfigTransfer\n
538 * CR PL LL_DMA_ConfigTransfer\n
539 * CR PFCTRL LL_DMA_ConfigTransfer
540 * @param DMAx DMAx Instance
541 * @param Stream This parameter can be one of the following values:
542 * @arg @ref LL_DMA_STREAM_0
543 * @arg @ref LL_DMA_STREAM_1
544 * @arg @ref LL_DMA_STREAM_2
545 * @arg @ref LL_DMA_STREAM_3
546 * @arg @ref LL_DMA_STREAM_4
547 * @arg @ref LL_DMA_STREAM_5
548 * @arg @ref LL_DMA_STREAM_6
549 * @arg @ref LL_DMA_STREAM_7
550 * @param Configuration This parameter must be a combination of all the following values:
551 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
552 * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR or @ref LL_DMA_MODE_PFCTRL
553 * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
554 * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
555 * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
556 * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
557 * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
558 *@retval None
559 */
LL_DMA_ConfigTransfer(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t Configuration)560 __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configuration)
561 {
562 MODIFY_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR,
563 DMA_SxCR_DIR | DMA_SxCR_CIRC | DMA_SxCR_PINC | DMA_SxCR_MINC | DMA_SxCR_PSIZE | DMA_SxCR_MSIZE | DMA_SxCR_PL | DMA_SxCR_PFCTRL,
564 Configuration);
565 }
566
567 /**
568 * @brief Set Data transfer direction (read from peripheral or from memory).
569 * @rmtoll CR DIR LL_DMA_SetDataTransferDirection
570 * @param DMAx DMAx Instance
571 * @param Stream This parameter can be one of the following values:
572 * @arg @ref LL_DMA_STREAM_0
573 * @arg @ref LL_DMA_STREAM_1
574 * @arg @ref LL_DMA_STREAM_2
575 * @arg @ref LL_DMA_STREAM_3
576 * @arg @ref LL_DMA_STREAM_4
577 * @arg @ref LL_DMA_STREAM_5
578 * @arg @ref LL_DMA_STREAM_6
579 * @arg @ref LL_DMA_STREAM_7
580 * @param Direction This parameter can be one of the following values:
581 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
582 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
583 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
584 * @retval None
585 */
LL_DMA_SetDataTransferDirection(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t Direction)586 __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Direction)
587 {
588 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DIR, Direction);
589 }
590
591 /**
592 * @brief Get Data transfer direction (read from peripheral or from memory).
593 * @rmtoll CR DIR LL_DMA_GetDataTransferDirection
594 * @param DMAx DMAx Instance
595 * @param Stream This parameter can be one of the following values:
596 * @arg @ref LL_DMA_STREAM_0
597 * @arg @ref LL_DMA_STREAM_1
598 * @arg @ref LL_DMA_STREAM_2
599 * @arg @ref LL_DMA_STREAM_3
600 * @arg @ref LL_DMA_STREAM_4
601 * @arg @ref LL_DMA_STREAM_5
602 * @arg @ref LL_DMA_STREAM_6
603 * @arg @ref LL_DMA_STREAM_7
604 * @retval Returned value can be one of the following values:
605 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
606 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
607 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
608 */
LL_DMA_GetDataTransferDirection(DMA_TypeDef * DMAx,uint32_t Stream)609 __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream)
610 {
611 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DIR));
612 }
613
614 /**
615 * @brief Set DMA mode normal, circular or peripheral flow control.
616 * @rmtoll CR CIRC LL_DMA_SetMode\n
617 * CR PFCTRL LL_DMA_SetMode
618 * @param DMAx DMAx Instance
619 * @param Stream This parameter can be one of the following values:
620 * @arg @ref LL_DMA_STREAM_0
621 * @arg @ref LL_DMA_STREAM_1
622 * @arg @ref LL_DMA_STREAM_2
623 * @arg @ref LL_DMA_STREAM_3
624 * @arg @ref LL_DMA_STREAM_4
625 * @arg @ref LL_DMA_STREAM_5
626 * @arg @ref LL_DMA_STREAM_6
627 * @arg @ref LL_DMA_STREAM_7
628 * @param Mode This parameter can be one of the following values:
629 * @arg @ref LL_DMA_MODE_NORMAL
630 * @arg @ref LL_DMA_MODE_CIRCULAR
631 * @arg @ref LL_DMA_MODE_PFCTRL
632 * @retval None
633 */
LL_DMA_SetMode(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t Mode)634 __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mode)
635 {
636 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL, Mode);
637 }
638
639 /**
640 * @brief Get DMA mode normal, circular or peripheral flow control.
641 * @rmtoll CR CIRC LL_DMA_GetMode\n
642 * CR PFCTRL LL_DMA_GetMode
643 * @param DMAx DMAx Instance
644 * @param Stream This parameter can be one of the following values:
645 * @arg @ref LL_DMA_STREAM_0
646 * @arg @ref LL_DMA_STREAM_1
647 * @arg @ref LL_DMA_STREAM_2
648 * @arg @ref LL_DMA_STREAM_3
649 * @arg @ref LL_DMA_STREAM_4
650 * @arg @ref LL_DMA_STREAM_5
651 * @arg @ref LL_DMA_STREAM_6
652 * @arg @ref LL_DMA_STREAM_7
653 * @retval Returned value can be one of the following values:
654 * @arg @ref LL_DMA_MODE_NORMAL
655 * @arg @ref LL_DMA_MODE_CIRCULAR
656 * @arg @ref LL_DMA_MODE_PFCTRL
657 */
LL_DMA_GetMode(DMA_TypeDef * DMAx,uint32_t Stream)658 __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Stream)
659 {
660 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL));
661 }
662
663 /**
664 * @brief Set Peripheral increment mode.
665 * @rmtoll CR PINC LL_DMA_SetPeriphIncMode
666 * @param DMAx DMAx Instance
667 * @param Stream This parameter can be one of the following values:
668 * @arg @ref LL_DMA_STREAM_0
669 * @arg @ref LL_DMA_STREAM_1
670 * @arg @ref LL_DMA_STREAM_2
671 * @arg @ref LL_DMA_STREAM_3
672 * @arg @ref LL_DMA_STREAM_4
673 * @arg @ref LL_DMA_STREAM_5
674 * @arg @ref LL_DMA_STREAM_6
675 * @arg @ref LL_DMA_STREAM_7
676 * @param IncrementMode This parameter can be one of the following values:
677 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
678 * @arg @ref LL_DMA_PERIPH_INCREMENT
679 * @retval None
680 */
LL_DMA_SetPeriphIncMode(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t IncrementMode)681 __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode)
682 {
683 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINC, IncrementMode);
684 }
685
686 /**
687 * @brief Get Peripheral increment mode.
688 * @rmtoll CR PINC LL_DMA_GetPeriphIncMode
689 * @param DMAx DMAx Instance
690 * @param Stream This parameter can be one of the following values:
691 * @arg @ref LL_DMA_STREAM_0
692 * @arg @ref LL_DMA_STREAM_1
693 * @arg @ref LL_DMA_STREAM_2
694 * @arg @ref LL_DMA_STREAM_3
695 * @arg @ref LL_DMA_STREAM_4
696 * @arg @ref LL_DMA_STREAM_5
697 * @arg @ref LL_DMA_STREAM_6
698 * @arg @ref LL_DMA_STREAM_7
699 * @retval Returned value can be one of the following values:
700 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
701 * @arg @ref LL_DMA_PERIPH_INCREMENT
702 */
LL_DMA_GetPeriphIncMode(DMA_TypeDef * DMAx,uint32_t Stream)703 __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream)
704 {
705 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINC));
706 }
707
708 /**
709 * @brief Set Memory increment mode.
710 * @rmtoll CR MINC LL_DMA_SetMemoryIncMode
711 * @param DMAx DMAx Instance
712 * @param Stream This parameter can be one of the following values:
713 * @arg @ref LL_DMA_STREAM_0
714 * @arg @ref LL_DMA_STREAM_1
715 * @arg @ref LL_DMA_STREAM_2
716 * @arg @ref LL_DMA_STREAM_3
717 * @arg @ref LL_DMA_STREAM_4
718 * @arg @ref LL_DMA_STREAM_5
719 * @arg @ref LL_DMA_STREAM_6
720 * @arg @ref LL_DMA_STREAM_7
721 * @param IncrementMode This parameter can be one of the following values:
722 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
723 * @arg @ref LL_DMA_MEMORY_INCREMENT
724 * @retval None
725 */
LL_DMA_SetMemoryIncMode(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t IncrementMode)726 __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode)
727 {
728 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MINC, IncrementMode);
729 }
730
731 /**
732 * @brief Get Memory increment mode.
733 * @rmtoll CR MINC LL_DMA_GetMemoryIncMode
734 * @param DMAx DMAx Instance
735 * @param Stream This parameter can be one of the following values:
736 * @arg @ref LL_DMA_STREAM_0
737 * @arg @ref LL_DMA_STREAM_1
738 * @arg @ref LL_DMA_STREAM_2
739 * @arg @ref LL_DMA_STREAM_3
740 * @arg @ref LL_DMA_STREAM_4
741 * @arg @ref LL_DMA_STREAM_5
742 * @arg @ref LL_DMA_STREAM_6
743 * @arg @ref LL_DMA_STREAM_7
744 * @retval Returned value can be one of the following values:
745 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
746 * @arg @ref LL_DMA_MEMORY_INCREMENT
747 */
LL_DMA_GetMemoryIncMode(DMA_TypeDef * DMAx,uint32_t Stream)748 __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream)
749 {
750 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MINC));
751 }
752
753 /**
754 * @brief Set Peripheral size.
755 * @rmtoll CR PSIZE LL_DMA_SetPeriphSize
756 * @param DMAx DMAx Instance
757 * @param Stream This parameter can be one of the following values:
758 * @arg @ref LL_DMA_STREAM_0
759 * @arg @ref LL_DMA_STREAM_1
760 * @arg @ref LL_DMA_STREAM_2
761 * @arg @ref LL_DMA_STREAM_3
762 * @arg @ref LL_DMA_STREAM_4
763 * @arg @ref LL_DMA_STREAM_5
764 * @arg @ref LL_DMA_STREAM_6
765 * @arg @ref LL_DMA_STREAM_7
766 * @param Size This parameter can be one of the following values:
767 * @arg @ref LL_DMA_PDATAALIGN_BYTE
768 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
769 * @arg @ref LL_DMA_PDATAALIGN_WORD
770 * @retval None
771 */
LL_DMA_SetPeriphSize(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t Size)772 __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size)
773 {
774 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PSIZE, Size);
775 }
776
777 /**
778 * @brief Get Peripheral size.
779 * @rmtoll CR PSIZE LL_DMA_GetPeriphSize
780 * @param DMAx DMAx Instance
781 * @param Stream This parameter can be one of the following values:
782 * @arg @ref LL_DMA_STREAM_0
783 * @arg @ref LL_DMA_STREAM_1
784 * @arg @ref LL_DMA_STREAM_2
785 * @arg @ref LL_DMA_STREAM_3
786 * @arg @ref LL_DMA_STREAM_4
787 * @arg @ref LL_DMA_STREAM_5
788 * @arg @ref LL_DMA_STREAM_6
789 * @arg @ref LL_DMA_STREAM_7
790 * @retval Returned value can be one of the following values:
791 * @arg @ref LL_DMA_PDATAALIGN_BYTE
792 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
793 * @arg @ref LL_DMA_PDATAALIGN_WORD
794 */
LL_DMA_GetPeriphSize(DMA_TypeDef * DMAx,uint32_t Stream)795 __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream)
796 {
797 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PSIZE));
798 }
799
800 /**
801 * @brief Set Memory size.
802 * @rmtoll CR MSIZE LL_DMA_SetMemorySize
803 * @param DMAx DMAx Instance
804 * @param Stream This parameter can be one of the following values:
805 * @arg @ref LL_DMA_STREAM_0
806 * @arg @ref LL_DMA_STREAM_1
807 * @arg @ref LL_DMA_STREAM_2
808 * @arg @ref LL_DMA_STREAM_3
809 * @arg @ref LL_DMA_STREAM_4
810 * @arg @ref LL_DMA_STREAM_5
811 * @arg @ref LL_DMA_STREAM_6
812 * @arg @ref LL_DMA_STREAM_7
813 * @param Size This parameter can be one of the following values:
814 * @arg @ref LL_DMA_MDATAALIGN_BYTE
815 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
816 * @arg @ref LL_DMA_MDATAALIGN_WORD
817 * @retval None
818 */
LL_DMA_SetMemorySize(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t Size)819 __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size)
820 {
821 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MSIZE, Size);
822 }
823
824 /**
825 * @brief Get Memory size.
826 * @rmtoll CR MSIZE LL_DMA_GetMemorySize
827 * @param DMAx DMAx Instance
828 * @param Stream This parameter can be one of the following values:
829 * @arg @ref LL_DMA_STREAM_0
830 * @arg @ref LL_DMA_STREAM_1
831 * @arg @ref LL_DMA_STREAM_2
832 * @arg @ref LL_DMA_STREAM_3
833 * @arg @ref LL_DMA_STREAM_4
834 * @arg @ref LL_DMA_STREAM_5
835 * @arg @ref LL_DMA_STREAM_6
836 * @arg @ref LL_DMA_STREAM_7
837 * @retval Returned value can be one of the following values:
838 * @arg @ref LL_DMA_MDATAALIGN_BYTE
839 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
840 * @arg @ref LL_DMA_MDATAALIGN_WORD
841 */
LL_DMA_GetMemorySize(DMA_TypeDef * DMAx,uint32_t Stream)842 __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream)
843 {
844 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MSIZE));
845 }
846
847 /**
848 * @brief Set Peripheral increment offset size.
849 * @rmtoll CR PINCOS LL_DMA_SetIncOffsetSize
850 * @param DMAx DMAx Instance
851 * @param Stream This parameter can be one of the following values:
852 * @arg @ref LL_DMA_STREAM_0
853 * @arg @ref LL_DMA_STREAM_1
854 * @arg @ref LL_DMA_STREAM_2
855 * @arg @ref LL_DMA_STREAM_3
856 * @arg @ref LL_DMA_STREAM_4
857 * @arg @ref LL_DMA_STREAM_5
858 * @arg @ref LL_DMA_STREAM_6
859 * @arg @ref LL_DMA_STREAM_7
860 * @param OffsetSize This parameter can be one of the following values:
861 * @arg @ref LL_DMA_OFFSETSIZE_PSIZE
862 * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4
863 * @retval None
864 */
LL_DMA_SetIncOffsetSize(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t OffsetSize)865 __STATIC_INLINE void LL_DMA_SetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t OffsetSize)
866 {
867 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINCOS, OffsetSize);
868 }
869
870 /**
871 * @brief Get Peripheral increment offset size.
872 * @rmtoll CR PINCOS LL_DMA_GetIncOffsetSize
873 * @param DMAx DMAx Instance
874 * @param Stream This parameter can be one of the following values:
875 * @arg @ref LL_DMA_STREAM_0
876 * @arg @ref LL_DMA_STREAM_1
877 * @arg @ref LL_DMA_STREAM_2
878 * @arg @ref LL_DMA_STREAM_3
879 * @arg @ref LL_DMA_STREAM_4
880 * @arg @ref LL_DMA_STREAM_5
881 * @arg @ref LL_DMA_STREAM_6
882 * @arg @ref LL_DMA_STREAM_7
883 * @retval Returned value can be one of the following values:
884 * @arg @ref LL_DMA_OFFSETSIZE_PSIZE
885 * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4
886 */
LL_DMA_GetIncOffsetSize(DMA_TypeDef * DMAx,uint32_t Stream)887 __STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream)
888 {
889 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINCOS));
890 }
891
892 /**
893 * @brief Set Stream priority level.
894 * @rmtoll CR PL LL_DMA_SetStreamPriorityLevel
895 * @param DMAx DMAx Instance
896 * @param Stream This parameter can be one of the following values:
897 * @arg @ref LL_DMA_STREAM_0
898 * @arg @ref LL_DMA_STREAM_1
899 * @arg @ref LL_DMA_STREAM_2
900 * @arg @ref LL_DMA_STREAM_3
901 * @arg @ref LL_DMA_STREAM_4
902 * @arg @ref LL_DMA_STREAM_5
903 * @arg @ref LL_DMA_STREAM_6
904 * @arg @ref LL_DMA_STREAM_7
905 * @param Priority This parameter can be one of the following values:
906 * @arg @ref LL_DMA_PRIORITY_LOW
907 * @arg @ref LL_DMA_PRIORITY_MEDIUM
908 * @arg @ref LL_DMA_PRIORITY_HIGH
909 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
910 * @retval None
911 */
LL_DMA_SetStreamPriorityLevel(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t Priority)912 __STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Priority)
913 {
914 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PL, Priority);
915 }
916
917 /**
918 * @brief Get Stream priority level.
919 * @rmtoll CR PL LL_DMA_GetStreamPriorityLevel
920 * @param DMAx DMAx Instance
921 * @param Stream This parameter can be one of the following values:
922 * @arg @ref LL_DMA_STREAM_0
923 * @arg @ref LL_DMA_STREAM_1
924 * @arg @ref LL_DMA_STREAM_2
925 * @arg @ref LL_DMA_STREAM_3
926 * @arg @ref LL_DMA_STREAM_4
927 * @arg @ref LL_DMA_STREAM_5
928 * @arg @ref LL_DMA_STREAM_6
929 * @arg @ref LL_DMA_STREAM_7
930 * @retval Returned value can be one of the following values:
931 * @arg @ref LL_DMA_PRIORITY_LOW
932 * @arg @ref LL_DMA_PRIORITY_MEDIUM
933 * @arg @ref LL_DMA_PRIORITY_HIGH
934 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
935 */
LL_DMA_GetStreamPriorityLevel(DMA_TypeDef * DMAx,uint32_t Stream)936 __STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream)
937 {
938 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PL));
939 }
940
941 /**
942 * @brief Set Number of data to transfer.
943 * @rmtoll NDTR NDT LL_DMA_SetDataLength
944 * @note This action has no effect if
945 * stream is enabled.
946 * @param DMAx DMAx Instance
947 * @param Stream This parameter can be one of the following values:
948 * @arg @ref LL_DMA_STREAM_0
949 * @arg @ref LL_DMA_STREAM_1
950 * @arg @ref LL_DMA_STREAM_2
951 * @arg @ref LL_DMA_STREAM_3
952 * @arg @ref LL_DMA_STREAM_4
953 * @arg @ref LL_DMA_STREAM_5
954 * @arg @ref LL_DMA_STREAM_6
955 * @arg @ref LL_DMA_STREAM_7
956 * @param NbData Between 0 to 0xFFFFFFFF
957 * @retval None
958 */
LL_DMA_SetDataLength(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t NbData)959 __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t NbData)
960 {
961 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->NDTR, DMA_SxNDT, NbData);
962 }
963
964 /**
965 * @brief Get Number of data to transfer.
966 * @rmtoll NDTR NDT LL_DMA_GetDataLength
967 * @note Once the stream is enabled, the return value indicate the
968 * remaining bytes to be transmitted.
969 * @param DMAx DMAx Instance
970 * @param Stream This parameter can be one of the following values:
971 * @arg @ref LL_DMA_STREAM_0
972 * @arg @ref LL_DMA_STREAM_1
973 * @arg @ref LL_DMA_STREAM_2
974 * @arg @ref LL_DMA_STREAM_3
975 * @arg @ref LL_DMA_STREAM_4
976 * @arg @ref LL_DMA_STREAM_5
977 * @arg @ref LL_DMA_STREAM_6
978 * @arg @ref LL_DMA_STREAM_7
979 * @retval Between 0 to 0xFFFFFFFF
980 */
LL_DMA_GetDataLength(DMA_TypeDef * DMAx,uint32_t Stream)981 __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef* DMAx, uint32_t Stream)
982 {
983 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->NDTR, DMA_SxNDT));
984 }
985
986 /**
987 * @brief Select Channel number associated to the Stream.
988 * @rmtoll CR CHSEL LL_DMA_SetChannelSelection
989 * @param DMAx DMAx Instance
990 * @param Stream This parameter can be one of the following values:
991 * @arg @ref LL_DMA_STREAM_0
992 * @arg @ref LL_DMA_STREAM_1
993 * @arg @ref LL_DMA_STREAM_2
994 * @arg @ref LL_DMA_STREAM_3
995 * @arg @ref LL_DMA_STREAM_4
996 * @arg @ref LL_DMA_STREAM_5
997 * @arg @ref LL_DMA_STREAM_6
998 * @arg @ref LL_DMA_STREAM_7
999 * @param Channel This parameter can be one of the following values:
1000 * @arg @ref LL_DMA_CHANNEL_0
1001 * @arg @ref LL_DMA_CHANNEL_1
1002 * @arg @ref LL_DMA_CHANNEL_2
1003 * @arg @ref LL_DMA_CHANNEL_3
1004 * @arg @ref LL_DMA_CHANNEL_4
1005 * @arg @ref LL_DMA_CHANNEL_5
1006 * @arg @ref LL_DMA_CHANNEL_6
1007 * @arg @ref LL_DMA_CHANNEL_7
1008 * @retval None
1009 */
LL_DMA_SetChannelSelection(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t Channel)1010 __STATIC_INLINE void LL_DMA_SetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Channel)
1011 {
1012 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CHSEL, Channel);
1013 }
1014
1015 /**
1016 * @brief Get the Channel number associated to the Stream.
1017 * @rmtoll CR CHSEL LL_DMA_GetChannelSelection
1018 * @param DMAx DMAx Instance
1019 * @param Stream This parameter can be one of the following values:
1020 * @arg @ref LL_DMA_STREAM_0
1021 * @arg @ref LL_DMA_STREAM_1
1022 * @arg @ref LL_DMA_STREAM_2
1023 * @arg @ref LL_DMA_STREAM_3
1024 * @arg @ref LL_DMA_STREAM_4
1025 * @arg @ref LL_DMA_STREAM_5
1026 * @arg @ref LL_DMA_STREAM_6
1027 * @arg @ref LL_DMA_STREAM_7
1028 * @retval Returned value can be one of the following values:
1029 * @arg @ref LL_DMA_CHANNEL_0
1030 * @arg @ref LL_DMA_CHANNEL_1
1031 * @arg @ref LL_DMA_CHANNEL_2
1032 * @arg @ref LL_DMA_CHANNEL_3
1033 * @arg @ref LL_DMA_CHANNEL_4
1034 * @arg @ref LL_DMA_CHANNEL_5
1035 * @arg @ref LL_DMA_CHANNEL_6
1036 * @arg @ref LL_DMA_CHANNEL_7
1037 */
LL_DMA_GetChannelSelection(DMA_TypeDef * DMAx,uint32_t Stream)1038 __STATIC_INLINE uint32_t LL_DMA_GetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream)
1039 {
1040 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CHSEL));
1041 }
1042
1043 /**
1044 * @brief Set Memory burst transfer configuration.
1045 * @rmtoll CR MBURST LL_DMA_SetMemoryBurstxfer
1046 * @param DMAx DMAx Instance
1047 * @param Stream This parameter can be one of the following values:
1048 * @arg @ref LL_DMA_STREAM_0
1049 * @arg @ref LL_DMA_STREAM_1
1050 * @arg @ref LL_DMA_STREAM_2
1051 * @arg @ref LL_DMA_STREAM_3
1052 * @arg @ref LL_DMA_STREAM_4
1053 * @arg @ref LL_DMA_STREAM_5
1054 * @arg @ref LL_DMA_STREAM_6
1055 * @arg @ref LL_DMA_STREAM_7
1056 * @param Mburst This parameter can be one of the following values:
1057 * @arg @ref LL_DMA_MBURST_SINGLE
1058 * @arg @ref LL_DMA_MBURST_INC4
1059 * @arg @ref LL_DMA_MBURST_INC8
1060 * @arg @ref LL_DMA_MBURST_INC16
1061 * @retval None
1062 */
LL_DMA_SetMemoryBurstxfer(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t Mburst)1063 __STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mburst)
1064 {
1065 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MBURST, Mburst);
1066 }
1067
1068 /**
1069 * @brief Get Memory burst transfer configuration.
1070 * @rmtoll CR MBURST LL_DMA_GetMemoryBurstxfer
1071 * @param DMAx DMAx Instance
1072 * @param Stream This parameter can be one of the following values:
1073 * @arg @ref LL_DMA_STREAM_0
1074 * @arg @ref LL_DMA_STREAM_1
1075 * @arg @ref LL_DMA_STREAM_2
1076 * @arg @ref LL_DMA_STREAM_3
1077 * @arg @ref LL_DMA_STREAM_4
1078 * @arg @ref LL_DMA_STREAM_5
1079 * @arg @ref LL_DMA_STREAM_6
1080 * @arg @ref LL_DMA_STREAM_7
1081 * @retval Returned value can be one of the following values:
1082 * @arg @ref LL_DMA_MBURST_SINGLE
1083 * @arg @ref LL_DMA_MBURST_INC4
1084 * @arg @ref LL_DMA_MBURST_INC8
1085 * @arg @ref LL_DMA_MBURST_INC16
1086 */
LL_DMA_GetMemoryBurstxfer(DMA_TypeDef * DMAx,uint32_t Stream)1087 __STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream)
1088 {
1089 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MBURST));
1090 }
1091
1092 /**
1093 * @brief Set Peripheral burst transfer configuration.
1094 * @rmtoll CR PBURST LL_DMA_SetPeriphBurstxfer
1095 * @param DMAx DMAx Instance
1096 * @param Stream This parameter can be one of the following values:
1097 * @arg @ref LL_DMA_STREAM_0
1098 * @arg @ref LL_DMA_STREAM_1
1099 * @arg @ref LL_DMA_STREAM_2
1100 * @arg @ref LL_DMA_STREAM_3
1101 * @arg @ref LL_DMA_STREAM_4
1102 * @arg @ref LL_DMA_STREAM_5
1103 * @arg @ref LL_DMA_STREAM_6
1104 * @arg @ref LL_DMA_STREAM_7
1105 * @param Pburst This parameter can be one of the following values:
1106 * @arg @ref LL_DMA_PBURST_SINGLE
1107 * @arg @ref LL_DMA_PBURST_INC4
1108 * @arg @ref LL_DMA_PBURST_INC8
1109 * @arg @ref LL_DMA_PBURST_INC16
1110 * @retval None
1111 */
LL_DMA_SetPeriphBurstxfer(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t Pburst)1112 __STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pburst)
1113 {
1114 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PBURST, Pburst);
1115 }
1116
1117 /**
1118 * @brief Get Peripheral burst transfer configuration.
1119 * @rmtoll CR PBURST LL_DMA_GetPeriphBurstxfer
1120 * @param DMAx DMAx Instance
1121 * @param Stream This parameter can be one of the following values:
1122 * @arg @ref LL_DMA_STREAM_0
1123 * @arg @ref LL_DMA_STREAM_1
1124 * @arg @ref LL_DMA_STREAM_2
1125 * @arg @ref LL_DMA_STREAM_3
1126 * @arg @ref LL_DMA_STREAM_4
1127 * @arg @ref LL_DMA_STREAM_5
1128 * @arg @ref LL_DMA_STREAM_6
1129 * @arg @ref LL_DMA_STREAM_7
1130 * @retval Returned value can be one of the following values:
1131 * @arg @ref LL_DMA_PBURST_SINGLE
1132 * @arg @ref LL_DMA_PBURST_INC4
1133 * @arg @ref LL_DMA_PBURST_INC8
1134 * @arg @ref LL_DMA_PBURST_INC16
1135 */
LL_DMA_GetPeriphBurstxfer(DMA_TypeDef * DMAx,uint32_t Stream)1136 __STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream)
1137 {
1138 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PBURST));
1139 }
1140
1141 /**
1142 * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
1143 * @rmtoll CR CT LL_DMA_SetCurrentTargetMem
1144 * @param DMAx DMAx Instance
1145 * @param Stream This parameter can be one of the following values:
1146 * @arg @ref LL_DMA_STREAM_0
1147 * @arg @ref LL_DMA_STREAM_1
1148 * @arg @ref LL_DMA_STREAM_2
1149 * @arg @ref LL_DMA_STREAM_3
1150 * @arg @ref LL_DMA_STREAM_4
1151 * @arg @ref LL_DMA_STREAM_5
1152 * @arg @ref LL_DMA_STREAM_6
1153 * @arg @ref LL_DMA_STREAM_7
1154 * @param CurrentMemory This parameter can be one of the following values:
1155 * @arg @ref LL_DMA_CURRENTTARGETMEM0
1156 * @arg @ref LL_DMA_CURRENTTARGETMEM1
1157 * @retval None
1158 */
LL_DMA_SetCurrentTargetMem(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t CurrentMemory)1159 __STATIC_INLINE void LL_DMA_SetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t CurrentMemory)
1160 {
1161 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CT, CurrentMemory);
1162 }
1163
1164 /**
1165 * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
1166 * @rmtoll CR CT LL_DMA_GetCurrentTargetMem
1167 * @param DMAx DMAx Instance
1168 * @param Stream This parameter can be one of the following values:
1169 * @arg @ref LL_DMA_STREAM_0
1170 * @arg @ref LL_DMA_STREAM_1
1171 * @arg @ref LL_DMA_STREAM_2
1172 * @arg @ref LL_DMA_STREAM_3
1173 * @arg @ref LL_DMA_STREAM_4
1174 * @arg @ref LL_DMA_STREAM_5
1175 * @arg @ref LL_DMA_STREAM_6
1176 * @arg @ref LL_DMA_STREAM_7
1177 * @retval Returned value can be one of the following values:
1178 * @arg @ref LL_DMA_CURRENTTARGETMEM0
1179 * @arg @ref LL_DMA_CURRENTTARGETMEM1
1180 */
LL_DMA_GetCurrentTargetMem(DMA_TypeDef * DMAx,uint32_t Stream)1181 __STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream)
1182 {
1183 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CT));
1184 }
1185
1186 /**
1187 * @brief Enable the double buffer mode.
1188 * @rmtoll CR DBM LL_DMA_EnableDoubleBufferMode
1189 * @param DMAx DMAx Instance
1190 * @param Stream This parameter can be one of the following values:
1191 * @arg @ref LL_DMA_STREAM_0
1192 * @arg @ref LL_DMA_STREAM_1
1193 * @arg @ref LL_DMA_STREAM_2
1194 * @arg @ref LL_DMA_STREAM_3
1195 * @arg @ref LL_DMA_STREAM_4
1196 * @arg @ref LL_DMA_STREAM_5
1197 * @arg @ref LL_DMA_STREAM_6
1198 * @arg @ref LL_DMA_STREAM_7
1199 * @retval None
1200 */
LL_DMA_EnableDoubleBufferMode(DMA_TypeDef * DMAx,uint32_t Stream)1201 __STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream)
1202 {
1203 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DBM);
1204 }
1205
1206 /**
1207 * @brief Disable the double buffer mode.
1208 * @rmtoll CR DBM LL_DMA_DisableDoubleBufferMode
1209 * @param DMAx DMAx Instance
1210 * @param Stream This parameter can be one of the following values:
1211 * @arg @ref LL_DMA_STREAM_0
1212 * @arg @ref LL_DMA_STREAM_1
1213 * @arg @ref LL_DMA_STREAM_2
1214 * @arg @ref LL_DMA_STREAM_3
1215 * @arg @ref LL_DMA_STREAM_4
1216 * @arg @ref LL_DMA_STREAM_5
1217 * @arg @ref LL_DMA_STREAM_6
1218 * @arg @ref LL_DMA_STREAM_7
1219 * @retval None
1220 */
LL_DMA_DisableDoubleBufferMode(DMA_TypeDef * DMAx,uint32_t Stream)1221 __STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream)
1222 {
1223 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DBM);
1224 }
1225
1226 /**
1227 * @brief Get FIFO status.
1228 * @rmtoll FCR FS LL_DMA_GetFIFOStatus
1229 * @param DMAx DMAx Instance
1230 * @param Stream This parameter can be one of the following values:
1231 * @arg @ref LL_DMA_STREAM_0
1232 * @arg @ref LL_DMA_STREAM_1
1233 * @arg @ref LL_DMA_STREAM_2
1234 * @arg @ref LL_DMA_STREAM_3
1235 * @arg @ref LL_DMA_STREAM_4
1236 * @arg @ref LL_DMA_STREAM_5
1237 * @arg @ref LL_DMA_STREAM_6
1238 * @arg @ref LL_DMA_STREAM_7
1239 * @retval Returned value can be one of the following values:
1240 * @arg @ref LL_DMA_FIFOSTATUS_0_25
1241 * @arg @ref LL_DMA_FIFOSTATUS_25_50
1242 * @arg @ref LL_DMA_FIFOSTATUS_50_75
1243 * @arg @ref LL_DMA_FIFOSTATUS_75_100
1244 * @arg @ref LL_DMA_FIFOSTATUS_EMPTY
1245 * @arg @ref LL_DMA_FIFOSTATUS_FULL
1246 */
LL_DMA_GetFIFOStatus(DMA_TypeDef * DMAx,uint32_t Stream)1247 __STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus(DMA_TypeDef *DMAx, uint32_t Stream)
1248 {
1249 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FS));
1250 }
1251
1252 /**
1253 * @brief Disable Fifo mode.
1254 * @rmtoll FCR DMDIS LL_DMA_DisableFifoMode
1255 * @param DMAx DMAx Instance
1256 * @param Stream This parameter can be one of the following values:
1257 * @arg @ref LL_DMA_STREAM_0
1258 * @arg @ref LL_DMA_STREAM_1
1259 * @arg @ref LL_DMA_STREAM_2
1260 * @arg @ref LL_DMA_STREAM_3
1261 * @arg @ref LL_DMA_STREAM_4
1262 * @arg @ref LL_DMA_STREAM_5
1263 * @arg @ref LL_DMA_STREAM_6
1264 * @arg @ref LL_DMA_STREAM_7
1265 * @retval None
1266 */
LL_DMA_DisableFifoMode(DMA_TypeDef * DMAx,uint32_t Stream)1267 __STATIC_INLINE void LL_DMA_DisableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream)
1268 {
1269 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_DMDIS);
1270 }
1271
1272 /**
1273 * @brief Enable Fifo mode.
1274 * @rmtoll FCR DMDIS LL_DMA_EnableFifoMode
1275 * @param DMAx DMAx Instance
1276 * @param Stream This parameter can be one of the following values:
1277 * @arg @ref LL_DMA_STREAM_0
1278 * @arg @ref LL_DMA_STREAM_1
1279 * @arg @ref LL_DMA_STREAM_2
1280 * @arg @ref LL_DMA_STREAM_3
1281 * @arg @ref LL_DMA_STREAM_4
1282 * @arg @ref LL_DMA_STREAM_5
1283 * @arg @ref LL_DMA_STREAM_6
1284 * @arg @ref LL_DMA_STREAM_7
1285 * @retval None
1286 */
LL_DMA_EnableFifoMode(DMA_TypeDef * DMAx,uint32_t Stream)1287 __STATIC_INLINE void LL_DMA_EnableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream)
1288 {
1289 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_DMDIS);
1290 }
1291
1292 /**
1293 * @brief Select FIFO threshold.
1294 * @rmtoll FCR FTH LL_DMA_SetFIFOThreshold
1295 * @param DMAx DMAx Instance
1296 * @param Stream This parameter can be one of the following values:
1297 * @arg @ref LL_DMA_STREAM_0
1298 * @arg @ref LL_DMA_STREAM_1
1299 * @arg @ref LL_DMA_STREAM_2
1300 * @arg @ref LL_DMA_STREAM_3
1301 * @arg @ref LL_DMA_STREAM_4
1302 * @arg @ref LL_DMA_STREAM_5
1303 * @arg @ref LL_DMA_STREAM_6
1304 * @arg @ref LL_DMA_STREAM_7
1305 * @param Threshold This parameter can be one of the following values:
1306 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
1307 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
1308 * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
1309 * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
1310 * @retval None
1311 */
LL_DMA_SetFIFOThreshold(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t Threshold)1312 __STATIC_INLINE void LL_DMA_SetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Threshold)
1313 {
1314 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH, Threshold);
1315 }
1316
1317 /**
1318 * @brief Get FIFO threshold.
1319 * @rmtoll FCR FTH LL_DMA_GetFIFOThreshold
1320 * @param DMAx DMAx Instance
1321 * @param Stream This parameter can be one of the following values:
1322 * @arg @ref LL_DMA_STREAM_0
1323 * @arg @ref LL_DMA_STREAM_1
1324 * @arg @ref LL_DMA_STREAM_2
1325 * @arg @ref LL_DMA_STREAM_3
1326 * @arg @ref LL_DMA_STREAM_4
1327 * @arg @ref LL_DMA_STREAM_5
1328 * @arg @ref LL_DMA_STREAM_6
1329 * @arg @ref LL_DMA_STREAM_7
1330 * @retval Returned value can be one of the following values:
1331 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
1332 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
1333 * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
1334 * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
1335 */
LL_DMA_GetFIFOThreshold(DMA_TypeDef * DMAx,uint32_t Stream)1336 __STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream)
1337 {
1338 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH));
1339 }
1340
1341 /**
1342 * @brief Configure the FIFO .
1343 * @rmtoll FCR FTH LL_DMA_ConfigFifo\n
1344 * FCR DMDIS LL_DMA_ConfigFifo
1345 * @param DMAx DMAx Instance
1346 * @param Stream This parameter can be one of the following values:
1347 * @arg @ref LL_DMA_STREAM_0
1348 * @arg @ref LL_DMA_STREAM_1
1349 * @arg @ref LL_DMA_STREAM_2
1350 * @arg @ref LL_DMA_STREAM_3
1351 * @arg @ref LL_DMA_STREAM_4
1352 * @arg @ref LL_DMA_STREAM_5
1353 * @arg @ref LL_DMA_STREAM_6
1354 * @arg @ref LL_DMA_STREAM_7
1355 * @param FifoMode This parameter can be one of the following values:
1356 * @arg @ref LL_DMA_FIFOMODE_ENABLE
1357 * @arg @ref LL_DMA_FIFOMODE_DISABLE
1358 * @param FifoThreshold This parameter can be one of the following values:
1359 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
1360 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
1361 * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
1362 * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
1363 * @retval None
1364 */
LL_DMA_ConfigFifo(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t FifoMode,uint32_t FifoThreshold)1365 __STATIC_INLINE void LL_DMA_ConfigFifo(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint32_t FifoThreshold)
1366 {
1367 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH|DMA_SxFCR_DMDIS, FifoMode|FifoThreshold);
1368 }
1369
1370 /**
1371 * @brief Configure the Source and Destination addresses.
1372 * @note This API must not be called when the DMA stream is enabled.
1373 * @rmtoll M0AR M0A LL_DMA_ConfigAddresses\n
1374 * PAR PA LL_DMA_ConfigAddresses
1375 * @param DMAx DMAx Instance
1376 * @param Stream This parameter can be one of the following values:
1377 * @arg @ref LL_DMA_STREAM_0
1378 * @arg @ref LL_DMA_STREAM_1
1379 * @arg @ref LL_DMA_STREAM_2
1380 * @arg @ref LL_DMA_STREAM_3
1381 * @arg @ref LL_DMA_STREAM_4
1382 * @arg @ref LL_DMA_STREAM_5
1383 * @arg @ref LL_DMA_STREAM_6
1384 * @arg @ref LL_DMA_STREAM_7
1385 * @param SrcAddress Between 0 to 0xFFFFFFFF
1386 * @param DstAddress Between 0 to 0xFFFFFFFF
1387 * @param Direction This parameter can be one of the following values:
1388 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
1389 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
1390 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
1391 * @retval None
1392 */
LL_DMA_ConfigAddresses(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t SrcAddress,uint32_t DstAddress,uint32_t Direction)1393 __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction)
1394 {
1395 /* Direction Memory to Periph */
1396 if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
1397 {
1398 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, SrcAddress);
1399 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, DstAddress);
1400 }
1401 /* Direction Periph to Memory and Memory to Memory */
1402 else
1403 {
1404 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, SrcAddress);
1405 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, DstAddress);
1406 }
1407 }
1408
1409 /**
1410 * @brief Set the Memory address.
1411 * @rmtoll M0AR M0A LL_DMA_SetMemoryAddress
1412 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1413 * @note This API must not be called when the DMA channel is enabled.
1414 * @param DMAx DMAx Instance
1415 * @param Stream This parameter can be one of the following values:
1416 * @arg @ref LL_DMA_STREAM_0
1417 * @arg @ref LL_DMA_STREAM_1
1418 * @arg @ref LL_DMA_STREAM_2
1419 * @arg @ref LL_DMA_STREAM_3
1420 * @arg @ref LL_DMA_STREAM_4
1421 * @arg @ref LL_DMA_STREAM_5
1422 * @arg @ref LL_DMA_STREAM_6
1423 * @arg @ref LL_DMA_STREAM_7
1424 * @param MemoryAddress Between 0 to 0xFFFFFFFF
1425 * @retval None
1426 */
LL_DMA_SetMemoryAddress(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t MemoryAddress)1427 __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress)
1428 {
1429 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, MemoryAddress);
1430 }
1431
1432 /**
1433 * @brief Set the Peripheral address.
1434 * @rmtoll PAR PA LL_DMA_SetPeriphAddress
1435 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1436 * @note This API must not be called when the DMA channel is enabled.
1437 * @param DMAx DMAx Instance
1438 * @param Stream This parameter can be one of the following values:
1439 * @arg @ref LL_DMA_STREAM_0
1440 * @arg @ref LL_DMA_STREAM_1
1441 * @arg @ref LL_DMA_STREAM_2
1442 * @arg @ref LL_DMA_STREAM_3
1443 * @arg @ref LL_DMA_STREAM_4
1444 * @arg @ref LL_DMA_STREAM_5
1445 * @arg @ref LL_DMA_STREAM_6
1446 * @arg @ref LL_DMA_STREAM_7
1447 * @param PeriphAddress Between 0 to 0xFFFFFFFF
1448 * @retval None
1449 */
LL_DMA_SetPeriphAddress(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t PeriphAddress)1450 __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t PeriphAddress)
1451 {
1452 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, PeriphAddress);
1453 }
1454
1455 /**
1456 * @brief Get the Memory address.
1457 * @rmtoll M0AR M0A LL_DMA_GetMemoryAddress
1458 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1459 * @param DMAx DMAx Instance
1460 * @param Stream This parameter can be one of the following values:
1461 * @arg @ref LL_DMA_STREAM_0
1462 * @arg @ref LL_DMA_STREAM_1
1463 * @arg @ref LL_DMA_STREAM_2
1464 * @arg @ref LL_DMA_STREAM_3
1465 * @arg @ref LL_DMA_STREAM_4
1466 * @arg @ref LL_DMA_STREAM_5
1467 * @arg @ref LL_DMA_STREAM_6
1468 * @arg @ref LL_DMA_STREAM_7
1469 * @retval Between 0 to 0xFFFFFFFF
1470 */
LL_DMA_GetMemoryAddress(DMA_TypeDef * DMAx,uint32_t Stream)1471 __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream)
1472 {
1473 return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR));
1474 }
1475
1476 /**
1477 * @brief Get the Peripheral address.
1478 * @rmtoll PAR PA LL_DMA_GetPeriphAddress
1479 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1480 * @param DMAx DMAx Instance
1481 * @param Stream This parameter can be one of the following values:
1482 * @arg @ref LL_DMA_STREAM_0
1483 * @arg @ref LL_DMA_STREAM_1
1484 * @arg @ref LL_DMA_STREAM_2
1485 * @arg @ref LL_DMA_STREAM_3
1486 * @arg @ref LL_DMA_STREAM_4
1487 * @arg @ref LL_DMA_STREAM_5
1488 * @arg @ref LL_DMA_STREAM_6
1489 * @arg @ref LL_DMA_STREAM_7
1490 * @retval Between 0 to 0xFFFFFFFF
1491 */
LL_DMA_GetPeriphAddress(DMA_TypeDef * DMAx,uint32_t Stream)1492 __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream)
1493 {
1494 return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR));
1495 }
1496
1497 /**
1498 * @brief Set the Memory to Memory Source address.
1499 * @rmtoll PAR PA LL_DMA_SetM2MSrcAddress
1500 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1501 * @note This API must not be called when the DMA channel is enabled.
1502 * @param DMAx DMAx Instance
1503 * @param Stream This parameter can be one of the following values:
1504 * @arg @ref LL_DMA_STREAM_0
1505 * @arg @ref LL_DMA_STREAM_1
1506 * @arg @ref LL_DMA_STREAM_2
1507 * @arg @ref LL_DMA_STREAM_3
1508 * @arg @ref LL_DMA_STREAM_4
1509 * @arg @ref LL_DMA_STREAM_5
1510 * @arg @ref LL_DMA_STREAM_6
1511 * @arg @ref LL_DMA_STREAM_7
1512 * @param MemoryAddress Between 0 to 0xFFFFFFFF
1513 * @retval None
1514 */
LL_DMA_SetM2MSrcAddress(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t MemoryAddress)1515 __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress)
1516 {
1517 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, MemoryAddress);
1518 }
1519
1520 /**
1521 * @brief Set the Memory to Memory Destination address.
1522 * @rmtoll M0AR M0A LL_DMA_SetM2MDstAddress
1523 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1524 * @note This API must not be called when the DMA channel is enabled.
1525 * @param DMAx DMAx Instance
1526 * @param Stream This parameter can be one of the following values:
1527 * @arg @ref LL_DMA_STREAM_0
1528 * @arg @ref LL_DMA_STREAM_1
1529 * @arg @ref LL_DMA_STREAM_2
1530 * @arg @ref LL_DMA_STREAM_3
1531 * @arg @ref LL_DMA_STREAM_4
1532 * @arg @ref LL_DMA_STREAM_5
1533 * @arg @ref LL_DMA_STREAM_6
1534 * @arg @ref LL_DMA_STREAM_7
1535 * @param MemoryAddress Between 0 to 0xFFFFFFFF
1536 * @retval None
1537 */
LL_DMA_SetM2MDstAddress(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t MemoryAddress)1538 __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress)
1539 {
1540 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, MemoryAddress);
1541 }
1542
1543 /**
1544 * @brief Get the Memory to Memory Source address.
1545 * @rmtoll PAR PA LL_DMA_GetM2MSrcAddress
1546 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1547 * @param DMAx DMAx Instance
1548 * @param Stream This parameter can be one of the following values:
1549 * @arg @ref LL_DMA_STREAM_0
1550 * @arg @ref LL_DMA_STREAM_1
1551 * @arg @ref LL_DMA_STREAM_2
1552 * @arg @ref LL_DMA_STREAM_3
1553 * @arg @ref LL_DMA_STREAM_4
1554 * @arg @ref LL_DMA_STREAM_5
1555 * @arg @ref LL_DMA_STREAM_6
1556 * @arg @ref LL_DMA_STREAM_7
1557 * @retval Between 0 to 0xFFFFFFFF
1558 */
LL_DMA_GetM2MSrcAddress(DMA_TypeDef * DMAx,uint32_t Stream)1559 __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream)
1560 {
1561 return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR));
1562 }
1563
1564 /**
1565 * @brief Get the Memory to Memory Destination address.
1566 * @rmtoll M0AR M0A LL_DMA_GetM2MDstAddress
1567 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1568 * @param DMAx DMAx Instance
1569 * @param Stream This parameter can be one of the following values:
1570 * @arg @ref LL_DMA_STREAM_0
1571 * @arg @ref LL_DMA_STREAM_1
1572 * @arg @ref LL_DMA_STREAM_2
1573 * @arg @ref LL_DMA_STREAM_3
1574 * @arg @ref LL_DMA_STREAM_4
1575 * @arg @ref LL_DMA_STREAM_5
1576 * @arg @ref LL_DMA_STREAM_6
1577 * @arg @ref LL_DMA_STREAM_7
1578 * @retval Between 0 to 0xFFFFFFFF
1579 */
LL_DMA_GetM2MDstAddress(DMA_TypeDef * DMAx,uint32_t Stream)1580 __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream)
1581 {
1582 return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR));
1583 }
1584
1585 /**
1586 * @brief Set Memory 1 address (used in case of Double buffer mode).
1587 * @rmtoll M1AR M1A LL_DMA_SetMemory1Address
1588 * @param DMAx DMAx Instance
1589 * @param Stream This parameter can be one of the following values:
1590 * @arg @ref LL_DMA_STREAM_0
1591 * @arg @ref LL_DMA_STREAM_1
1592 * @arg @ref LL_DMA_STREAM_2
1593 * @arg @ref LL_DMA_STREAM_3
1594 * @arg @ref LL_DMA_STREAM_4
1595 * @arg @ref LL_DMA_STREAM_5
1596 * @arg @ref LL_DMA_STREAM_6
1597 * @arg @ref LL_DMA_STREAM_7
1598 * @param Address Between 0 to 0xFFFFFFFF
1599 * @retval None
1600 */
LL_DMA_SetMemory1Address(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t Address)1601 __STATIC_INLINE void LL_DMA_SetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Address)
1602 {
1603 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR, DMA_SxM1AR_M1A, Address);
1604 }
1605
1606 /**
1607 * @brief Get Memory 1 address (used in case of Double buffer mode).
1608 * @rmtoll M1AR M1A LL_DMA_GetMemory1Address
1609 * @param DMAx DMAx Instance
1610 * @param Stream This parameter can be one of the following values:
1611 * @arg @ref LL_DMA_STREAM_0
1612 * @arg @ref LL_DMA_STREAM_1
1613 * @arg @ref LL_DMA_STREAM_2
1614 * @arg @ref LL_DMA_STREAM_3
1615 * @arg @ref LL_DMA_STREAM_4
1616 * @arg @ref LL_DMA_STREAM_5
1617 * @arg @ref LL_DMA_STREAM_6
1618 * @arg @ref LL_DMA_STREAM_7
1619 * @retval Between 0 to 0xFFFFFFFF
1620 */
LL_DMA_GetMemory1Address(DMA_TypeDef * DMAx,uint32_t Stream)1621 __STATIC_INLINE uint32_t LL_DMA_GetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream)
1622 {
1623 return (((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR);
1624 }
1625
1626 /**
1627 * @}
1628 */
1629
1630 /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
1631 * @{
1632 */
1633
1634 /**
1635 * @brief Get Stream 0 half transfer flag.
1636 * @rmtoll LISR HTIF0 LL_DMA_IsActiveFlag_HT0
1637 * @param DMAx DMAx Instance
1638 * @retval State of bit (1 or 0).
1639 */
LL_DMA_IsActiveFlag_HT0(DMA_TypeDef * DMAx)1640 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT0(DMA_TypeDef *DMAx)
1641 {
1642 return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF0)==(DMA_LISR_HTIF0));
1643 }
1644
1645 /**
1646 * @brief Get Stream 1 half transfer flag.
1647 * @rmtoll LISR HTIF1 LL_DMA_IsActiveFlag_HT1
1648 * @param DMAx DMAx Instance
1649 * @retval State of bit (1 or 0).
1650 */
LL_DMA_IsActiveFlag_HT1(DMA_TypeDef * DMAx)1651 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
1652 {
1653 return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF1)==(DMA_LISR_HTIF1));
1654 }
1655
1656 /**
1657 * @brief Get Stream 2 half transfer flag.
1658 * @rmtoll LISR HTIF2 LL_DMA_IsActiveFlag_HT2
1659 * @param DMAx DMAx Instance
1660 * @retval State of bit (1 or 0).
1661 */
LL_DMA_IsActiveFlag_HT2(DMA_TypeDef * DMAx)1662 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
1663 {
1664 return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF2)==(DMA_LISR_HTIF2));
1665 }
1666
1667 /**
1668 * @brief Get Stream 3 half transfer flag.
1669 * @rmtoll LISR HTIF3 LL_DMA_IsActiveFlag_HT3
1670 * @param DMAx DMAx Instance
1671 * @retval State of bit (1 or 0).
1672 */
LL_DMA_IsActiveFlag_HT3(DMA_TypeDef * DMAx)1673 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
1674 {
1675 return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF3)==(DMA_LISR_HTIF3));
1676 }
1677
1678 /**
1679 * @brief Get Stream 4 half transfer flag.
1680 * @rmtoll HISR HTIF4 LL_DMA_IsActiveFlag_HT4
1681 * @param DMAx DMAx Instance
1682 * @retval State of bit (1 or 0).
1683 */
LL_DMA_IsActiveFlag_HT4(DMA_TypeDef * DMAx)1684 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
1685 {
1686 return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF4)==(DMA_HISR_HTIF4));
1687 }
1688
1689 /**
1690 * @brief Get Stream 5 half transfer flag.
1691 * @rmtoll HISR HTIF0 LL_DMA_IsActiveFlag_HT5
1692 * @param DMAx DMAx Instance
1693 * @retval State of bit (1 or 0).
1694 */
LL_DMA_IsActiveFlag_HT5(DMA_TypeDef * DMAx)1695 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
1696 {
1697 return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF5)==(DMA_HISR_HTIF5));
1698 }
1699
1700 /**
1701 * @brief Get Stream 6 half transfer flag.
1702 * @rmtoll HISR HTIF6 LL_DMA_IsActiveFlag_HT6
1703 * @param DMAx DMAx Instance
1704 * @retval State of bit (1 or 0).
1705 */
LL_DMA_IsActiveFlag_HT6(DMA_TypeDef * DMAx)1706 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
1707 {
1708 return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF6)==(DMA_HISR_HTIF6));
1709 }
1710
1711 /**
1712 * @brief Get Stream 7 half transfer flag.
1713 * @rmtoll HISR HTIF7 LL_DMA_IsActiveFlag_HT7
1714 * @param DMAx DMAx Instance
1715 * @retval State of bit (1 or 0).
1716 */
LL_DMA_IsActiveFlag_HT7(DMA_TypeDef * DMAx)1717 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
1718 {
1719 return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF7)==(DMA_HISR_HTIF7));
1720 }
1721
1722 /**
1723 * @brief Get Stream 0 transfer complete flag.
1724 * @rmtoll LISR TCIF0 LL_DMA_IsActiveFlag_TC0
1725 * @param DMAx DMAx Instance
1726 * @retval State of bit (1 or 0).
1727 */
LL_DMA_IsActiveFlag_TC0(DMA_TypeDef * DMAx)1728 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC0(DMA_TypeDef *DMAx)
1729 {
1730 return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF0)==(DMA_LISR_TCIF0));
1731 }
1732
1733 /**
1734 * @brief Get Stream 1 transfer complete flag.
1735 * @rmtoll LISR TCIF1 LL_DMA_IsActiveFlag_TC1
1736 * @param DMAx DMAx Instance
1737 * @retval State of bit (1 or 0).
1738 */
LL_DMA_IsActiveFlag_TC1(DMA_TypeDef * DMAx)1739 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
1740 {
1741 return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF1)==(DMA_LISR_TCIF1));
1742 }
1743
1744 /**
1745 * @brief Get Stream 2 transfer complete flag.
1746 * @rmtoll LISR TCIF2 LL_DMA_IsActiveFlag_TC2
1747 * @param DMAx DMAx Instance
1748 * @retval State of bit (1 or 0).
1749 */
LL_DMA_IsActiveFlag_TC2(DMA_TypeDef * DMAx)1750 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
1751 {
1752 return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF2)==(DMA_LISR_TCIF2));
1753 }
1754
1755 /**
1756 * @brief Get Stream 3 transfer complete flag.
1757 * @rmtoll LISR TCIF3 LL_DMA_IsActiveFlag_TC3
1758 * @param DMAx DMAx Instance
1759 * @retval State of bit (1 or 0).
1760 */
LL_DMA_IsActiveFlag_TC3(DMA_TypeDef * DMAx)1761 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
1762 {
1763 return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF3)==(DMA_LISR_TCIF3));
1764 }
1765
1766 /**
1767 * @brief Get Stream 4 transfer complete flag.
1768 * @rmtoll HISR TCIF4 LL_DMA_IsActiveFlag_TC4
1769 * @param DMAx DMAx Instance
1770 * @retval State of bit (1 or 0).
1771 */
LL_DMA_IsActiveFlag_TC4(DMA_TypeDef * DMAx)1772 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
1773 {
1774 return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF4)==(DMA_HISR_TCIF4));
1775 }
1776
1777 /**
1778 * @brief Get Stream 5 transfer complete flag.
1779 * @rmtoll HISR TCIF0 LL_DMA_IsActiveFlag_TC5
1780 * @param DMAx DMAx Instance
1781 * @retval State of bit (1 or 0).
1782 */
LL_DMA_IsActiveFlag_TC5(DMA_TypeDef * DMAx)1783 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
1784 {
1785 return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF5)==(DMA_HISR_TCIF5));
1786 }
1787
1788 /**
1789 * @brief Get Stream 6 transfer complete flag.
1790 * @rmtoll HISR TCIF6 LL_DMA_IsActiveFlag_TC6
1791 * @param DMAx DMAx Instance
1792 * @retval State of bit (1 or 0).
1793 */
LL_DMA_IsActiveFlag_TC6(DMA_TypeDef * DMAx)1794 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
1795 {
1796 return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF6)==(DMA_HISR_TCIF6));
1797 }
1798
1799 /**
1800 * @brief Get Stream 7 transfer complete flag.
1801 * @rmtoll HISR TCIF7 LL_DMA_IsActiveFlag_TC7
1802 * @param DMAx DMAx Instance
1803 * @retval State of bit (1 or 0).
1804 */
LL_DMA_IsActiveFlag_TC7(DMA_TypeDef * DMAx)1805 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
1806 {
1807 return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF7)==(DMA_HISR_TCIF7));
1808 }
1809
1810 /**
1811 * @brief Get Stream 0 transfer error flag.
1812 * @rmtoll LISR TEIF0 LL_DMA_IsActiveFlag_TE0
1813 * @param DMAx DMAx Instance
1814 * @retval State of bit (1 or 0).
1815 */
LL_DMA_IsActiveFlag_TE0(DMA_TypeDef * DMAx)1816 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE0(DMA_TypeDef *DMAx)
1817 {
1818 return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF0)==(DMA_LISR_TEIF0));
1819 }
1820
1821 /**
1822 * @brief Get Stream 1 transfer error flag.
1823 * @rmtoll LISR TEIF1 LL_DMA_IsActiveFlag_TE1
1824 * @param DMAx DMAx Instance
1825 * @retval State of bit (1 or 0).
1826 */
LL_DMA_IsActiveFlag_TE1(DMA_TypeDef * DMAx)1827 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
1828 {
1829 return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF1)==(DMA_LISR_TEIF1));
1830 }
1831
1832 /**
1833 * @brief Get Stream 2 transfer error flag.
1834 * @rmtoll LISR TEIF2 LL_DMA_IsActiveFlag_TE2
1835 * @param DMAx DMAx Instance
1836 * @retval State of bit (1 or 0).
1837 */
LL_DMA_IsActiveFlag_TE2(DMA_TypeDef * DMAx)1838 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
1839 {
1840 return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF2)==(DMA_LISR_TEIF2));
1841 }
1842
1843 /**
1844 * @brief Get Stream 3 transfer error flag.
1845 * @rmtoll LISR TEIF3 LL_DMA_IsActiveFlag_TE3
1846 * @param DMAx DMAx Instance
1847 * @retval State of bit (1 or 0).
1848 */
LL_DMA_IsActiveFlag_TE3(DMA_TypeDef * DMAx)1849 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
1850 {
1851 return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF3)==(DMA_LISR_TEIF3));
1852 }
1853
1854 /**
1855 * @brief Get Stream 4 transfer error flag.
1856 * @rmtoll HISR TEIF4 LL_DMA_IsActiveFlag_TE4
1857 * @param DMAx DMAx Instance
1858 * @retval State of bit (1 or 0).
1859 */
LL_DMA_IsActiveFlag_TE4(DMA_TypeDef * DMAx)1860 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
1861 {
1862 return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF4)==(DMA_HISR_TEIF4));
1863 }
1864
1865 /**
1866 * @brief Get Stream 5 transfer error flag.
1867 * @rmtoll HISR TEIF0 LL_DMA_IsActiveFlag_TE5
1868 * @param DMAx DMAx Instance
1869 * @retval State of bit (1 or 0).
1870 */
LL_DMA_IsActiveFlag_TE5(DMA_TypeDef * DMAx)1871 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
1872 {
1873 return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF5)==(DMA_HISR_TEIF5));
1874 }
1875
1876 /**
1877 * @brief Get Stream 6 transfer error flag.
1878 * @rmtoll HISR TEIF6 LL_DMA_IsActiveFlag_TE6
1879 * @param DMAx DMAx Instance
1880 * @retval State of bit (1 or 0).
1881 */
LL_DMA_IsActiveFlag_TE6(DMA_TypeDef * DMAx)1882 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
1883 {
1884 return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF6)==(DMA_HISR_TEIF6));
1885 }
1886
1887 /**
1888 * @brief Get Stream 7 transfer error flag.
1889 * @rmtoll HISR TEIF7 LL_DMA_IsActiveFlag_TE7
1890 * @param DMAx DMAx Instance
1891 * @retval State of bit (1 or 0).
1892 */
LL_DMA_IsActiveFlag_TE7(DMA_TypeDef * DMAx)1893 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
1894 {
1895 return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF7)==(DMA_HISR_TEIF7));
1896 }
1897
1898 /**
1899 * @brief Get Stream 0 direct mode error flag.
1900 * @rmtoll LISR DMEIF0 LL_DMA_IsActiveFlag_DME0
1901 * @param DMAx DMAx Instance
1902 * @retval State of bit (1 or 0).
1903 */
LL_DMA_IsActiveFlag_DME0(DMA_TypeDef * DMAx)1904 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME0(DMA_TypeDef *DMAx)
1905 {
1906 return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF0)==(DMA_LISR_DMEIF0));
1907 }
1908
1909 /**
1910 * @brief Get Stream 1 direct mode error flag.
1911 * @rmtoll LISR DMEIF1 LL_DMA_IsActiveFlag_DME1
1912 * @param DMAx DMAx Instance
1913 * @retval State of bit (1 or 0).
1914 */
LL_DMA_IsActiveFlag_DME1(DMA_TypeDef * DMAx)1915 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME1(DMA_TypeDef *DMAx)
1916 {
1917 return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF1)==(DMA_LISR_DMEIF1));
1918 }
1919
1920 /**
1921 * @brief Get Stream 2 direct mode error flag.
1922 * @rmtoll LISR DMEIF2 LL_DMA_IsActiveFlag_DME2
1923 * @param DMAx DMAx Instance
1924 * @retval State of bit (1 or 0).
1925 */
LL_DMA_IsActiveFlag_DME2(DMA_TypeDef * DMAx)1926 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME2(DMA_TypeDef *DMAx)
1927 {
1928 return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF2)==(DMA_LISR_DMEIF2));
1929 }
1930
1931 /**
1932 * @brief Get Stream 3 direct mode error flag.
1933 * @rmtoll LISR DMEIF3 LL_DMA_IsActiveFlag_DME3
1934 * @param DMAx DMAx Instance
1935 * @retval State of bit (1 or 0).
1936 */
LL_DMA_IsActiveFlag_DME3(DMA_TypeDef * DMAx)1937 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME3(DMA_TypeDef *DMAx)
1938 {
1939 return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF3)==(DMA_LISR_DMEIF3));
1940 }
1941
1942 /**
1943 * @brief Get Stream 4 direct mode error flag.
1944 * @rmtoll HISR DMEIF4 LL_DMA_IsActiveFlag_DME4
1945 * @param DMAx DMAx Instance
1946 * @retval State of bit (1 or 0).
1947 */
LL_DMA_IsActiveFlag_DME4(DMA_TypeDef * DMAx)1948 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME4(DMA_TypeDef *DMAx)
1949 {
1950 return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF4)==(DMA_HISR_DMEIF4));
1951 }
1952
1953 /**
1954 * @brief Get Stream 5 direct mode error flag.
1955 * @rmtoll HISR DMEIF0 LL_DMA_IsActiveFlag_DME5
1956 * @param DMAx DMAx Instance
1957 * @retval State of bit (1 or 0).
1958 */
LL_DMA_IsActiveFlag_DME5(DMA_TypeDef * DMAx)1959 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME5(DMA_TypeDef *DMAx)
1960 {
1961 return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF5)==(DMA_HISR_DMEIF5));
1962 }
1963
1964 /**
1965 * @brief Get Stream 6 direct mode error flag.
1966 * @rmtoll HISR DMEIF6 LL_DMA_IsActiveFlag_DME6
1967 * @param DMAx DMAx Instance
1968 * @retval State of bit (1 or 0).
1969 */
LL_DMA_IsActiveFlag_DME6(DMA_TypeDef * DMAx)1970 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME6(DMA_TypeDef *DMAx)
1971 {
1972 return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF6)==(DMA_HISR_DMEIF6));
1973 }
1974
1975 /**
1976 * @brief Get Stream 7 direct mode error flag.
1977 * @rmtoll HISR DMEIF7 LL_DMA_IsActiveFlag_DME7
1978 * @param DMAx DMAx Instance
1979 * @retval State of bit (1 or 0).
1980 */
LL_DMA_IsActiveFlag_DME7(DMA_TypeDef * DMAx)1981 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME7(DMA_TypeDef *DMAx)
1982 {
1983 return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF7)==(DMA_HISR_DMEIF7));
1984 }
1985
1986 /**
1987 * @brief Get Stream 0 FIFO error flag.
1988 * @rmtoll LISR FEIF0 LL_DMA_IsActiveFlag_FE0
1989 * @param DMAx DMAx Instance
1990 * @retval State of bit (1 or 0).
1991 */
LL_DMA_IsActiveFlag_FE0(DMA_TypeDef * DMAx)1992 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE0(DMA_TypeDef *DMAx)
1993 {
1994 return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF0)==(DMA_LISR_FEIF0));
1995 }
1996
1997 /**
1998 * @brief Get Stream 1 FIFO error flag.
1999 * @rmtoll LISR FEIF1 LL_DMA_IsActiveFlag_FE1
2000 * @param DMAx DMAx Instance
2001 * @retval State of bit (1 or 0).
2002 */
LL_DMA_IsActiveFlag_FE1(DMA_TypeDef * DMAx)2003 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE1(DMA_TypeDef *DMAx)
2004 {
2005 return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF1)==(DMA_LISR_FEIF1));
2006 }
2007
2008 /**
2009 * @brief Get Stream 2 FIFO error flag.
2010 * @rmtoll LISR FEIF2 LL_DMA_IsActiveFlag_FE2
2011 * @param DMAx DMAx Instance
2012 * @retval State of bit (1 or 0).
2013 */
LL_DMA_IsActiveFlag_FE2(DMA_TypeDef * DMAx)2014 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE2(DMA_TypeDef *DMAx)
2015 {
2016 return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF2)==(DMA_LISR_FEIF2));
2017 }
2018
2019 /**
2020 * @brief Get Stream 3 FIFO error flag.
2021 * @rmtoll LISR FEIF3 LL_DMA_IsActiveFlag_FE3
2022 * @param DMAx DMAx Instance
2023 * @retval State of bit (1 or 0).
2024 */
LL_DMA_IsActiveFlag_FE3(DMA_TypeDef * DMAx)2025 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE3(DMA_TypeDef *DMAx)
2026 {
2027 return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF3)==(DMA_LISR_FEIF3));
2028 }
2029
2030 /**
2031 * @brief Get Stream 4 FIFO error flag.
2032 * @rmtoll HISR FEIF4 LL_DMA_IsActiveFlag_FE4
2033 * @param DMAx DMAx Instance
2034 * @retval State of bit (1 or 0).
2035 */
LL_DMA_IsActiveFlag_FE4(DMA_TypeDef * DMAx)2036 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE4(DMA_TypeDef *DMAx)
2037 {
2038 return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF4)==(DMA_HISR_FEIF4));
2039 }
2040
2041 /**
2042 * @brief Get Stream 5 FIFO error flag.
2043 * @rmtoll HISR FEIF0 LL_DMA_IsActiveFlag_FE5
2044 * @param DMAx DMAx Instance
2045 * @retval State of bit (1 or 0).
2046 */
LL_DMA_IsActiveFlag_FE5(DMA_TypeDef * DMAx)2047 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE5(DMA_TypeDef *DMAx)
2048 {
2049 return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF5)==(DMA_HISR_FEIF5));
2050 }
2051
2052 /**
2053 * @brief Get Stream 6 FIFO error flag.
2054 * @rmtoll HISR FEIF6 LL_DMA_IsActiveFlag_FE6
2055 * @param DMAx DMAx Instance
2056 * @retval State of bit (1 or 0).
2057 */
LL_DMA_IsActiveFlag_FE6(DMA_TypeDef * DMAx)2058 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE6(DMA_TypeDef *DMAx)
2059 {
2060 return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF6)==(DMA_HISR_FEIF6));
2061 }
2062
2063 /**
2064 * @brief Get Stream 7 FIFO error flag.
2065 * @rmtoll HISR FEIF7 LL_DMA_IsActiveFlag_FE7
2066 * @param DMAx DMAx Instance
2067 * @retval State of bit (1 or 0).
2068 */
LL_DMA_IsActiveFlag_FE7(DMA_TypeDef * DMAx)2069 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE7(DMA_TypeDef *DMAx)
2070 {
2071 return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF7)==(DMA_HISR_FEIF7));
2072 }
2073
2074 /**
2075 * @brief Clear Stream 0 half transfer flag.
2076 * @rmtoll LIFCR CHTIF0 LL_DMA_ClearFlag_HT0
2077 * @param DMAx DMAx Instance
2078 * @retval None
2079 */
LL_DMA_ClearFlag_HT0(DMA_TypeDef * DMAx)2080 __STATIC_INLINE void LL_DMA_ClearFlag_HT0(DMA_TypeDef *DMAx)
2081 {
2082 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF0);
2083 }
2084
2085 /**
2086 * @brief Clear Stream 1 half transfer flag.
2087 * @rmtoll LIFCR CHTIF1 LL_DMA_ClearFlag_HT1
2088 * @param DMAx DMAx Instance
2089 * @retval None
2090 */
LL_DMA_ClearFlag_HT1(DMA_TypeDef * DMAx)2091 __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
2092 {
2093 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF1);
2094 }
2095
2096 /**
2097 * @brief Clear Stream 2 half transfer flag.
2098 * @rmtoll LIFCR CHTIF2 LL_DMA_ClearFlag_HT2
2099 * @param DMAx DMAx Instance
2100 * @retval None
2101 */
LL_DMA_ClearFlag_HT2(DMA_TypeDef * DMAx)2102 __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
2103 {
2104 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF2);
2105 }
2106
2107 /**
2108 * @brief Clear Stream 3 half transfer flag.
2109 * @rmtoll LIFCR CHTIF3 LL_DMA_ClearFlag_HT3
2110 * @param DMAx DMAx Instance
2111 * @retval None
2112 */
LL_DMA_ClearFlag_HT3(DMA_TypeDef * DMAx)2113 __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
2114 {
2115 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF3);
2116 }
2117
2118 /**
2119 * @brief Clear Stream 4 half transfer flag.
2120 * @rmtoll HIFCR CHTIF4 LL_DMA_ClearFlag_HT4
2121 * @param DMAx DMAx Instance
2122 * @retval None
2123 */
LL_DMA_ClearFlag_HT4(DMA_TypeDef * DMAx)2124 __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
2125 {
2126 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF4);
2127 }
2128
2129 /**
2130 * @brief Clear Stream 5 half transfer flag.
2131 * @rmtoll HIFCR CHTIF5 LL_DMA_ClearFlag_HT5
2132 * @param DMAx DMAx Instance
2133 * @retval None
2134 */
LL_DMA_ClearFlag_HT5(DMA_TypeDef * DMAx)2135 __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
2136 {
2137 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF5);
2138 }
2139
2140 /**
2141 * @brief Clear Stream 6 half transfer flag.
2142 * @rmtoll HIFCR CHTIF6 LL_DMA_ClearFlag_HT6
2143 * @param DMAx DMAx Instance
2144 * @retval None
2145 */
LL_DMA_ClearFlag_HT6(DMA_TypeDef * DMAx)2146 __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
2147 {
2148 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF6);
2149 }
2150
2151 /**
2152 * @brief Clear Stream 7 half transfer flag.
2153 * @rmtoll HIFCR CHTIF7 LL_DMA_ClearFlag_HT7
2154 * @param DMAx DMAx Instance
2155 * @retval None
2156 */
LL_DMA_ClearFlag_HT7(DMA_TypeDef * DMAx)2157 __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
2158 {
2159 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF7);
2160 }
2161
2162 /**
2163 * @brief Clear Stream 0 transfer complete flag.
2164 * @rmtoll LIFCR CTCIF0 LL_DMA_ClearFlag_TC0
2165 * @param DMAx DMAx Instance
2166 * @retval None
2167 */
LL_DMA_ClearFlag_TC0(DMA_TypeDef * DMAx)2168 __STATIC_INLINE void LL_DMA_ClearFlag_TC0(DMA_TypeDef *DMAx)
2169 {
2170 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF0);
2171 }
2172
2173 /**
2174 * @brief Clear Stream 1 transfer complete flag.
2175 * @rmtoll LIFCR CTCIF1 LL_DMA_ClearFlag_TC1
2176 * @param DMAx DMAx Instance
2177 * @retval None
2178 */
LL_DMA_ClearFlag_TC1(DMA_TypeDef * DMAx)2179 __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
2180 {
2181 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF1);
2182 }
2183
2184 /**
2185 * @brief Clear Stream 2 transfer complete flag.
2186 * @rmtoll LIFCR CTCIF2 LL_DMA_ClearFlag_TC2
2187 * @param DMAx DMAx Instance
2188 * @retval None
2189 */
LL_DMA_ClearFlag_TC2(DMA_TypeDef * DMAx)2190 __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
2191 {
2192 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF2);
2193 }
2194
2195 /**
2196 * @brief Clear Stream 3 transfer complete flag.
2197 * @rmtoll LIFCR CTCIF3 LL_DMA_ClearFlag_TC3
2198 * @param DMAx DMAx Instance
2199 * @retval None
2200 */
LL_DMA_ClearFlag_TC3(DMA_TypeDef * DMAx)2201 __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
2202 {
2203 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF3);
2204 }
2205
2206 /**
2207 * @brief Clear Stream 4 transfer complete flag.
2208 * @rmtoll HIFCR CTCIF4 LL_DMA_ClearFlag_TC4
2209 * @param DMAx DMAx Instance
2210 * @retval None
2211 */
LL_DMA_ClearFlag_TC4(DMA_TypeDef * DMAx)2212 __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
2213 {
2214 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF4);
2215 }
2216
2217 /**
2218 * @brief Clear Stream 5 transfer complete flag.
2219 * @rmtoll HIFCR CTCIF5 LL_DMA_ClearFlag_TC5
2220 * @param DMAx DMAx Instance
2221 * @retval None
2222 */
LL_DMA_ClearFlag_TC5(DMA_TypeDef * DMAx)2223 __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
2224 {
2225 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF5);
2226 }
2227
2228 /**
2229 * @brief Clear Stream 6 transfer complete flag.
2230 * @rmtoll HIFCR CTCIF6 LL_DMA_ClearFlag_TC6
2231 * @param DMAx DMAx Instance
2232 * @retval None
2233 */
LL_DMA_ClearFlag_TC6(DMA_TypeDef * DMAx)2234 __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
2235 {
2236 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF6);
2237 }
2238
2239 /**
2240 * @brief Clear Stream 7 transfer complete flag.
2241 * @rmtoll HIFCR CTCIF7 LL_DMA_ClearFlag_TC7
2242 * @param DMAx DMAx Instance
2243 * @retval None
2244 */
LL_DMA_ClearFlag_TC7(DMA_TypeDef * DMAx)2245 __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
2246 {
2247 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF7);
2248 }
2249
2250 /**
2251 * @brief Clear Stream 0 transfer error flag.
2252 * @rmtoll LIFCR CTEIF0 LL_DMA_ClearFlag_TE0
2253 * @param DMAx DMAx Instance
2254 * @retval None
2255 */
LL_DMA_ClearFlag_TE0(DMA_TypeDef * DMAx)2256 __STATIC_INLINE void LL_DMA_ClearFlag_TE0(DMA_TypeDef *DMAx)
2257 {
2258 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF0);
2259 }
2260
2261 /**
2262 * @brief Clear Stream 1 transfer error flag.
2263 * @rmtoll LIFCR CTEIF1 LL_DMA_ClearFlag_TE1
2264 * @param DMAx DMAx Instance
2265 * @retval None
2266 */
LL_DMA_ClearFlag_TE1(DMA_TypeDef * DMAx)2267 __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
2268 {
2269 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF1);
2270 }
2271
2272 /**
2273 * @brief Clear Stream 2 transfer error flag.
2274 * @rmtoll LIFCR CTEIF2 LL_DMA_ClearFlag_TE2
2275 * @param DMAx DMAx Instance
2276 * @retval None
2277 */
LL_DMA_ClearFlag_TE2(DMA_TypeDef * DMAx)2278 __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
2279 {
2280 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF2);
2281 }
2282
2283 /**
2284 * @brief Clear Stream 3 transfer error flag.
2285 * @rmtoll LIFCR CTEIF3 LL_DMA_ClearFlag_TE3
2286 * @param DMAx DMAx Instance
2287 * @retval None
2288 */
LL_DMA_ClearFlag_TE3(DMA_TypeDef * DMAx)2289 __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
2290 {
2291 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF3);
2292 }
2293
2294 /**
2295 * @brief Clear Stream 4 transfer error flag.
2296 * @rmtoll HIFCR CTEIF4 LL_DMA_ClearFlag_TE4
2297 * @param DMAx DMAx Instance
2298 * @retval None
2299 */
LL_DMA_ClearFlag_TE4(DMA_TypeDef * DMAx)2300 __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
2301 {
2302 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF4);
2303 }
2304
2305 /**
2306 * @brief Clear Stream 5 transfer error flag.
2307 * @rmtoll HIFCR CTEIF5 LL_DMA_ClearFlag_TE5
2308 * @param DMAx DMAx Instance
2309 * @retval None
2310 */
LL_DMA_ClearFlag_TE5(DMA_TypeDef * DMAx)2311 __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
2312 {
2313 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF5);
2314 }
2315
2316 /**
2317 * @brief Clear Stream 6 transfer error flag.
2318 * @rmtoll HIFCR CTEIF6 LL_DMA_ClearFlag_TE6
2319 * @param DMAx DMAx Instance
2320 * @retval None
2321 */
LL_DMA_ClearFlag_TE6(DMA_TypeDef * DMAx)2322 __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
2323 {
2324 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF6);
2325 }
2326
2327 /**
2328 * @brief Clear Stream 7 transfer error flag.
2329 * @rmtoll HIFCR CTEIF7 LL_DMA_ClearFlag_TE7
2330 * @param DMAx DMAx Instance
2331 * @retval None
2332 */
LL_DMA_ClearFlag_TE7(DMA_TypeDef * DMAx)2333 __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
2334 {
2335 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF7);
2336 }
2337
2338 /**
2339 * @brief Clear Stream 0 direct mode error flag.
2340 * @rmtoll LIFCR CDMEIF0 LL_DMA_ClearFlag_DME0
2341 * @param DMAx DMAx Instance
2342 * @retval None
2343 */
LL_DMA_ClearFlag_DME0(DMA_TypeDef * DMAx)2344 __STATIC_INLINE void LL_DMA_ClearFlag_DME0(DMA_TypeDef *DMAx)
2345 {
2346 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF0);
2347 }
2348
2349 /**
2350 * @brief Clear Stream 1 direct mode error flag.
2351 * @rmtoll LIFCR CDMEIF1 LL_DMA_ClearFlag_DME1
2352 * @param DMAx DMAx Instance
2353 * @retval None
2354 */
LL_DMA_ClearFlag_DME1(DMA_TypeDef * DMAx)2355 __STATIC_INLINE void LL_DMA_ClearFlag_DME1(DMA_TypeDef *DMAx)
2356 {
2357 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF1);
2358 }
2359
2360 /**
2361 * @brief Clear Stream 2 direct mode error flag.
2362 * @rmtoll LIFCR CDMEIF2 LL_DMA_ClearFlag_DME2
2363 * @param DMAx DMAx Instance
2364 * @retval None
2365 */
LL_DMA_ClearFlag_DME2(DMA_TypeDef * DMAx)2366 __STATIC_INLINE void LL_DMA_ClearFlag_DME2(DMA_TypeDef *DMAx)
2367 {
2368 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF2);
2369 }
2370
2371 /**
2372 * @brief Clear Stream 3 direct mode error flag.
2373 * @rmtoll LIFCR CDMEIF3 LL_DMA_ClearFlag_DME3
2374 * @param DMAx DMAx Instance
2375 * @retval None
2376 */
LL_DMA_ClearFlag_DME3(DMA_TypeDef * DMAx)2377 __STATIC_INLINE void LL_DMA_ClearFlag_DME3(DMA_TypeDef *DMAx)
2378 {
2379 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF3);
2380 }
2381
2382 /**
2383 * @brief Clear Stream 4 direct mode error flag.
2384 * @rmtoll HIFCR CDMEIF4 LL_DMA_ClearFlag_DME4
2385 * @param DMAx DMAx Instance
2386 * @retval None
2387 */
LL_DMA_ClearFlag_DME4(DMA_TypeDef * DMAx)2388 __STATIC_INLINE void LL_DMA_ClearFlag_DME4(DMA_TypeDef *DMAx)
2389 {
2390 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF4);
2391 }
2392
2393 /**
2394 * @brief Clear Stream 5 direct mode error flag.
2395 * @rmtoll HIFCR CDMEIF5 LL_DMA_ClearFlag_DME5
2396 * @param DMAx DMAx Instance
2397 * @retval None
2398 */
LL_DMA_ClearFlag_DME5(DMA_TypeDef * DMAx)2399 __STATIC_INLINE void LL_DMA_ClearFlag_DME5(DMA_TypeDef *DMAx)
2400 {
2401 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF5);
2402 }
2403
2404 /**
2405 * @brief Clear Stream 6 direct mode error flag.
2406 * @rmtoll HIFCR CDMEIF6 LL_DMA_ClearFlag_DME6
2407 * @param DMAx DMAx Instance
2408 * @retval None
2409 */
LL_DMA_ClearFlag_DME6(DMA_TypeDef * DMAx)2410 __STATIC_INLINE void LL_DMA_ClearFlag_DME6(DMA_TypeDef *DMAx)
2411 {
2412 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF6);
2413 }
2414
2415 /**
2416 * @brief Clear Stream 7 direct mode error flag.
2417 * @rmtoll HIFCR CDMEIF7 LL_DMA_ClearFlag_DME7
2418 * @param DMAx DMAx Instance
2419 * @retval None
2420 */
LL_DMA_ClearFlag_DME7(DMA_TypeDef * DMAx)2421 __STATIC_INLINE void LL_DMA_ClearFlag_DME7(DMA_TypeDef *DMAx)
2422 {
2423 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF7);
2424 }
2425
2426 /**
2427 * @brief Clear Stream 0 FIFO error flag.
2428 * @rmtoll LIFCR CFEIF0 LL_DMA_ClearFlag_FE0
2429 * @param DMAx DMAx Instance
2430 * @retval None
2431 */
LL_DMA_ClearFlag_FE0(DMA_TypeDef * DMAx)2432 __STATIC_INLINE void LL_DMA_ClearFlag_FE0(DMA_TypeDef *DMAx)
2433 {
2434 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF0);
2435 }
2436
2437 /**
2438 * @brief Clear Stream 1 FIFO error flag.
2439 * @rmtoll LIFCR CFEIF1 LL_DMA_ClearFlag_FE1
2440 * @param DMAx DMAx Instance
2441 * @retval None
2442 */
LL_DMA_ClearFlag_FE1(DMA_TypeDef * DMAx)2443 __STATIC_INLINE void LL_DMA_ClearFlag_FE1(DMA_TypeDef *DMAx)
2444 {
2445 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF1);
2446 }
2447
2448 /**
2449 * @brief Clear Stream 2 FIFO error flag.
2450 * @rmtoll LIFCR CFEIF2 LL_DMA_ClearFlag_FE2
2451 * @param DMAx DMAx Instance
2452 * @retval None
2453 */
LL_DMA_ClearFlag_FE2(DMA_TypeDef * DMAx)2454 __STATIC_INLINE void LL_DMA_ClearFlag_FE2(DMA_TypeDef *DMAx)
2455 {
2456 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF2);
2457 }
2458
2459 /**
2460 * @brief Clear Stream 3 FIFO error flag.
2461 * @rmtoll LIFCR CFEIF3 LL_DMA_ClearFlag_FE3
2462 * @param DMAx DMAx Instance
2463 * @retval None
2464 */
LL_DMA_ClearFlag_FE3(DMA_TypeDef * DMAx)2465 __STATIC_INLINE void LL_DMA_ClearFlag_FE3(DMA_TypeDef *DMAx)
2466 {
2467 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF3);
2468 }
2469
2470 /**
2471 * @brief Clear Stream 4 FIFO error flag.
2472 * @rmtoll HIFCR CFEIF4 LL_DMA_ClearFlag_FE4
2473 * @param DMAx DMAx Instance
2474 * @retval None
2475 */
LL_DMA_ClearFlag_FE4(DMA_TypeDef * DMAx)2476 __STATIC_INLINE void LL_DMA_ClearFlag_FE4(DMA_TypeDef *DMAx)
2477 {
2478 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF4);
2479 }
2480
2481 /**
2482 * @brief Clear Stream 5 FIFO error flag.
2483 * @rmtoll HIFCR CFEIF5 LL_DMA_ClearFlag_FE5
2484 * @param DMAx DMAx Instance
2485 * @retval None
2486 */
LL_DMA_ClearFlag_FE5(DMA_TypeDef * DMAx)2487 __STATIC_INLINE void LL_DMA_ClearFlag_FE5(DMA_TypeDef *DMAx)
2488 {
2489 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF5);
2490 }
2491
2492 /**
2493 * @brief Clear Stream 6 FIFO error flag.
2494 * @rmtoll HIFCR CFEIF6 LL_DMA_ClearFlag_FE6
2495 * @param DMAx DMAx Instance
2496 * @retval None
2497 */
LL_DMA_ClearFlag_FE6(DMA_TypeDef * DMAx)2498 __STATIC_INLINE void LL_DMA_ClearFlag_FE6(DMA_TypeDef *DMAx)
2499 {
2500 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF6);
2501 }
2502
2503 /**
2504 * @brief Clear Stream 7 FIFO error flag.
2505 * @rmtoll HIFCR CFEIF7 LL_DMA_ClearFlag_FE7
2506 * @param DMAx DMAx Instance
2507 * @retval None
2508 */
LL_DMA_ClearFlag_FE7(DMA_TypeDef * DMAx)2509 __STATIC_INLINE void LL_DMA_ClearFlag_FE7(DMA_TypeDef *DMAx)
2510 {
2511 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF7);
2512 }
2513
2514 /**
2515 * @}
2516 */
2517
2518 /** @defgroup DMA_LL_EF_IT_Management IT_Management
2519 * @{
2520 */
2521
2522 /**
2523 * @brief Enable Half transfer interrupt.
2524 * @rmtoll CR HTIE LL_DMA_EnableIT_HT
2525 * @param DMAx DMAx Instance
2526 * @param Stream This parameter can be one of the following values:
2527 * @arg @ref LL_DMA_STREAM_0
2528 * @arg @ref LL_DMA_STREAM_1
2529 * @arg @ref LL_DMA_STREAM_2
2530 * @arg @ref LL_DMA_STREAM_3
2531 * @arg @ref LL_DMA_STREAM_4
2532 * @arg @ref LL_DMA_STREAM_5
2533 * @arg @ref LL_DMA_STREAM_6
2534 * @arg @ref LL_DMA_STREAM_7
2535 * @retval None
2536 */
LL_DMA_EnableIT_HT(DMA_TypeDef * DMAx,uint32_t Stream)2537 __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
2538 {
2539 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE);
2540 }
2541
2542 /**
2543 * @brief Enable Transfer error interrupt.
2544 * @rmtoll CR TEIE LL_DMA_EnableIT_TE
2545 * @param DMAx DMAx Instance
2546 * @param Stream This parameter can be one of the following values:
2547 * @arg @ref LL_DMA_STREAM_0
2548 * @arg @ref LL_DMA_STREAM_1
2549 * @arg @ref LL_DMA_STREAM_2
2550 * @arg @ref LL_DMA_STREAM_3
2551 * @arg @ref LL_DMA_STREAM_4
2552 * @arg @ref LL_DMA_STREAM_5
2553 * @arg @ref LL_DMA_STREAM_6
2554 * @arg @ref LL_DMA_STREAM_7
2555 * @retval None
2556 */
LL_DMA_EnableIT_TE(DMA_TypeDef * DMAx,uint32_t Stream)2557 __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
2558 {
2559 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE);
2560 }
2561
2562 /**
2563 * @brief Enable Transfer complete interrupt.
2564 * @rmtoll CR TCIE LL_DMA_EnableIT_TC
2565 * @param DMAx DMAx Instance
2566 * @param Stream This parameter can be one of the following values:
2567 * @arg @ref LL_DMA_STREAM_0
2568 * @arg @ref LL_DMA_STREAM_1
2569 * @arg @ref LL_DMA_STREAM_2
2570 * @arg @ref LL_DMA_STREAM_3
2571 * @arg @ref LL_DMA_STREAM_4
2572 * @arg @ref LL_DMA_STREAM_5
2573 * @arg @ref LL_DMA_STREAM_6
2574 * @arg @ref LL_DMA_STREAM_7
2575 * @retval None
2576 */
LL_DMA_EnableIT_TC(DMA_TypeDef * DMAx,uint32_t Stream)2577 __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
2578 {
2579 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE);
2580 }
2581
2582 /**
2583 * @brief Enable Direct mode error interrupt.
2584 * @rmtoll CR DMEIE LL_DMA_EnableIT_DME
2585 * @param DMAx DMAx Instance
2586 * @param Stream This parameter can be one of the following values:
2587 * @arg @ref LL_DMA_STREAM_0
2588 * @arg @ref LL_DMA_STREAM_1
2589 * @arg @ref LL_DMA_STREAM_2
2590 * @arg @ref LL_DMA_STREAM_3
2591 * @arg @ref LL_DMA_STREAM_4
2592 * @arg @ref LL_DMA_STREAM_5
2593 * @arg @ref LL_DMA_STREAM_6
2594 * @arg @ref LL_DMA_STREAM_7
2595 * @retval None
2596 */
LL_DMA_EnableIT_DME(DMA_TypeDef * DMAx,uint32_t Stream)2597 __STATIC_INLINE void LL_DMA_EnableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
2598 {
2599 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE);
2600 }
2601
2602 /**
2603 * @brief Enable FIFO error interrupt.
2604 * @rmtoll FCR FEIE LL_DMA_EnableIT_FE
2605 * @param DMAx DMAx Instance
2606 * @param Stream This parameter can be one of the following values:
2607 * @arg @ref LL_DMA_STREAM_0
2608 * @arg @ref LL_DMA_STREAM_1
2609 * @arg @ref LL_DMA_STREAM_2
2610 * @arg @ref LL_DMA_STREAM_3
2611 * @arg @ref LL_DMA_STREAM_4
2612 * @arg @ref LL_DMA_STREAM_5
2613 * @arg @ref LL_DMA_STREAM_6
2614 * @arg @ref LL_DMA_STREAM_7
2615 * @retval None
2616 */
LL_DMA_EnableIT_FE(DMA_TypeDef * DMAx,uint32_t Stream)2617 __STATIC_INLINE void LL_DMA_EnableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
2618 {
2619 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE);
2620 }
2621
2622 /**
2623 * @brief Disable Half transfer interrupt.
2624 * @rmtoll CR HTIE LL_DMA_DisableIT_HT
2625 * @param DMAx DMAx Instance
2626 * @param Stream This parameter can be one of the following values:
2627 * @arg @ref LL_DMA_STREAM_0
2628 * @arg @ref LL_DMA_STREAM_1
2629 * @arg @ref LL_DMA_STREAM_2
2630 * @arg @ref LL_DMA_STREAM_3
2631 * @arg @ref LL_DMA_STREAM_4
2632 * @arg @ref LL_DMA_STREAM_5
2633 * @arg @ref LL_DMA_STREAM_6
2634 * @arg @ref LL_DMA_STREAM_7
2635 * @retval None
2636 */
LL_DMA_DisableIT_HT(DMA_TypeDef * DMAx,uint32_t Stream)2637 __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
2638 {
2639 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE);
2640 }
2641
2642 /**
2643 * @brief Disable Transfer error interrupt.
2644 * @rmtoll CR TEIE LL_DMA_DisableIT_TE
2645 * @param DMAx DMAx Instance
2646 * @param Stream This parameter can be one of the following values:
2647 * @arg @ref LL_DMA_STREAM_0
2648 * @arg @ref LL_DMA_STREAM_1
2649 * @arg @ref LL_DMA_STREAM_2
2650 * @arg @ref LL_DMA_STREAM_3
2651 * @arg @ref LL_DMA_STREAM_4
2652 * @arg @ref LL_DMA_STREAM_5
2653 * @arg @ref LL_DMA_STREAM_6
2654 * @arg @ref LL_DMA_STREAM_7
2655 * @retval None
2656 */
LL_DMA_DisableIT_TE(DMA_TypeDef * DMAx,uint32_t Stream)2657 __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
2658 {
2659 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE);
2660 }
2661
2662 /**
2663 * @brief Disable Transfer complete interrupt.
2664 * @rmtoll CR TCIE LL_DMA_DisableIT_TC
2665 * @param DMAx DMAx Instance
2666 * @param Stream This parameter can be one of the following values:
2667 * @arg @ref LL_DMA_STREAM_0
2668 * @arg @ref LL_DMA_STREAM_1
2669 * @arg @ref LL_DMA_STREAM_2
2670 * @arg @ref LL_DMA_STREAM_3
2671 * @arg @ref LL_DMA_STREAM_4
2672 * @arg @ref LL_DMA_STREAM_5
2673 * @arg @ref LL_DMA_STREAM_6
2674 * @arg @ref LL_DMA_STREAM_7
2675 * @retval None
2676 */
LL_DMA_DisableIT_TC(DMA_TypeDef * DMAx,uint32_t Stream)2677 __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
2678 {
2679 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE);
2680 }
2681
2682 /**
2683 * @brief Disable Direct mode error interrupt.
2684 * @rmtoll CR DMEIE LL_DMA_DisableIT_DME
2685 * @param DMAx DMAx Instance
2686 * @param Stream This parameter can be one of the following values:
2687 * @arg @ref LL_DMA_STREAM_0
2688 * @arg @ref LL_DMA_STREAM_1
2689 * @arg @ref LL_DMA_STREAM_2
2690 * @arg @ref LL_DMA_STREAM_3
2691 * @arg @ref LL_DMA_STREAM_4
2692 * @arg @ref LL_DMA_STREAM_5
2693 * @arg @ref LL_DMA_STREAM_6
2694 * @arg @ref LL_DMA_STREAM_7
2695 * @retval None
2696 */
LL_DMA_DisableIT_DME(DMA_TypeDef * DMAx,uint32_t Stream)2697 __STATIC_INLINE void LL_DMA_DisableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
2698 {
2699 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE);
2700 }
2701
2702 /**
2703 * @brief Disable FIFO error interrupt.
2704 * @rmtoll FCR FEIE LL_DMA_DisableIT_FE
2705 * @param DMAx DMAx Instance
2706 * @param Stream This parameter can be one of the following values:
2707 * @arg @ref LL_DMA_STREAM_0
2708 * @arg @ref LL_DMA_STREAM_1
2709 * @arg @ref LL_DMA_STREAM_2
2710 * @arg @ref LL_DMA_STREAM_3
2711 * @arg @ref LL_DMA_STREAM_4
2712 * @arg @ref LL_DMA_STREAM_5
2713 * @arg @ref LL_DMA_STREAM_6
2714 * @arg @ref LL_DMA_STREAM_7
2715 * @retval None
2716 */
LL_DMA_DisableIT_FE(DMA_TypeDef * DMAx,uint32_t Stream)2717 __STATIC_INLINE void LL_DMA_DisableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
2718 {
2719 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE);
2720 }
2721
2722 /**
2723 * @brief Check if Half transfer interrup is enabled.
2724 * @rmtoll CR HTIE LL_DMA_IsEnabledIT_HT
2725 * @param DMAx DMAx Instance
2726 * @param Stream This parameter can be one of the following values:
2727 * @arg @ref LL_DMA_STREAM_0
2728 * @arg @ref LL_DMA_STREAM_1
2729 * @arg @ref LL_DMA_STREAM_2
2730 * @arg @ref LL_DMA_STREAM_3
2731 * @arg @ref LL_DMA_STREAM_4
2732 * @arg @ref LL_DMA_STREAM_5
2733 * @arg @ref LL_DMA_STREAM_6
2734 * @arg @ref LL_DMA_STREAM_7
2735 * @retval State of bit (1 or 0).
2736 */
LL_DMA_IsEnabledIT_HT(DMA_TypeDef * DMAx,uint32_t Stream)2737 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
2738 {
2739 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE) == DMA_SxCR_HTIE);
2740 }
2741
2742 /**
2743 * @brief Check if Transfer error nterrup is enabled.
2744 * @rmtoll CR TEIE LL_DMA_IsEnabledIT_TE
2745 * @param DMAx DMAx Instance
2746 * @param Stream This parameter can be one of the following values:
2747 * @arg @ref LL_DMA_STREAM_0
2748 * @arg @ref LL_DMA_STREAM_1
2749 * @arg @ref LL_DMA_STREAM_2
2750 * @arg @ref LL_DMA_STREAM_3
2751 * @arg @ref LL_DMA_STREAM_4
2752 * @arg @ref LL_DMA_STREAM_5
2753 * @arg @ref LL_DMA_STREAM_6
2754 * @arg @ref LL_DMA_STREAM_7
2755 * @retval State of bit (1 or 0).
2756 */
LL_DMA_IsEnabledIT_TE(DMA_TypeDef * DMAx,uint32_t Stream)2757 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
2758 {
2759 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE) == DMA_SxCR_TEIE);
2760 }
2761
2762 /**
2763 * @brief Check if Transfer complete interrup is enabled.
2764 * @rmtoll CR TCIE LL_DMA_IsEnabledIT_TC
2765 * @param DMAx DMAx Instance
2766 * @param Stream This parameter can be one of the following values:
2767 * @arg @ref LL_DMA_STREAM_0
2768 * @arg @ref LL_DMA_STREAM_1
2769 * @arg @ref LL_DMA_STREAM_2
2770 * @arg @ref LL_DMA_STREAM_3
2771 * @arg @ref LL_DMA_STREAM_4
2772 * @arg @ref LL_DMA_STREAM_5
2773 * @arg @ref LL_DMA_STREAM_6
2774 * @arg @ref LL_DMA_STREAM_7
2775 * @retval State of bit (1 or 0).
2776 */
LL_DMA_IsEnabledIT_TC(DMA_TypeDef * DMAx,uint32_t Stream)2777 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
2778 {
2779 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE) == DMA_SxCR_TCIE);
2780 }
2781
2782 /**
2783 * @brief Check if Direct mode error interrupt is enabled.
2784 * @rmtoll CR DMEIE LL_DMA_IsEnabledIT_DME
2785 * @param DMAx DMAx Instance
2786 * @param Stream This parameter can be one of the following values:
2787 * @arg @ref LL_DMA_STREAM_0
2788 * @arg @ref LL_DMA_STREAM_1
2789 * @arg @ref LL_DMA_STREAM_2
2790 * @arg @ref LL_DMA_STREAM_3
2791 * @arg @ref LL_DMA_STREAM_4
2792 * @arg @ref LL_DMA_STREAM_5
2793 * @arg @ref LL_DMA_STREAM_6
2794 * @arg @ref LL_DMA_STREAM_7
2795 * @retval State of bit (1 or 0).
2796 */
LL_DMA_IsEnabledIT_DME(DMA_TypeDef * DMAx,uint32_t Stream)2797 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
2798 {
2799 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE) == DMA_SxCR_DMEIE);
2800 }
2801
2802 /**
2803 * @brief Check if FIFO error interrup is enabled.
2804 * @rmtoll FCR FEIE LL_DMA_IsEnabledIT_FE
2805 * @param DMAx DMAx Instance
2806 * @param Stream This parameter can be one of the following values:
2807 * @arg @ref LL_DMA_STREAM_0
2808 * @arg @ref LL_DMA_STREAM_1
2809 * @arg @ref LL_DMA_STREAM_2
2810 * @arg @ref LL_DMA_STREAM_3
2811 * @arg @ref LL_DMA_STREAM_4
2812 * @arg @ref LL_DMA_STREAM_5
2813 * @arg @ref LL_DMA_STREAM_6
2814 * @arg @ref LL_DMA_STREAM_7
2815 * @retval State of bit (1 or 0).
2816 */
LL_DMA_IsEnabledIT_FE(DMA_TypeDef * DMAx,uint32_t Stream)2817 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
2818 {
2819 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE) == DMA_SxFCR_FEIE);
2820 }
2821
2822 /**
2823 * @}
2824 */
2825
2826 #if defined(USE_FULL_LL_DRIVER)
2827 /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
2828 * @{
2829 */
2830
2831 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA_InitStruct);
2832 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream);
2833 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
2834
2835 /**
2836 * @}
2837 */
2838 #endif /* USE_FULL_LL_DRIVER */
2839
2840 /**
2841 * @}
2842 */
2843
2844 /**
2845 * @}
2846 */
2847
2848 #endif /* DMA1 || DMA2 */
2849
2850 /**
2851 * @}
2852 */
2853
2854 #ifdef __cplusplus
2855 }
2856 #endif
2857
2858 #endif /* __STM32F4xx_LL_DMA_H */
2859
2860 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
2861