xref: /btstack/port/stm32-f4discovery-usb/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f413xx.h (revision a8f7f3fcbcd51f8d2e92aca076b6a9f812db358c) 
1 /**
2   ******************************************************************************
3   * @file    stm32f413xx.h
4   * @author  MCD Application Team
5   * @brief   CMSIS STM32F413xx Device Peripheral Access Layer Header File.
6   *
7   *          This file contains:
8   *           - Data structures and the address mapping for all peripherals
9   *           - peripherals registers declarations and bits definition
10   *           - Macros to access peripheral’s registers hardware
11   *
12   ******************************************************************************
13   * @attention
14   *
15   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
16   * All rights reserved.</center></h2>
17   *
18   * This software component is licensed by ST under BSD 3-Clause license,
19   * the "License"; You may not use this file except in compliance with the
20   * License. You may obtain a copy of the License at:
21   *                        opensource.org/licenses/BSD-3-Clause
22   *
23   ******************************************************************************
24   */
25 
26 /** @addtogroup CMSIS_Device
27   * @{
28   */
29 
30 /** @addtogroup stm32f413xx
31   * @{
32   */
33 
34 #ifndef __STM32F413xx_H
35 #define __STM32F413xx_H
36 
37 #ifdef __cplusplus
38  extern "C" {
39 #endif /* __cplusplus */
40 
41 /** @addtogroup Configuration_section_for_CMSIS
42   * @{
43   */
44 
45 /**
46   * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
47   */
48 #define __CM4_REV                 0x0001U  /*!< Core revision r0p1                            */
49 #define __MPU_PRESENT             1U       /*!< STM32F4XX provides an MPU                     */
50 #define __NVIC_PRIO_BITS          4U       /*!< STM32F4XX uses 4 Bits for the Priority Levels */
51 #define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
52 #define __FPU_PRESENT             1U       /*!< FPU present                                   */
53 
54 /**
55   * @}
56   */
57 
58 /** @addtogroup Peripheral_interrupt_number_definition
59   * @{
60   */
61 
62 /**
63  * @brief STM32F4XX Interrupt Number Definition, according to the selected device
64  *        in @ref Library_configuration_section
65  */
66 typedef enum
67 {
68 /******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/
69   NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
70   MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                           */
71   BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */
72   UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */
73   SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                    */
74   DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */
75   PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                    */
76   SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                */
77 /******  STM32 specific Interrupt Numbers **********************************************************************/
78   WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */
79   PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt                         */
80   TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */
81   RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */
82   FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
83   RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
84   EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
85   EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
86   EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */
87   EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
88   EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
89   DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */
90   DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */
91   DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */
92   DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */
93   DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */
94   DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */
95   DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */
96   ADC_IRQn                    = 18,     /*!< ADC1, ADC2 and ADC3 global Interrupts                             */
97   CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */
98   CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */
99   CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */
100   CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */
101   EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
102   TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */
103   TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */
104   TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
105   TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
106   TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
107   TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
108   TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
109   I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
110   I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
111   I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
112   I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */
113   SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
114   SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
115   USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
116   USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
117   USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
118   EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
119   RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
120   OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */
121   TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */
122   TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */
123   TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
124   TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare global interrupt                             */
125   DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
126   SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                             */
127   TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
128   SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
129   UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */
130   UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */
131   TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */
132   TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */
133   DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */
134   DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */
135   DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */
136   DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */
137   DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */
138   DFSDM1_FLT0_IRQn            = 61,     /*!< DFSDM1 Filter 0 global Interrupt                                  */
139   DFSDM1_FLT1_IRQn            = 62,     /*!< DFSDM1 Filter 1 global Interrupt                                  */
140   CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                                 */
141   CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                                */
142   CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                                */
143   CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                                */
144   OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */
145   DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */
146   DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */
147   DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */
148   USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */
149   I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
150   I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
151   CAN3_TX_IRQn                = 74,     /*!< CAN3 TX Interrupt                                                 */
152   CAN3_RX0_IRQn               = 75,     /*!< CAN3 RX0 Interrupt                                                */
153   CAN3_RX1_IRQn               = 76,     /*!< CAN3 RX1 Interrupt                                                */
154   CAN3_SCE_IRQn               = 77,     /*!< CAN3 SCE Interrupt                                                */
155   RNG_IRQn                    = 80,     /*!< RNG global Interrupt                                              */
156   FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */
157   UART7_IRQn                  = 82,     /*!< UART7 global interrupt                                            */
158   UART8_IRQn                  = 83,     /*!< UART8 global interrupt                                            */
159   SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */
160   SPI5_IRQn                   = 85,     /*!< SPI5 global Interrupt                                             */
161   SAI1_IRQn                   = 87,     /*!< SAI1 global Interrupt                                             */
162   UART9_IRQn                  = 88,     /*!< UART9 global Interrupt                                            */
163   UART10_IRQn                 = 89,     /*!< UART10 global Interrupt                                           */
164   QUADSPI_IRQn                = 92,     /*!< QuadSPI global Interrupt                                          */
165   FMPI2C1_EV_IRQn             = 95,     /*!< FMPI2C1 Event Interrupt                                           */
166   FMPI2C1_ER_IRQn             = 96,     /*!< FMPI2C1 Error Interrupt                                           */
167   LPTIM1_IRQn                 = 97,     /*!< LP TIM1 interrupt                                                 */
168   DFSDM2_FLT0_IRQn            = 98,     /*!< DFSDM2 Filter 0 global Interrupt                                  */
169   DFSDM2_FLT1_IRQn            = 99,     /*!< DFSDM2 Filter 1 global Interrupt                                  */
170   DFSDM2_FLT2_IRQn            = 100,    /*!< DFSDM2 Filter 2 global Interrupt                                  */
171   DFSDM2_FLT3_IRQn            = 101     /*!< DFSDM2 Filter 3 global Interrupt                                  */
172 } IRQn_Type;
173 
174 /**
175   * @}
176   */
177 
178 #include "core_cm4.h"             /* Cortex-M4 processor and core peripherals */
179 #include "system_stm32f4xx.h"
180 #include <stdint.h>
181 
182 /** @addtogroup Peripheral_registers_structures
183   * @{
184   */
185 
186 /**
187   * @brief Analog to Digital Converter
188   */
189 
190 typedef struct
191 {
192   __IO uint32_t SR;     /*!< ADC status register,                         Address offset: 0x00 */
193   __IO uint32_t CR1;    /*!< ADC control register 1,                      Address offset: 0x04 */
194   __IO uint32_t CR2;    /*!< ADC control register 2,                      Address offset: 0x08 */
195   __IO uint32_t SMPR1;  /*!< ADC sample time register 1,                  Address offset: 0x0C */
196   __IO uint32_t SMPR2;  /*!< ADC sample time register 2,                  Address offset: 0x10 */
197   __IO uint32_t JOFR1;  /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
198   __IO uint32_t JOFR2;  /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
199   __IO uint32_t JOFR3;  /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
200   __IO uint32_t JOFR4;  /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
201   __IO uint32_t HTR;    /*!< ADC watchdog higher threshold register,      Address offset: 0x24 */
202   __IO uint32_t LTR;    /*!< ADC watchdog lower threshold register,       Address offset: 0x28 */
203   __IO uint32_t SQR1;   /*!< ADC regular sequence register 1,             Address offset: 0x2C */
204   __IO uint32_t SQR2;   /*!< ADC regular sequence register 2,             Address offset: 0x30 */
205   __IO uint32_t SQR3;   /*!< ADC regular sequence register 3,             Address offset: 0x34 */
206   __IO uint32_t JSQR;   /*!< ADC injected sequence register,              Address offset: 0x38*/
207   __IO uint32_t JDR1;   /*!< ADC injected data register 1,                Address offset: 0x3C */
208   __IO uint32_t JDR2;   /*!< ADC injected data register 2,                Address offset: 0x40 */
209   __IO uint32_t JDR3;   /*!< ADC injected data register 3,                Address offset: 0x44 */
210   __IO uint32_t JDR4;   /*!< ADC injected data register 4,                Address offset: 0x48 */
211   __IO uint32_t DR;     /*!< ADC regular data register,                   Address offset: 0x4C */
212 } ADC_TypeDef;
213 
214 typedef struct
215 {
216   __IO uint32_t CSR;    /*!< ADC Common status register,                  Address offset: ADC1 base address + 0x300 */
217   __IO uint32_t CCR;    /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
218   __IO uint32_t CDR;    /*!< ADC common regular data register for dual
219                              AND triple modes,                            Address offset: ADC1 base address + 0x308 */
220 } ADC_Common_TypeDef;
221 
222 
223 /**
224   * @brief Controller Area Network TxMailBox
225   */
226 
227 typedef struct
228 {
229   __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */
230   __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
231   __IO uint32_t TDLR; /*!< CAN mailbox data low register */
232   __IO uint32_t TDHR; /*!< CAN mailbox data high register */
233 } CAN_TxMailBox_TypeDef;
234 
235 /**
236   * @brief Controller Area Network FIFOMailBox
237   */
238 
239 typedef struct
240 {
241   __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */
242   __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
243   __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
244   __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
245 } CAN_FIFOMailBox_TypeDef;
246 
247 /**
248   * @brief Controller Area Network FilterRegister
249   */
250 
251 typedef struct
252 {
253   __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
254   __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
255 } CAN_FilterRegister_TypeDef;
256 
257 /**
258   * @brief Controller Area Network
259   */
260 
261 typedef struct
262 {
263   __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */
264   __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */
265   __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */
266   __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */
267   __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */
268   __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */
269   __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */
270   __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */
271   uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */
272   CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */
273   CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */
274   uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */
275   __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */
276   __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */
277   uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */
278   __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */
279   uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */
280   __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */
281   uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */
282   __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */
283   uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */
284   CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */
285 } CAN_TypeDef;
286 
287 /**
288   * @brief CRC calculation unit
289   */
290 
291 typedef struct
292 {
293   __IO uint32_t DR;         /*!< CRC Data register,             Address offset: 0x00 */
294   __IO uint8_t  IDR;        /*!< CRC Independent data register, Address offset: 0x04 */
295   uint8_t       RESERVED0;  /*!< Reserved, 0x05                                      */
296   uint16_t      RESERVED1;  /*!< Reserved, 0x06                                      */
297   __IO uint32_t CR;         /*!< CRC Control register,          Address offset: 0x08 */
298 } CRC_TypeDef;
299 
300 /**
301   * @brief DFSDM module registers
302   */
303 typedef struct
304 {
305   __IO uint32_t FLTCR1;      /*!< DFSDM control register1,                          Address offset: 0x100 */
306   __IO uint32_t FLTCR2;      /*!< DFSDM control register2,                          Address offset: 0x104 */
307   __IO uint32_t FLTISR;      /*!< DFSDM interrupt and status register,              Address offset: 0x108 */
308   __IO uint32_t FLTICR;      /*!< DFSDM interrupt flag clear register,              Address offset: 0x10C */
309   __IO uint32_t FLTJCHGR;    /*!< DFSDM injected channel group selection register,  Address offset: 0x110 */
310   __IO uint32_t FLTFCR;      /*!< DFSDM filter control register,                    Address offset: 0x114 */
311   __IO uint32_t FLTJDATAR;   /*!< DFSDM data register for injected group,           Address offset: 0x118 */
312   __IO uint32_t FLTRDATAR;   /*!< DFSDM data register for regular group,            Address offset: 0x11C */
313   __IO uint32_t FLTAWHTR;    /*!< DFSDM analog watchdog high threshold register,    Address offset: 0x120 */
314   __IO uint32_t FLTAWLTR;    /*!< DFSDM analog watchdog low threshold register,     Address offset: 0x124 */
315   __IO uint32_t FLTAWSR;     /*!< DFSDM analog watchdog status register             Address offset: 0x128 */
316   __IO uint32_t FLTAWCFR;    /*!< DFSDM analog watchdog clear flag register         Address offset: 0x12C */
317   __IO uint32_t FLTEXMAX;    /*!< DFSDM extreme detector maximum register,          Address offset: 0x130 */
318   __IO uint32_t FLTEXMIN;    /*!< DFSDM extreme detector minimum register           Address offset: 0x134 */
319   __IO uint32_t FLTCNVTIMR;  /*!< DFSDM conversion timer,                           Address offset: 0x138 */
320 } DFSDM_Filter_TypeDef;
321 
322 /**
323   * @brief DFSDM channel configuration registers
324   */
325 typedef struct
326 {
327   __IO uint32_t CHCFGR1;     /*!< DFSDM channel configuration register1,            Address offset: 0x00 */
328   __IO uint32_t CHCFGR2;     /*!< DFSDM channel configuration register2,            Address offset: 0x04 */
329   __IO uint32_t CHAWSCDR;    /*!< DFSDM channel analog watchdog and
330                                   short circuit detector register,                  Address offset: 0x08 */
331   __IO uint32_t CHWDATAR;    /*!< DFSDM channel watchdog filter data register,      Address offset: 0x0C */
332   __IO uint32_t CHDATINR;    /*!< DFSDM channel data input register,                Address offset: 0x10 */
333 } DFSDM_Channel_TypeDef;
334 
335 /**
336   * @brief Digital to Analog Converter
337   */
338 
339 typedef struct
340 {
341   __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */
342   __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */
343   __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
344   __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
345   __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
346   __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
347   __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
348   __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
349   __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
350   __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
351   __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
352   __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */
353   __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */
354   __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */
355 } DAC_TypeDef;
356 
357 /**
358   * @brief Debug MCU
359   */
360 
361 typedef struct
362 {
363   __IO uint32_t IDCODE;  /*!< MCU device ID code,               Address offset: 0x00 */
364   __IO uint32_t CR;      /*!< Debug MCU configuration register, Address offset: 0x04 */
365   __IO uint32_t APB1FZ;  /*!< Debug MCU APB1 freeze register,   Address offset: 0x08 */
366   __IO uint32_t APB2FZ;  /*!< Debug MCU APB2 freeze register,   Address offset: 0x0C */
367 }DBGMCU_TypeDef;
368 
369 
370 /**
371   * @brief DMA Controller
372   */
373 
374 typedef struct
375 {
376   __IO uint32_t CR;     /*!< DMA stream x configuration register      */
377   __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */
378   __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */
379   __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */
380   __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */
381   __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */
382 } DMA_Stream_TypeDef;
383 
384 typedef struct
385 {
386   __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */
387   __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */
388   __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */
389   __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
390 } DMA_TypeDef;
391 
392 /**
393   * @brief External Interrupt/Event Controller
394   */
395 
396 typedef struct
397 {
398   __IO uint32_t IMR;    /*!< EXTI Interrupt mask register,            Address offset: 0x00 */
399   __IO uint32_t EMR;    /*!< EXTI Event mask register,                Address offset: 0x04 */
400   __IO uint32_t RTSR;   /*!< EXTI Rising trigger selection register,  Address offset: 0x08 */
401   __IO uint32_t FTSR;   /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
402   __IO uint32_t SWIER;  /*!< EXTI Software interrupt event register,  Address offset: 0x10 */
403   __IO uint32_t PR;     /*!< EXTI Pending register,                   Address offset: 0x14 */
404 } EXTI_TypeDef;
405 
406 /**
407   * @brief FLASH Registers
408   */
409 
410 typedef struct
411 {
412   __IO uint32_t ACR;      /*!< FLASH access control register,   Address offset: 0x00 */
413   __IO uint32_t KEYR;     /*!< FLASH key register,              Address offset: 0x04 */
414   __IO uint32_t OPTKEYR;  /*!< FLASH option key register,       Address offset: 0x08 */
415   __IO uint32_t SR;       /*!< FLASH status register,           Address offset: 0x0C */
416   __IO uint32_t CR;       /*!< FLASH control register,          Address offset: 0x10 */
417   __IO uint32_t OPTCR;    /*!< FLASH option control register ,  Address offset: 0x14 */
418   __IO uint32_t OPTCR1;   /*!< FLASH option control register 1, Address offset: 0x18 */
419 } FLASH_TypeDef;
420 
421 
422 
423 /**
424   * @brief Flexible Static Memory Controller
425   */
426 
427 typedef struct
428 {
429   __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
430 } FSMC_Bank1_TypeDef;
431 
432 /**
433   * @brief Flexible Static Memory Controller Bank1E
434   */
435 
436 typedef struct
437 {
438   __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
439 } FSMC_Bank1E_TypeDef;
440 /**
441   * @brief General Purpose I/O
442   */
443 
444 typedef struct
445 {
446   __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */
447   __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */
448   __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */
449   __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
450   __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */
451   __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */
452   __IO uint32_t BSRR;     /*!< GPIO port bit set/reset register,      Address offset: 0x18      */
453   __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */
454   __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
455 } GPIO_TypeDef;
456 
457 /**
458   * @brief System configuration controller
459   */
460 
461 typedef struct
462 {
463   __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
464   __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
465   __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
466   uint32_t      RESERVED;     /*!< Reserved, 0x18                                                               */
467   __IO uint32_t CFGR2;        /*!< SYSCFG Configuration register2,                    Address offset: 0x1C      */
468   __IO uint32_t CMPCR;        /*!< SYSCFG Compensation cell control register,         Address offset: 0x20      */
469   uint32_t      RESERVED1[2]; /*!< Reserved, 0x24-0x28                                                          */
470   __IO uint32_t CFGR;         /*!< SYSCFG Configuration register,                     Address offset: 0x2C      */
471   __IO uint32_t MCHDLYCR;     /*!< SYSCFG multi-channel delay register,               Address offset: 0x30      */
472 } SYSCFG_TypeDef;
473 
474 /**
475   * @brief Inter-integrated Circuit Interface
476   */
477 
478 typedef struct
479 {
480   __IO uint32_t CR1;        /*!< I2C Control register 1,     Address offset: 0x00 */
481   __IO uint32_t CR2;        /*!< I2C Control register 2,     Address offset: 0x04 */
482   __IO uint32_t OAR1;       /*!< I2C Own address register 1, Address offset: 0x08 */
483   __IO uint32_t OAR2;       /*!< I2C Own address register 2, Address offset: 0x0C */
484   __IO uint32_t DR;         /*!< I2C Data register,          Address offset: 0x10 */
485   __IO uint32_t SR1;        /*!< I2C Status register 1,      Address offset: 0x14 */
486   __IO uint32_t SR2;        /*!< I2C Status register 2,      Address offset: 0x18 */
487   __IO uint32_t CCR;        /*!< I2C Clock control register, Address offset: 0x1C */
488   __IO uint32_t TRISE;      /*!< I2C TRISE register,         Address offset: 0x20 */
489   __IO uint32_t FLTR;       /*!< I2C FLTR register,          Address offset: 0x24 */
490 } I2C_TypeDef;
491 
492 /**
493   * @brief Inter-integrated Circuit Interface
494   */
495 
496 typedef struct
497 {
498   __IO uint32_t CR1;         /*!< FMPI2C Control register 1,            Address offset: 0x00 */
499   __IO uint32_t CR2;         /*!< FMPI2C Control register 2,            Address offset: 0x04 */
500   __IO uint32_t OAR1;        /*!< FMPI2C Own address 1 register,        Address offset: 0x08 */
501   __IO uint32_t OAR2;        /*!< FMPI2C Own address 2 register,        Address offset: 0x0C */
502   __IO uint32_t TIMINGR;     /*!< FMPI2C Timing register,               Address offset: 0x10 */
503   __IO uint32_t TIMEOUTR;    /*!< FMPI2C Timeout register,              Address offset: 0x14 */
504   __IO uint32_t ISR;         /*!< FMPI2C Interrupt and status register, Address offset: 0x18 */
505   __IO uint32_t ICR;         /*!< FMPI2C Interrupt clear register,      Address offset: 0x1C */
506   __IO uint32_t PECR;        /*!< FMPI2C PEC register,                  Address offset: 0x20 */
507   __IO uint32_t RXDR;        /*!< FMPI2C Receive data register,         Address offset: 0x24 */
508   __IO uint32_t TXDR;        /*!< FMPI2C Transmit data register,        Address offset: 0x28 */
509 } FMPI2C_TypeDef;
510 
511 /**
512   * @brief Independent WATCHDOG
513   */
514 
515 typedef struct
516 {
517   __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
518   __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
519   __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
520   __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
521 } IWDG_TypeDef;
522 
523 
524 /**
525   * @brief Power Control
526   */
527 
528 typedef struct
529 {
530   __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
531   __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
532 } PWR_TypeDef;
533 
534 /**
535   * @brief Reset and Clock Control
536   */
537 
538 typedef struct
539 {
540   __IO uint32_t CR;            /*!< RCC clock control register,                                  Address offset: 0x00 */
541   __IO uint32_t PLLCFGR;       /*!< RCC PLL configuration register,                              Address offset: 0x04 */
542   __IO uint32_t CFGR;          /*!< RCC clock configuration register,                            Address offset: 0x08 */
543   __IO uint32_t CIR;           /*!< RCC clock interrupt register,                                Address offset: 0x0C */
544   __IO uint32_t AHB1RSTR;      /*!< RCC AHB1 peripheral reset register,                          Address offset: 0x10 */
545   __IO uint32_t AHB2RSTR;      /*!< RCC AHB2 peripheral reset register,                          Address offset: 0x14 */
546   __IO uint32_t AHB3RSTR;      /*!< RCC AHB3 peripheral reset register,                          Address offset: 0x18 */
547   uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                                    */
548   __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                          Address offset: 0x20 */
549   __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                          Address offset: 0x24 */
550   uint32_t      RESERVED1[2];  /*!< Reserved, 0x28-0x2C                                                               */
551   __IO uint32_t AHB1ENR;       /*!< RCC AHB1 peripheral clock register,                          Address offset: 0x30 */
552   __IO uint32_t AHB2ENR;       /*!< RCC AHB2 peripheral clock register,                          Address offset: 0x34 */
553   __IO uint32_t AHB3ENR;       /*!< RCC AHB3 peripheral clock register,                          Address offset: 0x38 */
554   uint32_t      RESERVED2;     /*!< Reserved, 0x3C                                                                    */
555   __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x40 */
556   __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x44 */
557   uint32_t      RESERVED3[2];  /*!< Reserved, 0x48-0x4C                                                               */
558   __IO uint32_t AHB1LPENR;     /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
559   __IO uint32_t AHB2LPENR;     /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
560   __IO uint32_t AHB3LPENR;     /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
561   uint32_t      RESERVED4;     /*!< Reserved, 0x5C                                                                    */
562   __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
563   __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
564   uint32_t      RESERVED5[2];  /*!< Reserved, 0x68-0x6C                                                               */
565   __IO uint32_t BDCR;          /*!< RCC Backup domain control register,                          Address offset: 0x70 */
566   __IO uint32_t CSR;           /*!< RCC clock control & status register,                         Address offset: 0x74 */
567   uint32_t      RESERVED6[2];  /*!< Reserved, 0x78-0x7C                                                               */
568   __IO uint32_t SSCGR;         /*!< RCC spread spectrum clock generation register,               Address offset: 0x80 */
569   __IO uint32_t PLLI2SCFGR;    /*!< RCC PLLI2S configuration register,                           Address offset: 0x84 */
570   uint32_t      RESERVED7;     /*!< Reserved, 0x84                                                                    */
571   __IO uint32_t DCKCFGR;       /*!< RCC Dedicated Clocks configuration register,                 Address offset: 0x8C */
572   __IO uint32_t CKGATENR;      /*!< RCC Clocks Gated ENable Register,                            Address offset: 0x90 */
573   __IO uint32_t DCKCFGR2;      /*!< RCC Dedicated Clocks configuration register 2,               Address offset: 0x94 */
574 } RCC_TypeDef;
575 
576 /**
577   * @brief Real-Time Clock
578   */
579 
580 typedef struct
581 {
582   __IO uint32_t TR;      /*!< RTC time register,                                        Address offset: 0x00 */
583   __IO uint32_t DR;      /*!< RTC date register,                                        Address offset: 0x04 */
584   __IO uint32_t CR;      /*!< RTC control register,                                     Address offset: 0x08 */
585   __IO uint32_t ISR;     /*!< RTC initialization and status register,                   Address offset: 0x0C */
586   __IO uint32_t PRER;    /*!< RTC prescaler register,                                   Address offset: 0x10 */
587   __IO uint32_t WUTR;    /*!< RTC wakeup timer register,                                Address offset: 0x14 */
588   __IO uint32_t CALIBR;  /*!< RTC calibration register,                                 Address offset: 0x18 */
589   __IO uint32_t ALRMAR;  /*!< RTC alarm A register,                                     Address offset: 0x1C */
590   __IO uint32_t ALRMBR;  /*!< RTC alarm B register,                                     Address offset: 0x20 */
591   __IO uint32_t WPR;     /*!< RTC write protection register,                            Address offset: 0x24 */
592   __IO uint32_t SSR;     /*!< RTC sub second register,                                  Address offset: 0x28 */
593   __IO uint32_t SHIFTR;  /*!< RTC shift control register,                               Address offset: 0x2C */
594   __IO uint32_t TSTR;    /*!< RTC time stamp time register,                             Address offset: 0x30 */
595   __IO uint32_t TSDR;    /*!< RTC time stamp date register,                             Address offset: 0x34 */
596   __IO uint32_t TSSSR;   /*!< RTC time-stamp sub second register,                       Address offset: 0x38 */
597   __IO uint32_t CALR;    /*!< RTC calibration register,                                 Address offset: 0x3C */
598   __IO uint32_t TAFCR;   /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
599   __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register,                          Address offset: 0x44 */
600   __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register,                          Address offset: 0x48 */
601   uint32_t RESERVED7;    /*!< Reserved, 0x4C                                                                 */
602   __IO uint32_t BKP0R;   /*!< RTC backup register 1,                                    Address offset: 0x50 */
603   __IO uint32_t BKP1R;   /*!< RTC backup register 1,                                    Address offset: 0x54 */
604   __IO uint32_t BKP2R;   /*!< RTC backup register 2,                                    Address offset: 0x58 */
605   __IO uint32_t BKP3R;   /*!< RTC backup register 3,                                    Address offset: 0x5C */
606   __IO uint32_t BKP4R;   /*!< RTC backup register 4,                                    Address offset: 0x60 */
607   __IO uint32_t BKP5R;   /*!< RTC backup register 5,                                    Address offset: 0x64 */
608   __IO uint32_t BKP6R;   /*!< RTC backup register 6,                                    Address offset: 0x68 */
609   __IO uint32_t BKP7R;   /*!< RTC backup register 7,                                    Address offset: 0x6C */
610   __IO uint32_t BKP8R;   /*!< RTC backup register 8,                                    Address offset: 0x70 */
611   __IO uint32_t BKP9R;   /*!< RTC backup register 9,                                    Address offset: 0x74 */
612   __IO uint32_t BKP10R;  /*!< RTC backup register 10,                                   Address offset: 0x78 */
613   __IO uint32_t BKP11R;  /*!< RTC backup register 11,                                   Address offset: 0x7C */
614   __IO uint32_t BKP12R;  /*!< RTC backup register 12,                                   Address offset: 0x80 */
615   __IO uint32_t BKP13R;  /*!< RTC backup register 13,                                   Address offset: 0x84 */
616   __IO uint32_t BKP14R;  /*!< RTC backup register 14,                                   Address offset: 0x88 */
617   __IO uint32_t BKP15R;  /*!< RTC backup register 15,                                   Address offset: 0x8C */
618   __IO uint32_t BKP16R;  /*!< RTC backup register 16,                                   Address offset: 0x90 */
619   __IO uint32_t BKP17R;  /*!< RTC backup register 17,                                   Address offset: 0x94 */
620   __IO uint32_t BKP18R;  /*!< RTC backup register 18,                                   Address offset: 0x98 */
621   __IO uint32_t BKP19R;  /*!< RTC backup register 19,                                   Address offset: 0x9C */
622 } RTC_TypeDef;
623 
624 /**
625   * @brief Serial Audio Interface
626   */
627 
628 typedef struct
629 {
630   __IO uint32_t GCR;      /*!< SAI global configuration register,        Address offset: 0x00 */
631 } SAI_TypeDef;
632 
633 typedef struct
634 {
635   __IO uint32_t CR1;      /*!< SAI block x configuration register 1,     Address offset: 0x04 */
636   __IO uint32_t CR2;      /*!< SAI block x configuration register 2,     Address offset: 0x08 */
637   __IO uint32_t FRCR;     /*!< SAI block x frame configuration register, Address offset: 0x0C */
638   __IO uint32_t SLOTR;    /*!< SAI block x slot register,                Address offset: 0x10 */
639   __IO uint32_t IMR;      /*!< SAI block x interrupt mask register,      Address offset: 0x14 */
640   __IO uint32_t SR;       /*!< SAI block x status register,              Address offset: 0x18 */
641   __IO uint32_t CLRFR;    /*!< SAI block x clear flag register,          Address offset: 0x1C */
642   __IO uint32_t DR;       /*!< SAI block x data register,                Address offset: 0x20 */
643 } SAI_Block_TypeDef;
644 
645 /**
646   * @brief SD host Interface
647   */
648 
649 typedef struct
650 {
651   __IO uint32_t POWER;                 /*!< SDIO power control register,    Address offset: 0x00 */
652   __IO uint32_t CLKCR;                 /*!< SDI clock control register,     Address offset: 0x04 */
653   __IO uint32_t ARG;                   /*!< SDIO argument register,         Address offset: 0x08 */
654   __IO uint32_t CMD;                   /*!< SDIO command register,          Address offset: 0x0C */
655   __IO const uint32_t  RESPCMD;        /*!< SDIO command response register, Address offset: 0x10 */
656   __IO const uint32_t  RESP1;          /*!< SDIO response 1 register,       Address offset: 0x14 */
657   __IO const uint32_t  RESP2;          /*!< SDIO response 2 register,       Address offset: 0x18 */
658   __IO const uint32_t  RESP3;          /*!< SDIO response 3 register,       Address offset: 0x1C */
659   __IO const uint32_t  RESP4;          /*!< SDIO response 4 register,       Address offset: 0x20 */
660   __IO uint32_t DTIMER;                /*!< SDIO data timer register,       Address offset: 0x24 */
661   __IO uint32_t DLEN;                  /*!< SDIO data length register,      Address offset: 0x28 */
662   __IO uint32_t DCTRL;                 /*!< SDIO data control register,     Address offset: 0x2C */
663   __IO const uint32_t  DCOUNT;         /*!< SDIO data counter register,     Address offset: 0x30 */
664   __IO const uint32_t  STA;            /*!< SDIO status register,           Address offset: 0x34 */
665   __IO uint32_t ICR;                   /*!< SDIO interrupt clear register,  Address offset: 0x38 */
666   __IO uint32_t MASK;                  /*!< SDIO mask register,             Address offset: 0x3C */
667   uint32_t      RESERVED0[2];          /*!< Reserved, 0x40-0x44                                  */
668   __IO const uint32_t  FIFOCNT;        /*!< SDIO FIFO counter register,     Address offset: 0x48 */
669   uint32_t      RESERVED1[13];         /*!< Reserved, 0x4C-0x7C                                  */
670   __IO uint32_t FIFO;                  /*!< SDIO data FIFO register,        Address offset: 0x80 */
671 } SDIO_TypeDef;
672 
673 /**
674   * @brief Serial Peripheral Interface
675   */
676 
677 typedef struct
678 {
679   __IO uint32_t CR1;        /*!< SPI control register 1 (not used in I2S mode),      Address offset: 0x00 */
680   __IO uint32_t CR2;        /*!< SPI control register 2,                             Address offset: 0x04 */
681   __IO uint32_t SR;         /*!< SPI status register,                                Address offset: 0x08 */
682   __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
683   __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
684   __IO uint32_t RXCRCR;     /*!< SPI RX CRC register (not used in I2S mode),         Address offset: 0x14 */
685   __IO uint32_t TXCRCR;     /*!< SPI TX CRC register (not used in I2S mode),         Address offset: 0x18 */
686   __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
687   __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
688 } SPI_TypeDef;
689 
690 /**
691   * @brief QUAD Serial Peripheral Interface
692   */
693 
694 typedef struct
695 {
696   __IO uint32_t CR;       /*!< QUADSPI Control register,                           Address offset: 0x00 */
697   __IO uint32_t DCR;      /*!< QUADSPI Device Configuration register,              Address offset: 0x04 */
698   __IO uint32_t SR;       /*!< QUADSPI Status register,                            Address offset: 0x08 */
699   __IO uint32_t FCR;      /*!< QUADSPI Flag Clear register,                        Address offset: 0x0C */
700   __IO uint32_t DLR;      /*!< QUADSPI Data Length register,                       Address offset: 0x10 */
701   __IO uint32_t CCR;      /*!< QUADSPI Communication Configuration register,       Address offset: 0x14 */
702   __IO uint32_t AR;       /*!< QUADSPI Address register,                           Address offset: 0x18 */
703   __IO uint32_t ABR;      /*!< QUADSPI Alternate Bytes register,                   Address offset: 0x1C */
704   __IO uint32_t DR;       /*!< QUADSPI Data register,                              Address offset: 0x20 */
705   __IO uint32_t PSMKR;    /*!< QUADSPI Polling Status Mask register,               Address offset: 0x24 */
706   __IO uint32_t PSMAR;    /*!< QUADSPI Polling Status Match register,              Address offset: 0x28 */
707   __IO uint32_t PIR;      /*!< QUADSPI Polling Interval register,                  Address offset: 0x2C */
708   __IO uint32_t LPTR;     /*!< QUADSPI Low Power Timeout register,                 Address offset: 0x30 */
709 } QUADSPI_TypeDef;
710 
711 /**
712   * @brief TIM
713   */
714 
715 typedef struct
716 {
717   __IO uint32_t CR1;         /*!< TIM control register 1,              Address offset: 0x00 */
718   __IO uint32_t CR2;         /*!< TIM control register 2,              Address offset: 0x04 */
719   __IO uint32_t SMCR;        /*!< TIM slave mode control register,     Address offset: 0x08 */
720   __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
721   __IO uint32_t SR;          /*!< TIM status register,                 Address offset: 0x10 */
722   __IO uint32_t EGR;         /*!< TIM event generation register,       Address offset: 0x14 */
723   __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
724   __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
725   __IO uint32_t CCER;        /*!< TIM capture/compare enable register, Address offset: 0x20 */
726   __IO uint32_t CNT;         /*!< TIM counter register,                Address offset: 0x24 */
727   __IO uint32_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */
728   __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */
729   __IO uint32_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */
730   __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */
731   __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */
732   __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */
733   __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */
734   __IO uint32_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */
735   __IO uint32_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */
736   __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
737   __IO uint32_t OR;          /*!< TIM option register,                 Address offset: 0x50 */
738 } TIM_TypeDef;
739 
740 /**
741   * @brief Universal Synchronous Asynchronous Receiver Transmitter
742   */
743 
744 typedef struct
745 {
746   __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
747   __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
748   __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
749   __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
750   __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
751   __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
752   __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
753 } USART_TypeDef;
754 
755 /**
756   * @brief Window WATCHDOG
757   */
758 
759 typedef struct
760 {
761   __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
762   __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
763   __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
764 } WWDG_TypeDef;
765 
766 /**
767   * @brief RNG
768   */
769 
770 typedef struct
771 {
772   __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
773   __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
774   __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
775 } RNG_TypeDef;
776 
777 /**
778   * @brief USB_OTG_Core_Registers
779   */
780 typedef struct
781 {
782   __IO uint32_t GOTGCTL;              /*!< USB_OTG Control and Status Register          000h */
783   __IO uint32_t GOTGINT;              /*!< USB_OTG Interrupt Register                   004h */
784   __IO uint32_t GAHBCFG;              /*!< Core AHB Configuration Register              008h */
785   __IO uint32_t GUSBCFG;              /*!< Core USB Configuration Register              00Ch */
786   __IO uint32_t GRSTCTL;              /*!< Core Reset Register                          010h */
787   __IO uint32_t GINTSTS;              /*!< Core Interrupt Register                      014h */
788   __IO uint32_t GINTMSK;              /*!< Core Interrupt Mask Register                 018h */
789   __IO uint32_t GRXSTSR;              /*!< Receive Sts Q Read Register                  01Ch */
790   __IO uint32_t GRXSTSP;              /*!< Receive Sts Q Read & POP Register            020h */
791   __IO uint32_t GRXFSIZ;              /*!< Receive FIFO Size Register                   024h */
792   __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!< EP0 / Non Periodic Tx FIFO Size Register     028h */
793   __IO uint32_t HNPTXSTS;             /*!< Non Periodic Tx FIFO/Queue Sts reg           02Ch */
794   uint32_t Reserved30[2];             /*!< Reserved                                     030h */
795   __IO uint32_t GCCFG;                /*!< General Purpose IO Register                  038h */
796   __IO uint32_t CID;                  /*!< User ID Register                             03Ch */
797   uint32_t  Reserved5[3];             /*!< Reserved                                040h-048h */
798   __IO uint32_t GHWCFG3;              /*!< User HW config3                              04Ch */
799   uint32_t  Reserved6;                /*!< Reserved                                     050h */
800   __IO uint32_t GLPMCFG;              /*!< LPM Register                                 054h */
801   uint32_t  Reserved;                 /*!< Reserved                                     058h */
802   __IO uint32_t GDFIFOCFG;            /*!< DFIFO Software Config Register               05Ch */
803   uint32_t  Reserved43[40];           /*!< Reserved                                058h-0FFh */
804   __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg               100h */
805   __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO                        */
806 } USB_OTG_GlobalTypeDef;
807 
808 /**
809   * @brief USB_OTG_device_Registers
810   */
811 typedef struct
812 {
813   __IO uint32_t DCFG;            /*!< dev Configuration Register   800h */
814   __IO uint32_t DCTL;            /*!< dev Control Register         804h */
815   __IO uint32_t DSTS;            /*!< dev Status Register (RO)     808h */
816   uint32_t Reserved0C;           /*!< Reserved                     80Ch */
817   __IO uint32_t DIEPMSK;         /*!< dev IN Endpoint Mask         810h */
818   __IO uint32_t DOEPMSK;         /*!< dev OUT Endpoint Mask        814h */
819   __IO uint32_t DAINT;           /*!< dev All Endpoints Itr Reg    818h */
820   __IO uint32_t DAINTMSK;        /*!< dev All Endpoints Itr Mask   81Ch */
821   uint32_t  Reserved20;          /*!< Reserved                     820h */
822   uint32_t Reserved9;            /*!< Reserved                     824h */
823   __IO uint32_t DVBUSDIS;        /*!< dev VBUS discharge Register  828h */
824   __IO uint32_t DVBUSPULSE;      /*!< dev VBUS Pulse Register      82Ch */
825   __IO uint32_t DTHRCTL;         /*!< dev threshold                830h */
826   __IO uint32_t DIEPEMPMSK;      /*!< dev empty msk                834h */
827   __IO uint32_t DEACHINT;        /*!< dedicated EP interrupt       838h */
828   __IO uint32_t DEACHMSK;        /*!< dedicated EP msk             83Ch */
829   uint32_t Reserved40;           /*!< dedicated EP mask            840h */
830   __IO uint32_t DINEP1MSK;       /*!< dedicated EP mask            844h */
831   uint32_t  Reserved44[15];      /*!< Reserved                 844-87Ch */
832   __IO uint32_t DOUTEP1MSK;      /*!< dedicated EP msk             884h */
833 } USB_OTG_DeviceTypeDef;
834 
835 /**
836   * @brief USB_OTG_IN_Endpoint-Specific_Register
837   */
838 typedef struct
839 {
840   __IO uint32_t DIEPCTL;           /*!< dev IN Endpoint Control Reg    900h + (ep_num * 20h) + 00h */
841   uint32_t Reserved04;             /*!< Reserved                       900h + (ep_num * 20h) + 04h */
842   __IO uint32_t DIEPINT;           /*!< dev IN Endpoint Itr Reg        900h + (ep_num * 20h) + 08h */
843   uint32_t Reserved0C;             /*!< Reserved                       900h + (ep_num * 20h) + 0Ch */
844   __IO uint32_t DIEPTSIZ;          /*!< IN Endpoint Txfer Size         900h + (ep_num * 20h) + 10h */
845   __IO uint32_t DIEPDMA;           /*!< IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h */
846   __IO uint32_t DTXFSTS;           /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
847   uint32_t Reserved18;             /*!< Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
848 } USB_OTG_INEndpointTypeDef;
849 
850 /**
851   * @brief USB_OTG_OUT_Endpoint-Specific_Registers
852   */
853 typedef struct
854 {
855   __IO uint32_t DOEPCTL;       /*!< dev OUT Endpoint Control Reg           B00h + (ep_num * 20h) + 00h */
856   uint32_t Reserved04;         /*!< Reserved                               B00h + (ep_num * 20h) + 04h */
857   __IO uint32_t DOEPINT;       /*!< dev OUT Endpoint Itr Reg               B00h + (ep_num * 20h) + 08h */
858   uint32_t Reserved0C;         /*!< Reserved                               B00h + (ep_num * 20h) + 0Ch */
859   __IO uint32_t DOEPTSIZ;      /*!< dev OUT Endpoint Txfer Size            B00h + (ep_num * 20h) + 10h */
860   __IO uint32_t DOEPDMA;       /*!< dev OUT Endpoint DMA Address           B00h + (ep_num * 20h) + 14h */
861   uint32_t Reserved18[2];      /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
862 } USB_OTG_OUTEndpointTypeDef;
863 
864 /**
865   * @brief USB_OTG_Host_Mode_Register_Structures
866   */
867 typedef struct
868 {
869   __IO uint32_t HCFG;             /*!< Host Configuration Register          400h */
870   __IO uint32_t HFIR;             /*!< Host Frame Interval Register         404h */
871   __IO uint32_t HFNUM;            /*!< Host Frame Nbr/Frame Remaining       408h */
872   uint32_t Reserved40C;           /*!< Reserved                             40Ch */
873   __IO uint32_t HPTXSTS;          /*!< Host Periodic Tx FIFO/ Queue Status  410h */
874   __IO uint32_t HAINT;            /*!< Host All Channels Interrupt Register 414h */
875   __IO uint32_t HAINTMSK;         /*!< Host All Channels Interrupt Mask     418h */
876 } USB_OTG_HostTypeDef;
877 
878 /**
879   * @brief USB_OTG_Host_Channel_Specific_Registers
880   */
881 typedef struct
882 {
883   __IO uint32_t HCCHAR;           /*!< Host Channel Characteristics Register    500h */
884   __IO uint32_t HCSPLT;           /*!< Host Channel Split Control Register      504h */
885   __IO uint32_t HCINT;            /*!< Host Channel Interrupt Register          508h */
886   __IO uint32_t HCINTMSK;         /*!< Host Channel Interrupt Mask Register     50Ch */
887   __IO uint32_t HCTSIZ;           /*!< Host Channel Transfer Size Register      510h */
888   __IO uint32_t HCDMA;            /*!< Host Channel DMA Address Register        514h */
889   uint32_t Reserved[2];           /*!< Reserved                                      */
890 } USB_OTG_HostChannelTypeDef;
891 
892 /**
893   * @brief LPTIMER
894   */
895 typedef struct
896 {
897   __IO uint32_t ISR;         /*!< LPTIM Interrupt and Status register,                Address offset: 0x00 */
898   __IO uint32_t ICR;         /*!< LPTIM Interrupt Clear register,                     Address offset: 0x04 */
899   __IO uint32_t IER;         /*!< LPTIM Interrupt Enable register,                    Address offset: 0x08 */
900   __IO uint32_t CFGR;        /*!< LPTIM Configuration register,                       Address offset: 0x0C */
901   __IO uint32_t CR;          /*!< LPTIM Control register,                             Address offset: 0x10 */
902   __IO uint32_t CMP;         /*!< LPTIM Compare register,                             Address offset: 0x14 */
903   __IO uint32_t ARR;         /*!< LPTIM Autoreload register,                          Address offset: 0x18 */
904   __IO uint32_t CNT;         /*!< LPTIM Counter register,                             Address offset: 0x1C */
905   __IO uint32_t OR;          /*!< LPTIM Option register,                              Address offset: 0x20 */
906 } LPTIM_TypeDef;
907 
908 /**
909   * @}
910   */
911 
912 /** @addtogroup Peripheral_memory_map
913   * @{
914   */
915 #define FLASH_BASE            0x08000000UL /*!< FLASH (up to 1.5 MB) base address in the alias region                      */
916 #define SRAM1_BASE            0x20000000UL /*!< SRAM1(256 KB) base address in the alias region                             */
917 #define SRAM2_BASE            0x20040000UL /*!< SRAM2(64 KB) base address in the alias region                              */
918 #define PERIPH_BASE           0x40000000UL /*!< Peripheral base address in the alias region                                */
919 #define FSMC_R_BASE           0xA0000000UL /*!< FSMC registers base address                                                */
920 #define QSPI_R_BASE           0xA0001000UL /*!< QuadSPI registers base address                                             */
921 #define SRAM1_BB_BASE         0x22000000UL /*!< SRAM1(256 KB) base address in the bit-band region                          */
922 #define SRAM2_BB_BASE         0x22800000UL /*!< SRAM2(64 KB) base address in the bit-band region                           */
923 #define PERIPH_BB_BASE        0x42000000UL /*!< Peripheral base address in the bit-band region                             */
924 #define FLASH_END             0x0817FFFFUL /*!< FLASH end address                                                          */
925 #define FLASH_OTP_BASE        0x1FFF7800UL /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area                */
926 #define FLASH_OTP_END         0x1FFF7A0FUL /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area                 */
927 
928 /* Legacy defines */
929 #define SRAM_BASE             SRAM1_BASE
930 #define SRAM_BB_BASE          SRAM1_BB_BASE
931 
932 /*!< Peripheral memory map */
933 #define APB1PERIPH_BASE       PERIPH_BASE
934 #define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)
935 #define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)
936 #define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000UL)
937 
938 /*!< APB1 peripherals */
939 #define TIM2_BASE             (APB1PERIPH_BASE + 0x0000UL)
940 #define TIM3_BASE             (APB1PERIPH_BASE + 0x0400UL)
941 #define TIM4_BASE             (APB1PERIPH_BASE + 0x0800UL)
942 #define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00UL)
943 #define TIM6_BASE             (APB1PERIPH_BASE + 0x1000UL)
944 #define TIM7_BASE             (APB1PERIPH_BASE + 0x1400UL)
945 #define TIM12_BASE            (APB1PERIPH_BASE + 0x1800UL)
946 #define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00UL)
947 #define TIM14_BASE            (APB1PERIPH_BASE + 0x2000UL)
948 #define LPTIM1_BASE           (APB1PERIPH_BASE + 0x2400UL)
949 #define RTC_BASE              (APB1PERIPH_BASE + 0x2800UL)
950 #define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00UL)
951 #define IWDG_BASE             (APB1PERIPH_BASE + 0x3000UL)
952 #define I2S2ext_BASE          (APB1PERIPH_BASE + 0x3400UL)
953 #define SPI2_BASE             (APB1PERIPH_BASE + 0x3800UL)
954 #define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00UL)
955 #define I2S3ext_BASE          (APB1PERIPH_BASE + 0x4000UL)
956 #define USART2_BASE           (APB1PERIPH_BASE + 0x4400UL)
957 #define USART3_BASE           (APB1PERIPH_BASE + 0x4800UL)
958 #define UART4_BASE            (APB1PERIPH_BASE + 0x4C00UL)
959 #define UART5_BASE            (APB1PERIPH_BASE + 0x5000UL)
960 #define I2C1_BASE             (APB1PERIPH_BASE + 0x5400UL)
961 #define I2C2_BASE             (APB1PERIPH_BASE + 0x5800UL)
962 #define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00UL)
963 #define FMPI2C1_BASE          (APB1PERIPH_BASE + 0x6000UL)
964 #define CAN1_BASE             (APB1PERIPH_BASE + 0x6400UL)
965 #define CAN2_BASE             (APB1PERIPH_BASE + 0x6800UL)
966 #define CAN3_BASE             (APB1PERIPH_BASE + 0x6C00UL)
967 #define PWR_BASE              (APB1PERIPH_BASE + 0x7000UL)
968 #define DAC_BASE              (APB1PERIPH_BASE + 0x7400UL)
969 #define UART7_BASE            (APB1PERIPH_BASE + 0x7800UL)
970 #define UART8_BASE            (APB1PERIPH_BASE + 0x7C00UL)
971 
972 /*!< APB2 peripherals */
973 #define TIM1_BASE             (APB2PERIPH_BASE + 0x0000UL)
974 #define TIM8_BASE             (APB2PERIPH_BASE + 0x0400UL)
975 #define USART1_BASE           (APB2PERIPH_BASE + 0x1000UL)
976 #define USART6_BASE           (APB2PERIPH_BASE + 0x1400UL)
977 #define UART9_BASE            (APB2PERIPH_BASE + 0x1800UL)
978 #define UART10_BASE           (APB2PERIPH_BASE + 0x1C00UL)
979 #define ADC1_BASE             (APB2PERIPH_BASE + 0x2000UL)
980 #define ADC1_COMMON_BASE      (APB2PERIPH_BASE + 0x2300UL)
981 /* Legacy define */
982 #define ADC_BASE               ADC1_COMMON_BASE
983 #define SDIO_BASE             (APB2PERIPH_BASE + 0x2C00UL)
984 #define SPI1_BASE             (APB2PERIPH_BASE + 0x3000UL)
985 #define SPI4_BASE             (APB2PERIPH_BASE + 0x3400UL)
986 #define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800UL)
987 #define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00UL)
988 #define TIM9_BASE             (APB2PERIPH_BASE + 0x4000UL)
989 #define TIM10_BASE            (APB2PERIPH_BASE + 0x4400UL)
990 #define TIM11_BASE            (APB2PERIPH_BASE + 0x4800UL)
991 #define SPI5_BASE             (APB2PERIPH_BASE + 0x5000UL)
992 #define DFSDM1_BASE           (APB2PERIPH_BASE + 0x6000UL)
993 #define DFSDM2_BASE           (APB2PERIPH_BASE + 0x6400UL)
994 #define DFSDM1_Channel0_BASE  (DFSDM1_BASE + 0x00UL)
995 #define DFSDM1_Channel1_BASE  (DFSDM1_BASE + 0x20UL)
996 #define DFSDM1_Channel2_BASE  (DFSDM1_BASE + 0x40UL)
997 #define DFSDM1_Channel3_BASE  (DFSDM1_BASE + 0x60UL)
998 #define DFSDM1_Filter0_BASE   (DFSDM1_BASE + 0x100UL)
999 #define DFSDM1_Filter1_BASE   (DFSDM1_BASE + 0x180UL)
1000 #define DFSDM2_Channel0_BASE  (DFSDM2_BASE + 0x00UL)
1001 #define DFSDM2_Channel1_BASE  (DFSDM2_BASE + 0x20UL)
1002 #define DFSDM2_Channel2_BASE  (DFSDM2_BASE + 0x40UL)
1003 #define DFSDM2_Channel3_BASE  (DFSDM2_BASE + 0x60UL)
1004 #define DFSDM2_Channel4_BASE  (DFSDM2_BASE + 0x80UL)
1005 #define DFSDM2_Channel5_BASE  (DFSDM2_BASE + 0xA0UL)
1006 #define DFSDM2_Channel6_BASE  (DFSDM2_BASE + 0xC0UL)
1007 #define DFSDM2_Channel7_BASE  (DFSDM2_BASE + 0xE0UL)
1008 #define DFSDM2_Filter0_BASE   (DFSDM2_BASE + 0x100UL)
1009 #define DFSDM2_Filter1_BASE   (DFSDM2_BASE + 0x180UL)
1010 #define DFSDM2_Filter2_BASE   (DFSDM2_BASE + 0x200UL)
1011 #define DFSDM2_Filter3_BASE   (DFSDM2_BASE + 0x280UL)
1012 #define SAI1_BASE             (APB2PERIPH_BASE + 0x5800UL)
1013 #define SAI1_Block_A_BASE     (SAI1_BASE + 0x004UL)
1014 #define SAI1_Block_B_BASE     (SAI1_BASE + 0x024UL)
1015 
1016 /*!< AHB1 peripherals */
1017 #define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000UL)
1018 #define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400UL)
1019 #define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800UL)
1020 #define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00UL)
1021 #define GPIOE_BASE            (AHB1PERIPH_BASE + 0x1000UL)
1022 #define GPIOF_BASE            (AHB1PERIPH_BASE + 0x1400UL)
1023 #define GPIOG_BASE            (AHB1PERIPH_BASE + 0x1800UL)
1024 #define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00UL)
1025 #define CRC_BASE              (AHB1PERIPH_BASE + 0x3000UL)
1026 #define RCC_BASE              (AHB1PERIPH_BASE + 0x3800UL)
1027 #define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00UL)
1028 #define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000UL)
1029 #define DMA1_Stream0_BASE     (DMA1_BASE + 0x010UL)
1030 #define DMA1_Stream1_BASE     (DMA1_BASE + 0x028UL)
1031 #define DMA1_Stream2_BASE     (DMA1_BASE + 0x040UL)
1032 #define DMA1_Stream3_BASE     (DMA1_BASE + 0x058UL)
1033 #define DMA1_Stream4_BASE     (DMA1_BASE + 0x070UL)
1034 #define DMA1_Stream5_BASE     (DMA1_BASE + 0x088UL)
1035 #define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0UL)
1036 #define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8UL)
1037 #define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400UL)
1038 #define DMA2_Stream0_BASE     (DMA2_BASE + 0x010UL)
1039 #define DMA2_Stream1_BASE     (DMA2_BASE + 0x028UL)
1040 #define DMA2_Stream2_BASE     (DMA2_BASE + 0x040UL)
1041 #define DMA2_Stream3_BASE     (DMA2_BASE + 0x058UL)
1042 #define DMA2_Stream4_BASE     (DMA2_BASE + 0x070UL)
1043 #define DMA2_Stream5_BASE     (DMA2_BASE + 0x088UL)
1044 #define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0UL)
1045 #define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8UL)
1046 
1047 /*!< AHB2 peripherals */
1048 #define RNG_BASE              (AHB2PERIPH_BASE + 0x60800UL)
1049 
1050 
1051 /*!< FSMC Bankx registers base address */
1052 #define FSMC_Bank1_R_BASE     (FSMC_R_BASE + 0x0000UL)
1053 #define FSMC_Bank1E_R_BASE    (FSMC_R_BASE + 0x0104UL)
1054 
1055 /*!< Debug MCU registers base address */
1056 #define DBGMCU_BASE           0xE0042000UL
1057 /*!< USB registers base address */
1058 #define USB_OTG_FS_PERIPH_BASE               0x50000000UL
1059 
1060 #define USB_OTG_GLOBAL_BASE                  0x000UL
1061 #define USB_OTG_DEVICE_BASE                  0x800UL
1062 #define USB_OTG_IN_ENDPOINT_BASE             0x900UL
1063 #define USB_OTG_OUT_ENDPOINT_BASE            0xB00UL
1064 #define USB_OTG_EP_REG_SIZE                  0x20UL
1065 #define USB_OTG_HOST_BASE                    0x400UL
1066 #define USB_OTG_HOST_PORT_BASE               0x440UL
1067 #define USB_OTG_HOST_CHANNEL_BASE            0x500UL
1068 #define USB_OTG_HOST_CHANNEL_SIZE            0x20UL
1069 #define USB_OTG_PCGCCTL_BASE                 0xE00UL
1070 #define USB_OTG_FIFO_BASE                    0x1000UL
1071 #define USB_OTG_FIFO_SIZE                    0x1000UL
1072 
1073 #define UID_BASE                     0x1FFF7A10UL           /*!< Unique device ID register base address */
1074 #define FLASHSIZE_BASE               0x1FFF7A22UL           /*!< FLASH Size register base address       */
1075 #define PACKAGE_BASE                 0x1FFF7BF0UL           /*!< Package size register base address     */
1076 /**
1077   * @}
1078   */
1079 
1080 /** @addtogroup Peripheral_declaration
1081   * @{
1082   */
1083 #define TIM2                ((TIM_TypeDef *) TIM2_BASE)
1084 #define TIM3                ((TIM_TypeDef *) TIM3_BASE)
1085 #define TIM4                ((TIM_TypeDef *) TIM4_BASE)
1086 #define TIM5                ((TIM_TypeDef *) TIM5_BASE)
1087 #define TIM6                ((TIM_TypeDef *) TIM6_BASE)
1088 #define TIM7                ((TIM_TypeDef *) TIM7_BASE)
1089 #define TIM12               ((TIM_TypeDef *) TIM12_BASE)
1090 #define TIM13               ((TIM_TypeDef *) TIM13_BASE)
1091 #define TIM14               ((TIM_TypeDef *) TIM14_BASE)
1092 #define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)
1093 #define RTC                 ((RTC_TypeDef *) RTC_BASE)
1094 #define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
1095 #define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
1096 #define I2S2ext             ((SPI_TypeDef *) I2S2ext_BASE)
1097 #define SPI2                ((SPI_TypeDef *) SPI2_BASE)
1098 #define SPI3                ((SPI_TypeDef *) SPI3_BASE)
1099 #define I2S3ext             ((SPI_TypeDef *) I2S3ext_BASE)
1100 #define USART2              ((USART_TypeDef *) USART2_BASE)
1101 #define USART3              ((USART_TypeDef *) USART3_BASE)
1102 #define UART4               ((USART_TypeDef *) UART4_BASE)
1103 #define UART5               ((USART_TypeDef *) UART5_BASE)
1104 #define I2C1                ((I2C_TypeDef *) I2C1_BASE)
1105 #define I2C2                ((I2C_TypeDef *) I2C2_BASE)
1106 #define I2C3                ((I2C_TypeDef *) I2C3_BASE)
1107 #define FMPI2C1             ((FMPI2C_TypeDef *) FMPI2C1_BASE)
1108 #define CAN1                ((CAN_TypeDef *) CAN1_BASE)
1109 #define CAN2                ((CAN_TypeDef *) CAN2_BASE)
1110 #define CAN3                ((CAN_TypeDef *) CAN3_BASE)
1111 #define PWR                 ((PWR_TypeDef *) PWR_BASE)
1112 #define DAC1                ((DAC_TypeDef *) DAC_BASE)
1113 #define DAC                 ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
1114 #define UART7               ((USART_TypeDef *) UART7_BASE)
1115 #define UART8               ((USART_TypeDef *) UART8_BASE)
1116 #define TIM1                ((TIM_TypeDef *) TIM1_BASE)
1117 #define TIM8                ((TIM_TypeDef *) TIM8_BASE)
1118 #define USART1              ((USART_TypeDef *) USART1_BASE)
1119 #define USART6              ((USART_TypeDef *) USART6_BASE)
1120 #define UART9               ((USART_TypeDef *) UART9_BASE)
1121 #define UART10              ((USART_TypeDef *) UART10_BASE)
1122 #define ADC1                ((ADC_TypeDef *) ADC1_BASE)
1123 #define ADC1_COMMON         ((ADC_Common_TypeDef *) ADC1_COMMON_BASE)
1124 /* Legacy define */
1125 #define ADC                  ADC1_COMMON
1126 #define SDIO                ((SDIO_TypeDef *) SDIO_BASE)
1127 #define SPI1                ((SPI_TypeDef *) SPI1_BASE)
1128 #define SPI4                ((SPI_TypeDef *) SPI4_BASE)
1129 #define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
1130 #define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
1131 #define TIM9                ((TIM_TypeDef *) TIM9_BASE)
1132 #define TIM10               ((TIM_TypeDef *) TIM10_BASE)
1133 #define TIM11               ((TIM_TypeDef *) TIM11_BASE)
1134 #define SPI5                ((SPI_TypeDef *) SPI5_BASE)
1135 #define DFSDM1_Channel0     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
1136 #define DFSDM1_Channel1     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
1137 #define DFSDM1_Channel2     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
1138 #define DFSDM1_Channel3     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
1139 #define DFSDM1_Filter0      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
1140 #define DFSDM1_Filter1      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
1141 #define DFSDM2_Channel0     ((DFSDM_Channel_TypeDef *) DFSDM2_Channel0_BASE)
1142 #define DFSDM2_Channel1     ((DFSDM_Channel_TypeDef *) DFSDM2_Channel1_BASE)
1143 #define DFSDM2_Channel2     ((DFSDM_Channel_TypeDef *) DFSDM2_Channel2_BASE)
1144 #define DFSDM2_Channel3     ((DFSDM_Channel_TypeDef *) DFSDM2_Channel3_BASE)
1145 #define DFSDM2_Channel4     ((DFSDM_Channel_TypeDef *) DFSDM2_Channel4_BASE)
1146 #define DFSDM2_Channel5     ((DFSDM_Channel_TypeDef *) DFSDM2_Channel5_BASE)
1147 #define DFSDM2_Channel6     ((DFSDM_Channel_TypeDef *) DFSDM2_Channel6_BASE)
1148 #define DFSDM2_Channel7     ((DFSDM_Channel_TypeDef *) DFSDM2_Channel7_BASE)
1149 #define DFSDM2_Filter0      ((DFSDM_Filter_TypeDef *) DFSDM2_Filter0_BASE)
1150 #define DFSDM2_Filter1      ((DFSDM_Filter_TypeDef *) DFSDM2_Filter1_BASE)
1151 #define DFSDM2_Filter2      ((DFSDM_Filter_TypeDef *) DFSDM2_Filter2_BASE)
1152 #define DFSDM2_Filter3      ((DFSDM_Filter_TypeDef *) DFSDM2_Filter3_BASE)
1153 #define SAI1                ((SAI_TypeDef *) SAI1_BASE)
1154 #define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
1155 #define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
1156 #define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
1157 #define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
1158 #define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
1159 #define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
1160 #define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
1161 #define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
1162 #define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
1163 #define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
1164 #define CRC                 ((CRC_TypeDef *) CRC_BASE)
1165 #define RCC                 ((RCC_TypeDef *) RCC_BASE)
1166 #define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
1167 #define DMA1                ((DMA_TypeDef *) DMA1_BASE)
1168 #define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
1169 #define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
1170 #define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
1171 #define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
1172 #define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
1173 #define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
1174 #define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
1175 #define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
1176 #define DMA2                ((DMA_TypeDef *) DMA2_BASE)
1177 #define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
1178 #define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
1179 #define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
1180 #define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
1181 #define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
1182 #define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
1183 #define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
1184 #define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
1185 #define RNG                 ((RNG_TypeDef *) RNG_BASE)
1186 #define FSMC_Bank1          ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
1187 #define FSMC_Bank1E         ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
1188 #define QUADSPI             ((QUADSPI_TypeDef *) QSPI_R_BASE)
1189 #define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
1190 #define USB_OTG_FS          ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
1191 
1192 /**
1193   * @}
1194   */
1195 
1196 /** @addtogroup Exported_constants
1197   * @{
1198   */
1199 
1200   /** @addtogroup Peripheral_Registers_Bits_Definition
1201   * @{
1202   */
1203 
1204 /******************************************************************************/
1205 /*                         Peripheral Registers_Bits_Definition               */
1206 /******************************************************************************/
1207 
1208 /******************************************************************************/
1209 /*                                                                            */
1210 /*                        Analog to Digital Converter                         */
1211 /*                                                                            */
1212 /******************************************************************************/
1213 
1214 /********************  Bit definition for ADC_SR register  ********************/
1215 #define ADC_SR_AWD_Pos            (0U)
1216 #define ADC_SR_AWD_Msk            (0x1UL << ADC_SR_AWD_Pos)                     /*!< 0x00000001 */
1217 #define ADC_SR_AWD                ADC_SR_AWD_Msk                               /*!<Analog watchdog flag */
1218 #define ADC_SR_EOC_Pos            (1U)
1219 #define ADC_SR_EOC_Msk            (0x1UL << ADC_SR_EOC_Pos)                     /*!< 0x00000002 */
1220 #define ADC_SR_EOC                ADC_SR_EOC_Msk                               /*!<End of conversion */
1221 #define ADC_SR_JEOC_Pos           (2U)
1222 #define ADC_SR_JEOC_Msk           (0x1UL << ADC_SR_JEOC_Pos)                    /*!< 0x00000004 */
1223 #define ADC_SR_JEOC               ADC_SR_JEOC_Msk                              /*!<Injected channel end of conversion */
1224 #define ADC_SR_JSTRT_Pos          (3U)
1225 #define ADC_SR_JSTRT_Msk          (0x1UL << ADC_SR_JSTRT_Pos)                   /*!< 0x00000008 */
1226 #define ADC_SR_JSTRT              ADC_SR_JSTRT_Msk                             /*!<Injected channel Start flag */
1227 #define ADC_SR_STRT_Pos           (4U)
1228 #define ADC_SR_STRT_Msk           (0x1UL << ADC_SR_STRT_Pos)                    /*!< 0x00000010 */
1229 #define ADC_SR_STRT               ADC_SR_STRT_Msk                              /*!<Regular channel Start flag */
1230 #define ADC_SR_OVR_Pos            (5U)
1231 #define ADC_SR_OVR_Msk            (0x1UL << ADC_SR_OVR_Pos)                     /*!< 0x00000020 */
1232 #define ADC_SR_OVR                ADC_SR_OVR_Msk                               /*!<Overrun flag */
1233 
1234 /*******************  Bit definition for ADC_CR1 register  ********************/
1235 #define ADC_CR1_AWDCH_Pos         (0U)
1236 #define ADC_CR1_AWDCH_Msk         (0x1FUL << ADC_CR1_AWDCH_Pos)                 /*!< 0x0000001F */
1237 #define ADC_CR1_AWDCH             ADC_CR1_AWDCH_Msk                            /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
1238 #define ADC_CR1_AWDCH_0           (0x01UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000001 */
1239 #define ADC_CR1_AWDCH_1           (0x02UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000002 */
1240 #define ADC_CR1_AWDCH_2           (0x04UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000004 */
1241 #define ADC_CR1_AWDCH_3           (0x08UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000008 */
1242 #define ADC_CR1_AWDCH_4           (0x10UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000010 */
1243 #define ADC_CR1_EOCIE_Pos         (5U)
1244 #define ADC_CR1_EOCIE_Msk         (0x1UL << ADC_CR1_EOCIE_Pos)                  /*!< 0x00000020 */
1245 #define ADC_CR1_EOCIE             ADC_CR1_EOCIE_Msk                            /*!<Interrupt enable for EOC */
1246 #define ADC_CR1_AWDIE_Pos         (6U)
1247 #define ADC_CR1_AWDIE_Msk         (0x1UL << ADC_CR1_AWDIE_Pos)                  /*!< 0x00000040 */
1248 #define ADC_CR1_AWDIE             ADC_CR1_AWDIE_Msk                            /*!<AAnalog Watchdog interrupt enable */
1249 #define ADC_CR1_JEOCIE_Pos        (7U)
1250 #define ADC_CR1_JEOCIE_Msk        (0x1UL << ADC_CR1_JEOCIE_Pos)                 /*!< 0x00000080 */
1251 #define ADC_CR1_JEOCIE            ADC_CR1_JEOCIE_Msk                           /*!<Interrupt enable for injected channels */
1252 #define ADC_CR1_SCAN_Pos          (8U)
1253 #define ADC_CR1_SCAN_Msk          (0x1UL << ADC_CR1_SCAN_Pos)                   /*!< 0x00000100 */
1254 #define ADC_CR1_SCAN              ADC_CR1_SCAN_Msk                             /*!<Scan mode */
1255 #define ADC_CR1_AWDSGL_Pos        (9U)
1256 #define ADC_CR1_AWDSGL_Msk        (0x1UL << ADC_CR1_AWDSGL_Pos)                 /*!< 0x00000200 */
1257 #define ADC_CR1_AWDSGL            ADC_CR1_AWDSGL_Msk                           /*!<Enable the watchdog on a single channel in scan mode */
1258 #define ADC_CR1_JAUTO_Pos         (10U)
1259 #define ADC_CR1_JAUTO_Msk         (0x1UL << ADC_CR1_JAUTO_Pos)                  /*!< 0x00000400 */
1260 #define ADC_CR1_JAUTO             ADC_CR1_JAUTO_Msk                            /*!<Automatic injected group conversion */
1261 #define ADC_CR1_DISCEN_Pos        (11U)
1262 #define ADC_CR1_DISCEN_Msk        (0x1UL << ADC_CR1_DISCEN_Pos)                 /*!< 0x00000800 */
1263 #define ADC_CR1_DISCEN            ADC_CR1_DISCEN_Msk                           /*!<Discontinuous mode on regular channels */
1264 #define ADC_CR1_JDISCEN_Pos       (12U)
1265 #define ADC_CR1_JDISCEN_Msk       (0x1UL << ADC_CR1_JDISCEN_Pos)                /*!< 0x00001000 */
1266 #define ADC_CR1_JDISCEN           ADC_CR1_JDISCEN_Msk                          /*!<Discontinuous mode on injected channels */
1267 #define ADC_CR1_DISCNUM_Pos       (13U)
1268 #define ADC_CR1_DISCNUM_Msk       (0x7UL << ADC_CR1_DISCNUM_Pos)                /*!< 0x0000E000 */
1269 #define ADC_CR1_DISCNUM           ADC_CR1_DISCNUM_Msk                          /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
1270 #define ADC_CR1_DISCNUM_0         (0x1UL << ADC_CR1_DISCNUM_Pos)                /*!< 0x00002000 */
1271 #define ADC_CR1_DISCNUM_1         (0x2UL << ADC_CR1_DISCNUM_Pos)                /*!< 0x00004000 */
1272 #define ADC_CR1_DISCNUM_2         (0x4UL << ADC_CR1_DISCNUM_Pos)                /*!< 0x00008000 */
1273 #define ADC_CR1_JAWDEN_Pos        (22U)
1274 #define ADC_CR1_JAWDEN_Msk        (0x1UL << ADC_CR1_JAWDEN_Pos)                 /*!< 0x00400000 */
1275 #define ADC_CR1_JAWDEN            ADC_CR1_JAWDEN_Msk                           /*!<Analog watchdog enable on injected channels */
1276 #define ADC_CR1_AWDEN_Pos         (23U)
1277 #define ADC_CR1_AWDEN_Msk         (0x1UL << ADC_CR1_AWDEN_Pos)                  /*!< 0x00800000 */
1278 #define ADC_CR1_AWDEN             ADC_CR1_AWDEN_Msk                            /*!<Analog watchdog enable on regular channels */
1279 #define ADC_CR1_RES_Pos           (24U)
1280 #define ADC_CR1_RES_Msk           (0x3UL << ADC_CR1_RES_Pos)                    /*!< 0x03000000 */
1281 #define ADC_CR1_RES               ADC_CR1_RES_Msk                              /*!<RES[2:0] bits (Resolution) */
1282 #define ADC_CR1_RES_0             (0x1UL << ADC_CR1_RES_Pos)                    /*!< 0x01000000 */
1283 #define ADC_CR1_RES_1             (0x2UL << ADC_CR1_RES_Pos)                    /*!< 0x02000000 */
1284 #define ADC_CR1_OVRIE_Pos         (26U)
1285 #define ADC_CR1_OVRIE_Msk         (0x1UL << ADC_CR1_OVRIE_Pos)                  /*!< 0x04000000 */
1286 #define ADC_CR1_OVRIE             ADC_CR1_OVRIE_Msk                            /*!<overrun interrupt enable */
1287 
1288 /*******************  Bit definition for ADC_CR2 register  ********************/
1289 #define ADC_CR2_ADON_Pos          (0U)
1290 #define ADC_CR2_ADON_Msk          (0x1UL << ADC_CR2_ADON_Pos)                   /*!< 0x00000001 */
1291 #define ADC_CR2_ADON              ADC_CR2_ADON_Msk                             /*!<A/D Converter ON / OFF */
1292 #define ADC_CR2_CONT_Pos          (1U)
1293 #define ADC_CR2_CONT_Msk          (0x1UL << ADC_CR2_CONT_Pos)                   /*!< 0x00000002 */
1294 #define ADC_CR2_CONT              ADC_CR2_CONT_Msk                             /*!<Continuous Conversion */
1295 #define ADC_CR2_DMA_Pos           (8U)
1296 #define ADC_CR2_DMA_Msk           (0x1UL << ADC_CR2_DMA_Pos)                    /*!< 0x00000100 */
1297 #define ADC_CR2_DMA               ADC_CR2_DMA_Msk                              /*!<Direct Memory access mode */
1298 #define ADC_CR2_DDS_Pos           (9U)
1299 #define ADC_CR2_DDS_Msk           (0x1UL << ADC_CR2_DDS_Pos)                    /*!< 0x00000200 */
1300 #define ADC_CR2_DDS               ADC_CR2_DDS_Msk                              /*!<DMA disable selection (Single ADC) */
1301 #define ADC_CR2_EOCS_Pos          (10U)
1302 #define ADC_CR2_EOCS_Msk          (0x1UL << ADC_CR2_EOCS_Pos)                   /*!< 0x00000400 */
1303 #define ADC_CR2_EOCS              ADC_CR2_EOCS_Msk                             /*!<End of conversion selection */
1304 #define ADC_CR2_ALIGN_Pos         (11U)
1305 #define ADC_CR2_ALIGN_Msk         (0x1UL << ADC_CR2_ALIGN_Pos)                  /*!< 0x00000800 */
1306 #define ADC_CR2_ALIGN             ADC_CR2_ALIGN_Msk                            /*!<Data Alignment */
1307 #define ADC_CR2_JEXTSEL_Pos       (16U)
1308 #define ADC_CR2_JEXTSEL_Msk       (0xFUL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x000F0000 */
1309 #define ADC_CR2_JEXTSEL           ADC_CR2_JEXTSEL_Msk                          /*!<JEXTSEL[3:0] bits (External event select for injected group) */
1310 #define ADC_CR2_JEXTSEL_0         (0x1UL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00010000 */
1311 #define ADC_CR2_JEXTSEL_1         (0x2UL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00020000 */
1312 #define ADC_CR2_JEXTSEL_2         (0x4UL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00040000 */
1313 #define ADC_CR2_JEXTSEL_3         (0x8UL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00080000 */
1314 #define ADC_CR2_JEXTEN_Pos        (20U)
1315 #define ADC_CR2_JEXTEN_Msk        (0x3UL << ADC_CR2_JEXTEN_Pos)                 /*!< 0x00300000 */
1316 #define ADC_CR2_JEXTEN            ADC_CR2_JEXTEN_Msk                           /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
1317 #define ADC_CR2_JEXTEN_0          (0x1UL << ADC_CR2_JEXTEN_Pos)                 /*!< 0x00100000 */
1318 #define ADC_CR2_JEXTEN_1          (0x2UL << ADC_CR2_JEXTEN_Pos)                 /*!< 0x00200000 */
1319 #define ADC_CR2_JSWSTART_Pos      (22U)
1320 #define ADC_CR2_JSWSTART_Msk      (0x1UL << ADC_CR2_JSWSTART_Pos)               /*!< 0x00400000 */
1321 #define ADC_CR2_JSWSTART          ADC_CR2_JSWSTART_Msk                         /*!<Start Conversion of injected channels */
1322 #define ADC_CR2_EXTSEL_Pos        (24U)
1323 #define ADC_CR2_EXTSEL_Msk        (0xFUL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x0F000000 */
1324 #define ADC_CR2_EXTSEL            ADC_CR2_EXTSEL_Msk                           /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
1325 #define ADC_CR2_EXTSEL_0          (0x1UL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x01000000 */
1326 #define ADC_CR2_EXTSEL_1          (0x2UL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x02000000 */
1327 #define ADC_CR2_EXTSEL_2          (0x4UL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x04000000 */
1328 #define ADC_CR2_EXTSEL_3          (0x8UL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x08000000 */
1329 #define ADC_CR2_EXTEN_Pos         (28U)
1330 #define ADC_CR2_EXTEN_Msk         (0x3UL << ADC_CR2_EXTEN_Pos)                  /*!< 0x30000000 */
1331 #define ADC_CR2_EXTEN             ADC_CR2_EXTEN_Msk                            /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
1332 #define ADC_CR2_EXTEN_0           (0x1UL << ADC_CR2_EXTEN_Pos)                  /*!< 0x10000000 */
1333 #define ADC_CR2_EXTEN_1           (0x2UL << ADC_CR2_EXTEN_Pos)                  /*!< 0x20000000 */
1334 #define ADC_CR2_SWSTART_Pos       (30U)
1335 #define ADC_CR2_SWSTART_Msk       (0x1UL << ADC_CR2_SWSTART_Pos)                /*!< 0x40000000 */
1336 #define ADC_CR2_SWSTART           ADC_CR2_SWSTART_Msk                          /*!<Start Conversion of regular channels */
1337 
1338 /******************  Bit definition for ADC_SMPR1 register  *******************/
1339 #define ADC_SMPR1_SMP10_Pos       (0U)
1340 #define ADC_SMPR1_SMP10_Msk       (0x7UL << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000007 */
1341 #define ADC_SMPR1_SMP10           ADC_SMPR1_SMP10_Msk                          /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
1342 #define ADC_SMPR1_SMP10_0         (0x1UL << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000001 */
1343 #define ADC_SMPR1_SMP10_1         (0x2UL << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000002 */
1344 #define ADC_SMPR1_SMP10_2         (0x4UL << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000004 */
1345 #define ADC_SMPR1_SMP11_Pos       (3U)
1346 #define ADC_SMPR1_SMP11_Msk       (0x7UL << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000038 */
1347 #define ADC_SMPR1_SMP11           ADC_SMPR1_SMP11_Msk                          /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
1348 #define ADC_SMPR1_SMP11_0         (0x1UL << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000008 */
1349 #define ADC_SMPR1_SMP11_1         (0x2UL << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000010 */
1350 #define ADC_SMPR1_SMP11_2         (0x4UL << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000020 */
1351 #define ADC_SMPR1_SMP12_Pos       (6U)
1352 #define ADC_SMPR1_SMP12_Msk       (0x7UL << ADC_SMPR1_SMP12_Pos)                /*!< 0x000001C0 */
1353 #define ADC_SMPR1_SMP12           ADC_SMPR1_SMP12_Msk                          /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
1354 #define ADC_SMPR1_SMP12_0         (0x1UL << ADC_SMPR1_SMP12_Pos)                /*!< 0x00000040 */
1355 #define ADC_SMPR1_SMP12_1         (0x2UL << ADC_SMPR1_SMP12_Pos)                /*!< 0x00000080 */
1356 #define ADC_SMPR1_SMP12_2         (0x4UL << ADC_SMPR1_SMP12_Pos)                /*!< 0x00000100 */
1357 #define ADC_SMPR1_SMP13_Pos       (9U)
1358 #define ADC_SMPR1_SMP13_Msk       (0x7UL << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000E00 */
1359 #define ADC_SMPR1_SMP13           ADC_SMPR1_SMP13_Msk                          /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
1360 #define ADC_SMPR1_SMP13_0         (0x1UL << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000200 */
1361 #define ADC_SMPR1_SMP13_1         (0x2UL << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000400 */
1362 #define ADC_SMPR1_SMP13_2         (0x4UL << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000800 */
1363 #define ADC_SMPR1_SMP14_Pos       (12U)
1364 #define ADC_SMPR1_SMP14_Msk       (0x7UL << ADC_SMPR1_SMP14_Pos)                /*!< 0x00007000 */
1365 #define ADC_SMPR1_SMP14           ADC_SMPR1_SMP14_Msk                          /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
1366 #define ADC_SMPR1_SMP14_0         (0x1UL << ADC_SMPR1_SMP14_Pos)                /*!< 0x00001000 */
1367 #define ADC_SMPR1_SMP14_1         (0x2UL << ADC_SMPR1_SMP14_Pos)                /*!< 0x00002000 */
1368 #define ADC_SMPR1_SMP14_2         (0x4UL << ADC_SMPR1_SMP14_Pos)                /*!< 0x00004000 */
1369 #define ADC_SMPR1_SMP15_Pos       (15U)
1370 #define ADC_SMPR1_SMP15_Msk       (0x7UL << ADC_SMPR1_SMP15_Pos)                /*!< 0x00038000 */
1371 #define ADC_SMPR1_SMP15           ADC_SMPR1_SMP15_Msk                          /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
1372 #define ADC_SMPR1_SMP15_0         (0x1UL << ADC_SMPR1_SMP15_Pos)                /*!< 0x00008000 */
1373 #define ADC_SMPR1_SMP15_1         (0x2UL << ADC_SMPR1_SMP15_Pos)                /*!< 0x00010000 */
1374 #define ADC_SMPR1_SMP15_2         (0x4UL << ADC_SMPR1_SMP15_Pos)                /*!< 0x00020000 */
1375 #define ADC_SMPR1_SMP16_Pos       (18U)
1376 #define ADC_SMPR1_SMP16_Msk       (0x7UL << ADC_SMPR1_SMP16_Pos)                /*!< 0x001C0000 */
1377 #define ADC_SMPR1_SMP16           ADC_SMPR1_SMP16_Msk                          /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
1378 #define ADC_SMPR1_SMP16_0         (0x1UL << ADC_SMPR1_SMP16_Pos)                /*!< 0x00040000 */
1379 #define ADC_SMPR1_SMP16_1         (0x2UL << ADC_SMPR1_SMP16_Pos)                /*!< 0x00080000 */
1380 #define ADC_SMPR1_SMP16_2         (0x4UL << ADC_SMPR1_SMP16_Pos)                /*!< 0x00100000 */
1381 #define ADC_SMPR1_SMP17_Pos       (21U)
1382 #define ADC_SMPR1_SMP17_Msk       (0x7UL << ADC_SMPR1_SMP17_Pos)                /*!< 0x00E00000 */
1383 #define ADC_SMPR1_SMP17           ADC_SMPR1_SMP17_Msk                          /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
1384 #define ADC_SMPR1_SMP17_0         (0x1UL << ADC_SMPR1_SMP17_Pos)                /*!< 0x00200000 */
1385 #define ADC_SMPR1_SMP17_1         (0x2UL << ADC_SMPR1_SMP17_Pos)                /*!< 0x00400000 */
1386 #define ADC_SMPR1_SMP17_2         (0x4UL << ADC_SMPR1_SMP17_Pos)                /*!< 0x00800000 */
1387 #define ADC_SMPR1_SMP18_Pos       (24U)
1388 #define ADC_SMPR1_SMP18_Msk       (0x7UL << ADC_SMPR1_SMP18_Pos)                /*!< 0x07000000 */
1389 #define ADC_SMPR1_SMP18           ADC_SMPR1_SMP18_Msk                          /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
1390 #define ADC_SMPR1_SMP18_0         (0x1UL << ADC_SMPR1_SMP18_Pos)                /*!< 0x01000000 */
1391 #define ADC_SMPR1_SMP18_1         (0x2UL << ADC_SMPR1_SMP18_Pos)                /*!< 0x02000000 */
1392 #define ADC_SMPR1_SMP18_2         (0x4UL << ADC_SMPR1_SMP18_Pos)                /*!< 0x04000000 */
1393 
1394 /******************  Bit definition for ADC_SMPR2 register  *******************/
1395 #define ADC_SMPR2_SMP0_Pos        (0U)
1396 #define ADC_SMPR2_SMP0_Msk        (0x7UL << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000007 */
1397 #define ADC_SMPR2_SMP0            ADC_SMPR2_SMP0_Msk                           /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
1398 #define ADC_SMPR2_SMP0_0          (0x1UL << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000001 */
1399 #define ADC_SMPR2_SMP0_1          (0x2UL << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000002 */
1400 #define ADC_SMPR2_SMP0_2          (0x4UL << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000004 */
1401 #define ADC_SMPR2_SMP1_Pos        (3U)
1402 #define ADC_SMPR2_SMP1_Msk        (0x7UL << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000038 */
1403 #define ADC_SMPR2_SMP1            ADC_SMPR2_SMP1_Msk                           /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
1404 #define ADC_SMPR2_SMP1_0          (0x1UL << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000008 */
1405 #define ADC_SMPR2_SMP1_1          (0x2UL << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000010 */
1406 #define ADC_SMPR2_SMP1_2          (0x4UL << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000020 */
1407 #define ADC_SMPR2_SMP2_Pos        (6U)
1408 #define ADC_SMPR2_SMP2_Msk        (0x7UL << ADC_SMPR2_SMP2_Pos)                 /*!< 0x000001C0 */
1409 #define ADC_SMPR2_SMP2            ADC_SMPR2_SMP2_Msk                           /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
1410 #define ADC_SMPR2_SMP2_0          (0x1UL << ADC_SMPR2_SMP2_Pos)                 /*!< 0x00000040 */
1411 #define ADC_SMPR2_SMP2_1          (0x2UL << ADC_SMPR2_SMP2_Pos)                 /*!< 0x00000080 */
1412 #define ADC_SMPR2_SMP2_2          (0x4UL << ADC_SMPR2_SMP2_Pos)                 /*!< 0x00000100 */
1413 #define ADC_SMPR2_SMP3_Pos        (9U)
1414 #define ADC_SMPR2_SMP3_Msk        (0x7UL << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000E00 */
1415 #define ADC_SMPR2_SMP3            ADC_SMPR2_SMP3_Msk                           /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
1416 #define ADC_SMPR2_SMP3_0          (0x1UL << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000200 */
1417 #define ADC_SMPR2_SMP3_1          (0x2UL << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000400 */
1418 #define ADC_SMPR2_SMP3_2          (0x4UL << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000800 */
1419 #define ADC_SMPR2_SMP4_Pos        (12U)
1420 #define ADC_SMPR2_SMP4_Msk        (0x7UL << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00007000 */
1421 #define ADC_SMPR2_SMP4            ADC_SMPR2_SMP4_Msk                           /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
1422 #define ADC_SMPR2_SMP4_0          (0x1UL << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00001000 */
1423 #define ADC_SMPR2_SMP4_1          (0x2UL << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00002000 */
1424 #define ADC_SMPR2_SMP4_2          (0x4UL << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00004000 */
1425 #define ADC_SMPR2_SMP5_Pos        (15U)
1426 #define ADC_SMPR2_SMP5_Msk        (0x7UL << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00038000 */
1427 #define ADC_SMPR2_SMP5            ADC_SMPR2_SMP5_Msk                           /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
1428 #define ADC_SMPR2_SMP5_0          (0x1UL << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00008000 */
1429 #define ADC_SMPR2_SMP5_1          (0x2UL << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00010000 */
1430 #define ADC_SMPR2_SMP5_2          (0x4UL << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00020000 */
1431 #define ADC_SMPR2_SMP6_Pos        (18U)
1432 #define ADC_SMPR2_SMP6_Msk        (0x7UL << ADC_SMPR2_SMP6_Pos)                 /*!< 0x001C0000 */
1433 #define ADC_SMPR2_SMP6            ADC_SMPR2_SMP6_Msk                           /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
1434 #define ADC_SMPR2_SMP6_0          (0x1UL << ADC_SMPR2_SMP6_Pos)                 /*!< 0x00040000 */
1435 #define ADC_SMPR2_SMP6_1          (0x2UL << ADC_SMPR2_SMP6_Pos)                 /*!< 0x00080000 */
1436 #define ADC_SMPR2_SMP6_2          (0x4UL << ADC_SMPR2_SMP6_Pos)                 /*!< 0x00100000 */
1437 #define ADC_SMPR2_SMP7_Pos        (21U)
1438 #define ADC_SMPR2_SMP7_Msk        (0x7UL << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00E00000 */
1439 #define ADC_SMPR2_SMP7            ADC_SMPR2_SMP7_Msk                           /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
1440 #define ADC_SMPR2_SMP7_0          (0x1UL << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00200000 */
1441 #define ADC_SMPR2_SMP7_1          (0x2UL << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00400000 */
1442 #define ADC_SMPR2_SMP7_2          (0x4UL << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00800000 */
1443 #define ADC_SMPR2_SMP8_Pos        (24U)
1444 #define ADC_SMPR2_SMP8_Msk        (0x7UL << ADC_SMPR2_SMP8_Pos)                 /*!< 0x07000000 */
1445 #define ADC_SMPR2_SMP8            ADC_SMPR2_SMP8_Msk                           /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
1446 #define ADC_SMPR2_SMP8_0          (0x1UL << ADC_SMPR2_SMP8_Pos)                 /*!< 0x01000000 */
1447 #define ADC_SMPR2_SMP8_1          (0x2UL << ADC_SMPR2_SMP8_Pos)                 /*!< 0x02000000 */
1448 #define ADC_SMPR2_SMP8_2          (0x4UL << ADC_SMPR2_SMP8_Pos)                 /*!< 0x04000000 */
1449 #define ADC_SMPR2_SMP9_Pos        (27U)
1450 #define ADC_SMPR2_SMP9_Msk        (0x7UL << ADC_SMPR2_SMP9_Pos)                 /*!< 0x38000000 */
1451 #define ADC_SMPR2_SMP9            ADC_SMPR2_SMP9_Msk                           /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
1452 #define ADC_SMPR2_SMP9_0          (0x1UL << ADC_SMPR2_SMP9_Pos)                 /*!< 0x08000000 */
1453 #define ADC_SMPR2_SMP9_1          (0x2UL << ADC_SMPR2_SMP9_Pos)                 /*!< 0x10000000 */
1454 #define ADC_SMPR2_SMP9_2          (0x4UL << ADC_SMPR2_SMP9_Pos)                 /*!< 0x20000000 */
1455 
1456 /******************  Bit definition for ADC_JOFR1 register  *******************/
1457 #define ADC_JOFR1_JOFFSET1_Pos    (0U)
1458 #define ADC_JOFR1_JOFFSET1_Msk    (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos)           /*!< 0x00000FFF */
1459 #define ADC_JOFR1_JOFFSET1        ADC_JOFR1_JOFFSET1_Msk                       /*!<Data offset for injected channel 1 */
1460 
1461 /******************  Bit definition for ADC_JOFR2 register  *******************/
1462 #define ADC_JOFR2_JOFFSET2_Pos    (0U)
1463 #define ADC_JOFR2_JOFFSET2_Msk    (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos)           /*!< 0x00000FFF */
1464 #define ADC_JOFR2_JOFFSET2        ADC_JOFR2_JOFFSET2_Msk                       /*!<Data offset for injected channel 2 */
1465 
1466 /******************  Bit definition for ADC_JOFR3 register  *******************/
1467 #define ADC_JOFR3_JOFFSET3_Pos    (0U)
1468 #define ADC_JOFR3_JOFFSET3_Msk    (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos)           /*!< 0x00000FFF */
1469 #define ADC_JOFR3_JOFFSET3        ADC_JOFR3_JOFFSET3_Msk                       /*!<Data offset for injected channel 3 */
1470 
1471 /******************  Bit definition for ADC_JOFR4 register  *******************/
1472 #define ADC_JOFR4_JOFFSET4_Pos    (0U)
1473 #define ADC_JOFR4_JOFFSET4_Msk    (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos)           /*!< 0x00000FFF */
1474 #define ADC_JOFR4_JOFFSET4        ADC_JOFR4_JOFFSET4_Msk                       /*!<Data offset for injected channel 4 */
1475 
1476 /*******************  Bit definition for ADC_HTR register  ********************/
1477 #define ADC_HTR_HT_Pos            (0U)
1478 #define ADC_HTR_HT_Msk            (0xFFFUL << ADC_HTR_HT_Pos)                   /*!< 0x00000FFF */
1479 #define ADC_HTR_HT                ADC_HTR_HT_Msk                               /*!<Analog watchdog high threshold */
1480 
1481 /*******************  Bit definition for ADC_LTR register  ********************/
1482 #define ADC_LTR_LT_Pos            (0U)
1483 #define ADC_LTR_LT_Msk            (0xFFFUL << ADC_LTR_LT_Pos)                   /*!< 0x00000FFF */
1484 #define ADC_LTR_LT                ADC_LTR_LT_Msk                               /*!<Analog watchdog low threshold */
1485 
1486 /*******************  Bit definition for ADC_SQR1 register  *******************/
1487 #define ADC_SQR1_SQ13_Pos         (0U)
1488 #define ADC_SQR1_SQ13_Msk         (0x1FUL << ADC_SQR1_SQ13_Pos)                 /*!< 0x0000001F */
1489 #define ADC_SQR1_SQ13             ADC_SQR1_SQ13_Msk                            /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
1490 #define ADC_SQR1_SQ13_0           (0x01UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000001 */
1491 #define ADC_SQR1_SQ13_1           (0x02UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000002 */
1492 #define ADC_SQR1_SQ13_2           (0x04UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000004 */
1493 #define ADC_SQR1_SQ13_3           (0x08UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000008 */
1494 #define ADC_SQR1_SQ13_4           (0x10UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000010 */
1495 #define ADC_SQR1_SQ14_Pos         (5U)
1496 #define ADC_SQR1_SQ14_Msk         (0x1FUL << ADC_SQR1_SQ14_Pos)                 /*!< 0x000003E0 */
1497 #define ADC_SQR1_SQ14             ADC_SQR1_SQ14_Msk                            /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
1498 #define ADC_SQR1_SQ14_0           (0x01UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000020 */
1499 #define ADC_SQR1_SQ14_1           (0x02UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000040 */
1500 #define ADC_SQR1_SQ14_2           (0x04UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000080 */
1501 #define ADC_SQR1_SQ14_3           (0x08UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000100 */
1502 #define ADC_SQR1_SQ14_4           (0x10UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000200 */
1503 #define ADC_SQR1_SQ15_Pos         (10U)
1504 #define ADC_SQR1_SQ15_Msk         (0x1FUL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00007C00 */
1505 #define ADC_SQR1_SQ15             ADC_SQR1_SQ15_Msk                            /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
1506 #define ADC_SQR1_SQ15_0           (0x01UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00000400 */
1507 #define ADC_SQR1_SQ15_1           (0x02UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00000800 */
1508 #define ADC_SQR1_SQ15_2           (0x04UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00001000 */
1509 #define ADC_SQR1_SQ15_3           (0x08UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00002000 */
1510 #define ADC_SQR1_SQ15_4           (0x10UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00004000 */
1511 #define ADC_SQR1_SQ16_Pos         (15U)
1512 #define ADC_SQR1_SQ16_Msk         (0x1FUL << ADC_SQR1_SQ16_Pos)                 /*!< 0x000F8000 */
1513 #define ADC_SQR1_SQ16             ADC_SQR1_SQ16_Msk                            /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
1514 #define ADC_SQR1_SQ16_0           (0x01UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00008000 */
1515 #define ADC_SQR1_SQ16_1           (0x02UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00010000 */
1516 #define ADC_SQR1_SQ16_2           (0x04UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00020000 */
1517 #define ADC_SQR1_SQ16_3           (0x08UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00040000 */
1518 #define ADC_SQR1_SQ16_4           (0x10UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00080000 */
1519 #define ADC_SQR1_L_Pos            (20U)
1520 #define ADC_SQR1_L_Msk            (0xFUL << ADC_SQR1_L_Pos)                     /*!< 0x00F00000 */
1521 #define ADC_SQR1_L                ADC_SQR1_L_Msk                               /*!<L[3:0] bits (Regular channel sequence length) */
1522 #define ADC_SQR1_L_0              (0x1UL << ADC_SQR1_L_Pos)                     /*!< 0x00100000 */
1523 #define ADC_SQR1_L_1              (0x2UL << ADC_SQR1_L_Pos)                     /*!< 0x00200000 */
1524 #define ADC_SQR1_L_2              (0x4UL << ADC_SQR1_L_Pos)                     /*!< 0x00400000 */
1525 #define ADC_SQR1_L_3              (0x8UL << ADC_SQR1_L_Pos)                     /*!< 0x00800000 */
1526 
1527 /*******************  Bit definition for ADC_SQR2 register  *******************/
1528 #define ADC_SQR2_SQ7_Pos          (0U)
1529 #define ADC_SQR2_SQ7_Msk          (0x1FUL << ADC_SQR2_SQ7_Pos)                  /*!< 0x0000001F */
1530 #define ADC_SQR2_SQ7              ADC_SQR2_SQ7_Msk                             /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
1531 #define ADC_SQR2_SQ7_0            (0x01UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000001 */
1532 #define ADC_SQR2_SQ7_1            (0x02UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000002 */
1533 #define ADC_SQR2_SQ7_2            (0x04UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000004 */
1534 #define ADC_SQR2_SQ7_3            (0x08UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000008 */
1535 #define ADC_SQR2_SQ7_4            (0x10UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000010 */
1536 #define ADC_SQR2_SQ8_Pos          (5U)
1537 #define ADC_SQR2_SQ8_Msk          (0x1FUL << ADC_SQR2_SQ8_Pos)                  /*!< 0x000003E0 */
1538 #define ADC_SQR2_SQ8              ADC_SQR2_SQ8_Msk                             /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
1539 #define ADC_SQR2_SQ8_0            (0x01UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000020 */
1540 #define ADC_SQR2_SQ8_1            (0x02UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000040 */
1541 #define ADC_SQR2_SQ8_2            (0x04UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000080 */
1542 #define ADC_SQR2_SQ8_3            (0x08UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000100 */
1543 #define ADC_SQR2_SQ8_4            (0x10UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000200 */
1544 #define ADC_SQR2_SQ9_Pos          (10U)
1545 #define ADC_SQR2_SQ9_Msk          (0x1FUL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00007C00 */
1546 #define ADC_SQR2_SQ9              ADC_SQR2_SQ9_Msk                             /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
1547 #define ADC_SQR2_SQ9_0            (0x01UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00000400 */
1548 #define ADC_SQR2_SQ9_1            (0x02UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00000800 */
1549 #define ADC_SQR2_SQ9_2            (0x04UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00001000 */
1550 #define ADC_SQR2_SQ9_3            (0x08UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00002000 */
1551 #define ADC_SQR2_SQ9_4            (0x10UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00004000 */
1552 #define ADC_SQR2_SQ10_Pos         (15U)
1553 #define ADC_SQR2_SQ10_Msk         (0x1FUL << ADC_SQR2_SQ10_Pos)                 /*!< 0x000F8000 */
1554 #define ADC_SQR2_SQ10             ADC_SQR2_SQ10_Msk                            /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
1555 #define ADC_SQR2_SQ10_0           (0x01UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00008000 */
1556 #define ADC_SQR2_SQ10_1           (0x02UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00010000 */
1557 #define ADC_SQR2_SQ10_2           (0x04UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00020000 */
1558 #define ADC_SQR2_SQ10_3           (0x08UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00040000 */
1559 #define ADC_SQR2_SQ10_4           (0x10UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00080000 */
1560 #define ADC_SQR2_SQ11_Pos         (20U)
1561 #define ADC_SQR2_SQ11_Msk         (0x1FUL << ADC_SQR2_SQ11_Pos)                 /*!< 0x01F00000 */
1562 #define ADC_SQR2_SQ11             ADC_SQR2_SQ11_Msk                            /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
1563 #define ADC_SQR2_SQ11_0           (0x01UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x00100000 */
1564 #define ADC_SQR2_SQ11_1           (0x02UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x00200000 */
1565 #define ADC_SQR2_SQ11_2           (0x04UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x00400000 */
1566 #define ADC_SQR2_SQ11_3           (0x08UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x00800000 */
1567 #define ADC_SQR2_SQ11_4           (0x10UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x01000000 */
1568 #define ADC_SQR2_SQ12_Pos         (25U)
1569 #define ADC_SQR2_SQ12_Msk         (0x1FUL << ADC_SQR2_SQ12_Pos)                 /*!< 0x3E000000 */
1570 #define ADC_SQR2_SQ12             ADC_SQR2_SQ12_Msk                            /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
1571 #define ADC_SQR2_SQ12_0           (0x01UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x02000000 */
1572 #define ADC_SQR2_SQ12_1           (0x02UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x04000000 */
1573 #define ADC_SQR2_SQ12_2           (0x04UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x08000000 */
1574 #define ADC_SQR2_SQ12_3           (0x08UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x10000000 */
1575 #define ADC_SQR2_SQ12_4           (0x10UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x20000000 */
1576 
1577 /*******************  Bit definition for ADC_SQR3 register  *******************/
1578 #define ADC_SQR3_SQ1_Pos          (0U)
1579 #define ADC_SQR3_SQ1_Msk          (0x1FUL << ADC_SQR3_SQ1_Pos)                  /*!< 0x0000001F */
1580 #define ADC_SQR3_SQ1              ADC_SQR3_SQ1_Msk                             /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
1581 #define ADC_SQR3_SQ1_0            (0x01UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000001 */
1582 #define ADC_SQR3_SQ1_1            (0x02UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000002 */
1583 #define ADC_SQR3_SQ1_2            (0x04UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000004 */
1584 #define ADC_SQR3_SQ1_3            (0x08UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000008 */
1585 #define ADC_SQR3_SQ1_4            (0x10UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000010 */
1586 #define ADC_SQR3_SQ2_Pos          (5U)
1587 #define ADC_SQR3_SQ2_Msk          (0x1FUL << ADC_SQR3_SQ2_Pos)                  /*!< 0x000003E0 */
1588 #define ADC_SQR3_SQ2              ADC_SQR3_SQ2_Msk                             /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
1589 #define ADC_SQR3_SQ2_0            (0x01UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000020 */
1590 #define ADC_SQR3_SQ2_1            (0x02UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000040 */
1591 #define ADC_SQR3_SQ2_2            (0x04UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000080 */
1592 #define ADC_SQR3_SQ2_3            (0x08UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000100 */
1593 #define ADC_SQR3_SQ2_4            (0x10UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000200 */
1594 #define ADC_SQR3_SQ3_Pos          (10U)
1595 #define ADC_SQR3_SQ3_Msk          (0x1FUL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00007C00 */
1596 #define ADC_SQR3_SQ3              ADC_SQR3_SQ3_Msk                             /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
1597 #define ADC_SQR3_SQ3_0            (0x01UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00000400 */
1598 #define ADC_SQR3_SQ3_1            (0x02UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00000800 */
1599 #define ADC_SQR3_SQ3_2            (0x04UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00001000 */
1600 #define ADC_SQR3_SQ3_3            (0x08UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00002000 */
1601 #define ADC_SQR3_SQ3_4            (0x10UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00004000 */
1602 #define ADC_SQR3_SQ4_Pos          (15U)
1603 #define ADC_SQR3_SQ4_Msk          (0x1FUL << ADC_SQR3_SQ4_Pos)                  /*!< 0x000F8000 */
1604 #define ADC_SQR3_SQ4              ADC_SQR3_SQ4_Msk                             /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
1605 #define ADC_SQR3_SQ4_0            (0x01UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00008000 */
1606 #define ADC_SQR3_SQ4_1            (0x02UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00010000 */
1607 #define ADC_SQR3_SQ4_2            (0x04UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00020000 */
1608 #define ADC_SQR3_SQ4_3            (0x08UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00040000 */
1609 #define ADC_SQR3_SQ4_4            (0x10UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00080000 */
1610 #define ADC_SQR3_SQ5_Pos          (20U)
1611 #define ADC_SQR3_SQ5_Msk          (0x1FUL << ADC_SQR3_SQ5_Pos)                  /*!< 0x01F00000 */
1612 #define ADC_SQR3_SQ5              ADC_SQR3_SQ5_Msk                             /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
1613 #define ADC_SQR3_SQ5_0            (0x01UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x00100000 */
1614 #define ADC_SQR3_SQ5_1            (0x02UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x00200000 */
1615 #define ADC_SQR3_SQ5_2            (0x04UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x00400000 */
1616 #define ADC_SQR3_SQ5_3            (0x08UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x00800000 */
1617 #define ADC_SQR3_SQ5_4            (0x10UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x01000000 */
1618 #define ADC_SQR3_SQ6_Pos          (25U)
1619 #define ADC_SQR3_SQ6_Msk          (0x1FUL << ADC_SQR3_SQ6_Pos)                  /*!< 0x3E000000 */
1620 #define ADC_SQR3_SQ6              ADC_SQR3_SQ6_Msk                             /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
1621 #define ADC_SQR3_SQ6_0            (0x01UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x02000000 */
1622 #define ADC_SQR3_SQ6_1            (0x02UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x04000000 */
1623 #define ADC_SQR3_SQ6_2            (0x04UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x08000000 */
1624 #define ADC_SQR3_SQ6_3            (0x08UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x10000000 */
1625 #define ADC_SQR3_SQ6_4            (0x10UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x20000000 */
1626 
1627 /*******************  Bit definition for ADC_JSQR register  *******************/
1628 #define ADC_JSQR_JSQ1_Pos         (0U)
1629 #define ADC_JSQR_JSQ1_Msk         (0x1FUL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x0000001F */
1630 #define ADC_JSQR_JSQ1             ADC_JSQR_JSQ1_Msk                            /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
1631 #define ADC_JSQR_JSQ1_0           (0x01UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000001 */
1632 #define ADC_JSQR_JSQ1_1           (0x02UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000002 */
1633 #define ADC_JSQR_JSQ1_2           (0x04UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000004 */
1634 #define ADC_JSQR_JSQ1_3           (0x08UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000008 */
1635 #define ADC_JSQR_JSQ1_4           (0x10UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000010 */
1636 #define ADC_JSQR_JSQ2_Pos         (5U)
1637 #define ADC_JSQR_JSQ2_Msk         (0x1FUL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x000003E0 */
1638 #define ADC_JSQR_JSQ2             ADC_JSQR_JSQ2_Msk                            /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
1639 #define ADC_JSQR_JSQ2_0           (0x01UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000020 */
1640 #define ADC_JSQR_JSQ2_1           (0x02UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000040 */
1641 #define ADC_JSQR_JSQ2_2           (0x04UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000080 */
1642 #define ADC_JSQR_JSQ2_3           (0x08UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000100 */
1643 #define ADC_JSQR_JSQ2_4           (0x10UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000200 */
1644 #define ADC_JSQR_JSQ3_Pos         (10U)
1645 #define ADC_JSQR_JSQ3_Msk         (0x1FUL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00007C00 */
1646 #define ADC_JSQR_JSQ3             ADC_JSQR_JSQ3_Msk                            /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
1647 #define ADC_JSQR_JSQ3_0           (0x01UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00000400 */
1648 #define ADC_JSQR_JSQ3_1           (0x02UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00000800 */
1649 #define ADC_JSQR_JSQ3_2           (0x04UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00001000 */
1650 #define ADC_JSQR_JSQ3_3           (0x08UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00002000 */
1651 #define ADC_JSQR_JSQ3_4           (0x10UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00004000 */
1652 #define ADC_JSQR_JSQ4_Pos         (15U)
1653 #define ADC_JSQR_JSQ4_Msk         (0x1FUL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x000F8000 */
1654 #define ADC_JSQR_JSQ4             ADC_JSQR_JSQ4_Msk                            /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
1655 #define ADC_JSQR_JSQ4_0           (0x01UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00008000 */
1656 #define ADC_JSQR_JSQ4_1           (0x02UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00010000 */
1657 #define ADC_JSQR_JSQ4_2           (0x04UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00020000 */
1658 #define ADC_JSQR_JSQ4_3           (0x08UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00040000 */
1659 #define ADC_JSQR_JSQ4_4           (0x10UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00080000 */
1660 #define ADC_JSQR_JL_Pos           (20U)
1661 #define ADC_JSQR_JL_Msk           (0x3UL << ADC_JSQR_JL_Pos)                    /*!< 0x00300000 */
1662 #define ADC_JSQR_JL               ADC_JSQR_JL_Msk                              /*!<JL[1:0] bits (Injected Sequence length) */
1663 #define ADC_JSQR_JL_0             (0x1UL << ADC_JSQR_JL_Pos)                    /*!< 0x00100000 */
1664 #define ADC_JSQR_JL_1             (0x2UL << ADC_JSQR_JL_Pos)                    /*!< 0x00200000 */
1665 
1666 /*******************  Bit definition for ADC_JDR1 register  *******************/
1667 #define ADC_JDR1_JDATA_Pos        (0U)
1668 #define ADC_JDR1_JDATA_Msk        (0xFFFFUL << ADC_JDR1_JDATA_Pos)              /*!< 0x0000FFFF */
1669 #define ADC_JDR1_JDATA            ADC_JDR1_JDATA_Msk                           /*!<Injected data */
1670 
1671 /*******************  Bit definition for ADC_JDR2 register  *******************/
1672 #define ADC_JDR2_JDATA_Pos        (0U)
1673 #define ADC_JDR2_JDATA_Msk        (0xFFFFUL << ADC_JDR2_JDATA_Pos)              /*!< 0x0000FFFF */
1674 #define ADC_JDR2_JDATA            ADC_JDR2_JDATA_Msk                           /*!<Injected data */
1675 
1676 /*******************  Bit definition for ADC_JDR3 register  *******************/
1677 #define ADC_JDR3_JDATA_Pos        (0U)
1678 #define ADC_JDR3_JDATA_Msk        (0xFFFFUL << ADC_JDR3_JDATA_Pos)              /*!< 0x0000FFFF */
1679 #define ADC_JDR3_JDATA            ADC_JDR3_JDATA_Msk                           /*!<Injected data */
1680 
1681 /*******************  Bit definition for ADC_JDR4 register  *******************/
1682 #define ADC_JDR4_JDATA_Pos        (0U)
1683 #define ADC_JDR4_JDATA_Msk        (0xFFFFUL << ADC_JDR4_JDATA_Pos)              /*!< 0x0000FFFF */
1684 #define ADC_JDR4_JDATA            ADC_JDR4_JDATA_Msk                           /*!<Injected data */
1685 
1686 /********************  Bit definition for ADC_DR register  ********************/
1687 #define ADC_DR_DATA_Pos           (0U)
1688 #define ADC_DR_DATA_Msk           (0xFFFFUL << ADC_DR_DATA_Pos)                 /*!< 0x0000FFFF */
1689 #define ADC_DR_DATA               ADC_DR_DATA_Msk                              /*!<Regular data */
1690 #define ADC_DR_ADC2DATA_Pos       (16U)
1691 #define ADC_DR_ADC2DATA_Msk       (0xFFFFUL << ADC_DR_ADC2DATA_Pos)             /*!< 0xFFFF0000 */
1692 #define ADC_DR_ADC2DATA           ADC_DR_ADC2DATA_Msk                          /*!<ADC2 data */
1693 
1694 /*******************  Bit definition for ADC_CSR register  ********************/
1695 #define ADC_CSR_AWD1_Pos          (0U)
1696 #define ADC_CSR_AWD1_Msk          (0x1UL << ADC_CSR_AWD1_Pos)                   /*!< 0x00000001 */
1697 #define ADC_CSR_AWD1              ADC_CSR_AWD1_Msk                             /*!<ADC1 Analog watchdog flag */
1698 #define ADC_CSR_EOC1_Pos          (1U)
1699 #define ADC_CSR_EOC1_Msk          (0x1UL << ADC_CSR_EOC1_Pos)                   /*!< 0x00000002 */
1700 #define ADC_CSR_EOC1              ADC_CSR_EOC1_Msk                             /*!<ADC1 End of conversion */
1701 #define ADC_CSR_JEOC1_Pos         (2U)
1702 #define ADC_CSR_JEOC1_Msk         (0x1UL << ADC_CSR_JEOC1_Pos)                  /*!< 0x00000004 */
1703 #define ADC_CSR_JEOC1             ADC_CSR_JEOC1_Msk                            /*!<ADC1 Injected channel end of conversion */
1704 #define ADC_CSR_JSTRT1_Pos        (3U)
1705 #define ADC_CSR_JSTRT1_Msk        (0x1UL << ADC_CSR_JSTRT1_Pos)                 /*!< 0x00000008 */
1706 #define ADC_CSR_JSTRT1            ADC_CSR_JSTRT1_Msk                           /*!<ADC1 Injected channel Start flag */
1707 #define ADC_CSR_STRT1_Pos         (4U)
1708 #define ADC_CSR_STRT1_Msk         (0x1UL << ADC_CSR_STRT1_Pos)                  /*!< 0x00000010 */
1709 #define ADC_CSR_STRT1             ADC_CSR_STRT1_Msk                            /*!<ADC1 Regular channel Start flag */
1710 #define ADC_CSR_OVR1_Pos          (5U)
1711 #define ADC_CSR_OVR1_Msk          (0x1UL << ADC_CSR_OVR1_Pos)                   /*!< 0x00000020 */
1712 #define ADC_CSR_OVR1              ADC_CSR_OVR1_Msk                             /*!<ADC1 DMA overrun  flag */
1713 
1714 /* Legacy defines */
1715 #define  ADC_CSR_DOVR1                        ADC_CSR_OVR1
1716 
1717 /*******************  Bit definition for ADC_CCR register  ********************/
1718 #define ADC_CCR_MULTI_Pos         (0U)
1719 #define ADC_CCR_MULTI_Msk         (0x1FUL << ADC_CCR_MULTI_Pos)                 /*!< 0x0000001F */
1720 #define ADC_CCR_MULTI             ADC_CCR_MULTI_Msk                            /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
1721 #define ADC_CCR_MULTI_0           (0x01UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000001 */
1722 #define ADC_CCR_MULTI_1           (0x02UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000002 */
1723 #define ADC_CCR_MULTI_2           (0x04UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000004 */
1724 #define ADC_CCR_MULTI_3           (0x08UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000008 */
1725 #define ADC_CCR_MULTI_4           (0x10UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000010 */
1726 #define ADC_CCR_DELAY_Pos         (8U)
1727 #define ADC_CCR_DELAY_Msk         (0xFUL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000F00 */
1728 #define ADC_CCR_DELAY             ADC_CCR_DELAY_Msk                            /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
1729 #define ADC_CCR_DELAY_0           (0x1UL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000100 */
1730 #define ADC_CCR_DELAY_1           (0x2UL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000200 */
1731 #define ADC_CCR_DELAY_2           (0x4UL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000400 */
1732 #define ADC_CCR_DELAY_3           (0x8UL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000800 */
1733 #define ADC_CCR_DDS_Pos           (13U)
1734 #define ADC_CCR_DDS_Msk           (0x1UL << ADC_CCR_DDS_Pos)                    /*!< 0x00002000 */
1735 #define ADC_CCR_DDS               ADC_CCR_DDS_Msk                              /*!<DMA disable selection (Multi-ADC mode) */
1736 #define ADC_CCR_DMA_Pos           (14U)
1737 #define ADC_CCR_DMA_Msk           (0x3UL << ADC_CCR_DMA_Pos)                    /*!< 0x0000C000 */
1738 #define ADC_CCR_DMA               ADC_CCR_DMA_Msk                              /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
1739 #define ADC_CCR_DMA_0             (0x1UL << ADC_CCR_DMA_Pos)                    /*!< 0x00004000 */
1740 #define ADC_CCR_DMA_1             (0x2UL << ADC_CCR_DMA_Pos)                    /*!< 0x00008000 */
1741 #define ADC_CCR_ADCPRE_Pos        (16U)
1742 #define ADC_CCR_ADCPRE_Msk        (0x3UL << ADC_CCR_ADCPRE_Pos)                 /*!< 0x00030000 */
1743 #define ADC_CCR_ADCPRE            ADC_CCR_ADCPRE_Msk                           /*!<ADCPRE[1:0] bits (ADC prescaler) */
1744 #define ADC_CCR_ADCPRE_0          (0x1UL << ADC_CCR_ADCPRE_Pos)                 /*!< 0x00010000 */
1745 #define ADC_CCR_ADCPRE_1          (0x2UL << ADC_CCR_ADCPRE_Pos)                 /*!< 0x00020000 */
1746 #define ADC_CCR_VBATE_Pos         (22U)
1747 #define ADC_CCR_VBATE_Msk         (0x1UL << ADC_CCR_VBATE_Pos)                  /*!< 0x00400000 */
1748 #define ADC_CCR_VBATE             ADC_CCR_VBATE_Msk                            /*!<VBAT Enable */
1749 #define ADC_CCR_TSVREFE_Pos       (23U)
1750 #define ADC_CCR_TSVREFE_Msk       (0x1UL << ADC_CCR_TSVREFE_Pos)                /*!< 0x00800000 */
1751 #define ADC_CCR_TSVREFE           ADC_CCR_TSVREFE_Msk                          /*!<Temperature Sensor and VREFINT Enable */
1752 
1753 /*******************  Bit definition for ADC_CDR register  ********************/
1754 #define ADC_CDR_DATA1_Pos         (0U)
1755 #define ADC_CDR_DATA1_Msk         (0xFFFFUL << ADC_CDR_DATA1_Pos)               /*!< 0x0000FFFF */
1756 #define ADC_CDR_DATA1             ADC_CDR_DATA1_Msk                            /*!<1st data of a pair of regular conversions */
1757 #define ADC_CDR_DATA2_Pos         (16U)
1758 #define ADC_CDR_DATA2_Msk         (0xFFFFUL << ADC_CDR_DATA2_Pos)               /*!< 0xFFFF0000 */
1759 #define ADC_CDR_DATA2             ADC_CDR_DATA2_Msk                            /*!<2nd data of a pair of regular conversions */
1760 
1761 /* Legacy defines */
1762 #define ADC_CDR_RDATA_MST         ADC_CDR_DATA1
1763 #define ADC_CDR_RDATA_SLV         ADC_CDR_DATA2
1764 
1765 /******************************************************************************/
1766 /*                                                                            */
1767 /*                         Controller Area Network                            */
1768 /*                                                                            */
1769 /******************************************************************************/
1770 /*!<CAN control and status registers */
1771 /*******************  Bit definition for CAN_MCR register  ********************/
1772 #define CAN_MCR_INRQ_Pos       (0U)
1773 #define CAN_MCR_INRQ_Msk       (0x1UL << CAN_MCR_INRQ_Pos)                      /*!< 0x00000001 */
1774 #define CAN_MCR_INRQ           CAN_MCR_INRQ_Msk                                /*!<Initialization Request */
1775 #define CAN_MCR_SLEEP_Pos      (1U)
1776 #define CAN_MCR_SLEEP_Msk      (0x1UL << CAN_MCR_SLEEP_Pos)                     /*!< 0x00000002 */
1777 #define CAN_MCR_SLEEP          CAN_MCR_SLEEP_Msk                               /*!<Sleep Mode Request */
1778 #define CAN_MCR_TXFP_Pos       (2U)
1779 #define CAN_MCR_TXFP_Msk       (0x1UL << CAN_MCR_TXFP_Pos)                      /*!< 0x00000004 */
1780 #define CAN_MCR_TXFP           CAN_MCR_TXFP_Msk                                /*!<Transmit FIFO Priority */
1781 #define CAN_MCR_RFLM_Pos       (3U)
1782 #define CAN_MCR_RFLM_Msk       (0x1UL << CAN_MCR_RFLM_Pos)                      /*!< 0x00000008 */
1783 #define CAN_MCR_RFLM           CAN_MCR_RFLM_Msk                                /*!<Receive FIFO Locked Mode */
1784 #define CAN_MCR_NART_Pos       (4U)
1785 #define CAN_MCR_NART_Msk       (0x1UL << CAN_MCR_NART_Pos)                      /*!< 0x00000010 */
1786 #define CAN_MCR_NART           CAN_MCR_NART_Msk                                /*!<No Automatic Retransmission */
1787 #define CAN_MCR_AWUM_Pos       (5U)
1788 #define CAN_MCR_AWUM_Msk       (0x1UL << CAN_MCR_AWUM_Pos)                      /*!< 0x00000020 */
1789 #define CAN_MCR_AWUM           CAN_MCR_AWUM_Msk                                /*!<Automatic Wakeup Mode */
1790 #define CAN_MCR_ABOM_Pos       (6U)
1791 #define CAN_MCR_ABOM_Msk       (0x1UL << CAN_MCR_ABOM_Pos)                      /*!< 0x00000040 */
1792 #define CAN_MCR_ABOM           CAN_MCR_ABOM_Msk                                /*!<Automatic Bus-Off Management */
1793 #define CAN_MCR_TTCM_Pos       (7U)
1794 #define CAN_MCR_TTCM_Msk       (0x1UL << CAN_MCR_TTCM_Pos)                      /*!< 0x00000080 */
1795 #define CAN_MCR_TTCM           CAN_MCR_TTCM_Msk                                /*!<Time Triggered Communication Mode */
1796 #define CAN_MCR_RESET_Pos      (15U)
1797 #define CAN_MCR_RESET_Msk      (0x1UL << CAN_MCR_RESET_Pos)                     /*!< 0x00008000 */
1798 #define CAN_MCR_RESET          CAN_MCR_RESET_Msk                               /*!<bxCAN software master reset */
1799 #define CAN_MCR_DBF_Pos        (16U)
1800 #define CAN_MCR_DBF_Msk        (0x1UL << CAN_MCR_DBF_Pos)                       /*!< 0x00010000 */
1801 #define CAN_MCR_DBF            CAN_MCR_DBF_Msk                                 /*!<bxCAN Debug freeze */
1802 /*******************  Bit definition for CAN_MSR register  ********************/
1803 #define CAN_MSR_INAK_Pos       (0U)
1804 #define CAN_MSR_INAK_Msk       (0x1UL << CAN_MSR_INAK_Pos)                      /*!< 0x00000001 */
1805 #define CAN_MSR_INAK           CAN_MSR_INAK_Msk                                /*!<Initialization Acknowledge */
1806 #define CAN_MSR_SLAK_Pos       (1U)
1807 #define CAN_MSR_SLAK_Msk       (0x1UL << CAN_MSR_SLAK_Pos)                      /*!< 0x00000002 */
1808 #define CAN_MSR_SLAK           CAN_MSR_SLAK_Msk                                /*!<Sleep Acknowledge */
1809 #define CAN_MSR_ERRI_Pos       (2U)
1810 #define CAN_MSR_ERRI_Msk       (0x1UL << CAN_MSR_ERRI_Pos)                      /*!< 0x00000004 */
1811 #define CAN_MSR_ERRI           CAN_MSR_ERRI_Msk                                /*!<Error Interrupt */
1812 #define CAN_MSR_WKUI_Pos       (3U)
1813 #define CAN_MSR_WKUI_Msk       (0x1UL << CAN_MSR_WKUI_Pos)                      /*!< 0x00000008 */
1814 #define CAN_MSR_WKUI           CAN_MSR_WKUI_Msk                                /*!<Wakeup Interrupt */
1815 #define CAN_MSR_SLAKI_Pos      (4U)
1816 #define CAN_MSR_SLAKI_Msk      (0x1UL << CAN_MSR_SLAKI_Pos)                     /*!< 0x00000010 */
1817 #define CAN_MSR_SLAKI          CAN_MSR_SLAKI_Msk                               /*!<Sleep Acknowledge Interrupt */
1818 #define CAN_MSR_TXM_Pos        (8U)
1819 #define CAN_MSR_TXM_Msk        (0x1UL << CAN_MSR_TXM_Pos)                       /*!< 0x00000100 */
1820 #define CAN_MSR_TXM            CAN_MSR_TXM_Msk                                 /*!<Transmit Mode */
1821 #define CAN_MSR_RXM_Pos        (9U)
1822 #define CAN_MSR_RXM_Msk        (0x1UL << CAN_MSR_RXM_Pos)                       /*!< 0x00000200 */
1823 #define CAN_MSR_RXM            CAN_MSR_RXM_Msk                                 /*!<Receive Mode */
1824 #define CAN_MSR_SAMP_Pos       (10U)
1825 #define CAN_MSR_SAMP_Msk       (0x1UL << CAN_MSR_SAMP_Pos)                      /*!< 0x00000400 */
1826 #define CAN_MSR_SAMP           CAN_MSR_SAMP_Msk                                /*!<Last Sample Point */
1827 #define CAN_MSR_RX_Pos         (11U)
1828 #define CAN_MSR_RX_Msk         (0x1UL << CAN_MSR_RX_Pos)                        /*!< 0x00000800 */
1829 #define CAN_MSR_RX             CAN_MSR_RX_Msk                                  /*!<CAN Rx Signal */
1830 
1831 /*******************  Bit definition for CAN_TSR register  ********************/
1832 #define CAN_TSR_RQCP0_Pos      (0U)
1833 #define CAN_TSR_RQCP0_Msk      (0x1UL << CAN_TSR_RQCP0_Pos)                     /*!< 0x00000001 */
1834 #define CAN_TSR_RQCP0          CAN_TSR_RQCP0_Msk                               /*!<Request Completed Mailbox0 */
1835 #define CAN_TSR_TXOK0_Pos      (1U)
1836 #define CAN_TSR_TXOK0_Msk      (0x1UL << CAN_TSR_TXOK0_Pos)                     /*!< 0x00000002 */
1837 #define CAN_TSR_TXOK0          CAN_TSR_TXOK0_Msk                               /*!<Transmission OK of Mailbox0 */
1838 #define CAN_TSR_ALST0_Pos      (2U)
1839 #define CAN_TSR_ALST0_Msk      (0x1UL << CAN_TSR_ALST0_Pos)                     /*!< 0x00000004 */
1840 #define CAN_TSR_ALST0          CAN_TSR_ALST0_Msk                               /*!<Arbitration Lost for Mailbox0 */
1841 #define CAN_TSR_TERR0_Pos      (3U)
1842 #define CAN_TSR_TERR0_Msk      (0x1UL << CAN_TSR_TERR0_Pos)                     /*!< 0x00000008 */
1843 #define CAN_TSR_TERR0          CAN_TSR_TERR0_Msk                               /*!<Transmission Error of Mailbox0 */
1844 #define CAN_TSR_ABRQ0_Pos      (7U)
1845 #define CAN_TSR_ABRQ0_Msk      (0x1UL << CAN_TSR_ABRQ0_Pos)                     /*!< 0x00000080 */
1846 #define CAN_TSR_ABRQ0          CAN_TSR_ABRQ0_Msk                               /*!<Abort Request for Mailbox0 */
1847 #define CAN_TSR_RQCP1_Pos      (8U)
1848 #define CAN_TSR_RQCP1_Msk      (0x1UL << CAN_TSR_RQCP1_Pos)                     /*!< 0x00000100 */
1849 #define CAN_TSR_RQCP1          CAN_TSR_RQCP1_Msk                               /*!<Request Completed Mailbox1 */
1850 #define CAN_TSR_TXOK1_Pos      (9U)
1851 #define CAN_TSR_TXOK1_Msk      (0x1UL << CAN_TSR_TXOK1_Pos)                     /*!< 0x00000200 */
1852 #define CAN_TSR_TXOK1          CAN_TSR_TXOK1_Msk                               /*!<Transmission OK of Mailbox1 */
1853 #define CAN_TSR_ALST1_Pos      (10U)
1854 #define CAN_TSR_ALST1_Msk      (0x1UL << CAN_TSR_ALST1_Pos)                     /*!< 0x00000400 */
1855 #define CAN_TSR_ALST1          CAN_TSR_ALST1_Msk                               /*!<Arbitration Lost for Mailbox1 */
1856 #define CAN_TSR_TERR1_Pos      (11U)
1857 #define CAN_TSR_TERR1_Msk      (0x1UL << CAN_TSR_TERR1_Pos)                     /*!< 0x00000800 */
1858 #define CAN_TSR_TERR1          CAN_TSR_TERR1_Msk                               /*!<Transmission Error of Mailbox1 */
1859 #define CAN_TSR_ABRQ1_Pos      (15U)
1860 #define CAN_TSR_ABRQ1_Msk      (0x1UL << CAN_TSR_ABRQ1_Pos)                     /*!< 0x00008000 */
1861 #define CAN_TSR_ABRQ1          CAN_TSR_ABRQ1_Msk                               /*!<Abort Request for Mailbox 1 */
1862 #define CAN_TSR_RQCP2_Pos      (16U)
1863 #define CAN_TSR_RQCP2_Msk      (0x1UL << CAN_TSR_RQCP2_Pos)                     /*!< 0x00010000 */
1864 #define CAN_TSR_RQCP2          CAN_TSR_RQCP2_Msk                               /*!<Request Completed Mailbox2 */
1865 #define CAN_TSR_TXOK2_Pos      (17U)
1866 #define CAN_TSR_TXOK2_Msk      (0x1UL << CAN_TSR_TXOK2_Pos)                     /*!< 0x00020000 */
1867 #define CAN_TSR_TXOK2          CAN_TSR_TXOK2_Msk                               /*!<Transmission OK of Mailbox 2 */
1868 #define CAN_TSR_ALST2_Pos      (18U)
1869 #define CAN_TSR_ALST2_Msk      (0x1UL << CAN_TSR_ALST2_Pos)                     /*!< 0x00040000 */
1870 #define CAN_TSR_ALST2          CAN_TSR_ALST2_Msk                               /*!<Arbitration Lost for mailbox 2 */
1871 #define CAN_TSR_TERR2_Pos      (19U)
1872 #define CAN_TSR_TERR2_Msk      (0x1UL << CAN_TSR_TERR2_Pos)                     /*!< 0x00080000 */
1873 #define CAN_TSR_TERR2          CAN_TSR_TERR2_Msk                               /*!<Transmission Error of Mailbox 2 */
1874 #define CAN_TSR_ABRQ2_Pos      (23U)
1875 #define CAN_TSR_ABRQ2_Msk      (0x1UL << CAN_TSR_ABRQ2_Pos)                     /*!< 0x00800000 */
1876 #define CAN_TSR_ABRQ2          CAN_TSR_ABRQ2_Msk                               /*!<Abort Request for Mailbox 2 */
1877 #define CAN_TSR_CODE_Pos       (24U)
1878 #define CAN_TSR_CODE_Msk       (0x3UL << CAN_TSR_CODE_Pos)                      /*!< 0x03000000 */
1879 #define CAN_TSR_CODE           CAN_TSR_CODE_Msk                                /*!<Mailbox Code */
1880 
1881 #define CAN_TSR_TME_Pos        (26U)
1882 #define CAN_TSR_TME_Msk        (0x7UL << CAN_TSR_TME_Pos)                       /*!< 0x1C000000 */
1883 #define CAN_TSR_TME            CAN_TSR_TME_Msk                                 /*!<TME[2:0] bits */
1884 #define CAN_TSR_TME0_Pos       (26U)
1885 #define CAN_TSR_TME0_Msk       (0x1UL << CAN_TSR_TME0_Pos)                      /*!< 0x04000000 */
1886 #define CAN_TSR_TME0           CAN_TSR_TME0_Msk                                /*!<Transmit Mailbox 0 Empty */
1887 #define CAN_TSR_TME1_Pos       (27U)
1888 #define CAN_TSR_TME1_Msk       (0x1UL << CAN_TSR_TME1_Pos)                      /*!< 0x08000000 */
1889 #define CAN_TSR_TME1           CAN_TSR_TME1_Msk                                /*!<Transmit Mailbox 1 Empty */
1890 #define CAN_TSR_TME2_Pos       (28U)
1891 #define CAN_TSR_TME2_Msk       (0x1UL << CAN_TSR_TME2_Pos)                      /*!< 0x10000000 */
1892 #define CAN_TSR_TME2           CAN_TSR_TME2_Msk                                /*!<Transmit Mailbox 2 Empty */
1893 
1894 #define CAN_TSR_LOW_Pos        (29U)
1895 #define CAN_TSR_LOW_Msk        (0x7UL << CAN_TSR_LOW_Pos)                       /*!< 0xE0000000 */
1896 #define CAN_TSR_LOW            CAN_TSR_LOW_Msk                                 /*!<LOW[2:0] bits */
1897 #define CAN_TSR_LOW0_Pos       (29U)
1898 #define CAN_TSR_LOW0_Msk       (0x1UL << CAN_TSR_LOW0_Pos)                      /*!< 0x20000000 */
1899 #define CAN_TSR_LOW0           CAN_TSR_LOW0_Msk                                /*!<Lowest Priority Flag for Mailbox 0 */
1900 #define CAN_TSR_LOW1_Pos       (30U)
1901 #define CAN_TSR_LOW1_Msk       (0x1UL << CAN_TSR_LOW1_Pos)                      /*!< 0x40000000 */
1902 #define CAN_TSR_LOW1           CAN_TSR_LOW1_Msk                                /*!<Lowest Priority Flag for Mailbox 1 */
1903 #define CAN_TSR_LOW2_Pos       (31U)
1904 #define CAN_TSR_LOW2_Msk       (0x1UL << CAN_TSR_LOW2_Pos)                      /*!< 0x80000000 */
1905 #define CAN_TSR_LOW2           CAN_TSR_LOW2_Msk                                /*!<Lowest Priority Flag for Mailbox 2 */
1906 
1907 /*******************  Bit definition for CAN_RF0R register  *******************/
1908 #define CAN_RF0R_FMP0_Pos      (0U)
1909 #define CAN_RF0R_FMP0_Msk      (0x3UL << CAN_RF0R_FMP0_Pos)                     /*!< 0x00000003 */
1910 #define CAN_RF0R_FMP0          CAN_RF0R_FMP0_Msk                               /*!<FIFO 0 Message Pending */
1911 #define CAN_RF0R_FULL0_Pos     (3U)
1912 #define CAN_RF0R_FULL0_Msk     (0x1UL << CAN_RF0R_FULL0_Pos)                    /*!< 0x00000008 */
1913 #define CAN_RF0R_FULL0         CAN_RF0R_FULL0_Msk                              /*!<FIFO 0 Full */
1914 #define CAN_RF0R_FOVR0_Pos     (4U)
1915 #define CAN_RF0R_FOVR0_Msk     (0x1UL << CAN_RF0R_FOVR0_Pos)                    /*!< 0x00000010 */
1916 #define CAN_RF0R_FOVR0         CAN_RF0R_FOVR0_Msk                              /*!<FIFO 0 Overrun */
1917 #define CAN_RF0R_RFOM0_Pos     (5U)
1918 #define CAN_RF0R_RFOM0_Msk     (0x1UL << CAN_RF0R_RFOM0_Pos)                    /*!< 0x00000020 */
1919 #define CAN_RF0R_RFOM0         CAN_RF0R_RFOM0_Msk                              /*!<Release FIFO 0 Output Mailbox */
1920 
1921 /*******************  Bit definition for CAN_RF1R register  *******************/
1922 #define CAN_RF1R_FMP1_Pos      (0U)
1923 #define CAN_RF1R_FMP1_Msk      (0x3UL << CAN_RF1R_FMP1_Pos)                     /*!< 0x00000003 */
1924 #define CAN_RF1R_FMP1          CAN_RF1R_FMP1_Msk                               /*!<FIFO 1 Message Pending */
1925 #define CAN_RF1R_FULL1_Pos     (3U)
1926 #define CAN_RF1R_FULL1_Msk     (0x1UL << CAN_RF1R_FULL1_Pos)                    /*!< 0x00000008 */
1927 #define CAN_RF1R_FULL1         CAN_RF1R_FULL1_Msk                              /*!<FIFO 1 Full */
1928 #define CAN_RF1R_FOVR1_Pos     (4U)
1929 #define CAN_RF1R_FOVR1_Msk     (0x1UL << CAN_RF1R_FOVR1_Pos)                    /*!< 0x00000010 */
1930 #define CAN_RF1R_FOVR1         CAN_RF1R_FOVR1_Msk                              /*!<FIFO 1 Overrun */
1931 #define CAN_RF1R_RFOM1_Pos     (5U)
1932 #define CAN_RF1R_RFOM1_Msk     (0x1UL << CAN_RF1R_RFOM1_Pos)                    /*!< 0x00000020 */
1933 #define CAN_RF1R_RFOM1         CAN_RF1R_RFOM1_Msk                              /*!<Release FIFO 1 Output Mailbox */
1934 
1935 /********************  Bit definition for CAN_IER register  *******************/
1936 #define CAN_IER_TMEIE_Pos      (0U)
1937 #define CAN_IER_TMEIE_Msk      (0x1UL << CAN_IER_TMEIE_Pos)                     /*!< 0x00000001 */
1938 #define CAN_IER_TMEIE          CAN_IER_TMEIE_Msk                               /*!<Transmit Mailbox Empty Interrupt Enable */
1939 #define CAN_IER_FMPIE0_Pos     (1U)
1940 #define CAN_IER_FMPIE0_Msk     (0x1UL << CAN_IER_FMPIE0_Pos)                    /*!< 0x00000002 */
1941 #define CAN_IER_FMPIE0         CAN_IER_FMPIE0_Msk                              /*!<FIFO Message Pending Interrupt Enable */
1942 #define CAN_IER_FFIE0_Pos      (2U)
1943 #define CAN_IER_FFIE0_Msk      (0x1UL << CAN_IER_FFIE0_Pos)                     /*!< 0x00000004 */
1944 #define CAN_IER_FFIE0          CAN_IER_FFIE0_Msk                               /*!<FIFO Full Interrupt Enable */
1945 #define CAN_IER_FOVIE0_Pos     (3U)
1946 #define CAN_IER_FOVIE0_Msk     (0x1UL << CAN_IER_FOVIE0_Pos)                    /*!< 0x00000008 */
1947 #define CAN_IER_FOVIE0         CAN_IER_FOVIE0_Msk                              /*!<FIFO Overrun Interrupt Enable */
1948 #define CAN_IER_FMPIE1_Pos     (4U)
1949 #define CAN_IER_FMPIE1_Msk     (0x1UL << CAN_IER_FMPIE1_Pos)                    /*!< 0x00000010 */
1950 #define CAN_IER_FMPIE1         CAN_IER_FMPIE1_Msk                              /*!<FIFO Message Pending Interrupt Enable */
1951 #define CAN_IER_FFIE1_Pos      (5U)
1952 #define CAN_IER_FFIE1_Msk      (0x1UL << CAN_IER_FFIE1_Pos)                     /*!< 0x00000020 */
1953 #define CAN_IER_FFIE1          CAN_IER_FFIE1_Msk                               /*!<FIFO Full Interrupt Enable */
1954 #define CAN_IER_FOVIE1_Pos     (6U)
1955 #define CAN_IER_FOVIE1_Msk     (0x1UL << CAN_IER_FOVIE1_Pos)                    /*!< 0x00000040 */
1956 #define CAN_IER_FOVIE1         CAN_IER_FOVIE1_Msk                              /*!<FIFO Overrun Interrupt Enable */
1957 #define CAN_IER_EWGIE_Pos      (8U)
1958 #define CAN_IER_EWGIE_Msk      (0x1UL << CAN_IER_EWGIE_Pos)                     /*!< 0x00000100 */
1959 #define CAN_IER_EWGIE          CAN_IER_EWGIE_Msk                               /*!<Error Warning Interrupt Enable */
1960 #define CAN_IER_EPVIE_Pos      (9U)
1961 #define CAN_IER_EPVIE_Msk      (0x1UL << CAN_IER_EPVIE_Pos)                     /*!< 0x00000200 */
1962 #define CAN_IER_EPVIE          CAN_IER_EPVIE_Msk                               /*!<Error Passive Interrupt Enable */
1963 #define CAN_IER_BOFIE_Pos      (10U)
1964 #define CAN_IER_BOFIE_Msk      (0x1UL << CAN_IER_BOFIE_Pos)                     /*!< 0x00000400 */
1965 #define CAN_IER_BOFIE          CAN_IER_BOFIE_Msk                               /*!<Bus-Off Interrupt Enable */
1966 #define CAN_IER_LECIE_Pos      (11U)
1967 #define CAN_IER_LECIE_Msk      (0x1UL << CAN_IER_LECIE_Pos)                     /*!< 0x00000800 */
1968 #define CAN_IER_LECIE          CAN_IER_LECIE_Msk                               /*!<Last Error Code Interrupt Enable */
1969 #define CAN_IER_ERRIE_Pos      (15U)
1970 #define CAN_IER_ERRIE_Msk      (0x1UL << CAN_IER_ERRIE_Pos)                     /*!< 0x00008000 */
1971 #define CAN_IER_ERRIE          CAN_IER_ERRIE_Msk                               /*!<Error Interrupt Enable */
1972 #define CAN_IER_WKUIE_Pos      (16U)
1973 #define CAN_IER_WKUIE_Msk      (0x1UL << CAN_IER_WKUIE_Pos)                     /*!< 0x00010000 */
1974 #define CAN_IER_WKUIE          CAN_IER_WKUIE_Msk                               /*!<Wakeup Interrupt Enable */
1975 #define CAN_IER_SLKIE_Pos      (17U)
1976 #define CAN_IER_SLKIE_Msk      (0x1UL << CAN_IER_SLKIE_Pos)                     /*!< 0x00020000 */
1977 #define CAN_IER_SLKIE          CAN_IER_SLKIE_Msk                               /*!<Sleep Interrupt Enable */
1978 #define CAN_IER_EWGIE_Pos      (8U)
1979 
1980 /********************  Bit definition for CAN_ESR register  *******************/
1981 #define CAN_ESR_EWGF_Pos       (0U)
1982 #define CAN_ESR_EWGF_Msk       (0x1UL << CAN_ESR_EWGF_Pos)                      /*!< 0x00000001 */
1983 #define CAN_ESR_EWGF           CAN_ESR_EWGF_Msk                                /*!<Error Warning Flag */
1984 #define CAN_ESR_EPVF_Pos       (1U)
1985 #define CAN_ESR_EPVF_Msk       (0x1UL << CAN_ESR_EPVF_Pos)                      /*!< 0x00000002 */
1986 #define CAN_ESR_EPVF           CAN_ESR_EPVF_Msk                                /*!<Error Passive Flag */
1987 #define CAN_ESR_BOFF_Pos       (2U)
1988 #define CAN_ESR_BOFF_Msk       (0x1UL << CAN_ESR_BOFF_Pos)                      /*!< 0x00000004 */
1989 #define CAN_ESR_BOFF           CAN_ESR_BOFF_Msk                                /*!<Bus-Off Flag */
1990 
1991 #define CAN_ESR_LEC_Pos        (4U)
1992 #define CAN_ESR_LEC_Msk        (0x7UL << CAN_ESR_LEC_Pos)                       /*!< 0x00000070 */
1993 #define CAN_ESR_LEC            CAN_ESR_LEC_Msk                                 /*!<LEC[2:0] bits (Last Error Code) */
1994 #define CAN_ESR_LEC_0          (0x1UL << CAN_ESR_LEC_Pos)                       /*!< 0x00000010 */
1995 #define CAN_ESR_LEC_1          (0x2UL << CAN_ESR_LEC_Pos)                       /*!< 0x00000020 */
1996 #define CAN_ESR_LEC_2          (0x4UL << CAN_ESR_LEC_Pos)                       /*!< 0x00000040 */
1997 
1998 #define CAN_ESR_TEC_Pos        (16U)
1999 #define CAN_ESR_TEC_Msk        (0xFFUL << CAN_ESR_TEC_Pos)                      /*!< 0x00FF0000 */
2000 #define CAN_ESR_TEC            CAN_ESR_TEC_Msk                                 /*!<Least significant byte of the 9-bit Transmit Error Counter */
2001 #define CAN_ESR_REC_Pos        (24U)
2002 #define CAN_ESR_REC_Msk        (0xFFUL << CAN_ESR_REC_Pos)                      /*!< 0xFF000000 */
2003 #define CAN_ESR_REC            CAN_ESR_REC_Msk                                 /*!<Receive Error Counter */
2004 
2005 /*******************  Bit definition for CAN_BTR register  ********************/
2006 #define CAN_BTR_BRP_Pos        (0U)
2007 #define CAN_BTR_BRP_Msk        (0x3FFUL << CAN_BTR_BRP_Pos)                     /*!< 0x000003FF */
2008 #define CAN_BTR_BRP            CAN_BTR_BRP_Msk                                 /*!<Baud Rate Prescaler */
2009 #define CAN_BTR_TS1_Pos        (16U)
2010 #define CAN_BTR_TS1_Msk        (0xFUL << CAN_BTR_TS1_Pos)                       /*!< 0x000F0000 */
2011 #define CAN_BTR_TS1            CAN_BTR_TS1_Msk                                 /*!<Time Segment 1 */
2012 #define CAN_BTR_TS1_0          (0x1UL << CAN_BTR_TS1_Pos)                       /*!< 0x00010000 */
2013 #define CAN_BTR_TS1_1          (0x2UL << CAN_BTR_TS1_Pos)                       /*!< 0x00020000 */
2014 #define CAN_BTR_TS1_2          (0x4UL << CAN_BTR_TS1_Pos)                       /*!< 0x00040000 */
2015 #define CAN_BTR_TS1_3          (0x8UL << CAN_BTR_TS1_Pos)                       /*!< 0x00080000 */
2016 #define CAN_BTR_TS2_Pos        (20U)
2017 #define CAN_BTR_TS2_Msk        (0x7UL << CAN_BTR_TS2_Pos)                       /*!< 0x00700000 */
2018 #define CAN_BTR_TS2            CAN_BTR_TS2_Msk                                 /*!<Time Segment 2 */
2019 #define CAN_BTR_TS2_0          (0x1UL << CAN_BTR_TS2_Pos)                       /*!< 0x00100000 */
2020 #define CAN_BTR_TS2_1          (0x2UL << CAN_BTR_TS2_Pos)                       /*!< 0x00200000 */
2021 #define CAN_BTR_TS2_2          (0x4UL << CAN_BTR_TS2_Pos)                       /*!< 0x00400000 */
2022 #define CAN_BTR_SJW_Pos        (24U)
2023 #define CAN_BTR_SJW_Msk        (0x3UL << CAN_BTR_SJW_Pos)                       /*!< 0x03000000 */
2024 #define CAN_BTR_SJW            CAN_BTR_SJW_Msk                                 /*!<Resynchronization Jump Width */
2025 #define CAN_BTR_SJW_0          (0x1UL << CAN_BTR_SJW_Pos)                       /*!< 0x01000000 */
2026 #define CAN_BTR_SJW_1          (0x2UL << CAN_BTR_SJW_Pos)                       /*!< 0x02000000 */
2027 #define CAN_BTR_LBKM_Pos       (30U)
2028 #define CAN_BTR_LBKM_Msk       (0x1UL << CAN_BTR_LBKM_Pos)                      /*!< 0x40000000 */
2029 #define CAN_BTR_LBKM           CAN_BTR_LBKM_Msk                                /*!<Loop Back Mode (Debug) */
2030 #define CAN_BTR_SILM_Pos       (31U)
2031 #define CAN_BTR_SILM_Msk       (0x1UL << CAN_BTR_SILM_Pos)                      /*!< 0x80000000 */
2032 #define CAN_BTR_SILM           CAN_BTR_SILM_Msk                                /*!<Silent Mode */
2033 
2034 
2035 /*!<Mailbox registers */
2036 /******************  Bit definition for CAN_TI0R register  ********************/
2037 #define CAN_TI0R_TXRQ_Pos      (0U)
2038 #define CAN_TI0R_TXRQ_Msk      (0x1UL << CAN_TI0R_TXRQ_Pos)                     /*!< 0x00000001 */
2039 #define CAN_TI0R_TXRQ          CAN_TI0R_TXRQ_Msk                               /*!<Transmit Mailbox Request */
2040 #define CAN_TI0R_RTR_Pos       (1U)
2041 #define CAN_TI0R_RTR_Msk       (0x1UL << CAN_TI0R_RTR_Pos)                      /*!< 0x00000002 */
2042 #define CAN_TI0R_RTR           CAN_TI0R_RTR_Msk                                /*!<Remote Transmission Request */
2043 #define CAN_TI0R_IDE_Pos       (2U)
2044 #define CAN_TI0R_IDE_Msk       (0x1UL << CAN_TI0R_IDE_Pos)                      /*!< 0x00000004 */
2045 #define CAN_TI0R_IDE           CAN_TI0R_IDE_Msk                                /*!<Identifier Extension */
2046 #define CAN_TI0R_EXID_Pos      (3U)
2047 #define CAN_TI0R_EXID_Msk      (0x3FFFFUL << CAN_TI0R_EXID_Pos)                 /*!< 0x001FFFF8 */
2048 #define CAN_TI0R_EXID          CAN_TI0R_EXID_Msk                               /*!<Extended Identifier */
2049 #define CAN_TI0R_STID_Pos      (21U)
2050 #define CAN_TI0R_STID_Msk      (0x7FFUL << CAN_TI0R_STID_Pos)                   /*!< 0xFFE00000 */
2051 #define CAN_TI0R_STID          CAN_TI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
2052 
2053 /******************  Bit definition for CAN_TDT0R register  *******************/
2054 #define CAN_TDT0R_DLC_Pos      (0U)
2055 #define CAN_TDT0R_DLC_Msk      (0xFUL << CAN_TDT0R_DLC_Pos)                     /*!< 0x0000000F */
2056 #define CAN_TDT0R_DLC          CAN_TDT0R_DLC_Msk                               /*!<Data Length Code */
2057 #define CAN_TDT0R_TGT_Pos      (8U)
2058 #define CAN_TDT0R_TGT_Msk      (0x1UL << CAN_TDT0R_TGT_Pos)                     /*!< 0x00000100 */
2059 #define CAN_TDT0R_TGT          CAN_TDT0R_TGT_Msk                               /*!<Transmit Global Time */
2060 #define CAN_TDT0R_TIME_Pos     (16U)
2061 #define CAN_TDT0R_TIME_Msk     (0xFFFFUL << CAN_TDT0R_TIME_Pos)                 /*!< 0xFFFF0000 */
2062 #define CAN_TDT0R_TIME         CAN_TDT0R_TIME_Msk                              /*!<Message Time Stamp */
2063 
2064 /******************  Bit definition for CAN_TDL0R register  *******************/
2065 #define CAN_TDL0R_DATA0_Pos    (0U)
2066 #define CAN_TDL0R_DATA0_Msk    (0xFFUL << CAN_TDL0R_DATA0_Pos)                  /*!< 0x000000FF */
2067 #define CAN_TDL0R_DATA0        CAN_TDL0R_DATA0_Msk                             /*!<Data byte 0 */
2068 #define CAN_TDL0R_DATA1_Pos    (8U)
2069 #define CAN_TDL0R_DATA1_Msk    (0xFFUL << CAN_TDL0R_DATA1_Pos)                  /*!< 0x0000FF00 */
2070 #define CAN_TDL0R_DATA1        CAN_TDL0R_DATA1_Msk                             /*!<Data byte 1 */
2071 #define CAN_TDL0R_DATA2_Pos    (16U)
2072 #define CAN_TDL0R_DATA2_Msk    (0xFFUL << CAN_TDL0R_DATA2_Pos)                  /*!< 0x00FF0000 */
2073 #define CAN_TDL0R_DATA2        CAN_TDL0R_DATA2_Msk                             /*!<Data byte 2 */
2074 #define CAN_TDL0R_DATA3_Pos    (24U)
2075 #define CAN_TDL0R_DATA3_Msk    (0xFFUL << CAN_TDL0R_DATA3_Pos)                  /*!< 0xFF000000 */
2076 #define CAN_TDL0R_DATA3        CAN_TDL0R_DATA3_Msk                             /*!<Data byte 3 */
2077 
2078 /******************  Bit definition for CAN_TDH0R register  *******************/
2079 #define CAN_TDH0R_DATA4_Pos    (0U)
2080 #define CAN_TDH0R_DATA4_Msk    (0xFFUL << CAN_TDH0R_DATA4_Pos)                  /*!< 0x000000FF */
2081 #define CAN_TDH0R_DATA4        CAN_TDH0R_DATA4_Msk                             /*!<Data byte 4 */
2082 #define CAN_TDH0R_DATA5_Pos    (8U)
2083 #define CAN_TDH0R_DATA5_Msk    (0xFFUL << CAN_TDH0R_DATA5_Pos)                  /*!< 0x0000FF00 */
2084 #define CAN_TDH0R_DATA5        CAN_TDH0R_DATA5_Msk                             /*!<Data byte 5 */
2085 #define CAN_TDH0R_DATA6_Pos    (16U)
2086 #define CAN_TDH0R_DATA6_Msk    (0xFFUL << CAN_TDH0R_DATA6_Pos)                  /*!< 0x00FF0000 */
2087 #define CAN_TDH0R_DATA6        CAN_TDH0R_DATA6_Msk                             /*!<Data byte 6 */
2088 #define CAN_TDH0R_DATA7_Pos    (24U)
2089 #define CAN_TDH0R_DATA7_Msk    (0xFFUL << CAN_TDH0R_DATA7_Pos)                  /*!< 0xFF000000 */
2090 #define CAN_TDH0R_DATA7        CAN_TDH0R_DATA7_Msk                             /*!<Data byte 7 */
2091 
2092 /*******************  Bit definition for CAN_TI1R register  *******************/
2093 #define CAN_TI1R_TXRQ_Pos      (0U)
2094 #define CAN_TI1R_TXRQ_Msk      (0x1UL << CAN_TI1R_TXRQ_Pos)                     /*!< 0x00000001 */
2095 #define CAN_TI1R_TXRQ          CAN_TI1R_TXRQ_Msk                               /*!<Transmit Mailbox Request */
2096 #define CAN_TI1R_RTR_Pos       (1U)
2097 #define CAN_TI1R_RTR_Msk       (0x1UL << CAN_TI1R_RTR_Pos)                      /*!< 0x00000002 */
2098 #define CAN_TI1R_RTR           CAN_TI1R_RTR_Msk                                /*!<Remote Transmission Request */
2099 #define CAN_TI1R_IDE_Pos       (2U)
2100 #define CAN_TI1R_IDE_Msk       (0x1UL << CAN_TI1R_IDE_Pos)                      /*!< 0x00000004 */
2101 #define CAN_TI1R_IDE           CAN_TI1R_IDE_Msk                                /*!<Identifier Extension */
2102 #define CAN_TI1R_EXID_Pos      (3U)
2103 #define CAN_TI1R_EXID_Msk      (0x3FFFFUL << CAN_TI1R_EXID_Pos)                 /*!< 0x001FFFF8 */
2104 #define CAN_TI1R_EXID          CAN_TI1R_EXID_Msk                               /*!<Extended Identifier */
2105 #define CAN_TI1R_STID_Pos      (21U)
2106 #define CAN_TI1R_STID_Msk      (0x7FFUL << CAN_TI1R_STID_Pos)                   /*!< 0xFFE00000 */
2107 #define CAN_TI1R_STID          CAN_TI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
2108 
2109 /*******************  Bit definition for CAN_TDT1R register  ******************/
2110 #define CAN_TDT1R_DLC_Pos      (0U)
2111 #define CAN_TDT1R_DLC_Msk      (0xFUL << CAN_TDT1R_DLC_Pos)                     /*!< 0x0000000F */
2112 #define CAN_TDT1R_DLC          CAN_TDT1R_DLC_Msk                               /*!<Data Length Code */
2113 #define CAN_TDT1R_TGT_Pos      (8U)
2114 #define CAN_TDT1R_TGT_Msk      (0x1UL << CAN_TDT1R_TGT_Pos)                     /*!< 0x00000100 */
2115 #define CAN_TDT1R_TGT          CAN_TDT1R_TGT_Msk                               /*!<Transmit Global Time */
2116 #define CAN_TDT1R_TIME_Pos     (16U)
2117 #define CAN_TDT1R_TIME_Msk     (0xFFFFUL << CAN_TDT1R_TIME_Pos)                 /*!< 0xFFFF0000 */
2118 #define CAN_TDT1R_TIME         CAN_TDT1R_TIME_Msk                              /*!<Message Time Stamp */
2119 
2120 /*******************  Bit definition for CAN_TDL1R register  ******************/
2121 #define CAN_TDL1R_DATA0_Pos    (0U)
2122 #define CAN_TDL1R_DATA0_Msk    (0xFFUL << CAN_TDL1R_DATA0_Pos)                  /*!< 0x000000FF */
2123 #define CAN_TDL1R_DATA0        CAN_TDL1R_DATA0_Msk                             /*!<Data byte 0 */
2124 #define CAN_TDL1R_DATA1_Pos    (8U)
2125 #define CAN_TDL1R_DATA1_Msk    (0xFFUL << CAN_TDL1R_DATA1_Pos)                  /*!< 0x0000FF00 */
2126 #define CAN_TDL1R_DATA1        CAN_TDL1R_DATA1_Msk                             /*!<Data byte 1 */
2127 #define CAN_TDL1R_DATA2_Pos    (16U)
2128 #define CAN_TDL1R_DATA2_Msk    (0xFFUL << CAN_TDL1R_DATA2_Pos)                  /*!< 0x00FF0000 */
2129 #define CAN_TDL1R_DATA2        CAN_TDL1R_DATA2_Msk                             /*!<Data byte 2 */
2130 #define CAN_TDL1R_DATA3_Pos    (24U)
2131 #define CAN_TDL1R_DATA3_Msk    (0xFFUL << CAN_TDL1R_DATA3_Pos)                  /*!< 0xFF000000 */
2132 #define CAN_TDL1R_DATA3        CAN_TDL1R_DATA3_Msk                             /*!<Data byte 3 */
2133 
2134 /*******************  Bit definition for CAN_TDH1R register  ******************/
2135 #define CAN_TDH1R_DATA4_Pos    (0U)
2136 #define CAN_TDH1R_DATA4_Msk    (0xFFUL << CAN_TDH1R_DATA4_Pos)                  /*!< 0x000000FF */
2137 #define CAN_TDH1R_DATA4        CAN_TDH1R_DATA4_Msk                             /*!<Data byte 4 */
2138 #define CAN_TDH1R_DATA5_Pos    (8U)
2139 #define CAN_TDH1R_DATA5_Msk    (0xFFUL << CAN_TDH1R_DATA5_Pos)                  /*!< 0x0000FF00 */
2140 #define CAN_TDH1R_DATA5        CAN_TDH1R_DATA5_Msk                             /*!<Data byte 5 */
2141 #define CAN_TDH1R_DATA6_Pos    (16U)
2142 #define CAN_TDH1R_DATA6_Msk    (0xFFUL << CAN_TDH1R_DATA6_Pos)                  /*!< 0x00FF0000 */
2143 #define CAN_TDH1R_DATA6        CAN_TDH1R_DATA6_Msk                             /*!<Data byte 6 */
2144 #define CAN_TDH1R_DATA7_Pos    (24U)
2145 #define CAN_TDH1R_DATA7_Msk    (0xFFUL << CAN_TDH1R_DATA7_Pos)                  /*!< 0xFF000000 */
2146 #define CAN_TDH1R_DATA7        CAN_TDH1R_DATA7_Msk                             /*!<Data byte 7 */
2147 
2148 /*******************  Bit definition for CAN_TI2R register  *******************/
2149 #define CAN_TI2R_TXRQ_Pos      (0U)
2150 #define CAN_TI2R_TXRQ_Msk      (0x1UL << CAN_TI2R_TXRQ_Pos)                     /*!< 0x00000001 */
2151 #define CAN_TI2R_TXRQ          CAN_TI2R_TXRQ_Msk                               /*!<Transmit Mailbox Request */
2152 #define CAN_TI2R_RTR_Pos       (1U)
2153 #define CAN_TI2R_RTR_Msk       (0x1UL << CAN_TI2R_RTR_Pos)                      /*!< 0x00000002 */
2154 #define CAN_TI2R_RTR           CAN_TI2R_RTR_Msk                                /*!<Remote Transmission Request */
2155 #define CAN_TI2R_IDE_Pos       (2U)
2156 #define CAN_TI2R_IDE_Msk       (0x1UL << CAN_TI2R_IDE_Pos)                      /*!< 0x00000004 */
2157 #define CAN_TI2R_IDE           CAN_TI2R_IDE_Msk                                /*!<Identifier Extension */
2158 #define CAN_TI2R_EXID_Pos      (3U)
2159 #define CAN_TI2R_EXID_Msk      (0x3FFFFUL << CAN_TI2R_EXID_Pos)                 /*!< 0x001FFFF8 */
2160 #define CAN_TI2R_EXID          CAN_TI2R_EXID_Msk                               /*!<Extended identifier */
2161 #define CAN_TI2R_STID_Pos      (21U)
2162 #define CAN_TI2R_STID_Msk      (0x7FFUL << CAN_TI2R_STID_Pos)                   /*!< 0xFFE00000 */
2163 #define CAN_TI2R_STID          CAN_TI2R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
2164 
2165 /*******************  Bit definition for CAN_TDT2R register  ******************/
2166 #define CAN_TDT2R_DLC_Pos      (0U)
2167 #define CAN_TDT2R_DLC_Msk      (0xFUL << CAN_TDT2R_DLC_Pos)                     /*!< 0x0000000F */
2168 #define CAN_TDT2R_DLC          CAN_TDT2R_DLC_Msk                               /*!<Data Length Code */
2169 #define CAN_TDT2R_TGT_Pos      (8U)
2170 #define CAN_TDT2R_TGT_Msk      (0x1UL << CAN_TDT2R_TGT_Pos)                     /*!< 0x00000100 */
2171 #define CAN_TDT2R_TGT          CAN_TDT2R_TGT_Msk                               /*!<Transmit Global Time */
2172 #define CAN_TDT2R_TIME_Pos     (16U)
2173 #define CAN_TDT2R_TIME_Msk     (0xFFFFUL << CAN_TDT2R_TIME_Pos)                 /*!< 0xFFFF0000 */
2174 #define CAN_TDT2R_TIME         CAN_TDT2R_TIME_Msk                              /*!<Message Time Stamp */
2175 
2176 /*******************  Bit definition for CAN_TDL2R register  ******************/
2177 #define CAN_TDL2R_DATA0_Pos    (0U)
2178 #define CAN_TDL2R_DATA0_Msk    (0xFFUL << CAN_TDL2R_DATA0_Pos)                  /*!< 0x000000FF */
2179 #define CAN_TDL2R_DATA0        CAN_TDL2R_DATA0_Msk                             /*!<Data byte 0 */
2180 #define CAN_TDL2R_DATA1_Pos    (8U)
2181 #define CAN_TDL2R_DATA1_Msk    (0xFFUL << CAN_TDL2R_DATA1_Pos)                  /*!< 0x0000FF00 */
2182 #define CAN_TDL2R_DATA1        CAN_TDL2R_DATA1_Msk                             /*!<Data byte 1 */
2183 #define CAN_TDL2R_DATA2_Pos    (16U)
2184 #define CAN_TDL2R_DATA2_Msk    (0xFFUL << CAN_TDL2R_DATA2_Pos)                  /*!< 0x00FF0000 */
2185 #define CAN_TDL2R_DATA2        CAN_TDL2R_DATA2_Msk                             /*!<Data byte 2 */
2186 #define CAN_TDL2R_DATA3_Pos    (24U)
2187 #define CAN_TDL2R_DATA3_Msk    (0xFFUL << CAN_TDL2R_DATA3_Pos)                  /*!< 0xFF000000 */
2188 #define CAN_TDL2R_DATA3        CAN_TDL2R_DATA3_Msk                             /*!<Data byte 3 */
2189 
2190 /*******************  Bit definition for CAN_TDH2R register  ******************/
2191 #define CAN_TDH2R_DATA4_Pos    (0U)
2192 #define CAN_TDH2R_DATA4_Msk    (0xFFUL << CAN_TDH2R_DATA4_Pos)                  /*!< 0x000000FF */
2193 #define CAN_TDH2R_DATA4        CAN_TDH2R_DATA4_Msk                             /*!<Data byte 4 */
2194 #define CAN_TDH2R_DATA5_Pos    (8U)
2195 #define CAN_TDH2R_DATA5_Msk    (0xFFUL << CAN_TDH2R_DATA5_Pos)                  /*!< 0x0000FF00 */
2196 #define CAN_TDH2R_DATA5        CAN_TDH2R_DATA5_Msk                             /*!<Data byte 5 */
2197 #define CAN_TDH2R_DATA6_Pos    (16U)
2198 #define CAN_TDH2R_DATA6_Msk    (0xFFUL << CAN_TDH2R_DATA6_Pos)                  /*!< 0x00FF0000 */
2199 #define CAN_TDH2R_DATA6        CAN_TDH2R_DATA6_Msk                             /*!<Data byte 6 */
2200 #define CAN_TDH2R_DATA7_Pos    (24U)
2201 #define CAN_TDH2R_DATA7_Msk    (0xFFUL << CAN_TDH2R_DATA7_Pos)                  /*!< 0xFF000000 */
2202 #define CAN_TDH2R_DATA7        CAN_TDH2R_DATA7_Msk                             /*!<Data byte 7 */
2203 
2204 /*******************  Bit definition for CAN_RI0R register  *******************/
2205 #define CAN_RI0R_RTR_Pos       (1U)
2206 #define CAN_RI0R_RTR_Msk       (0x1UL << CAN_RI0R_RTR_Pos)                      /*!< 0x00000002 */
2207 #define CAN_RI0R_RTR           CAN_RI0R_RTR_Msk                                /*!<Remote Transmission Request */
2208 #define CAN_RI0R_IDE_Pos       (2U)
2209 #define CAN_RI0R_IDE_Msk       (0x1UL << CAN_RI0R_IDE_Pos)                      /*!< 0x00000004 */
2210 #define CAN_RI0R_IDE           CAN_RI0R_IDE_Msk                                /*!<Identifier Extension */
2211 #define CAN_RI0R_EXID_Pos      (3U)
2212 #define CAN_RI0R_EXID_Msk      (0x3FFFFUL << CAN_RI0R_EXID_Pos)                 /*!< 0x001FFFF8 */
2213 #define CAN_RI0R_EXID          CAN_RI0R_EXID_Msk                               /*!<Extended Identifier */
2214 #define CAN_RI0R_STID_Pos      (21U)
2215 #define CAN_RI0R_STID_Msk      (0x7FFUL << CAN_RI0R_STID_Pos)                   /*!< 0xFFE00000 */
2216 #define CAN_RI0R_STID          CAN_RI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
2217 
2218 /*******************  Bit definition for CAN_RDT0R register  ******************/
2219 #define CAN_RDT0R_DLC_Pos      (0U)
2220 #define CAN_RDT0R_DLC_Msk      (0xFUL << CAN_RDT0R_DLC_Pos)                     /*!< 0x0000000F */
2221 #define CAN_RDT0R_DLC          CAN_RDT0R_DLC_Msk                               /*!<Data Length Code */
2222 #define CAN_RDT0R_FMI_Pos      (8U)
2223 #define CAN_RDT0R_FMI_Msk      (0xFFUL << CAN_RDT0R_FMI_Pos)                    /*!< 0x0000FF00 */
2224 #define CAN_RDT0R_FMI          CAN_RDT0R_FMI_Msk                               /*!<Filter Match Index */
2225 #define CAN_RDT0R_TIME_Pos     (16U)
2226 #define CAN_RDT0R_TIME_Msk     (0xFFFFUL << CAN_RDT0R_TIME_Pos)                 /*!< 0xFFFF0000 */
2227 #define CAN_RDT0R_TIME         CAN_RDT0R_TIME_Msk                              /*!<Message Time Stamp */
2228 
2229 /*******************  Bit definition for CAN_RDL0R register  ******************/
2230 #define CAN_RDL0R_DATA0_Pos    (0U)
2231 #define CAN_RDL0R_DATA0_Msk    (0xFFUL << CAN_RDL0R_DATA0_Pos)                  /*!< 0x000000FF */
2232 #define CAN_RDL0R_DATA0        CAN_RDL0R_DATA0_Msk                             /*!<Data byte 0 */
2233 #define CAN_RDL0R_DATA1_Pos    (8U)
2234 #define CAN_RDL0R_DATA1_Msk    (0xFFUL << CAN_RDL0R_DATA1_Pos)                  /*!< 0x0000FF00 */
2235 #define CAN_RDL0R_DATA1        CAN_RDL0R_DATA1_Msk                             /*!<Data byte 1 */
2236 #define CAN_RDL0R_DATA2_Pos    (16U)
2237 #define CAN_RDL0R_DATA2_Msk    (0xFFUL << CAN_RDL0R_DATA2_Pos)                  /*!< 0x00FF0000 */
2238 #define CAN_RDL0R_DATA2        CAN_RDL0R_DATA2_Msk                             /*!<Data byte 2 */
2239 #define CAN_RDL0R_DATA3_Pos    (24U)
2240 #define CAN_RDL0R_DATA3_Msk    (0xFFUL << CAN_RDL0R_DATA3_Pos)                  /*!< 0xFF000000 */
2241 #define CAN_RDL0R_DATA3        CAN_RDL0R_DATA3_Msk                             /*!<Data byte 3 */
2242 
2243 /*******************  Bit definition for CAN_RDH0R register  ******************/
2244 #define CAN_RDH0R_DATA4_Pos    (0U)
2245 #define CAN_RDH0R_DATA4_Msk    (0xFFUL << CAN_RDH0R_DATA4_Pos)                  /*!< 0x000000FF */
2246 #define CAN_RDH0R_DATA4        CAN_RDH0R_DATA4_Msk                             /*!<Data byte 4 */
2247 #define CAN_RDH0R_DATA5_Pos    (8U)
2248 #define CAN_RDH0R_DATA5_Msk    (0xFFUL << CAN_RDH0R_DATA5_Pos)                  /*!< 0x0000FF00 */
2249 #define CAN_RDH0R_DATA5        CAN_RDH0R_DATA5_Msk                             /*!<Data byte 5 */
2250 #define CAN_RDH0R_DATA6_Pos    (16U)
2251 #define CAN_RDH0R_DATA6_Msk    (0xFFUL << CAN_RDH0R_DATA6_Pos)                  /*!< 0x00FF0000 */
2252 #define CAN_RDH0R_DATA6        CAN_RDH0R_DATA6_Msk                             /*!<Data byte 6 */
2253 #define CAN_RDH0R_DATA7_Pos    (24U)
2254 #define CAN_RDH0R_DATA7_Msk    (0xFFUL << CAN_RDH0R_DATA7_Pos)                  /*!< 0xFF000000 */
2255 #define CAN_RDH0R_DATA7        CAN_RDH0R_DATA7_Msk                             /*!<Data byte 7 */
2256 
2257 /*******************  Bit definition for CAN_RI1R register  *******************/
2258 #define CAN_RI1R_RTR_Pos       (1U)
2259 #define CAN_RI1R_RTR_Msk       (0x1UL << CAN_RI1R_RTR_Pos)                      /*!< 0x00000002 */
2260 #define CAN_RI1R_RTR           CAN_RI1R_RTR_Msk                                /*!<Remote Transmission Request */
2261 #define CAN_RI1R_IDE_Pos       (2U)
2262 #define CAN_RI1R_IDE_Msk       (0x1UL << CAN_RI1R_IDE_Pos)                      /*!< 0x00000004 */
2263 #define CAN_RI1R_IDE           CAN_RI1R_IDE_Msk                                /*!<Identifier Extension */
2264 #define CAN_RI1R_EXID_Pos      (3U)
2265 #define CAN_RI1R_EXID_Msk      (0x3FFFFUL << CAN_RI1R_EXID_Pos)                 /*!< 0x001FFFF8 */
2266 #define CAN_RI1R_EXID          CAN_RI1R_EXID_Msk                               /*!<Extended identifier */
2267 #define CAN_RI1R_STID_Pos      (21U)
2268 #define CAN_RI1R_STID_Msk      (0x7FFUL << CAN_RI1R_STID_Pos)                   /*!< 0xFFE00000 */
2269 #define CAN_RI1R_STID          CAN_RI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
2270 
2271 /*******************  Bit definition for CAN_RDT1R register  ******************/
2272 #define CAN_RDT1R_DLC_Pos      (0U)
2273 #define CAN_RDT1R_DLC_Msk      (0xFUL << CAN_RDT1R_DLC_Pos)                     /*!< 0x0000000F */
2274 #define CAN_RDT1R_DLC          CAN_RDT1R_DLC_Msk                               /*!<Data Length Code */
2275 #define CAN_RDT1R_FMI_Pos      (8U)
2276 #define CAN_RDT1R_FMI_Msk      (0xFFUL << CAN_RDT1R_FMI_Pos)                    /*!< 0x0000FF00 */
2277 #define CAN_RDT1R_FMI          CAN_RDT1R_FMI_Msk                               /*!<Filter Match Index */
2278 #define CAN_RDT1R_TIME_Pos     (16U)
2279 #define CAN_RDT1R_TIME_Msk     (0xFFFFUL << CAN_RDT1R_TIME_Pos)                 /*!< 0xFFFF0000 */
2280 #define CAN_RDT1R_TIME         CAN_RDT1R_TIME_Msk                              /*!<Message Time Stamp */
2281 
2282 /*******************  Bit definition for CAN_RDL1R register  ******************/
2283 #define CAN_RDL1R_DATA0_Pos    (0U)
2284 #define CAN_RDL1R_DATA0_Msk    (0xFFUL << CAN_RDL1R_DATA0_Pos)                  /*!< 0x000000FF */
2285 #define CAN_RDL1R_DATA0        CAN_RDL1R_DATA0_Msk                             /*!<Data byte 0 */
2286 #define CAN_RDL1R_DATA1_Pos    (8U)
2287 #define CAN_RDL1R_DATA1_Msk    (0xFFUL << CAN_RDL1R_DATA1_Pos)                  /*!< 0x0000FF00 */
2288 #define CAN_RDL1R_DATA1        CAN_RDL1R_DATA1_Msk                             /*!<Data byte 1 */
2289 #define CAN_RDL1R_DATA2_Pos    (16U)
2290 #define CAN_RDL1R_DATA2_Msk    (0xFFUL << CAN_RDL1R_DATA2_Pos)                  /*!< 0x00FF0000 */
2291 #define CAN_RDL1R_DATA2        CAN_RDL1R_DATA2_Msk                             /*!<Data byte 2 */
2292 #define CAN_RDL1R_DATA3_Pos    (24U)
2293 #define CAN_RDL1R_DATA3_Msk    (0xFFUL << CAN_RDL1R_DATA3_Pos)                  /*!< 0xFF000000 */
2294 #define CAN_RDL1R_DATA3        CAN_RDL1R_DATA3_Msk                             /*!<Data byte 3 */
2295 
2296 /*******************  Bit definition for CAN_RDH1R register  ******************/
2297 #define CAN_RDH1R_DATA4_Pos    (0U)
2298 #define CAN_RDH1R_DATA4_Msk    (0xFFUL << CAN_RDH1R_DATA4_Pos)                  /*!< 0x000000FF */
2299 #define CAN_RDH1R_DATA4        CAN_RDH1R_DATA4_Msk                             /*!<Data byte 4 */
2300 #define CAN_RDH1R_DATA5_Pos    (8U)
2301 #define CAN_RDH1R_DATA5_Msk    (0xFFUL << CAN_RDH1R_DATA5_Pos)                  /*!< 0x0000FF00 */
2302 #define CAN_RDH1R_DATA5        CAN_RDH1R_DATA5_Msk                             /*!<Data byte 5 */
2303 #define CAN_RDH1R_DATA6_Pos    (16U)
2304 #define CAN_RDH1R_DATA6_Msk    (0xFFUL << CAN_RDH1R_DATA6_Pos)                  /*!< 0x00FF0000 */
2305 #define CAN_RDH1R_DATA6        CAN_RDH1R_DATA6_Msk                             /*!<Data byte 6 */
2306 #define CAN_RDH1R_DATA7_Pos    (24U)
2307 #define CAN_RDH1R_DATA7_Msk    (0xFFUL << CAN_RDH1R_DATA7_Pos)                  /*!< 0xFF000000 */
2308 #define CAN_RDH1R_DATA7        CAN_RDH1R_DATA7_Msk                             /*!<Data byte 7 */
2309 
2310 /*!<CAN filter registers */
2311 /*******************  Bit definition for CAN_FMR register  ********************/
2312 #define CAN_FMR_FINIT_Pos      (0U)
2313 #define CAN_FMR_FINIT_Msk      (0x1UL << CAN_FMR_FINIT_Pos)                     /*!< 0x00000001 */
2314 #define CAN_FMR_FINIT          CAN_FMR_FINIT_Msk                               /*!<Filter Init Mode */
2315 #define CAN_FMR_CAN2SB_Pos     (8U)
2316 #define CAN_FMR_CAN2SB_Msk     (0x3FUL << CAN_FMR_CAN2SB_Pos)                   /*!< 0x00003F00 */
2317 #define CAN_FMR_CAN2SB         CAN_FMR_CAN2SB_Msk                              /*!<CAN2 start bank */
2318 
2319 /*******************  Bit definition for CAN_FM1R register  *******************/
2320 #define CAN_FM1R_FBM_Pos       (0U)
2321 #define CAN_FM1R_FBM_Msk       (0xFFFFFFFUL << CAN_FM1R_FBM_Pos)                /*!< 0x0FFFFFFF */
2322 #define CAN_FM1R_FBM           CAN_FM1R_FBM_Msk                                /*!<Filter Mode */
2323 #define CAN_FM1R_FBM0_Pos      (0U)
2324 #define CAN_FM1R_FBM0_Msk      (0x1UL << CAN_FM1R_FBM0_Pos)                     /*!< 0x00000001 */
2325 #define CAN_FM1R_FBM0          CAN_FM1R_FBM0_Msk                               /*!<Filter Init Mode bit 0 */
2326 #define CAN_FM1R_FBM1_Pos      (1U)
2327 #define CAN_FM1R_FBM1_Msk      (0x1UL << CAN_FM1R_FBM1_Pos)                     /*!< 0x00000002 */
2328 #define CAN_FM1R_FBM1          CAN_FM1R_FBM1_Msk                               /*!<Filter Init Mode bit 1 */
2329 #define CAN_FM1R_FBM2_Pos      (2U)
2330 #define CAN_FM1R_FBM2_Msk      (0x1UL << CAN_FM1R_FBM2_Pos)                     /*!< 0x00000004 */
2331 #define CAN_FM1R_FBM2          CAN_FM1R_FBM2_Msk                               /*!<Filter Init Mode bit 2 */
2332 #define CAN_FM1R_FBM3_Pos      (3U)
2333 #define CAN_FM1R_FBM3_Msk      (0x1UL << CAN_FM1R_FBM3_Pos)                     /*!< 0x00000008 */
2334 #define CAN_FM1R_FBM3          CAN_FM1R_FBM3_Msk                               /*!<Filter Init Mode bit 3 */
2335 #define CAN_FM1R_FBM4_Pos      (4U)
2336 #define CAN_FM1R_FBM4_Msk      (0x1UL << CAN_FM1R_FBM4_Pos)                     /*!< 0x00000010 */
2337 #define CAN_FM1R_FBM4          CAN_FM1R_FBM4_Msk                               /*!<Filter Init Mode bit 4 */
2338 #define CAN_FM1R_FBM5_Pos      (5U)
2339 #define CAN_FM1R_FBM5_Msk      (0x1UL << CAN_FM1R_FBM5_Pos)                     /*!< 0x00000020 */
2340 #define CAN_FM1R_FBM5          CAN_FM1R_FBM5_Msk                               /*!<Filter Init Mode bit 5 */
2341 #define CAN_FM1R_FBM6_Pos      (6U)
2342 #define CAN_FM1R_FBM6_Msk      (0x1UL << CAN_FM1R_FBM6_Pos)                     /*!< 0x00000040 */
2343 #define CAN_FM1R_FBM6          CAN_FM1R_FBM6_Msk                               /*!<Filter Init Mode bit 6 */
2344 #define CAN_FM1R_FBM7_Pos      (7U)
2345 #define CAN_FM1R_FBM7_Msk      (0x1UL << CAN_FM1R_FBM7_Pos)                     /*!< 0x00000080 */
2346 #define CAN_FM1R_FBM7          CAN_FM1R_FBM7_Msk                               /*!<Filter Init Mode bit 7 */
2347 #define CAN_FM1R_FBM8_Pos      (8U)
2348 #define CAN_FM1R_FBM8_Msk      (0x1UL << CAN_FM1R_FBM8_Pos)                     /*!< 0x00000100 */
2349 #define CAN_FM1R_FBM8          CAN_FM1R_FBM8_Msk                               /*!<Filter Init Mode bit 8 */
2350 #define CAN_FM1R_FBM9_Pos      (9U)
2351 #define CAN_FM1R_FBM9_Msk      (0x1UL << CAN_FM1R_FBM9_Pos)                     /*!< 0x00000200 */
2352 #define CAN_FM1R_FBM9          CAN_FM1R_FBM9_Msk                               /*!<Filter Init Mode bit 9 */
2353 #define CAN_FM1R_FBM10_Pos     (10U)
2354 #define CAN_FM1R_FBM10_Msk     (0x1UL << CAN_FM1R_FBM10_Pos)                    /*!< 0x00000400 */
2355 #define CAN_FM1R_FBM10         CAN_FM1R_FBM10_Msk                              /*!<Filter Init Mode bit 10 */
2356 #define CAN_FM1R_FBM11_Pos     (11U)
2357 #define CAN_FM1R_FBM11_Msk     (0x1UL << CAN_FM1R_FBM11_Pos)                    /*!< 0x00000800 */
2358 #define CAN_FM1R_FBM11         CAN_FM1R_FBM11_Msk                              /*!<Filter Init Mode bit 11 */
2359 #define CAN_FM1R_FBM12_Pos     (12U)
2360 #define CAN_FM1R_FBM12_Msk     (0x1UL << CAN_FM1R_FBM12_Pos)                    /*!< 0x00001000 */
2361 #define CAN_FM1R_FBM12         CAN_FM1R_FBM12_Msk                              /*!<Filter Init Mode bit 12 */
2362 #define CAN_FM1R_FBM13_Pos     (13U)
2363 #define CAN_FM1R_FBM13_Msk     (0x1UL << CAN_FM1R_FBM13_Pos)                    /*!< 0x00002000 */
2364 #define CAN_FM1R_FBM13         CAN_FM1R_FBM13_Msk                              /*!<Filter Init Mode bit 13 */
2365 #define CAN_FM1R_FBM14_Pos     (14U)
2366 #define CAN_FM1R_FBM14_Msk     (0x1UL << CAN_FM1R_FBM14_Pos)                    /*!< 0x00004000 */
2367 #define CAN_FM1R_FBM14         CAN_FM1R_FBM14_Msk                              /*!<Filter Init Mode bit 14 */
2368 #define CAN_FM1R_FBM15_Pos     (15U)
2369 #define CAN_FM1R_FBM15_Msk     (0x1UL << CAN_FM1R_FBM15_Pos)                    /*!< 0x00008000 */
2370 #define CAN_FM1R_FBM15         CAN_FM1R_FBM15_Msk                              /*!<Filter Init Mode bit 15 */
2371 #define CAN_FM1R_FBM16_Pos     (16U)
2372 #define CAN_FM1R_FBM16_Msk     (0x1UL << CAN_FM1R_FBM16_Pos)                    /*!< 0x00010000 */
2373 #define CAN_FM1R_FBM16         CAN_FM1R_FBM16_Msk                              /*!<Filter Init Mode bit 16 */
2374 #define CAN_FM1R_FBM17_Pos     (17U)
2375 #define CAN_FM1R_FBM17_Msk     (0x1UL << CAN_FM1R_FBM17_Pos)                    /*!< 0x00020000 */
2376 #define CAN_FM1R_FBM17         CAN_FM1R_FBM17_Msk                              /*!<Filter Init Mode bit 17 */
2377 #define CAN_FM1R_FBM18_Pos     (18U)
2378 #define CAN_FM1R_FBM18_Msk     (0x1UL << CAN_FM1R_FBM18_Pos)                    /*!< 0x00040000 */
2379 #define CAN_FM1R_FBM18         CAN_FM1R_FBM18_Msk                              /*!<Filter Init Mode bit 18 */
2380 #define CAN_FM1R_FBM19_Pos     (19U)
2381 #define CAN_FM1R_FBM19_Msk     (0x1UL << CAN_FM1R_FBM19_Pos)                    /*!< 0x00080000 */
2382 #define CAN_FM1R_FBM19         CAN_FM1R_FBM19_Msk                              /*!<Filter Init Mode bit 19 */
2383 #define CAN_FM1R_FBM20_Pos     (20U)
2384 #define CAN_FM1R_FBM20_Msk     (0x1UL << CAN_FM1R_FBM20_Pos)                    /*!< 0x00100000 */
2385 #define CAN_FM1R_FBM20         CAN_FM1R_FBM20_Msk                              /*!<Filter Init Mode bit 20 */
2386 #define CAN_FM1R_FBM21_Pos     (21U)
2387 #define CAN_FM1R_FBM21_Msk     (0x1UL << CAN_FM1R_FBM21_Pos)                    /*!< 0x00200000 */
2388 #define CAN_FM1R_FBM21         CAN_FM1R_FBM21_Msk                              /*!<Filter Init Mode bit 21 */
2389 #define CAN_FM1R_FBM22_Pos     (22U)
2390 #define CAN_FM1R_FBM22_Msk     (0x1UL << CAN_FM1R_FBM22_Pos)                    /*!< 0x00400000 */
2391 #define CAN_FM1R_FBM22         CAN_FM1R_FBM22_Msk                              /*!<Filter Init Mode bit 22 */
2392 #define CAN_FM1R_FBM23_Pos     (23U)
2393 #define CAN_FM1R_FBM23_Msk     (0x1UL << CAN_FM1R_FBM23_Pos)                    /*!< 0x00800000 */
2394 #define CAN_FM1R_FBM23         CAN_FM1R_FBM23_Msk                              /*!<Filter Init Mode bit 23 */
2395 #define CAN_FM1R_FBM24_Pos     (24U)
2396 #define CAN_FM1R_FBM24_Msk     (0x1UL << CAN_FM1R_FBM24_Pos)                    /*!< 0x01000000 */
2397 #define CAN_FM1R_FBM24         CAN_FM1R_FBM24_Msk                              /*!<Filter Init Mode bit 24 */
2398 #define CAN_FM1R_FBM25_Pos     (25U)
2399 #define CAN_FM1R_FBM25_Msk     (0x1UL << CAN_FM1R_FBM25_Pos)                    /*!< 0x02000000 */
2400 #define CAN_FM1R_FBM25         CAN_FM1R_FBM25_Msk                              /*!<Filter Init Mode bit 25 */
2401 #define CAN_FM1R_FBM26_Pos     (26U)
2402 #define CAN_FM1R_FBM26_Msk     (0x1UL << CAN_FM1R_FBM26_Pos)                    /*!< 0x04000000 */
2403 #define CAN_FM1R_FBM26         CAN_FM1R_FBM26_Msk                              /*!<Filter Init Mode bit 26 */
2404 #define CAN_FM1R_FBM27_Pos     (27U)
2405 #define CAN_FM1R_FBM27_Msk     (0x1UL << CAN_FM1R_FBM27_Pos)                    /*!< 0x08000000 */
2406 #define CAN_FM1R_FBM27         CAN_FM1R_FBM27_Msk                              /*!<Filter Init Mode bit 27 */
2407 
2408 /*******************  Bit definition for CAN_FS1R register  *******************/
2409 #define CAN_FS1R_FSC_Pos       (0U)
2410 #define CAN_FS1R_FSC_Msk       (0xFFFFFFFUL << CAN_FS1R_FSC_Pos)                /*!< 0x0FFFFFFF */
2411 #define CAN_FS1R_FSC           CAN_FS1R_FSC_Msk                                /*!<Filter Scale Configuration */
2412 #define CAN_FS1R_FSC0_Pos      (0U)
2413 #define CAN_FS1R_FSC0_Msk      (0x1UL << CAN_FS1R_FSC0_Pos)                     /*!< 0x00000001 */
2414 #define CAN_FS1R_FSC0          CAN_FS1R_FSC0_Msk                               /*!<Filter Scale Configuration bit 0 */
2415 #define CAN_FS1R_FSC1_Pos      (1U)
2416 #define CAN_FS1R_FSC1_Msk      (0x1UL << CAN_FS1R_FSC1_Pos)                     /*!< 0x00000002 */
2417 #define CAN_FS1R_FSC1          CAN_FS1R_FSC1_Msk                               /*!<Filter Scale Configuration bit 1 */
2418 #define CAN_FS1R_FSC2_Pos      (2U)
2419 #define CAN_FS1R_FSC2_Msk      (0x1UL << CAN_FS1R_FSC2_Pos)                     /*!< 0x00000004 */
2420 #define CAN_FS1R_FSC2          CAN_FS1R_FSC2_Msk                               /*!<Filter Scale Configuration bit 2 */
2421 #define CAN_FS1R_FSC3_Pos      (3U)
2422 #define CAN_FS1R_FSC3_Msk      (0x1UL << CAN_FS1R_FSC3_Pos)                     /*!< 0x00000008 */
2423 #define CAN_FS1R_FSC3          CAN_FS1R_FSC3_Msk                               /*!<Filter Scale Configuration bit 3 */
2424 #define CAN_FS1R_FSC4_Pos      (4U)
2425 #define CAN_FS1R_FSC4_Msk      (0x1UL << CAN_FS1R_FSC4_Pos)                     /*!< 0x00000010 */
2426 #define CAN_FS1R_FSC4          CAN_FS1R_FSC4_Msk                               /*!<Filter Scale Configuration bit 4 */
2427 #define CAN_FS1R_FSC5_Pos      (5U)
2428 #define CAN_FS1R_FSC5_Msk      (0x1UL << CAN_FS1R_FSC5_Pos)                     /*!< 0x00000020 */
2429 #define CAN_FS1R_FSC5          CAN_FS1R_FSC5_Msk                               /*!<Filter Scale Configuration bit 5 */
2430 #define CAN_FS1R_FSC6_Pos      (6U)
2431 #define CAN_FS1R_FSC6_Msk      (0x1UL << CAN_FS1R_FSC6_Pos)                     /*!< 0x00000040 */
2432 #define CAN_FS1R_FSC6          CAN_FS1R_FSC6_Msk                               /*!<Filter Scale Configuration bit 6 */
2433 #define CAN_FS1R_FSC7_Pos      (7U)
2434 #define CAN_FS1R_FSC7_Msk      (0x1UL << CAN_FS1R_FSC7_Pos)                     /*!< 0x00000080 */
2435 #define CAN_FS1R_FSC7          CAN_FS1R_FSC7_Msk                               /*!<Filter Scale Configuration bit 7 */
2436 #define CAN_FS1R_FSC8_Pos      (8U)
2437 #define CAN_FS1R_FSC8_Msk      (0x1UL << CAN_FS1R_FSC8_Pos)                     /*!< 0x00000100 */
2438 #define CAN_FS1R_FSC8          CAN_FS1R_FSC8_Msk                               /*!<Filter Scale Configuration bit 8 */
2439 #define CAN_FS1R_FSC9_Pos      (9U)
2440 #define CAN_FS1R_FSC9_Msk      (0x1UL << CAN_FS1R_FSC9_Pos)                     /*!< 0x00000200 */
2441 #define CAN_FS1R_FSC9          CAN_FS1R_FSC9_Msk                               /*!<Filter Scale Configuration bit 9 */
2442 #define CAN_FS1R_FSC10_Pos     (10U)
2443 #define CAN_FS1R_FSC10_Msk     (0x1UL << CAN_FS1R_FSC10_Pos)                    /*!< 0x00000400 */
2444 #define CAN_FS1R_FSC10         CAN_FS1R_FSC10_Msk                              /*!<Filter Scale Configuration bit 10 */
2445 #define CAN_FS1R_FSC11_Pos     (11U)
2446 #define CAN_FS1R_FSC11_Msk     (0x1UL << CAN_FS1R_FSC11_Pos)                    /*!< 0x00000800 */
2447 #define CAN_FS1R_FSC11         CAN_FS1R_FSC11_Msk                              /*!<Filter Scale Configuration bit 11 */
2448 #define CAN_FS1R_FSC12_Pos     (12U)
2449 #define CAN_FS1R_FSC12_Msk     (0x1UL << CAN_FS1R_FSC12_Pos)                    /*!< 0x00001000 */
2450 #define CAN_FS1R_FSC12         CAN_FS1R_FSC12_Msk                              /*!<Filter Scale Configuration bit 12 */
2451 #define CAN_FS1R_FSC13_Pos     (13U)
2452 #define CAN_FS1R_FSC13_Msk     (0x1UL << CAN_FS1R_FSC13_Pos)                    /*!< 0x00002000 */
2453 #define CAN_FS1R_FSC13         CAN_FS1R_FSC13_Msk                              /*!<Filter Scale Configuration bit 13 */
2454 #define CAN_FS1R_FSC14_Pos     (14U)
2455 #define CAN_FS1R_FSC14_Msk     (0x1UL << CAN_FS1R_FSC14_Pos)                    /*!< 0x00004000 */
2456 #define CAN_FS1R_FSC14         CAN_FS1R_FSC14_Msk                              /*!<Filter Scale Configuration bit 14 */
2457 #define CAN_FS1R_FSC15_Pos     (15U)
2458 #define CAN_FS1R_FSC15_Msk     (0x1UL << CAN_FS1R_FSC15_Pos)                    /*!< 0x00008000 */
2459 #define CAN_FS1R_FSC15         CAN_FS1R_FSC15_Msk                              /*!<Filter Scale Configuration bit 15 */
2460 #define CAN_FS1R_FSC16_Pos     (16U)
2461 #define CAN_FS1R_FSC16_Msk     (0x1UL << CAN_FS1R_FSC16_Pos)                    /*!< 0x00010000 */
2462 #define CAN_FS1R_FSC16         CAN_FS1R_FSC16_Msk                              /*!<Filter Scale Configuration bit 16 */
2463 #define CAN_FS1R_FSC17_Pos     (17U)
2464 #define CAN_FS1R_FSC17_Msk     (0x1UL << CAN_FS1R_FSC17_Pos)                    /*!< 0x00020000 */
2465 #define CAN_FS1R_FSC17         CAN_FS1R_FSC17_Msk                              /*!<Filter Scale Configuration bit 17 */
2466 #define CAN_FS1R_FSC18_Pos     (18U)
2467 #define CAN_FS1R_FSC18_Msk     (0x1UL << CAN_FS1R_FSC18_Pos)                    /*!< 0x00040000 */
2468 #define CAN_FS1R_FSC18         CAN_FS1R_FSC18_Msk                              /*!<Filter Scale Configuration bit 18 */
2469 #define CAN_FS1R_FSC19_Pos     (19U)
2470 #define CAN_FS1R_FSC19_Msk     (0x1UL << CAN_FS1R_FSC19_Pos)                    /*!< 0x00080000 */
2471 #define CAN_FS1R_FSC19         CAN_FS1R_FSC19_Msk                              /*!<Filter Scale Configuration bit 19 */
2472 #define CAN_FS1R_FSC20_Pos     (20U)
2473 #define CAN_FS1R_FSC20_Msk     (0x1UL << CAN_FS1R_FSC20_Pos)                    /*!< 0x00100000 */
2474 #define CAN_FS1R_FSC20         CAN_FS1R_FSC20_Msk                              /*!<Filter Scale Configuration bit 20 */
2475 #define CAN_FS1R_FSC21_Pos     (21U)
2476 #define CAN_FS1R_FSC21_Msk     (0x1UL << CAN_FS1R_FSC21_Pos)                    /*!< 0x00200000 */
2477 #define CAN_FS1R_FSC21         CAN_FS1R_FSC21_Msk                              /*!<Filter Scale Configuration bit 21 */
2478 #define CAN_FS1R_FSC22_Pos     (22U)
2479 #define CAN_FS1R_FSC22_Msk     (0x1UL << CAN_FS1R_FSC22_Pos)                    /*!< 0x00400000 */
2480 #define CAN_FS1R_FSC22         CAN_FS1R_FSC22_Msk                              /*!<Filter Scale Configuration bit 22 */
2481 #define CAN_FS1R_FSC23_Pos     (23U)
2482 #define CAN_FS1R_FSC23_Msk     (0x1UL << CAN_FS1R_FSC23_Pos)                    /*!< 0x00800000 */
2483 #define CAN_FS1R_FSC23         CAN_FS1R_FSC23_Msk                              /*!<Filter Scale Configuration bit 23 */
2484 #define CAN_FS1R_FSC24_Pos     (24U)
2485 #define CAN_FS1R_FSC24_Msk     (0x1UL << CAN_FS1R_FSC24_Pos)                    /*!< 0x01000000 */
2486 #define CAN_FS1R_FSC24         CAN_FS1R_FSC24_Msk                              /*!<Filter Scale Configuration bit 24 */
2487 #define CAN_FS1R_FSC25_Pos     (25U)
2488 #define CAN_FS1R_FSC25_Msk     (0x1UL << CAN_FS1R_FSC25_Pos)                    /*!< 0x02000000 */
2489 #define CAN_FS1R_FSC25         CAN_FS1R_FSC25_Msk                              /*!<Filter Scale Configuration bit 25 */
2490 #define CAN_FS1R_FSC26_Pos     (26U)
2491 #define CAN_FS1R_FSC26_Msk     (0x1UL << CAN_FS1R_FSC26_Pos)                    /*!< 0x04000000 */
2492 #define CAN_FS1R_FSC26         CAN_FS1R_FSC26_Msk                              /*!<Filter Scale Configuration bit 26 */
2493 #define CAN_FS1R_FSC27_Pos     (27U)
2494 #define CAN_FS1R_FSC27_Msk     (0x1UL << CAN_FS1R_FSC27_Pos)                    /*!< 0x08000000 */
2495 #define CAN_FS1R_FSC27         CAN_FS1R_FSC27_Msk                              /*!<Filter Scale Configuration bit 27 */
2496 
2497 /******************  Bit definition for CAN_FFA1R register  *******************/
2498 #define CAN_FFA1R_FFA_Pos      (0U)
2499 #define CAN_FFA1R_FFA_Msk      (0xFFFFFFFUL << CAN_FFA1R_FFA_Pos)               /*!< 0x0FFFFFFF */
2500 #define CAN_FFA1R_FFA          CAN_FFA1R_FFA_Msk                               /*!<Filter FIFO Assignment */
2501 #define CAN_FFA1R_FFA0_Pos     (0U)
2502 #define CAN_FFA1R_FFA0_Msk     (0x1UL << CAN_FFA1R_FFA0_Pos)                    /*!< 0x00000001 */
2503 #define CAN_FFA1R_FFA0         CAN_FFA1R_FFA0_Msk                              /*!<Filter FIFO Assignment bit 0 */
2504 #define CAN_FFA1R_FFA1_Pos     (1U)
2505 #define CAN_FFA1R_FFA1_Msk     (0x1UL << CAN_FFA1R_FFA1_Pos)                    /*!< 0x00000002 */
2506 #define CAN_FFA1R_FFA1         CAN_FFA1R_FFA1_Msk                              /*!<Filter FIFO Assignment bit 1 */
2507 #define CAN_FFA1R_FFA2_Pos     (2U)
2508 #define CAN_FFA1R_FFA2_Msk     (0x1UL << CAN_FFA1R_FFA2_Pos)                    /*!< 0x00000004 */
2509 #define CAN_FFA1R_FFA2         CAN_FFA1R_FFA2_Msk                              /*!<Filter FIFO Assignment bit 2 */
2510 #define CAN_FFA1R_FFA3_Pos     (3U)
2511 #define CAN_FFA1R_FFA3_Msk     (0x1UL << CAN_FFA1R_FFA3_Pos)                    /*!< 0x00000008 */
2512 #define CAN_FFA1R_FFA3         CAN_FFA1R_FFA3_Msk                              /*!<Filter FIFO Assignment bit 3 */
2513 #define CAN_FFA1R_FFA4_Pos     (4U)
2514 #define CAN_FFA1R_FFA4_Msk     (0x1UL << CAN_FFA1R_FFA4_Pos)                    /*!< 0x00000010 */
2515 #define CAN_FFA1R_FFA4         CAN_FFA1R_FFA4_Msk                              /*!<Filter FIFO Assignment bit 4 */
2516 #define CAN_FFA1R_FFA5_Pos     (5U)
2517 #define CAN_FFA1R_FFA5_Msk     (0x1UL << CAN_FFA1R_FFA5_Pos)                    /*!< 0x00000020 */
2518 #define CAN_FFA1R_FFA5         CAN_FFA1R_FFA5_Msk                              /*!<Filter FIFO Assignment bit 5 */
2519 #define CAN_FFA1R_FFA6_Pos     (6U)
2520 #define CAN_FFA1R_FFA6_Msk     (0x1UL << CAN_FFA1R_FFA6_Pos)                    /*!< 0x00000040 */
2521 #define CAN_FFA1R_FFA6         CAN_FFA1R_FFA6_Msk                              /*!<Filter FIFO Assignment bit 6 */
2522 #define CAN_FFA1R_FFA7_Pos     (7U)
2523 #define CAN_FFA1R_FFA7_Msk     (0x1UL << CAN_FFA1R_FFA7_Pos)                    /*!< 0x00000080 */
2524 #define CAN_FFA1R_FFA7         CAN_FFA1R_FFA7_Msk                              /*!<Filter FIFO Assignment bit 7 */
2525 #define CAN_FFA1R_FFA8_Pos     (8U)
2526 #define CAN_FFA1R_FFA8_Msk     (0x1UL << CAN_FFA1R_FFA8_Pos)                    /*!< 0x00000100 */
2527 #define CAN_FFA1R_FFA8         CAN_FFA1R_FFA8_Msk                              /*!<Filter FIFO Assignment bit 8 */
2528 #define CAN_FFA1R_FFA9_Pos     (9U)
2529 #define CAN_FFA1R_FFA9_Msk     (0x1UL << CAN_FFA1R_FFA9_Pos)                    /*!< 0x00000200 */
2530 #define CAN_FFA1R_FFA9         CAN_FFA1R_FFA9_Msk                              /*!<Filter FIFO Assignment bit 9 */
2531 #define CAN_FFA1R_FFA10_Pos    (10U)
2532 #define CAN_FFA1R_FFA10_Msk    (0x1UL << CAN_FFA1R_FFA10_Pos)                   /*!< 0x00000400 */
2533 #define CAN_FFA1R_FFA10        CAN_FFA1R_FFA10_Msk                             /*!<Filter FIFO Assignment bit 10 */
2534 #define CAN_FFA1R_FFA11_Pos    (11U)
2535 #define CAN_FFA1R_FFA11_Msk    (0x1UL << CAN_FFA1R_FFA11_Pos)                   /*!< 0x00000800 */
2536 #define CAN_FFA1R_FFA11        CAN_FFA1R_FFA11_Msk                             /*!<Filter FIFO Assignment bit 11 */
2537 #define CAN_FFA1R_FFA12_Pos    (12U)
2538 #define CAN_FFA1R_FFA12_Msk    (0x1UL << CAN_FFA1R_FFA12_Pos)                   /*!< 0x00001000 */
2539 #define CAN_FFA1R_FFA12        CAN_FFA1R_FFA12_Msk                             /*!<Filter FIFO Assignment bit 12 */
2540 #define CAN_FFA1R_FFA13_Pos    (13U)
2541 #define CAN_FFA1R_FFA13_Msk    (0x1UL << CAN_FFA1R_FFA13_Pos)                   /*!< 0x00002000 */
2542 #define CAN_FFA1R_FFA13        CAN_FFA1R_FFA13_Msk                             /*!<Filter FIFO Assignment bit 13 */
2543 #define CAN_FFA1R_FFA14_Pos    (14U)
2544 #define CAN_FFA1R_FFA14_Msk    (0x1UL << CAN_FFA1R_FFA14_Pos)                   /*!< 0x00004000 */
2545 #define CAN_FFA1R_FFA14        CAN_FFA1R_FFA14_Msk                             /*!<Filter FIFO Assignment bit 14 */
2546 #define CAN_FFA1R_FFA15_Pos    (15U)
2547 #define CAN_FFA1R_FFA15_Msk    (0x1UL << CAN_FFA1R_FFA15_Pos)                   /*!< 0x00008000 */
2548 #define CAN_FFA1R_FFA15        CAN_FFA1R_FFA15_Msk                             /*!<Filter FIFO Assignment bit 15 */
2549 #define CAN_FFA1R_FFA16_Pos    (16U)
2550 #define CAN_FFA1R_FFA16_Msk    (0x1UL << CAN_FFA1R_FFA16_Pos)                   /*!< 0x00010000 */
2551 #define CAN_FFA1R_FFA16        CAN_FFA1R_FFA16_Msk                             /*!<Filter FIFO Assignment bit 16 */
2552 #define CAN_FFA1R_FFA17_Pos    (17U)
2553 #define CAN_FFA1R_FFA17_Msk    (0x1UL << CAN_FFA1R_FFA17_Pos)                   /*!< 0x00020000 */
2554 #define CAN_FFA1R_FFA17        CAN_FFA1R_FFA17_Msk                             /*!<Filter FIFO Assignment bit 17 */
2555 #define CAN_FFA1R_FFA18_Pos    (18U)
2556 #define CAN_FFA1R_FFA18_Msk    (0x1UL << CAN_FFA1R_FFA18_Pos)                   /*!< 0x00040000 */
2557 #define CAN_FFA1R_FFA18        CAN_FFA1R_FFA18_Msk                             /*!<Filter FIFO Assignment bit 18 */
2558 #define CAN_FFA1R_FFA19_Pos    (19U)
2559 #define CAN_FFA1R_FFA19_Msk    (0x1UL << CAN_FFA1R_FFA19_Pos)                   /*!< 0x00080000 */
2560 #define CAN_FFA1R_FFA19        CAN_FFA1R_FFA19_Msk                             /*!<Filter FIFO Assignment bit 19 */
2561 #define CAN_FFA1R_FFA20_Pos    (20U)
2562 #define CAN_FFA1R_FFA20_Msk    (0x1UL << CAN_FFA1R_FFA20_Pos)                   /*!< 0x00100000 */
2563 #define CAN_FFA1R_FFA20        CAN_FFA1R_FFA20_Msk                             /*!<Filter FIFO Assignment bit 20 */
2564 #define CAN_FFA1R_FFA21_Pos    (21U)
2565 #define CAN_FFA1R_FFA21_Msk    (0x1UL << CAN_FFA1R_FFA21_Pos)                   /*!< 0x00200000 */
2566 #define CAN_FFA1R_FFA21        CAN_FFA1R_FFA21_Msk                             /*!<Filter FIFO Assignment bit 21 */
2567 #define CAN_FFA1R_FFA22_Pos    (22U)
2568 #define CAN_FFA1R_FFA22_Msk    (0x1UL << CAN_FFA1R_FFA22_Pos)                   /*!< 0x00400000 */
2569 #define CAN_FFA1R_FFA22        CAN_FFA1R_FFA22_Msk                             /*!<Filter FIFO Assignment bit 22 */
2570 #define CAN_FFA1R_FFA23_Pos    (23U)
2571 #define CAN_FFA1R_FFA23_Msk    (0x1UL << CAN_FFA1R_FFA23_Pos)                   /*!< 0x00800000 */
2572 #define CAN_FFA1R_FFA23        CAN_FFA1R_FFA23_Msk                             /*!<Filter FIFO Assignment bit 23 */
2573 #define CAN_FFA1R_FFA24_Pos    (24U)
2574 #define CAN_FFA1R_FFA24_Msk    (0x1UL << CAN_FFA1R_FFA24_Pos)                   /*!< 0x01000000 */
2575 #define CAN_FFA1R_FFA24        CAN_FFA1R_FFA24_Msk                             /*!<Filter FIFO Assignment bit 24 */
2576 #define CAN_FFA1R_FFA25_Pos    (25U)
2577 #define CAN_FFA1R_FFA25_Msk    (0x1UL << CAN_FFA1R_FFA25_Pos)                   /*!< 0x02000000 */
2578 #define CAN_FFA1R_FFA25        CAN_FFA1R_FFA25_Msk                             /*!<Filter FIFO Assignment bit 25 */
2579 #define CAN_FFA1R_FFA26_Pos    (26U)
2580 #define CAN_FFA1R_FFA26_Msk    (0x1UL << CAN_FFA1R_FFA26_Pos)                   /*!< 0x04000000 */
2581 #define CAN_FFA1R_FFA26        CAN_FFA1R_FFA26_Msk                             /*!<Filter FIFO Assignment bit 26 */
2582 #define CAN_FFA1R_FFA27_Pos    (27U)
2583 #define CAN_FFA1R_FFA27_Msk    (0x1UL << CAN_FFA1R_FFA27_Pos)                   /*!< 0x08000000 */
2584 #define CAN_FFA1R_FFA27        CAN_FFA1R_FFA27_Msk                             /*!<Filter FIFO Assignment bit 27 */
2585 
2586 /*******************  Bit definition for CAN_FA1R register  *******************/
2587 #define CAN_FA1R_FACT_Pos      (0U)
2588 #define CAN_FA1R_FACT_Msk      (0xFFFFFFFUL << CAN_FA1R_FACT_Pos)               /*!< 0x0FFFFFFF */
2589 #define CAN_FA1R_FACT          CAN_FA1R_FACT_Msk                               /*!<Filter Active */
2590 #define CAN_FA1R_FACT0_Pos     (0U)
2591 #define CAN_FA1R_FACT0_Msk     (0x1UL << CAN_FA1R_FACT0_Pos)                    /*!< 0x00000001 */
2592 #define CAN_FA1R_FACT0         CAN_FA1R_FACT0_Msk                              /*!<Filter Active bit 0 */
2593 #define CAN_FA1R_FACT1_Pos     (1U)
2594 #define CAN_FA1R_FACT1_Msk     (0x1UL << CAN_FA1R_FACT1_Pos)                    /*!< 0x00000002 */
2595 #define CAN_FA1R_FACT1         CAN_FA1R_FACT1_Msk                              /*!<Filter Active bit 1 */
2596 #define CAN_FA1R_FACT2_Pos     (2U)
2597 #define CAN_FA1R_FACT2_Msk     (0x1UL << CAN_FA1R_FACT2_Pos)                    /*!< 0x00000004 */
2598 #define CAN_FA1R_FACT2         CAN_FA1R_FACT2_Msk                              /*!<Filter Active bit 2 */
2599 #define CAN_FA1R_FACT3_Pos     (3U)
2600 #define CAN_FA1R_FACT3_Msk     (0x1UL << CAN_FA1R_FACT3_Pos)                    /*!< 0x00000008 */
2601 #define CAN_FA1R_FACT3         CAN_FA1R_FACT3_Msk                              /*!<Filter Active bit 3 */
2602 #define CAN_FA1R_FACT4_Pos     (4U)
2603 #define CAN_FA1R_FACT4_Msk     (0x1UL << CAN_FA1R_FACT4_Pos)                    /*!< 0x00000010 */
2604 #define CAN_FA1R_FACT4         CAN_FA1R_FACT4_Msk                              /*!<Filter Active bit 4 */
2605 #define CAN_FA1R_FACT5_Pos     (5U)
2606 #define CAN_FA1R_FACT5_Msk     (0x1UL << CAN_FA1R_FACT5_Pos)                    /*!< 0x00000020 */
2607 #define CAN_FA1R_FACT5         CAN_FA1R_FACT5_Msk                              /*!<Filter Active bit 5 */
2608 #define CAN_FA1R_FACT6_Pos     (6U)
2609 #define CAN_FA1R_FACT6_Msk     (0x1UL << CAN_FA1R_FACT6_Pos)                    /*!< 0x00000040 */
2610 #define CAN_FA1R_FACT6         CAN_FA1R_FACT6_Msk                              /*!<Filter Active bit 6 */
2611 #define CAN_FA1R_FACT7_Pos     (7U)
2612 #define CAN_FA1R_FACT7_Msk     (0x1UL << CAN_FA1R_FACT7_Pos)                    /*!< 0x00000080 */
2613 #define CAN_FA1R_FACT7         CAN_FA1R_FACT7_Msk                              /*!<Filter Active bit 7 */
2614 #define CAN_FA1R_FACT8_Pos     (8U)
2615 #define CAN_FA1R_FACT8_Msk     (0x1UL << CAN_FA1R_FACT8_Pos)                    /*!< 0x00000100 */
2616 #define CAN_FA1R_FACT8         CAN_FA1R_FACT8_Msk                              /*!<Filter Active bit 8 */
2617 #define CAN_FA1R_FACT9_Pos     (9U)
2618 #define CAN_FA1R_FACT9_Msk     (0x1UL << CAN_FA1R_FACT9_Pos)                    /*!< 0x00000200 */
2619 #define CAN_FA1R_FACT9         CAN_FA1R_FACT9_Msk                              /*!<Filter Active bit 9 */
2620 #define CAN_FA1R_FACT10_Pos    (10U)
2621 #define CAN_FA1R_FACT10_Msk    (0x1UL << CAN_FA1R_FACT10_Pos)                   /*!< 0x00000400 */
2622 #define CAN_FA1R_FACT10        CAN_FA1R_FACT10_Msk                             /*!<Filter Active bit 10 */
2623 #define CAN_FA1R_FACT11_Pos    (11U)
2624 #define CAN_FA1R_FACT11_Msk    (0x1UL << CAN_FA1R_FACT11_Pos)                   /*!< 0x00000800 */
2625 #define CAN_FA1R_FACT11        CAN_FA1R_FACT11_Msk                             /*!<Filter Active bit 11 */
2626 #define CAN_FA1R_FACT12_Pos    (12U)
2627 #define CAN_FA1R_FACT12_Msk    (0x1UL << CAN_FA1R_FACT12_Pos)                   /*!< 0x00001000 */
2628 #define CAN_FA1R_FACT12        CAN_FA1R_FACT12_Msk                             /*!<Filter Active bit 12 */
2629 #define CAN_FA1R_FACT13_Pos    (13U)
2630 #define CAN_FA1R_FACT13_Msk    (0x1UL << CAN_FA1R_FACT13_Pos)                   /*!< 0x00002000 */
2631 #define CAN_FA1R_FACT13        CAN_FA1R_FACT13_Msk                             /*!<Filter Active bit 13 */
2632 #define CAN_FA1R_FACT14_Pos    (14U)
2633 #define CAN_FA1R_FACT14_Msk    (0x1UL << CAN_FA1R_FACT14_Pos)                   /*!< 0x00004000 */
2634 #define CAN_FA1R_FACT14        CAN_FA1R_FACT14_Msk                             /*!<Filter Active bit 14 */
2635 #define CAN_FA1R_FACT15_Pos    (15U)
2636 #define CAN_FA1R_FACT15_Msk    (0x1UL << CAN_FA1R_FACT15_Pos)                   /*!< 0x00008000 */
2637 #define CAN_FA1R_FACT15        CAN_FA1R_FACT15_Msk                             /*!<Filter Active bit 15 */
2638 #define CAN_FA1R_FACT16_Pos    (16U)
2639 #define CAN_FA1R_FACT16_Msk    (0x1UL << CAN_FA1R_FACT16_Pos)                   /*!< 0x00010000 */
2640 #define CAN_FA1R_FACT16        CAN_FA1R_FACT16_Msk                             /*!<Filter Active bit 16 */
2641 #define CAN_FA1R_FACT17_Pos    (17U)
2642 #define CAN_FA1R_FACT17_Msk    (0x1UL << CAN_FA1R_FACT17_Pos)                   /*!< 0x00020000 */
2643 #define CAN_FA1R_FACT17        CAN_FA1R_FACT17_Msk                             /*!<Filter Active bit 17 */
2644 #define CAN_FA1R_FACT18_Pos    (18U)
2645 #define CAN_FA1R_FACT18_Msk    (0x1UL << CAN_FA1R_FACT18_Pos)                   /*!< 0x00040000 */
2646 #define CAN_FA1R_FACT18        CAN_FA1R_FACT18_Msk                             /*!<Filter Active bit 18 */
2647 #define CAN_FA1R_FACT19_Pos    (19U)
2648 #define CAN_FA1R_FACT19_Msk    (0x1UL << CAN_FA1R_FACT19_Pos)                   /*!< 0x00080000 */
2649 #define CAN_FA1R_FACT19        CAN_FA1R_FACT19_Msk                             /*!<Filter Active bit 19 */
2650 #define CAN_FA1R_FACT20_Pos    (20U)
2651 #define CAN_FA1R_FACT20_Msk    (0x1UL << CAN_FA1R_FACT20_Pos)                   /*!< 0x00100000 */
2652 #define CAN_FA1R_FACT20        CAN_FA1R_FACT20_Msk                             /*!<Filter Active bit 20 */
2653 #define CAN_FA1R_FACT21_Pos    (21U)
2654 #define CAN_FA1R_FACT21_Msk    (0x1UL << CAN_FA1R_FACT21_Pos)                   /*!< 0x00200000 */
2655 #define CAN_FA1R_FACT21        CAN_FA1R_FACT21_Msk                             /*!<Filter Active bit 21 */
2656 #define CAN_FA1R_FACT22_Pos    (22U)
2657 #define CAN_FA1R_FACT22_Msk    (0x1UL << CAN_FA1R_FACT22_Pos)                   /*!< 0x00400000 */
2658 #define CAN_FA1R_FACT22        CAN_FA1R_FACT22_Msk                             /*!<Filter Active bit 22 */
2659 #define CAN_FA1R_FACT23_Pos    (23U)
2660 #define CAN_FA1R_FACT23_Msk    (0x1UL << CAN_FA1R_FACT23_Pos)                   /*!< 0x00800000 */
2661 #define CAN_FA1R_FACT23        CAN_FA1R_FACT23_Msk                             /*!<Filter Active bit 23 */
2662 #define CAN_FA1R_FACT24_Pos    (24U)
2663 #define CAN_FA1R_FACT24_Msk    (0x1UL << CAN_FA1R_FACT24_Pos)                   /*!< 0x01000000 */
2664 #define CAN_FA1R_FACT24        CAN_FA1R_FACT24_Msk                             /*!<Filter Active bit 24 */
2665 #define CAN_FA1R_FACT25_Pos    (25U)
2666 #define CAN_FA1R_FACT25_Msk    (0x1UL << CAN_FA1R_FACT25_Pos)                   /*!< 0x02000000 */
2667 #define CAN_FA1R_FACT25        CAN_FA1R_FACT25_Msk                             /*!<Filter Active bit 25 */
2668 #define CAN_FA1R_FACT26_Pos    (26U)
2669 #define CAN_FA1R_FACT26_Msk    (0x1UL << CAN_FA1R_FACT26_Pos)                   /*!< 0x04000000 */
2670 #define CAN_FA1R_FACT26        CAN_FA1R_FACT26_Msk                             /*!<Filter Active bit 26 */
2671 #define CAN_FA1R_FACT27_Pos    (27U)
2672 #define CAN_FA1R_FACT27_Msk    (0x1UL << CAN_FA1R_FACT27_Pos)                   /*!< 0x08000000 */
2673 #define CAN_FA1R_FACT27        CAN_FA1R_FACT27_Msk                             /*!<Filter Active bit 27 */
2674 
2675 
2676 /*******************  Bit definition for CAN_F0R1 register  *******************/
2677 #define CAN_F0R1_FB0_Pos       (0U)
2678 #define CAN_F0R1_FB0_Msk       (0x1UL << CAN_F0R1_FB0_Pos)                      /*!< 0x00000001 */
2679 #define CAN_F0R1_FB0           CAN_F0R1_FB0_Msk                                /*!<Filter bit 0 */
2680 #define CAN_F0R1_FB1_Pos       (1U)
2681 #define CAN_F0R1_FB1_Msk       (0x1UL << CAN_F0R1_FB1_Pos)                      /*!< 0x00000002 */
2682 #define CAN_F0R1_FB1           CAN_F0R1_FB1_Msk                                /*!<Filter bit 1 */
2683 #define CAN_F0R1_FB2_Pos       (2U)
2684 #define CAN_F0R1_FB2_Msk       (0x1UL << CAN_F0R1_FB2_Pos)                      /*!< 0x00000004 */
2685 #define CAN_F0R1_FB2           CAN_F0R1_FB2_Msk                                /*!<Filter bit 2 */
2686 #define CAN_F0R1_FB3_Pos       (3U)
2687 #define CAN_F0R1_FB3_Msk       (0x1UL << CAN_F0R1_FB3_Pos)                      /*!< 0x00000008 */
2688 #define CAN_F0R1_FB3           CAN_F0R1_FB3_Msk                                /*!<Filter bit 3 */
2689 #define CAN_F0R1_FB4_Pos       (4U)
2690 #define CAN_F0R1_FB4_Msk       (0x1UL << CAN_F0R1_FB4_Pos)                      /*!< 0x00000010 */
2691 #define CAN_F0R1_FB4           CAN_F0R1_FB4_Msk                                /*!<Filter bit 4 */
2692 #define CAN_F0R1_FB5_Pos       (5U)
2693 #define CAN_F0R1_FB5_Msk       (0x1UL << CAN_F0R1_FB5_Pos)                      /*!< 0x00000020 */
2694 #define CAN_F0R1_FB5           CAN_F0R1_FB5_Msk                                /*!<Filter bit 5 */
2695 #define CAN_F0R1_FB6_Pos       (6U)
2696 #define CAN_F0R1_FB6_Msk       (0x1UL << CAN_F0R1_FB6_Pos)                      /*!< 0x00000040 */
2697 #define CAN_F0R1_FB6           CAN_F0R1_FB6_Msk                                /*!<Filter bit 6 */
2698 #define CAN_F0R1_FB7_Pos       (7U)
2699 #define CAN_F0R1_FB7_Msk       (0x1UL << CAN_F0R1_FB7_Pos)                      /*!< 0x00000080 */
2700 #define CAN_F0R1_FB7           CAN_F0R1_FB7_Msk                                /*!<Filter bit 7 */
2701 #define CAN_F0R1_FB8_Pos       (8U)
2702 #define CAN_F0R1_FB8_Msk       (0x1UL << CAN_F0R1_FB8_Pos)                      /*!< 0x00000100 */
2703 #define CAN_F0R1_FB8           CAN_F0R1_FB8_Msk                                /*!<Filter bit 8 */
2704 #define CAN_F0R1_FB9_Pos       (9U)
2705 #define CAN_F0R1_FB9_Msk       (0x1UL << CAN_F0R1_FB9_Pos)                      /*!< 0x00000200 */
2706 #define CAN_F0R1_FB9           CAN_F0R1_FB9_Msk                                /*!<Filter bit 9 */
2707 #define CAN_F0R1_FB10_Pos      (10U)
2708 #define CAN_F0R1_FB10_Msk      (0x1UL << CAN_F0R1_FB10_Pos)                     /*!< 0x00000400 */
2709 #define CAN_F0R1_FB10          CAN_F0R1_FB10_Msk                               /*!<Filter bit 10 */
2710 #define CAN_F0R1_FB11_Pos      (11U)
2711 #define CAN_F0R1_FB11_Msk      (0x1UL << CAN_F0R1_FB11_Pos)                     /*!< 0x00000800 */
2712 #define CAN_F0R1_FB11          CAN_F0R1_FB11_Msk                               /*!<Filter bit 11 */
2713 #define CAN_F0R1_FB12_Pos      (12U)
2714 #define CAN_F0R1_FB12_Msk      (0x1UL << CAN_F0R1_FB12_Pos)                     /*!< 0x00001000 */
2715 #define CAN_F0R1_FB12          CAN_F0R1_FB12_Msk                               /*!<Filter bit 12 */
2716 #define CAN_F0R1_FB13_Pos      (13U)
2717 #define CAN_F0R1_FB13_Msk      (0x1UL << CAN_F0R1_FB13_Pos)                     /*!< 0x00002000 */
2718 #define CAN_F0R1_FB13          CAN_F0R1_FB13_Msk                               /*!<Filter bit 13 */
2719 #define CAN_F0R1_FB14_Pos      (14U)
2720 #define CAN_F0R1_FB14_Msk      (0x1UL << CAN_F0R1_FB14_Pos)                     /*!< 0x00004000 */
2721 #define CAN_F0R1_FB14          CAN_F0R1_FB14_Msk                               /*!<Filter bit 14 */
2722 #define CAN_F0R1_FB15_Pos      (15U)
2723 #define CAN_F0R1_FB15_Msk      (0x1UL << CAN_F0R1_FB15_Pos)                     /*!< 0x00008000 */
2724 #define CAN_F0R1_FB15          CAN_F0R1_FB15_Msk                               /*!<Filter bit 15 */
2725 #define CAN_F0R1_FB16_Pos      (16U)
2726 #define CAN_F0R1_FB16_Msk      (0x1UL << CAN_F0R1_FB16_Pos)                     /*!< 0x00010000 */
2727 #define CAN_F0R1_FB16          CAN_F0R1_FB16_Msk                               /*!<Filter bit 16 */
2728 #define CAN_F0R1_FB17_Pos      (17U)
2729 #define CAN_F0R1_FB17_Msk      (0x1UL << CAN_F0R1_FB17_Pos)                     /*!< 0x00020000 */
2730 #define CAN_F0R1_FB17          CAN_F0R1_FB17_Msk                               /*!<Filter bit 17 */
2731 #define CAN_F0R1_FB18_Pos      (18U)
2732 #define CAN_F0R1_FB18_Msk      (0x1UL << CAN_F0R1_FB18_Pos)                     /*!< 0x00040000 */
2733 #define CAN_F0R1_FB18          CAN_F0R1_FB18_Msk                               /*!<Filter bit 18 */
2734 #define CAN_F0R1_FB19_Pos      (19U)
2735 #define CAN_F0R1_FB19_Msk      (0x1UL << CAN_F0R1_FB19_Pos)                     /*!< 0x00080000 */
2736 #define CAN_F0R1_FB19          CAN_F0R1_FB19_Msk                               /*!<Filter bit 19 */
2737 #define CAN_F0R1_FB20_Pos      (20U)
2738 #define CAN_F0R1_FB20_Msk      (0x1UL << CAN_F0R1_FB20_Pos)                     /*!< 0x00100000 */
2739 #define CAN_F0R1_FB20          CAN_F0R1_FB20_Msk                               /*!<Filter bit 20 */
2740 #define CAN_F0R1_FB21_Pos      (21U)
2741 #define CAN_F0R1_FB21_Msk      (0x1UL << CAN_F0R1_FB21_Pos)                     /*!< 0x00200000 */
2742 #define CAN_F0R1_FB21          CAN_F0R1_FB21_Msk                               /*!<Filter bit 21 */
2743 #define CAN_F0R1_FB22_Pos      (22U)
2744 #define CAN_F0R1_FB22_Msk      (0x1UL << CAN_F0R1_FB22_Pos)                     /*!< 0x00400000 */
2745 #define CAN_F0R1_FB22          CAN_F0R1_FB22_Msk                               /*!<Filter bit 22 */
2746 #define CAN_F0R1_FB23_Pos      (23U)
2747 #define CAN_F0R1_FB23_Msk      (0x1UL << CAN_F0R1_FB23_Pos)                     /*!< 0x00800000 */
2748 #define CAN_F0R1_FB23          CAN_F0R1_FB23_Msk                               /*!<Filter bit 23 */
2749 #define CAN_F0R1_FB24_Pos      (24U)
2750 #define CAN_F0R1_FB24_Msk      (0x1UL << CAN_F0R1_FB24_Pos)                     /*!< 0x01000000 */
2751 #define CAN_F0R1_FB24          CAN_F0R1_FB24_Msk                               /*!<Filter bit 24 */
2752 #define CAN_F0R1_FB25_Pos      (25U)
2753 #define CAN_F0R1_FB25_Msk      (0x1UL << CAN_F0R1_FB25_Pos)                     /*!< 0x02000000 */
2754 #define CAN_F0R1_FB25          CAN_F0R1_FB25_Msk                               /*!<Filter bit 25 */
2755 #define CAN_F0R1_FB26_Pos      (26U)
2756 #define CAN_F0R1_FB26_Msk      (0x1UL << CAN_F0R1_FB26_Pos)                     /*!< 0x04000000 */
2757 #define CAN_F0R1_FB26          CAN_F0R1_FB26_Msk                               /*!<Filter bit 26 */
2758 #define CAN_F0R1_FB27_Pos      (27U)
2759 #define CAN_F0R1_FB27_Msk      (0x1UL << CAN_F0R1_FB27_Pos)                     /*!< 0x08000000 */
2760 #define CAN_F0R1_FB27          CAN_F0R1_FB27_Msk                               /*!<Filter bit 27 */
2761 #define CAN_F0R1_FB28_Pos      (28U)
2762 #define CAN_F0R1_FB28_Msk      (0x1UL << CAN_F0R1_FB28_Pos)                     /*!< 0x10000000 */
2763 #define CAN_F0R1_FB28          CAN_F0R1_FB28_Msk                               /*!<Filter bit 28 */
2764 #define CAN_F0R1_FB29_Pos      (29U)
2765 #define CAN_F0R1_FB29_Msk      (0x1UL << CAN_F0R1_FB29_Pos)                     /*!< 0x20000000 */
2766 #define CAN_F0R1_FB29          CAN_F0R1_FB29_Msk                               /*!<Filter bit 29 */
2767 #define CAN_F0R1_FB30_Pos      (30U)
2768 #define CAN_F0R1_FB30_Msk      (0x1UL << CAN_F0R1_FB30_Pos)                     /*!< 0x40000000 */
2769 #define CAN_F0R1_FB30          CAN_F0R1_FB30_Msk                               /*!<Filter bit 30 */
2770 #define CAN_F0R1_FB31_Pos      (31U)
2771 #define CAN_F0R1_FB31_Msk      (0x1UL << CAN_F0R1_FB31_Pos)                     /*!< 0x80000000 */
2772 #define CAN_F0R1_FB31          CAN_F0R1_FB31_Msk                               /*!<Filter bit 31 */
2773 
2774 /*******************  Bit definition for CAN_F1R1 register  *******************/
2775 #define CAN_F1R1_FB0_Pos       (0U)
2776 #define CAN_F1R1_FB0_Msk       (0x1UL << CAN_F1R1_FB0_Pos)                      /*!< 0x00000001 */
2777 #define CAN_F1R1_FB0           CAN_F1R1_FB0_Msk                                /*!<Filter bit 0 */
2778 #define CAN_F1R1_FB1_Pos       (1U)
2779 #define CAN_F1R1_FB1_Msk       (0x1UL << CAN_F1R1_FB1_Pos)                      /*!< 0x00000002 */
2780 #define CAN_F1R1_FB1           CAN_F1R1_FB1_Msk                                /*!<Filter bit 1 */
2781 #define CAN_F1R1_FB2_Pos       (2U)
2782 #define CAN_F1R1_FB2_Msk       (0x1UL << CAN_F1R1_FB2_Pos)                      /*!< 0x00000004 */
2783 #define CAN_F1R1_FB2           CAN_F1R1_FB2_Msk                                /*!<Filter bit 2 */
2784 #define CAN_F1R1_FB3_Pos       (3U)
2785 #define CAN_F1R1_FB3_Msk       (0x1UL << CAN_F1R1_FB3_Pos)                      /*!< 0x00000008 */
2786 #define CAN_F1R1_FB3           CAN_F1R1_FB3_Msk                                /*!<Filter bit 3 */
2787 #define CAN_F1R1_FB4_Pos       (4U)
2788 #define CAN_F1R1_FB4_Msk       (0x1UL << CAN_F1R1_FB4_Pos)                      /*!< 0x00000010 */
2789 #define CAN_F1R1_FB4           CAN_F1R1_FB4_Msk                                /*!<Filter bit 4 */
2790 #define CAN_F1R1_FB5_Pos       (5U)
2791 #define CAN_F1R1_FB5_Msk       (0x1UL << CAN_F1R1_FB5_Pos)                      /*!< 0x00000020 */
2792 #define CAN_F1R1_FB5           CAN_F1R1_FB5_Msk                                /*!<Filter bit 5 */
2793 #define CAN_F1R1_FB6_Pos       (6U)
2794 #define CAN_F1R1_FB6_Msk       (0x1UL << CAN_F1R1_FB6_Pos)                      /*!< 0x00000040 */
2795 #define CAN_F1R1_FB6           CAN_F1R1_FB6_Msk                                /*!<Filter bit 6 */
2796 #define CAN_F1R1_FB7_Pos       (7U)
2797 #define CAN_F1R1_FB7_Msk       (0x1UL << CAN_F1R1_FB7_Pos)                      /*!< 0x00000080 */
2798 #define CAN_F1R1_FB7           CAN_F1R1_FB7_Msk                                /*!<Filter bit 7 */
2799 #define CAN_F1R1_FB8_Pos       (8U)
2800 #define CAN_F1R1_FB8_Msk       (0x1UL << CAN_F1R1_FB8_Pos)                      /*!< 0x00000100 */
2801 #define CAN_F1R1_FB8           CAN_F1R1_FB8_Msk                                /*!<Filter bit 8 */
2802 #define CAN_F1R1_FB9_Pos       (9U)
2803 #define CAN_F1R1_FB9_Msk       (0x1UL << CAN_F1R1_FB9_Pos)                      /*!< 0x00000200 */
2804 #define CAN_F1R1_FB9           CAN_F1R1_FB9_Msk                                /*!<Filter bit 9 */
2805 #define CAN_F1R1_FB10_Pos      (10U)
2806 #define CAN_F1R1_FB10_Msk      (0x1UL << CAN_F1R1_FB10_Pos)                     /*!< 0x00000400 */
2807 #define CAN_F1R1_FB10          CAN_F1R1_FB10_Msk                               /*!<Filter bit 10 */
2808 #define CAN_F1R1_FB11_Pos      (11U)
2809 #define CAN_F1R1_FB11_Msk      (0x1UL << CAN_F1R1_FB11_Pos)                     /*!< 0x00000800 */
2810 #define CAN_F1R1_FB11          CAN_F1R1_FB11_Msk                               /*!<Filter bit 11 */
2811 #define CAN_F1R1_FB12_Pos      (12U)
2812 #define CAN_F1R1_FB12_Msk      (0x1UL << CAN_F1R1_FB12_Pos)                     /*!< 0x00001000 */
2813 #define CAN_F1R1_FB12          CAN_F1R1_FB12_Msk                               /*!<Filter bit 12 */
2814 #define CAN_F1R1_FB13_Pos      (13U)
2815 #define CAN_F1R1_FB13_Msk      (0x1UL << CAN_F1R1_FB13_Pos)                     /*!< 0x00002000 */
2816 #define CAN_F1R1_FB13          CAN_F1R1_FB13_Msk                               /*!<Filter bit 13 */
2817 #define CAN_F1R1_FB14_Pos      (14U)
2818 #define CAN_F1R1_FB14_Msk      (0x1UL << CAN_F1R1_FB14_Pos)                     /*!< 0x00004000 */
2819 #define CAN_F1R1_FB14          CAN_F1R1_FB14_Msk                               /*!<Filter bit 14 */
2820 #define CAN_F1R1_FB15_Pos      (15U)
2821 #define CAN_F1R1_FB15_Msk      (0x1UL << CAN_F1R1_FB15_Pos)                     /*!< 0x00008000 */
2822 #define CAN_F1R1_FB15          CAN_F1R1_FB15_Msk                               /*!<Filter bit 15 */
2823 #define CAN_F1R1_FB16_Pos      (16U)
2824 #define CAN_F1R1_FB16_Msk      (0x1UL << CAN_F1R1_FB16_Pos)                     /*!< 0x00010000 */
2825 #define CAN_F1R1_FB16          CAN_F1R1_FB16_Msk                               /*!<Filter bit 16 */
2826 #define CAN_F1R1_FB17_Pos      (17U)
2827 #define CAN_F1R1_FB17_Msk      (0x1UL << CAN_F1R1_FB17_Pos)                     /*!< 0x00020000 */
2828 #define CAN_F1R1_FB17          CAN_F1R1_FB17_Msk                               /*!<Filter bit 17 */
2829 #define CAN_F1R1_FB18_Pos      (18U)
2830 #define CAN_F1R1_FB18_Msk      (0x1UL << CAN_F1R1_FB18_Pos)                     /*!< 0x00040000 */
2831 #define CAN_F1R1_FB18          CAN_F1R1_FB18_Msk                               /*!<Filter bit 18 */
2832 #define CAN_F1R1_FB19_Pos      (19U)
2833 #define CAN_F1R1_FB19_Msk      (0x1UL << CAN_F1R1_FB19_Pos)                     /*!< 0x00080000 */
2834 #define CAN_F1R1_FB19          CAN_F1R1_FB19_Msk                               /*!<Filter bit 19 */
2835 #define CAN_F1R1_FB20_Pos      (20U)
2836 #define CAN_F1R1_FB20_Msk      (0x1UL << CAN_F1R1_FB20_Pos)                     /*!< 0x00100000 */
2837 #define CAN_F1R1_FB20          CAN_F1R1_FB20_Msk                               /*!<Filter bit 20 */
2838 #define CAN_F1R1_FB21_Pos      (21U)
2839 #define CAN_F1R1_FB21_Msk      (0x1UL << CAN_F1R1_FB21_Pos)                     /*!< 0x00200000 */
2840 #define CAN_F1R1_FB21          CAN_F1R1_FB21_Msk                               /*!<Filter bit 21 */
2841 #define CAN_F1R1_FB22_Pos      (22U)
2842 #define CAN_F1R1_FB22_Msk      (0x1UL << CAN_F1R1_FB22_Pos)                     /*!< 0x00400000 */
2843 #define CAN_F1R1_FB22          CAN_F1R1_FB22_Msk                               /*!<Filter bit 22 */
2844 #define CAN_F1R1_FB23_Pos      (23U)
2845 #define CAN_F1R1_FB23_Msk      (0x1UL << CAN_F1R1_FB23_Pos)                     /*!< 0x00800000 */
2846 #define CAN_F1R1_FB23          CAN_F1R1_FB23_Msk                               /*!<Filter bit 23 */
2847 #define CAN_F1R1_FB24_Pos      (24U)
2848 #define CAN_F1R1_FB24_Msk      (0x1UL << CAN_F1R1_FB24_Pos)                     /*!< 0x01000000 */
2849 #define CAN_F1R1_FB24          CAN_F1R1_FB24_Msk                               /*!<Filter bit 24 */
2850 #define CAN_F1R1_FB25_Pos      (25U)
2851 #define CAN_F1R1_FB25_Msk      (0x1UL << CAN_F1R1_FB25_Pos)                     /*!< 0x02000000 */
2852 #define CAN_F1R1_FB25          CAN_F1R1_FB25_Msk                               /*!<Filter bit 25 */
2853 #define CAN_F1R1_FB26_Pos      (26U)
2854 #define CAN_F1R1_FB26_Msk      (0x1UL << CAN_F1R1_FB26_Pos)                     /*!< 0x04000000 */
2855 #define CAN_F1R1_FB26          CAN_F1R1_FB26_Msk                               /*!<Filter bit 26 */
2856 #define CAN_F1R1_FB27_Pos      (27U)
2857 #define CAN_F1R1_FB27_Msk      (0x1UL << CAN_F1R1_FB27_Pos)                     /*!< 0x08000000 */
2858 #define CAN_F1R1_FB27          CAN_F1R1_FB27_Msk                               /*!<Filter bit 27 */
2859 #define CAN_F1R1_FB28_Pos      (28U)
2860 #define CAN_F1R1_FB28_Msk      (0x1UL << CAN_F1R1_FB28_Pos)                     /*!< 0x10000000 */
2861 #define CAN_F1R1_FB28          CAN_F1R1_FB28_Msk                               /*!<Filter bit 28 */
2862 #define CAN_F1R1_FB29_Pos      (29U)
2863 #define CAN_F1R1_FB29_Msk      (0x1UL << CAN_F1R1_FB29_Pos)                     /*!< 0x20000000 */
2864 #define CAN_F1R1_FB29          CAN_F1R1_FB29_Msk                               /*!<Filter bit 29 */
2865 #define CAN_F1R1_FB30_Pos      (30U)
2866 #define CAN_F1R1_FB30_Msk      (0x1UL << CAN_F1R1_FB30_Pos)                     /*!< 0x40000000 */
2867 #define CAN_F1R1_FB30          CAN_F1R1_FB30_Msk                               /*!<Filter bit 30 */
2868 #define CAN_F1R1_FB31_Pos      (31U)
2869 #define CAN_F1R1_FB31_Msk      (0x1UL << CAN_F1R1_FB31_Pos)                     /*!< 0x80000000 */
2870 #define CAN_F1R1_FB31          CAN_F1R1_FB31_Msk                               /*!<Filter bit 31 */
2871 
2872 /*******************  Bit definition for CAN_F2R1 register  *******************/
2873 #define CAN_F2R1_FB0_Pos       (0U)
2874 #define CAN_F2R1_FB0_Msk       (0x1UL << CAN_F2R1_FB0_Pos)                      /*!< 0x00000001 */
2875 #define CAN_F2R1_FB0           CAN_F2R1_FB0_Msk                                /*!<Filter bit 0 */
2876 #define CAN_F2R1_FB1_Pos       (1U)
2877 #define CAN_F2R1_FB1_Msk       (0x1UL << CAN_F2R1_FB1_Pos)                      /*!< 0x00000002 */
2878 #define CAN_F2R1_FB1           CAN_F2R1_FB1_Msk                                /*!<Filter bit 1 */
2879 #define CAN_F2R1_FB2_Pos       (2U)
2880 #define CAN_F2R1_FB2_Msk       (0x1UL << CAN_F2R1_FB2_Pos)                      /*!< 0x00000004 */
2881 #define CAN_F2R1_FB2           CAN_F2R1_FB2_Msk                                /*!<Filter bit 2 */
2882 #define CAN_F2R1_FB3_Pos       (3U)
2883 #define CAN_F2R1_FB3_Msk       (0x1UL << CAN_F2R1_FB3_Pos)                      /*!< 0x00000008 */
2884 #define CAN_F2R1_FB3           CAN_F2R1_FB3_Msk                                /*!<Filter bit 3 */
2885 #define CAN_F2R1_FB4_Pos       (4U)
2886 #define CAN_F2R1_FB4_Msk       (0x1UL << CAN_F2R1_FB4_Pos)                      /*!< 0x00000010 */
2887 #define CAN_F2R1_FB4           CAN_F2R1_FB4_Msk                                /*!<Filter bit 4 */
2888 #define CAN_F2R1_FB5_Pos       (5U)
2889 #define CAN_F2R1_FB5_Msk       (0x1UL << CAN_F2R1_FB5_Pos)                      /*!< 0x00000020 */
2890 #define CAN_F2R1_FB5           CAN_F2R1_FB5_Msk                                /*!<Filter bit 5 */
2891 #define CAN_F2R1_FB6_Pos       (6U)
2892 #define CAN_F2R1_FB6_Msk       (0x1UL << CAN_F2R1_FB6_Pos)                      /*!< 0x00000040 */
2893 #define CAN_F2R1_FB6           CAN_F2R1_FB6_Msk                                /*!<Filter bit 6 */
2894 #define CAN_F2R1_FB7_Pos       (7U)
2895 #define CAN_F2R1_FB7_Msk       (0x1UL << CAN_F2R1_FB7_Pos)                      /*!< 0x00000080 */
2896 #define CAN_F2R1_FB7           CAN_F2R1_FB7_Msk                                /*!<Filter bit 7 */
2897 #define CAN_F2R1_FB8_Pos       (8U)
2898 #define CAN_F2R1_FB8_Msk       (0x1UL << CAN_F2R1_FB8_Pos)                      /*!< 0x00000100 */
2899 #define CAN_F2R1_FB8           CAN_F2R1_FB8_Msk                                /*!<Filter bit 8 */
2900 #define CAN_F2R1_FB9_Pos       (9U)
2901 #define CAN_F2R1_FB9_Msk       (0x1UL << CAN_F2R1_FB9_Pos)                      /*!< 0x00000200 */
2902 #define CAN_F2R1_FB9           CAN_F2R1_FB9_Msk                                /*!<Filter bit 9 */
2903 #define CAN_F2R1_FB10_Pos      (10U)
2904 #define CAN_F2R1_FB10_Msk      (0x1UL << CAN_F2R1_FB10_Pos)                     /*!< 0x00000400 */
2905 #define CAN_F2R1_FB10          CAN_F2R1_FB10_Msk                               /*!<Filter bit 10 */
2906 #define CAN_F2R1_FB11_Pos      (11U)
2907 #define CAN_F2R1_FB11_Msk      (0x1UL << CAN_F2R1_FB11_Pos)                     /*!< 0x00000800 */
2908 #define CAN_F2R1_FB11          CAN_F2R1_FB11_Msk                               /*!<Filter bit 11 */
2909 #define CAN_F2R1_FB12_Pos      (12U)
2910 #define CAN_F2R1_FB12_Msk      (0x1UL << CAN_F2R1_FB12_Pos)                     /*!< 0x00001000 */
2911 #define CAN_F2R1_FB12          CAN_F2R1_FB12_Msk                               /*!<Filter bit 12 */
2912 #define CAN_F2R1_FB13_Pos      (13U)
2913 #define CAN_F2R1_FB13_Msk      (0x1UL << CAN_F2R1_FB13_Pos)                     /*!< 0x00002000 */
2914 #define CAN_F2R1_FB13          CAN_F2R1_FB13_Msk                               /*!<Filter bit 13 */
2915 #define CAN_F2R1_FB14_Pos      (14U)
2916 #define CAN_F2R1_FB14_Msk      (0x1UL << CAN_F2R1_FB14_Pos)                     /*!< 0x00004000 */
2917 #define CAN_F2R1_FB14          CAN_F2R1_FB14_Msk                               /*!<Filter bit 14 */
2918 #define CAN_F2R1_FB15_Pos      (15U)
2919 #define CAN_F2R1_FB15_Msk      (0x1UL << CAN_F2R1_FB15_Pos)                     /*!< 0x00008000 */
2920 #define CAN_F2R1_FB15          CAN_F2R1_FB15_Msk                               /*!<Filter bit 15 */
2921 #define CAN_F2R1_FB16_Pos      (16U)
2922 #define CAN_F2R1_FB16_Msk      (0x1UL << CAN_F2R1_FB16_Pos)                     /*!< 0x00010000 */
2923 #define CAN_F2R1_FB16          CAN_F2R1_FB16_Msk                               /*!<Filter bit 16 */
2924 #define CAN_F2R1_FB17_Pos      (17U)
2925 #define CAN_F2R1_FB17_Msk      (0x1UL << CAN_F2R1_FB17_Pos)                     /*!< 0x00020000 */
2926 #define CAN_F2R1_FB17          CAN_F2R1_FB17_Msk                               /*!<Filter bit 17 */
2927 #define CAN_F2R1_FB18_Pos      (18U)
2928 #define CAN_F2R1_FB18_Msk      (0x1UL << CAN_F2R1_FB18_Pos)                     /*!< 0x00040000 */
2929 #define CAN_F2R1_FB18          CAN_F2R1_FB18_Msk                               /*!<Filter bit 18 */
2930 #define CAN_F2R1_FB19_Pos      (19U)
2931 #define CAN_F2R1_FB19_Msk      (0x1UL << CAN_F2R1_FB19_Pos)                     /*!< 0x00080000 */
2932 #define CAN_F2R1_FB19          CAN_F2R1_FB19_Msk                               /*!<Filter bit 19 */
2933 #define CAN_F2R1_FB20_Pos      (20U)
2934 #define CAN_F2R1_FB20_Msk      (0x1UL << CAN_F2R1_FB20_Pos)                     /*!< 0x00100000 */
2935 #define CAN_F2R1_FB20          CAN_F2R1_FB20_Msk                               /*!<Filter bit 20 */
2936 #define CAN_F2R1_FB21_Pos      (21U)
2937 #define CAN_F2R1_FB21_Msk      (0x1UL << CAN_F2R1_FB21_Pos)                     /*!< 0x00200000 */
2938 #define CAN_F2R1_FB21          CAN_F2R1_FB21_Msk                               /*!<Filter bit 21 */
2939 #define CAN_F2R1_FB22_Pos      (22U)
2940 #define CAN_F2R1_FB22_Msk      (0x1UL << CAN_F2R1_FB22_Pos)                     /*!< 0x00400000 */
2941 #define CAN_F2R1_FB22          CAN_F2R1_FB22_Msk                               /*!<Filter bit 22 */
2942 #define CAN_F2R1_FB23_Pos      (23U)
2943 #define CAN_F2R1_FB23_Msk      (0x1UL << CAN_F2R1_FB23_Pos)                     /*!< 0x00800000 */
2944 #define CAN_F2R1_FB23          CAN_F2R1_FB23_Msk                               /*!<Filter bit 23 */
2945 #define CAN_F2R1_FB24_Pos      (24U)
2946 #define CAN_F2R1_FB24_Msk      (0x1UL << CAN_F2R1_FB24_Pos)                     /*!< 0x01000000 */
2947 #define CAN_F2R1_FB24          CAN_F2R1_FB24_Msk                               /*!<Filter bit 24 */
2948 #define CAN_F2R1_FB25_Pos      (25U)
2949 #define CAN_F2R1_FB25_Msk      (0x1UL << CAN_F2R1_FB25_Pos)                     /*!< 0x02000000 */
2950 #define CAN_F2R1_FB25          CAN_F2R1_FB25_Msk                               /*!<Filter bit 25 */
2951 #define CAN_F2R1_FB26_Pos      (26U)
2952 #define CAN_F2R1_FB26_Msk      (0x1UL << CAN_F2R1_FB26_Pos)                     /*!< 0x04000000 */
2953 #define CAN_F2R1_FB26          CAN_F2R1_FB26_Msk                               /*!<Filter bit 26 */
2954 #define CAN_F2R1_FB27_Pos      (27U)
2955 #define CAN_F2R1_FB27_Msk      (0x1UL << CAN_F2R1_FB27_Pos)                     /*!< 0x08000000 */
2956 #define CAN_F2R1_FB27          CAN_F2R1_FB27_Msk                               /*!<Filter bit 27 */
2957 #define CAN_F2R1_FB28_Pos      (28U)
2958 #define CAN_F2R1_FB28_Msk      (0x1UL << CAN_F2R1_FB28_Pos)                     /*!< 0x10000000 */
2959 #define CAN_F2R1_FB28          CAN_F2R1_FB28_Msk                               /*!<Filter bit 28 */
2960 #define CAN_F2R1_FB29_Pos      (29U)
2961 #define CAN_F2R1_FB29_Msk      (0x1UL << CAN_F2R1_FB29_Pos)                     /*!< 0x20000000 */
2962 #define CAN_F2R1_FB29          CAN_F2R1_FB29_Msk                               /*!<Filter bit 29 */
2963 #define CAN_F2R1_FB30_Pos      (30U)
2964 #define CAN_F2R1_FB30_Msk      (0x1UL << CAN_F2R1_FB30_Pos)                     /*!< 0x40000000 */
2965 #define CAN_F2R1_FB30          CAN_F2R1_FB30_Msk                               /*!<Filter bit 30 */
2966 #define CAN_F2R1_FB31_Pos      (31U)
2967 #define CAN_F2R1_FB31_Msk      (0x1UL << CAN_F2R1_FB31_Pos)                     /*!< 0x80000000 */
2968 #define CAN_F2R1_FB31          CAN_F2R1_FB31_Msk                               /*!<Filter bit 31 */
2969 
2970 /*******************  Bit definition for CAN_F3R1 register  *******************/
2971 #define CAN_F3R1_FB0_Pos       (0U)
2972 #define CAN_F3R1_FB0_Msk       (0x1UL << CAN_F3R1_FB0_Pos)                      /*!< 0x00000001 */
2973 #define CAN_F3R1_FB0           CAN_F3R1_FB0_Msk                                /*!<Filter bit 0 */
2974 #define CAN_F3R1_FB1_Pos       (1U)
2975 #define CAN_F3R1_FB1_Msk       (0x1UL << CAN_F3R1_FB1_Pos)                      /*!< 0x00000002 */
2976 #define CAN_F3R1_FB1           CAN_F3R1_FB1_Msk                                /*!<Filter bit 1 */
2977 #define CAN_F3R1_FB2_Pos       (2U)
2978 #define CAN_F3R1_FB2_Msk       (0x1UL << CAN_F3R1_FB2_Pos)                      /*!< 0x00000004 */
2979 #define CAN_F3R1_FB2           CAN_F3R1_FB2_Msk                                /*!<Filter bit 2 */
2980 #define CAN_F3R1_FB3_Pos       (3U)
2981 #define CAN_F3R1_FB3_Msk       (0x1UL << CAN_F3R1_FB3_Pos)                      /*!< 0x00000008 */
2982 #define CAN_F3R1_FB3           CAN_F3R1_FB3_Msk                                /*!<Filter bit 3 */
2983 #define CAN_F3R1_FB4_Pos       (4U)
2984 #define CAN_F3R1_FB4_Msk       (0x1UL << CAN_F3R1_FB4_Pos)                      /*!< 0x00000010 */
2985 #define CAN_F3R1_FB4           CAN_F3R1_FB4_Msk                                /*!<Filter bit 4 */
2986 #define CAN_F3R1_FB5_Pos       (5U)
2987 #define CAN_F3R1_FB5_Msk       (0x1UL << CAN_F3R1_FB5_Pos)                      /*!< 0x00000020 */
2988 #define CAN_F3R1_FB5           CAN_F3R1_FB5_Msk                                /*!<Filter bit 5 */
2989 #define CAN_F3R1_FB6_Pos       (6U)
2990 #define CAN_F3R1_FB6_Msk       (0x1UL << CAN_F3R1_FB6_Pos)                      /*!< 0x00000040 */
2991 #define CAN_F3R1_FB6           CAN_F3R1_FB6_Msk                                /*!<Filter bit 6 */
2992 #define CAN_F3R1_FB7_Pos       (7U)
2993 #define CAN_F3R1_FB7_Msk       (0x1UL << CAN_F3R1_FB7_Pos)                      /*!< 0x00000080 */
2994 #define CAN_F3R1_FB7           CAN_F3R1_FB7_Msk                                /*!<Filter bit 7 */
2995 #define CAN_F3R1_FB8_Pos       (8U)
2996 #define CAN_F3R1_FB8_Msk       (0x1UL << CAN_F3R1_FB8_Pos)                      /*!< 0x00000100 */
2997 #define CAN_F3R1_FB8           CAN_F3R1_FB8_Msk                                /*!<Filter bit 8 */
2998 #define CAN_F3R1_FB9_Pos       (9U)
2999 #define CAN_F3R1_FB9_Msk       (0x1UL << CAN_F3R1_FB9_Pos)                      /*!< 0x00000200 */
3000 #define CAN_F3R1_FB9           CAN_F3R1_FB9_Msk                                /*!<Filter bit 9 */
3001 #define CAN_F3R1_FB10_Pos      (10U)
3002 #define CAN_F3R1_FB10_Msk      (0x1UL << CAN_F3R1_FB10_Pos)                     /*!< 0x00000400 */
3003 #define CAN_F3R1_FB10          CAN_F3R1_FB10_Msk                               /*!<Filter bit 10 */
3004 #define CAN_F3R1_FB11_Pos      (11U)
3005 #define CAN_F3R1_FB11_Msk      (0x1UL << CAN_F3R1_FB11_Pos)                     /*!< 0x00000800 */
3006 #define CAN_F3R1_FB11          CAN_F3R1_FB11_Msk                               /*!<Filter bit 11 */
3007 #define CAN_F3R1_FB12_Pos      (12U)
3008 #define CAN_F3R1_FB12_Msk      (0x1UL << CAN_F3R1_FB12_Pos)                     /*!< 0x00001000 */
3009 #define CAN_F3R1_FB12          CAN_F3R1_FB12_Msk                               /*!<Filter bit 12 */
3010 #define CAN_F3R1_FB13_Pos      (13U)
3011 #define CAN_F3R1_FB13_Msk      (0x1UL << CAN_F3R1_FB13_Pos)                     /*!< 0x00002000 */
3012 #define CAN_F3R1_FB13          CAN_F3R1_FB13_Msk                               /*!<Filter bit 13 */
3013 #define CAN_F3R1_FB14_Pos      (14U)
3014 #define CAN_F3R1_FB14_Msk      (0x1UL << CAN_F3R1_FB14_Pos)                     /*!< 0x00004000 */
3015 #define CAN_F3R1_FB14          CAN_F3R1_FB14_Msk                               /*!<Filter bit 14 */
3016 #define CAN_F3R1_FB15_Pos      (15U)
3017 #define CAN_F3R1_FB15_Msk      (0x1UL << CAN_F3R1_FB15_Pos)                     /*!< 0x00008000 */
3018 #define CAN_F3R1_FB15          CAN_F3R1_FB15_Msk                               /*!<Filter bit 15 */
3019 #define CAN_F3R1_FB16_Pos      (16U)
3020 #define CAN_F3R1_FB16_Msk      (0x1UL << CAN_F3R1_FB16_Pos)                     /*!< 0x00010000 */
3021 #define CAN_F3R1_FB16          CAN_F3R1_FB16_Msk                               /*!<Filter bit 16 */
3022 #define CAN_F3R1_FB17_Pos      (17U)
3023 #define CAN_F3R1_FB17_Msk      (0x1UL << CAN_F3R1_FB17_Pos)                     /*!< 0x00020000 */
3024 #define CAN_F3R1_FB17          CAN_F3R1_FB17_Msk                               /*!<Filter bit 17 */
3025 #define CAN_F3R1_FB18_Pos      (18U)
3026 #define CAN_F3R1_FB18_Msk      (0x1UL << CAN_F3R1_FB18_Pos)                     /*!< 0x00040000 */
3027 #define CAN_F3R1_FB18          CAN_F3R1_FB18_Msk                               /*!<Filter bit 18 */
3028 #define CAN_F3R1_FB19_Pos      (19U)
3029 #define CAN_F3R1_FB19_Msk      (0x1UL << CAN_F3R1_FB19_Pos)                     /*!< 0x00080000 */
3030 #define CAN_F3R1_FB19          CAN_F3R1_FB19_Msk                               /*!<Filter bit 19 */
3031 #define CAN_F3R1_FB20_Pos      (20U)
3032 #define CAN_F3R1_FB20_Msk      (0x1UL << CAN_F3R1_FB20_Pos)                     /*!< 0x00100000 */
3033 #define CAN_F3R1_FB20          CAN_F3R1_FB20_Msk                               /*!<Filter bit 20 */
3034 #define CAN_F3R1_FB21_Pos      (21U)
3035 #define CAN_F3R1_FB21_Msk      (0x1UL << CAN_F3R1_FB21_Pos)                     /*!< 0x00200000 */
3036 #define CAN_F3R1_FB21          CAN_F3R1_FB21_Msk                               /*!<Filter bit 21 */
3037 #define CAN_F3R1_FB22_Pos      (22U)
3038 #define CAN_F3R1_FB22_Msk      (0x1UL << CAN_F3R1_FB22_Pos)                     /*!< 0x00400000 */
3039 #define CAN_F3R1_FB22          CAN_F3R1_FB22_Msk                               /*!<Filter bit 22 */
3040 #define CAN_F3R1_FB23_Pos      (23U)
3041 #define CAN_F3R1_FB23_Msk      (0x1UL << CAN_F3R1_FB23_Pos)                     /*!< 0x00800000 */
3042 #define CAN_F3R1_FB23          CAN_F3R1_FB23_Msk                               /*!<Filter bit 23 */
3043 #define CAN_F3R1_FB24_Pos      (24U)
3044 #define CAN_F3R1_FB24_Msk      (0x1UL << CAN_F3R1_FB24_Pos)                     /*!< 0x01000000 */
3045 #define CAN_F3R1_FB24          CAN_F3R1_FB24_Msk                               /*!<Filter bit 24 */
3046 #define CAN_F3R1_FB25_Pos      (25U)
3047 #define CAN_F3R1_FB25_Msk      (0x1UL << CAN_F3R1_FB25_Pos)                     /*!< 0x02000000 */
3048 #define CAN_F3R1_FB25          CAN_F3R1_FB25_Msk                               /*!<Filter bit 25 */
3049 #define CAN_F3R1_FB26_Pos      (26U)
3050 #define CAN_F3R1_FB26_Msk      (0x1UL << CAN_F3R1_FB26_Pos)                     /*!< 0x04000000 */
3051 #define CAN_F3R1_FB26          CAN_F3R1_FB26_Msk                               /*!<Filter bit 26 */
3052 #define CAN_F3R1_FB27_Pos      (27U)
3053 #define CAN_F3R1_FB27_Msk      (0x1UL << CAN_F3R1_FB27_Pos)                     /*!< 0x08000000 */
3054 #define CAN_F3R1_FB27          CAN_F3R1_FB27_Msk                               /*!<Filter bit 27 */
3055 #define CAN_F3R1_FB28_Pos      (28U)
3056 #define CAN_F3R1_FB28_Msk      (0x1UL << CAN_F3R1_FB28_Pos)                     /*!< 0x10000000 */
3057 #define CAN_F3R1_FB28          CAN_F3R1_FB28_Msk                               /*!<Filter bit 28 */
3058 #define CAN_F3R1_FB29_Pos      (29U)
3059 #define CAN_F3R1_FB29_Msk      (0x1UL << CAN_F3R1_FB29_Pos)                     /*!< 0x20000000 */
3060 #define CAN_F3R1_FB29          CAN_F3R1_FB29_Msk                               /*!<Filter bit 29 */
3061 #define CAN_F3R1_FB30_Pos      (30U)
3062 #define CAN_F3R1_FB30_Msk      (0x1UL << CAN_F3R1_FB30_Pos)                     /*!< 0x40000000 */
3063 #define CAN_F3R1_FB30          CAN_F3R1_FB30_Msk                               /*!<Filter bit 30 */
3064 #define CAN_F3R1_FB31_Pos      (31U)
3065 #define CAN_F3R1_FB31_Msk      (0x1UL << CAN_F3R1_FB31_Pos)                     /*!< 0x80000000 */
3066 #define CAN_F3R1_FB31          CAN_F3R1_FB31_Msk                               /*!<Filter bit 31 */
3067 
3068 /*******************  Bit definition for CAN_F4R1 register  *******************/
3069 #define CAN_F4R1_FB0_Pos       (0U)
3070 #define CAN_F4R1_FB0_Msk       (0x1UL << CAN_F4R1_FB0_Pos)                      /*!< 0x00000001 */
3071 #define CAN_F4R1_FB0           CAN_F4R1_FB0_Msk                                /*!<Filter bit 0 */
3072 #define CAN_F4R1_FB1_Pos       (1U)
3073 #define CAN_F4R1_FB1_Msk       (0x1UL << CAN_F4R1_FB1_Pos)                      /*!< 0x00000002 */
3074 #define CAN_F4R1_FB1           CAN_F4R1_FB1_Msk                                /*!<Filter bit 1 */
3075 #define CAN_F4R1_FB2_Pos       (2U)
3076 #define CAN_F4R1_FB2_Msk       (0x1UL << CAN_F4R1_FB2_Pos)                      /*!< 0x00000004 */
3077 #define CAN_F4R1_FB2           CAN_F4R1_FB2_Msk                                /*!<Filter bit 2 */
3078 #define CAN_F4R1_FB3_Pos       (3U)
3079 #define CAN_F4R1_FB3_Msk       (0x1UL << CAN_F4R1_FB3_Pos)                      /*!< 0x00000008 */
3080 #define CAN_F4R1_FB3           CAN_F4R1_FB3_Msk                                /*!<Filter bit 3 */
3081 #define CAN_F4R1_FB4_Pos       (4U)
3082 #define CAN_F4R1_FB4_Msk       (0x1UL << CAN_F4R1_FB4_Pos)                      /*!< 0x00000010 */
3083 #define CAN_F4R1_FB4           CAN_F4R1_FB4_Msk                                /*!<Filter bit 4 */
3084 #define CAN_F4R1_FB5_Pos       (5U)
3085 #define CAN_F4R1_FB5_Msk       (0x1UL << CAN_F4R1_FB5_Pos)                      /*!< 0x00000020 */
3086 #define CAN_F4R1_FB5           CAN_F4R1_FB5_Msk                                /*!<Filter bit 5 */
3087 #define CAN_F4R1_FB6_Pos       (6U)
3088 #define CAN_F4R1_FB6_Msk       (0x1UL << CAN_F4R1_FB6_Pos)                      /*!< 0x00000040 */
3089 #define CAN_F4R1_FB6           CAN_F4R1_FB6_Msk                                /*!<Filter bit 6 */
3090 #define CAN_F4R1_FB7_Pos       (7U)
3091 #define CAN_F4R1_FB7_Msk       (0x1UL << CAN_F4R1_FB7_Pos)                      /*!< 0x00000080 */
3092 #define CAN_F4R1_FB7           CAN_F4R1_FB7_Msk                                /*!<Filter bit 7 */
3093 #define CAN_F4R1_FB8_Pos       (8U)
3094 #define CAN_F4R1_FB8_Msk       (0x1UL << CAN_F4R1_FB8_Pos)                      /*!< 0x00000100 */
3095 #define CAN_F4R1_FB8           CAN_F4R1_FB8_Msk                                /*!<Filter bit 8 */
3096 #define CAN_F4R1_FB9_Pos       (9U)
3097 #define CAN_F4R1_FB9_Msk       (0x1UL << CAN_F4R1_FB9_Pos)                      /*!< 0x00000200 */
3098 #define CAN_F4R1_FB9           CAN_F4R1_FB9_Msk                                /*!<Filter bit 9 */
3099 #define CAN_F4R1_FB10_Pos      (10U)
3100 #define CAN_F4R1_FB10_Msk      (0x1UL << CAN_F4R1_FB10_Pos)                     /*!< 0x00000400 */
3101 #define CAN_F4R1_FB10          CAN_F4R1_FB10_Msk                               /*!<Filter bit 10 */
3102 #define CAN_F4R1_FB11_Pos      (11U)
3103 #define CAN_F4R1_FB11_Msk      (0x1UL << CAN_F4R1_FB11_Pos)                     /*!< 0x00000800 */
3104 #define CAN_F4R1_FB11          CAN_F4R1_FB11_Msk                               /*!<Filter bit 11 */
3105 #define CAN_F4R1_FB12_Pos      (12U)
3106 #define CAN_F4R1_FB12_Msk      (0x1UL << CAN_F4R1_FB12_Pos)                     /*!< 0x00001000 */
3107 #define CAN_F4R1_FB12          CAN_F4R1_FB12_Msk                               /*!<Filter bit 12 */
3108 #define CAN_F4R1_FB13_Pos      (13U)
3109 #define CAN_F4R1_FB13_Msk      (0x1UL << CAN_F4R1_FB13_Pos)                     /*!< 0x00002000 */
3110 #define CAN_F4R1_FB13          CAN_F4R1_FB13_Msk                               /*!<Filter bit 13 */
3111 #define CAN_F4R1_FB14_Pos      (14U)
3112 #define CAN_F4R1_FB14_Msk      (0x1UL << CAN_F4R1_FB14_Pos)                     /*!< 0x00004000 */
3113 #define CAN_F4R1_FB14          CAN_F4R1_FB14_Msk                               /*!<Filter bit 14 */
3114 #define CAN_F4R1_FB15_Pos      (15U)
3115 #define CAN_F4R1_FB15_Msk      (0x1UL << CAN_F4R1_FB15_Pos)                     /*!< 0x00008000 */
3116 #define CAN_F4R1_FB15          CAN_F4R1_FB15_Msk                               /*!<Filter bit 15 */
3117 #define CAN_F4R1_FB16_Pos      (16U)
3118 #define CAN_F4R1_FB16_Msk      (0x1UL << CAN_F4R1_FB16_Pos)                     /*!< 0x00010000 */
3119 #define CAN_F4R1_FB16          CAN_F4R1_FB16_Msk                               /*!<Filter bit 16 */
3120 #define CAN_F4R1_FB17_Pos      (17U)
3121 #define CAN_F4R1_FB17_Msk      (0x1UL << CAN_F4R1_FB17_Pos)                     /*!< 0x00020000 */
3122 #define CAN_F4R1_FB17          CAN_F4R1_FB17_Msk                               /*!<Filter bit 17 */
3123 #define CAN_F4R1_FB18_Pos      (18U)
3124 #define CAN_F4R1_FB18_Msk      (0x1UL << CAN_F4R1_FB18_Pos)                     /*!< 0x00040000 */
3125 #define CAN_F4R1_FB18          CAN_F4R1_FB18_Msk                               /*!<Filter bit 18 */
3126 #define CAN_F4R1_FB19_Pos      (19U)
3127 #define CAN_F4R1_FB19_Msk      (0x1UL << CAN_F4R1_FB19_Pos)                     /*!< 0x00080000 */
3128 #define CAN_F4R1_FB19          CAN_F4R1_FB19_Msk                               /*!<Filter bit 19 */
3129 #define CAN_F4R1_FB20_Pos      (20U)
3130 #define CAN_F4R1_FB20_Msk      (0x1UL << CAN_F4R1_FB20_Pos)                     /*!< 0x00100000 */
3131 #define CAN_F4R1_FB20          CAN_F4R1_FB20_Msk                               /*!<Filter bit 20 */
3132 #define CAN_F4R1_FB21_Pos      (21U)
3133 #define CAN_F4R1_FB21_Msk      (0x1UL << CAN_F4R1_FB21_Pos)                     /*!< 0x00200000 */
3134 #define CAN_F4R1_FB21          CAN_F4R1_FB21_Msk                               /*!<Filter bit 21 */
3135 #define CAN_F4R1_FB22_Pos      (22U)
3136 #define CAN_F4R1_FB22_Msk      (0x1UL << CAN_F4R1_FB22_Pos)                     /*!< 0x00400000 */
3137 #define CAN_F4R1_FB22          CAN_F4R1_FB22_Msk                               /*!<Filter bit 22 */
3138 #define CAN_F4R1_FB23_Pos      (23U)
3139 #define CAN_F4R1_FB23_Msk      (0x1UL << CAN_F4R1_FB23_Pos)                     /*!< 0x00800000 */
3140 #define CAN_F4R1_FB23          CAN_F4R1_FB23_Msk                               /*!<Filter bit 23 */
3141 #define CAN_F4R1_FB24_Pos      (24U)
3142 #define CAN_F4R1_FB24_Msk      (0x1UL << CAN_F4R1_FB24_Pos)                     /*!< 0x01000000 */
3143 #define CAN_F4R1_FB24          CAN_F4R1_FB24_Msk                               /*!<Filter bit 24 */
3144 #define CAN_F4R1_FB25_Pos      (25U)
3145 #define CAN_F4R1_FB25_Msk      (0x1UL << CAN_F4R1_FB25_Pos)                     /*!< 0x02000000 */
3146 #define CAN_F4R1_FB25          CAN_F4R1_FB25_Msk                               /*!<Filter bit 25 */
3147 #define CAN_F4R1_FB26_Pos      (26U)
3148 #define CAN_F4R1_FB26_Msk      (0x1UL << CAN_F4R1_FB26_Pos)                     /*!< 0x04000000 */
3149 #define CAN_F4R1_FB26          CAN_F4R1_FB26_Msk                               /*!<Filter bit 26 */
3150 #define CAN_F4R1_FB27_Pos      (27U)
3151 #define CAN_F4R1_FB27_Msk      (0x1UL << CAN_F4R1_FB27_Pos)                     /*!< 0x08000000 */
3152 #define CAN_F4R1_FB27          CAN_F4R1_FB27_Msk                               /*!<Filter bit 27 */
3153 #define CAN_F4R1_FB28_Pos      (28U)
3154 #define CAN_F4R1_FB28_Msk      (0x1UL << CAN_F4R1_FB28_Pos)                     /*!< 0x10000000 */
3155 #define CAN_F4R1_FB28          CAN_F4R1_FB28_Msk                               /*!<Filter bit 28 */
3156 #define CAN_F4R1_FB29_Pos      (29U)
3157 #define CAN_F4R1_FB29_Msk      (0x1UL << CAN_F4R1_FB29_Pos)                     /*!< 0x20000000 */
3158 #define CAN_F4R1_FB29          CAN_F4R1_FB29_Msk                               /*!<Filter bit 29 */
3159 #define CAN_F4R1_FB30_Pos      (30U)
3160 #define CAN_F4R1_FB30_Msk      (0x1UL << CAN_F4R1_FB30_Pos)                     /*!< 0x40000000 */
3161 #define CAN_F4R1_FB30          CAN_F4R1_FB30_Msk                               /*!<Filter bit 30 */
3162 #define CAN_F4R1_FB31_Pos      (31U)
3163 #define CAN_F4R1_FB31_Msk      (0x1UL << CAN_F4R1_FB31_Pos)                     /*!< 0x80000000 */
3164 #define CAN_F4R1_FB31          CAN_F4R1_FB31_Msk                               /*!<Filter bit 31 */
3165 
3166 /*******************  Bit definition for CAN_F5R1 register  *******************/
3167 #define CAN_F5R1_FB0_Pos       (0U)
3168 #define CAN_F5R1_FB0_Msk       (0x1UL << CAN_F5R1_FB0_Pos)                      /*!< 0x00000001 */
3169 #define CAN_F5R1_FB0           CAN_F5R1_FB0_Msk                                /*!<Filter bit 0 */
3170 #define CAN_F5R1_FB1_Pos       (1U)
3171 #define CAN_F5R1_FB1_Msk       (0x1UL << CAN_F5R1_FB1_Pos)                      /*!< 0x00000002 */
3172 #define CAN_F5R1_FB1           CAN_F5R1_FB1_Msk                                /*!<Filter bit 1 */
3173 #define CAN_F5R1_FB2_Pos       (2U)
3174 #define CAN_F5R1_FB2_Msk       (0x1UL << CAN_F5R1_FB2_Pos)                      /*!< 0x00000004 */
3175 #define CAN_F5R1_FB2           CAN_F5R1_FB2_Msk                                /*!<Filter bit 2 */
3176 #define CAN_F5R1_FB3_Pos       (3U)
3177 #define CAN_F5R1_FB3_Msk       (0x1UL << CAN_F5R1_FB3_Pos)                      /*!< 0x00000008 */
3178 #define CAN_F5R1_FB3           CAN_F5R1_FB3_Msk                                /*!<Filter bit 3 */
3179 #define CAN_F5R1_FB4_Pos       (4U)
3180 #define CAN_F5R1_FB4_Msk       (0x1UL << CAN_F5R1_FB4_Pos)                      /*!< 0x00000010 */
3181 #define CAN_F5R1_FB4           CAN_F5R1_FB4_Msk                                /*!<Filter bit 4 */
3182 #define CAN_F5R1_FB5_Pos       (5U)
3183 #define CAN_F5R1_FB5_Msk       (0x1UL << CAN_F5R1_FB5_Pos)                      /*!< 0x00000020 */
3184 #define CAN_F5R1_FB5           CAN_F5R1_FB5_Msk                                /*!<Filter bit 5 */
3185 #define CAN_F5R1_FB6_Pos       (6U)
3186 #define CAN_F5R1_FB6_Msk       (0x1UL << CAN_F5R1_FB6_Pos)                      /*!< 0x00000040 */
3187 #define CAN_F5R1_FB6           CAN_F5R1_FB6_Msk                                /*!<Filter bit 6 */
3188 #define CAN_F5R1_FB7_Pos       (7U)
3189 #define CAN_F5R1_FB7_Msk       (0x1UL << CAN_F5R1_FB7_Pos)                      /*!< 0x00000080 */
3190 #define CAN_F5R1_FB7           CAN_F5R1_FB7_Msk                                /*!<Filter bit 7 */
3191 #define CAN_F5R1_FB8_Pos       (8U)
3192 #define CAN_F5R1_FB8_Msk       (0x1UL << CAN_F5R1_FB8_Pos)                      /*!< 0x00000100 */
3193 #define CAN_F5R1_FB8           CAN_F5R1_FB8_Msk                                /*!<Filter bit 8 */
3194 #define CAN_F5R1_FB9_Pos       (9U)
3195 #define CAN_F5R1_FB9_Msk       (0x1UL << CAN_F5R1_FB9_Pos)                      /*!< 0x00000200 */
3196 #define CAN_F5R1_FB9           CAN_F5R1_FB9_Msk                                /*!<Filter bit 9 */
3197 #define CAN_F5R1_FB10_Pos      (10U)
3198 #define CAN_F5R1_FB10_Msk      (0x1UL << CAN_F5R1_FB10_Pos)                     /*!< 0x00000400 */
3199 #define CAN_F5R1_FB10          CAN_F5R1_FB10_Msk                               /*!<Filter bit 10 */
3200 #define CAN_F5R1_FB11_Pos      (11U)
3201 #define CAN_F5R1_FB11_Msk      (0x1UL << CAN_F5R1_FB11_Pos)                     /*!< 0x00000800 */
3202 #define CAN_F5R1_FB11          CAN_F5R1_FB11_Msk                               /*!<Filter bit 11 */
3203 #define CAN_F5R1_FB12_Pos      (12U)
3204 #define CAN_F5R1_FB12_Msk      (0x1UL << CAN_F5R1_FB12_Pos)                     /*!< 0x00001000 */
3205 #define CAN_F5R1_FB12          CAN_F5R1_FB12_Msk                               /*!<Filter bit 12 */
3206 #define CAN_F5R1_FB13_Pos      (13U)
3207 #define CAN_F5R1_FB13_Msk      (0x1UL << CAN_F5R1_FB13_Pos)                     /*!< 0x00002000 */
3208 #define CAN_F5R1_FB13          CAN_F5R1_FB13_Msk                               /*!<Filter bit 13 */
3209 #define CAN_F5R1_FB14_Pos      (14U)
3210 #define CAN_F5R1_FB14_Msk      (0x1UL << CAN_F5R1_FB14_Pos)                     /*!< 0x00004000 */
3211 #define CAN_F5R1_FB14          CAN_F5R1_FB14_Msk                               /*!<Filter bit 14 */
3212 #define CAN_F5R1_FB15_Pos      (15U)
3213 #define CAN_F5R1_FB15_Msk      (0x1UL << CAN_F5R1_FB15_Pos)                     /*!< 0x00008000 */
3214 #define CAN_F5R1_FB15          CAN_F5R1_FB15_Msk                               /*!<Filter bit 15 */
3215 #define CAN_F5R1_FB16_Pos      (16U)
3216 #define CAN_F5R1_FB16_Msk      (0x1UL << CAN_F5R1_FB16_Pos)                     /*!< 0x00010000 */
3217 #define CAN_F5R1_FB16          CAN_F5R1_FB16_Msk                               /*!<Filter bit 16 */
3218 #define CAN_F5R1_FB17_Pos      (17U)
3219 #define CAN_F5R1_FB17_Msk      (0x1UL << CAN_F5R1_FB17_Pos)                     /*!< 0x00020000 */
3220 #define CAN_F5R1_FB17          CAN_F5R1_FB17_Msk                               /*!<Filter bit 17 */
3221 #define CAN_F5R1_FB18_Pos      (18U)
3222 #define CAN_F5R1_FB18_Msk      (0x1UL << CAN_F5R1_FB18_Pos)                     /*!< 0x00040000 */
3223 #define CAN_F5R1_FB18          CAN_F5R1_FB18_Msk                               /*!<Filter bit 18 */
3224 #define CAN_F5R1_FB19_Pos      (19U)
3225 #define CAN_F5R1_FB19_Msk      (0x1UL << CAN_F5R1_FB19_Pos)                     /*!< 0x00080000 */
3226 #define CAN_F5R1_FB19          CAN_F5R1_FB19_Msk                               /*!<Filter bit 19 */
3227 #define CAN_F5R1_FB20_Pos      (20U)
3228 #define CAN_F5R1_FB20_Msk      (0x1UL << CAN_F5R1_FB20_Pos)                     /*!< 0x00100000 */
3229 #define CAN_F5R1_FB20          CAN_F5R1_FB20_Msk                               /*!<Filter bit 20 */
3230 #define CAN_F5R1_FB21_Pos      (21U)
3231 #define CAN_F5R1_FB21_Msk      (0x1UL << CAN_F5R1_FB21_Pos)                     /*!< 0x00200000 */
3232 #define CAN_F5R1_FB21          CAN_F5R1_FB21_Msk                               /*!<Filter bit 21 */
3233 #define CAN_F5R1_FB22_Pos      (22U)
3234 #define CAN_F5R1_FB22_Msk      (0x1UL << CAN_F5R1_FB22_Pos)                     /*!< 0x00400000 */
3235 #define CAN_F5R1_FB22          CAN_F5R1_FB22_Msk                               /*!<Filter bit 22 */
3236 #define CAN_F5R1_FB23_Pos      (23U)
3237 #define CAN_F5R1_FB23_Msk      (0x1UL << CAN_F5R1_FB23_Pos)                     /*!< 0x00800000 */
3238 #define CAN_F5R1_FB23          CAN_F5R1_FB23_Msk                               /*!<Filter bit 23 */
3239 #define CAN_F5R1_FB24_Pos      (24U)
3240 #define CAN_F5R1_FB24_Msk      (0x1UL << CAN_F5R1_FB24_Pos)                     /*!< 0x01000000 */
3241 #define CAN_F5R1_FB24          CAN_F5R1_FB24_Msk                               /*!<Filter bit 24 */
3242 #define CAN_F5R1_FB25_Pos      (25U)
3243 #define CAN_F5R1_FB25_Msk      (0x1UL << CAN_F5R1_FB25_Pos)                     /*!< 0x02000000 */
3244 #define CAN_F5R1_FB25          CAN_F5R1_FB25_Msk                               /*!<Filter bit 25 */
3245 #define CAN_F5R1_FB26_Pos      (26U)
3246 #define CAN_F5R1_FB26_Msk      (0x1UL << CAN_F5R1_FB26_Pos)                     /*!< 0x04000000 */
3247 #define CAN_F5R1_FB26          CAN_F5R1_FB26_Msk                               /*!<Filter bit 26 */
3248 #define CAN_F5R1_FB27_Pos      (27U)
3249 #define CAN_F5R1_FB27_Msk      (0x1UL << CAN_F5R1_FB27_Pos)                     /*!< 0x08000000 */
3250 #define CAN_F5R1_FB27          CAN_F5R1_FB27_Msk                               /*!<Filter bit 27 */
3251 #define CAN_F5R1_FB28_Pos      (28U)
3252 #define CAN_F5R1_FB28_Msk      (0x1UL << CAN_F5R1_FB28_Pos)                     /*!< 0x10000000 */
3253 #define CAN_F5R1_FB28          CAN_F5R1_FB28_Msk                               /*!<Filter bit 28 */
3254 #define CAN_F5R1_FB29_Pos      (29U)
3255 #define CAN_F5R1_FB29_Msk      (0x1UL << CAN_F5R1_FB29_Pos)                     /*!< 0x20000000 */
3256 #define CAN_F5R1_FB29          CAN_F5R1_FB29_Msk                               /*!<Filter bit 29 */
3257 #define CAN_F5R1_FB30_Pos      (30U)
3258 #define CAN_F5R1_FB30_Msk      (0x1UL << CAN_F5R1_FB30_Pos)                     /*!< 0x40000000 */
3259 #define CAN_F5R1_FB30          CAN_F5R1_FB30_Msk                               /*!<Filter bit 30 */
3260 #define CAN_F5R1_FB31_Pos      (31U)
3261 #define CAN_F5R1_FB31_Msk      (0x1UL << CAN_F5R1_FB31_Pos)                     /*!< 0x80000000 */
3262 #define CAN_F5R1_FB31          CAN_F5R1_FB31_Msk                               /*!<Filter bit 31 */
3263 
3264 /*******************  Bit definition for CAN_F6R1 register  *******************/
3265 #define CAN_F6R1_FB0_Pos       (0U)
3266 #define CAN_F6R1_FB0_Msk       (0x1UL << CAN_F6R1_FB0_Pos)                      /*!< 0x00000001 */
3267 #define CAN_F6R1_FB0           CAN_F6R1_FB0_Msk                                /*!<Filter bit 0 */
3268 #define CAN_F6R1_FB1_Pos       (1U)
3269 #define CAN_F6R1_FB1_Msk       (0x1UL << CAN_F6R1_FB1_Pos)                      /*!< 0x00000002 */
3270 #define CAN_F6R1_FB1           CAN_F6R1_FB1_Msk                                /*!<Filter bit 1 */
3271 #define CAN_F6R1_FB2_Pos       (2U)
3272 #define CAN_F6R1_FB2_Msk       (0x1UL << CAN_F6R1_FB2_Pos)                      /*!< 0x00000004 */
3273 #define CAN_F6R1_FB2           CAN_F6R1_FB2_Msk                                /*!<Filter bit 2 */
3274 #define CAN_F6R1_FB3_Pos       (3U)
3275 #define CAN_F6R1_FB3_Msk       (0x1UL << CAN_F6R1_FB3_Pos)                      /*!< 0x00000008 */
3276 #define CAN_F6R1_FB3           CAN_F6R1_FB3_Msk                                /*!<Filter bit 3 */
3277 #define CAN_F6R1_FB4_Pos       (4U)
3278 #define CAN_F6R1_FB4_Msk       (0x1UL << CAN_F6R1_FB4_Pos)                      /*!< 0x00000010 */
3279 #define CAN_F6R1_FB4           CAN_F6R1_FB4_Msk                                /*!<Filter bit 4 */
3280 #define CAN_F6R1_FB5_Pos       (5U)
3281 #define CAN_F6R1_FB5_Msk       (0x1UL << CAN_F6R1_FB5_Pos)                      /*!< 0x00000020 */
3282 #define CAN_F6R1_FB5           CAN_F6R1_FB5_Msk                                /*!<Filter bit 5 */
3283 #define CAN_F6R1_FB6_Pos       (6U)
3284 #define CAN_F6R1_FB6_Msk       (0x1UL << CAN_F6R1_FB6_Pos)                      /*!< 0x00000040 */
3285 #define CAN_F6R1_FB6           CAN_F6R1_FB6_Msk                                /*!<Filter bit 6 */
3286 #define CAN_F6R1_FB7_Pos       (7U)
3287 #define CAN_F6R1_FB7_Msk       (0x1UL << CAN_F6R1_FB7_Pos)                      /*!< 0x00000080 */
3288 #define CAN_F6R1_FB7           CAN_F6R1_FB7_Msk                                /*!<Filter bit 7 */
3289 #define CAN_F6R1_FB8_Pos       (8U)
3290 #define CAN_F6R1_FB8_Msk       (0x1UL << CAN_F6R1_FB8_Pos)                      /*!< 0x00000100 */
3291 #define CAN_F6R1_FB8           CAN_F6R1_FB8_Msk                                /*!<Filter bit 8 */
3292 #define CAN_F6R1_FB9_Pos       (9U)
3293 #define CAN_F6R1_FB9_Msk       (0x1UL << CAN_F6R1_FB9_Pos)                      /*!< 0x00000200 */
3294 #define CAN_F6R1_FB9           CAN_F6R1_FB9_Msk                                /*!<Filter bit 9 */
3295 #define CAN_F6R1_FB10_Pos      (10U)
3296 #define CAN_F6R1_FB10_Msk      (0x1UL << CAN_F6R1_FB10_Pos)                     /*!< 0x00000400 */
3297 #define CAN_F6R1_FB10          CAN_F6R1_FB10_Msk                               /*!<Filter bit 10 */
3298 #define CAN_F6R1_FB11_Pos      (11U)
3299 #define CAN_F6R1_FB11_Msk      (0x1UL << CAN_F6R1_FB11_Pos)                     /*!< 0x00000800 */
3300 #define CAN_F6R1_FB11          CAN_F6R1_FB11_Msk                               /*!<Filter bit 11 */
3301 #define CAN_F6R1_FB12_Pos      (12U)
3302 #define CAN_F6R1_FB12_Msk      (0x1UL << CAN_F6R1_FB12_Pos)                     /*!< 0x00001000 */
3303 #define CAN_F6R1_FB12          CAN_F6R1_FB12_Msk                               /*!<Filter bit 12 */
3304 #define CAN_F6R1_FB13_Pos      (13U)
3305 #define CAN_F6R1_FB13_Msk      (0x1UL << CAN_F6R1_FB13_Pos)                     /*!< 0x00002000 */
3306 #define CAN_F6R1_FB13          CAN_F6R1_FB13_Msk                               /*!<Filter bit 13 */
3307 #define CAN_F6R1_FB14_Pos      (14U)
3308 #define CAN_F6R1_FB14_Msk      (0x1UL << CAN_F6R1_FB14_Pos)                     /*!< 0x00004000 */
3309 #define CAN_F6R1_FB14          CAN_F6R1_FB14_Msk                               /*!<Filter bit 14 */
3310 #define CAN_F6R1_FB15_Pos      (15U)
3311 #define CAN_F6R1_FB15_Msk      (0x1UL << CAN_F6R1_FB15_Pos)                     /*!< 0x00008000 */
3312 #define CAN_F6R1_FB15          CAN_F6R1_FB15_Msk                               /*!<Filter bit 15 */
3313 #define CAN_F6R1_FB16_Pos      (16U)
3314 #define CAN_F6R1_FB16_Msk      (0x1UL << CAN_F6R1_FB16_Pos)                     /*!< 0x00010000 */
3315 #define CAN_F6R1_FB16          CAN_F6R1_FB16_Msk                               /*!<Filter bit 16 */
3316 #define CAN_F6R1_FB17_Pos      (17U)
3317 #define CAN_F6R1_FB17_Msk      (0x1UL << CAN_F6R1_FB17_Pos)                     /*!< 0x00020000 */
3318 #define CAN_F6R1_FB17          CAN_F6R1_FB17_Msk                               /*!<Filter bit 17 */
3319 #define CAN_F6R1_FB18_Pos      (18U)
3320 #define CAN_F6R1_FB18_Msk      (0x1UL << CAN_F6R1_FB18_Pos)                     /*!< 0x00040000 */
3321 #define CAN_F6R1_FB18          CAN_F6R1_FB18_Msk                               /*!<Filter bit 18 */
3322 #define CAN_F6R1_FB19_Pos      (19U)
3323 #define CAN_F6R1_FB19_Msk      (0x1UL << CAN_F6R1_FB19_Pos)                     /*!< 0x00080000 */
3324 #define CAN_F6R1_FB19          CAN_F6R1_FB19_Msk                               /*!<Filter bit 19 */
3325 #define CAN_F6R1_FB20_Pos      (20U)
3326 #define CAN_F6R1_FB20_Msk      (0x1UL << CAN_F6R1_FB20_Pos)                     /*!< 0x00100000 */
3327 #define CAN_F6R1_FB20          CAN_F6R1_FB20_Msk                               /*!<Filter bit 20 */
3328 #define CAN_F6R1_FB21_Pos      (21U)
3329 #define CAN_F6R1_FB21_Msk      (0x1UL << CAN_F6R1_FB21_Pos)                     /*!< 0x00200000 */
3330 #define CAN_F6R1_FB21          CAN_F6R1_FB21_Msk                               /*!<Filter bit 21 */
3331 #define CAN_F6R1_FB22_Pos      (22U)
3332 #define CAN_F6R1_FB22_Msk      (0x1UL << CAN_F6R1_FB22_Pos)                     /*!< 0x00400000 */
3333 #define CAN_F6R1_FB22          CAN_F6R1_FB22_Msk                               /*!<Filter bit 22 */
3334 #define CAN_F6R1_FB23_Pos      (23U)
3335 #define CAN_F6R1_FB23_Msk      (0x1UL << CAN_F6R1_FB23_Pos)                     /*!< 0x00800000 */
3336 #define CAN_F6R1_FB23          CAN_F6R1_FB23_Msk                               /*!<Filter bit 23 */
3337 #define CAN_F6R1_FB24_Pos      (24U)
3338 #define CAN_F6R1_FB24_Msk      (0x1UL << CAN_F6R1_FB24_Pos)                     /*!< 0x01000000 */
3339 #define CAN_F6R1_FB24          CAN_F6R1_FB24_Msk                               /*!<Filter bit 24 */
3340 #define CAN_F6R1_FB25_Pos      (25U)
3341 #define CAN_F6R1_FB25_Msk      (0x1UL << CAN_F6R1_FB25_Pos)                     /*!< 0x02000000 */
3342 #define CAN_F6R1_FB25          CAN_F6R1_FB25_Msk                               /*!<Filter bit 25 */
3343 #define CAN_F6R1_FB26_Pos      (26U)
3344 #define CAN_F6R1_FB26_Msk      (0x1UL << CAN_F6R1_FB26_Pos)                     /*!< 0x04000000 */
3345 #define CAN_F6R1_FB26          CAN_F6R1_FB26_Msk                               /*!<Filter bit 26 */
3346 #define CAN_F6R1_FB27_Pos      (27U)
3347 #define CAN_F6R1_FB27_Msk      (0x1UL << CAN_F6R1_FB27_Pos)                     /*!< 0x08000000 */
3348 #define CAN_F6R1_FB27          CAN_F6R1_FB27_Msk                               /*!<Filter bit 27 */
3349 #define CAN_F6R1_FB28_Pos      (28U)
3350 #define CAN_F6R1_FB28_Msk      (0x1UL << CAN_F6R1_FB28_Pos)                     /*!< 0x10000000 */
3351 #define CAN_F6R1_FB28          CAN_F6R1_FB28_Msk                               /*!<Filter bit 28 */
3352 #define CAN_F6R1_FB29_Pos      (29U)
3353 #define CAN_F6R1_FB29_Msk      (0x1UL << CAN_F6R1_FB29_Pos)                     /*!< 0x20000000 */
3354 #define CAN_F6R1_FB29          CAN_F6R1_FB29_Msk                               /*!<Filter bit 29 */
3355 #define CAN_F6R1_FB30_Pos      (30U)
3356 #define CAN_F6R1_FB30_Msk      (0x1UL << CAN_F6R1_FB30_Pos)                     /*!< 0x40000000 */
3357 #define CAN_F6R1_FB30          CAN_F6R1_FB30_Msk                               /*!<Filter bit 30 */
3358 #define CAN_F6R1_FB31_Pos      (31U)
3359 #define CAN_F6R1_FB31_Msk      (0x1UL << CAN_F6R1_FB31_Pos)                     /*!< 0x80000000 */
3360 #define CAN_F6R1_FB31          CAN_F6R1_FB31_Msk                               /*!<Filter bit 31 */
3361 
3362 /*******************  Bit definition for CAN_F7R1 register  *******************/
3363 #define CAN_F7R1_FB0_Pos       (0U)
3364 #define CAN_F7R1_FB0_Msk       (0x1UL << CAN_F7R1_FB0_Pos)                      /*!< 0x00000001 */
3365 #define CAN_F7R1_FB0           CAN_F7R1_FB0_Msk                                /*!<Filter bit 0 */
3366 #define CAN_F7R1_FB1_Pos       (1U)
3367 #define CAN_F7R1_FB1_Msk       (0x1UL << CAN_F7R1_FB1_Pos)                      /*!< 0x00000002 */
3368 #define CAN_F7R1_FB1           CAN_F7R1_FB1_Msk                                /*!<Filter bit 1 */
3369 #define CAN_F7R1_FB2_Pos       (2U)
3370 #define CAN_F7R1_FB2_Msk       (0x1UL << CAN_F7R1_FB2_Pos)                      /*!< 0x00000004 */
3371 #define CAN_F7R1_FB2           CAN_F7R1_FB2_Msk                                /*!<Filter bit 2 */
3372 #define CAN_F7R1_FB3_Pos       (3U)
3373 #define CAN_F7R1_FB3_Msk       (0x1UL << CAN_F7R1_FB3_Pos)                      /*!< 0x00000008 */
3374 #define CAN_F7R1_FB3           CAN_F7R1_FB3_Msk                                /*!<Filter bit 3 */
3375 #define CAN_F7R1_FB4_Pos       (4U)
3376 #define CAN_F7R1_FB4_Msk       (0x1UL << CAN_F7R1_FB4_Pos)                      /*!< 0x00000010 */
3377 #define CAN_F7R1_FB4           CAN_F7R1_FB4_Msk                                /*!<Filter bit 4 */
3378 #define CAN_F7R1_FB5_Pos       (5U)
3379 #define CAN_F7R1_FB5_Msk       (0x1UL << CAN_F7R1_FB5_Pos)                      /*!< 0x00000020 */
3380 #define CAN_F7R1_FB5           CAN_F7R1_FB5_Msk                                /*!<Filter bit 5 */
3381 #define CAN_F7R1_FB6_Pos       (6U)
3382 #define CAN_F7R1_FB6_Msk       (0x1UL << CAN_F7R1_FB6_Pos)                      /*!< 0x00000040 */
3383 #define CAN_F7R1_FB6           CAN_F7R1_FB6_Msk                                /*!<Filter bit 6 */
3384 #define CAN_F7R1_FB7_Pos       (7U)
3385 #define CAN_F7R1_FB7_Msk       (0x1UL << CAN_F7R1_FB7_Pos)                      /*!< 0x00000080 */
3386 #define CAN_F7R1_FB7           CAN_F7R1_FB7_Msk                                /*!<Filter bit 7 */
3387 #define CAN_F7R1_FB8_Pos       (8U)
3388 #define CAN_F7R1_FB8_Msk       (0x1UL << CAN_F7R1_FB8_Pos)                      /*!< 0x00000100 */
3389 #define CAN_F7R1_FB8           CAN_F7R1_FB8_Msk                                /*!<Filter bit 8 */
3390 #define CAN_F7R1_FB9_Pos       (9U)
3391 #define CAN_F7R1_FB9_Msk       (0x1UL << CAN_F7R1_FB9_Pos)                      /*!< 0x00000200 */
3392 #define CAN_F7R1_FB9           CAN_F7R1_FB9_Msk                                /*!<Filter bit 9 */
3393 #define CAN_F7R1_FB10_Pos      (10U)
3394 #define CAN_F7R1_FB10_Msk      (0x1UL << CAN_F7R1_FB10_Pos)                     /*!< 0x00000400 */
3395 #define CAN_F7R1_FB10          CAN_F7R1_FB10_Msk                               /*!<Filter bit 10 */
3396 #define CAN_F7R1_FB11_Pos      (11U)
3397 #define CAN_F7R1_FB11_Msk      (0x1UL << CAN_F7R1_FB11_Pos)                     /*!< 0x00000800 */
3398 #define CAN_F7R1_FB11          CAN_F7R1_FB11_Msk                               /*!<Filter bit 11 */
3399 #define CAN_F7R1_FB12_Pos      (12U)
3400 #define CAN_F7R1_FB12_Msk      (0x1UL << CAN_F7R1_FB12_Pos)                     /*!< 0x00001000 */
3401 #define CAN_F7R1_FB12          CAN_F7R1_FB12_Msk                               /*!<Filter bit 12 */
3402 #define CAN_F7R1_FB13_Pos      (13U)
3403 #define CAN_F7R1_FB13_Msk      (0x1UL << CAN_F7R1_FB13_Pos)                     /*!< 0x00002000 */
3404 #define CAN_F7R1_FB13          CAN_F7R1_FB13_Msk                               /*!<Filter bit 13 */
3405 #define CAN_F7R1_FB14_Pos      (14U)
3406 #define CAN_F7R1_FB14_Msk      (0x1UL << CAN_F7R1_FB14_Pos)                     /*!< 0x00004000 */
3407 #define CAN_F7R1_FB14          CAN_F7R1_FB14_Msk                               /*!<Filter bit 14 */
3408 #define CAN_F7R1_FB15_Pos      (15U)
3409 #define CAN_F7R1_FB15_Msk      (0x1UL << CAN_F7R1_FB15_Pos)                     /*!< 0x00008000 */
3410 #define CAN_F7R1_FB15          CAN_F7R1_FB15_Msk                               /*!<Filter bit 15 */
3411 #define CAN_F7R1_FB16_Pos      (16U)
3412 #define CAN_F7R1_FB16_Msk      (0x1UL << CAN_F7R1_FB16_Pos)                     /*!< 0x00010000 */
3413 #define CAN_F7R1_FB16          CAN_F7R1_FB16_Msk                               /*!<Filter bit 16 */
3414 #define CAN_F7R1_FB17_Pos      (17U)
3415 #define CAN_F7R1_FB17_Msk      (0x1UL << CAN_F7R1_FB17_Pos)                     /*!< 0x00020000 */
3416 #define CAN_F7R1_FB17          CAN_F7R1_FB17_Msk                               /*!<Filter bit 17 */
3417 #define CAN_F7R1_FB18_Pos      (18U)
3418 #define CAN_F7R1_FB18_Msk      (0x1UL << CAN_F7R1_FB18_Pos)                     /*!< 0x00040000 */
3419 #define CAN_F7R1_FB18          CAN_F7R1_FB18_Msk                               /*!<Filter bit 18 */
3420 #define CAN_F7R1_FB19_Pos      (19U)
3421 #define CAN_F7R1_FB19_Msk      (0x1UL << CAN_F7R1_FB19_Pos)                     /*!< 0x00080000 */
3422 #define CAN_F7R1_FB19          CAN_F7R1_FB19_Msk                               /*!<Filter bit 19 */
3423 #define CAN_F7R1_FB20_Pos      (20U)
3424 #define CAN_F7R1_FB20_Msk      (0x1UL << CAN_F7R1_FB20_Pos)                     /*!< 0x00100000 */
3425 #define CAN_F7R1_FB20          CAN_F7R1_FB20_Msk                               /*!<Filter bit 20 */
3426 #define CAN_F7R1_FB21_Pos      (21U)
3427 #define CAN_F7R1_FB21_Msk      (0x1UL << CAN_F7R1_FB21_Pos)                     /*!< 0x00200000 */
3428 #define CAN_F7R1_FB21          CAN_F7R1_FB21_Msk                               /*!<Filter bit 21 */
3429 #define CAN_F7R1_FB22_Pos      (22U)
3430 #define CAN_F7R1_FB22_Msk      (0x1UL << CAN_F7R1_FB22_Pos)                     /*!< 0x00400000 */
3431 #define CAN_F7R1_FB22          CAN_F7R1_FB22_Msk                               /*!<Filter bit 22 */
3432 #define CAN_F7R1_FB23_Pos      (23U)
3433 #define CAN_F7R1_FB23_Msk      (0x1UL << CAN_F7R1_FB23_Pos)                     /*!< 0x00800000 */
3434 #define CAN_F7R1_FB23          CAN_F7R1_FB23_Msk                               /*!<Filter bit 23 */
3435 #define CAN_F7R1_FB24_Pos      (24U)
3436 #define CAN_F7R1_FB24_Msk      (0x1UL << CAN_F7R1_FB24_Pos)                     /*!< 0x01000000 */
3437 #define CAN_F7R1_FB24          CAN_F7R1_FB24_Msk                               /*!<Filter bit 24 */
3438 #define CAN_F7R1_FB25_Pos      (25U)
3439 #define CAN_F7R1_FB25_Msk      (0x1UL << CAN_F7R1_FB25_Pos)                     /*!< 0x02000000 */
3440 #define CAN_F7R1_FB25          CAN_F7R1_FB25_Msk                               /*!<Filter bit 25 */
3441 #define CAN_F7R1_FB26_Pos      (26U)
3442 #define CAN_F7R1_FB26_Msk      (0x1UL << CAN_F7R1_FB26_Pos)                     /*!< 0x04000000 */
3443 #define CAN_F7R1_FB26          CAN_F7R1_FB26_Msk                               /*!<Filter bit 26 */
3444 #define CAN_F7R1_FB27_Pos      (27U)
3445 #define CAN_F7R1_FB27_Msk      (0x1UL << CAN_F7R1_FB27_Pos)                     /*!< 0x08000000 */
3446 #define CAN_F7R1_FB27          CAN_F7R1_FB27_Msk                               /*!<Filter bit 27 */
3447 #define CAN_F7R1_FB28_Pos      (28U)
3448 #define CAN_F7R1_FB28_Msk      (0x1UL << CAN_F7R1_FB28_Pos)                     /*!< 0x10000000 */
3449 #define CAN_F7R1_FB28          CAN_F7R1_FB28_Msk                               /*!<Filter bit 28 */
3450 #define CAN_F7R1_FB29_Pos      (29U)
3451 #define CAN_F7R1_FB29_Msk      (0x1UL << CAN_F7R1_FB29_Pos)                     /*!< 0x20000000 */
3452 #define CAN_F7R1_FB29          CAN_F7R1_FB29_Msk                               /*!<Filter bit 29 */
3453 #define CAN_F7R1_FB30_Pos      (30U)
3454 #define CAN_F7R1_FB30_Msk      (0x1UL << CAN_F7R1_FB30_Pos)                     /*!< 0x40000000 */
3455 #define CAN_F7R1_FB30          CAN_F7R1_FB30_Msk                               /*!<Filter bit 30 */
3456 #define CAN_F7R1_FB31_Pos      (31U)
3457 #define CAN_F7R1_FB31_Msk      (0x1UL << CAN_F7R1_FB31_Pos)                     /*!< 0x80000000 */
3458 #define CAN_F7R1_FB31          CAN_F7R1_FB31_Msk                               /*!<Filter bit 31 */
3459 
3460 /*******************  Bit definition for CAN_F8R1 register  *******************/
3461 #define CAN_F8R1_FB0_Pos       (0U)
3462 #define CAN_F8R1_FB0_Msk       (0x1UL << CAN_F8R1_FB0_Pos)                      /*!< 0x00000001 */
3463 #define CAN_F8R1_FB0           CAN_F8R1_FB0_Msk                                /*!<Filter bit 0 */
3464 #define CAN_F8R1_FB1_Pos       (1U)
3465 #define CAN_F8R1_FB1_Msk       (0x1UL << CAN_F8R1_FB1_Pos)                      /*!< 0x00000002 */
3466 #define CAN_F8R1_FB1           CAN_F8R1_FB1_Msk                                /*!<Filter bit 1 */
3467 #define CAN_F8R1_FB2_Pos       (2U)
3468 #define CAN_F8R1_FB2_Msk       (0x1UL << CAN_F8R1_FB2_Pos)                      /*!< 0x00000004 */
3469 #define CAN_F8R1_FB2           CAN_F8R1_FB2_Msk                                /*!<Filter bit 2 */
3470 #define CAN_F8R1_FB3_Pos       (3U)
3471 #define CAN_F8R1_FB3_Msk       (0x1UL << CAN_F8R1_FB3_Pos)                      /*!< 0x00000008 */
3472 #define CAN_F8R1_FB3           CAN_F8R1_FB3_Msk                                /*!<Filter bit 3 */
3473 #define CAN_F8R1_FB4_Pos       (4U)
3474 #define CAN_F8R1_FB4_Msk       (0x1UL << CAN_F8R1_FB4_Pos)                      /*!< 0x00000010 */
3475 #define CAN_F8R1_FB4           CAN_F8R1_FB4_Msk                                /*!<Filter bit 4 */
3476 #define CAN_F8R1_FB5_Pos       (5U)
3477 #define CAN_F8R1_FB5_Msk       (0x1UL << CAN_F8R1_FB5_Pos)                      /*!< 0x00000020 */
3478 #define CAN_F8R1_FB5           CAN_F8R1_FB5_Msk                                /*!<Filter bit 5 */
3479 #define CAN_F8R1_FB6_Pos       (6U)
3480 #define CAN_F8R1_FB6_Msk       (0x1UL << CAN_F8R1_FB6_Pos)                      /*!< 0x00000040 */
3481 #define CAN_F8R1_FB6           CAN_F8R1_FB6_Msk                                /*!<Filter bit 6 */
3482 #define CAN_F8R1_FB7_Pos       (7U)
3483 #define CAN_F8R1_FB7_Msk       (0x1UL << CAN_F8R1_FB7_Pos)                      /*!< 0x00000080 */
3484 #define CAN_F8R1_FB7           CAN_F8R1_FB7_Msk                                /*!<Filter bit 7 */
3485 #define CAN_F8R1_FB8_Pos       (8U)
3486 #define CAN_F8R1_FB8_Msk       (0x1UL << CAN_F8R1_FB8_Pos)                      /*!< 0x00000100 */
3487 #define CAN_F8R1_FB8           CAN_F8R1_FB8_Msk                                /*!<Filter bit 8 */
3488 #define CAN_F8R1_FB9_Pos       (9U)
3489 #define CAN_F8R1_FB9_Msk       (0x1UL << CAN_F8R1_FB9_Pos)                      /*!< 0x00000200 */
3490 #define CAN_F8R1_FB9           CAN_F8R1_FB9_Msk                                /*!<Filter bit 9 */
3491 #define CAN_F8R1_FB10_Pos      (10U)
3492 #define CAN_F8R1_FB10_Msk      (0x1UL << CAN_F8R1_FB10_Pos)                     /*!< 0x00000400 */
3493 #define CAN_F8R1_FB10          CAN_F8R1_FB10_Msk                               /*!<Filter bit 10 */
3494 #define CAN_F8R1_FB11_Pos      (11U)
3495 #define CAN_F8R1_FB11_Msk      (0x1UL << CAN_F8R1_FB11_Pos)                     /*!< 0x00000800 */
3496 #define CAN_F8R1_FB11          CAN_F8R1_FB11_Msk                               /*!<Filter bit 11 */
3497 #define CAN_F8R1_FB12_Pos      (12U)
3498 #define CAN_F8R1_FB12_Msk      (0x1UL << CAN_F8R1_FB12_Pos)                     /*!< 0x00001000 */
3499 #define CAN_F8R1_FB12          CAN_F8R1_FB12_Msk                               /*!<Filter bit 12 */
3500 #define CAN_F8R1_FB13_Pos      (13U)
3501 #define CAN_F8R1_FB13_Msk      (0x1UL << CAN_F8R1_FB13_Pos)                     /*!< 0x00002000 */
3502 #define CAN_F8R1_FB13          CAN_F8R1_FB13_Msk                               /*!<Filter bit 13 */
3503 #define CAN_F8R1_FB14_Pos      (14U)
3504 #define CAN_F8R1_FB14_Msk      (0x1UL << CAN_F8R1_FB14_Pos)                     /*!< 0x00004000 */
3505 #define CAN_F8R1_FB14          CAN_F8R1_FB14_Msk                               /*!<Filter bit 14 */
3506 #define CAN_F8R1_FB15_Pos      (15U)
3507 #define CAN_F8R1_FB15_Msk      (0x1UL << CAN_F8R1_FB15_Pos)                     /*!< 0x00008000 */
3508 #define CAN_F8R1_FB15          CAN_F8R1_FB15_Msk                               /*!<Filter bit 15 */
3509 #define CAN_F8R1_FB16_Pos      (16U)
3510 #define CAN_F8R1_FB16_Msk      (0x1UL << CAN_F8R1_FB16_Pos)                     /*!< 0x00010000 */
3511 #define CAN_F8R1_FB16          CAN_F8R1_FB16_Msk                               /*!<Filter bit 16 */
3512 #define CAN_F8R1_FB17_Pos      (17U)
3513 #define CAN_F8R1_FB17_Msk      (0x1UL << CAN_F8R1_FB17_Pos)                     /*!< 0x00020000 */
3514 #define CAN_F8R1_FB17          CAN_F8R1_FB17_Msk                               /*!<Filter bit 17 */
3515 #define CAN_F8R1_FB18_Pos      (18U)
3516 #define CAN_F8R1_FB18_Msk      (0x1UL << CAN_F8R1_FB18_Pos)                     /*!< 0x00040000 */
3517 #define CAN_F8R1_FB18          CAN_F8R1_FB18_Msk                               /*!<Filter bit 18 */
3518 #define CAN_F8R1_FB19_Pos      (19U)
3519 #define CAN_F8R1_FB19_Msk      (0x1UL << CAN_F8R1_FB19_Pos)                     /*!< 0x00080000 */
3520 #define CAN_F8R1_FB19          CAN_F8R1_FB19_Msk                               /*!<Filter bit 19 */
3521 #define CAN_F8R1_FB20_Pos      (20U)
3522 #define CAN_F8R1_FB20_Msk      (0x1UL << CAN_F8R1_FB20_Pos)                     /*!< 0x00100000 */
3523 #define CAN_F8R1_FB20          CAN_F8R1_FB20_Msk                               /*!<Filter bit 20 */
3524 #define CAN_F8R1_FB21_Pos      (21U)
3525 #define CAN_F8R1_FB21_Msk      (0x1UL << CAN_F8R1_FB21_Pos)                     /*!< 0x00200000 */
3526 #define CAN_F8R1_FB21          CAN_F8R1_FB21_Msk                               /*!<Filter bit 21 */
3527 #define CAN_F8R1_FB22_Pos      (22U)
3528 #define CAN_F8R1_FB22_Msk      (0x1UL << CAN_F8R1_FB22_Pos)                     /*!< 0x00400000 */
3529 #define CAN_F8R1_FB22          CAN_F8R1_FB22_Msk                               /*!<Filter bit 22 */
3530 #define CAN_F8R1_FB23_Pos      (23U)
3531 #define CAN_F8R1_FB23_Msk      (0x1UL << CAN_F8R1_FB23_Pos)                     /*!< 0x00800000 */
3532 #define CAN_F8R1_FB23          CAN_F8R1_FB23_Msk                               /*!<Filter bit 23 */
3533 #define CAN_F8R1_FB24_Pos      (24U)
3534 #define CAN_F8R1_FB24_Msk      (0x1UL << CAN_F8R1_FB24_Pos)                     /*!< 0x01000000 */
3535 #define CAN_F8R1_FB24          CAN_F8R1_FB24_Msk                               /*!<Filter bit 24 */
3536 #define CAN_F8R1_FB25_Pos      (25U)
3537 #define CAN_F8R1_FB25_Msk      (0x1UL << CAN_F8R1_FB25_Pos)                     /*!< 0x02000000 */
3538 #define CAN_F8R1_FB25          CAN_F8R1_FB25_Msk                               /*!<Filter bit 25 */
3539 #define CAN_F8R1_FB26_Pos      (26U)
3540 #define CAN_F8R1_FB26_Msk      (0x1UL << CAN_F8R1_FB26_Pos)                     /*!< 0x04000000 */
3541 #define CAN_F8R1_FB26          CAN_F8R1_FB26_Msk                               /*!<Filter bit 26 */
3542 #define CAN_F8R1_FB27_Pos      (27U)
3543 #define CAN_F8R1_FB27_Msk      (0x1UL << CAN_F8R1_FB27_Pos)                     /*!< 0x08000000 */
3544 #define CAN_F8R1_FB27          CAN_F8R1_FB27_Msk                               /*!<Filter bit 27 */
3545 #define CAN_F8R1_FB28_Pos      (28U)
3546 #define CAN_F8R1_FB28_Msk      (0x1UL << CAN_F8R1_FB28_Pos)                     /*!< 0x10000000 */
3547 #define CAN_F8R1_FB28          CAN_F8R1_FB28_Msk                               /*!<Filter bit 28 */
3548 #define CAN_F8R1_FB29_Pos      (29U)
3549 #define CAN_F8R1_FB29_Msk      (0x1UL << CAN_F8R1_FB29_Pos)                     /*!< 0x20000000 */
3550 #define CAN_F8R1_FB29          CAN_F8R1_FB29_Msk                               /*!<Filter bit 29 */
3551 #define CAN_F8R1_FB30_Pos      (30U)
3552 #define CAN_F8R1_FB30_Msk      (0x1UL << CAN_F8R1_FB30_Pos)                     /*!< 0x40000000 */
3553 #define CAN_F8R1_FB30          CAN_F8R1_FB30_Msk                               /*!<Filter bit 30 */
3554 #define CAN_F8R1_FB31_Pos      (31U)
3555 #define CAN_F8R1_FB31_Msk      (0x1UL << CAN_F8R1_FB31_Pos)                     /*!< 0x80000000 */
3556 #define CAN_F8R1_FB31          CAN_F8R1_FB31_Msk                               /*!<Filter bit 31 */
3557 
3558 /*******************  Bit definition for CAN_F9R1 register  *******************/
3559 #define CAN_F9R1_FB0_Pos       (0U)
3560 #define CAN_F9R1_FB0_Msk       (0x1UL << CAN_F9R1_FB0_Pos)                      /*!< 0x00000001 */
3561 #define CAN_F9R1_FB0           CAN_F9R1_FB0_Msk                                /*!<Filter bit 0 */
3562 #define CAN_F9R1_FB1_Pos       (1U)
3563 #define CAN_F9R1_FB1_Msk       (0x1UL << CAN_F9R1_FB1_Pos)                      /*!< 0x00000002 */
3564 #define CAN_F9R1_FB1           CAN_F9R1_FB1_Msk                                /*!<Filter bit 1 */
3565 #define CAN_F9R1_FB2_Pos       (2U)
3566 #define CAN_F9R1_FB2_Msk       (0x1UL << CAN_F9R1_FB2_Pos)                      /*!< 0x00000004 */
3567 #define CAN_F9R1_FB2           CAN_F9R1_FB2_Msk                                /*!<Filter bit 2 */
3568 #define CAN_F9R1_FB3_Pos       (3U)
3569 #define CAN_F9R1_FB3_Msk       (0x1UL << CAN_F9R1_FB3_Pos)                      /*!< 0x00000008 */
3570 #define CAN_F9R1_FB3           CAN_F9R1_FB3_Msk                                /*!<Filter bit 3 */
3571 #define CAN_F9R1_FB4_Pos       (4U)
3572 #define CAN_F9R1_FB4_Msk       (0x1UL << CAN_F9R1_FB4_Pos)                      /*!< 0x00000010 */
3573 #define CAN_F9R1_FB4           CAN_F9R1_FB4_Msk                                /*!<Filter bit 4 */
3574 #define CAN_F9R1_FB5_Pos       (5U)
3575 #define CAN_F9R1_FB5_Msk       (0x1UL << CAN_F9R1_FB5_Pos)                      /*!< 0x00000020 */
3576 #define CAN_F9R1_FB5           CAN_F9R1_FB5_Msk                                /*!<Filter bit 5 */
3577 #define CAN_F9R1_FB6_Pos       (6U)
3578 #define CAN_F9R1_FB6_Msk       (0x1UL << CAN_F9R1_FB6_Pos)                      /*!< 0x00000040 */
3579 #define CAN_F9R1_FB6           CAN_F9R1_FB6_Msk                                /*!<Filter bit 6 */
3580 #define CAN_F9R1_FB7_Pos       (7U)
3581 #define CAN_F9R1_FB7_Msk       (0x1UL << CAN_F9R1_FB7_Pos)                      /*!< 0x00000080 */
3582 #define CAN_F9R1_FB7           CAN_F9R1_FB7_Msk                                /*!<Filter bit 7 */
3583 #define CAN_F9R1_FB8_Pos       (8U)
3584 #define CAN_F9R1_FB8_Msk       (0x1UL << CAN_F9R1_FB8_Pos)                      /*!< 0x00000100 */
3585 #define CAN_F9R1_FB8           CAN_F9R1_FB8_Msk                                /*!<Filter bit 8 */
3586 #define CAN_F9R1_FB9_Pos       (9U)
3587 #define CAN_F9R1_FB9_Msk       (0x1UL << CAN_F9R1_FB9_Pos)                      /*!< 0x00000200 */
3588 #define CAN_F9R1_FB9           CAN_F9R1_FB9_Msk                                /*!<Filter bit 9 */
3589 #define CAN_F9R1_FB10_Pos      (10U)
3590 #define CAN_F9R1_FB10_Msk      (0x1UL << CAN_F9R1_FB10_Pos)                     /*!< 0x00000400 */
3591 #define CAN_F9R1_FB10          CAN_F9R1_FB10_Msk                               /*!<Filter bit 10 */
3592 #define CAN_F9R1_FB11_Pos      (11U)
3593 #define CAN_F9R1_FB11_Msk      (0x1UL << CAN_F9R1_FB11_Pos)                     /*!< 0x00000800 */
3594 #define CAN_F9R1_FB11          CAN_F9R1_FB11_Msk                               /*!<Filter bit 11 */
3595 #define CAN_F9R1_FB12_Pos      (12U)
3596 #define CAN_F9R1_FB12_Msk      (0x1UL << CAN_F9R1_FB12_Pos)                     /*!< 0x00001000 */
3597 #define CAN_F9R1_FB12          CAN_F9R1_FB12_Msk                               /*!<Filter bit 12 */
3598 #define CAN_F9R1_FB13_Pos      (13U)
3599 #define CAN_F9R1_FB13_Msk      (0x1UL << CAN_F9R1_FB13_Pos)                     /*!< 0x00002000 */
3600 #define CAN_F9R1_FB13          CAN_F9R1_FB13_Msk                               /*!<Filter bit 13 */
3601 #define CAN_F9R1_FB14_Pos      (14U)
3602 #define CAN_F9R1_FB14_Msk      (0x1UL << CAN_F9R1_FB14_Pos)                     /*!< 0x00004000 */
3603 #define CAN_F9R1_FB14          CAN_F9R1_FB14_Msk                               /*!<Filter bit 14 */
3604 #define CAN_F9R1_FB15_Pos      (15U)
3605 #define CAN_F9R1_FB15_Msk      (0x1UL << CAN_F9R1_FB15_Pos)                     /*!< 0x00008000 */
3606 #define CAN_F9R1_FB15          CAN_F9R1_FB15_Msk                               /*!<Filter bit 15 */
3607 #define CAN_F9R1_FB16_Pos      (16U)
3608 #define CAN_F9R1_FB16_Msk      (0x1UL << CAN_F9R1_FB16_Pos)                     /*!< 0x00010000 */
3609 #define CAN_F9R1_FB16          CAN_F9R1_FB16_Msk                               /*!<Filter bit 16 */
3610 #define CAN_F9R1_FB17_Pos      (17U)
3611 #define CAN_F9R1_FB17_Msk      (0x1UL << CAN_F9R1_FB17_Pos)                     /*!< 0x00020000 */
3612 #define CAN_F9R1_FB17          CAN_F9R1_FB17_Msk                               /*!<Filter bit 17 */
3613 #define CAN_F9R1_FB18_Pos      (18U)
3614 #define CAN_F9R1_FB18_Msk      (0x1UL << CAN_F9R1_FB18_Pos)                     /*!< 0x00040000 */
3615 #define CAN_F9R1_FB18          CAN_F9R1_FB18_Msk                               /*!<Filter bit 18 */
3616 #define CAN_F9R1_FB19_Pos      (19U)
3617 #define CAN_F9R1_FB19_Msk      (0x1UL << CAN_F9R1_FB19_Pos)                     /*!< 0x00080000 */
3618 #define CAN_F9R1_FB19          CAN_F9R1_FB19_Msk                               /*!<Filter bit 19 */
3619 #define CAN_F9R1_FB20_Pos      (20U)
3620 #define CAN_F9R1_FB20_Msk      (0x1UL << CAN_F9R1_FB20_Pos)                     /*!< 0x00100000 */
3621 #define CAN_F9R1_FB20          CAN_F9R1_FB20_Msk                               /*!<Filter bit 20 */
3622 #define CAN_F9R1_FB21_Pos      (21U)
3623 #define CAN_F9R1_FB21_Msk      (0x1UL << CAN_F9R1_FB21_Pos)                     /*!< 0x00200000 */
3624 #define CAN_F9R1_FB21          CAN_F9R1_FB21_Msk                               /*!<Filter bit 21 */
3625 #define CAN_F9R1_FB22_Pos      (22U)
3626 #define CAN_F9R1_FB22_Msk      (0x1UL << CAN_F9R1_FB22_Pos)                     /*!< 0x00400000 */
3627 #define CAN_F9R1_FB22          CAN_F9R1_FB22_Msk                               /*!<Filter bit 22 */
3628 #define CAN_F9R1_FB23_Pos      (23U)
3629 #define CAN_F9R1_FB23_Msk      (0x1UL << CAN_F9R1_FB23_Pos)                     /*!< 0x00800000 */
3630 #define CAN_F9R1_FB23          CAN_F9R1_FB23_Msk                               /*!<Filter bit 23 */
3631 #define CAN_F9R1_FB24_Pos      (24U)
3632 #define CAN_F9R1_FB24_Msk      (0x1UL << CAN_F9R1_FB24_Pos)                     /*!< 0x01000000 */
3633 #define CAN_F9R1_FB24          CAN_F9R1_FB24_Msk                               /*!<Filter bit 24 */
3634 #define CAN_F9R1_FB25_Pos      (25U)
3635 #define CAN_F9R1_FB25_Msk      (0x1UL << CAN_F9R1_FB25_Pos)                     /*!< 0x02000000 */
3636 #define CAN_F9R1_FB25          CAN_F9R1_FB25_Msk                               /*!<Filter bit 25 */
3637 #define CAN_F9R1_FB26_Pos      (26U)
3638 #define CAN_F9R1_FB26_Msk      (0x1UL << CAN_F9R1_FB26_Pos)                     /*!< 0x04000000 */
3639 #define CAN_F9R1_FB26          CAN_F9R1_FB26_Msk                               /*!<Filter bit 26 */
3640 #define CAN_F9R1_FB27_Pos      (27U)
3641 #define CAN_F9R1_FB27_Msk      (0x1UL << CAN_F9R1_FB27_Pos)                     /*!< 0x08000000 */
3642 #define CAN_F9R1_FB27          CAN_F9R1_FB27_Msk                               /*!<Filter bit 27 */
3643 #define CAN_F9R1_FB28_Pos      (28U)
3644 #define CAN_F9R1_FB28_Msk      (0x1UL << CAN_F9R1_FB28_Pos)                     /*!< 0x10000000 */
3645 #define CAN_F9R1_FB28          CAN_F9R1_FB28_Msk                               /*!<Filter bit 28 */
3646 #define CAN_F9R1_FB29_Pos      (29U)
3647 #define CAN_F9R1_FB29_Msk      (0x1UL << CAN_F9R1_FB29_Pos)                     /*!< 0x20000000 */
3648 #define CAN_F9R1_FB29          CAN_F9R1_FB29_Msk                               /*!<Filter bit 29 */
3649 #define CAN_F9R1_FB30_Pos      (30U)
3650 #define CAN_F9R1_FB30_Msk      (0x1UL << CAN_F9R1_FB30_Pos)                     /*!< 0x40000000 */
3651 #define CAN_F9R1_FB30          CAN_F9R1_FB30_Msk                               /*!<Filter bit 30 */
3652 #define CAN_F9R1_FB31_Pos      (31U)
3653 #define CAN_F9R1_FB31_Msk      (0x1UL << CAN_F9R1_FB31_Pos)                     /*!< 0x80000000 */
3654 #define CAN_F9R1_FB31          CAN_F9R1_FB31_Msk                               /*!<Filter bit 31 */
3655 
3656 /*******************  Bit definition for CAN_F10R1 register  ******************/
3657 #define CAN_F10R1_FB0_Pos      (0U)
3658 #define CAN_F10R1_FB0_Msk      (0x1UL << CAN_F10R1_FB0_Pos)                     /*!< 0x00000001 */
3659 #define CAN_F10R1_FB0          CAN_F10R1_FB0_Msk                               /*!<Filter bit 0 */
3660 #define CAN_F10R1_FB1_Pos      (1U)
3661 #define CAN_F10R1_FB1_Msk      (0x1UL << CAN_F10R1_FB1_Pos)                     /*!< 0x00000002 */
3662 #define CAN_F10R1_FB1          CAN_F10R1_FB1_Msk                               /*!<Filter bit 1 */
3663 #define CAN_F10R1_FB2_Pos      (2U)
3664 #define CAN_F10R1_FB2_Msk      (0x1UL << CAN_F10R1_FB2_Pos)                     /*!< 0x00000004 */
3665 #define CAN_F10R1_FB2          CAN_F10R1_FB2_Msk                               /*!<Filter bit 2 */
3666 #define CAN_F10R1_FB3_Pos      (3U)
3667 #define CAN_F10R1_FB3_Msk      (0x1UL << CAN_F10R1_FB3_Pos)                     /*!< 0x00000008 */
3668 #define CAN_F10R1_FB3          CAN_F10R1_FB3_Msk                               /*!<Filter bit 3 */
3669 #define CAN_F10R1_FB4_Pos      (4U)
3670 #define CAN_F10R1_FB4_Msk      (0x1UL << CAN_F10R1_FB4_Pos)                     /*!< 0x00000010 */
3671 #define CAN_F10R1_FB4          CAN_F10R1_FB4_Msk                               /*!<Filter bit 4 */
3672 #define CAN_F10R1_FB5_Pos      (5U)
3673 #define CAN_F10R1_FB5_Msk      (0x1UL << CAN_F10R1_FB5_Pos)                     /*!< 0x00000020 */
3674 #define CAN_F10R1_FB5          CAN_F10R1_FB5_Msk                               /*!<Filter bit 5 */
3675 #define CAN_F10R1_FB6_Pos      (6U)
3676 #define CAN_F10R1_FB6_Msk      (0x1UL << CAN_F10R1_FB6_Pos)                     /*!< 0x00000040 */
3677 #define CAN_F10R1_FB6          CAN_F10R1_FB6_Msk                               /*!<Filter bit 6 */
3678 #define CAN_F10R1_FB7_Pos      (7U)
3679 #define CAN_F10R1_FB7_Msk      (0x1UL << CAN_F10R1_FB7_Pos)                     /*!< 0x00000080 */
3680 #define CAN_F10R1_FB7          CAN_F10R1_FB7_Msk                               /*!<Filter bit 7 */
3681 #define CAN_F10R1_FB8_Pos      (8U)
3682 #define CAN_F10R1_FB8_Msk      (0x1UL << CAN_F10R1_FB8_Pos)                     /*!< 0x00000100 */
3683 #define CAN_F10R1_FB8          CAN_F10R1_FB8_Msk                               /*!<Filter bit 8 */
3684 #define CAN_F10R1_FB9_Pos      (9U)
3685 #define CAN_F10R1_FB9_Msk      (0x1UL << CAN_F10R1_FB9_Pos)                     /*!< 0x00000200 */
3686 #define CAN_F10R1_FB9          CAN_F10R1_FB9_Msk                               /*!<Filter bit 9 */
3687 #define CAN_F10R1_FB10_Pos     (10U)
3688 #define CAN_F10R1_FB10_Msk     (0x1UL << CAN_F10R1_FB10_Pos)                    /*!< 0x00000400 */
3689 #define CAN_F10R1_FB10         CAN_F10R1_FB10_Msk                              /*!<Filter bit 10 */
3690 #define CAN_F10R1_FB11_Pos     (11U)
3691 #define CAN_F10R1_FB11_Msk     (0x1UL << CAN_F10R1_FB11_Pos)                    /*!< 0x00000800 */
3692 #define CAN_F10R1_FB11         CAN_F10R1_FB11_Msk                              /*!<Filter bit 11 */
3693 #define CAN_F10R1_FB12_Pos     (12U)
3694 #define CAN_F10R1_FB12_Msk     (0x1UL << CAN_F10R1_FB12_Pos)                    /*!< 0x00001000 */
3695 #define CAN_F10R1_FB12         CAN_F10R1_FB12_Msk                              /*!<Filter bit 12 */
3696 #define CAN_F10R1_FB13_Pos     (13U)
3697 #define CAN_F10R1_FB13_Msk     (0x1UL << CAN_F10R1_FB13_Pos)                    /*!< 0x00002000 */
3698 #define CAN_F10R1_FB13         CAN_F10R1_FB13_Msk                              /*!<Filter bit 13 */
3699 #define CAN_F10R1_FB14_Pos     (14U)
3700 #define CAN_F10R1_FB14_Msk     (0x1UL << CAN_F10R1_FB14_Pos)                    /*!< 0x00004000 */
3701 #define CAN_F10R1_FB14         CAN_F10R1_FB14_Msk                              /*!<Filter bit 14 */
3702 #define CAN_F10R1_FB15_Pos     (15U)
3703 #define CAN_F10R1_FB15_Msk     (0x1UL << CAN_F10R1_FB15_Pos)                    /*!< 0x00008000 */
3704 #define CAN_F10R1_FB15         CAN_F10R1_FB15_Msk                              /*!<Filter bit 15 */
3705 #define CAN_F10R1_FB16_Pos     (16U)
3706 #define CAN_F10R1_FB16_Msk     (0x1UL << CAN_F10R1_FB16_Pos)                    /*!< 0x00010000 */
3707 #define CAN_F10R1_FB16         CAN_F10R1_FB16_Msk                              /*!<Filter bit 16 */
3708 #define CAN_F10R1_FB17_Pos     (17U)
3709 #define CAN_F10R1_FB17_Msk     (0x1UL << CAN_F10R1_FB17_Pos)                    /*!< 0x00020000 */
3710 #define CAN_F10R1_FB17         CAN_F10R1_FB17_Msk                              /*!<Filter bit 17 */
3711 #define CAN_F10R1_FB18_Pos     (18U)
3712 #define CAN_F10R1_FB18_Msk     (0x1UL << CAN_F10R1_FB18_Pos)                    /*!< 0x00040000 */
3713 #define CAN_F10R1_FB18         CAN_F10R1_FB18_Msk                              /*!<Filter bit 18 */
3714 #define CAN_F10R1_FB19_Pos     (19U)
3715 #define CAN_F10R1_FB19_Msk     (0x1UL << CAN_F10R1_FB19_Pos)                    /*!< 0x00080000 */
3716 #define CAN_F10R1_FB19         CAN_F10R1_FB19_Msk                              /*!<Filter bit 19 */
3717 #define CAN_F10R1_FB20_Pos     (20U)
3718 #define CAN_F10R1_FB20_Msk     (0x1UL << CAN_F10R1_FB20_Pos)                    /*!< 0x00100000 */
3719 #define CAN_F10R1_FB20         CAN_F10R1_FB20_Msk                              /*!<Filter bit 20 */
3720 #define CAN_F10R1_FB21_Pos     (21U)
3721 #define CAN_F10R1_FB21_Msk     (0x1UL << CAN_F10R1_FB21_Pos)                    /*!< 0x00200000 */
3722 #define CAN_F10R1_FB21         CAN_F10R1_FB21_Msk                              /*!<Filter bit 21 */
3723 #define CAN_F10R1_FB22_Pos     (22U)
3724 #define CAN_F10R1_FB22_Msk     (0x1UL << CAN_F10R1_FB22_Pos)                    /*!< 0x00400000 */
3725 #define CAN_F10R1_FB22         CAN_F10R1_FB22_Msk                              /*!<Filter bit 22 */
3726 #define CAN_F10R1_FB23_Pos     (23U)
3727 #define CAN_F10R1_FB23_Msk     (0x1UL << CAN_F10R1_FB23_Pos)                    /*!< 0x00800000 */
3728 #define CAN_F10R1_FB23         CAN_F10R1_FB23_Msk                              /*!<Filter bit 23 */
3729 #define CAN_F10R1_FB24_Pos     (24U)
3730 #define CAN_F10R1_FB24_Msk     (0x1UL << CAN_F10R1_FB24_Pos)                    /*!< 0x01000000 */
3731 #define CAN_F10R1_FB24         CAN_F10R1_FB24_Msk                              /*!<Filter bit 24 */
3732 #define CAN_F10R1_FB25_Pos     (25U)
3733 #define CAN_F10R1_FB25_Msk     (0x1UL << CAN_F10R1_FB25_Pos)                    /*!< 0x02000000 */
3734 #define CAN_F10R1_FB25         CAN_F10R1_FB25_Msk                              /*!<Filter bit 25 */
3735 #define CAN_F10R1_FB26_Pos     (26U)
3736 #define CAN_F10R1_FB26_Msk     (0x1UL << CAN_F10R1_FB26_Pos)                    /*!< 0x04000000 */
3737 #define CAN_F10R1_FB26         CAN_F10R1_FB26_Msk                              /*!<Filter bit 26 */
3738 #define CAN_F10R1_FB27_Pos     (27U)
3739 #define CAN_F10R1_FB27_Msk     (0x1UL << CAN_F10R1_FB27_Pos)                    /*!< 0x08000000 */
3740 #define CAN_F10R1_FB27         CAN_F10R1_FB27_Msk                              /*!<Filter bit 27 */
3741 #define CAN_F10R1_FB28_Pos     (28U)
3742 #define CAN_F10R1_FB28_Msk     (0x1UL << CAN_F10R1_FB28_Pos)                    /*!< 0x10000000 */
3743 #define CAN_F10R1_FB28         CAN_F10R1_FB28_Msk                              /*!<Filter bit 28 */
3744 #define CAN_F10R1_FB29_Pos     (29U)
3745 #define CAN_F10R1_FB29_Msk     (0x1UL << CAN_F10R1_FB29_Pos)                    /*!< 0x20000000 */
3746 #define CAN_F10R1_FB29         CAN_F10R1_FB29_Msk                              /*!<Filter bit 29 */
3747 #define CAN_F10R1_FB30_Pos     (30U)
3748 #define CAN_F10R1_FB30_Msk     (0x1UL << CAN_F10R1_FB30_Pos)                    /*!< 0x40000000 */
3749 #define CAN_F10R1_FB30         CAN_F10R1_FB30_Msk                              /*!<Filter bit 30 */
3750 #define CAN_F10R1_FB31_Pos     (31U)
3751 #define CAN_F10R1_FB31_Msk     (0x1UL << CAN_F10R1_FB31_Pos)                    /*!< 0x80000000 */
3752 #define CAN_F10R1_FB31         CAN_F10R1_FB31_Msk                              /*!<Filter bit 31 */
3753 
3754 /*******************  Bit definition for CAN_F11R1 register  ******************/
3755 #define CAN_F11R1_FB0_Pos      (0U)
3756 #define CAN_F11R1_FB0_Msk      (0x1UL << CAN_F11R1_FB0_Pos)                     /*!< 0x00000001 */
3757 #define CAN_F11R1_FB0          CAN_F11R1_FB0_Msk                               /*!<Filter bit 0 */
3758 #define CAN_F11R1_FB1_Pos      (1U)
3759 #define CAN_F11R1_FB1_Msk      (0x1UL << CAN_F11R1_FB1_Pos)                     /*!< 0x00000002 */
3760 #define CAN_F11R1_FB1          CAN_F11R1_FB1_Msk                               /*!<Filter bit 1 */
3761 #define CAN_F11R1_FB2_Pos      (2U)
3762 #define CAN_F11R1_FB2_Msk      (0x1UL << CAN_F11R1_FB2_Pos)                     /*!< 0x00000004 */
3763 #define CAN_F11R1_FB2          CAN_F11R1_FB2_Msk                               /*!<Filter bit 2 */
3764 #define CAN_F11R1_FB3_Pos      (3U)
3765 #define CAN_F11R1_FB3_Msk      (0x1UL << CAN_F11R1_FB3_Pos)                     /*!< 0x00000008 */
3766 #define CAN_F11R1_FB3          CAN_F11R1_FB3_Msk                               /*!<Filter bit 3 */
3767 #define CAN_F11R1_FB4_Pos      (4U)
3768 #define CAN_F11R1_FB4_Msk      (0x1UL << CAN_F11R1_FB4_Pos)                     /*!< 0x00000010 */
3769 #define CAN_F11R1_FB4          CAN_F11R1_FB4_Msk                               /*!<Filter bit 4 */
3770 #define CAN_F11R1_FB5_Pos      (5U)
3771 #define CAN_F11R1_FB5_Msk      (0x1UL << CAN_F11R1_FB5_Pos)                     /*!< 0x00000020 */
3772 #define CAN_F11R1_FB5          CAN_F11R1_FB5_Msk                               /*!<Filter bit 5 */
3773 #define CAN_F11R1_FB6_Pos      (6U)
3774 #define CAN_F11R1_FB6_Msk      (0x1UL << CAN_F11R1_FB6_Pos)                     /*!< 0x00000040 */
3775 #define CAN_F11R1_FB6          CAN_F11R1_FB6_Msk                               /*!<Filter bit 6 */
3776 #define CAN_F11R1_FB7_Pos      (7U)
3777 #define CAN_F11R1_FB7_Msk      (0x1UL << CAN_F11R1_FB7_Pos)                     /*!< 0x00000080 */
3778 #define CAN_F11R1_FB7          CAN_F11R1_FB7_Msk                               /*!<Filter bit 7 */
3779 #define CAN_F11R1_FB8_Pos      (8U)
3780 #define CAN_F11R1_FB8_Msk      (0x1UL << CAN_F11R1_FB8_Pos)                     /*!< 0x00000100 */
3781 #define CAN_F11R1_FB8          CAN_F11R1_FB8_Msk                               /*!<Filter bit 8 */
3782 #define CAN_F11R1_FB9_Pos      (9U)
3783 #define CAN_F11R1_FB9_Msk      (0x1UL << CAN_F11R1_FB9_Pos)                     /*!< 0x00000200 */
3784 #define CAN_F11R1_FB9          CAN_F11R1_FB9_Msk                               /*!<Filter bit 9 */
3785 #define CAN_F11R1_FB10_Pos     (10U)
3786 #define CAN_F11R1_FB10_Msk     (0x1UL << CAN_F11R1_FB10_Pos)                    /*!< 0x00000400 */
3787 #define CAN_F11R1_FB10         CAN_F11R1_FB10_Msk                              /*!<Filter bit 10 */
3788 #define CAN_F11R1_FB11_Pos     (11U)
3789 #define CAN_F11R1_FB11_Msk     (0x1UL << CAN_F11R1_FB11_Pos)                    /*!< 0x00000800 */
3790 #define CAN_F11R1_FB11         CAN_F11R1_FB11_Msk                              /*!<Filter bit 11 */
3791 #define CAN_F11R1_FB12_Pos     (12U)
3792 #define CAN_F11R1_FB12_Msk     (0x1UL << CAN_F11R1_FB12_Pos)                    /*!< 0x00001000 */
3793 #define CAN_F11R1_FB12         CAN_F11R1_FB12_Msk                              /*!<Filter bit 12 */
3794 #define CAN_F11R1_FB13_Pos     (13U)
3795 #define CAN_F11R1_FB13_Msk     (0x1UL << CAN_F11R1_FB13_Pos)                    /*!< 0x00002000 */
3796 #define CAN_F11R1_FB13         CAN_F11R1_FB13_Msk                              /*!<Filter bit 13 */
3797 #define CAN_F11R1_FB14_Pos     (14U)
3798 #define CAN_F11R1_FB14_Msk     (0x1UL << CAN_F11R1_FB14_Pos)                    /*!< 0x00004000 */
3799 #define CAN_F11R1_FB14         CAN_F11R1_FB14_Msk                              /*!<Filter bit 14 */
3800 #define CAN_F11R1_FB15_Pos     (15U)
3801 #define CAN_F11R1_FB15_Msk     (0x1UL << CAN_F11R1_FB15_Pos)                    /*!< 0x00008000 */
3802 #define CAN_F11R1_FB15         CAN_F11R1_FB15_Msk                              /*!<Filter bit 15 */
3803 #define CAN_F11R1_FB16_Pos     (16U)
3804 #define CAN_F11R1_FB16_Msk     (0x1UL << CAN_F11R1_FB16_Pos)                    /*!< 0x00010000 */
3805 #define CAN_F11R1_FB16         CAN_F11R1_FB16_Msk                              /*!<Filter bit 16 */
3806 #define CAN_F11R1_FB17_Pos     (17U)
3807 #define CAN_F11R1_FB17_Msk     (0x1UL << CAN_F11R1_FB17_Pos)                    /*!< 0x00020000 */
3808 #define CAN_F11R1_FB17         CAN_F11R1_FB17_Msk                              /*!<Filter bit 17 */
3809 #define CAN_F11R1_FB18_Pos     (18U)
3810 #define CAN_F11R1_FB18_Msk     (0x1UL << CAN_F11R1_FB18_Pos)                    /*!< 0x00040000 */
3811 #define CAN_F11R1_FB18         CAN_F11R1_FB18_Msk                              /*!<Filter bit 18 */
3812 #define CAN_F11R1_FB19_Pos     (19U)
3813 #define CAN_F11R1_FB19_Msk     (0x1UL << CAN_F11R1_FB19_Pos)                    /*!< 0x00080000 */
3814 #define CAN_F11R1_FB19         CAN_F11R1_FB19_Msk                              /*!<Filter bit 19 */
3815 #define CAN_F11R1_FB20_Pos     (20U)
3816 #define CAN_F11R1_FB20_Msk     (0x1UL << CAN_F11R1_FB20_Pos)                    /*!< 0x00100000 */
3817 #define CAN_F11R1_FB20         CAN_F11R1_FB20_Msk                              /*!<Filter bit 20 */
3818 #define CAN_F11R1_FB21_Pos     (21U)
3819 #define CAN_F11R1_FB21_Msk     (0x1UL << CAN_F11R1_FB21_Pos)                    /*!< 0x00200000 */
3820 #define CAN_F11R1_FB21         CAN_F11R1_FB21_Msk                              /*!<Filter bit 21 */
3821 #define CAN_F11R1_FB22_Pos     (22U)
3822 #define CAN_F11R1_FB22_Msk     (0x1UL << CAN_F11R1_FB22_Pos)                    /*!< 0x00400000 */
3823 #define CAN_F11R1_FB22         CAN_F11R1_FB22_Msk                              /*!<Filter bit 22 */
3824 #define CAN_F11R1_FB23_Pos     (23U)
3825 #define CAN_F11R1_FB23_Msk     (0x1UL << CAN_F11R1_FB23_Pos)                    /*!< 0x00800000 */
3826 #define CAN_F11R1_FB23         CAN_F11R1_FB23_Msk                              /*!<Filter bit 23 */
3827 #define CAN_F11R1_FB24_Pos     (24U)
3828 #define CAN_F11R1_FB24_Msk     (0x1UL << CAN_F11R1_FB24_Pos)                    /*!< 0x01000000 */
3829 #define CAN_F11R1_FB24         CAN_F11R1_FB24_Msk                              /*!<Filter bit 24 */
3830 #define CAN_F11R1_FB25_Pos     (25U)
3831 #define CAN_F11R1_FB25_Msk     (0x1UL << CAN_F11R1_FB25_Pos)                    /*!< 0x02000000 */
3832 #define CAN_F11R1_FB25         CAN_F11R1_FB25_Msk                              /*!<Filter bit 25 */
3833 #define CAN_F11R1_FB26_Pos     (26U)
3834 #define CAN_F11R1_FB26_Msk     (0x1UL << CAN_F11R1_FB26_Pos)                    /*!< 0x04000000 */
3835 #define CAN_F11R1_FB26         CAN_F11R1_FB26_Msk                              /*!<Filter bit 26 */
3836 #define CAN_F11R1_FB27_Pos     (27U)
3837 #define CAN_F11R1_FB27_Msk     (0x1UL << CAN_F11R1_FB27_Pos)                    /*!< 0x08000000 */
3838 #define CAN_F11R1_FB27         CAN_F11R1_FB27_Msk                              /*!<Filter bit 27 */
3839 #define CAN_F11R1_FB28_Pos     (28U)
3840 #define CAN_F11R1_FB28_Msk     (0x1UL << CAN_F11R1_FB28_Pos)                    /*!< 0x10000000 */
3841 #define CAN_F11R1_FB28         CAN_F11R1_FB28_Msk                              /*!<Filter bit 28 */
3842 #define CAN_F11R1_FB29_Pos     (29U)
3843 #define CAN_F11R1_FB29_Msk     (0x1UL << CAN_F11R1_FB29_Pos)                    /*!< 0x20000000 */
3844 #define CAN_F11R1_FB29         CAN_F11R1_FB29_Msk                              /*!<Filter bit 29 */
3845 #define CAN_F11R1_FB30_Pos     (30U)
3846 #define CAN_F11R1_FB30_Msk     (0x1UL << CAN_F11R1_FB30_Pos)                    /*!< 0x40000000 */
3847 #define CAN_F11R1_FB30         CAN_F11R1_FB30_Msk                              /*!<Filter bit 30 */
3848 #define CAN_F11R1_FB31_Pos     (31U)
3849 #define CAN_F11R1_FB31_Msk     (0x1UL << CAN_F11R1_FB31_Pos)                    /*!< 0x80000000 */
3850 #define CAN_F11R1_FB31         CAN_F11R1_FB31_Msk                              /*!<Filter bit 31 */
3851 
3852 /*******************  Bit definition for CAN_F12R1 register  ******************/
3853 #define CAN_F12R1_FB0_Pos      (0U)
3854 #define CAN_F12R1_FB0_Msk      (0x1UL << CAN_F12R1_FB0_Pos)                     /*!< 0x00000001 */
3855 #define CAN_F12R1_FB0          CAN_F12R1_FB0_Msk                               /*!<Filter bit 0 */
3856 #define CAN_F12R1_FB1_Pos      (1U)
3857 #define CAN_F12R1_FB1_Msk      (0x1UL << CAN_F12R1_FB1_Pos)                     /*!< 0x00000002 */
3858 #define CAN_F12R1_FB1          CAN_F12R1_FB1_Msk                               /*!<Filter bit 1 */
3859 #define CAN_F12R1_FB2_Pos      (2U)
3860 #define CAN_F12R1_FB2_Msk      (0x1UL << CAN_F12R1_FB2_Pos)                     /*!< 0x00000004 */
3861 #define CAN_F12R1_FB2          CAN_F12R1_FB2_Msk                               /*!<Filter bit 2 */
3862 #define CAN_F12R1_FB3_Pos      (3U)
3863 #define CAN_F12R1_FB3_Msk      (0x1UL << CAN_F12R1_FB3_Pos)                     /*!< 0x00000008 */
3864 #define CAN_F12R1_FB3          CAN_F12R1_FB3_Msk                               /*!<Filter bit 3 */
3865 #define CAN_F12R1_FB4_Pos      (4U)
3866 #define CAN_F12R1_FB4_Msk      (0x1UL << CAN_F12R1_FB4_Pos)                     /*!< 0x00000010 */
3867 #define CAN_F12R1_FB4          CAN_F12R1_FB4_Msk                               /*!<Filter bit 4 */
3868 #define CAN_F12R1_FB5_Pos      (5U)
3869 #define CAN_F12R1_FB5_Msk      (0x1UL << CAN_F12R1_FB5_Pos)                     /*!< 0x00000020 */
3870 #define CAN_F12R1_FB5          CAN_F12R1_FB5_Msk                               /*!<Filter bit 5 */
3871 #define CAN_F12R1_FB6_Pos      (6U)
3872 #define CAN_F12R1_FB6_Msk      (0x1UL << CAN_F12R1_FB6_Pos)                     /*!< 0x00000040 */
3873 #define CAN_F12R1_FB6          CAN_F12R1_FB6_Msk                               /*!<Filter bit 6 */
3874 #define CAN_F12R1_FB7_Pos      (7U)
3875 #define CAN_F12R1_FB7_Msk      (0x1UL << CAN_F12R1_FB7_Pos)                     /*!< 0x00000080 */
3876 #define CAN_F12R1_FB7          CAN_F12R1_FB7_Msk                               /*!<Filter bit 7 */
3877 #define CAN_F12R1_FB8_Pos      (8U)
3878 #define CAN_F12R1_FB8_Msk      (0x1UL << CAN_F12R1_FB8_Pos)                     /*!< 0x00000100 */
3879 #define CAN_F12R1_FB8          CAN_F12R1_FB8_Msk                               /*!<Filter bit 8 */
3880 #define CAN_F12R1_FB9_Pos      (9U)
3881 #define CAN_F12R1_FB9_Msk      (0x1UL << CAN_F12R1_FB9_Pos)                     /*!< 0x00000200 */
3882 #define CAN_F12R1_FB9          CAN_F12R1_FB9_Msk                               /*!<Filter bit 9 */
3883 #define CAN_F12R1_FB10_Pos     (10U)
3884 #define CAN_F12R1_FB10_Msk     (0x1UL << CAN_F12R1_FB10_Pos)                    /*!< 0x00000400 */
3885 #define CAN_F12R1_FB10         CAN_F12R1_FB10_Msk                              /*!<Filter bit 10 */
3886 #define CAN_F12R1_FB11_Pos     (11U)
3887 #define CAN_F12R1_FB11_Msk     (0x1UL << CAN_F12R1_FB11_Pos)                    /*!< 0x00000800 */
3888 #define CAN_F12R1_FB11         CAN_F12R1_FB11_Msk                              /*!<Filter bit 11 */
3889 #define CAN_F12R1_FB12_Pos     (12U)
3890 #define CAN_F12R1_FB12_Msk     (0x1UL << CAN_F12R1_FB12_Pos)                    /*!< 0x00001000 */
3891 #define CAN_F12R1_FB12         CAN_F12R1_FB12_Msk                              /*!<Filter bit 12 */
3892 #define CAN_F12R1_FB13_Pos     (13U)
3893 #define CAN_F12R1_FB13_Msk     (0x1UL << CAN_F12R1_FB13_Pos)                    /*!< 0x00002000 */
3894 #define CAN_F12R1_FB13         CAN_F12R1_FB13_Msk                              /*!<Filter bit 13 */
3895 #define CAN_F12R1_FB14_Pos     (14U)
3896 #define CAN_F12R1_FB14_Msk     (0x1UL << CAN_F12R1_FB14_Pos)                    /*!< 0x00004000 */
3897 #define CAN_F12R1_FB14         CAN_F12R1_FB14_Msk                              /*!<Filter bit 14 */
3898 #define CAN_F12R1_FB15_Pos     (15U)
3899 #define CAN_F12R1_FB15_Msk     (0x1UL << CAN_F12R1_FB15_Pos)                    /*!< 0x00008000 */
3900 #define CAN_F12R1_FB15         CAN_F12R1_FB15_Msk                              /*!<Filter bit 15 */
3901 #define CAN_F12R1_FB16_Pos     (16U)
3902 #define CAN_F12R1_FB16_Msk     (0x1UL << CAN_F12R1_FB16_Pos)                    /*!< 0x00010000 */
3903 #define CAN_F12R1_FB16         CAN_F12R1_FB16_Msk                              /*!<Filter bit 16 */
3904 #define CAN_F12R1_FB17_Pos     (17U)
3905 #define CAN_F12R1_FB17_Msk     (0x1UL << CAN_F12R1_FB17_Pos)                    /*!< 0x00020000 */
3906 #define CAN_F12R1_FB17         CAN_F12R1_FB17_Msk                              /*!<Filter bit 17 */
3907 #define CAN_F12R1_FB18_Pos     (18U)
3908 #define CAN_F12R1_FB18_Msk     (0x1UL << CAN_F12R1_FB18_Pos)                    /*!< 0x00040000 */
3909 #define CAN_F12R1_FB18         CAN_F12R1_FB18_Msk                              /*!<Filter bit 18 */
3910 #define CAN_F12R1_FB19_Pos     (19U)
3911 #define CAN_F12R1_FB19_Msk     (0x1UL << CAN_F12R1_FB19_Pos)                    /*!< 0x00080000 */
3912 #define CAN_F12R1_FB19         CAN_F12R1_FB19_Msk                              /*!<Filter bit 19 */
3913 #define CAN_F12R1_FB20_Pos     (20U)
3914 #define CAN_F12R1_FB20_Msk     (0x1UL << CAN_F12R1_FB20_Pos)                    /*!< 0x00100000 */
3915 #define CAN_F12R1_FB20         CAN_F12R1_FB20_Msk                              /*!<Filter bit 20 */
3916 #define CAN_F12R1_FB21_Pos     (21U)
3917 #define CAN_F12R1_FB21_Msk     (0x1UL << CAN_F12R1_FB21_Pos)                    /*!< 0x00200000 */
3918 #define CAN_F12R1_FB21         CAN_F12R1_FB21_Msk                              /*!<Filter bit 21 */
3919 #define CAN_F12R1_FB22_Pos     (22U)
3920 #define CAN_F12R1_FB22_Msk     (0x1UL << CAN_F12R1_FB22_Pos)                    /*!< 0x00400000 */
3921 #define CAN_F12R1_FB22         CAN_F12R1_FB22_Msk                              /*!<Filter bit 22 */
3922 #define CAN_F12R1_FB23_Pos     (23U)
3923 #define CAN_F12R1_FB23_Msk     (0x1UL << CAN_F12R1_FB23_Pos)                    /*!< 0x00800000 */
3924 #define CAN_F12R1_FB23         CAN_F12R1_FB23_Msk                              /*!<Filter bit 23 */
3925 #define CAN_F12R1_FB24_Pos     (24U)
3926 #define CAN_F12R1_FB24_Msk     (0x1UL << CAN_F12R1_FB24_Pos)                    /*!< 0x01000000 */
3927 #define CAN_F12R1_FB24         CAN_F12R1_FB24_Msk                              /*!<Filter bit 24 */
3928 #define CAN_F12R1_FB25_Pos     (25U)
3929 #define CAN_F12R1_FB25_Msk     (0x1UL << CAN_F12R1_FB25_Pos)                    /*!< 0x02000000 */
3930 #define CAN_F12R1_FB25         CAN_F12R1_FB25_Msk                              /*!<Filter bit 25 */
3931 #define CAN_F12R1_FB26_Pos     (26U)
3932 #define CAN_F12R1_FB26_Msk     (0x1UL << CAN_F12R1_FB26_Pos)                    /*!< 0x04000000 */
3933 #define CAN_F12R1_FB26         CAN_F12R1_FB26_Msk                              /*!<Filter bit 26 */
3934 #define CAN_F12R1_FB27_Pos     (27U)
3935 #define CAN_F12R1_FB27_Msk     (0x1UL << CAN_F12R1_FB27_Pos)                    /*!< 0x08000000 */
3936 #define CAN_F12R1_FB27         CAN_F12R1_FB27_Msk                              /*!<Filter bit 27 */
3937 #define CAN_F12R1_FB28_Pos     (28U)
3938 #define CAN_F12R1_FB28_Msk     (0x1UL << CAN_F12R1_FB28_Pos)                    /*!< 0x10000000 */
3939 #define CAN_F12R1_FB28         CAN_F12R1_FB28_Msk                              /*!<Filter bit 28 */
3940 #define CAN_F12R1_FB29_Pos     (29U)
3941 #define CAN_F12R1_FB29_Msk     (0x1UL << CAN_F12R1_FB29_Pos)                    /*!< 0x20000000 */
3942 #define CAN_F12R1_FB29         CAN_F12R1_FB29_Msk                              /*!<Filter bit 29 */
3943 #define CAN_F12R1_FB30_Pos     (30U)
3944 #define CAN_F12R1_FB30_Msk     (0x1UL << CAN_F12R1_FB30_Pos)                    /*!< 0x40000000 */
3945 #define CAN_F12R1_FB30         CAN_F12R1_FB30_Msk                              /*!<Filter bit 30 */
3946 #define CAN_F12R1_FB31_Pos     (31U)
3947 #define CAN_F12R1_FB31_Msk     (0x1UL << CAN_F12R1_FB31_Pos)                    /*!< 0x80000000 */
3948 #define CAN_F12R1_FB31         CAN_F12R1_FB31_Msk                              /*!<Filter bit 31 */
3949 
3950 /*******************  Bit definition for CAN_F13R1 register  ******************/
3951 #define CAN_F13R1_FB0_Pos      (0U)
3952 #define CAN_F13R1_FB0_Msk      (0x1UL << CAN_F13R1_FB0_Pos)                     /*!< 0x00000001 */
3953 #define CAN_F13R1_FB0          CAN_F13R1_FB0_Msk                               /*!<Filter bit 0 */
3954 #define CAN_F13R1_FB1_Pos      (1U)
3955 #define CAN_F13R1_FB1_Msk      (0x1UL << CAN_F13R1_FB1_Pos)                     /*!< 0x00000002 */
3956 #define CAN_F13R1_FB1          CAN_F13R1_FB1_Msk                               /*!<Filter bit 1 */
3957 #define CAN_F13R1_FB2_Pos      (2U)
3958 #define CAN_F13R1_FB2_Msk      (0x1UL << CAN_F13R1_FB2_Pos)                     /*!< 0x00000004 */
3959 #define CAN_F13R1_FB2          CAN_F13R1_FB2_Msk                               /*!<Filter bit 2 */
3960 #define CAN_F13R1_FB3_Pos      (3U)
3961 #define CAN_F13R1_FB3_Msk      (0x1UL << CAN_F13R1_FB3_Pos)                     /*!< 0x00000008 */
3962 #define CAN_F13R1_FB3          CAN_F13R1_FB3_Msk                               /*!<Filter bit 3 */
3963 #define CAN_F13R1_FB4_Pos      (4U)
3964 #define CAN_F13R1_FB4_Msk      (0x1UL << CAN_F13R1_FB4_Pos)                     /*!< 0x00000010 */
3965 #define CAN_F13R1_FB4          CAN_F13R1_FB4_Msk                               /*!<Filter bit 4 */
3966 #define CAN_F13R1_FB5_Pos      (5U)
3967 #define CAN_F13R1_FB5_Msk      (0x1UL << CAN_F13R1_FB5_Pos)                     /*!< 0x00000020 */
3968 #define CAN_F13R1_FB5          CAN_F13R1_FB5_Msk                               /*!<Filter bit 5 */
3969 #define CAN_F13R1_FB6_Pos      (6U)
3970 #define CAN_F13R1_FB6_Msk      (0x1UL << CAN_F13R1_FB6_Pos)                     /*!< 0x00000040 */
3971 #define CAN_F13R1_FB6          CAN_F13R1_FB6_Msk                               /*!<Filter bit 6 */
3972 #define CAN_F13R1_FB7_Pos      (7U)
3973 #define CAN_F13R1_FB7_Msk      (0x1UL << CAN_F13R1_FB7_Pos)                     /*!< 0x00000080 */
3974 #define CAN_F13R1_FB7          CAN_F13R1_FB7_Msk                               /*!<Filter bit 7 */
3975 #define CAN_F13R1_FB8_Pos      (8U)
3976 #define CAN_F13R1_FB8_Msk      (0x1UL << CAN_F13R1_FB8_Pos)                     /*!< 0x00000100 */
3977 #define CAN_F13R1_FB8          CAN_F13R1_FB8_Msk                               /*!<Filter bit 8 */
3978 #define CAN_F13R1_FB9_Pos      (9U)
3979 #define CAN_F13R1_FB9_Msk      (0x1UL << CAN_F13R1_FB9_Pos)                     /*!< 0x00000200 */
3980 #define CAN_F13R1_FB9          CAN_F13R1_FB9_Msk                               /*!<Filter bit 9 */
3981 #define CAN_F13R1_FB10_Pos     (10U)
3982 #define CAN_F13R1_FB10_Msk     (0x1UL << CAN_F13R1_FB10_Pos)                    /*!< 0x00000400 */
3983 #define CAN_F13R1_FB10         CAN_F13R1_FB10_Msk                              /*!<Filter bit 10 */
3984 #define CAN_F13R1_FB11_Pos     (11U)
3985 #define CAN_F13R1_FB11_Msk     (0x1UL << CAN_F13R1_FB11_Pos)                    /*!< 0x00000800 */
3986 #define CAN_F13R1_FB11         CAN_F13R1_FB11_Msk                              /*!<Filter bit 11 */
3987 #define CAN_F13R1_FB12_Pos     (12U)
3988 #define CAN_F13R1_FB12_Msk     (0x1UL << CAN_F13R1_FB12_Pos)                    /*!< 0x00001000 */
3989 #define CAN_F13R1_FB12         CAN_F13R1_FB12_Msk                              /*!<Filter bit 12 */
3990 #define CAN_F13R1_FB13_Pos     (13U)
3991 #define CAN_F13R1_FB13_Msk     (0x1UL << CAN_F13R1_FB13_Pos)                    /*!< 0x00002000 */
3992 #define CAN_F13R1_FB13         CAN_F13R1_FB13_Msk                              /*!<Filter bit 13 */
3993 #define CAN_F13R1_FB14_Pos     (14U)
3994 #define CAN_F13R1_FB14_Msk     (0x1UL << CAN_F13R1_FB14_Pos)                    /*!< 0x00004000 */
3995 #define CAN_F13R1_FB14         CAN_F13R1_FB14_Msk                              /*!<Filter bit 14 */
3996 #define CAN_F13R1_FB15_Pos     (15U)
3997 #define CAN_F13R1_FB15_Msk     (0x1UL << CAN_F13R1_FB15_Pos)                    /*!< 0x00008000 */
3998 #define CAN_F13R1_FB15         CAN_F13R1_FB15_Msk                              /*!<Filter bit 15 */
3999 #define CAN_F13R1_FB16_Pos     (16U)
4000 #define CAN_F13R1_FB16_Msk     (0x1UL << CAN_F13R1_FB16_Pos)                    /*!< 0x00010000 */
4001 #define CAN_F13R1_FB16         CAN_F13R1_FB16_Msk                              /*!<Filter bit 16 */
4002 #define CAN_F13R1_FB17_Pos     (17U)
4003 #define CAN_F13R1_FB17_Msk     (0x1UL << CAN_F13R1_FB17_Pos)                    /*!< 0x00020000 */
4004 #define CAN_F13R1_FB17         CAN_F13R1_FB17_Msk                              /*!<Filter bit 17 */
4005 #define CAN_F13R1_FB18_Pos     (18U)
4006 #define CAN_F13R1_FB18_Msk     (0x1UL << CAN_F13R1_FB18_Pos)                    /*!< 0x00040000 */
4007 #define CAN_F13R1_FB18         CAN_F13R1_FB18_Msk                              /*!<Filter bit 18 */
4008 #define CAN_F13R1_FB19_Pos     (19U)
4009 #define CAN_F13R1_FB19_Msk     (0x1UL << CAN_F13R1_FB19_Pos)                    /*!< 0x00080000 */
4010 #define CAN_F13R1_FB19         CAN_F13R1_FB19_Msk                              /*!<Filter bit 19 */
4011 #define CAN_F13R1_FB20_Pos     (20U)
4012 #define CAN_F13R1_FB20_Msk     (0x1UL << CAN_F13R1_FB20_Pos)                    /*!< 0x00100000 */
4013 #define CAN_F13R1_FB20         CAN_F13R1_FB20_Msk                              /*!<Filter bit 20 */
4014 #define CAN_F13R1_FB21_Pos     (21U)
4015 #define CAN_F13R1_FB21_Msk     (0x1UL << CAN_F13R1_FB21_Pos)                    /*!< 0x00200000 */
4016 #define CAN_F13R1_FB21         CAN_F13R1_FB21_Msk                              /*!<Filter bit 21 */
4017 #define CAN_F13R1_FB22_Pos     (22U)
4018 #define CAN_F13R1_FB22_Msk     (0x1UL << CAN_F13R1_FB22_Pos)                    /*!< 0x00400000 */
4019 #define CAN_F13R1_FB22         CAN_F13R1_FB22_Msk                              /*!<Filter bit 22 */
4020 #define CAN_F13R1_FB23_Pos     (23U)
4021 #define CAN_F13R1_FB23_Msk     (0x1UL << CAN_F13R1_FB23_Pos)                    /*!< 0x00800000 */
4022 #define CAN_F13R1_FB23         CAN_F13R1_FB23_Msk                              /*!<Filter bit 23 */
4023 #define CAN_F13R1_FB24_Pos     (24U)
4024 #define CAN_F13R1_FB24_Msk     (0x1UL << CAN_F13R1_FB24_Pos)                    /*!< 0x01000000 */
4025 #define CAN_F13R1_FB24         CAN_F13R1_FB24_Msk                              /*!<Filter bit 24 */
4026 #define CAN_F13R1_FB25_Pos     (25U)
4027 #define CAN_F13R1_FB25_Msk     (0x1UL << CAN_F13R1_FB25_Pos)                    /*!< 0x02000000 */
4028 #define CAN_F13R1_FB25         CAN_F13R1_FB25_Msk                              /*!<Filter bit 25 */
4029 #define CAN_F13R1_FB26_Pos     (26U)
4030 #define CAN_F13R1_FB26_Msk     (0x1UL << CAN_F13R1_FB26_Pos)                    /*!< 0x04000000 */
4031 #define CAN_F13R1_FB26         CAN_F13R1_FB26_Msk                              /*!<Filter bit 26 */
4032 #define CAN_F13R1_FB27_Pos     (27U)
4033 #define CAN_F13R1_FB27_Msk     (0x1UL << CAN_F13R1_FB27_Pos)                    /*!< 0x08000000 */
4034 #define CAN_F13R1_FB27         CAN_F13R1_FB27_Msk                              /*!<Filter bit 27 */
4035 #define CAN_F13R1_FB28_Pos     (28U)
4036 #define CAN_F13R1_FB28_Msk     (0x1UL << CAN_F13R1_FB28_Pos)                    /*!< 0x10000000 */
4037 #define CAN_F13R1_FB28         CAN_F13R1_FB28_Msk                              /*!<Filter bit 28 */
4038 #define CAN_F13R1_FB29_Pos     (29U)
4039 #define CAN_F13R1_FB29_Msk     (0x1UL << CAN_F13R1_FB29_Pos)                    /*!< 0x20000000 */
4040 #define CAN_F13R1_FB29         CAN_F13R1_FB29_Msk                              /*!<Filter bit 29 */
4041 #define CAN_F13R1_FB30_Pos     (30U)
4042 #define CAN_F13R1_FB30_Msk     (0x1UL << CAN_F13R1_FB30_Pos)                    /*!< 0x40000000 */
4043 #define CAN_F13R1_FB30         CAN_F13R1_FB30_Msk                              /*!<Filter bit 30 */
4044 #define CAN_F13R1_FB31_Pos     (31U)
4045 #define CAN_F13R1_FB31_Msk     (0x1UL << CAN_F13R1_FB31_Pos)                    /*!< 0x80000000 */
4046 #define CAN_F13R1_FB31         CAN_F13R1_FB31_Msk                              /*!<Filter bit 31 */
4047 
4048 /*******************  Bit definition for CAN_F0R2 register  *******************/
4049 #define CAN_F0R2_FB0_Pos       (0U)
4050 #define CAN_F0R2_FB0_Msk       (0x1UL << CAN_F0R2_FB0_Pos)                      /*!< 0x00000001 */
4051 #define CAN_F0R2_FB0           CAN_F0R2_FB0_Msk                                /*!<Filter bit 0 */
4052 #define CAN_F0R2_FB1_Pos       (1U)
4053 #define CAN_F0R2_FB1_Msk       (0x1UL << CAN_F0R2_FB1_Pos)                      /*!< 0x00000002 */
4054 #define CAN_F0R2_FB1           CAN_F0R2_FB1_Msk                                /*!<Filter bit 1 */
4055 #define CAN_F0R2_FB2_Pos       (2U)
4056 #define CAN_F0R2_FB2_Msk       (0x1UL << CAN_F0R2_FB2_Pos)                      /*!< 0x00000004 */
4057 #define CAN_F0R2_FB2           CAN_F0R2_FB2_Msk                                /*!<Filter bit 2 */
4058 #define CAN_F0R2_FB3_Pos       (3U)
4059 #define CAN_F0R2_FB3_Msk       (0x1UL << CAN_F0R2_FB3_Pos)                      /*!< 0x00000008 */
4060 #define CAN_F0R2_FB3           CAN_F0R2_FB3_Msk                                /*!<Filter bit 3 */
4061 #define CAN_F0R2_FB4_Pos       (4U)
4062 #define CAN_F0R2_FB4_Msk       (0x1UL << CAN_F0R2_FB4_Pos)                      /*!< 0x00000010 */
4063 #define CAN_F0R2_FB4           CAN_F0R2_FB4_Msk                                /*!<Filter bit 4 */
4064 #define CAN_F0R2_FB5_Pos       (5U)
4065 #define CAN_F0R2_FB5_Msk       (0x1UL << CAN_F0R2_FB5_Pos)                      /*!< 0x00000020 */
4066 #define CAN_F0R2_FB5           CAN_F0R2_FB5_Msk                                /*!<Filter bit 5 */
4067 #define CAN_F0R2_FB6_Pos       (6U)
4068 #define CAN_F0R2_FB6_Msk       (0x1UL << CAN_F0R2_FB6_Pos)                      /*!< 0x00000040 */
4069 #define CAN_F0R2_FB6           CAN_F0R2_FB6_Msk                                /*!<Filter bit 6 */
4070 #define CAN_F0R2_FB7_Pos       (7U)
4071 #define CAN_F0R2_FB7_Msk       (0x1UL << CAN_F0R2_FB7_Pos)                      /*!< 0x00000080 */
4072 #define CAN_F0R2_FB7           CAN_F0R2_FB7_Msk                                /*!<Filter bit 7 */
4073 #define CAN_F0R2_FB8_Pos       (8U)
4074 #define CAN_F0R2_FB8_Msk       (0x1UL << CAN_F0R2_FB8_Pos)                      /*!< 0x00000100 */
4075 #define CAN_F0R2_FB8           CAN_F0R2_FB8_Msk                                /*!<Filter bit 8 */
4076 #define CAN_F0R2_FB9_Pos       (9U)
4077 #define CAN_F0R2_FB9_Msk       (0x1UL << CAN_F0R2_FB9_Pos)                      /*!< 0x00000200 */
4078 #define CAN_F0R2_FB9           CAN_F0R2_FB9_Msk                                /*!<Filter bit 9 */
4079 #define CAN_F0R2_FB10_Pos      (10U)
4080 #define CAN_F0R2_FB10_Msk      (0x1UL << CAN_F0R2_FB10_Pos)                     /*!< 0x00000400 */
4081 #define CAN_F0R2_FB10          CAN_F0R2_FB10_Msk                               /*!<Filter bit 10 */
4082 #define CAN_F0R2_FB11_Pos      (11U)
4083 #define CAN_F0R2_FB11_Msk      (0x1UL << CAN_F0R2_FB11_Pos)                     /*!< 0x00000800 */
4084 #define CAN_F0R2_FB11          CAN_F0R2_FB11_Msk                               /*!<Filter bit 11 */
4085 #define CAN_F0R2_FB12_Pos      (12U)
4086 #define CAN_F0R2_FB12_Msk      (0x1UL << CAN_F0R2_FB12_Pos)                     /*!< 0x00001000 */
4087 #define CAN_F0R2_FB12          CAN_F0R2_FB12_Msk                               /*!<Filter bit 12 */
4088 #define CAN_F0R2_FB13_Pos      (13U)
4089 #define CAN_F0R2_FB13_Msk      (0x1UL << CAN_F0R2_FB13_Pos)                     /*!< 0x00002000 */
4090 #define CAN_F0R2_FB13          CAN_F0R2_FB13_Msk                               /*!<Filter bit 13 */
4091 #define CAN_F0R2_FB14_Pos      (14U)
4092 #define CAN_F0R2_FB14_Msk      (0x1UL << CAN_F0R2_FB14_Pos)                     /*!< 0x00004000 */
4093 #define CAN_F0R2_FB14          CAN_F0R2_FB14_Msk                               /*!<Filter bit 14 */
4094 #define CAN_F0R2_FB15_Pos      (15U)
4095 #define CAN_F0R2_FB15_Msk      (0x1UL << CAN_F0R2_FB15_Pos)                     /*!< 0x00008000 */
4096 #define CAN_F0R2_FB15          CAN_F0R2_FB15_Msk                               /*!<Filter bit 15 */
4097 #define CAN_F0R2_FB16_Pos      (16U)
4098 #define CAN_F0R2_FB16_Msk      (0x1UL << CAN_F0R2_FB16_Pos)                     /*!< 0x00010000 */
4099 #define CAN_F0R2_FB16          CAN_F0R2_FB16_Msk                               /*!<Filter bit 16 */
4100 #define CAN_F0R2_FB17_Pos      (17U)
4101 #define CAN_F0R2_FB17_Msk      (0x1UL << CAN_F0R2_FB17_Pos)                     /*!< 0x00020000 */
4102 #define CAN_F0R2_FB17          CAN_F0R2_FB17_Msk                               /*!<Filter bit 17 */
4103 #define CAN_F0R2_FB18_Pos      (18U)
4104 #define CAN_F0R2_FB18_Msk      (0x1UL << CAN_F0R2_FB18_Pos)                     /*!< 0x00040000 */
4105 #define CAN_F0R2_FB18          CAN_F0R2_FB18_Msk                               /*!<Filter bit 18 */
4106 #define CAN_F0R2_FB19_Pos      (19U)
4107 #define CAN_F0R2_FB19_Msk      (0x1UL << CAN_F0R2_FB19_Pos)                     /*!< 0x00080000 */
4108 #define CAN_F0R2_FB19          CAN_F0R2_FB19_Msk                               /*!<Filter bit 19 */
4109 #define CAN_F0R2_FB20_Pos      (20U)
4110 #define CAN_F0R2_FB20_Msk      (0x1UL << CAN_F0R2_FB20_Pos)                     /*!< 0x00100000 */
4111 #define CAN_F0R2_FB20          CAN_F0R2_FB20_Msk                               /*!<Filter bit 20 */
4112 #define CAN_F0R2_FB21_Pos      (21U)
4113 #define CAN_F0R2_FB21_Msk      (0x1UL << CAN_F0R2_FB21_Pos)                     /*!< 0x00200000 */
4114 #define CAN_F0R2_FB21          CAN_F0R2_FB21_Msk                               /*!<Filter bit 21 */
4115 #define CAN_F0R2_FB22_Pos      (22U)
4116 #define CAN_F0R2_FB22_Msk      (0x1UL << CAN_F0R2_FB22_Pos)                     /*!< 0x00400000 */
4117 #define CAN_F0R2_FB22          CAN_F0R2_FB22_Msk                               /*!<Filter bit 22 */
4118 #define CAN_F0R2_FB23_Pos      (23U)
4119 #define CAN_F0R2_FB23_Msk      (0x1UL << CAN_F0R2_FB23_Pos)                     /*!< 0x00800000 */
4120 #define CAN_F0R2_FB23          CAN_F0R2_FB23_Msk                               /*!<Filter bit 23 */
4121 #define CAN_F0R2_FB24_Pos      (24U)
4122 #define CAN_F0R2_FB24_Msk      (0x1UL << CAN_F0R2_FB24_Pos)                     /*!< 0x01000000 */
4123 #define CAN_F0R2_FB24          CAN_F0R2_FB24_Msk                               /*!<Filter bit 24 */
4124 #define CAN_F0R2_FB25_Pos      (25U)
4125 #define CAN_F0R2_FB25_Msk      (0x1UL << CAN_F0R2_FB25_Pos)                     /*!< 0x02000000 */
4126 #define CAN_F0R2_FB25          CAN_F0R2_FB25_Msk                               /*!<Filter bit 25 */
4127 #define CAN_F0R2_FB26_Pos      (26U)
4128 #define CAN_F0R2_FB26_Msk      (0x1UL << CAN_F0R2_FB26_Pos)                     /*!< 0x04000000 */
4129 #define CAN_F0R2_FB26          CAN_F0R2_FB26_Msk                               /*!<Filter bit 26 */
4130 #define CAN_F0R2_FB27_Pos      (27U)
4131 #define CAN_F0R2_FB27_Msk      (0x1UL << CAN_F0R2_FB27_Pos)                     /*!< 0x08000000 */
4132 #define CAN_F0R2_FB27          CAN_F0R2_FB27_Msk                               /*!<Filter bit 27 */
4133 #define CAN_F0R2_FB28_Pos      (28U)
4134 #define CAN_F0R2_FB28_Msk      (0x1UL << CAN_F0R2_FB28_Pos)                     /*!< 0x10000000 */
4135 #define CAN_F0R2_FB28          CAN_F0R2_FB28_Msk                               /*!<Filter bit 28 */
4136 #define CAN_F0R2_FB29_Pos      (29U)
4137 #define CAN_F0R2_FB29_Msk      (0x1UL << CAN_F0R2_FB29_Pos)                     /*!< 0x20000000 */
4138 #define CAN_F0R2_FB29          CAN_F0R2_FB29_Msk                               /*!<Filter bit 29 */
4139 #define CAN_F0R2_FB30_Pos      (30U)
4140 #define CAN_F0R2_FB30_Msk      (0x1UL << CAN_F0R2_FB30_Pos)                     /*!< 0x40000000 */
4141 #define CAN_F0R2_FB30          CAN_F0R2_FB30_Msk                               /*!<Filter bit 30 */
4142 #define CAN_F0R2_FB31_Pos      (31U)
4143 #define CAN_F0R2_FB31_Msk      (0x1UL << CAN_F0R2_FB31_Pos)                     /*!< 0x80000000 */
4144 #define CAN_F0R2_FB31          CAN_F0R2_FB31_Msk                               /*!<Filter bit 31 */
4145 
4146 /*******************  Bit definition for CAN_F1R2 register  *******************/
4147 #define CAN_F1R2_FB0_Pos       (0U)
4148 #define CAN_F1R2_FB0_Msk       (0x1UL << CAN_F1R2_FB0_Pos)                      /*!< 0x00000001 */
4149 #define CAN_F1R2_FB0           CAN_F1R2_FB0_Msk                                /*!<Filter bit 0 */
4150 #define CAN_F1R2_FB1_Pos       (1U)
4151 #define CAN_F1R2_FB1_Msk       (0x1UL << CAN_F1R2_FB1_Pos)                      /*!< 0x00000002 */
4152 #define CAN_F1R2_FB1           CAN_F1R2_FB1_Msk                                /*!<Filter bit 1 */
4153 #define CAN_F1R2_FB2_Pos       (2U)
4154 #define CAN_F1R2_FB2_Msk       (0x1UL << CAN_F1R2_FB2_Pos)                      /*!< 0x00000004 */
4155 #define CAN_F1R2_FB2           CAN_F1R2_FB2_Msk                                /*!<Filter bit 2 */
4156 #define CAN_F1R2_FB3_Pos       (3U)
4157 #define CAN_F1R2_FB3_Msk       (0x1UL << CAN_F1R2_FB3_Pos)                      /*!< 0x00000008 */
4158 #define CAN_F1R2_FB3           CAN_F1R2_FB3_Msk                                /*!<Filter bit 3 */
4159 #define CAN_F1R2_FB4_Pos       (4U)
4160 #define CAN_F1R2_FB4_Msk       (0x1UL << CAN_F1R2_FB4_Pos)                      /*!< 0x00000010 */
4161 #define CAN_F1R2_FB4           CAN_F1R2_FB4_Msk                                /*!<Filter bit 4 */
4162 #define CAN_F1R2_FB5_Pos       (5U)
4163 #define CAN_F1R2_FB5_Msk       (0x1UL << CAN_F1R2_FB5_Pos)                      /*!< 0x00000020 */
4164 #define CAN_F1R2_FB5           CAN_F1R2_FB5_Msk                                /*!<Filter bit 5 */
4165 #define CAN_F1R2_FB6_Pos       (6U)
4166 #define CAN_F1R2_FB6_Msk       (0x1UL << CAN_F1R2_FB6_Pos)                      /*!< 0x00000040 */
4167 #define CAN_F1R2_FB6           CAN_F1R2_FB6_Msk                                /*!<Filter bit 6 */
4168 #define CAN_F1R2_FB7_Pos       (7U)
4169 #define CAN_F1R2_FB7_Msk       (0x1UL << CAN_F1R2_FB7_Pos)                      /*!< 0x00000080 */
4170 #define CAN_F1R2_FB7           CAN_F1R2_FB7_Msk                                /*!<Filter bit 7 */
4171 #define CAN_F1R2_FB8_Pos       (8U)
4172 #define CAN_F1R2_FB8_Msk       (0x1UL << CAN_F1R2_FB8_Pos)                      /*!< 0x00000100 */
4173 #define CAN_F1R2_FB8           CAN_F1R2_FB8_Msk                                /*!<Filter bit 8 */
4174 #define CAN_F1R2_FB9_Pos       (9U)
4175 #define CAN_F1R2_FB9_Msk       (0x1UL << CAN_F1R2_FB9_Pos)                      /*!< 0x00000200 */
4176 #define CAN_F1R2_FB9           CAN_F1R2_FB9_Msk                                /*!<Filter bit 9 */
4177 #define CAN_F1R2_FB10_Pos      (10U)
4178 #define CAN_F1R2_FB10_Msk      (0x1UL << CAN_F1R2_FB10_Pos)                     /*!< 0x00000400 */
4179 #define CAN_F1R2_FB10          CAN_F1R2_FB10_Msk                               /*!<Filter bit 10 */
4180 #define CAN_F1R2_FB11_Pos      (11U)
4181 #define CAN_F1R2_FB11_Msk      (0x1UL << CAN_F1R2_FB11_Pos)                     /*!< 0x00000800 */
4182 #define CAN_F1R2_FB11          CAN_F1R2_FB11_Msk                               /*!<Filter bit 11 */
4183 #define CAN_F1R2_FB12_Pos      (12U)
4184 #define CAN_F1R2_FB12_Msk      (0x1UL << CAN_F1R2_FB12_Pos)                     /*!< 0x00001000 */
4185 #define CAN_F1R2_FB12          CAN_F1R2_FB12_Msk                               /*!<Filter bit 12 */
4186 #define CAN_F1R2_FB13_Pos      (13U)
4187 #define CAN_F1R2_FB13_Msk      (0x1UL << CAN_F1R2_FB13_Pos)                     /*!< 0x00002000 */
4188 #define CAN_F1R2_FB13          CAN_F1R2_FB13_Msk                               /*!<Filter bit 13 */
4189 #define CAN_F1R2_FB14_Pos      (14U)
4190 #define CAN_F1R2_FB14_Msk      (0x1UL << CAN_F1R2_FB14_Pos)                     /*!< 0x00004000 */
4191 #define CAN_F1R2_FB14          CAN_F1R2_FB14_Msk                               /*!<Filter bit 14 */
4192 #define CAN_F1R2_FB15_Pos      (15U)
4193 #define CAN_F1R2_FB15_Msk      (0x1UL << CAN_F1R2_FB15_Pos)                     /*!< 0x00008000 */
4194 #define CAN_F1R2_FB15          CAN_F1R2_FB15_Msk                               /*!<Filter bit 15 */
4195 #define CAN_F1R2_FB16_Pos      (16U)
4196 #define CAN_F1R2_FB16_Msk      (0x1UL << CAN_F1R2_FB16_Pos)                     /*!< 0x00010000 */
4197 #define CAN_F1R2_FB16          CAN_F1R2_FB16_Msk                               /*!<Filter bit 16 */
4198 #define CAN_F1R2_FB17_Pos      (17U)
4199 #define CAN_F1R2_FB17_Msk      (0x1UL << CAN_F1R2_FB17_Pos)                     /*!< 0x00020000 */
4200 #define CAN_F1R2_FB17          CAN_F1R2_FB17_Msk                               /*!<Filter bit 17 */
4201 #define CAN_F1R2_FB18_Pos      (18U)
4202 #define CAN_F1R2_FB18_Msk      (0x1UL << CAN_F1R2_FB18_Pos)                     /*!< 0x00040000 */
4203 #define CAN_F1R2_FB18          CAN_F1R2_FB18_Msk                               /*!<Filter bit 18 */
4204 #define CAN_F1R2_FB19_Pos      (19U)
4205 #define CAN_F1R2_FB19_Msk      (0x1UL << CAN_F1R2_FB19_Pos)                     /*!< 0x00080000 */
4206 #define CAN_F1R2_FB19          CAN_F1R2_FB19_Msk                               /*!<Filter bit 19 */
4207 #define CAN_F1R2_FB20_Pos      (20U)
4208 #define CAN_F1R2_FB20_Msk      (0x1UL << CAN_F1R2_FB20_Pos)                     /*!< 0x00100000 */
4209 #define CAN_F1R2_FB20          CAN_F1R2_FB20_Msk                               /*!<Filter bit 20 */
4210 #define CAN_F1R2_FB21_Pos      (21U)
4211 #define CAN_F1R2_FB21_Msk      (0x1UL << CAN_F1R2_FB21_Pos)                     /*!< 0x00200000 */
4212 #define CAN_F1R2_FB21          CAN_F1R2_FB21_Msk                               /*!<Filter bit 21 */
4213 #define CAN_F1R2_FB22_Pos      (22U)
4214 #define CAN_F1R2_FB22_Msk      (0x1UL << CAN_F1R2_FB22_Pos)                     /*!< 0x00400000 */
4215 #define CAN_F1R2_FB22          CAN_F1R2_FB22_Msk                               /*!<Filter bit 22 */
4216 #define CAN_F1R2_FB23_Pos      (23U)
4217 #define CAN_F1R2_FB23_Msk      (0x1UL << CAN_F1R2_FB23_Pos)                     /*!< 0x00800000 */
4218 #define CAN_F1R2_FB23          CAN_F1R2_FB23_Msk                               /*!<Filter bit 23 */
4219 #define CAN_F1R2_FB24_Pos      (24U)
4220 #define CAN_F1R2_FB24_Msk      (0x1UL << CAN_F1R2_FB24_Pos)                     /*!< 0x01000000 */
4221 #define CAN_F1R2_FB24          CAN_F1R2_FB24_Msk                               /*!<Filter bit 24 */
4222 #define CAN_F1R2_FB25_Pos      (25U)
4223 #define CAN_F1R2_FB25_Msk      (0x1UL << CAN_F1R2_FB25_Pos)                     /*!< 0x02000000 */
4224 #define CAN_F1R2_FB25          CAN_F1R2_FB25_Msk                               /*!<Filter bit 25 */
4225 #define CAN_F1R2_FB26_Pos      (26U)
4226 #define CAN_F1R2_FB26_Msk      (0x1UL << CAN_F1R2_FB26_Pos)                     /*!< 0x04000000 */
4227 #define CAN_F1R2_FB26          CAN_F1R2_FB26_Msk                               /*!<Filter bit 26 */
4228 #define CAN_F1R2_FB27_Pos      (27U)
4229 #define CAN_F1R2_FB27_Msk      (0x1UL << CAN_F1R2_FB27_Pos)                     /*!< 0x08000000 */
4230 #define CAN_F1R2_FB27          CAN_F1R2_FB27_Msk                               /*!<Filter bit 27 */
4231 #define CAN_F1R2_FB28_Pos      (28U)
4232 #define CAN_F1R2_FB28_Msk      (0x1UL << CAN_F1R2_FB28_Pos)                     /*!< 0x10000000 */
4233 #define CAN_F1R2_FB28          CAN_F1R2_FB28_Msk                               /*!<Filter bit 28 */
4234 #define CAN_F1R2_FB29_Pos      (29U)
4235 #define CAN_F1R2_FB29_Msk      (0x1UL << CAN_F1R2_FB29_Pos)                     /*!< 0x20000000 */
4236 #define CAN_F1R2_FB29          CAN_F1R2_FB29_Msk                               /*!<Filter bit 29 */
4237 #define CAN_F1R2_FB30_Pos      (30U)
4238 #define CAN_F1R2_FB30_Msk      (0x1UL << CAN_F1R2_FB30_Pos)                     /*!< 0x40000000 */
4239 #define CAN_F1R2_FB30          CAN_F1R2_FB30_Msk                               /*!<Filter bit 30 */
4240 #define CAN_F1R2_FB31_Pos      (31U)
4241 #define CAN_F1R2_FB31_Msk      (0x1UL << CAN_F1R2_FB31_Pos)                     /*!< 0x80000000 */
4242 #define CAN_F1R2_FB31          CAN_F1R2_FB31_Msk                               /*!<Filter bit 31 */
4243 
4244 /*******************  Bit definition for CAN_F2R2 register  *******************/
4245 #define CAN_F2R2_FB0_Pos       (0U)
4246 #define CAN_F2R2_FB0_Msk       (0x1UL << CAN_F2R2_FB0_Pos)                      /*!< 0x00000001 */
4247 #define CAN_F2R2_FB0           CAN_F2R2_FB0_Msk                                /*!<Filter bit 0 */
4248 #define CAN_F2R2_FB1_Pos       (1U)
4249 #define CAN_F2R2_FB1_Msk       (0x1UL << CAN_F2R2_FB1_Pos)                      /*!< 0x00000002 */
4250 #define CAN_F2R2_FB1           CAN_F2R2_FB1_Msk                                /*!<Filter bit 1 */
4251 #define CAN_F2R2_FB2_Pos       (2U)
4252 #define CAN_F2R2_FB2_Msk       (0x1UL << CAN_F2R2_FB2_Pos)                      /*!< 0x00000004 */
4253 #define CAN_F2R2_FB2           CAN_F2R2_FB2_Msk                                /*!<Filter bit 2 */
4254 #define CAN_F2R2_FB3_Pos       (3U)
4255 #define CAN_F2R2_FB3_Msk       (0x1UL << CAN_F2R2_FB3_Pos)                      /*!< 0x00000008 */
4256 #define CAN_F2R2_FB3           CAN_F2R2_FB3_Msk                                /*!<Filter bit 3 */
4257 #define CAN_F2R2_FB4_Pos       (4U)
4258 #define CAN_F2R2_FB4_Msk       (0x1UL << CAN_F2R2_FB4_Pos)                      /*!< 0x00000010 */
4259 #define CAN_F2R2_FB4           CAN_F2R2_FB4_Msk                                /*!<Filter bit 4 */
4260 #define CAN_F2R2_FB5_Pos       (5U)
4261 #define CAN_F2R2_FB5_Msk       (0x1UL << CAN_F2R2_FB5_Pos)                      /*!< 0x00000020 */
4262 #define CAN_F2R2_FB5           CAN_F2R2_FB5_Msk                                /*!<Filter bit 5 */
4263 #define CAN_F2R2_FB6_Pos       (6U)
4264 #define CAN_F2R2_FB6_Msk       (0x1UL << CAN_F2R2_FB6_Pos)                      /*!< 0x00000040 */
4265 #define CAN_F2R2_FB6           CAN_F2R2_FB6_Msk                                /*!<Filter bit 6 */
4266 #define CAN_F2R2_FB7_Pos       (7U)
4267 #define CAN_F2R2_FB7_Msk       (0x1UL << CAN_F2R2_FB7_Pos)                      /*!< 0x00000080 */
4268 #define CAN_F2R2_FB7           CAN_F2R2_FB7_Msk                                /*!<Filter bit 7 */
4269 #define CAN_F2R2_FB8_Pos       (8U)
4270 #define CAN_F2R2_FB8_Msk       (0x1UL << CAN_F2R2_FB8_Pos)                      /*!< 0x00000100 */
4271 #define CAN_F2R2_FB8           CAN_F2R2_FB8_Msk                                /*!<Filter bit 8 */
4272 #define CAN_F2R2_FB9_Pos       (9U)
4273 #define CAN_F2R2_FB9_Msk       (0x1UL << CAN_F2R2_FB9_Pos)                      /*!< 0x00000200 */
4274 #define CAN_F2R2_FB9           CAN_F2R2_FB9_Msk                                /*!<Filter bit 9 */
4275 #define CAN_F2R2_FB10_Pos      (10U)
4276 #define CAN_F2R2_FB10_Msk      (0x1UL << CAN_F2R2_FB10_Pos)                     /*!< 0x00000400 */
4277 #define CAN_F2R2_FB10          CAN_F2R2_FB10_Msk                               /*!<Filter bit 10 */
4278 #define CAN_F2R2_FB11_Pos      (11U)
4279 #define CAN_F2R2_FB11_Msk      (0x1UL << CAN_F2R2_FB11_Pos)                     /*!< 0x00000800 */
4280 #define CAN_F2R2_FB11          CAN_F2R2_FB11_Msk                               /*!<Filter bit 11 */
4281 #define CAN_F2R2_FB12_Pos      (12U)
4282 #define CAN_F2R2_FB12_Msk      (0x1UL << CAN_F2R2_FB12_Pos)                     /*!< 0x00001000 */
4283 #define CAN_F2R2_FB12          CAN_F2R2_FB12_Msk                               /*!<Filter bit 12 */
4284 #define CAN_F2R2_FB13_Pos      (13U)
4285 #define CAN_F2R2_FB13_Msk      (0x1UL << CAN_F2R2_FB13_Pos)                     /*!< 0x00002000 */
4286 #define CAN_F2R2_FB13          CAN_F2R2_FB13_Msk                               /*!<Filter bit 13 */
4287 #define CAN_F2R2_FB14_Pos      (14U)
4288 #define CAN_F2R2_FB14_Msk      (0x1UL << CAN_F2R2_FB14_Pos)                     /*!< 0x00004000 */
4289 #define CAN_F2R2_FB14          CAN_F2R2_FB14_Msk                               /*!<Filter bit 14 */
4290 #define CAN_F2R2_FB15_Pos      (15U)
4291 #define CAN_F2R2_FB15_Msk      (0x1UL << CAN_F2R2_FB15_Pos)                     /*!< 0x00008000 */
4292 #define CAN_F2R2_FB15          CAN_F2R2_FB15_Msk                               /*!<Filter bit 15 */
4293 #define CAN_F2R2_FB16_Pos      (16U)
4294 #define CAN_F2R2_FB16_Msk      (0x1UL << CAN_F2R2_FB16_Pos)                     /*!< 0x00010000 */
4295 #define CAN_F2R2_FB16          CAN_F2R2_FB16_Msk                               /*!<Filter bit 16 */
4296 #define CAN_F2R2_FB17_Pos      (17U)
4297 #define CAN_F2R2_FB17_Msk      (0x1UL << CAN_F2R2_FB17_Pos)                     /*!< 0x00020000 */
4298 #define CAN_F2R2_FB17          CAN_F2R2_FB17_Msk                               /*!<Filter bit 17 */
4299 #define CAN_F2R2_FB18_Pos      (18U)
4300 #define CAN_F2R2_FB18_Msk      (0x1UL << CAN_F2R2_FB18_Pos)                     /*!< 0x00040000 */
4301 #define CAN_F2R2_FB18          CAN_F2R2_FB18_Msk                               /*!<Filter bit 18 */
4302 #define CAN_F2R2_FB19_Pos      (19U)
4303 #define CAN_F2R2_FB19_Msk      (0x1UL << CAN_F2R2_FB19_Pos)                     /*!< 0x00080000 */
4304 #define CAN_F2R2_FB19          CAN_F2R2_FB19_Msk                               /*!<Filter bit 19 */
4305 #define CAN_F2R2_FB20_Pos      (20U)
4306 #define CAN_F2R2_FB20_Msk      (0x1UL << CAN_F2R2_FB20_Pos)                     /*!< 0x00100000 */
4307 #define CAN_F2R2_FB20          CAN_F2R2_FB20_Msk                               /*!<Filter bit 20 */
4308 #define CAN_F2R2_FB21_Pos      (21U)
4309 #define CAN_F2R2_FB21_Msk      (0x1UL << CAN_F2R2_FB21_Pos)                     /*!< 0x00200000 */
4310 #define CAN_F2R2_FB21          CAN_F2R2_FB21_Msk                               /*!<Filter bit 21 */
4311 #define CAN_F2R2_FB22_Pos      (22U)
4312 #define CAN_F2R2_FB22_Msk      (0x1UL << CAN_F2R2_FB22_Pos)                     /*!< 0x00400000 */
4313 #define CAN_F2R2_FB22          CAN_F2R2_FB22_Msk                               /*!<Filter bit 22 */
4314 #define CAN_F2R2_FB23_Pos      (23U)
4315 #define CAN_F2R2_FB23_Msk      (0x1UL << CAN_F2R2_FB23_Pos)                     /*!< 0x00800000 */
4316 #define CAN_F2R2_FB23          CAN_F2R2_FB23_Msk                               /*!<Filter bit 23 */
4317 #define CAN_F2R2_FB24_Pos      (24U)
4318 #define CAN_F2R2_FB24_Msk      (0x1UL << CAN_F2R2_FB24_Pos)                     /*!< 0x01000000 */
4319 #define CAN_F2R2_FB24          CAN_F2R2_FB24_Msk                               /*!<Filter bit 24 */
4320 #define CAN_F2R2_FB25_Pos      (25U)
4321 #define CAN_F2R2_FB25_Msk      (0x1UL << CAN_F2R2_FB25_Pos)                     /*!< 0x02000000 */
4322 #define CAN_F2R2_FB25          CAN_F2R2_FB25_Msk                               /*!<Filter bit 25 */
4323 #define CAN_F2R2_FB26_Pos      (26U)
4324 #define CAN_F2R2_FB26_Msk      (0x1UL << CAN_F2R2_FB26_Pos)                     /*!< 0x04000000 */
4325 #define CAN_F2R2_FB26          CAN_F2R2_FB26_Msk                               /*!<Filter bit 26 */
4326 #define CAN_F2R2_FB27_Pos      (27U)
4327 #define CAN_F2R2_FB27_Msk      (0x1UL << CAN_F2R2_FB27_Pos)                     /*!< 0x08000000 */
4328 #define CAN_F2R2_FB27          CAN_F2R2_FB27_Msk                               /*!<Filter bit 27 */
4329 #define CAN_F2R2_FB28_Pos      (28U)
4330 #define CAN_F2R2_FB28_Msk      (0x1UL << CAN_F2R2_FB28_Pos)                     /*!< 0x10000000 */
4331 #define CAN_F2R2_FB28          CAN_F2R2_FB28_Msk                               /*!<Filter bit 28 */
4332 #define CAN_F2R2_FB29_Pos      (29U)
4333 #define CAN_F2R2_FB29_Msk      (0x1UL << CAN_F2R2_FB29_Pos)                     /*!< 0x20000000 */
4334 #define CAN_F2R2_FB29          CAN_F2R2_FB29_Msk                               /*!<Filter bit 29 */
4335 #define CAN_F2R2_FB30_Pos      (30U)
4336 #define CAN_F2R2_FB30_Msk      (0x1UL << CAN_F2R2_FB30_Pos)                     /*!< 0x40000000 */
4337 #define CAN_F2R2_FB30          CAN_F2R2_FB30_Msk                               /*!<Filter bit 30 */
4338 #define CAN_F2R2_FB31_Pos      (31U)
4339 #define CAN_F2R2_FB31_Msk      (0x1UL << CAN_F2R2_FB31_Pos)                     /*!< 0x80000000 */
4340 #define CAN_F2R2_FB31          CAN_F2R2_FB31_Msk                               /*!<Filter bit 31 */
4341 
4342 /*******************  Bit definition for CAN_F3R2 register  *******************/
4343 #define CAN_F3R2_FB0_Pos       (0U)
4344 #define CAN_F3R2_FB0_Msk       (0x1UL << CAN_F3R2_FB0_Pos)                      /*!< 0x00000001 */
4345 #define CAN_F3R2_FB0           CAN_F3R2_FB0_Msk                                /*!<Filter bit 0 */
4346 #define CAN_F3R2_FB1_Pos       (1U)
4347 #define CAN_F3R2_FB1_Msk       (0x1UL << CAN_F3R2_FB1_Pos)                      /*!< 0x00000002 */
4348 #define CAN_F3R2_FB1           CAN_F3R2_FB1_Msk                                /*!<Filter bit 1 */
4349 #define CAN_F3R2_FB2_Pos       (2U)
4350 #define CAN_F3R2_FB2_Msk       (0x1UL << CAN_F3R2_FB2_Pos)                      /*!< 0x00000004 */
4351 #define CAN_F3R2_FB2           CAN_F3R2_FB2_Msk                                /*!<Filter bit 2 */
4352 #define CAN_F3R2_FB3_Pos       (3U)
4353 #define CAN_F3R2_FB3_Msk       (0x1UL << CAN_F3R2_FB3_Pos)                      /*!< 0x00000008 */
4354 #define CAN_F3R2_FB3           CAN_F3R2_FB3_Msk                                /*!<Filter bit 3 */
4355 #define CAN_F3R2_FB4_Pos       (4U)
4356 #define CAN_F3R2_FB4_Msk       (0x1UL << CAN_F3R2_FB4_Pos)                      /*!< 0x00000010 */
4357 #define CAN_F3R2_FB4           CAN_F3R2_FB4_Msk                                /*!<Filter bit 4 */
4358 #define CAN_F3R2_FB5_Pos       (5U)
4359 #define CAN_F3R2_FB5_Msk       (0x1UL << CAN_F3R2_FB5_Pos)                      /*!< 0x00000020 */
4360 #define CAN_F3R2_FB5           CAN_F3R2_FB5_Msk                                /*!<Filter bit 5 */
4361 #define CAN_F3R2_FB6_Pos       (6U)
4362 #define CAN_F3R2_FB6_Msk       (0x1UL << CAN_F3R2_FB6_Pos)                      /*!< 0x00000040 */
4363 #define CAN_F3R2_FB6           CAN_F3R2_FB6_Msk                                /*!<Filter bit 6 */
4364 #define CAN_F3R2_FB7_Pos       (7U)
4365 #define CAN_F3R2_FB7_Msk       (0x1UL << CAN_F3R2_FB7_Pos)                      /*!< 0x00000080 */
4366 #define CAN_F3R2_FB7           CAN_F3R2_FB7_Msk                                /*!<Filter bit 7 */
4367 #define CAN_F3R2_FB8_Pos       (8U)
4368 #define CAN_F3R2_FB8_Msk       (0x1UL << CAN_F3R2_FB8_Pos)                      /*!< 0x00000100 */
4369 #define CAN_F3R2_FB8           CAN_F3R2_FB8_Msk                                /*!<Filter bit 8 */
4370 #define CAN_F3R2_FB9_Pos       (9U)
4371 #define CAN_F3R2_FB9_Msk       (0x1UL << CAN_F3R2_FB9_Pos)                      /*!< 0x00000200 */
4372 #define CAN_F3R2_FB9           CAN_F3R2_FB9_Msk                                /*!<Filter bit 9 */
4373 #define CAN_F3R2_FB10_Pos      (10U)
4374 #define CAN_F3R2_FB10_Msk      (0x1UL << CAN_F3R2_FB10_Pos)                     /*!< 0x00000400 */
4375 #define CAN_F3R2_FB10          CAN_F3R2_FB10_Msk                               /*!<Filter bit 10 */
4376 #define CAN_F3R2_FB11_Pos      (11U)
4377 #define CAN_F3R2_FB11_Msk      (0x1UL << CAN_F3R2_FB11_Pos)                     /*!< 0x00000800 */
4378 #define CAN_F3R2_FB11          CAN_F3R2_FB11_Msk                               /*!<Filter bit 11 */
4379 #define CAN_F3R2_FB12_Pos      (12U)
4380 #define CAN_F3R2_FB12_Msk      (0x1UL << CAN_F3R2_FB12_Pos)                     /*!< 0x00001000 */
4381 #define CAN_F3R2_FB12          CAN_F3R2_FB12_Msk                               /*!<Filter bit 12 */
4382 #define CAN_F3R2_FB13_Pos      (13U)
4383 #define CAN_F3R2_FB13_Msk      (0x1UL << CAN_F3R2_FB13_Pos)                     /*!< 0x00002000 */
4384 #define CAN_F3R2_FB13          CAN_F3R2_FB13_Msk                               /*!<Filter bit 13 */
4385 #define CAN_F3R2_FB14_Pos      (14U)
4386 #define CAN_F3R2_FB14_Msk      (0x1UL << CAN_F3R2_FB14_Pos)                     /*!< 0x00004000 */
4387 #define CAN_F3R2_FB14          CAN_F3R2_FB14_Msk                               /*!<Filter bit 14 */
4388 #define CAN_F3R2_FB15_Pos      (15U)
4389 #define CAN_F3R2_FB15_Msk      (0x1UL << CAN_F3R2_FB15_Pos)                     /*!< 0x00008000 */
4390 #define CAN_F3R2_FB15          CAN_F3R2_FB15_Msk                               /*!<Filter bit 15 */
4391 #define CAN_F3R2_FB16_Pos      (16U)
4392 #define CAN_F3R2_FB16_Msk      (0x1UL << CAN_F3R2_FB16_Pos)                     /*!< 0x00010000 */
4393 #define CAN_F3R2_FB16          CAN_F3R2_FB16_Msk                               /*!<Filter bit 16 */
4394 #define CAN_F3R2_FB17_Pos      (17U)
4395 #define CAN_F3R2_FB17_Msk      (0x1UL << CAN_F3R2_FB17_Pos)                     /*!< 0x00020000 */
4396 #define CAN_F3R2_FB17          CAN_F3R2_FB17_Msk                               /*!<Filter bit 17 */
4397 #define CAN_F3R2_FB18_Pos      (18U)
4398 #define CAN_F3R2_FB18_Msk      (0x1UL << CAN_F3R2_FB18_Pos)                     /*!< 0x00040000 */
4399 #define CAN_F3R2_FB18          CAN_F3R2_FB18_Msk                               /*!<Filter bit 18 */
4400 #define CAN_F3R2_FB19_Pos      (19U)
4401 #define CAN_F3R2_FB19_Msk      (0x1UL << CAN_F3R2_FB19_Pos)                     /*!< 0x00080000 */
4402 #define CAN_F3R2_FB19          CAN_F3R2_FB19_Msk                               /*!<Filter bit 19 */
4403 #define CAN_F3R2_FB20_Pos      (20U)
4404 #define CAN_F3R2_FB20_Msk      (0x1UL << CAN_F3R2_FB20_Pos)                     /*!< 0x00100000 */
4405 #define CAN_F3R2_FB20          CAN_F3R2_FB20_Msk                               /*!<Filter bit 20 */
4406 #define CAN_F3R2_FB21_Pos      (21U)
4407 #define CAN_F3R2_FB21_Msk      (0x1UL << CAN_F3R2_FB21_Pos)                     /*!< 0x00200000 */
4408 #define CAN_F3R2_FB21          CAN_F3R2_FB21_Msk                               /*!<Filter bit 21 */
4409 #define CAN_F3R2_FB22_Pos      (22U)
4410 #define CAN_F3R2_FB22_Msk      (0x1UL << CAN_F3R2_FB22_Pos)                     /*!< 0x00400000 */
4411 #define CAN_F3R2_FB22          CAN_F3R2_FB22_Msk                               /*!<Filter bit 22 */
4412 #define CAN_F3R2_FB23_Pos      (23U)
4413 #define CAN_F3R2_FB23_Msk      (0x1UL << CAN_F3R2_FB23_Pos)                     /*!< 0x00800000 */
4414 #define CAN_F3R2_FB23          CAN_F3R2_FB23_Msk                               /*!<Filter bit 23 */
4415 #define CAN_F3R2_FB24_Pos      (24U)
4416 #define CAN_F3R2_FB24_Msk      (0x1UL << CAN_F3R2_FB24_Pos)                     /*!< 0x01000000 */
4417 #define CAN_F3R2_FB24          CAN_F3R2_FB24_Msk                               /*!<Filter bit 24 */
4418 #define CAN_F3R2_FB25_Pos      (25U)
4419 #define CAN_F3R2_FB25_Msk      (0x1UL << CAN_F3R2_FB25_Pos)                     /*!< 0x02000000 */
4420 #define CAN_F3R2_FB25          CAN_F3R2_FB25_Msk                               /*!<Filter bit 25 */
4421 #define CAN_F3R2_FB26_Pos      (26U)
4422 #define CAN_F3R2_FB26_Msk      (0x1UL << CAN_F3R2_FB26_Pos)                     /*!< 0x04000000 */
4423 #define CAN_F3R2_FB26          CAN_F3R2_FB26_Msk                               /*!<Filter bit 26 */
4424 #define CAN_F3R2_FB27_Pos      (27U)
4425 #define CAN_F3R2_FB27_Msk      (0x1UL << CAN_F3R2_FB27_Pos)                     /*!< 0x08000000 */
4426 #define CAN_F3R2_FB27          CAN_F3R2_FB27_Msk                               /*!<Filter bit 27 */
4427 #define CAN_F3R2_FB28_Pos      (28U)
4428 #define CAN_F3R2_FB28_Msk      (0x1UL << CAN_F3R2_FB28_Pos)                     /*!< 0x10000000 */
4429 #define CAN_F3R2_FB28          CAN_F3R2_FB28_Msk                               /*!<Filter bit 28 */
4430 #define CAN_F3R2_FB29_Pos      (29U)
4431 #define CAN_F3R2_FB29_Msk      (0x1UL << CAN_F3R2_FB29_Pos)                     /*!< 0x20000000 */
4432 #define CAN_F3R2_FB29          CAN_F3R2_FB29_Msk                               /*!<Filter bit 29 */
4433 #define CAN_F3R2_FB30_Pos      (30U)
4434 #define CAN_F3R2_FB30_Msk      (0x1UL << CAN_F3R2_FB30_Pos)                     /*!< 0x40000000 */
4435 #define CAN_F3R2_FB30          CAN_F3R2_FB30_Msk                               /*!<Filter bit 30 */
4436 #define CAN_F3R2_FB31_Pos      (31U)
4437 #define CAN_F3R2_FB31_Msk      (0x1UL << CAN_F3R2_FB31_Pos)                     /*!< 0x80000000 */
4438 #define CAN_F3R2_FB31          CAN_F3R2_FB31_Msk                               /*!<Filter bit 31 */
4439 
4440 /*******************  Bit definition for CAN_F4R2 register  *******************/
4441 #define CAN_F4R2_FB0_Pos       (0U)
4442 #define CAN_F4R2_FB0_Msk       (0x1UL << CAN_F4R2_FB0_Pos)                      /*!< 0x00000001 */
4443 #define CAN_F4R2_FB0           CAN_F4R2_FB0_Msk                                /*!<Filter bit 0 */
4444 #define CAN_F4R2_FB1_Pos       (1U)
4445 #define CAN_F4R2_FB1_Msk       (0x1UL << CAN_F4R2_FB1_Pos)                      /*!< 0x00000002 */
4446 #define CAN_F4R2_FB1           CAN_F4R2_FB1_Msk                                /*!<Filter bit 1 */
4447 #define CAN_F4R2_FB2_Pos       (2U)
4448 #define CAN_F4R2_FB2_Msk       (0x1UL << CAN_F4R2_FB2_Pos)                      /*!< 0x00000004 */
4449 #define CAN_F4R2_FB2           CAN_F4R2_FB2_Msk                                /*!<Filter bit 2 */
4450 #define CAN_F4R2_FB3_Pos       (3U)
4451 #define CAN_F4R2_FB3_Msk       (0x1UL << CAN_F4R2_FB3_Pos)                      /*!< 0x00000008 */
4452 #define CAN_F4R2_FB3           CAN_F4R2_FB3_Msk                                /*!<Filter bit 3 */
4453 #define CAN_F4R2_FB4_Pos       (4U)
4454 #define CAN_F4R2_FB4_Msk       (0x1UL << CAN_F4R2_FB4_Pos)                      /*!< 0x00000010 */
4455 #define CAN_F4R2_FB4           CAN_F4R2_FB4_Msk                                /*!<Filter bit 4 */
4456 #define CAN_F4R2_FB5_Pos       (5U)
4457 #define CAN_F4R2_FB5_Msk       (0x1UL << CAN_F4R2_FB5_Pos)                      /*!< 0x00000020 */
4458 #define CAN_F4R2_FB5           CAN_F4R2_FB5_Msk                                /*!<Filter bit 5 */
4459 #define CAN_F4R2_FB6_Pos       (6U)
4460 #define CAN_F4R2_FB6_Msk       (0x1UL << CAN_F4R2_FB6_Pos)                      /*!< 0x00000040 */
4461 #define CAN_F4R2_FB6           CAN_F4R2_FB6_Msk                                /*!<Filter bit 6 */
4462 #define CAN_F4R2_FB7_Pos       (7U)
4463 #define CAN_F4R2_FB7_Msk       (0x1UL << CAN_F4R2_FB7_Pos)                      /*!< 0x00000080 */
4464 #define CAN_F4R2_FB7           CAN_F4R2_FB7_Msk                                /*!<Filter bit 7 */
4465 #define CAN_F4R2_FB8_Pos       (8U)
4466 #define CAN_F4R2_FB8_Msk       (0x1UL << CAN_F4R2_FB8_Pos)                      /*!< 0x00000100 */
4467 #define CAN_F4R2_FB8           CAN_F4R2_FB8_Msk                                /*!<Filter bit 8 */
4468 #define CAN_F4R2_FB9_Pos       (9U)
4469 #define CAN_F4R2_FB9_Msk       (0x1UL << CAN_F4R2_FB9_Pos)                      /*!< 0x00000200 */
4470 #define CAN_F4R2_FB9           CAN_F4R2_FB9_Msk                                /*!<Filter bit 9 */
4471 #define CAN_F4R2_FB10_Pos      (10U)
4472 #define CAN_F4R2_FB10_Msk      (0x1UL << CAN_F4R2_FB10_Pos)                     /*!< 0x00000400 */
4473 #define CAN_F4R2_FB10          CAN_F4R2_FB10_Msk                               /*!<Filter bit 10 */
4474 #define CAN_F4R2_FB11_Pos      (11U)
4475 #define CAN_F4R2_FB11_Msk      (0x1UL << CAN_F4R2_FB11_Pos)                     /*!< 0x00000800 */
4476 #define CAN_F4R2_FB11          CAN_F4R2_FB11_Msk                               /*!<Filter bit 11 */
4477 #define CAN_F4R2_FB12_Pos      (12U)
4478 #define CAN_F4R2_FB12_Msk      (0x1UL << CAN_F4R2_FB12_Pos)                     /*!< 0x00001000 */
4479 #define CAN_F4R2_FB12          CAN_F4R2_FB12_Msk                               /*!<Filter bit 12 */
4480 #define CAN_F4R2_FB13_Pos      (13U)
4481 #define CAN_F4R2_FB13_Msk      (0x1UL << CAN_F4R2_FB13_Pos)                     /*!< 0x00002000 */
4482 #define CAN_F4R2_FB13          CAN_F4R2_FB13_Msk                               /*!<Filter bit 13 */
4483 #define CAN_F4R2_FB14_Pos      (14U)
4484 #define CAN_F4R2_FB14_Msk      (0x1UL << CAN_F4R2_FB14_Pos)                     /*!< 0x00004000 */
4485 #define CAN_F4R2_FB14          CAN_F4R2_FB14_Msk                               /*!<Filter bit 14 */
4486 #define CAN_F4R2_FB15_Pos      (15U)
4487 #define CAN_F4R2_FB15_Msk      (0x1UL << CAN_F4R2_FB15_Pos)                     /*!< 0x00008000 */
4488 #define CAN_F4R2_FB15          CAN_F4R2_FB15_Msk                               /*!<Filter bit 15 */
4489 #define CAN_F4R2_FB16_Pos      (16U)
4490 #define CAN_F4R2_FB16_Msk      (0x1UL << CAN_F4R2_FB16_Pos)                     /*!< 0x00010000 */
4491 #define CAN_F4R2_FB16          CAN_F4R2_FB16_Msk                               /*!<Filter bit 16 */
4492 #define CAN_F4R2_FB17_Pos      (17U)
4493 #define CAN_F4R2_FB17_Msk      (0x1UL << CAN_F4R2_FB17_Pos)                     /*!< 0x00020000 */
4494 #define CAN_F4R2_FB17          CAN_F4R2_FB17_Msk                               /*!<Filter bit 17 */
4495 #define CAN_F4R2_FB18_Pos      (18U)
4496 #define CAN_F4R2_FB18_Msk      (0x1UL << CAN_F4R2_FB18_Pos)                     /*!< 0x00040000 */
4497 #define CAN_F4R2_FB18          CAN_F4R2_FB18_Msk                               /*!<Filter bit 18 */
4498 #define CAN_F4R2_FB19_Pos      (19U)
4499 #define CAN_F4R2_FB19_Msk      (0x1UL << CAN_F4R2_FB19_Pos)                     /*!< 0x00080000 */
4500 #define CAN_F4R2_FB19          CAN_F4R2_FB19_Msk                               /*!<Filter bit 19 */
4501 #define CAN_F4R2_FB20_Pos      (20U)
4502 #define CAN_F4R2_FB20_Msk      (0x1UL << CAN_F4R2_FB20_Pos)                     /*!< 0x00100000 */
4503 #define CAN_F4R2_FB20          CAN_F4R2_FB20_Msk                               /*!<Filter bit 20 */
4504 #define CAN_F4R2_FB21_Pos      (21U)
4505 #define CAN_F4R2_FB21_Msk      (0x1UL << CAN_F4R2_FB21_Pos)                     /*!< 0x00200000 */
4506 #define CAN_F4R2_FB21          CAN_F4R2_FB21_Msk                               /*!<Filter bit 21 */
4507 #define CAN_F4R2_FB22_Pos      (22U)
4508 #define CAN_F4R2_FB22_Msk      (0x1UL << CAN_F4R2_FB22_Pos)                     /*!< 0x00400000 */
4509 #define CAN_F4R2_FB22          CAN_F4R2_FB22_Msk                               /*!<Filter bit 22 */
4510 #define CAN_F4R2_FB23_Pos      (23U)
4511 #define CAN_F4R2_FB23_Msk      (0x1UL << CAN_F4R2_FB23_Pos)                     /*!< 0x00800000 */
4512 #define CAN_F4R2_FB23          CAN_F4R2_FB23_Msk                               /*!<Filter bit 23 */
4513 #define CAN_F4R2_FB24_Pos      (24U)
4514 #define CAN_F4R2_FB24_Msk      (0x1UL << CAN_F4R2_FB24_Pos)                     /*!< 0x01000000 */
4515 #define CAN_F4R2_FB24          CAN_F4R2_FB24_Msk                               /*!<Filter bit 24 */
4516 #define CAN_F4R2_FB25_Pos      (25U)
4517 #define CAN_F4R2_FB25_Msk      (0x1UL << CAN_F4R2_FB25_Pos)                     /*!< 0x02000000 */
4518 #define CAN_F4R2_FB25          CAN_F4R2_FB25_Msk                               /*!<Filter bit 25 */
4519 #define CAN_F4R2_FB26_Pos      (26U)
4520 #define CAN_F4R2_FB26_Msk      (0x1UL << CAN_F4R2_FB26_Pos)                     /*!< 0x04000000 */
4521 #define CAN_F4R2_FB26          CAN_F4R2_FB26_Msk                               /*!<Filter bit 26 */
4522 #define CAN_F4R2_FB27_Pos      (27U)
4523 #define CAN_F4R2_FB27_Msk      (0x1UL << CAN_F4R2_FB27_Pos)                     /*!< 0x08000000 */
4524 #define CAN_F4R2_FB27          CAN_F4R2_FB27_Msk                               /*!<Filter bit 27 */
4525 #define CAN_F4R2_FB28_Pos      (28U)
4526 #define CAN_F4R2_FB28_Msk      (0x1UL << CAN_F4R2_FB28_Pos)                     /*!< 0x10000000 */
4527 #define CAN_F4R2_FB28          CAN_F4R2_FB28_Msk                               /*!<Filter bit 28 */
4528 #define CAN_F4R2_FB29_Pos      (29U)
4529 #define CAN_F4R2_FB29_Msk      (0x1UL << CAN_F4R2_FB29_Pos)                     /*!< 0x20000000 */
4530 #define CAN_F4R2_FB29          CAN_F4R2_FB29_Msk                               /*!<Filter bit 29 */
4531 #define CAN_F4R2_FB30_Pos      (30U)
4532 #define CAN_F4R2_FB30_Msk      (0x1UL << CAN_F4R2_FB30_Pos)                     /*!< 0x40000000 */
4533 #define CAN_F4R2_FB30          CAN_F4R2_FB30_Msk                               /*!<Filter bit 30 */
4534 #define CAN_F4R2_FB31_Pos      (31U)
4535 #define CAN_F4R2_FB31_Msk      (0x1UL << CAN_F4R2_FB31_Pos)                     /*!< 0x80000000 */
4536 #define CAN_F4R2_FB31          CAN_F4R2_FB31_Msk                               /*!<Filter bit 31 */
4537 
4538 /*******************  Bit definition for CAN_F5R2 register  *******************/
4539 #define CAN_F5R2_FB0_Pos       (0U)
4540 #define CAN_F5R2_FB0_Msk       (0x1UL << CAN_F5R2_FB0_Pos)                      /*!< 0x00000001 */
4541 #define CAN_F5R2_FB0           CAN_F5R2_FB0_Msk                                /*!<Filter bit 0 */
4542 #define CAN_F5R2_FB1_Pos       (1U)
4543 #define CAN_F5R2_FB1_Msk       (0x1UL << CAN_F5R2_FB1_Pos)                      /*!< 0x00000002 */
4544 #define CAN_F5R2_FB1           CAN_F5R2_FB1_Msk                                /*!<Filter bit 1 */
4545 #define CAN_F5R2_FB2_Pos       (2U)
4546 #define CAN_F5R2_FB2_Msk       (0x1UL << CAN_F5R2_FB2_Pos)                      /*!< 0x00000004 */
4547 #define CAN_F5R2_FB2           CAN_F5R2_FB2_Msk                                /*!<Filter bit 2 */
4548 #define CAN_F5R2_FB3_Pos       (3U)
4549 #define CAN_F5R2_FB3_Msk       (0x1UL << CAN_F5R2_FB3_Pos)                      /*!< 0x00000008 */
4550 #define CAN_F5R2_FB3           CAN_F5R2_FB3_Msk                                /*!<Filter bit 3 */
4551 #define CAN_F5R2_FB4_Pos       (4U)
4552 #define CAN_F5R2_FB4_Msk       (0x1UL << CAN_F5R2_FB4_Pos)                      /*!< 0x00000010 */
4553 #define CAN_F5R2_FB4           CAN_F5R2_FB4_Msk                                /*!<Filter bit 4 */
4554 #define CAN_F5R2_FB5_Pos       (5U)
4555 #define CAN_F5R2_FB5_Msk       (0x1UL << CAN_F5R2_FB5_Pos)                      /*!< 0x00000020 */
4556 #define CAN_F5R2_FB5           CAN_F5R2_FB5_Msk                                /*!<Filter bit 5 */
4557 #define CAN_F5R2_FB6_Pos       (6U)
4558 #define CAN_F5R2_FB6_Msk       (0x1UL << CAN_F5R2_FB6_Pos)                      /*!< 0x00000040 */
4559 #define CAN_F5R2_FB6           CAN_F5R2_FB6_Msk                                /*!<Filter bit 6 */
4560 #define CAN_F5R2_FB7_Pos       (7U)
4561 #define CAN_F5R2_FB7_Msk       (0x1UL << CAN_F5R2_FB7_Pos)                      /*!< 0x00000080 */
4562 #define CAN_F5R2_FB7           CAN_F5R2_FB7_Msk                                /*!<Filter bit 7 */
4563 #define CAN_F5R2_FB8_Pos       (8U)
4564 #define CAN_F5R2_FB8_Msk       (0x1UL << CAN_F5R2_FB8_Pos)                      /*!< 0x00000100 */
4565 #define CAN_F5R2_FB8           CAN_F5R2_FB8_Msk                                /*!<Filter bit 8 */
4566 #define CAN_F5R2_FB9_Pos       (9U)
4567 #define CAN_F5R2_FB9_Msk       (0x1UL << CAN_F5R2_FB9_Pos)                      /*!< 0x00000200 */
4568 #define CAN_F5R2_FB9           CAN_F5R2_FB9_Msk                                /*!<Filter bit 9 */
4569 #define CAN_F5R2_FB10_Pos      (10U)
4570 #define CAN_F5R2_FB10_Msk      (0x1UL << CAN_F5R2_FB10_Pos)                     /*!< 0x00000400 */
4571 #define CAN_F5R2_FB10          CAN_F5R2_FB10_Msk                               /*!<Filter bit 10 */
4572 #define CAN_F5R2_FB11_Pos      (11U)
4573 #define CAN_F5R2_FB11_Msk      (0x1UL << CAN_F5R2_FB11_Pos)                     /*!< 0x00000800 */
4574 #define CAN_F5R2_FB11          CAN_F5R2_FB11_Msk                               /*!<Filter bit 11 */
4575 #define CAN_F5R2_FB12_Pos      (12U)
4576 #define CAN_F5R2_FB12_Msk      (0x1UL << CAN_F5R2_FB12_Pos)                     /*!< 0x00001000 */
4577 #define CAN_F5R2_FB12          CAN_F5R2_FB12_Msk                               /*!<Filter bit 12 */
4578 #define CAN_F5R2_FB13_Pos      (13U)
4579 #define CAN_F5R2_FB13_Msk      (0x1UL << CAN_F5R2_FB13_Pos)                     /*!< 0x00002000 */
4580 #define CAN_F5R2_FB13          CAN_F5R2_FB13_Msk                               /*!<Filter bit 13 */
4581 #define CAN_F5R2_FB14_Pos      (14U)
4582 #define CAN_F5R2_FB14_Msk      (0x1UL << CAN_F5R2_FB14_Pos)                     /*!< 0x00004000 */
4583 #define CAN_F5R2_FB14          CAN_F5R2_FB14_Msk                               /*!<Filter bit 14 */
4584 #define CAN_F5R2_FB15_Pos      (15U)
4585 #define CAN_F5R2_FB15_Msk      (0x1UL << CAN_F5R2_FB15_Pos)                     /*!< 0x00008000 */
4586 #define CAN_F5R2_FB15          CAN_F5R2_FB15_Msk                               /*!<Filter bit 15 */
4587 #define CAN_F5R2_FB16_Pos      (16U)
4588 #define CAN_F5R2_FB16_Msk      (0x1UL << CAN_F5R2_FB16_Pos)                     /*!< 0x00010000 */
4589 #define CAN_F5R2_FB16          CAN_F5R2_FB16_Msk                               /*!<Filter bit 16 */
4590 #define CAN_F5R2_FB17_Pos      (17U)
4591 #define CAN_F5R2_FB17_Msk      (0x1UL << CAN_F5R2_FB17_Pos)                     /*!< 0x00020000 */
4592 #define CAN_F5R2_FB17          CAN_F5R2_FB17_Msk                               /*!<Filter bit 17 */
4593 #define CAN_F5R2_FB18_Pos      (18U)
4594 #define CAN_F5R2_FB18_Msk      (0x1UL << CAN_F5R2_FB18_Pos)                     /*!< 0x00040000 */
4595 #define CAN_F5R2_FB18          CAN_F5R2_FB18_Msk                               /*!<Filter bit 18 */
4596 #define CAN_F5R2_FB19_Pos      (19U)
4597 #define CAN_F5R2_FB19_Msk      (0x1UL << CAN_F5R2_FB19_Pos)                     /*!< 0x00080000 */
4598 #define CAN_F5R2_FB19          CAN_F5R2_FB19_Msk                               /*!<Filter bit 19 */
4599 #define CAN_F5R2_FB20_Pos      (20U)
4600 #define CAN_F5R2_FB20_Msk      (0x1UL << CAN_F5R2_FB20_Pos)                     /*!< 0x00100000 */
4601 #define CAN_F5R2_FB20          CAN_F5R2_FB20_Msk                               /*!<Filter bit 20 */
4602 #define CAN_F5R2_FB21_Pos      (21U)
4603 #define CAN_F5R2_FB21_Msk      (0x1UL << CAN_F5R2_FB21_Pos)                     /*!< 0x00200000 */
4604 #define CAN_F5R2_FB21          CAN_F5R2_FB21_Msk                               /*!<Filter bit 21 */
4605 #define CAN_F5R2_FB22_Pos      (22U)
4606 #define CAN_F5R2_FB22_Msk      (0x1UL << CAN_F5R2_FB22_Pos)                     /*!< 0x00400000 */
4607 #define CAN_F5R2_FB22          CAN_F5R2_FB22_Msk                               /*!<Filter bit 22 */
4608 #define CAN_F5R2_FB23_Pos      (23U)
4609 #define CAN_F5R2_FB23_Msk      (0x1UL << CAN_F5R2_FB23_Pos)                     /*!< 0x00800000 */
4610 #define CAN_F5R2_FB23          CAN_F5R2_FB23_Msk                               /*!<Filter bit 23 */
4611 #define CAN_F5R2_FB24_Pos      (24U)
4612 #define CAN_F5R2_FB24_Msk      (0x1UL << CAN_F5R2_FB24_Pos)                     /*!< 0x01000000 */
4613 #define CAN_F5R2_FB24          CAN_F5R2_FB24_Msk                               /*!<Filter bit 24 */
4614 #define CAN_F5R2_FB25_Pos      (25U)
4615 #define CAN_F5R2_FB25_Msk      (0x1UL << CAN_F5R2_FB25_Pos)                     /*!< 0x02000000 */
4616 #define CAN_F5R2_FB25          CAN_F5R2_FB25_Msk                               /*!<Filter bit 25 */
4617 #define CAN_F5R2_FB26_Pos      (26U)
4618 #define CAN_F5R2_FB26_Msk      (0x1UL << CAN_F5R2_FB26_Pos)                     /*!< 0x04000000 */
4619 #define CAN_F5R2_FB26          CAN_F5R2_FB26_Msk                               /*!<Filter bit 26 */
4620 #define CAN_F5R2_FB27_Pos      (27U)
4621 #define CAN_F5R2_FB27_Msk      (0x1UL << CAN_F5R2_FB27_Pos)                     /*!< 0x08000000 */
4622 #define CAN_F5R2_FB27          CAN_F5R2_FB27_Msk                               /*!<Filter bit 27 */
4623 #define CAN_F5R2_FB28_Pos      (28U)
4624 #define CAN_F5R2_FB28_Msk      (0x1UL << CAN_F5R2_FB28_Pos)                     /*!< 0x10000000 */
4625 #define CAN_F5R2_FB28          CAN_F5R2_FB28_Msk                               /*!<Filter bit 28 */
4626 #define CAN_F5R2_FB29_Pos      (29U)
4627 #define CAN_F5R2_FB29_Msk      (0x1UL << CAN_F5R2_FB29_Pos)                     /*!< 0x20000000 */
4628 #define CAN_F5R2_FB29          CAN_F5R2_FB29_Msk                               /*!<Filter bit 29 */
4629 #define CAN_F5R2_FB30_Pos      (30U)
4630 #define CAN_F5R2_FB30_Msk      (0x1UL << CAN_F5R2_FB30_Pos)                     /*!< 0x40000000 */
4631 #define CAN_F5R2_FB30          CAN_F5R2_FB30_Msk                               /*!<Filter bit 30 */
4632 #define CAN_F5R2_FB31_Pos      (31U)
4633 #define CAN_F5R2_FB31_Msk      (0x1UL << CAN_F5R2_FB31_Pos)                     /*!< 0x80000000 */
4634 #define CAN_F5R2_FB31          CAN_F5R2_FB31_Msk                               /*!<Filter bit 31 */
4635 
4636 /*******************  Bit definition for CAN_F6R2 register  *******************/
4637 #define CAN_F6R2_FB0_Pos       (0U)
4638 #define CAN_F6R2_FB0_Msk       (0x1UL << CAN_F6R2_FB0_Pos)                      /*!< 0x00000001 */
4639 #define CAN_F6R2_FB0           CAN_F6R2_FB0_Msk                                /*!<Filter bit 0 */
4640 #define CAN_F6R2_FB1_Pos       (1U)
4641 #define CAN_F6R2_FB1_Msk       (0x1UL << CAN_F6R2_FB1_Pos)                      /*!< 0x00000002 */
4642 #define CAN_F6R2_FB1           CAN_F6R2_FB1_Msk                                /*!<Filter bit 1 */
4643 #define CAN_F6R2_FB2_Pos       (2U)
4644 #define CAN_F6R2_FB2_Msk       (0x1UL << CAN_F6R2_FB2_Pos)                      /*!< 0x00000004 */
4645 #define CAN_F6R2_FB2           CAN_F6R2_FB2_Msk                                /*!<Filter bit 2 */
4646 #define CAN_F6R2_FB3_Pos       (3U)
4647 #define CAN_F6R2_FB3_Msk       (0x1UL << CAN_F6R2_FB3_Pos)                      /*!< 0x00000008 */
4648 #define CAN_F6R2_FB3           CAN_F6R2_FB3_Msk                                /*!<Filter bit 3 */
4649 #define CAN_F6R2_FB4_Pos       (4U)
4650 #define CAN_F6R2_FB4_Msk       (0x1UL << CAN_F6R2_FB4_Pos)                      /*!< 0x00000010 */
4651 #define CAN_F6R2_FB4           CAN_F6R2_FB4_Msk                                /*!<Filter bit 4 */
4652 #define CAN_F6R2_FB5_Pos       (5U)
4653 #define CAN_F6R2_FB5_Msk       (0x1UL << CAN_F6R2_FB5_Pos)                      /*!< 0x00000020 */
4654 #define CAN_F6R2_FB5           CAN_F6R2_FB5_Msk                                /*!<Filter bit 5 */
4655 #define CAN_F6R2_FB6_Pos       (6U)
4656 #define CAN_F6R2_FB6_Msk       (0x1UL << CAN_F6R2_FB6_Pos)                      /*!< 0x00000040 */
4657 #define CAN_F6R2_FB6           CAN_F6R2_FB6_Msk                                /*!<Filter bit 6 */
4658 #define CAN_F6R2_FB7_Pos       (7U)
4659 #define CAN_F6R2_FB7_Msk       (0x1UL << CAN_F6R2_FB7_Pos)                      /*!< 0x00000080 */
4660 #define CAN_F6R2_FB7           CAN_F6R2_FB7_Msk                                /*!<Filter bit 7 */
4661 #define CAN_F6R2_FB8_Pos       (8U)
4662 #define CAN_F6R2_FB8_Msk       (0x1UL << CAN_F6R2_FB8_Pos)                      /*!< 0x00000100 */
4663 #define CAN_F6R2_FB8           CAN_F6R2_FB8_Msk                                /*!<Filter bit 8 */
4664 #define CAN_F6R2_FB9_Pos       (9U)
4665 #define CAN_F6R2_FB9_Msk       (0x1UL << CAN_F6R2_FB9_Pos)                      /*!< 0x00000200 */
4666 #define CAN_F6R2_FB9           CAN_F6R2_FB9_Msk                                /*!<Filter bit 9 */
4667 #define CAN_F6R2_FB10_Pos      (10U)
4668 #define CAN_F6R2_FB10_Msk      (0x1UL << CAN_F6R2_FB10_Pos)                     /*!< 0x00000400 */
4669 #define CAN_F6R2_FB10          CAN_F6R2_FB10_Msk                               /*!<Filter bit 10 */
4670 #define CAN_F6R2_FB11_Pos      (11U)
4671 #define CAN_F6R2_FB11_Msk      (0x1UL << CAN_F6R2_FB11_Pos)                     /*!< 0x00000800 */
4672 #define CAN_F6R2_FB11          CAN_F6R2_FB11_Msk                               /*!<Filter bit 11 */
4673 #define CAN_F6R2_FB12_Pos      (12U)
4674 #define CAN_F6R2_FB12_Msk      (0x1UL << CAN_F6R2_FB12_Pos)                     /*!< 0x00001000 */
4675 #define CAN_F6R2_FB12          CAN_F6R2_FB12_Msk                               /*!<Filter bit 12 */
4676 #define CAN_F6R2_FB13_Pos      (13U)
4677 #define CAN_F6R2_FB13_Msk      (0x1UL << CAN_F6R2_FB13_Pos)                     /*!< 0x00002000 */
4678 #define CAN_F6R2_FB13          CAN_F6R2_FB13_Msk                               /*!<Filter bit 13 */
4679 #define CAN_F6R2_FB14_Pos      (14U)
4680 #define CAN_F6R2_FB14_Msk      (0x1UL << CAN_F6R2_FB14_Pos)                     /*!< 0x00004000 */
4681 #define CAN_F6R2_FB14          CAN_F6R2_FB14_Msk                               /*!<Filter bit 14 */
4682 #define CAN_F6R2_FB15_Pos      (15U)
4683 #define CAN_F6R2_FB15_Msk      (0x1UL << CAN_F6R2_FB15_Pos)                     /*!< 0x00008000 */
4684 #define CAN_F6R2_FB15          CAN_F6R2_FB15_Msk                               /*!<Filter bit 15 */
4685 #define CAN_F6R2_FB16_Pos      (16U)
4686 #define CAN_F6R2_FB16_Msk      (0x1UL << CAN_F6R2_FB16_Pos)                     /*!< 0x00010000 */
4687 #define CAN_F6R2_FB16          CAN_F6R2_FB16_Msk                               /*!<Filter bit 16 */
4688 #define CAN_F6R2_FB17_Pos      (17U)
4689 #define CAN_F6R2_FB17_Msk      (0x1UL << CAN_F6R2_FB17_Pos)                     /*!< 0x00020000 */
4690 #define CAN_F6R2_FB17          CAN_F6R2_FB17_Msk                               /*!<Filter bit 17 */
4691 #define CAN_F6R2_FB18_Pos      (18U)
4692 #define CAN_F6R2_FB18_Msk      (0x1UL << CAN_F6R2_FB18_Pos)                     /*!< 0x00040000 */
4693 #define CAN_F6R2_FB18          CAN_F6R2_FB18_Msk                               /*!<Filter bit 18 */
4694 #define CAN_F6R2_FB19_Pos      (19U)
4695 #define CAN_F6R2_FB19_Msk      (0x1UL << CAN_F6R2_FB19_Pos)                     /*!< 0x00080000 */
4696 #define CAN_F6R2_FB19          CAN_F6R2_FB19_Msk                               /*!<Filter bit 19 */
4697 #define CAN_F6R2_FB20_Pos      (20U)
4698 #define CAN_F6R2_FB20_Msk      (0x1UL << CAN_F6R2_FB20_Pos)                     /*!< 0x00100000 */
4699 #define CAN_F6R2_FB20          CAN_F6R2_FB20_Msk                               /*!<Filter bit 20 */
4700 #define CAN_F6R2_FB21_Pos      (21U)
4701 #define CAN_F6R2_FB21_Msk      (0x1UL << CAN_F6R2_FB21_Pos)                     /*!< 0x00200000 */
4702 #define CAN_F6R2_FB21          CAN_F6R2_FB21_Msk                               /*!<Filter bit 21 */
4703 #define CAN_F6R2_FB22_Pos      (22U)
4704 #define CAN_F6R2_FB22_Msk      (0x1UL << CAN_F6R2_FB22_Pos)                     /*!< 0x00400000 */
4705 #define CAN_F6R2_FB22          CAN_F6R2_FB22_Msk                               /*!<Filter bit 22 */
4706 #define CAN_F6R2_FB23_Pos      (23U)
4707 #define CAN_F6R2_FB23_Msk      (0x1UL << CAN_F6R2_FB23_Pos)                     /*!< 0x00800000 */
4708 #define CAN_F6R2_FB23          CAN_F6R2_FB23_Msk                               /*!<Filter bit 23 */
4709 #define CAN_F6R2_FB24_Pos      (24U)
4710 #define CAN_F6R2_FB24_Msk      (0x1UL << CAN_F6R2_FB24_Pos)                     /*!< 0x01000000 */
4711 #define CAN_F6R2_FB24          CAN_F6R2_FB24_Msk                               /*!<Filter bit 24 */
4712 #define CAN_F6R2_FB25_Pos      (25U)
4713 #define CAN_F6R2_FB25_Msk      (0x1UL << CAN_F6R2_FB25_Pos)                     /*!< 0x02000000 */
4714 #define CAN_F6R2_FB25          CAN_F6R2_FB25_Msk                               /*!<Filter bit 25 */
4715 #define CAN_F6R2_FB26_Pos      (26U)
4716 #define CAN_F6R2_FB26_Msk      (0x1UL << CAN_F6R2_FB26_Pos)                     /*!< 0x04000000 */
4717 #define CAN_F6R2_FB26          CAN_F6R2_FB26_Msk                               /*!<Filter bit 26 */
4718 #define CAN_F6R2_FB27_Pos      (27U)
4719 #define CAN_F6R2_FB27_Msk      (0x1UL << CAN_F6R2_FB27_Pos)                     /*!< 0x08000000 */
4720 #define CAN_F6R2_FB27          CAN_F6R2_FB27_Msk                               /*!<Filter bit 27 */
4721 #define CAN_F6R2_FB28_Pos      (28U)
4722 #define CAN_F6R2_FB28_Msk      (0x1UL << CAN_F6R2_FB28_Pos)                     /*!< 0x10000000 */
4723 #define CAN_F6R2_FB28          CAN_F6R2_FB28_Msk                               /*!<Filter bit 28 */
4724 #define CAN_F6R2_FB29_Pos      (29U)
4725 #define CAN_F6R2_FB29_Msk      (0x1UL << CAN_F6R2_FB29_Pos)                     /*!< 0x20000000 */
4726 #define CAN_F6R2_FB29          CAN_F6R2_FB29_Msk                               /*!<Filter bit 29 */
4727 #define CAN_F6R2_FB30_Pos      (30U)
4728 #define CAN_F6R2_FB30_Msk      (0x1UL << CAN_F6R2_FB30_Pos)                     /*!< 0x40000000 */
4729 #define CAN_F6R2_FB30          CAN_F6R2_FB30_Msk                               /*!<Filter bit 30 */
4730 #define CAN_F6R2_FB31_Pos      (31U)
4731 #define CAN_F6R2_FB31_Msk      (0x1UL << CAN_F6R2_FB31_Pos)                     /*!< 0x80000000 */
4732 #define CAN_F6R2_FB31          CAN_F6R2_FB31_Msk                               /*!<Filter bit 31 */
4733 
4734 /*******************  Bit definition for CAN_F7R2 register  *******************/
4735 #define CAN_F7R2_FB0_Pos       (0U)
4736 #define CAN_F7R2_FB0_Msk       (0x1UL << CAN_F7R2_FB0_Pos)                      /*!< 0x00000001 */
4737 #define CAN_F7R2_FB0           CAN_F7R2_FB0_Msk                                /*!<Filter bit 0 */
4738 #define CAN_F7R2_FB1_Pos       (1U)
4739 #define CAN_F7R2_FB1_Msk       (0x1UL << CAN_F7R2_FB1_Pos)                      /*!< 0x00000002 */
4740 #define CAN_F7R2_FB1           CAN_F7R2_FB1_Msk                                /*!<Filter bit 1 */
4741 #define CAN_F7R2_FB2_Pos       (2U)
4742 #define CAN_F7R2_FB2_Msk       (0x1UL << CAN_F7R2_FB2_Pos)                      /*!< 0x00000004 */
4743 #define CAN_F7R2_FB2           CAN_F7R2_FB2_Msk                                /*!<Filter bit 2 */
4744 #define CAN_F7R2_FB3_Pos       (3U)
4745 #define CAN_F7R2_FB3_Msk       (0x1UL << CAN_F7R2_FB3_Pos)                      /*!< 0x00000008 */
4746 #define CAN_F7R2_FB3           CAN_F7R2_FB3_Msk                                /*!<Filter bit 3 */
4747 #define CAN_F7R2_FB4_Pos       (4U)
4748 #define CAN_F7R2_FB4_Msk       (0x1UL << CAN_F7R2_FB4_Pos)                      /*!< 0x00000010 */
4749 #define CAN_F7R2_FB4           CAN_F7R2_FB4_Msk                                /*!<Filter bit 4 */
4750 #define CAN_F7R2_FB5_Pos       (5U)
4751 #define CAN_F7R2_FB5_Msk       (0x1UL << CAN_F7R2_FB5_Pos)                      /*!< 0x00000020 */
4752 #define CAN_F7R2_FB5           CAN_F7R2_FB5_Msk                                /*!<Filter bit 5 */
4753 #define CAN_F7R2_FB6_Pos       (6U)
4754 #define CAN_F7R2_FB6_Msk       (0x1UL << CAN_F7R2_FB6_Pos)                      /*!< 0x00000040 */
4755 #define CAN_F7R2_FB6           CAN_F7R2_FB6_Msk                                /*!<Filter bit 6 */
4756 #define CAN_F7R2_FB7_Pos       (7U)
4757 #define CAN_F7R2_FB7_Msk       (0x1UL << CAN_F7R2_FB7_Pos)                      /*!< 0x00000080 */
4758 #define CAN_F7R2_FB7           CAN_F7R2_FB7_Msk                                /*!<Filter bit 7 */
4759 #define CAN_F7R2_FB8_Pos       (8U)
4760 #define CAN_F7R2_FB8_Msk       (0x1UL << CAN_F7R2_FB8_Pos)                      /*!< 0x00000100 */
4761 #define CAN_F7R2_FB8           CAN_F7R2_FB8_Msk                                /*!<Filter bit 8 */
4762 #define CAN_F7R2_FB9_Pos       (9U)
4763 #define CAN_F7R2_FB9_Msk       (0x1UL << CAN_F7R2_FB9_Pos)                      /*!< 0x00000200 */
4764 #define CAN_F7R2_FB9           CAN_F7R2_FB9_Msk                                /*!<Filter bit 9 */
4765 #define CAN_F7R2_FB10_Pos      (10U)
4766 #define CAN_F7R2_FB10_Msk      (0x1UL << CAN_F7R2_FB10_Pos)                     /*!< 0x00000400 */
4767 #define CAN_F7R2_FB10          CAN_F7R2_FB10_Msk                               /*!<Filter bit 10 */
4768 #define CAN_F7R2_FB11_Pos      (11U)
4769 #define CAN_F7R2_FB11_Msk      (0x1UL << CAN_F7R2_FB11_Pos)                     /*!< 0x00000800 */
4770 #define CAN_F7R2_FB11          CAN_F7R2_FB11_Msk                               /*!<Filter bit 11 */
4771 #define CAN_F7R2_FB12_Pos      (12U)
4772 #define CAN_F7R2_FB12_Msk      (0x1UL << CAN_F7R2_FB12_Pos)                     /*!< 0x00001000 */
4773 #define CAN_F7R2_FB12          CAN_F7R2_FB12_Msk                               /*!<Filter bit 12 */
4774 #define CAN_F7R2_FB13_Pos      (13U)
4775 #define CAN_F7R2_FB13_Msk      (0x1UL << CAN_F7R2_FB13_Pos)                     /*!< 0x00002000 */
4776 #define CAN_F7R2_FB13          CAN_F7R2_FB13_Msk                               /*!<Filter bit 13 */
4777 #define CAN_F7R2_FB14_Pos      (14U)
4778 #define CAN_F7R2_FB14_Msk      (0x1UL << CAN_F7R2_FB14_Pos)                     /*!< 0x00004000 */
4779 #define CAN_F7R2_FB14          CAN_F7R2_FB14_Msk                               /*!<Filter bit 14 */
4780 #define CAN_F7R2_FB15_Pos      (15U)
4781 #define CAN_F7R2_FB15_Msk      (0x1UL << CAN_F7R2_FB15_Pos)                     /*!< 0x00008000 */
4782 #define CAN_F7R2_FB15          CAN_F7R2_FB15_Msk                               /*!<Filter bit 15 */
4783 #define CAN_F7R2_FB16_Pos      (16U)
4784 #define CAN_F7R2_FB16_Msk      (0x1UL << CAN_F7R2_FB16_Pos)                     /*!< 0x00010000 */
4785 #define CAN_F7R2_FB16          CAN_F7R2_FB16_Msk                               /*!<Filter bit 16 */
4786 #define CAN_F7R2_FB17_Pos      (17U)
4787 #define CAN_F7R2_FB17_Msk      (0x1UL << CAN_F7R2_FB17_Pos)                     /*!< 0x00020000 */
4788 #define CAN_F7R2_FB17          CAN_F7R2_FB17_Msk                               /*!<Filter bit 17 */
4789 #define CAN_F7R2_FB18_Pos      (18U)
4790 #define CAN_F7R2_FB18_Msk      (0x1UL << CAN_F7R2_FB18_Pos)                     /*!< 0x00040000 */
4791 #define CAN_F7R2_FB18          CAN_F7R2_FB18_Msk                               /*!<Filter bit 18 */
4792 #define CAN_F7R2_FB19_Pos      (19U)
4793 #define CAN_F7R2_FB19_Msk      (0x1UL << CAN_F7R2_FB19_Pos)                     /*!< 0x00080000 */
4794 #define CAN_F7R2_FB19          CAN_F7R2_FB19_Msk                               /*!<Filter bit 19 */
4795 #define CAN_F7R2_FB20_Pos      (20U)
4796 #define CAN_F7R2_FB20_Msk      (0x1UL << CAN_F7R2_FB20_Pos)                     /*!< 0x00100000 */
4797 #define CAN_F7R2_FB20          CAN_F7R2_FB20_Msk                               /*!<Filter bit 20 */
4798 #define CAN_F7R2_FB21_Pos      (21U)
4799 #define CAN_F7R2_FB21_Msk      (0x1UL << CAN_F7R2_FB21_Pos)                     /*!< 0x00200000 */
4800 #define CAN_F7R2_FB21          CAN_F7R2_FB21_Msk                               /*!<Filter bit 21 */
4801 #define CAN_F7R2_FB22_Pos      (22U)
4802 #define CAN_F7R2_FB22_Msk      (0x1UL << CAN_F7R2_FB22_Pos)                     /*!< 0x00400000 */
4803 #define CAN_F7R2_FB22          CAN_F7R2_FB22_Msk                               /*!<Filter bit 22 */
4804 #define CAN_F7R2_FB23_Pos      (23U)
4805 #define CAN_F7R2_FB23_Msk      (0x1UL << CAN_F7R2_FB23_Pos)                     /*!< 0x00800000 */
4806 #define CAN_F7R2_FB23          CAN_F7R2_FB23_Msk                               /*!<Filter bit 23 */
4807 #define CAN_F7R2_FB24_Pos      (24U)
4808 #define CAN_F7R2_FB24_Msk      (0x1UL << CAN_F7R2_FB24_Pos)                     /*!< 0x01000000 */
4809 #define CAN_F7R2_FB24          CAN_F7R2_FB24_Msk                               /*!<Filter bit 24 */
4810 #define CAN_F7R2_FB25_Pos      (25U)
4811 #define CAN_F7R2_FB25_Msk      (0x1UL << CAN_F7R2_FB25_Pos)                     /*!< 0x02000000 */
4812 #define CAN_F7R2_FB25          CAN_F7R2_FB25_Msk                               /*!<Filter bit 25 */
4813 #define CAN_F7R2_FB26_Pos      (26U)
4814 #define CAN_F7R2_FB26_Msk      (0x1UL << CAN_F7R2_FB26_Pos)                     /*!< 0x04000000 */
4815 #define CAN_F7R2_FB26          CAN_F7R2_FB26_Msk                               /*!<Filter bit 26 */
4816 #define CAN_F7R2_FB27_Pos      (27U)
4817 #define CAN_F7R2_FB27_Msk      (0x1UL << CAN_F7R2_FB27_Pos)                     /*!< 0x08000000 */
4818 #define CAN_F7R2_FB27          CAN_F7R2_FB27_Msk                               /*!<Filter bit 27 */
4819 #define CAN_F7R2_FB28_Pos      (28U)
4820 #define CAN_F7R2_FB28_Msk      (0x1UL << CAN_F7R2_FB28_Pos)                     /*!< 0x10000000 */
4821 #define CAN_F7R2_FB28          CAN_F7R2_FB28_Msk                               /*!<Filter bit 28 */
4822 #define CAN_F7R2_FB29_Pos      (29U)
4823 #define CAN_F7R2_FB29_Msk      (0x1UL << CAN_F7R2_FB29_Pos)                     /*!< 0x20000000 */
4824 #define CAN_F7R2_FB29          CAN_F7R2_FB29_Msk                               /*!<Filter bit 29 */
4825 #define CAN_F7R2_FB30_Pos      (30U)
4826 #define CAN_F7R2_FB30_Msk      (0x1UL << CAN_F7R2_FB30_Pos)                     /*!< 0x40000000 */
4827 #define CAN_F7R2_FB30          CAN_F7R2_FB30_Msk                               /*!<Filter bit 30 */
4828 #define CAN_F7R2_FB31_Pos      (31U)
4829 #define CAN_F7R2_FB31_Msk      (0x1UL << CAN_F7R2_FB31_Pos)                     /*!< 0x80000000 */
4830 #define CAN_F7R2_FB31          CAN_F7R2_FB31_Msk                               /*!<Filter bit 31 */
4831 
4832 /*******************  Bit definition for CAN_F8R2 register  *******************/
4833 #define CAN_F8R2_FB0_Pos       (0U)
4834 #define CAN_F8R2_FB0_Msk       (0x1UL << CAN_F8R2_FB0_Pos)                      /*!< 0x00000001 */
4835 #define CAN_F8R2_FB0           CAN_F8R2_FB0_Msk                                /*!<Filter bit 0 */
4836 #define CAN_F8R2_FB1_Pos       (1U)
4837 #define CAN_F8R2_FB1_Msk       (0x1UL << CAN_F8R2_FB1_Pos)                      /*!< 0x00000002 */
4838 #define CAN_F8R2_FB1           CAN_F8R2_FB1_Msk                                /*!<Filter bit 1 */
4839 #define CAN_F8R2_FB2_Pos       (2U)
4840 #define CAN_F8R2_FB2_Msk       (0x1UL << CAN_F8R2_FB2_Pos)                      /*!< 0x00000004 */
4841 #define CAN_F8R2_FB2           CAN_F8R2_FB2_Msk                                /*!<Filter bit 2 */
4842 #define CAN_F8R2_FB3_Pos       (3U)
4843 #define CAN_F8R2_FB3_Msk       (0x1UL << CAN_F8R2_FB3_Pos)                      /*!< 0x00000008 */
4844 #define CAN_F8R2_FB3           CAN_F8R2_FB3_Msk                                /*!<Filter bit 3 */
4845 #define CAN_F8R2_FB4_Pos       (4U)
4846 #define CAN_F8R2_FB4_Msk       (0x1UL << CAN_F8R2_FB4_Pos)                      /*!< 0x00000010 */
4847 #define CAN_F8R2_FB4           CAN_F8R2_FB4_Msk                                /*!<Filter bit 4 */
4848 #define CAN_F8R2_FB5_Pos       (5U)
4849 #define CAN_F8R2_FB5_Msk       (0x1UL << CAN_F8R2_FB5_Pos)                      /*!< 0x00000020 */
4850 #define CAN_F8R2_FB5           CAN_F8R2_FB5_Msk                                /*!<Filter bit 5 */
4851 #define CAN_F8R2_FB6_Pos       (6U)
4852 #define CAN_F8R2_FB6_Msk       (0x1UL << CAN_F8R2_FB6_Pos)                      /*!< 0x00000040 */
4853 #define CAN_F8R2_FB6           CAN_F8R2_FB6_Msk                                /*!<Filter bit 6 */
4854 #define CAN_F8R2_FB7_Pos       (7U)
4855 #define CAN_F8R2_FB7_Msk       (0x1UL << CAN_F8R2_FB7_Pos)                      /*!< 0x00000080 */
4856 #define CAN_F8R2_FB7           CAN_F8R2_FB7_Msk                                /*!<Filter bit 7 */
4857 #define CAN_F8R2_FB8_Pos       (8U)
4858 #define CAN_F8R2_FB8_Msk       (0x1UL << CAN_F8R2_FB8_Pos)                      /*!< 0x00000100 */
4859 #define CAN_F8R2_FB8           CAN_F8R2_FB8_Msk                                /*!<Filter bit 8 */
4860 #define CAN_F8R2_FB9_Pos       (9U)
4861 #define CAN_F8R2_FB9_Msk       (0x1UL << CAN_F8R2_FB9_Pos)                      /*!< 0x00000200 */
4862 #define CAN_F8R2_FB9           CAN_F8R2_FB9_Msk                                /*!<Filter bit 9 */
4863 #define CAN_F8R2_FB10_Pos      (10U)
4864 #define CAN_F8R2_FB10_Msk      (0x1UL << CAN_F8R2_FB10_Pos)                     /*!< 0x00000400 */
4865 #define CAN_F8R2_FB10          CAN_F8R2_FB10_Msk                               /*!<Filter bit 10 */
4866 #define CAN_F8R2_FB11_Pos      (11U)
4867 #define CAN_F8R2_FB11_Msk      (0x1UL << CAN_F8R2_FB11_Pos)                     /*!< 0x00000800 */
4868 #define CAN_F8R2_FB11          CAN_F8R2_FB11_Msk                               /*!<Filter bit 11 */
4869 #define CAN_F8R2_FB12_Pos      (12U)
4870 #define CAN_F8R2_FB12_Msk      (0x1UL << CAN_F8R2_FB12_Pos)                     /*!< 0x00001000 */
4871 #define CAN_F8R2_FB12          CAN_F8R2_FB12_Msk                               /*!<Filter bit 12 */
4872 #define CAN_F8R2_FB13_Pos      (13U)
4873 #define CAN_F8R2_FB13_Msk      (0x1UL << CAN_F8R2_FB13_Pos)                     /*!< 0x00002000 */
4874 #define CAN_F8R2_FB13          CAN_F8R2_FB13_Msk                               /*!<Filter bit 13 */
4875 #define CAN_F8R2_FB14_Pos      (14U)
4876 #define CAN_F8R2_FB14_Msk      (0x1UL << CAN_F8R2_FB14_Pos)                     /*!< 0x00004000 */
4877 #define CAN_F8R2_FB14          CAN_F8R2_FB14_Msk                               /*!<Filter bit 14 */
4878 #define CAN_F8R2_FB15_Pos      (15U)
4879 #define CAN_F8R2_FB15_Msk      (0x1UL << CAN_F8R2_FB15_Pos)                     /*!< 0x00008000 */
4880 #define CAN_F8R2_FB15          CAN_F8R2_FB15_Msk                               /*!<Filter bit 15 */
4881 #define CAN_F8R2_FB16_Pos      (16U)
4882 #define CAN_F8R2_FB16_Msk      (0x1UL << CAN_F8R2_FB16_Pos)                     /*!< 0x00010000 */
4883 #define CAN_F8R2_FB16          CAN_F8R2_FB16_Msk                               /*!<Filter bit 16 */
4884 #define CAN_F8R2_FB17_Pos      (17U)
4885 #define CAN_F8R2_FB17_Msk      (0x1UL << CAN_F8R2_FB17_Pos)                     /*!< 0x00020000 */
4886 #define CAN_F8R2_FB17          CAN_F8R2_FB17_Msk                               /*!<Filter bit 17 */
4887 #define CAN_F8R2_FB18_Pos      (18U)
4888 #define CAN_F8R2_FB18_Msk      (0x1UL << CAN_F8R2_FB18_Pos)                     /*!< 0x00040000 */
4889 #define CAN_F8R2_FB18          CAN_F8R2_FB18_Msk                               /*!<Filter bit 18 */
4890 #define CAN_F8R2_FB19_Pos      (19U)
4891 #define CAN_F8R2_FB19_Msk      (0x1UL << CAN_F8R2_FB19_Pos)                     /*!< 0x00080000 */
4892 #define CAN_F8R2_FB19          CAN_F8R2_FB19_Msk                               /*!<Filter bit 19 */
4893 #define CAN_F8R2_FB20_Pos      (20U)
4894 #define CAN_F8R2_FB20_Msk      (0x1UL << CAN_F8R2_FB20_Pos)                     /*!< 0x00100000 */
4895 #define CAN_F8R2_FB20          CAN_F8R2_FB20_Msk                               /*!<Filter bit 20 */
4896 #define CAN_F8R2_FB21_Pos      (21U)
4897 #define CAN_F8R2_FB21_Msk      (0x1UL << CAN_F8R2_FB21_Pos)                     /*!< 0x00200000 */
4898 #define CAN_F8R2_FB21          CAN_F8R2_FB21_Msk                               /*!<Filter bit 21 */
4899 #define CAN_F8R2_FB22_Pos      (22U)
4900 #define CAN_F8R2_FB22_Msk      (0x1UL << CAN_F8R2_FB22_Pos)                     /*!< 0x00400000 */
4901 #define CAN_F8R2_FB22          CAN_F8R2_FB22_Msk                               /*!<Filter bit 22 */
4902 #define CAN_F8R2_FB23_Pos      (23U)
4903 #define CAN_F8R2_FB23_Msk      (0x1UL << CAN_F8R2_FB23_Pos)                     /*!< 0x00800000 */
4904 #define CAN_F8R2_FB23          CAN_F8R2_FB23_Msk                               /*!<Filter bit 23 */
4905 #define CAN_F8R2_FB24_Pos      (24U)
4906 #define CAN_F8R2_FB24_Msk      (0x1UL << CAN_F8R2_FB24_Pos)                     /*!< 0x01000000 */
4907 #define CAN_F8R2_FB24          CAN_F8R2_FB24_Msk                               /*!<Filter bit 24 */
4908 #define CAN_F8R2_FB25_Pos      (25U)
4909 #define CAN_F8R2_FB25_Msk      (0x1UL << CAN_F8R2_FB25_Pos)                     /*!< 0x02000000 */
4910 #define CAN_F8R2_FB25          CAN_F8R2_FB25_Msk                               /*!<Filter bit 25 */
4911 #define CAN_F8R2_FB26_Pos      (26U)
4912 #define CAN_F8R2_FB26_Msk      (0x1UL << CAN_F8R2_FB26_Pos)                     /*!< 0x04000000 */
4913 #define CAN_F8R2_FB26          CAN_F8R2_FB26_Msk                               /*!<Filter bit 26 */
4914 #define CAN_F8R2_FB27_Pos      (27U)
4915 #define CAN_F8R2_FB27_Msk      (0x1UL << CAN_F8R2_FB27_Pos)                     /*!< 0x08000000 */
4916 #define CAN_F8R2_FB27          CAN_F8R2_FB27_Msk                               /*!<Filter bit 27 */
4917 #define CAN_F8R2_FB28_Pos      (28U)
4918 #define CAN_F8R2_FB28_Msk      (0x1UL << CAN_F8R2_FB28_Pos)                     /*!< 0x10000000 */
4919 #define CAN_F8R2_FB28          CAN_F8R2_FB28_Msk                               /*!<Filter bit 28 */
4920 #define CAN_F8R2_FB29_Pos      (29U)
4921 #define CAN_F8R2_FB29_Msk      (0x1UL << CAN_F8R2_FB29_Pos)                     /*!< 0x20000000 */
4922 #define CAN_F8R2_FB29          CAN_F8R2_FB29_Msk                               /*!<Filter bit 29 */
4923 #define CAN_F8R2_FB30_Pos      (30U)
4924 #define CAN_F8R2_FB30_Msk      (0x1UL << CAN_F8R2_FB30_Pos)                     /*!< 0x40000000 */
4925 #define CAN_F8R2_FB30          CAN_F8R2_FB30_Msk                               /*!<Filter bit 30 */
4926 #define CAN_F8R2_FB31_Pos      (31U)
4927 #define CAN_F8R2_FB31_Msk      (0x1UL << CAN_F8R2_FB31_Pos)                     /*!< 0x80000000 */
4928 #define CAN_F8R2_FB31          CAN_F8R2_FB31_Msk                               /*!<Filter bit 31 */
4929 
4930 /*******************  Bit definition for CAN_F9R2 register  *******************/
4931 #define CAN_F9R2_FB0_Pos       (0U)
4932 #define CAN_F9R2_FB0_Msk       (0x1UL << CAN_F9R2_FB0_Pos)                      /*!< 0x00000001 */
4933 #define CAN_F9R2_FB0           CAN_F9R2_FB0_Msk                                /*!<Filter bit 0 */
4934 #define CAN_F9R2_FB1_Pos       (1U)
4935 #define CAN_F9R2_FB1_Msk       (0x1UL << CAN_F9R2_FB1_Pos)                      /*!< 0x00000002 */
4936 #define CAN_F9R2_FB1           CAN_F9R2_FB1_Msk                                /*!<Filter bit 1 */
4937 #define CAN_F9R2_FB2_Pos       (2U)
4938 #define CAN_F9R2_FB2_Msk       (0x1UL << CAN_F9R2_FB2_Pos)                      /*!< 0x00000004 */
4939 #define CAN_F9R2_FB2           CAN_F9R2_FB2_Msk                                /*!<Filter bit 2 */
4940 #define CAN_F9R2_FB3_Pos       (3U)
4941 #define CAN_F9R2_FB3_Msk       (0x1UL << CAN_F9R2_FB3_Pos)                      /*!< 0x00000008 */
4942 #define CAN_F9R2_FB3           CAN_F9R2_FB3_Msk                                /*!<Filter bit 3 */
4943 #define CAN_F9R2_FB4_Pos       (4U)
4944 #define CAN_F9R2_FB4_Msk       (0x1UL << CAN_F9R2_FB4_Pos)                      /*!< 0x00000010 */
4945 #define CAN_F9R2_FB4           CAN_F9R2_FB4_Msk                                /*!<Filter bit 4 */
4946 #define CAN_F9R2_FB5_Pos       (5U)
4947 #define CAN_F9R2_FB5_Msk       (0x1UL << CAN_F9R2_FB5_Pos)                      /*!< 0x00000020 */
4948 #define CAN_F9R2_FB5           CAN_F9R2_FB5_Msk                                /*!<Filter bit 5 */
4949 #define CAN_F9R2_FB6_Pos       (6U)
4950 #define CAN_F9R2_FB6_Msk       (0x1UL << CAN_F9R2_FB6_Pos)                      /*!< 0x00000040 */
4951 #define CAN_F9R2_FB6           CAN_F9R2_FB6_Msk                                /*!<Filter bit 6 */
4952 #define CAN_F9R2_FB7_Pos       (7U)
4953 #define CAN_F9R2_FB7_Msk       (0x1UL << CAN_F9R2_FB7_Pos)                      /*!< 0x00000080 */
4954 #define CAN_F9R2_FB7           CAN_F9R2_FB7_Msk                                /*!<Filter bit 7 */
4955 #define CAN_F9R2_FB8_Pos       (8U)
4956 #define CAN_F9R2_FB8_Msk       (0x1UL << CAN_F9R2_FB8_Pos)                      /*!< 0x00000100 */
4957 #define CAN_F9R2_FB8           CAN_F9R2_FB8_Msk                                /*!<Filter bit 8 */
4958 #define CAN_F9R2_FB9_Pos       (9U)
4959 #define CAN_F9R2_FB9_Msk       (0x1UL << CAN_F9R2_FB9_Pos)                      /*!< 0x00000200 */
4960 #define CAN_F9R2_FB9           CAN_F9R2_FB9_Msk                                /*!<Filter bit 9 */
4961 #define CAN_F9R2_FB10_Pos      (10U)
4962 #define CAN_F9R2_FB10_Msk      (0x1UL << CAN_F9R2_FB10_Pos)                     /*!< 0x00000400 */
4963 #define CAN_F9R2_FB10          CAN_F9R2_FB10_Msk                               /*!<Filter bit 10 */
4964 #define CAN_F9R2_FB11_Pos      (11U)
4965 #define CAN_F9R2_FB11_Msk      (0x1UL << CAN_F9R2_FB11_Pos)                     /*!< 0x00000800 */
4966 #define CAN_F9R2_FB11          CAN_F9R2_FB11_Msk                               /*!<Filter bit 11 */
4967 #define CAN_F9R2_FB12_Pos      (12U)
4968 #define CAN_F9R2_FB12_Msk      (0x1UL << CAN_F9R2_FB12_Pos)                     /*!< 0x00001000 */
4969 #define CAN_F9R2_FB12          CAN_F9R2_FB12_Msk                               /*!<Filter bit 12 */
4970 #define CAN_F9R2_FB13_Pos      (13U)
4971 #define CAN_F9R2_FB13_Msk      (0x1UL << CAN_F9R2_FB13_Pos)                     /*!< 0x00002000 */
4972 #define CAN_F9R2_FB13          CAN_F9R2_FB13_Msk                               /*!<Filter bit 13 */
4973 #define CAN_F9R2_FB14_Pos      (14U)
4974 #define CAN_F9R2_FB14_Msk      (0x1UL << CAN_F9R2_FB14_Pos)                     /*!< 0x00004000 */
4975 #define CAN_F9R2_FB14          CAN_F9R2_FB14_Msk                               /*!<Filter bit 14 */
4976 #define CAN_F9R2_FB15_Pos      (15U)
4977 #define CAN_F9R2_FB15_Msk      (0x1UL << CAN_F9R2_FB15_Pos)                     /*!< 0x00008000 */
4978 #define CAN_F9R2_FB15          CAN_F9R2_FB15_Msk                               /*!<Filter bit 15 */
4979 #define CAN_F9R2_FB16_Pos      (16U)
4980 #define CAN_F9R2_FB16_Msk      (0x1UL << CAN_F9R2_FB16_Pos)                     /*!< 0x00010000 */
4981 #define CAN_F9R2_FB16          CAN_F9R2_FB16_Msk                               /*!<Filter bit 16 */
4982 #define CAN_F9R2_FB17_Pos      (17U)
4983 #define CAN_F9R2_FB17_Msk      (0x1UL << CAN_F9R2_FB17_Pos)                     /*!< 0x00020000 */
4984 #define CAN_F9R2_FB17          CAN_F9R2_FB17_Msk                               /*!<Filter bit 17 */
4985 #define CAN_F9R2_FB18_Pos      (18U)
4986 #define CAN_F9R2_FB18_Msk      (0x1UL << CAN_F9R2_FB18_Pos)                     /*!< 0x00040000 */
4987 #define CAN_F9R2_FB18          CAN_F9R2_FB18_Msk                               /*!<Filter bit 18 */
4988 #define CAN_F9R2_FB19_Pos      (19U)
4989 #define CAN_F9R2_FB19_Msk      (0x1UL << CAN_F9R2_FB19_Pos)                     /*!< 0x00080000 */
4990 #define CAN_F9R2_FB19          CAN_F9R2_FB19_Msk                               /*!<Filter bit 19 */
4991 #define CAN_F9R2_FB20_Pos      (20U)
4992 #define CAN_F9R2_FB20_Msk      (0x1UL << CAN_F9R2_FB20_Pos)                     /*!< 0x00100000 */
4993 #define CAN_F9R2_FB20          CAN_F9R2_FB20_Msk                               /*!<Filter bit 20 */
4994 #define CAN_F9R2_FB21_Pos      (21U)
4995 #define CAN_F9R2_FB21_Msk      (0x1UL << CAN_F9R2_FB21_Pos)                     /*!< 0x00200000 */
4996 #define CAN_F9R2_FB21          CAN_F9R2_FB21_Msk                               /*!<Filter bit 21 */
4997 #define CAN_F9R2_FB22_Pos      (22U)
4998 #define CAN_F9R2_FB22_Msk      (0x1UL << CAN_F9R2_FB22_Pos)                     /*!< 0x00400000 */
4999 #define CAN_F9R2_FB22          CAN_F9R2_FB22_Msk                               /*!<Filter bit 22 */
5000 #define CAN_F9R2_FB23_Pos      (23U)
5001 #define CAN_F9R2_FB23_Msk      (0x1UL << CAN_F9R2_FB23_Pos)                     /*!< 0x00800000 */
5002 #define CAN_F9R2_FB23          CAN_F9R2_FB23_Msk                               /*!<Filter bit 23 */
5003 #define CAN_F9R2_FB24_Pos      (24U)
5004 #define CAN_F9R2_FB24_Msk      (0x1UL << CAN_F9R2_FB24_Pos)                     /*!< 0x01000000 */
5005 #define CAN_F9R2_FB24          CAN_F9R2_FB24_Msk                               /*!<Filter bit 24 */
5006 #define CAN_F9R2_FB25_Pos      (25U)
5007 #define CAN_F9R2_FB25_Msk      (0x1UL << CAN_F9R2_FB25_Pos)                     /*!< 0x02000000 */
5008 #define CAN_F9R2_FB25          CAN_F9R2_FB25_Msk                               /*!<Filter bit 25 */
5009 #define CAN_F9R2_FB26_Pos      (26U)
5010 #define CAN_F9R2_FB26_Msk      (0x1UL << CAN_F9R2_FB26_Pos)                     /*!< 0x04000000 */
5011 #define CAN_F9R2_FB26          CAN_F9R2_FB26_Msk                               /*!<Filter bit 26 */
5012 #define CAN_F9R2_FB27_Pos      (27U)
5013 #define CAN_F9R2_FB27_Msk      (0x1UL << CAN_F9R2_FB27_Pos)                     /*!< 0x08000000 */
5014 #define CAN_F9R2_FB27          CAN_F9R2_FB27_Msk                               /*!<Filter bit 27 */
5015 #define CAN_F9R2_FB28_Pos      (28U)
5016 #define CAN_F9R2_FB28_Msk      (0x1UL << CAN_F9R2_FB28_Pos)                     /*!< 0x10000000 */
5017 #define CAN_F9R2_FB28          CAN_F9R2_FB28_Msk                               /*!<Filter bit 28 */
5018 #define CAN_F9R2_FB29_Pos      (29U)
5019 #define CAN_F9R2_FB29_Msk      (0x1UL << CAN_F9R2_FB29_Pos)                     /*!< 0x20000000 */
5020 #define CAN_F9R2_FB29          CAN_F9R2_FB29_Msk                               /*!<Filter bit 29 */
5021 #define CAN_F9R2_FB30_Pos      (30U)
5022 #define CAN_F9R2_FB30_Msk      (0x1UL << CAN_F9R2_FB30_Pos)                     /*!< 0x40000000 */
5023 #define CAN_F9R2_FB30          CAN_F9R2_FB30_Msk                               /*!<Filter bit 30 */
5024 #define CAN_F9R2_FB31_Pos      (31U)
5025 #define CAN_F9R2_FB31_Msk      (0x1UL << CAN_F9R2_FB31_Pos)                     /*!< 0x80000000 */
5026 #define CAN_F9R2_FB31          CAN_F9R2_FB31_Msk                               /*!<Filter bit 31 */
5027 
5028 /*******************  Bit definition for CAN_F10R2 register  ******************/
5029 #define CAN_F10R2_FB0_Pos      (0U)
5030 #define CAN_F10R2_FB0_Msk      (0x1UL << CAN_F10R2_FB0_Pos)                     /*!< 0x00000001 */
5031 #define CAN_F10R2_FB0          CAN_F10R2_FB0_Msk                               /*!<Filter bit 0 */
5032 #define CAN_F10R2_FB1_Pos      (1U)
5033 #define CAN_F10R2_FB1_Msk      (0x1UL << CAN_F10R2_FB1_Pos)                     /*!< 0x00000002 */
5034 #define CAN_F10R2_FB1          CAN_F10R2_FB1_Msk                               /*!<Filter bit 1 */
5035 #define CAN_F10R2_FB2_Pos      (2U)
5036 #define CAN_F10R2_FB2_Msk      (0x1UL << CAN_F10R2_FB2_Pos)                     /*!< 0x00000004 */
5037 #define CAN_F10R2_FB2          CAN_F10R2_FB2_Msk                               /*!<Filter bit 2 */
5038 #define CAN_F10R2_FB3_Pos      (3U)
5039 #define CAN_F10R2_FB3_Msk      (0x1UL << CAN_F10R2_FB3_Pos)                     /*!< 0x00000008 */
5040 #define CAN_F10R2_FB3          CAN_F10R2_FB3_Msk                               /*!<Filter bit 3 */
5041 #define CAN_F10R2_FB4_Pos      (4U)
5042 #define CAN_F10R2_FB4_Msk      (0x1UL << CAN_F10R2_FB4_Pos)                     /*!< 0x00000010 */
5043 #define CAN_F10R2_FB4          CAN_F10R2_FB4_Msk                               /*!<Filter bit 4 */
5044 #define CAN_F10R2_FB5_Pos      (5U)
5045 #define CAN_F10R2_FB5_Msk      (0x1UL << CAN_F10R2_FB5_Pos)                     /*!< 0x00000020 */
5046 #define CAN_F10R2_FB5          CAN_F10R2_FB5_Msk                               /*!<Filter bit 5 */
5047 #define CAN_F10R2_FB6_Pos      (6U)
5048 #define CAN_F10R2_FB6_Msk      (0x1UL << CAN_F10R2_FB6_Pos)                     /*!< 0x00000040 */
5049 #define CAN_F10R2_FB6          CAN_F10R2_FB6_Msk                               /*!<Filter bit 6 */
5050 #define CAN_F10R2_FB7_Pos      (7U)
5051 #define CAN_F10R2_FB7_Msk      (0x1UL << CAN_F10R2_FB7_Pos)                     /*!< 0x00000080 */
5052 #define CAN_F10R2_FB7          CAN_F10R2_FB7_Msk                               /*!<Filter bit 7 */
5053 #define CAN_F10R2_FB8_Pos      (8U)
5054 #define CAN_F10R2_FB8_Msk      (0x1UL << CAN_F10R2_FB8_Pos)                     /*!< 0x00000100 */
5055 #define CAN_F10R2_FB8          CAN_F10R2_FB8_Msk                               /*!<Filter bit 8 */
5056 #define CAN_F10R2_FB9_Pos      (9U)
5057 #define CAN_F10R2_FB9_Msk      (0x1UL << CAN_F10R2_FB9_Pos)                     /*!< 0x00000200 */
5058 #define CAN_F10R2_FB9          CAN_F10R2_FB9_Msk                               /*!<Filter bit 9 */
5059 #define CAN_F10R2_FB10_Pos     (10U)
5060 #define CAN_F10R2_FB10_Msk     (0x1UL << CAN_F10R2_FB10_Pos)                    /*!< 0x00000400 */
5061 #define CAN_F10R2_FB10         CAN_F10R2_FB10_Msk                              /*!<Filter bit 10 */
5062 #define CAN_F10R2_FB11_Pos     (11U)
5063 #define CAN_F10R2_FB11_Msk     (0x1UL << CAN_F10R2_FB11_Pos)                    /*!< 0x00000800 */
5064 #define CAN_F10R2_FB11         CAN_F10R2_FB11_Msk                              /*!<Filter bit 11 */
5065 #define CAN_F10R2_FB12_Pos     (12U)
5066 #define CAN_F10R2_FB12_Msk     (0x1UL << CAN_F10R2_FB12_Pos)                    /*!< 0x00001000 */
5067 #define CAN_F10R2_FB12         CAN_F10R2_FB12_Msk                              /*!<Filter bit 12 */
5068 #define CAN_F10R2_FB13_Pos     (13U)
5069 #define CAN_F10R2_FB13_Msk     (0x1UL << CAN_F10R2_FB13_Pos)                    /*!< 0x00002000 */
5070 #define CAN_F10R2_FB13         CAN_F10R2_FB13_Msk                              /*!<Filter bit 13 */
5071 #define CAN_F10R2_FB14_Pos     (14U)
5072 #define CAN_F10R2_FB14_Msk     (0x1UL << CAN_F10R2_FB14_Pos)                    /*!< 0x00004000 */
5073 #define CAN_F10R2_FB14         CAN_F10R2_FB14_Msk                              /*!<Filter bit 14 */
5074 #define CAN_F10R2_FB15_Pos     (15U)
5075 #define CAN_F10R2_FB15_Msk     (0x1UL << CAN_F10R2_FB15_Pos)                    /*!< 0x00008000 */
5076 #define CAN_F10R2_FB15         CAN_F10R2_FB15_Msk                              /*!<Filter bit 15 */
5077 #define CAN_F10R2_FB16_Pos     (16U)
5078 #define CAN_F10R2_FB16_Msk     (0x1UL << CAN_F10R2_FB16_Pos)                    /*!< 0x00010000 */
5079 #define CAN_F10R2_FB16         CAN_F10R2_FB16_Msk                              /*!<Filter bit 16 */
5080 #define CAN_F10R2_FB17_Pos     (17U)
5081 #define CAN_F10R2_FB17_Msk     (0x1UL << CAN_F10R2_FB17_Pos)                    /*!< 0x00020000 */
5082 #define CAN_F10R2_FB17         CAN_F10R2_FB17_Msk                              /*!<Filter bit 17 */
5083 #define CAN_F10R2_FB18_Pos     (18U)
5084 #define CAN_F10R2_FB18_Msk     (0x1UL << CAN_F10R2_FB18_Pos)                    /*!< 0x00040000 */
5085 #define CAN_F10R2_FB18         CAN_F10R2_FB18_Msk                              /*!<Filter bit 18 */
5086 #define CAN_F10R2_FB19_Pos     (19U)
5087 #define CAN_F10R2_FB19_Msk     (0x1UL << CAN_F10R2_FB19_Pos)                    /*!< 0x00080000 */
5088 #define CAN_F10R2_FB19         CAN_F10R2_FB19_Msk                              /*!<Filter bit 19 */
5089 #define CAN_F10R2_FB20_Pos     (20U)
5090 #define CAN_F10R2_FB20_Msk     (0x1UL << CAN_F10R2_FB20_Pos)                    /*!< 0x00100000 */
5091 #define CAN_F10R2_FB20         CAN_F10R2_FB20_Msk                              /*!<Filter bit 20 */
5092 #define CAN_F10R2_FB21_Pos     (21U)
5093 #define CAN_F10R2_FB21_Msk     (0x1UL << CAN_F10R2_FB21_Pos)                    /*!< 0x00200000 */
5094 #define CAN_F10R2_FB21         CAN_F10R2_FB21_Msk                              /*!<Filter bit 21 */
5095 #define CAN_F10R2_FB22_Pos     (22U)
5096 #define CAN_F10R2_FB22_Msk     (0x1UL << CAN_F10R2_FB22_Pos)                    /*!< 0x00400000 */
5097 #define CAN_F10R2_FB22         CAN_F10R2_FB22_Msk                              /*!<Filter bit 22 */
5098 #define CAN_F10R2_FB23_Pos     (23U)
5099 #define CAN_F10R2_FB23_Msk     (0x1UL << CAN_F10R2_FB23_Pos)                    /*!< 0x00800000 */
5100 #define CAN_F10R2_FB23         CAN_F10R2_FB23_Msk                              /*!<Filter bit 23 */
5101 #define CAN_F10R2_FB24_Pos     (24U)
5102 #define CAN_F10R2_FB24_Msk     (0x1UL << CAN_F10R2_FB24_Pos)                    /*!< 0x01000000 */
5103 #define CAN_F10R2_FB24         CAN_F10R2_FB24_Msk                              /*!<Filter bit 24 */
5104 #define CAN_F10R2_FB25_Pos     (25U)
5105 #define CAN_F10R2_FB25_Msk     (0x1UL << CAN_F10R2_FB25_Pos)                    /*!< 0x02000000 */
5106 #define CAN_F10R2_FB25         CAN_F10R2_FB25_Msk                              /*!<Filter bit 25 */
5107 #define CAN_F10R2_FB26_Pos     (26U)
5108 #define CAN_F10R2_FB26_Msk     (0x1UL << CAN_F10R2_FB26_Pos)                    /*!< 0x04000000 */
5109 #define CAN_F10R2_FB26         CAN_F10R2_FB26_Msk                              /*!<Filter bit 26 */
5110 #define CAN_F10R2_FB27_Pos     (27U)
5111 #define CAN_F10R2_FB27_Msk     (0x1UL << CAN_F10R2_FB27_Pos)                    /*!< 0x08000000 */
5112 #define CAN_F10R2_FB27         CAN_F10R2_FB27_Msk                              /*!<Filter bit 27 */
5113 #define CAN_F10R2_FB28_Pos     (28U)
5114 #define CAN_F10R2_FB28_Msk     (0x1UL << CAN_F10R2_FB28_Pos)                    /*!< 0x10000000 */
5115 #define CAN_F10R2_FB28         CAN_F10R2_FB28_Msk                              /*!<Filter bit 28 */
5116 #define CAN_F10R2_FB29_Pos     (29U)
5117 #define CAN_F10R2_FB29_Msk     (0x1UL << CAN_F10R2_FB29_Pos)                    /*!< 0x20000000 */
5118 #define CAN_F10R2_FB29         CAN_F10R2_FB29_Msk                              /*!<Filter bit 29 */
5119 #define CAN_F10R2_FB30_Pos     (30U)
5120 #define CAN_F10R2_FB30_Msk     (0x1UL << CAN_F10R2_FB30_Pos)                    /*!< 0x40000000 */
5121 #define CAN_F10R2_FB30         CAN_F10R2_FB30_Msk                              /*!<Filter bit 30 */
5122 #define CAN_F10R2_FB31_Pos     (31U)
5123 #define CAN_F10R2_FB31_Msk     (0x1UL << CAN_F10R2_FB31_Pos)                    /*!< 0x80000000 */
5124 #define CAN_F10R2_FB31         CAN_F10R2_FB31_Msk                              /*!<Filter bit 31 */
5125 
5126 /*******************  Bit definition for CAN_F11R2 register  ******************/
5127 #define CAN_F11R2_FB0_Pos      (0U)
5128 #define CAN_F11R2_FB0_Msk      (0x1UL << CAN_F11R2_FB0_Pos)                     /*!< 0x00000001 */
5129 #define CAN_F11R2_FB0          CAN_F11R2_FB0_Msk                               /*!<Filter bit 0 */
5130 #define CAN_F11R2_FB1_Pos      (1U)
5131 #define CAN_F11R2_FB1_Msk      (0x1UL << CAN_F11R2_FB1_Pos)                     /*!< 0x00000002 */
5132 #define CAN_F11R2_FB1          CAN_F11R2_FB1_Msk                               /*!<Filter bit 1 */
5133 #define CAN_F11R2_FB2_Pos      (2U)
5134 #define CAN_F11R2_FB2_Msk      (0x1UL << CAN_F11R2_FB2_Pos)                     /*!< 0x00000004 */
5135 #define CAN_F11R2_FB2          CAN_F11R2_FB2_Msk                               /*!<Filter bit 2 */
5136 #define CAN_F11R2_FB3_Pos      (3U)
5137 #define CAN_F11R2_FB3_Msk      (0x1UL << CAN_F11R2_FB3_Pos)                     /*!< 0x00000008 */
5138 #define CAN_F11R2_FB3          CAN_F11R2_FB3_Msk                               /*!<Filter bit 3 */
5139 #define CAN_F11R2_FB4_Pos      (4U)
5140 #define CAN_F11R2_FB4_Msk      (0x1UL << CAN_F11R2_FB4_Pos)                     /*!< 0x00000010 */
5141 #define CAN_F11R2_FB4          CAN_F11R2_FB4_Msk                               /*!<Filter bit 4 */
5142 #define CAN_F11R2_FB5_Pos      (5U)
5143 #define CAN_F11R2_FB5_Msk      (0x1UL << CAN_F11R2_FB5_Pos)                     /*!< 0x00000020 */
5144 #define CAN_F11R2_FB5          CAN_F11R2_FB5_Msk                               /*!<Filter bit 5 */
5145 #define CAN_F11R2_FB6_Pos      (6U)
5146 #define CAN_F11R2_FB6_Msk      (0x1UL << CAN_F11R2_FB6_Pos)                     /*!< 0x00000040 */
5147 #define CAN_F11R2_FB6          CAN_F11R2_FB6_Msk                               /*!<Filter bit 6 */
5148 #define CAN_F11R2_FB7_Pos      (7U)
5149 #define CAN_F11R2_FB7_Msk      (0x1UL << CAN_F11R2_FB7_Pos)                     /*!< 0x00000080 */
5150 #define CAN_F11R2_FB7          CAN_F11R2_FB7_Msk                               /*!<Filter bit 7 */
5151 #define CAN_F11R2_FB8_Pos      (8U)
5152 #define CAN_F11R2_FB8_Msk      (0x1UL << CAN_F11R2_FB8_Pos)                     /*!< 0x00000100 */
5153 #define CAN_F11R2_FB8          CAN_F11R2_FB8_Msk                               /*!<Filter bit 8 */
5154 #define CAN_F11R2_FB9_Pos      (9U)
5155 #define CAN_F11R2_FB9_Msk      (0x1UL << CAN_F11R2_FB9_Pos)                     /*!< 0x00000200 */
5156 #define CAN_F11R2_FB9          CAN_F11R2_FB9_Msk                               /*!<Filter bit 9 */
5157 #define CAN_F11R2_FB10_Pos     (10U)
5158 #define CAN_F11R2_FB10_Msk     (0x1UL << CAN_F11R2_FB10_Pos)                    /*!< 0x00000400 */
5159 #define CAN_F11R2_FB10         CAN_F11R2_FB10_Msk                              /*!<Filter bit 10 */
5160 #define CAN_F11R2_FB11_Pos     (11U)
5161 #define CAN_F11R2_FB11_Msk     (0x1UL << CAN_F11R2_FB11_Pos)                    /*!< 0x00000800 */
5162 #define CAN_F11R2_FB11         CAN_F11R2_FB11_Msk                              /*!<Filter bit 11 */
5163 #define CAN_F11R2_FB12_Pos     (12U)
5164 #define CAN_F11R2_FB12_Msk     (0x1UL << CAN_F11R2_FB12_Pos)                    /*!< 0x00001000 */
5165 #define CAN_F11R2_FB12         CAN_F11R2_FB12_Msk                              /*!<Filter bit 12 */
5166 #define CAN_F11R2_FB13_Pos     (13U)
5167 #define CAN_F11R2_FB13_Msk     (0x1UL << CAN_F11R2_FB13_Pos)                    /*!< 0x00002000 */
5168 #define CAN_F11R2_FB13         CAN_F11R2_FB13_Msk                              /*!<Filter bit 13 */
5169 #define CAN_F11R2_FB14_Pos     (14U)
5170 #define CAN_F11R2_FB14_Msk     (0x1UL << CAN_F11R2_FB14_Pos)                    /*!< 0x00004000 */
5171 #define CAN_F11R2_FB14         CAN_F11R2_FB14_Msk                              /*!<Filter bit 14 */
5172 #define CAN_F11R2_FB15_Pos     (15U)
5173 #define CAN_F11R2_FB15_Msk     (0x1UL << CAN_F11R2_FB15_Pos)                    /*!< 0x00008000 */
5174 #define CAN_F11R2_FB15         CAN_F11R2_FB15_Msk                              /*!<Filter bit 15 */
5175 #define CAN_F11R2_FB16_Pos     (16U)
5176 #define CAN_F11R2_FB16_Msk     (0x1UL << CAN_F11R2_FB16_Pos)                    /*!< 0x00010000 */
5177 #define CAN_F11R2_FB16         CAN_F11R2_FB16_Msk                              /*!<Filter bit 16 */
5178 #define CAN_F11R2_FB17_Pos     (17U)
5179 #define CAN_F11R2_FB17_Msk     (0x1UL << CAN_F11R2_FB17_Pos)                    /*!< 0x00020000 */
5180 #define CAN_F11R2_FB17         CAN_F11R2_FB17_Msk                              /*!<Filter bit 17 */
5181 #define CAN_F11R2_FB18_Pos     (18U)
5182 #define CAN_F11R2_FB18_Msk     (0x1UL << CAN_F11R2_FB18_Pos)                    /*!< 0x00040000 */
5183 #define CAN_F11R2_FB18         CAN_F11R2_FB18_Msk                              /*!<Filter bit 18 */
5184 #define CAN_F11R2_FB19_Pos     (19U)
5185 #define CAN_F11R2_FB19_Msk     (0x1UL << CAN_F11R2_FB19_Pos)                    /*!< 0x00080000 */
5186 #define CAN_F11R2_FB19         CAN_F11R2_FB19_Msk                              /*!<Filter bit 19 */
5187 #define CAN_F11R2_FB20_Pos     (20U)
5188 #define CAN_F11R2_FB20_Msk     (0x1UL << CAN_F11R2_FB20_Pos)                    /*!< 0x00100000 */
5189 #define CAN_F11R2_FB20         CAN_F11R2_FB20_Msk                              /*!<Filter bit 20 */
5190 #define CAN_F11R2_FB21_Pos     (21U)
5191 #define CAN_F11R2_FB21_Msk     (0x1UL << CAN_F11R2_FB21_Pos)                    /*!< 0x00200000 */
5192 #define CAN_F11R2_FB21         CAN_F11R2_FB21_Msk                              /*!<Filter bit 21 */
5193 #define CAN_F11R2_FB22_Pos     (22U)
5194 #define CAN_F11R2_FB22_Msk     (0x1UL << CAN_F11R2_FB22_Pos)                    /*!< 0x00400000 */
5195 #define CAN_F11R2_FB22         CAN_F11R2_FB22_Msk                              /*!<Filter bit 22 */
5196 #define CAN_F11R2_FB23_Pos     (23U)
5197 #define CAN_F11R2_FB23_Msk     (0x1UL << CAN_F11R2_FB23_Pos)                    /*!< 0x00800000 */
5198 #define CAN_F11R2_FB23         CAN_F11R2_FB23_Msk                              /*!<Filter bit 23 */
5199 #define CAN_F11R2_FB24_Pos     (24U)
5200 #define CAN_F11R2_FB24_Msk     (0x1UL << CAN_F11R2_FB24_Pos)                    /*!< 0x01000000 */
5201 #define CAN_F11R2_FB24         CAN_F11R2_FB24_Msk                              /*!<Filter bit 24 */
5202 #define CAN_F11R2_FB25_Pos     (25U)
5203 #define CAN_F11R2_FB25_Msk     (0x1UL << CAN_F11R2_FB25_Pos)                    /*!< 0x02000000 */
5204 #define CAN_F11R2_FB25         CAN_F11R2_FB25_Msk                              /*!<Filter bit 25 */
5205 #define CAN_F11R2_FB26_Pos     (26U)
5206 #define CAN_F11R2_FB26_Msk     (0x1UL << CAN_F11R2_FB26_Pos)                    /*!< 0x04000000 */
5207 #define CAN_F11R2_FB26         CAN_F11R2_FB26_Msk                              /*!<Filter bit 26 */
5208 #define CAN_F11R2_FB27_Pos     (27U)
5209 #define CAN_F11R2_FB27_Msk     (0x1UL << CAN_F11R2_FB27_Pos)                    /*!< 0x08000000 */
5210 #define CAN_F11R2_FB27         CAN_F11R2_FB27_Msk                              /*!<Filter bit 27 */
5211 #define CAN_F11R2_FB28_Pos     (28U)
5212 #define CAN_F11R2_FB28_Msk     (0x1UL << CAN_F11R2_FB28_Pos)                    /*!< 0x10000000 */
5213 #define CAN_F11R2_FB28         CAN_F11R2_FB28_Msk                              /*!<Filter bit 28 */
5214 #define CAN_F11R2_FB29_Pos     (29U)
5215 #define CAN_F11R2_FB29_Msk     (0x1UL << CAN_F11R2_FB29_Pos)                    /*!< 0x20000000 */
5216 #define CAN_F11R2_FB29         CAN_F11R2_FB29_Msk                              /*!<Filter bit 29 */
5217 #define CAN_F11R2_FB30_Pos     (30U)
5218 #define CAN_F11R2_FB30_Msk     (0x1UL << CAN_F11R2_FB30_Pos)                    /*!< 0x40000000 */
5219 #define CAN_F11R2_FB30         CAN_F11R2_FB30_Msk                              /*!<Filter bit 30 */
5220 #define CAN_F11R2_FB31_Pos     (31U)
5221 #define CAN_F11R2_FB31_Msk     (0x1UL << CAN_F11R2_FB31_Pos)                    /*!< 0x80000000 */
5222 #define CAN_F11R2_FB31         CAN_F11R2_FB31_Msk                              /*!<Filter bit 31 */
5223 
5224 /*******************  Bit definition for CAN_F12R2 register  ******************/
5225 #define CAN_F12R2_FB0_Pos      (0U)
5226 #define CAN_F12R2_FB0_Msk      (0x1UL << CAN_F12R2_FB0_Pos)                     /*!< 0x00000001 */
5227 #define CAN_F12R2_FB0          CAN_F12R2_FB0_Msk                               /*!<Filter bit 0 */
5228 #define CAN_F12R2_FB1_Pos      (1U)
5229 #define CAN_F12R2_FB1_Msk      (0x1UL << CAN_F12R2_FB1_Pos)                     /*!< 0x00000002 */
5230 #define CAN_F12R2_FB1          CAN_F12R2_FB1_Msk                               /*!<Filter bit 1 */
5231 #define CAN_F12R2_FB2_Pos      (2U)
5232 #define CAN_F12R2_FB2_Msk      (0x1UL << CAN_F12R2_FB2_Pos)                     /*!< 0x00000004 */
5233 #define CAN_F12R2_FB2          CAN_F12R2_FB2_Msk                               /*!<Filter bit 2 */
5234 #define CAN_F12R2_FB3_Pos      (3U)
5235 #define CAN_F12R2_FB3_Msk      (0x1UL << CAN_F12R2_FB3_Pos)                     /*!< 0x00000008 */
5236 #define CAN_F12R2_FB3          CAN_F12R2_FB3_Msk                               /*!<Filter bit 3 */
5237 #define CAN_F12R2_FB4_Pos      (4U)
5238 #define CAN_F12R2_FB4_Msk      (0x1UL << CAN_F12R2_FB4_Pos)                     /*!< 0x00000010 */
5239 #define CAN_F12R2_FB4          CAN_F12R2_FB4_Msk                               /*!<Filter bit 4 */
5240 #define CAN_F12R2_FB5_Pos      (5U)
5241 #define CAN_F12R2_FB5_Msk      (0x1UL << CAN_F12R2_FB5_Pos)                     /*!< 0x00000020 */
5242 #define CAN_F12R2_FB5          CAN_F12R2_FB5_Msk                               /*!<Filter bit 5 */
5243 #define CAN_F12R2_FB6_Pos      (6U)
5244 #define CAN_F12R2_FB6_Msk      (0x1UL << CAN_F12R2_FB6_Pos)                     /*!< 0x00000040 */
5245 #define CAN_F12R2_FB6          CAN_F12R2_FB6_Msk                               /*!<Filter bit 6 */
5246 #define CAN_F12R2_FB7_Pos      (7U)
5247 #define CAN_F12R2_FB7_Msk      (0x1UL << CAN_F12R2_FB7_Pos)                     /*!< 0x00000080 */
5248 #define CAN_F12R2_FB7          CAN_F12R2_FB7_Msk                               /*!<Filter bit 7 */
5249 #define CAN_F12R2_FB8_Pos      (8U)
5250 #define CAN_F12R2_FB8_Msk      (0x1UL << CAN_F12R2_FB8_Pos)                     /*!< 0x00000100 */
5251 #define CAN_F12R2_FB8          CAN_F12R2_FB8_Msk                               /*!<Filter bit 8 */
5252 #define CAN_F12R2_FB9_Pos      (9U)
5253 #define CAN_F12R2_FB9_Msk      (0x1UL << CAN_F12R2_FB9_Pos)                     /*!< 0x00000200 */
5254 #define CAN_F12R2_FB9          CAN_F12R2_FB9_Msk                               /*!<Filter bit 9 */
5255 #define CAN_F12R2_FB10_Pos     (10U)
5256 #define CAN_F12R2_FB10_Msk     (0x1UL << CAN_F12R2_FB10_Pos)                    /*!< 0x00000400 */
5257 #define CAN_F12R2_FB10         CAN_F12R2_FB10_Msk                              /*!<Filter bit 10 */
5258 #define CAN_F12R2_FB11_Pos     (11U)
5259 #define CAN_F12R2_FB11_Msk     (0x1UL << CAN_F12R2_FB11_Pos)                    /*!< 0x00000800 */
5260 #define CAN_F12R2_FB11         CAN_F12R2_FB11_Msk                              /*!<Filter bit 11 */
5261 #define CAN_F12R2_FB12_Pos     (12U)
5262 #define CAN_F12R2_FB12_Msk     (0x1UL << CAN_F12R2_FB12_Pos)                    /*!< 0x00001000 */
5263 #define CAN_F12R2_FB12         CAN_F12R2_FB12_Msk                              /*!<Filter bit 12 */
5264 #define CAN_F12R2_FB13_Pos     (13U)
5265 #define CAN_F12R2_FB13_Msk     (0x1UL << CAN_F12R2_FB13_Pos)                    /*!< 0x00002000 */
5266 #define CAN_F12R2_FB13         CAN_F12R2_FB13_Msk                              /*!<Filter bit 13 */
5267 #define CAN_F12R2_FB14_Pos     (14U)
5268 #define CAN_F12R2_FB14_Msk     (0x1UL << CAN_F12R2_FB14_Pos)                    /*!< 0x00004000 */
5269 #define CAN_F12R2_FB14         CAN_F12R2_FB14_Msk                              /*!<Filter bit 14 */
5270 #define CAN_F12R2_FB15_Pos     (15U)
5271 #define CAN_F12R2_FB15_Msk     (0x1UL << CAN_F12R2_FB15_Pos)                    /*!< 0x00008000 */
5272 #define CAN_F12R2_FB15         CAN_F12R2_FB15_Msk                              /*!<Filter bit 15 */
5273 #define CAN_F12R2_FB16_Pos     (16U)
5274 #define CAN_F12R2_FB16_Msk     (0x1UL << CAN_F12R2_FB16_Pos)                    /*!< 0x00010000 */
5275 #define CAN_F12R2_FB16         CAN_F12R2_FB16_Msk                              /*!<Filter bit 16 */
5276 #define CAN_F12R2_FB17_Pos     (17U)
5277 #define CAN_F12R2_FB17_Msk     (0x1UL << CAN_F12R2_FB17_Pos)                    /*!< 0x00020000 */
5278 #define CAN_F12R2_FB17         CAN_F12R2_FB17_Msk                              /*!<Filter bit 17 */
5279 #define CAN_F12R2_FB18_Pos     (18U)
5280 #define CAN_F12R2_FB18_Msk     (0x1UL << CAN_F12R2_FB18_Pos)                    /*!< 0x00040000 */
5281 #define CAN_F12R2_FB18         CAN_F12R2_FB18_Msk                              /*!<Filter bit 18 */
5282 #define CAN_F12R2_FB19_Pos     (19U)
5283 #define CAN_F12R2_FB19_Msk     (0x1UL << CAN_F12R2_FB19_Pos)                    /*!< 0x00080000 */
5284 #define CAN_F12R2_FB19         CAN_F12R2_FB19_Msk                              /*!<Filter bit 19 */
5285 #define CAN_F12R2_FB20_Pos     (20U)
5286 #define CAN_F12R2_FB20_Msk     (0x1UL << CAN_F12R2_FB20_Pos)                    /*!< 0x00100000 */
5287 #define CAN_F12R2_FB20         CAN_F12R2_FB20_Msk                              /*!<Filter bit 20 */
5288 #define CAN_F12R2_FB21_Pos     (21U)
5289 #define CAN_F12R2_FB21_Msk     (0x1UL << CAN_F12R2_FB21_Pos)                    /*!< 0x00200000 */
5290 #define CAN_F12R2_FB21         CAN_F12R2_FB21_Msk                              /*!<Filter bit 21 */
5291 #define CAN_F12R2_FB22_Pos     (22U)
5292 #define CAN_F12R2_FB22_Msk     (0x1UL << CAN_F12R2_FB22_Pos)                    /*!< 0x00400000 */
5293 #define CAN_F12R2_FB22         CAN_F12R2_FB22_Msk                              /*!<Filter bit 22 */
5294 #define CAN_F12R2_FB23_Pos     (23U)
5295 #define CAN_F12R2_FB23_Msk     (0x1UL << CAN_F12R2_FB23_Pos)                    /*!< 0x00800000 */
5296 #define CAN_F12R2_FB23         CAN_F12R2_FB23_Msk                              /*!<Filter bit 23 */
5297 #define CAN_F12R2_FB24_Pos     (24U)
5298 #define CAN_F12R2_FB24_Msk     (0x1UL << CAN_F12R2_FB24_Pos)                    /*!< 0x01000000 */
5299 #define CAN_F12R2_FB24         CAN_F12R2_FB24_Msk                              /*!<Filter bit 24 */
5300 #define CAN_F12R2_FB25_Pos     (25U)
5301 #define CAN_F12R2_FB25_Msk     (0x1UL << CAN_F12R2_FB25_Pos)                    /*!< 0x02000000 */
5302 #define CAN_F12R2_FB25         CAN_F12R2_FB25_Msk                              /*!<Filter bit 25 */
5303 #define CAN_F12R2_FB26_Pos     (26U)
5304 #define CAN_F12R2_FB26_Msk     (0x1UL << CAN_F12R2_FB26_Pos)                    /*!< 0x04000000 */
5305 #define CAN_F12R2_FB26         CAN_F12R2_FB26_Msk                              /*!<Filter bit 26 */
5306 #define CAN_F12R2_FB27_Pos     (27U)
5307 #define CAN_F12R2_FB27_Msk     (0x1UL << CAN_F12R2_FB27_Pos)                    /*!< 0x08000000 */
5308 #define CAN_F12R2_FB27         CAN_F12R2_FB27_Msk                              /*!<Filter bit 27 */
5309 #define CAN_F12R2_FB28_Pos     (28U)
5310 #define CAN_F12R2_FB28_Msk     (0x1UL << CAN_F12R2_FB28_Pos)                    /*!< 0x10000000 */
5311 #define CAN_F12R2_FB28         CAN_F12R2_FB28_Msk                              /*!<Filter bit 28 */
5312 #define CAN_F12R2_FB29_Pos     (29U)
5313 #define CAN_F12R2_FB29_Msk     (0x1UL << CAN_F12R2_FB29_Pos)                    /*!< 0x20000000 */
5314 #define CAN_F12R2_FB29         CAN_F12R2_FB29_Msk                              /*!<Filter bit 29 */
5315 #define CAN_F12R2_FB30_Pos     (30U)
5316 #define CAN_F12R2_FB30_Msk     (0x1UL << CAN_F12R2_FB30_Pos)                    /*!< 0x40000000 */
5317 #define CAN_F12R2_FB30         CAN_F12R2_FB30_Msk                              /*!<Filter bit 30 */
5318 #define CAN_F12R2_FB31_Pos     (31U)
5319 #define CAN_F12R2_FB31_Msk     (0x1UL << CAN_F12R2_FB31_Pos)                    /*!< 0x80000000 */
5320 #define CAN_F12R2_FB31         CAN_F12R2_FB31_Msk                              /*!<Filter bit 31 */
5321 
5322 /*******************  Bit definition for CAN_F13R2 register  ******************/
5323 #define CAN_F13R2_FB0_Pos      (0U)
5324 #define CAN_F13R2_FB0_Msk      (0x1UL << CAN_F13R2_FB0_Pos)                     /*!< 0x00000001 */
5325 #define CAN_F13R2_FB0          CAN_F13R2_FB0_Msk                               /*!<Filter bit 0 */
5326 #define CAN_F13R2_FB1_Pos      (1U)
5327 #define CAN_F13R2_FB1_Msk      (0x1UL << CAN_F13R2_FB1_Pos)                     /*!< 0x00000002 */
5328 #define CAN_F13R2_FB1          CAN_F13R2_FB1_Msk                               /*!<Filter bit 1 */
5329 #define CAN_F13R2_FB2_Pos      (2U)
5330 #define CAN_F13R2_FB2_Msk      (0x1UL << CAN_F13R2_FB2_Pos)                     /*!< 0x00000004 */
5331 #define CAN_F13R2_FB2          CAN_F13R2_FB2_Msk                               /*!<Filter bit 2 */
5332 #define CAN_F13R2_FB3_Pos      (3U)
5333 #define CAN_F13R2_FB3_Msk      (0x1UL << CAN_F13R2_FB3_Pos)                     /*!< 0x00000008 */
5334 #define CAN_F13R2_FB3          CAN_F13R2_FB3_Msk                               /*!<Filter bit 3 */
5335 #define CAN_F13R2_FB4_Pos      (4U)
5336 #define CAN_F13R2_FB4_Msk      (0x1UL << CAN_F13R2_FB4_Pos)                     /*!< 0x00000010 */
5337 #define CAN_F13R2_FB4          CAN_F13R2_FB4_Msk                               /*!<Filter bit 4 */
5338 #define CAN_F13R2_FB5_Pos      (5U)
5339 #define CAN_F13R2_FB5_Msk      (0x1UL << CAN_F13R2_FB5_Pos)                     /*!< 0x00000020 */
5340 #define CAN_F13R2_FB5          CAN_F13R2_FB5_Msk                               /*!<Filter bit 5 */
5341 #define CAN_F13R2_FB6_Pos      (6U)
5342 #define CAN_F13R2_FB6_Msk      (0x1UL << CAN_F13R2_FB6_Pos)                     /*!< 0x00000040 */
5343 #define CAN_F13R2_FB6          CAN_F13R2_FB6_Msk                               /*!<Filter bit 6 */
5344 #define CAN_F13R2_FB7_Pos      (7U)
5345 #define CAN_F13R2_FB7_Msk      (0x1UL << CAN_F13R2_FB7_Pos)                     /*!< 0x00000080 */
5346 #define CAN_F13R2_FB7          CAN_F13R2_FB7_Msk                               /*!<Filter bit 7 */
5347 #define CAN_F13R2_FB8_Pos      (8U)
5348 #define CAN_F13R2_FB8_Msk      (0x1UL << CAN_F13R2_FB8_Pos)                     /*!< 0x00000100 */
5349 #define CAN_F13R2_FB8          CAN_F13R2_FB8_Msk                               /*!<Filter bit 8 */
5350 #define CAN_F13R2_FB9_Pos      (9U)
5351 #define CAN_F13R2_FB9_Msk      (0x1UL << CAN_F13R2_FB9_Pos)                     /*!< 0x00000200 */
5352 #define CAN_F13R2_FB9          CAN_F13R2_FB9_Msk                               /*!<Filter bit 9 */
5353 #define CAN_F13R2_FB10_Pos     (10U)
5354 #define CAN_F13R2_FB10_Msk     (0x1UL << CAN_F13R2_FB10_Pos)                    /*!< 0x00000400 */
5355 #define CAN_F13R2_FB10         CAN_F13R2_FB10_Msk                              /*!<Filter bit 10 */
5356 #define CAN_F13R2_FB11_Pos     (11U)
5357 #define CAN_F13R2_FB11_Msk     (0x1UL << CAN_F13R2_FB11_Pos)                    /*!< 0x00000800 */
5358 #define CAN_F13R2_FB11         CAN_F13R2_FB11_Msk                              /*!<Filter bit 11 */
5359 #define CAN_F13R2_FB12_Pos     (12U)
5360 #define CAN_F13R2_FB12_Msk     (0x1UL << CAN_F13R2_FB12_Pos)                    /*!< 0x00001000 */
5361 #define CAN_F13R2_FB12         CAN_F13R2_FB12_Msk                              /*!<Filter bit 12 */
5362 #define CAN_F13R2_FB13_Pos     (13U)
5363 #define CAN_F13R2_FB13_Msk     (0x1UL << CAN_F13R2_FB13_Pos)                    /*!< 0x00002000 */
5364 #define CAN_F13R2_FB13         CAN_F13R2_FB13_Msk                              /*!<Filter bit 13 */
5365 #define CAN_F13R2_FB14_Pos     (14U)
5366 #define CAN_F13R2_FB14_Msk     (0x1UL << CAN_F13R2_FB14_Pos)                    /*!< 0x00004000 */
5367 #define CAN_F13R2_FB14         CAN_F13R2_FB14_Msk                              /*!<Filter bit 14 */
5368 #define CAN_F13R2_FB15_Pos     (15U)
5369 #define CAN_F13R2_FB15_Msk     (0x1UL << CAN_F13R2_FB15_Pos)                    /*!< 0x00008000 */
5370 #define CAN_F13R2_FB15         CAN_F13R2_FB15_Msk                              /*!<Filter bit 15 */
5371 #define CAN_F13R2_FB16_Pos     (16U)
5372 #define CAN_F13R2_FB16_Msk     (0x1UL << CAN_F13R2_FB16_Pos)                    /*!< 0x00010000 */
5373 #define CAN_F13R2_FB16         CAN_F13R2_FB16_Msk                              /*!<Filter bit 16 */
5374 #define CAN_F13R2_FB17_Pos     (17U)
5375 #define CAN_F13R2_FB17_Msk     (0x1UL << CAN_F13R2_FB17_Pos)                    /*!< 0x00020000 */
5376 #define CAN_F13R2_FB17         CAN_F13R2_FB17_Msk                              /*!<Filter bit 17 */
5377 #define CAN_F13R2_FB18_Pos     (18U)
5378 #define CAN_F13R2_FB18_Msk     (0x1UL << CAN_F13R2_FB18_Pos)                    /*!< 0x00040000 */
5379 #define CAN_F13R2_FB18         CAN_F13R2_FB18_Msk                              /*!<Filter bit 18 */
5380 #define CAN_F13R2_FB19_Pos     (19U)
5381 #define CAN_F13R2_FB19_Msk     (0x1UL << CAN_F13R2_FB19_Pos)                    /*!< 0x00080000 */
5382 #define CAN_F13R2_FB19         CAN_F13R2_FB19_Msk                              /*!<Filter bit 19 */
5383 #define CAN_F13R2_FB20_Pos     (20U)
5384 #define CAN_F13R2_FB20_Msk     (0x1UL << CAN_F13R2_FB20_Pos)                    /*!< 0x00100000 */
5385 #define CAN_F13R2_FB20         CAN_F13R2_FB20_Msk                              /*!<Filter bit 20 */
5386 #define CAN_F13R2_FB21_Pos     (21U)
5387 #define CAN_F13R2_FB21_Msk     (0x1UL << CAN_F13R2_FB21_Pos)                    /*!< 0x00200000 */
5388 #define CAN_F13R2_FB21         CAN_F13R2_FB21_Msk                              /*!<Filter bit 21 */
5389 #define CAN_F13R2_FB22_Pos     (22U)
5390 #define CAN_F13R2_FB22_Msk     (0x1UL << CAN_F13R2_FB22_Pos)                    /*!< 0x00400000 */
5391 #define CAN_F13R2_FB22         CAN_F13R2_FB22_Msk                              /*!<Filter bit 22 */
5392 #define CAN_F13R2_FB23_Pos     (23U)
5393 #define CAN_F13R2_FB23_Msk     (0x1UL << CAN_F13R2_FB23_Pos)                    /*!< 0x00800000 */
5394 #define CAN_F13R2_FB23         CAN_F13R2_FB23_Msk                              /*!<Filter bit 23 */
5395 #define CAN_F13R2_FB24_Pos     (24U)
5396 #define CAN_F13R2_FB24_Msk     (0x1UL << CAN_F13R2_FB24_Pos)                    /*!< 0x01000000 */
5397 #define CAN_F13R2_FB24         CAN_F13R2_FB24_Msk                              /*!<Filter bit 24 */
5398 #define CAN_F13R2_FB25_Pos     (25U)
5399 #define CAN_F13R2_FB25_Msk     (0x1UL << CAN_F13R2_FB25_Pos)                    /*!< 0x02000000 */
5400 #define CAN_F13R2_FB25         CAN_F13R2_FB25_Msk                              /*!<Filter bit 25 */
5401 #define CAN_F13R2_FB26_Pos     (26U)
5402 #define CAN_F13R2_FB26_Msk     (0x1UL << CAN_F13R2_FB26_Pos)                    /*!< 0x04000000 */
5403 #define CAN_F13R2_FB26         CAN_F13R2_FB26_Msk                              /*!<Filter bit 26 */
5404 #define CAN_F13R2_FB27_Pos     (27U)
5405 #define CAN_F13R2_FB27_Msk     (0x1UL << CAN_F13R2_FB27_Pos)                    /*!< 0x08000000 */
5406 #define CAN_F13R2_FB27         CAN_F13R2_FB27_Msk                              /*!<Filter bit 27 */
5407 #define CAN_F13R2_FB28_Pos     (28U)
5408 #define CAN_F13R2_FB28_Msk     (0x1UL << CAN_F13R2_FB28_Pos)                    /*!< 0x10000000 */
5409 #define CAN_F13R2_FB28         CAN_F13R2_FB28_Msk                              /*!<Filter bit 28 */
5410 #define CAN_F13R2_FB29_Pos     (29U)
5411 #define CAN_F13R2_FB29_Msk     (0x1UL << CAN_F13R2_FB29_Pos)                    /*!< 0x20000000 */
5412 #define CAN_F13R2_FB29         CAN_F13R2_FB29_Msk                              /*!<Filter bit 29 */
5413 #define CAN_F13R2_FB30_Pos     (30U)
5414 #define CAN_F13R2_FB30_Msk     (0x1UL << CAN_F13R2_FB30_Pos)                    /*!< 0x40000000 */
5415 #define CAN_F13R2_FB30         CAN_F13R2_FB30_Msk                              /*!<Filter bit 30 */
5416 #define CAN_F13R2_FB31_Pos     (31U)
5417 #define CAN_F13R2_FB31_Msk     (0x1UL << CAN_F13R2_FB31_Pos)                    /*!< 0x80000000 */
5418 #define CAN_F13R2_FB31         CAN_F13R2_FB31_Msk                              /*!<Filter bit 31 */
5419 
5420 /******************************************************************************/
5421 /*                                                                            */
5422 /*                          CRC calculation unit                              */
5423 /*                                                                            */
5424 /******************************************************************************/
5425 /*******************  Bit definition for CRC_DR register  *********************/
5426 #define CRC_DR_DR_Pos       (0U)
5427 #define CRC_DR_DR_Msk       (0xFFFFFFFFUL << CRC_DR_DR_Pos)                     /*!< 0xFFFFFFFF */
5428 #define CRC_DR_DR           CRC_DR_DR_Msk                                      /*!< Data register bits */
5429 
5430 
5431 /*******************  Bit definition for CRC_IDR register  ********************/
5432 #define CRC_IDR_IDR_Pos     (0U)
5433 #define CRC_IDR_IDR_Msk     (0xFFUL << CRC_IDR_IDR_Pos)                         /*!< 0x000000FF */
5434 #define CRC_IDR_IDR         CRC_IDR_IDR_Msk                                    /*!< General-purpose 8-bit data register bits */
5435 
5436 
5437 /********************  Bit definition for CRC_CR register  ********************/
5438 #define CRC_CR_RESET_Pos    (0U)
5439 #define CRC_CR_RESET_Msk    (0x1UL << CRC_CR_RESET_Pos)                         /*!< 0x00000001 */
5440 #define CRC_CR_RESET        CRC_CR_RESET_Msk                                   /*!< RESET bit */
5441 
5442 /******************************************************************************/
5443 /*                                                                            */
5444 /*                      Digital to Analog Converter                           */
5445 /*                                                                            */
5446 /******************************************************************************/
5447 /*
5448  * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
5449  */
5450 #define DAC_CHANNEL2_SUPPORT                                    /*!< DAC feature available only on specific devices: availability of DAC channel 2 */
5451 /********************  Bit definition for DAC_CR register  ********************/
5452 #define DAC_CR_EN1_Pos              (0U)
5453 #define DAC_CR_EN1_Msk              (0x1UL << DAC_CR_EN1_Pos)                   /*!< 0x00000001 */
5454 #define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!<DAC channel1 enable */
5455 #define DAC_CR_BOFF1_Pos            (1U)
5456 #define DAC_CR_BOFF1_Msk            (0x1UL << DAC_CR_BOFF1_Pos)                 /*!< 0x00000002 */
5457 #define DAC_CR_BOFF1                DAC_CR_BOFF1_Msk                           /*!<DAC channel1 output buffer disable */
5458 #define DAC_CR_TEN1_Pos             (2U)
5459 #define DAC_CR_TEN1_Msk             (0x1UL << DAC_CR_TEN1_Pos)                  /*!< 0x00000004 */
5460 #define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!<DAC channel1 Trigger enable */
5461 
5462 #define DAC_CR_TSEL1_Pos            (3U)
5463 #define DAC_CR_TSEL1_Msk            (0x7UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000038 */
5464 #define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
5465 #define DAC_CR_TSEL1_0              (0x1UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000008 */
5466 #define DAC_CR_TSEL1_1              (0x2UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000010 */
5467 #define DAC_CR_TSEL1_2              (0x4UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000020 */
5468 
5469 #define DAC_CR_WAVE1_Pos            (6U)
5470 #define DAC_CR_WAVE1_Msk            (0x3UL << DAC_CR_WAVE1_Pos)                 /*!< 0x000000C0 */
5471 #define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
5472 #define DAC_CR_WAVE1_0              (0x1UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000040 */
5473 #define DAC_CR_WAVE1_1              (0x2UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000080 */
5474 
5475 #define DAC_CR_MAMP1_Pos            (8U)
5476 #define DAC_CR_MAMP1_Msk            (0xFUL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000F00 */
5477 #define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
5478 #define DAC_CR_MAMP1_0              (0x1UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000100 */
5479 #define DAC_CR_MAMP1_1              (0x2UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000200 */
5480 #define DAC_CR_MAMP1_2              (0x4UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000400 */
5481 #define DAC_CR_MAMP1_3              (0x8UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000800 */
5482 
5483 #define DAC_CR_DMAEN1_Pos           (12U)
5484 #define DAC_CR_DMAEN1_Msk           (0x1UL << DAC_CR_DMAEN1_Pos)                /*!< 0x00001000 */
5485 #define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!<DAC channel1 DMA enable */
5486 #define DAC_CR_DMAUDRIE1_Pos        (13U)
5487 #define DAC_CR_DMAUDRIE1_Msk        (0x1UL << DAC_CR_DMAUDRIE1_Pos)             /*!< 0x00002000 */
5488 #define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!<DAC channel1 DMA underrun interrupt enable*/
5489 #define DAC_CR_EN2_Pos              (16U)
5490 #define DAC_CR_EN2_Msk              (0x1UL << DAC_CR_EN2_Pos)                   /*!< 0x00010000 */
5491 #define DAC_CR_EN2                  DAC_CR_EN2_Msk                             /*!<DAC channel2 enable */
5492 #define DAC_CR_BOFF2_Pos            (17U)
5493 #define DAC_CR_BOFF2_Msk            (0x1UL << DAC_CR_BOFF2_Pos)                 /*!< 0x00020000 */
5494 #define DAC_CR_BOFF2                DAC_CR_BOFF2_Msk                           /*!<DAC channel2 output buffer disable */
5495 #define DAC_CR_TEN2_Pos             (18U)
5496 #define DAC_CR_TEN2_Msk             (0x1UL << DAC_CR_TEN2_Pos)                  /*!< 0x00040000 */
5497 #define DAC_CR_TEN2                 DAC_CR_TEN2_Msk                            /*!<DAC channel2 Trigger enable */
5498 
5499 #define DAC_CR_TSEL2_Pos            (19U)
5500 #define DAC_CR_TSEL2_Msk            (0x7UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00380000 */
5501 #define DAC_CR_TSEL2                DAC_CR_TSEL2_Msk                           /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
5502 #define DAC_CR_TSEL2_0              (0x1UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00080000 */
5503 #define DAC_CR_TSEL2_1              (0x2UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00100000 */
5504 #define DAC_CR_TSEL2_2              (0x4UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00200000 */
5505 
5506 #define DAC_CR_WAVE2_Pos            (22U)
5507 #define DAC_CR_WAVE2_Msk            (0x3UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00C00000 */
5508 #define DAC_CR_WAVE2                DAC_CR_WAVE2_Msk                           /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
5509 #define DAC_CR_WAVE2_0              (0x1UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00400000 */
5510 #define DAC_CR_WAVE2_1              (0x2UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00800000 */
5511 
5512 #define DAC_CR_MAMP2_Pos            (24U)
5513 #define DAC_CR_MAMP2_Msk            (0xFUL << DAC_CR_MAMP2_Pos)                 /*!< 0x0F000000 */
5514 #define DAC_CR_MAMP2                DAC_CR_MAMP2_Msk                           /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
5515 #define DAC_CR_MAMP2_0              (0x1UL << DAC_CR_MAMP2_Pos)                 /*!< 0x01000000 */
5516 #define DAC_CR_MAMP2_1              (0x2UL << DAC_CR_MAMP2_Pos)                 /*!< 0x02000000 */
5517 #define DAC_CR_MAMP2_2              (0x4UL << DAC_CR_MAMP2_Pos)                 /*!< 0x04000000 */
5518 #define DAC_CR_MAMP2_3              (0x8UL << DAC_CR_MAMP2_Pos)                 /*!< 0x08000000 */
5519 
5520 #define DAC_CR_DMAEN2_Pos           (28U)
5521 #define DAC_CR_DMAEN2_Msk           (0x1UL << DAC_CR_DMAEN2_Pos)                /*!< 0x10000000 */
5522 #define DAC_CR_DMAEN2               DAC_CR_DMAEN2_Msk                          /*!<DAC channel2 DMA enabled */
5523 #define DAC_CR_DMAUDRIE2_Pos        (29U)
5524 #define DAC_CR_DMAUDRIE2_Msk        (0x1UL << DAC_CR_DMAUDRIE2_Pos)             /*!< 0x20000000 */
5525 #define DAC_CR_DMAUDRIE2            DAC_CR_DMAUDRIE2_Msk                       /*!<DAC channel2 DMA underrun interrupt enable*/
5526 
5527 /*****************  Bit definition for DAC_SWTRIGR register  ******************/
5528 #define DAC_SWTRIGR_SWTRIG1_Pos     (0U)
5529 #define DAC_SWTRIGR_SWTRIG1_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)          /*!< 0x00000001 */
5530 #define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!<DAC channel1 software trigger */
5531 #define DAC_SWTRIGR_SWTRIG2_Pos     (1U)
5532 #define DAC_SWTRIGR_SWTRIG2_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)          /*!< 0x00000002 */
5533 #define DAC_SWTRIGR_SWTRIG2         DAC_SWTRIGR_SWTRIG2_Msk                    /*!<DAC channel2 software trigger */
5534 
5535 /*****************  Bit definition for DAC_DHR12R1 register  ******************/
5536 #define DAC_DHR12R1_DACC1DHR_Pos    (0U)
5537 #define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)       /*!< 0x00000FFF */
5538 #define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
5539 
5540 /*****************  Bit definition for DAC_DHR12L1 register  ******************/
5541 #define DAC_DHR12L1_DACC1DHR_Pos    (4U)
5542 #define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)       /*!< 0x0000FFF0 */
5543 #define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
5544 
5545 /******************  Bit definition for DAC_DHR8R1 register  ******************/
5546 #define DAC_DHR8R1_DACC1DHR_Pos     (0U)
5547 #define DAC_DHR8R1_DACC1DHR_Msk     (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)         /*!< 0x000000FF */
5548 #define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
5549 
5550 /*****************  Bit definition for DAC_DHR12R2 register  ******************/
5551 #define DAC_DHR12R2_DACC2DHR_Pos    (0U)
5552 #define DAC_DHR12R2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)       /*!< 0x00000FFF */
5553 #define DAC_DHR12R2_DACC2DHR        DAC_DHR12R2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */
5554 
5555 /*****************  Bit definition for DAC_DHR12L2 register  ******************/
5556 #define DAC_DHR12L2_DACC2DHR_Pos    (4U)
5557 #define DAC_DHR12L2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)       /*!< 0x0000FFF0 */
5558 #define DAC_DHR12L2_DACC2DHR        DAC_DHR12L2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */
5559 
5560 /******************  Bit definition for DAC_DHR8R2 register  ******************/
5561 #define DAC_DHR8R2_DACC2DHR_Pos     (0U)
5562 #define DAC_DHR8R2_DACC2DHR_Msk     (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)         /*!< 0x000000FF */
5563 #define DAC_DHR8R2_DACC2DHR         DAC_DHR8R2_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */
5564 
5565 /*****************  Bit definition for DAC_DHR12RD register  ******************/
5566 #define DAC_DHR12RD_DACC1DHR_Pos    (0U)
5567 #define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)       /*!< 0x00000FFF */
5568 #define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
5569 #define DAC_DHR12RD_DACC2DHR_Pos    (16U)
5570 #define DAC_DHR12RD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)       /*!< 0x0FFF0000 */
5571 #define DAC_DHR12RD_DACC2DHR        DAC_DHR12RD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */
5572 
5573 /*****************  Bit definition for DAC_DHR12LD register  ******************/
5574 #define DAC_DHR12LD_DACC1DHR_Pos    (4U)
5575 #define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)       /*!< 0x0000FFF0 */
5576 #define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
5577 #define DAC_DHR12LD_DACC2DHR_Pos    (20U)
5578 #define DAC_DHR12LD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)       /*!< 0xFFF00000 */
5579 #define DAC_DHR12LD_DACC2DHR        DAC_DHR12LD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */
5580 
5581 /******************  Bit definition for DAC_DHR8RD register  ******************/
5582 #define DAC_DHR8RD_DACC1DHR_Pos     (0U)
5583 #define DAC_DHR8RD_DACC1DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)         /*!< 0x000000FF */
5584 #define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
5585 #define DAC_DHR8RD_DACC2DHR_Pos     (8U)
5586 #define DAC_DHR8RD_DACC2DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)         /*!< 0x0000FF00 */
5587 #define DAC_DHR8RD_DACC2DHR         DAC_DHR8RD_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */
5588 
5589 /*******************  Bit definition for DAC_DOR1 register  *******************/
5590 #define DAC_DOR1_DACC1DOR_Pos       (0U)
5591 #define DAC_DOR1_DACC1DOR_Msk       (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)          /*!< 0x00000FFF */
5592 #define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!<DAC channel1 data output */
5593 
5594 /*******************  Bit definition for DAC_DOR2 register  *******************/
5595 #define DAC_DOR2_DACC2DOR_Pos       (0U)
5596 #define DAC_DOR2_DACC2DOR_Msk       (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)          /*!< 0x00000FFF */
5597 #define DAC_DOR2_DACC2DOR           DAC_DOR2_DACC2DOR_Msk                      /*!<DAC channel2 data output */
5598 
5599 /********************  Bit definition for DAC_SR register  ********************/
5600 #define DAC_SR_DMAUDR1_Pos          (13U)
5601 #define DAC_SR_DMAUDR1_Msk          (0x1UL << DAC_SR_DMAUDR1_Pos)               /*!< 0x00002000 */
5602 #define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!<DAC channel1 DMA underrun flag */
5603 #define DAC_SR_DMAUDR2_Pos          (29U)
5604 #define DAC_SR_DMAUDR2_Msk          (0x1UL << DAC_SR_DMAUDR2_Pos)               /*!< 0x20000000 */
5605 #define DAC_SR_DMAUDR2              DAC_SR_DMAUDR2_Msk                         /*!<DAC channel2 DMA underrun flag */
5606 
5607 /******************************************************************************/
5608 /*                                                                            */
5609 /*                 Digital Filter for Sigma Delta Modulators                  */
5610 /*                                                                            */
5611 /******************************************************************************/
5612 
5613 /****************   DFSDM channel configuration registers  ********************/
5614 
5615 /***************  Bit definition for DFSDM_CHCFGR1 register  ******************/
5616 #define DFSDM_CHCFGR1_DFSDMEN_Pos       (31U)
5617 #define DFSDM_CHCFGR1_DFSDMEN_Msk       (0x1UL << DFSDM_CHCFGR1_DFSDMEN_Pos)    /*!< 0x80000000 */
5618 #define DFSDM_CHCFGR1_DFSDMEN           DFSDM_CHCFGR1_DFSDMEN_Msk              /*!< Global enable for DFSDM interface */
5619 #define DFSDM_CHCFGR1_CKOUTSRC_Pos      (30U)
5620 #define DFSDM_CHCFGR1_CKOUTSRC_Msk      (0x1UL << DFSDM_CHCFGR1_CKOUTSRC_Pos)   /*!< 0x40000000 */
5621 #define DFSDM_CHCFGR1_CKOUTSRC          DFSDM_CHCFGR1_CKOUTSRC_Msk             /*!< Output serial clock source selection */
5622 #define DFSDM_CHCFGR1_CKOUTDIV_Pos      (16U)
5623 #define DFSDM_CHCFGR1_CKOUTDIV_Msk      (0xFFUL << DFSDM_CHCFGR1_CKOUTDIV_Pos)  /*!< 0x00FF0000 */
5624 #define DFSDM_CHCFGR1_CKOUTDIV          DFSDM_CHCFGR1_CKOUTDIV_Msk             /*!< CKOUTDIV[7:0] output serial clock divider */
5625 #define DFSDM_CHCFGR1_DATPACK_Pos       (14U)
5626 #define DFSDM_CHCFGR1_DATPACK_Msk       (0x3UL << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x0000C000 */
5627 #define DFSDM_CHCFGR1_DATPACK           DFSDM_CHCFGR1_DATPACK_Msk              /*!< DATPACK[1:0] Data packing mode */
5628 #define DFSDM_CHCFGR1_DATPACK_1         (0x2UL << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x00008000 */
5629 #define DFSDM_CHCFGR1_DATPACK_0         (0x1UL << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x00004000 */
5630 #define DFSDM_CHCFGR1_DATMPX_Pos        (12U)
5631 #define DFSDM_CHCFGR1_DATMPX_Msk        (0x3UL << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00003000 */
5632 #define DFSDM_CHCFGR1_DATMPX            DFSDM_CHCFGR1_DATMPX_Msk               /*!< DATMPX[1:0] Input data multiplexer for channel y */
5633 #define DFSDM_CHCFGR1_DATMPX_1          (0x2UL << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00002000 */
5634 #define DFSDM_CHCFGR1_DATMPX_0          (0x1UL << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00001000 */
5635 #define DFSDM_CHCFGR1_CHINSEL_Pos       (8U)
5636 #define DFSDM_CHCFGR1_CHINSEL_Msk       (0x1UL << DFSDM_CHCFGR1_CHINSEL_Pos)    /*!< 0x00000100 */
5637 #define DFSDM_CHCFGR1_CHINSEL           DFSDM_CHCFGR1_CHINSEL_Msk              /*!< Serial inputs selection for channel y */
5638 #define DFSDM_CHCFGR1_CHEN_Pos          (7U)
5639 #define DFSDM_CHCFGR1_CHEN_Msk          (0x1UL << DFSDM_CHCFGR1_CHEN_Pos)       /*!< 0x00000080 */
5640 #define DFSDM_CHCFGR1_CHEN              DFSDM_CHCFGR1_CHEN_Msk                 /*!< Channel y enable */
5641 #define DFSDM_CHCFGR1_CKABEN_Pos        (6U)
5642 #define DFSDM_CHCFGR1_CKABEN_Msk        (0x1UL << DFSDM_CHCFGR1_CKABEN_Pos)     /*!< 0x00000040 */
5643 #define DFSDM_CHCFGR1_CKABEN            DFSDM_CHCFGR1_CKABEN_Msk               /*!< Clock absence detector enable on channel y */
5644 #define DFSDM_CHCFGR1_SCDEN_Pos         (5U)
5645 #define DFSDM_CHCFGR1_SCDEN_Msk         (0x1UL << DFSDM_CHCFGR1_SCDEN_Pos)      /*!< 0x00000020 */
5646 #define DFSDM_CHCFGR1_SCDEN             DFSDM_CHCFGR1_SCDEN_Msk                /*!< Short circuit detector enable on channel y */
5647 #define DFSDM_CHCFGR1_SPICKSEL_Pos      (2U)
5648 #define DFSDM_CHCFGR1_SPICKSEL_Msk      (0x3UL << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x0000000C */
5649 #define DFSDM_CHCFGR1_SPICKSEL          DFSDM_CHCFGR1_SPICKSEL_Msk             /*!< SPICKSEL[1:0] SPI clock select for channel y */
5650 #define DFSDM_CHCFGR1_SPICKSEL_1        (0x2UL << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x00000008 */
5651 #define DFSDM_CHCFGR1_SPICKSEL_0        (0x1UL << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x00000004 */
5652 #define DFSDM_CHCFGR1_SITP_Pos          (0U)
5653 #define DFSDM_CHCFGR1_SITP_Msk          (0x3UL << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000003 */
5654 #define DFSDM_CHCFGR1_SITP              DFSDM_CHCFGR1_SITP_Msk                 /*!< SITP[1:0] Serial interface type for channel y */
5655 #define DFSDM_CHCFGR1_SITP_1            (0x2UL << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000002 */
5656 #define DFSDM_CHCFGR1_SITP_0            (0x1UL << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000001 */
5657 
5658 /***************  Bit definition for DFSDM_CHCFGR2 register  ******************/
5659 #define DFSDM_CHCFGR2_OFFSET_Pos        (8U)
5660 #define DFSDM_CHCFGR2_OFFSET_Msk        (0xFFFFFFUL << DFSDM_CHCFGR2_OFFSET_Pos) /*!< 0xFFFFFF00 */
5661 #define DFSDM_CHCFGR2_OFFSET            DFSDM_CHCFGR2_OFFSET_Msk               /*!< OFFSET[23:0] 24-bit calibration offset for channel y */
5662 #define DFSDM_CHCFGR2_DTRBS_Pos         (3U)
5663 #define DFSDM_CHCFGR2_DTRBS_Msk         (0x1FUL << DFSDM_CHCFGR2_DTRBS_Pos)     /*!< 0x000000F8 */
5664 #define DFSDM_CHCFGR2_DTRBS             DFSDM_CHCFGR2_DTRBS_Msk                /*!< DTRBS[4:0] Data right bit-shift for channel y */
5665 
5666 /****************  Bit definition for DFSDM_CHAWSCDR register *****************/
5667 #define DFSDM_CHAWSCDR_AWFORD_Pos       (22U)
5668 #define DFSDM_CHAWSCDR_AWFORD_Msk       (0x3UL << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00C00000 */
5669 #define DFSDM_CHAWSCDR_AWFORD           DFSDM_CHAWSCDR_AWFORD_Msk              /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */
5670 #define DFSDM_CHAWSCDR_AWFORD_1         (0x2UL << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00800000 */
5671 #define DFSDM_CHAWSCDR_AWFORD_0         (0x1UL << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00400000 */
5672 #define DFSDM_CHAWSCDR_AWFOSR_Pos       (16U)
5673 #define DFSDM_CHAWSCDR_AWFOSR_Msk       (0x1FUL << DFSDM_CHAWSCDR_AWFOSR_Pos)   /*!< 0x001F0000 */
5674 #define DFSDM_CHAWSCDR_AWFOSR           DFSDM_CHAWSCDR_AWFOSR_Msk              /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */
5675 #define DFSDM_CHAWSCDR_BKSCD_Pos        (12U)
5676 #define DFSDM_CHAWSCDR_BKSCD_Msk        (0xFUL << DFSDM_CHAWSCDR_BKSCD_Pos)     /*!< 0x0000F000 */
5677 #define DFSDM_CHAWSCDR_BKSCD            DFSDM_CHAWSCDR_BKSCD_Msk               /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */
5678 #define DFSDM_CHAWSCDR_SCDT_Pos         (0U)
5679 #define DFSDM_CHAWSCDR_SCDT_Msk         (0xFFUL << DFSDM_CHAWSCDR_SCDT_Pos)     /*!< 0x000000FF */
5680 #define DFSDM_CHAWSCDR_SCDT             DFSDM_CHAWSCDR_SCDT_Msk                /*!< SCDT[7:0] Short circuit detector threshold for channel y */
5681 
5682 /****************  Bit definition for DFSDM_CHWDATR register *******************/
5683 #define DFSDM_CHWDATR_WDATA_Pos         (0U)
5684 #define DFSDM_CHWDATR_WDATA_Msk         (0xFFFFUL << DFSDM_CHWDATR_WDATA_Pos)   /*!< 0x0000FFFF */
5685 #define DFSDM_CHWDATR_WDATA             DFSDM_CHWDATR_WDATA_Msk                /*!< WDATA[15:0] Input channel y watchdog data */
5686 
5687 /****************  Bit definition for DFSDM_CHDATINR register *****************/
5688 #define DFSDM_CHDATINR_INDAT0_Pos       (0U)
5689 #define DFSDM_CHDATINR_INDAT0_Msk       (0xFFFFUL << DFSDM_CHDATINR_INDAT0_Pos) /*!< 0x0000FFFF */
5690 #define DFSDM_CHDATINR_INDAT0           DFSDM_CHDATINR_INDAT0_Msk              /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */
5691 #define DFSDM_CHDATINR_INDAT1_Pos       (16U)
5692 #define DFSDM_CHDATINR_INDAT1_Msk       (0xFFFFUL << DFSDM_CHDATINR_INDAT1_Pos) /*!< 0xFFFF0000 */
5693 #define DFSDM_CHDATINR_INDAT1           DFSDM_CHDATINR_INDAT1_Msk              /*!< INDAT0[15:0] Input data for channel y */
5694 
5695 /************************   DFSDM module registers  ****************************/
5696 
5697 /*****************  Bit definition for DFSDM_FLTCR1 register *******************/
5698 #define DFSDM_FLTCR1_AWFSEL_Pos         (30U)
5699 #define DFSDM_FLTCR1_AWFSEL_Msk         (0x1UL << DFSDM_FLTCR1_AWFSEL_Pos)      /*!< 0x40000000 */
5700 #define DFSDM_FLTCR1_AWFSEL             DFSDM_FLTCR1_AWFSEL_Msk                /*!< Analog watchdog fast mode select */
5701 #define DFSDM_FLTCR1_FAST_Pos           (29U)
5702 #define DFSDM_FLTCR1_FAST_Msk           (0x1UL << DFSDM_FLTCR1_FAST_Pos)        /*!< 0x20000000 */
5703 #define DFSDM_FLTCR1_FAST               DFSDM_FLTCR1_FAST_Msk                  /*!< Fast conversion mode selection */
5704 #define DFSDM_FLTCR1_RCH_Pos            (24U)
5705 #define DFSDM_FLTCR1_RCH_Msk            (0x7UL << DFSDM_FLTCR1_RCH_Pos)         /*!< 0x07000000 */
5706 #define DFSDM_FLTCR1_RCH                DFSDM_FLTCR1_RCH_Msk                   /*!< RCH[2:0] Regular channel selection */
5707 #define DFSDM_FLTCR1_RDMAEN_Pos         (21U)
5708 #define DFSDM_FLTCR1_RDMAEN_Msk         (0x1UL << DFSDM_FLTCR1_RDMAEN_Pos)      /*!< 0x00200000 */
5709 #define DFSDM_FLTCR1_RDMAEN             DFSDM_FLTCR1_RDMAEN_Msk                /*!< DMA channel enabled to read data for the regular conversion */
5710 #define DFSDM_FLTCR1_RSYNC_Pos          (19U)
5711 #define DFSDM_FLTCR1_RSYNC_Msk          (0x1UL << DFSDM_FLTCR1_RSYNC_Pos)       /*!< 0x00080000 */
5712 #define DFSDM_FLTCR1_RSYNC              DFSDM_FLTCR1_RSYNC_Msk                 /*!< Launch regular conversion synchronously with DFSDMx */
5713 #define DFSDM_FLTCR1_RCONT_Pos          (18U)
5714 #define DFSDM_FLTCR1_RCONT_Msk          (0x1UL << DFSDM_FLTCR1_RCONT_Pos)       /*!< 0x00040000 */
5715 #define DFSDM_FLTCR1_RCONT              DFSDM_FLTCR1_RCONT_Msk                 /*!< Continuous mode selection for regular conversions */
5716 #define DFSDM_FLTCR1_RSWSTART_Pos       (17U)
5717 #define DFSDM_FLTCR1_RSWSTART_Msk       (0x1UL << DFSDM_FLTCR1_RSWSTART_Pos)    /*!< 0x00020000 */
5718 #define DFSDM_FLTCR1_RSWSTART           DFSDM_FLTCR1_RSWSTART_Msk              /*!< Software start of a conversion on the regular channel */
5719 #define DFSDM_FLTCR1_JEXTEN_Pos         (13U)
5720 #define DFSDM_FLTCR1_JEXTEN_Msk         (0x3UL << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00006000 */
5721 #define DFSDM_FLTCR1_JEXTEN             DFSDM_FLTCR1_JEXTEN_Msk                /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */
5722 #define DFSDM_FLTCR1_JEXTEN_1           (0x2UL << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00004000 */
5723 #define DFSDM_FLTCR1_JEXTEN_0           (0x1UL << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00002000 */
5724 #define DFSDM_FLTCR1_JEXTSEL_Pos        (8U)
5725 #define DFSDM_FLTCR1_JEXTSEL_Msk        (0x7UL << DFSDM_FLTCR1_JEXTSEL_Pos)     /*!< 0x00000700 */
5726 #define DFSDM_FLTCR1_JEXTSEL            DFSDM_FLTCR1_JEXTSEL_Msk               /*!< JEXTSEL[2:0]Trigger signal selection for launching injected conversions */
5727 #define DFSDM_FLTCR1_JEXTSEL_2          (0x4UL << DFSDM_FLTCR1_JEXTSEL_Pos)     /*!< 0x00000400 */
5728 #define DFSDM_FLTCR1_JEXTSEL_1          (0x2UL << DFSDM_FLTCR1_JEXTSEL_Pos)     /*!< 0x00000200 */
5729 #define DFSDM_FLTCR1_JEXTSEL_0          (0x1UL << DFSDM_FLTCR1_JEXTSEL_Pos)     /*!< 0x00000100 */
5730 #define DFSDM_FLTCR1_JDMAEN_Pos         (5U)
5731 #define DFSDM_FLTCR1_JDMAEN_Msk         (0x1UL << DFSDM_FLTCR1_JDMAEN_Pos)      /*!< 0x00000020 */
5732 #define DFSDM_FLTCR1_JDMAEN             DFSDM_FLTCR1_JDMAEN_Msk                /*!< DMA channel enabled to read data for the injected channel group */
5733 #define DFSDM_FLTCR1_JSCAN_Pos          (4U)
5734 #define DFSDM_FLTCR1_JSCAN_Msk          (0x1UL << DFSDM_FLTCR1_JSCAN_Pos)       /*!< 0x00000010 */
5735 #define DFSDM_FLTCR1_JSCAN              DFSDM_FLTCR1_JSCAN_Msk                 /*!< Scanning conversion in continuous mode selection for injected conversions */
5736 #define DFSDM_FLTCR1_JSYNC_Pos          (3U)
5737 #define DFSDM_FLTCR1_JSYNC_Msk          (0x1UL << DFSDM_FLTCR1_JSYNC_Pos)       /*!< 0x00000008 */
5738 #define DFSDM_FLTCR1_JSYNC              DFSDM_FLTCR1_JSYNC_Msk                 /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger  */
5739 #define DFSDM_FLTCR1_JSWSTART_Pos       (1U)
5740 #define DFSDM_FLTCR1_JSWSTART_Msk       (0x1UL << DFSDM_FLTCR1_JSWSTART_Pos)    /*!< 0x00000002 */
5741 #define DFSDM_FLTCR1_JSWSTART           DFSDM_FLTCR1_JSWSTART_Msk              /*!< Start the conversion of the injected group of channels */
5742 #define DFSDM_FLTCR1_DFEN_Pos           (0U)
5743 #define DFSDM_FLTCR1_DFEN_Msk           (0x1UL << DFSDM_FLTCR1_DFEN_Pos)        /*!< 0x00000001 */
5744 #define DFSDM_FLTCR1_DFEN               DFSDM_FLTCR1_DFEN_Msk                  /*!< DFSDM enable */
5745 
5746 /*****************  Bit definition for DFSDM_FLTCR2 register *******************/
5747 #define DFSDM_FLTCR2_AWDCH_Pos          (16U)
5748 #define DFSDM_FLTCR2_AWDCH_Msk          (0xFFUL << DFSDM_FLTCR2_AWDCH_Pos)      /*!< 0x00FF0000 */
5749 #define DFSDM_FLTCR2_AWDCH              DFSDM_FLTCR2_AWDCH_Msk                 /*!< AWDCH[7:0] Analog watchdog channel selection */
5750 #define DFSDM_FLTCR2_EXCH_Pos           (8U)
5751 #define DFSDM_FLTCR2_EXCH_Msk           (0xFFUL << DFSDM_FLTCR2_EXCH_Pos)       /*!< 0x0000FF00 */
5752 #define DFSDM_FLTCR2_EXCH               DFSDM_FLTCR2_EXCH_Msk                  /*!< EXCH[7:0] Extreme detector channel selection */
5753 #define DFSDM_FLTCR2_CKABIE_Pos         (6U)
5754 #define DFSDM_FLTCR2_CKABIE_Msk         (0x1UL << DFSDM_FLTCR2_CKABIE_Pos)      /*!< 0x00000040 */
5755 #define DFSDM_FLTCR2_CKABIE             DFSDM_FLTCR2_CKABIE_Msk                /*!< Clock absence interrupt enable */
5756 #define DFSDM_FLTCR2_SCDIE_Pos          (5U)
5757 #define DFSDM_FLTCR2_SCDIE_Msk          (0x1UL << DFSDM_FLTCR2_SCDIE_Pos)       /*!< 0x00000020 */
5758 #define DFSDM_FLTCR2_SCDIE              DFSDM_FLTCR2_SCDIE_Msk                 /*!< Short circuit detector interrupt enable */
5759 #define DFSDM_FLTCR2_AWDIE_Pos          (4U)
5760 #define DFSDM_FLTCR2_AWDIE_Msk          (0x1UL << DFSDM_FLTCR2_AWDIE_Pos)       /*!< 0x00000010 */
5761 #define DFSDM_FLTCR2_AWDIE              DFSDM_FLTCR2_AWDIE_Msk                 /*!< Analog watchdog interrupt enable */
5762 #define DFSDM_FLTCR2_ROVRIE_Pos         (3U)
5763 #define DFSDM_FLTCR2_ROVRIE_Msk         (0x1UL << DFSDM_FLTCR2_ROVRIE_Pos)      /*!< 0x00000008 */
5764 #define DFSDM_FLTCR2_ROVRIE             DFSDM_FLTCR2_ROVRIE_Msk                /*!< Regular data overrun interrupt enable */
5765 #define DFSDM_FLTCR2_JOVRIE_Pos         (2U)
5766 #define DFSDM_FLTCR2_JOVRIE_Msk         (0x1UL << DFSDM_FLTCR2_JOVRIE_Pos)      /*!< 0x00000004 */
5767 #define DFSDM_FLTCR2_JOVRIE             DFSDM_FLTCR2_JOVRIE_Msk                /*!< Injected data overrun interrupt enable */
5768 #define DFSDM_FLTCR2_REOCIE_Pos         (1U)
5769 #define DFSDM_FLTCR2_REOCIE_Msk         (0x1UL << DFSDM_FLTCR2_REOCIE_Pos)      /*!< 0x00000002 */
5770 #define DFSDM_FLTCR2_REOCIE             DFSDM_FLTCR2_REOCIE_Msk                /*!< Regular end of conversion interrupt enable */
5771 #define DFSDM_FLTCR2_JEOCIE_Pos         (0U)
5772 #define DFSDM_FLTCR2_JEOCIE_Msk         (0x1UL << DFSDM_FLTCR2_JEOCIE_Pos)      /*!< 0x00000001 */
5773 #define DFSDM_FLTCR2_JEOCIE             DFSDM_FLTCR2_JEOCIE_Msk                /*!< Injected end of conversion interrupt enable */
5774 
5775 /*****************  Bit definition for DFSDM_FLTISR register *******************/
5776 #define DFSDM_FLTISR_SCDF_Pos           (24U)
5777 #define DFSDM_FLTISR_SCDF_Msk           (0xFFUL << DFSDM_FLTISR_SCDF_Pos)       /*!< 0xFF000000 */
5778 #define DFSDM_FLTISR_SCDF               DFSDM_FLTISR_SCDF_Msk                  /*!< SCDF[7:0] Short circuit detector flag */
5779 #define DFSDM_FLTISR_CKABF_Pos          (16U)
5780 #define DFSDM_FLTISR_CKABF_Msk          (0xFFUL << DFSDM_FLTISR_CKABF_Pos)      /*!< 0x00FF0000 */
5781 #define DFSDM_FLTISR_CKABF              DFSDM_FLTISR_CKABF_Msk                 /*!< CKABF[7:0] Clock absence flag */
5782 #define DFSDM_FLTISR_RCIP_Pos           (14U)
5783 #define DFSDM_FLTISR_RCIP_Msk           (0x1UL << DFSDM_FLTISR_RCIP_Pos)        /*!< 0x00004000 */
5784 #define DFSDM_FLTISR_RCIP               DFSDM_FLTISR_RCIP_Msk                  /*!< Regular conversion in progress status */
5785 #define DFSDM_FLTISR_JCIP_Pos           (13U)
5786 #define DFSDM_FLTISR_JCIP_Msk           (0x1UL << DFSDM_FLTISR_JCIP_Pos)        /*!< 0x00002000 */
5787 #define DFSDM_FLTISR_JCIP               DFSDM_FLTISR_JCIP_Msk                  /*!< Injected conversion in progress status */
5788 #define DFSDM_FLTISR_AWDF_Pos           (4U)
5789 #define DFSDM_FLTISR_AWDF_Msk           (0x1UL << DFSDM_FLTISR_AWDF_Pos)        /*!< 0x00000010 */
5790 #define DFSDM_FLTISR_AWDF               DFSDM_FLTISR_AWDF_Msk                  /*!< Analog watchdog */
5791 #define DFSDM_FLTISR_ROVRF_Pos          (3U)
5792 #define DFSDM_FLTISR_ROVRF_Msk          (0x1UL << DFSDM_FLTISR_ROVRF_Pos)       /*!< 0x00000008 */
5793 #define DFSDM_FLTISR_ROVRF              DFSDM_FLTISR_ROVRF_Msk                 /*!< Regular conversion overrun flag */
5794 #define DFSDM_FLTISR_JOVRF_Pos          (2U)
5795 #define DFSDM_FLTISR_JOVRF_Msk          (0x1UL << DFSDM_FLTISR_JOVRF_Pos)       /*!< 0x00000004 */
5796 #define DFSDM_FLTISR_JOVRF              DFSDM_FLTISR_JOVRF_Msk                 /*!< Injected conversion overrun flag */
5797 #define DFSDM_FLTISR_REOCF_Pos          (1U)
5798 #define DFSDM_FLTISR_REOCF_Msk          (0x1UL << DFSDM_FLTISR_REOCF_Pos)       /*!< 0x00000002 */
5799 #define DFSDM_FLTISR_REOCF              DFSDM_FLTISR_REOCF_Msk                 /*!< End of regular conversion flag */
5800 #define DFSDM_FLTISR_JEOCF_Pos          (0U)
5801 #define DFSDM_FLTISR_JEOCF_Msk          (0x1UL << DFSDM_FLTISR_JEOCF_Pos)       /*!< 0x00000001 */
5802 #define DFSDM_FLTISR_JEOCF              DFSDM_FLTISR_JEOCF_Msk                 /*!< End of injected conversion flag */
5803 
5804 /*****************  Bit definition for DFSDM_FLTICR register *******************/
5805 #define DFSDM_FLTICR_CLRSCDF_Pos       (24U)
5806 #define DFSDM_FLTICR_CLRSCDF_Msk       (0xFFUL << DFSDM_FLTICR_CLRSCDF_Pos)     /*!< 0xFF000000 */
5807 #define DFSDM_FLTICR_CLRSCDF           DFSDM_FLTICR_CLRSCDF_Msk                /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */
5808 #define DFSDM_FLTICR_CLRCKABF_Pos       (16U)
5809 #define DFSDM_FLTICR_CLRCKABF_Msk       (0xFFUL << DFSDM_FLTICR_CLRCKABF_Pos)   /*!< 0x00FF0000 */
5810 #define DFSDM_FLTICR_CLRCKABF           DFSDM_FLTICR_CLRCKABF_Msk              /*!< CLRCKABF[7:0] Clear the clock absence flag */
5811 #define DFSDM_FLTICR_CLRROVRF_Pos       (3U)
5812 #define DFSDM_FLTICR_CLRROVRF_Msk       (0x1UL << DFSDM_FLTICR_CLRROVRF_Pos)    /*!< 0x00000008 */
5813 #define DFSDM_FLTICR_CLRROVRF           DFSDM_FLTICR_CLRROVRF_Msk              /*!< Clear the regular conversion overrun flag */
5814 #define DFSDM_FLTICR_CLRJOVRF_Pos       (2U)
5815 #define DFSDM_FLTICR_CLRJOVRF_Msk       (0x1UL << DFSDM_FLTICR_CLRJOVRF_Pos)    /*!< 0x00000004 */
5816 #define DFSDM_FLTICR_CLRJOVRF           DFSDM_FLTICR_CLRJOVRF_Msk              /*!< Clear the injected conversion overrun flag */
5817 
5818 /****************  Bit definition for DFSDM_FLTJCHGR register ******************/
5819 #define DFSDM_FLTJCHGR_JCHG_Pos         (0U)
5820 #define DFSDM_FLTJCHGR_JCHG_Msk         (0xFFUL << DFSDM_FLTJCHGR_JCHG_Pos)     /*!< 0x000000FF */
5821 #define DFSDM_FLTJCHGR_JCHG             DFSDM_FLTJCHGR_JCHG_Msk                /*!< JCHG[7:0] Injected channel group selection */
5822 
5823 /*****************  Bit definition for DFSDM_FLTFCR register *******************/
5824 #define DFSDM_FLTFCR_FORD_Pos           (29U)
5825 #define DFSDM_FLTFCR_FORD_Msk           (0x7UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0xE0000000 */
5826 #define DFSDM_FLTFCR_FORD               DFSDM_FLTFCR_FORD_Msk                  /*!< FORD[2:0] Sinc filter order */
5827 #define DFSDM_FLTFCR_FORD_2             (0x4UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x80000000 */
5828 #define DFSDM_FLTFCR_FORD_1             (0x2UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x40000000 */
5829 #define DFSDM_FLTFCR_FORD_0             (0x1UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x20000000 */
5830 #define DFSDM_FLTFCR_FOSR_Pos           (16U)
5831 #define DFSDM_FLTFCR_FOSR_Msk           (0x3FFUL << DFSDM_FLTFCR_FOSR_Pos)      /*!< 0x03FF0000 */
5832 #define DFSDM_FLTFCR_FOSR               DFSDM_FLTFCR_FOSR_Msk                  /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */
5833 #define DFSDM_FLTFCR_IOSR_Pos           (0U)
5834 #define DFSDM_FLTFCR_IOSR_Msk           (0xFFUL << DFSDM_FLTFCR_IOSR_Pos)       /*!< 0x000000FF */
5835 #define DFSDM_FLTFCR_IOSR               DFSDM_FLTFCR_IOSR_Msk                  /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */
5836 
5837 /***************  Bit definition for DFSDM_FLTJDATAR register *****************/
5838 #define DFSDM_FLTJDATAR_JDATA_Pos       (8U)
5839 #define DFSDM_FLTJDATAR_JDATA_Msk       (0xFFFFFFUL << DFSDM_FLTJDATAR_JDATA_Pos) /*!< 0xFFFFFF00 */
5840 #define DFSDM_FLTJDATAR_JDATA           DFSDM_FLTJDATAR_JDATA_Msk              /*!< JDATA[23:0] Injected group conversion data */
5841 #define DFSDM_FLTJDATAR_JDATACH_Pos     (0U)
5842 #define DFSDM_FLTJDATAR_JDATACH_Msk     (0x7UL << DFSDM_FLTJDATAR_JDATACH_Pos)  /*!< 0x00000007 */
5843 #define DFSDM_FLTJDATAR_JDATACH         DFSDM_FLTJDATAR_JDATACH_Msk            /*!< JDATACH[2:0] Injected channel most recently converted */
5844 
5845 /***************  Bit definition for DFSDM_FLTRDATAR register *****************/
5846 #define DFSDM_FLTRDATAR_RDATA_Pos       (8U)
5847 #define DFSDM_FLTRDATAR_RDATA_Msk       (0xFFFFFFUL << DFSDM_FLTRDATAR_RDATA_Pos) /*!< 0xFFFFFF00 */
5848 #define DFSDM_FLTRDATAR_RDATA           DFSDM_FLTRDATAR_RDATA_Msk              /*!< RDATA[23:0] Regular channel conversion data */
5849 #define DFSDM_FLTRDATAR_RPEND_Pos       (4U)
5850 #define DFSDM_FLTRDATAR_RPEND_Msk       (0x1UL << DFSDM_FLTRDATAR_RPEND_Pos)    /*!< 0x00000010 */
5851 #define DFSDM_FLTRDATAR_RPEND           DFSDM_FLTRDATAR_RPEND_Msk              /*!< RPEND Regular channel pending data */
5852 #define DFSDM_FLTRDATAR_RDATACH_Pos     (0U)
5853 #define DFSDM_FLTRDATAR_RDATACH_Msk     (0x7UL << DFSDM_FLTRDATAR_RDATACH_Pos)  /*!< 0x00000007 */
5854 #define DFSDM_FLTRDATAR_RDATACH         DFSDM_FLTRDATAR_RDATACH_Msk            /*!< RDATACH[2:0] Regular channel most recently converted */
5855 
5856 /***************  Bit definition for DFSDM_FLTAWHTR register ******************/
5857 #define DFSDM_FLTAWHTR_AWHT_Pos         (8U)
5858 #define DFSDM_FLTAWHTR_AWHT_Msk         (0xFFFFFFUL << DFSDM_FLTAWHTR_AWHT_Pos) /*!< 0xFFFFFF00 */
5859 #define DFSDM_FLTAWHTR_AWHT             DFSDM_FLTAWHTR_AWHT_Msk                /*!< AWHT[23:0] Analog watchdog high threshold */
5860 #define DFSDM_FLTAWHTR_BKAWH_Pos        (0U)
5861 #define DFSDM_FLTAWHTR_BKAWH_Msk        (0xFUL << DFSDM_FLTAWHTR_BKAWH_Pos)     /*!< 0x0000000F */
5862 #define DFSDM_FLTAWHTR_BKAWH            DFSDM_FLTAWHTR_BKAWH_Msk               /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */
5863 
5864 /***************  Bit definition for DFSDM_FLTAWLTR register ******************/
5865 #define DFSDM_FLTAWLTR_AWLT_Pos         (8U)
5866 #define DFSDM_FLTAWLTR_AWLT_Msk         (0xFFFFFFUL << DFSDM_FLTAWLTR_AWLT_Pos) /*!< 0xFFFFFF00 */
5867 #define DFSDM_FLTAWLTR_AWLT             DFSDM_FLTAWLTR_AWLT_Msk                /*!< AWLT[23:0] Analog watchdog low threshold */
5868 #define DFSDM_FLTAWLTR_BKAWL_Pos        (0U)
5869 #define DFSDM_FLTAWLTR_BKAWL_Msk        (0xFUL << DFSDM_FLTAWLTR_BKAWL_Pos)     /*!< 0x0000000F */
5870 #define DFSDM_FLTAWLTR_BKAWL            DFSDM_FLTAWLTR_BKAWL_Msk               /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */
5871 
5872 /***************  Bit definition for DFSDM_FLTAWSR register *******************/
5873 #define DFSDM_FLTAWSR_AWHTF_Pos         (8U)
5874 #define DFSDM_FLTAWSR_AWHTF_Msk         (0xFFUL << DFSDM_FLTAWSR_AWHTF_Pos)     /*!< 0x0000FF00 */
5875 #define DFSDM_FLTAWSR_AWHTF             DFSDM_FLTAWSR_AWHTF_Msk                /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */
5876 #define DFSDM_FLTAWSR_AWLTF_Pos         (0U)
5877 #define DFSDM_FLTAWSR_AWLTF_Msk         (0xFFUL << DFSDM_FLTAWSR_AWLTF_Pos)     /*!< 0x000000FF */
5878 #define DFSDM_FLTAWSR_AWLTF             DFSDM_FLTAWSR_AWLTF_Msk                /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */
5879 
5880 
5881 /***************  Bit definition for DFSDM_FLTAWCFR register ******************/
5882 #define DFSDM_FLTAWCFR_CLRAWHTF_Pos     (8U)
5883 #define DFSDM_FLTAWCFR_CLRAWHTF_Msk     (0xFFUL << DFSDM_FLTAWCFR_CLRAWHTF_Pos) /*!< 0x0000FF00 */
5884 #define DFSDM_FLTAWCFR_CLRAWHTF         DFSDM_FLTAWCFR_CLRAWHTF_Msk            /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */
5885 #define DFSDM_FLTAWCFR_CLRAWLTF_Pos     (0U)
5886 #define DFSDM_FLTAWCFR_CLRAWLTF_Msk     (0xFFUL << DFSDM_FLTAWCFR_CLRAWLTF_Pos) /*!< 0x000000FF */
5887 #define DFSDM_FLTAWCFR_CLRAWLTF         DFSDM_FLTAWCFR_CLRAWLTF_Msk            /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */
5888 
5889 /***************  Bit definition for DFSDM_FLTEXMAX register ******************/
5890 #define DFSDM_FLTEXMAX_EXMAX_Pos        (8U)
5891 #define DFSDM_FLTEXMAX_EXMAX_Msk        (0xFFFFFFUL << DFSDM_FLTEXMAX_EXMAX_Pos) /*!< 0xFFFFFF00 */
5892 #define DFSDM_FLTEXMAX_EXMAX            DFSDM_FLTEXMAX_EXMAX_Msk               /*!< EXMAX[23:0] Extreme detector maximum value */
5893 #define DFSDM_FLTEXMAX_EXMAXCH_Pos      (0U)
5894 #define DFSDM_FLTEXMAX_EXMAXCH_Msk      (0x7UL << DFSDM_FLTEXMAX_EXMAXCH_Pos)   /*!< 0x00000007 */
5895 #define DFSDM_FLTEXMAX_EXMAXCH          DFSDM_FLTEXMAX_EXMAXCH_Msk             /*!< EXMAXCH[2:0] Extreme detector maximum data channel */
5896 
5897 /***************  Bit definition for DFSDM_FLTEXMIN register ******************/
5898 #define DFSDM_FLTEXMIN_EXMIN_Pos        (8U)
5899 #define DFSDM_FLTEXMIN_EXMIN_Msk        (0xFFFFFFUL << DFSDM_FLTEXMIN_EXMIN_Pos) /*!< 0xFFFFFF00 */
5900 #define DFSDM_FLTEXMIN_EXMIN            DFSDM_FLTEXMIN_EXMIN_Msk               /*!< EXMIN[23:0] Extreme detector minimum value */
5901 #define DFSDM_FLTEXMIN_EXMINCH_Pos      (0U)
5902 #define DFSDM_FLTEXMIN_EXMINCH_Msk      (0x7UL << DFSDM_FLTEXMIN_EXMINCH_Pos)   /*!< 0x00000007 */
5903 #define DFSDM_FLTEXMIN_EXMINCH          DFSDM_FLTEXMIN_EXMINCH_Msk             /*!< EXMINCH[2:0] Extreme detector minimum data channel */
5904 
5905 /***************  Bit definition for DFSDM_FLTCNVTIMR register ****************/
5906 #define DFSDM_FLTCNVTIMR_CNVCNT_Pos     (4U)
5907 #define DFSDM_FLTCNVTIMR_CNVCNT_Msk     (0xFFFFFFFUL << DFSDM_FLTCNVTIMR_CNVCNT_Pos) /*!< 0xFFFFFFF0 */
5908 #define DFSDM_FLTCNVTIMR_CNVCNT         DFSDM_FLTCNVTIMR_CNVCNT_Msk            /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */
5909 
5910 /* Legacy Defines */
5911 #define DFSDM_FLTICR_CLRSCSDF_Pos        DFSDM_FLTICR_CLRSCDF_Pos
5912 #define DFSDM_FLTICR_CLRSCSDF_Msk        DFSDM_FLTICR_CLRSCDF_Msk
5913 #define DFSDM_FLTICR_CLRSCSDF            DFSDM_FLTICR_CLRSCDF
5914 
5915 /******************************************************************************/
5916 /*                                                                            */
5917 /*                             DMA Controller                                 */
5918 /*                                                                            */
5919 /******************************************************************************/
5920 /********************  Bits definition for DMA_SxCR register  *****************/
5921 #define DMA_SxCR_CHSEL_Pos       (25U)
5922 #define DMA_SxCR_CHSEL_Msk       (0xFUL << DMA_SxCR_CHSEL_Pos)                  /*!< 0x1E000000 */
5923 #define DMA_SxCR_CHSEL           DMA_SxCR_CHSEL_Msk
5924 #define DMA_SxCR_CHSEL_0         0x02000000U
5925 #define DMA_SxCR_CHSEL_1         0x04000000U
5926 #define DMA_SxCR_CHSEL_2         0x08000000U
5927 #define DMA_SxCR_CHSEL_3         0x10000000U
5928 #define DMA_SxCR_MBURST_Pos      (23U)
5929 #define DMA_SxCR_MBURST_Msk      (0x3UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x01800000 */
5930 #define DMA_SxCR_MBURST          DMA_SxCR_MBURST_Msk
5931 #define DMA_SxCR_MBURST_0        (0x1UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x00800000 */
5932 #define DMA_SxCR_MBURST_1        (0x2UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x01000000 */
5933 #define DMA_SxCR_PBURST_Pos      (21U)
5934 #define DMA_SxCR_PBURST_Msk      (0x3UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00600000 */
5935 #define DMA_SxCR_PBURST          DMA_SxCR_PBURST_Msk
5936 #define DMA_SxCR_PBURST_0        (0x1UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00200000 */
5937 #define DMA_SxCR_PBURST_1        (0x2UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00400000 */
5938 #define DMA_SxCR_CT_Pos          (19U)
5939 #define DMA_SxCR_CT_Msk          (0x1UL << DMA_SxCR_CT_Pos)                     /*!< 0x00080000 */
5940 #define DMA_SxCR_CT              DMA_SxCR_CT_Msk
5941 #define DMA_SxCR_DBM_Pos         (18U)
5942 #define DMA_SxCR_DBM_Msk         (0x1UL << DMA_SxCR_DBM_Pos)                    /*!< 0x00040000 */
5943 #define DMA_SxCR_DBM             DMA_SxCR_DBM_Msk
5944 #define DMA_SxCR_PL_Pos          (16U)
5945 #define DMA_SxCR_PL_Msk          (0x3UL << DMA_SxCR_PL_Pos)                     /*!< 0x00030000 */
5946 #define DMA_SxCR_PL              DMA_SxCR_PL_Msk
5947 #define DMA_SxCR_PL_0            (0x1UL << DMA_SxCR_PL_Pos)                     /*!< 0x00010000 */
5948 #define DMA_SxCR_PL_1            (0x2UL << DMA_SxCR_PL_Pos)                     /*!< 0x00020000 */
5949 #define DMA_SxCR_PINCOS_Pos      (15U)
5950 #define DMA_SxCR_PINCOS_Msk      (0x1UL << DMA_SxCR_PINCOS_Pos)                 /*!< 0x00008000 */
5951 #define DMA_SxCR_PINCOS          DMA_SxCR_PINCOS_Msk
5952 #define DMA_SxCR_MSIZE_Pos       (13U)
5953 #define DMA_SxCR_MSIZE_Msk       (0x3UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00006000 */
5954 #define DMA_SxCR_MSIZE           DMA_SxCR_MSIZE_Msk
5955 #define DMA_SxCR_MSIZE_0         (0x1UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00002000 */
5956 #define DMA_SxCR_MSIZE_1         (0x2UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00004000 */
5957 #define DMA_SxCR_PSIZE_Pos       (11U)
5958 #define DMA_SxCR_PSIZE_Msk       (0x3UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00001800 */
5959 #define DMA_SxCR_PSIZE           DMA_SxCR_PSIZE_Msk
5960 #define DMA_SxCR_PSIZE_0         (0x1UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00000800 */
5961 #define DMA_SxCR_PSIZE_1         (0x2UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00001000 */
5962 #define DMA_SxCR_MINC_Pos        (10U)
5963 #define DMA_SxCR_MINC_Msk        (0x1UL << DMA_SxCR_MINC_Pos)                   /*!< 0x00000400 */
5964 #define DMA_SxCR_MINC            DMA_SxCR_MINC_Msk
5965 #define DMA_SxCR_PINC_Pos        (9U)
5966 #define DMA_SxCR_PINC_Msk        (0x1UL << DMA_SxCR_PINC_Pos)                   /*!< 0x00000200 */
5967 #define DMA_SxCR_PINC            DMA_SxCR_PINC_Msk
5968 #define DMA_SxCR_CIRC_Pos        (8U)
5969 #define DMA_SxCR_CIRC_Msk        (0x1UL << DMA_SxCR_CIRC_Pos)                   /*!< 0x00000100 */
5970 #define DMA_SxCR_CIRC            DMA_SxCR_CIRC_Msk
5971 #define DMA_SxCR_DIR_Pos         (6U)
5972 #define DMA_SxCR_DIR_Msk         (0x3UL << DMA_SxCR_DIR_Pos)                    /*!< 0x000000C0 */
5973 #define DMA_SxCR_DIR             DMA_SxCR_DIR_Msk
5974 #define DMA_SxCR_DIR_0           (0x1UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000040 */
5975 #define DMA_SxCR_DIR_1           (0x2UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000080 */
5976 #define DMA_SxCR_PFCTRL_Pos      (5U)
5977 #define DMA_SxCR_PFCTRL_Msk      (0x1UL << DMA_SxCR_PFCTRL_Pos)                 /*!< 0x00000020 */
5978 #define DMA_SxCR_PFCTRL          DMA_SxCR_PFCTRL_Msk
5979 #define DMA_SxCR_TCIE_Pos        (4U)
5980 #define DMA_SxCR_TCIE_Msk        (0x1UL << DMA_SxCR_TCIE_Pos)                   /*!< 0x00000010 */
5981 #define DMA_SxCR_TCIE            DMA_SxCR_TCIE_Msk
5982 #define DMA_SxCR_HTIE_Pos        (3U)
5983 #define DMA_SxCR_HTIE_Msk        (0x1UL << DMA_SxCR_HTIE_Pos)                   /*!< 0x00000008 */
5984 #define DMA_SxCR_HTIE            DMA_SxCR_HTIE_Msk
5985 #define DMA_SxCR_TEIE_Pos        (2U)
5986 #define DMA_SxCR_TEIE_Msk        (0x1UL << DMA_SxCR_TEIE_Pos)                   /*!< 0x00000004 */
5987 #define DMA_SxCR_TEIE            DMA_SxCR_TEIE_Msk
5988 #define DMA_SxCR_DMEIE_Pos       (1U)
5989 #define DMA_SxCR_DMEIE_Msk       (0x1UL << DMA_SxCR_DMEIE_Pos)                  /*!< 0x00000002 */
5990 #define DMA_SxCR_DMEIE           DMA_SxCR_DMEIE_Msk
5991 #define DMA_SxCR_EN_Pos          (0U)
5992 #define DMA_SxCR_EN_Msk          (0x1UL << DMA_SxCR_EN_Pos)                     /*!< 0x00000001 */
5993 #define DMA_SxCR_EN              DMA_SxCR_EN_Msk
5994 
5995 /* Legacy defines */
5996 #define DMA_SxCR_ACK_Pos         (20U)
5997 #define DMA_SxCR_ACK_Msk         (0x1UL << DMA_SxCR_ACK_Pos)                    /*!< 0x00100000 */
5998 #define DMA_SxCR_ACK             DMA_SxCR_ACK_Msk
5999 
6000 /********************  Bits definition for DMA_SxCNDTR register  **************/
6001 #define DMA_SxNDT_Pos            (0U)
6002 #define DMA_SxNDT_Msk            (0xFFFFUL << DMA_SxNDT_Pos)                    /*!< 0x0000FFFF */
6003 #define DMA_SxNDT                DMA_SxNDT_Msk
6004 #define DMA_SxNDT_0              (0x0001UL << DMA_SxNDT_Pos)                    /*!< 0x00000001 */
6005 #define DMA_SxNDT_1              (0x0002UL << DMA_SxNDT_Pos)                    /*!< 0x00000002 */
6006 #define DMA_SxNDT_2              (0x0004UL << DMA_SxNDT_Pos)                    /*!< 0x00000004 */
6007 #define DMA_SxNDT_3              (0x0008UL << DMA_SxNDT_Pos)                    /*!< 0x00000008 */
6008 #define DMA_SxNDT_4              (0x0010UL << DMA_SxNDT_Pos)                    /*!< 0x00000010 */
6009 #define DMA_SxNDT_5              (0x0020UL << DMA_SxNDT_Pos)                    /*!< 0x00000020 */
6010 #define DMA_SxNDT_6              (0x0040UL << DMA_SxNDT_Pos)                    /*!< 0x00000040 */
6011 #define DMA_SxNDT_7              (0x0080UL << DMA_SxNDT_Pos)                    /*!< 0x00000080 */
6012 #define DMA_SxNDT_8              (0x0100UL << DMA_SxNDT_Pos)                    /*!< 0x00000100 */
6013 #define DMA_SxNDT_9              (0x0200UL << DMA_SxNDT_Pos)                    /*!< 0x00000200 */
6014 #define DMA_SxNDT_10             (0x0400UL << DMA_SxNDT_Pos)                    /*!< 0x00000400 */
6015 #define DMA_SxNDT_11             (0x0800UL << DMA_SxNDT_Pos)                    /*!< 0x00000800 */
6016 #define DMA_SxNDT_12             (0x1000UL << DMA_SxNDT_Pos)                    /*!< 0x00001000 */
6017 #define DMA_SxNDT_13             (0x2000UL << DMA_SxNDT_Pos)                    /*!< 0x00002000 */
6018 #define DMA_SxNDT_14             (0x4000UL << DMA_SxNDT_Pos)                    /*!< 0x00004000 */
6019 #define DMA_SxNDT_15             (0x8000UL << DMA_SxNDT_Pos)                    /*!< 0x00008000 */
6020 
6021 /********************  Bits definition for DMA_SxFCR register  ****************/
6022 #define DMA_SxFCR_FEIE_Pos       (7U)
6023 #define DMA_SxFCR_FEIE_Msk       (0x1UL << DMA_SxFCR_FEIE_Pos)                  /*!< 0x00000080 */
6024 #define DMA_SxFCR_FEIE           DMA_SxFCR_FEIE_Msk
6025 #define DMA_SxFCR_FS_Pos         (3U)
6026 #define DMA_SxFCR_FS_Msk         (0x7UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000038 */
6027 #define DMA_SxFCR_FS             DMA_SxFCR_FS_Msk
6028 #define DMA_SxFCR_FS_0           (0x1UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000008 */
6029 #define DMA_SxFCR_FS_1           (0x2UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000010 */
6030 #define DMA_SxFCR_FS_2           (0x4UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000020 */
6031 #define DMA_SxFCR_DMDIS_Pos      (2U)
6032 #define DMA_SxFCR_DMDIS_Msk      (0x1UL << DMA_SxFCR_DMDIS_Pos)                 /*!< 0x00000004 */
6033 #define DMA_SxFCR_DMDIS          DMA_SxFCR_DMDIS_Msk
6034 #define DMA_SxFCR_FTH_Pos        (0U)
6035 #define DMA_SxFCR_FTH_Msk        (0x3UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000003 */
6036 #define DMA_SxFCR_FTH            DMA_SxFCR_FTH_Msk
6037 #define DMA_SxFCR_FTH_0          (0x1UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000001 */
6038 #define DMA_SxFCR_FTH_1          (0x2UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000002 */
6039 
6040 /********************  Bits definition for DMA_LISR register  *****************/
6041 #define DMA_LISR_TCIF3_Pos       (27U)
6042 #define DMA_LISR_TCIF3_Msk       (0x1UL << DMA_LISR_TCIF3_Pos)                  /*!< 0x08000000 */
6043 #define DMA_LISR_TCIF3           DMA_LISR_TCIF3_Msk
6044 #define DMA_LISR_HTIF3_Pos       (26U)
6045 #define DMA_LISR_HTIF3_Msk       (0x1UL << DMA_LISR_HTIF3_Pos)                  /*!< 0x04000000 */
6046 #define DMA_LISR_HTIF3           DMA_LISR_HTIF3_Msk
6047 #define DMA_LISR_TEIF3_Pos       (25U)
6048 #define DMA_LISR_TEIF3_Msk       (0x1UL << DMA_LISR_TEIF3_Pos)                  /*!< 0x02000000 */
6049 #define DMA_LISR_TEIF3           DMA_LISR_TEIF3_Msk
6050 #define DMA_LISR_DMEIF3_Pos      (24U)
6051 #define DMA_LISR_DMEIF3_Msk      (0x1UL << DMA_LISR_DMEIF3_Pos)                 /*!< 0x01000000 */
6052 #define DMA_LISR_DMEIF3          DMA_LISR_DMEIF3_Msk
6053 #define DMA_LISR_FEIF3_Pos       (22U)
6054 #define DMA_LISR_FEIF3_Msk       (0x1UL << DMA_LISR_FEIF3_Pos)                  /*!< 0x00400000 */
6055 #define DMA_LISR_FEIF3           DMA_LISR_FEIF3_Msk
6056 #define DMA_LISR_TCIF2_Pos       (21U)
6057 #define DMA_LISR_TCIF2_Msk       (0x1UL << DMA_LISR_TCIF2_Pos)                  /*!< 0x00200000 */
6058 #define DMA_LISR_TCIF2           DMA_LISR_TCIF2_Msk
6059 #define DMA_LISR_HTIF2_Pos       (20U)
6060 #define DMA_LISR_HTIF2_Msk       (0x1UL << DMA_LISR_HTIF2_Pos)                  /*!< 0x00100000 */
6061 #define DMA_LISR_HTIF2           DMA_LISR_HTIF2_Msk
6062 #define DMA_LISR_TEIF2_Pos       (19U)
6063 #define DMA_LISR_TEIF2_Msk       (0x1UL << DMA_LISR_TEIF2_Pos)                  /*!< 0x00080000 */
6064 #define DMA_LISR_TEIF2           DMA_LISR_TEIF2_Msk
6065 #define DMA_LISR_DMEIF2_Pos      (18U)
6066 #define DMA_LISR_DMEIF2_Msk      (0x1UL << DMA_LISR_DMEIF2_Pos)                 /*!< 0x00040000 */
6067 #define DMA_LISR_DMEIF2          DMA_LISR_DMEIF2_Msk
6068 #define DMA_LISR_FEIF2_Pos       (16U)
6069 #define DMA_LISR_FEIF2_Msk       (0x1UL << DMA_LISR_FEIF2_Pos)                  /*!< 0x00010000 */
6070 #define DMA_LISR_FEIF2           DMA_LISR_FEIF2_Msk
6071 #define DMA_LISR_TCIF1_Pos       (11U)
6072 #define DMA_LISR_TCIF1_Msk       (0x1UL << DMA_LISR_TCIF1_Pos)                  /*!< 0x00000800 */
6073 #define DMA_LISR_TCIF1           DMA_LISR_TCIF1_Msk
6074 #define DMA_LISR_HTIF1_Pos       (10U)
6075 #define DMA_LISR_HTIF1_Msk       (0x1UL << DMA_LISR_HTIF1_Pos)                  /*!< 0x00000400 */
6076 #define DMA_LISR_HTIF1           DMA_LISR_HTIF1_Msk
6077 #define DMA_LISR_TEIF1_Pos       (9U)
6078 #define DMA_LISR_TEIF1_Msk       (0x1UL << DMA_LISR_TEIF1_Pos)                  /*!< 0x00000200 */
6079 #define DMA_LISR_TEIF1           DMA_LISR_TEIF1_Msk
6080 #define DMA_LISR_DMEIF1_Pos      (8U)
6081 #define DMA_LISR_DMEIF1_Msk      (0x1UL << DMA_LISR_DMEIF1_Pos)                 /*!< 0x00000100 */
6082 #define DMA_LISR_DMEIF1          DMA_LISR_DMEIF1_Msk
6083 #define DMA_LISR_FEIF1_Pos       (6U)
6084 #define DMA_LISR_FEIF1_Msk       (0x1UL << DMA_LISR_FEIF1_Pos)                  /*!< 0x00000040 */
6085 #define DMA_LISR_FEIF1           DMA_LISR_FEIF1_Msk
6086 #define DMA_LISR_TCIF0_Pos       (5U)
6087 #define DMA_LISR_TCIF0_Msk       (0x1UL << DMA_LISR_TCIF0_Pos)                  /*!< 0x00000020 */
6088 #define DMA_LISR_TCIF0           DMA_LISR_TCIF0_Msk
6089 #define DMA_LISR_HTIF0_Pos       (4U)
6090 #define DMA_LISR_HTIF0_Msk       (0x1UL << DMA_LISR_HTIF0_Pos)                  /*!< 0x00000010 */
6091 #define DMA_LISR_HTIF0           DMA_LISR_HTIF0_Msk
6092 #define DMA_LISR_TEIF0_Pos       (3U)
6093 #define DMA_LISR_TEIF0_Msk       (0x1UL << DMA_LISR_TEIF0_Pos)                  /*!< 0x00000008 */
6094 #define DMA_LISR_TEIF0           DMA_LISR_TEIF0_Msk
6095 #define DMA_LISR_DMEIF0_Pos      (2U)
6096 #define DMA_LISR_DMEIF0_Msk      (0x1UL << DMA_LISR_DMEIF0_Pos)                 /*!< 0x00000004 */
6097 #define DMA_LISR_DMEIF0          DMA_LISR_DMEIF0_Msk
6098 #define DMA_LISR_FEIF0_Pos       (0U)
6099 #define DMA_LISR_FEIF0_Msk       (0x1UL << DMA_LISR_FEIF0_Pos)                  /*!< 0x00000001 */
6100 #define DMA_LISR_FEIF0           DMA_LISR_FEIF0_Msk
6101 
6102 /********************  Bits definition for DMA_HISR register  *****************/
6103 #define DMA_HISR_TCIF7_Pos       (27U)
6104 #define DMA_HISR_TCIF7_Msk       (0x1UL << DMA_HISR_TCIF7_Pos)                  /*!< 0x08000000 */
6105 #define DMA_HISR_TCIF7           DMA_HISR_TCIF7_Msk
6106 #define DMA_HISR_HTIF7_Pos       (26U)
6107 #define DMA_HISR_HTIF7_Msk       (0x1UL << DMA_HISR_HTIF7_Pos)                  /*!< 0x04000000 */
6108 #define DMA_HISR_HTIF7           DMA_HISR_HTIF7_Msk
6109 #define DMA_HISR_TEIF7_Pos       (25U)
6110 #define DMA_HISR_TEIF7_Msk       (0x1UL << DMA_HISR_TEIF7_Pos)                  /*!< 0x02000000 */
6111 #define DMA_HISR_TEIF7           DMA_HISR_TEIF7_Msk
6112 #define DMA_HISR_DMEIF7_Pos      (24U)
6113 #define DMA_HISR_DMEIF7_Msk      (0x1UL << DMA_HISR_DMEIF7_Pos)                 /*!< 0x01000000 */
6114 #define DMA_HISR_DMEIF7          DMA_HISR_DMEIF7_Msk
6115 #define DMA_HISR_FEIF7_Pos       (22U)
6116 #define DMA_HISR_FEIF7_Msk       (0x1UL << DMA_HISR_FEIF7_Pos)                  /*!< 0x00400000 */
6117 #define DMA_HISR_FEIF7           DMA_HISR_FEIF7_Msk
6118 #define DMA_HISR_TCIF6_Pos       (21U)
6119 #define DMA_HISR_TCIF6_Msk       (0x1UL << DMA_HISR_TCIF6_Pos)                  /*!< 0x00200000 */
6120 #define DMA_HISR_TCIF6           DMA_HISR_TCIF6_Msk
6121 #define DMA_HISR_HTIF6_Pos       (20U)
6122 #define DMA_HISR_HTIF6_Msk       (0x1UL << DMA_HISR_HTIF6_Pos)                  /*!< 0x00100000 */
6123 #define DMA_HISR_HTIF6           DMA_HISR_HTIF6_Msk
6124 #define DMA_HISR_TEIF6_Pos       (19U)
6125 #define DMA_HISR_TEIF6_Msk       (0x1UL << DMA_HISR_TEIF6_Pos)                  /*!< 0x00080000 */
6126 #define DMA_HISR_TEIF6           DMA_HISR_TEIF6_Msk
6127 #define DMA_HISR_DMEIF6_Pos      (18U)
6128 #define DMA_HISR_DMEIF6_Msk      (0x1UL << DMA_HISR_DMEIF6_Pos)                 /*!< 0x00040000 */
6129 #define DMA_HISR_DMEIF6          DMA_HISR_DMEIF6_Msk
6130 #define DMA_HISR_FEIF6_Pos       (16U)
6131 #define DMA_HISR_FEIF6_Msk       (0x1UL << DMA_HISR_FEIF6_Pos)                  /*!< 0x00010000 */
6132 #define DMA_HISR_FEIF6           DMA_HISR_FEIF6_Msk
6133 #define DMA_HISR_TCIF5_Pos       (11U)
6134 #define DMA_HISR_TCIF5_Msk       (0x1UL << DMA_HISR_TCIF5_Pos)                  /*!< 0x00000800 */
6135 #define DMA_HISR_TCIF5           DMA_HISR_TCIF5_Msk
6136 #define DMA_HISR_HTIF5_Pos       (10U)
6137 #define DMA_HISR_HTIF5_Msk       (0x1UL << DMA_HISR_HTIF5_Pos)                  /*!< 0x00000400 */
6138 #define DMA_HISR_HTIF5           DMA_HISR_HTIF5_Msk
6139 #define DMA_HISR_TEIF5_Pos       (9U)
6140 #define DMA_HISR_TEIF5_Msk       (0x1UL << DMA_HISR_TEIF5_Pos)                  /*!< 0x00000200 */
6141 #define DMA_HISR_TEIF5           DMA_HISR_TEIF5_Msk
6142 #define DMA_HISR_DMEIF5_Pos      (8U)
6143 #define DMA_HISR_DMEIF5_Msk      (0x1UL << DMA_HISR_DMEIF5_Pos)                 /*!< 0x00000100 */
6144 #define DMA_HISR_DMEIF5          DMA_HISR_DMEIF5_Msk
6145 #define DMA_HISR_FEIF5_Pos       (6U)
6146 #define DMA_HISR_FEIF5_Msk       (0x1UL << DMA_HISR_FEIF5_Pos)                  /*!< 0x00000040 */
6147 #define DMA_HISR_FEIF5           DMA_HISR_FEIF5_Msk
6148 #define DMA_HISR_TCIF4_Pos       (5U)
6149 #define DMA_HISR_TCIF4_Msk       (0x1UL << DMA_HISR_TCIF4_Pos)                  /*!< 0x00000020 */
6150 #define DMA_HISR_TCIF4           DMA_HISR_TCIF4_Msk
6151 #define DMA_HISR_HTIF4_Pos       (4U)
6152 #define DMA_HISR_HTIF4_Msk       (0x1UL << DMA_HISR_HTIF4_Pos)                  /*!< 0x00000010 */
6153 #define DMA_HISR_HTIF4           DMA_HISR_HTIF4_Msk
6154 #define DMA_HISR_TEIF4_Pos       (3U)
6155 #define DMA_HISR_TEIF4_Msk       (0x1UL << DMA_HISR_TEIF4_Pos)                  /*!< 0x00000008 */
6156 #define DMA_HISR_TEIF4           DMA_HISR_TEIF4_Msk
6157 #define DMA_HISR_DMEIF4_Pos      (2U)
6158 #define DMA_HISR_DMEIF4_Msk      (0x1UL << DMA_HISR_DMEIF4_Pos)                 /*!< 0x00000004 */
6159 #define DMA_HISR_DMEIF4          DMA_HISR_DMEIF4_Msk
6160 #define DMA_HISR_FEIF4_Pos       (0U)
6161 #define DMA_HISR_FEIF4_Msk       (0x1UL << DMA_HISR_FEIF4_Pos)                  /*!< 0x00000001 */
6162 #define DMA_HISR_FEIF4           DMA_HISR_FEIF4_Msk
6163 
6164 /********************  Bits definition for DMA_LIFCR register  ****************/
6165 #define DMA_LIFCR_CTCIF3_Pos     (27U)
6166 #define DMA_LIFCR_CTCIF3_Msk     (0x1UL << DMA_LIFCR_CTCIF3_Pos)                /*!< 0x08000000 */
6167 #define DMA_LIFCR_CTCIF3         DMA_LIFCR_CTCIF3_Msk
6168 #define DMA_LIFCR_CHTIF3_Pos     (26U)
6169 #define DMA_LIFCR_CHTIF3_Msk     (0x1UL << DMA_LIFCR_CHTIF3_Pos)                /*!< 0x04000000 */
6170 #define DMA_LIFCR_CHTIF3         DMA_LIFCR_CHTIF3_Msk
6171 #define DMA_LIFCR_CTEIF3_Pos     (25U)
6172 #define DMA_LIFCR_CTEIF3_Msk     (0x1UL << DMA_LIFCR_CTEIF3_Pos)                /*!< 0x02000000 */
6173 #define DMA_LIFCR_CTEIF3         DMA_LIFCR_CTEIF3_Msk
6174 #define DMA_LIFCR_CDMEIF3_Pos    (24U)
6175 #define DMA_LIFCR_CDMEIF3_Msk    (0x1UL << DMA_LIFCR_CDMEIF3_Pos)               /*!< 0x01000000 */
6176 #define DMA_LIFCR_CDMEIF3        DMA_LIFCR_CDMEIF3_Msk
6177 #define DMA_LIFCR_CFEIF3_Pos     (22U)
6178 #define DMA_LIFCR_CFEIF3_Msk     (0x1UL << DMA_LIFCR_CFEIF3_Pos)                /*!< 0x00400000 */
6179 #define DMA_LIFCR_CFEIF3         DMA_LIFCR_CFEIF3_Msk
6180 #define DMA_LIFCR_CTCIF2_Pos     (21U)
6181 #define DMA_LIFCR_CTCIF2_Msk     (0x1UL << DMA_LIFCR_CTCIF2_Pos)                /*!< 0x00200000 */
6182 #define DMA_LIFCR_CTCIF2         DMA_LIFCR_CTCIF2_Msk
6183 #define DMA_LIFCR_CHTIF2_Pos     (20U)
6184 #define DMA_LIFCR_CHTIF2_Msk     (0x1UL << DMA_LIFCR_CHTIF2_Pos)                /*!< 0x00100000 */
6185 #define DMA_LIFCR_CHTIF2         DMA_LIFCR_CHTIF2_Msk
6186 #define DMA_LIFCR_CTEIF2_Pos     (19U)
6187 #define DMA_LIFCR_CTEIF2_Msk     (0x1UL << DMA_LIFCR_CTEIF2_Pos)                /*!< 0x00080000 */
6188 #define DMA_LIFCR_CTEIF2         DMA_LIFCR_CTEIF2_Msk
6189 #define DMA_LIFCR_CDMEIF2_Pos    (18U)
6190 #define DMA_LIFCR_CDMEIF2_Msk    (0x1UL << DMA_LIFCR_CDMEIF2_Pos)               /*!< 0x00040000 */
6191 #define DMA_LIFCR_CDMEIF2        DMA_LIFCR_CDMEIF2_Msk
6192 #define DMA_LIFCR_CFEIF2_Pos     (16U)
6193 #define DMA_LIFCR_CFEIF2_Msk     (0x1UL << DMA_LIFCR_CFEIF2_Pos)                /*!< 0x00010000 */
6194 #define DMA_LIFCR_CFEIF2         DMA_LIFCR_CFEIF2_Msk
6195 #define DMA_LIFCR_CTCIF1_Pos     (11U)
6196 #define DMA_LIFCR_CTCIF1_Msk     (0x1UL << DMA_LIFCR_CTCIF1_Pos)                /*!< 0x00000800 */
6197 #define DMA_LIFCR_CTCIF1         DMA_LIFCR_CTCIF1_Msk
6198 #define DMA_LIFCR_CHTIF1_Pos     (10U)
6199 #define DMA_LIFCR_CHTIF1_Msk     (0x1UL << DMA_LIFCR_CHTIF1_Pos)                /*!< 0x00000400 */
6200 #define DMA_LIFCR_CHTIF1         DMA_LIFCR_CHTIF1_Msk
6201 #define DMA_LIFCR_CTEIF1_Pos     (9U)
6202 #define DMA_LIFCR_CTEIF1_Msk     (0x1UL << DMA_LIFCR_CTEIF1_Pos)                /*!< 0x00000200 */
6203 #define DMA_LIFCR_CTEIF1         DMA_LIFCR_CTEIF1_Msk
6204 #define DMA_LIFCR_CDMEIF1_Pos    (8U)
6205 #define DMA_LIFCR_CDMEIF1_Msk    (0x1UL << DMA_LIFCR_CDMEIF1_Pos)               /*!< 0x00000100 */
6206 #define DMA_LIFCR_CDMEIF1        DMA_LIFCR_CDMEIF1_Msk
6207 #define DMA_LIFCR_CFEIF1_Pos     (6U)
6208 #define DMA_LIFCR_CFEIF1_Msk     (0x1UL << DMA_LIFCR_CFEIF1_Pos)                /*!< 0x00000040 */
6209 #define DMA_LIFCR_CFEIF1         DMA_LIFCR_CFEIF1_Msk
6210 #define DMA_LIFCR_CTCIF0_Pos     (5U)
6211 #define DMA_LIFCR_CTCIF0_Msk     (0x1UL << DMA_LIFCR_CTCIF0_Pos)                /*!< 0x00000020 */
6212 #define DMA_LIFCR_CTCIF0         DMA_LIFCR_CTCIF0_Msk
6213 #define DMA_LIFCR_CHTIF0_Pos     (4U)
6214 #define DMA_LIFCR_CHTIF0_Msk     (0x1UL << DMA_LIFCR_CHTIF0_Pos)                /*!< 0x00000010 */
6215 #define DMA_LIFCR_CHTIF0         DMA_LIFCR_CHTIF0_Msk
6216 #define DMA_LIFCR_CTEIF0_Pos     (3U)
6217 #define DMA_LIFCR_CTEIF0_Msk     (0x1UL << DMA_LIFCR_CTEIF0_Pos)                /*!< 0x00000008 */
6218 #define DMA_LIFCR_CTEIF0         DMA_LIFCR_CTEIF0_Msk
6219 #define DMA_LIFCR_CDMEIF0_Pos    (2U)
6220 #define DMA_LIFCR_CDMEIF0_Msk    (0x1UL << DMA_LIFCR_CDMEIF0_Pos)               /*!< 0x00000004 */
6221 #define DMA_LIFCR_CDMEIF0        DMA_LIFCR_CDMEIF0_Msk
6222 #define DMA_LIFCR_CFEIF0_Pos     (0U)
6223 #define DMA_LIFCR_CFEIF0_Msk     (0x1UL << DMA_LIFCR_CFEIF0_Pos)                /*!< 0x00000001 */
6224 #define DMA_LIFCR_CFEIF0         DMA_LIFCR_CFEIF0_Msk
6225 
6226 /********************  Bits definition for DMA_HIFCR  register  ****************/
6227 #define DMA_HIFCR_CTCIF7_Pos     (27U)
6228 #define DMA_HIFCR_CTCIF7_Msk     (0x1UL << DMA_HIFCR_CTCIF7_Pos)                /*!< 0x08000000 */
6229 #define DMA_HIFCR_CTCIF7         DMA_HIFCR_CTCIF7_Msk
6230 #define DMA_HIFCR_CHTIF7_Pos     (26U)
6231 #define DMA_HIFCR_CHTIF7_Msk     (0x1UL << DMA_HIFCR_CHTIF7_Pos)                /*!< 0x04000000 */
6232 #define DMA_HIFCR_CHTIF7         DMA_HIFCR_CHTIF7_Msk
6233 #define DMA_HIFCR_CTEIF7_Pos     (25U)
6234 #define DMA_HIFCR_CTEIF7_Msk     (0x1UL << DMA_HIFCR_CTEIF7_Pos)                /*!< 0x02000000 */
6235 #define DMA_HIFCR_CTEIF7         DMA_HIFCR_CTEIF7_Msk
6236 #define DMA_HIFCR_CDMEIF7_Pos    (24U)
6237 #define DMA_HIFCR_CDMEIF7_Msk    (0x1UL << DMA_HIFCR_CDMEIF7_Pos)               /*!< 0x01000000 */
6238 #define DMA_HIFCR_CDMEIF7        DMA_HIFCR_CDMEIF7_Msk
6239 #define DMA_HIFCR_CFEIF7_Pos     (22U)
6240 #define DMA_HIFCR_CFEIF7_Msk     (0x1UL << DMA_HIFCR_CFEIF7_Pos)                /*!< 0x00400000 */
6241 #define DMA_HIFCR_CFEIF7         DMA_HIFCR_CFEIF7_Msk
6242 #define DMA_HIFCR_CTCIF6_Pos     (21U)
6243 #define DMA_HIFCR_CTCIF6_Msk     (0x1UL << DMA_HIFCR_CTCIF6_Pos)                /*!< 0x00200000 */
6244 #define DMA_HIFCR_CTCIF6         DMA_HIFCR_CTCIF6_Msk
6245 #define DMA_HIFCR_CHTIF6_Pos     (20U)
6246 #define DMA_HIFCR_CHTIF6_Msk     (0x1UL << DMA_HIFCR_CHTIF6_Pos)                /*!< 0x00100000 */
6247 #define DMA_HIFCR_CHTIF6         DMA_HIFCR_CHTIF6_Msk
6248 #define DMA_HIFCR_CTEIF6_Pos     (19U)
6249 #define DMA_HIFCR_CTEIF6_Msk     (0x1UL << DMA_HIFCR_CTEIF6_Pos)                /*!< 0x00080000 */
6250 #define DMA_HIFCR_CTEIF6         DMA_HIFCR_CTEIF6_Msk
6251 #define DMA_HIFCR_CDMEIF6_Pos    (18U)
6252 #define DMA_HIFCR_CDMEIF6_Msk    (0x1UL << DMA_HIFCR_CDMEIF6_Pos)               /*!< 0x00040000 */
6253 #define DMA_HIFCR_CDMEIF6        DMA_HIFCR_CDMEIF6_Msk
6254 #define DMA_HIFCR_CFEIF6_Pos     (16U)
6255 #define DMA_HIFCR_CFEIF6_Msk     (0x1UL << DMA_HIFCR_CFEIF6_Pos)                /*!< 0x00010000 */
6256 #define DMA_HIFCR_CFEIF6         DMA_HIFCR_CFEIF6_Msk
6257 #define DMA_HIFCR_CTCIF5_Pos     (11U)
6258 #define DMA_HIFCR_CTCIF5_Msk     (0x1UL << DMA_HIFCR_CTCIF5_Pos)                /*!< 0x00000800 */
6259 #define DMA_HIFCR_CTCIF5         DMA_HIFCR_CTCIF5_Msk
6260 #define DMA_HIFCR_CHTIF5_Pos     (10U)
6261 #define DMA_HIFCR_CHTIF5_Msk     (0x1UL << DMA_HIFCR_CHTIF5_Pos)                /*!< 0x00000400 */
6262 #define DMA_HIFCR_CHTIF5         DMA_HIFCR_CHTIF5_Msk
6263 #define DMA_HIFCR_CTEIF5_Pos     (9U)
6264 #define DMA_HIFCR_CTEIF5_Msk     (0x1UL << DMA_HIFCR_CTEIF5_Pos)                /*!< 0x00000200 */
6265 #define DMA_HIFCR_CTEIF5         DMA_HIFCR_CTEIF5_Msk
6266 #define DMA_HIFCR_CDMEIF5_Pos    (8U)
6267 #define DMA_HIFCR_CDMEIF5_Msk    (0x1UL << DMA_HIFCR_CDMEIF5_Pos)               /*!< 0x00000100 */
6268 #define DMA_HIFCR_CDMEIF5        DMA_HIFCR_CDMEIF5_Msk
6269 #define DMA_HIFCR_CFEIF5_Pos     (6U)
6270 #define DMA_HIFCR_CFEIF5_Msk     (0x1UL << DMA_HIFCR_CFEIF5_Pos)                /*!< 0x00000040 */
6271 #define DMA_HIFCR_CFEIF5         DMA_HIFCR_CFEIF5_Msk
6272 #define DMA_HIFCR_CTCIF4_Pos     (5U)
6273 #define DMA_HIFCR_CTCIF4_Msk     (0x1UL << DMA_HIFCR_CTCIF4_Pos)                /*!< 0x00000020 */
6274 #define DMA_HIFCR_CTCIF4         DMA_HIFCR_CTCIF4_Msk
6275 #define DMA_HIFCR_CHTIF4_Pos     (4U)
6276 #define DMA_HIFCR_CHTIF4_Msk     (0x1UL << DMA_HIFCR_CHTIF4_Pos)                /*!< 0x00000010 */
6277 #define DMA_HIFCR_CHTIF4         DMA_HIFCR_CHTIF4_Msk
6278 #define DMA_HIFCR_CTEIF4_Pos     (3U)
6279 #define DMA_HIFCR_CTEIF4_Msk     (0x1UL << DMA_HIFCR_CTEIF4_Pos)                /*!< 0x00000008 */
6280 #define DMA_HIFCR_CTEIF4         DMA_HIFCR_CTEIF4_Msk
6281 #define DMA_HIFCR_CDMEIF4_Pos    (2U)
6282 #define DMA_HIFCR_CDMEIF4_Msk    (0x1UL << DMA_HIFCR_CDMEIF4_Pos)               /*!< 0x00000004 */
6283 #define DMA_HIFCR_CDMEIF4        DMA_HIFCR_CDMEIF4_Msk
6284 #define DMA_HIFCR_CFEIF4_Pos     (0U)
6285 #define DMA_HIFCR_CFEIF4_Msk     (0x1UL << DMA_HIFCR_CFEIF4_Pos)                /*!< 0x00000001 */
6286 #define DMA_HIFCR_CFEIF4         DMA_HIFCR_CFEIF4_Msk
6287 
6288 /******************  Bit definition for DMA_SxPAR register  ********************/
6289 #define DMA_SxPAR_PA_Pos         (0U)
6290 #define DMA_SxPAR_PA_Msk         (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos)             /*!< 0xFFFFFFFF */
6291 #define DMA_SxPAR_PA             DMA_SxPAR_PA_Msk                              /*!< Peripheral Address */
6292 
6293 /******************  Bit definition for DMA_SxM0AR register  ********************/
6294 #define DMA_SxM0AR_M0A_Pos       (0U)
6295 #define DMA_SxM0AR_M0A_Msk       (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos)           /*!< 0xFFFFFFFF */
6296 #define DMA_SxM0AR_M0A           DMA_SxM0AR_M0A_Msk                            /*!< Memory Address */
6297 
6298 /******************  Bit definition for DMA_SxM1AR register  ********************/
6299 #define DMA_SxM1AR_M1A_Pos       (0U)
6300 #define DMA_SxM1AR_M1A_Msk       (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos)           /*!< 0xFFFFFFFF */
6301 #define DMA_SxM1AR_M1A           DMA_SxM1AR_M1A_Msk                            /*!< Memory Address */
6302 
6303 
6304 /******************************************************************************/
6305 /*                                                                            */
6306 /*                    External Interrupt/Event Controller                     */
6307 /*                                                                            */
6308 /******************************************************************************/
6309 /*******************  Bit definition for EXTI_IMR register  *******************/
6310 #define EXTI_IMR_MR0_Pos          (0U)
6311 #define EXTI_IMR_MR0_Msk          (0x1UL << EXTI_IMR_MR0_Pos)                   /*!< 0x00000001 */
6312 #define EXTI_IMR_MR0              EXTI_IMR_MR0_Msk                             /*!< Interrupt Mask on line 0 */
6313 #define EXTI_IMR_MR1_Pos          (1U)
6314 #define EXTI_IMR_MR1_Msk          (0x1UL << EXTI_IMR_MR1_Pos)                   /*!< 0x00000002 */
6315 #define EXTI_IMR_MR1              EXTI_IMR_MR1_Msk                             /*!< Interrupt Mask on line 1 */
6316 #define EXTI_IMR_MR2_Pos          (2U)
6317 #define EXTI_IMR_MR2_Msk          (0x1UL << EXTI_IMR_MR2_Pos)                   /*!< 0x00000004 */
6318 #define EXTI_IMR_MR2              EXTI_IMR_MR2_Msk                             /*!< Interrupt Mask on line 2 */
6319 #define EXTI_IMR_MR3_Pos          (3U)
6320 #define EXTI_IMR_MR3_Msk          (0x1UL << EXTI_IMR_MR3_Pos)                   /*!< 0x00000008 */
6321 #define EXTI_IMR_MR3              EXTI_IMR_MR3_Msk                             /*!< Interrupt Mask on line 3 */
6322 #define EXTI_IMR_MR4_Pos          (4U)
6323 #define EXTI_IMR_MR4_Msk          (0x1UL << EXTI_IMR_MR4_Pos)                   /*!< 0x00000010 */
6324 #define EXTI_IMR_MR4              EXTI_IMR_MR4_Msk                             /*!< Interrupt Mask on line 4 */
6325 #define EXTI_IMR_MR5_Pos          (5U)
6326 #define EXTI_IMR_MR5_Msk          (0x1UL << EXTI_IMR_MR5_Pos)                   /*!< 0x00000020 */
6327 #define EXTI_IMR_MR5              EXTI_IMR_MR5_Msk                             /*!< Interrupt Mask on line 5 */
6328 #define EXTI_IMR_MR6_Pos          (6U)
6329 #define EXTI_IMR_MR6_Msk          (0x1UL << EXTI_IMR_MR6_Pos)                   /*!< 0x00000040 */
6330 #define EXTI_IMR_MR6              EXTI_IMR_MR6_Msk                             /*!< Interrupt Mask on line 6 */
6331 #define EXTI_IMR_MR7_Pos          (7U)
6332 #define EXTI_IMR_MR7_Msk          (0x1UL << EXTI_IMR_MR7_Pos)                   /*!< 0x00000080 */
6333 #define EXTI_IMR_MR7              EXTI_IMR_MR7_Msk                             /*!< Interrupt Mask on line 7 */
6334 #define EXTI_IMR_MR8_Pos          (8U)
6335 #define EXTI_IMR_MR8_Msk          (0x1UL << EXTI_IMR_MR8_Pos)                   /*!< 0x00000100 */
6336 #define EXTI_IMR_MR8              EXTI_IMR_MR8_Msk                             /*!< Interrupt Mask on line 8 */
6337 #define EXTI_IMR_MR9_Pos          (9U)
6338 #define EXTI_IMR_MR9_Msk          (0x1UL << EXTI_IMR_MR9_Pos)                   /*!< 0x00000200 */
6339 #define EXTI_IMR_MR9              EXTI_IMR_MR9_Msk                             /*!< Interrupt Mask on line 9 */
6340 #define EXTI_IMR_MR10_Pos         (10U)
6341 #define EXTI_IMR_MR10_Msk         (0x1UL << EXTI_IMR_MR10_Pos)                  /*!< 0x00000400 */
6342 #define EXTI_IMR_MR10             EXTI_IMR_MR10_Msk                            /*!< Interrupt Mask on line 10 */
6343 #define EXTI_IMR_MR11_Pos         (11U)
6344 #define EXTI_IMR_MR11_Msk         (0x1UL << EXTI_IMR_MR11_Pos)                  /*!< 0x00000800 */
6345 #define EXTI_IMR_MR11             EXTI_IMR_MR11_Msk                            /*!< Interrupt Mask on line 11 */
6346 #define EXTI_IMR_MR12_Pos         (12U)
6347 #define EXTI_IMR_MR12_Msk         (0x1UL << EXTI_IMR_MR12_Pos)                  /*!< 0x00001000 */
6348 #define EXTI_IMR_MR12             EXTI_IMR_MR12_Msk                            /*!< Interrupt Mask on line 12 */
6349 #define EXTI_IMR_MR13_Pos         (13U)
6350 #define EXTI_IMR_MR13_Msk         (0x1UL << EXTI_IMR_MR13_Pos)                  /*!< 0x00002000 */
6351 #define EXTI_IMR_MR13             EXTI_IMR_MR13_Msk                            /*!< Interrupt Mask on line 13 */
6352 #define EXTI_IMR_MR14_Pos         (14U)
6353 #define EXTI_IMR_MR14_Msk         (0x1UL << EXTI_IMR_MR14_Pos)                  /*!< 0x00004000 */
6354 #define EXTI_IMR_MR14             EXTI_IMR_MR14_Msk                            /*!< Interrupt Mask on line 14 */
6355 #define EXTI_IMR_MR15_Pos         (15U)
6356 #define EXTI_IMR_MR15_Msk         (0x1UL << EXTI_IMR_MR15_Pos)                  /*!< 0x00008000 */
6357 #define EXTI_IMR_MR15             EXTI_IMR_MR15_Msk                            /*!< Interrupt Mask on line 15 */
6358 #define EXTI_IMR_MR16_Pos         (16U)
6359 #define EXTI_IMR_MR16_Msk         (0x1UL << EXTI_IMR_MR16_Pos)                  /*!< 0x00010000 */
6360 #define EXTI_IMR_MR16             EXTI_IMR_MR16_Msk                            /*!< Interrupt Mask on line 16 */
6361 #define EXTI_IMR_MR17_Pos         (17U)
6362 #define EXTI_IMR_MR17_Msk         (0x1UL << EXTI_IMR_MR17_Pos)                  /*!< 0x00020000 */
6363 #define EXTI_IMR_MR17             EXTI_IMR_MR17_Msk                            /*!< Interrupt Mask on line 17 */
6364 #define EXTI_IMR_MR18_Pos         (18U)
6365 #define EXTI_IMR_MR18_Msk         (0x1UL << EXTI_IMR_MR18_Pos)                  /*!< 0x00040000 */
6366 #define EXTI_IMR_MR18             EXTI_IMR_MR18_Msk                            /*!< Interrupt Mask on line 18 */
6367 #define EXTI_IMR_MR19_Pos         (19U)
6368 #define EXTI_IMR_MR19_Msk         (0x1UL << EXTI_IMR_MR19_Pos)                  /*!< 0x00080000 */
6369 #define EXTI_IMR_MR19             EXTI_IMR_MR19_Msk                            /*!< Interrupt Mask on line 19 */
6370 #define EXTI_IMR_MR20_Pos         (20U)
6371 #define EXTI_IMR_MR20_Msk         (0x1UL << EXTI_IMR_MR20_Pos)                  /*!< 0x00100000 */
6372 #define EXTI_IMR_MR20             EXTI_IMR_MR20_Msk                            /*!< Interrupt Mask on line 20 */
6373 #define EXTI_IMR_MR21_Pos         (21U)
6374 #define EXTI_IMR_MR21_Msk         (0x1UL << EXTI_IMR_MR21_Pos)                  /*!< 0x00200000 */
6375 #define EXTI_IMR_MR21             EXTI_IMR_MR21_Msk                            /*!< Interrupt Mask on line 21 */
6376 #define EXTI_IMR_MR22_Pos         (22U)
6377 #define EXTI_IMR_MR22_Msk         (0x1UL << EXTI_IMR_MR22_Pos)                  /*!< 0x00400000 */
6378 #define EXTI_IMR_MR22             EXTI_IMR_MR22_Msk                            /*!< Interrupt Mask on line 22 */
6379 #define EXTI_IMR_MR23_Pos         (23U)
6380 #define EXTI_IMR_MR23_Msk         (0x1UL << EXTI_IMR_MR23_Pos)                  /*!< 0x00800000 */
6381 #define EXTI_IMR_MR23             EXTI_IMR_MR23_Msk                            /*!< Interrupt Mask on line 23 */
6382 
6383 /* Reference Defines */
6384 #define  EXTI_IMR_IM0                        EXTI_IMR_MR0
6385 #define  EXTI_IMR_IM1                        EXTI_IMR_MR1
6386 #define  EXTI_IMR_IM2                        EXTI_IMR_MR2
6387 #define  EXTI_IMR_IM3                        EXTI_IMR_MR3
6388 #define  EXTI_IMR_IM4                        EXTI_IMR_MR4
6389 #define  EXTI_IMR_IM5                        EXTI_IMR_MR5
6390 #define  EXTI_IMR_IM6                        EXTI_IMR_MR6
6391 #define  EXTI_IMR_IM7                        EXTI_IMR_MR7
6392 #define  EXTI_IMR_IM8                        EXTI_IMR_MR8
6393 #define  EXTI_IMR_IM9                        EXTI_IMR_MR9
6394 #define  EXTI_IMR_IM10                       EXTI_IMR_MR10
6395 #define  EXTI_IMR_IM11                       EXTI_IMR_MR11
6396 #define  EXTI_IMR_IM12                       EXTI_IMR_MR12
6397 #define  EXTI_IMR_IM13                       EXTI_IMR_MR13
6398 #define  EXTI_IMR_IM14                       EXTI_IMR_MR14
6399 #define  EXTI_IMR_IM15                       EXTI_IMR_MR15
6400 #define  EXTI_IMR_IM16                       EXTI_IMR_MR16
6401 #define  EXTI_IMR_IM17                       EXTI_IMR_MR17
6402 #define  EXTI_IMR_IM18                       EXTI_IMR_MR18
6403 #define  EXTI_IMR_IM19                       EXTI_IMR_MR19
6404 #define  EXTI_IMR_IM20                       EXTI_IMR_MR20
6405 #define  EXTI_IMR_IM21                       EXTI_IMR_MR21
6406 #define  EXTI_IMR_IM22                       EXTI_IMR_MR22
6407 #define  EXTI_IMR_IM23                       EXTI_IMR_MR23
6408 #define EXTI_IMR_IM_Pos           (0U)
6409 #define EXTI_IMR_IM_Msk           (0xFFFFFFUL << EXTI_IMR_IM_Pos)               /*!< 0x00FFFFFF */
6410 #define EXTI_IMR_IM               EXTI_IMR_IM_Msk                              /*!< Interrupt Mask All */
6411 
6412 /*******************  Bit definition for EXTI_EMR register  *******************/
6413 #define EXTI_EMR_MR0_Pos          (0U)
6414 #define EXTI_EMR_MR0_Msk          (0x1UL << EXTI_EMR_MR0_Pos)                   /*!< 0x00000001 */
6415 #define EXTI_EMR_MR0              EXTI_EMR_MR0_Msk                             /*!< Event Mask on line 0 */
6416 #define EXTI_EMR_MR1_Pos          (1U)
6417 #define EXTI_EMR_MR1_Msk          (0x1UL << EXTI_EMR_MR1_Pos)                   /*!< 0x00000002 */
6418 #define EXTI_EMR_MR1              EXTI_EMR_MR1_Msk                             /*!< Event Mask on line 1 */
6419 #define EXTI_EMR_MR2_Pos          (2U)
6420 #define EXTI_EMR_MR2_Msk          (0x1UL << EXTI_EMR_MR2_Pos)                   /*!< 0x00000004 */
6421 #define EXTI_EMR_MR2              EXTI_EMR_MR2_Msk                             /*!< Event Mask on line 2 */
6422 #define EXTI_EMR_MR3_Pos          (3U)
6423 #define EXTI_EMR_MR3_Msk          (0x1UL << EXTI_EMR_MR3_Pos)                   /*!< 0x00000008 */
6424 #define EXTI_EMR_MR3              EXTI_EMR_MR3_Msk                             /*!< Event Mask on line 3 */
6425 #define EXTI_EMR_MR4_Pos          (4U)
6426 #define EXTI_EMR_MR4_Msk          (0x1UL << EXTI_EMR_MR4_Pos)                   /*!< 0x00000010 */
6427 #define EXTI_EMR_MR4              EXTI_EMR_MR4_Msk                             /*!< Event Mask on line 4 */
6428 #define EXTI_EMR_MR5_Pos          (5U)
6429 #define EXTI_EMR_MR5_Msk          (0x1UL << EXTI_EMR_MR5_Pos)                   /*!< 0x00000020 */
6430 #define EXTI_EMR_MR5              EXTI_EMR_MR5_Msk                             /*!< Event Mask on line 5 */
6431 #define EXTI_EMR_MR6_Pos          (6U)
6432 #define EXTI_EMR_MR6_Msk          (0x1UL << EXTI_EMR_MR6_Pos)                   /*!< 0x00000040 */
6433 #define EXTI_EMR_MR6              EXTI_EMR_MR6_Msk                             /*!< Event Mask on line 6 */
6434 #define EXTI_EMR_MR7_Pos          (7U)
6435 #define EXTI_EMR_MR7_Msk          (0x1UL << EXTI_EMR_MR7_Pos)                   /*!< 0x00000080 */
6436 #define EXTI_EMR_MR7              EXTI_EMR_MR7_Msk                             /*!< Event Mask on line 7 */
6437 #define EXTI_EMR_MR8_Pos          (8U)
6438 #define EXTI_EMR_MR8_Msk          (0x1UL << EXTI_EMR_MR8_Pos)                   /*!< 0x00000100 */
6439 #define EXTI_EMR_MR8              EXTI_EMR_MR8_Msk                             /*!< Event Mask on line 8 */
6440 #define EXTI_EMR_MR9_Pos          (9U)
6441 #define EXTI_EMR_MR9_Msk          (0x1UL << EXTI_EMR_MR9_Pos)                   /*!< 0x00000200 */
6442 #define EXTI_EMR_MR9              EXTI_EMR_MR9_Msk                             /*!< Event Mask on line 9 */
6443 #define EXTI_EMR_MR10_Pos         (10U)
6444 #define EXTI_EMR_MR10_Msk         (0x1UL << EXTI_EMR_MR10_Pos)                  /*!< 0x00000400 */
6445 #define EXTI_EMR_MR10             EXTI_EMR_MR10_Msk                            /*!< Event Mask on line 10 */
6446 #define EXTI_EMR_MR11_Pos         (11U)
6447 #define EXTI_EMR_MR11_Msk         (0x1UL << EXTI_EMR_MR11_Pos)                  /*!< 0x00000800 */
6448 #define EXTI_EMR_MR11             EXTI_EMR_MR11_Msk                            /*!< Event Mask on line 11 */
6449 #define EXTI_EMR_MR12_Pos         (12U)
6450 #define EXTI_EMR_MR12_Msk         (0x1UL << EXTI_EMR_MR12_Pos)                  /*!< 0x00001000 */
6451 #define EXTI_EMR_MR12             EXTI_EMR_MR12_Msk                            /*!< Event Mask on line 12 */
6452 #define EXTI_EMR_MR13_Pos         (13U)
6453 #define EXTI_EMR_MR13_Msk         (0x1UL << EXTI_EMR_MR13_Pos)                  /*!< 0x00002000 */
6454 #define EXTI_EMR_MR13             EXTI_EMR_MR13_Msk                            /*!< Event Mask on line 13 */
6455 #define EXTI_EMR_MR14_Pos         (14U)
6456 #define EXTI_EMR_MR14_Msk         (0x1UL << EXTI_EMR_MR14_Pos)                  /*!< 0x00004000 */
6457 #define EXTI_EMR_MR14             EXTI_EMR_MR14_Msk                            /*!< Event Mask on line 14 */
6458 #define EXTI_EMR_MR15_Pos         (15U)
6459 #define EXTI_EMR_MR15_Msk         (0x1UL << EXTI_EMR_MR15_Pos)                  /*!< 0x00008000 */
6460 #define EXTI_EMR_MR15             EXTI_EMR_MR15_Msk                            /*!< Event Mask on line 15 */
6461 #define EXTI_EMR_MR16_Pos         (16U)
6462 #define EXTI_EMR_MR16_Msk         (0x1UL << EXTI_EMR_MR16_Pos)                  /*!< 0x00010000 */
6463 #define EXTI_EMR_MR16             EXTI_EMR_MR16_Msk                            /*!< Event Mask on line 16 */
6464 #define EXTI_EMR_MR17_Pos         (17U)
6465 #define EXTI_EMR_MR17_Msk         (0x1UL << EXTI_EMR_MR17_Pos)                  /*!< 0x00020000 */
6466 #define EXTI_EMR_MR17             EXTI_EMR_MR17_Msk                            /*!< Event Mask on line 17 */
6467 #define EXTI_EMR_MR18_Pos         (18U)
6468 #define EXTI_EMR_MR18_Msk         (0x1UL << EXTI_EMR_MR18_Pos)                  /*!< 0x00040000 */
6469 #define EXTI_EMR_MR18             EXTI_EMR_MR18_Msk                            /*!< Event Mask on line 18 */
6470 #define EXTI_EMR_MR19_Pos         (19U)
6471 #define EXTI_EMR_MR19_Msk         (0x1UL << EXTI_EMR_MR19_Pos)                  /*!< 0x00080000 */
6472 #define EXTI_EMR_MR19             EXTI_EMR_MR19_Msk                            /*!< Event Mask on line 19 */
6473 #define EXTI_EMR_MR20_Pos         (20U)
6474 #define EXTI_EMR_MR20_Msk         (0x1UL << EXTI_EMR_MR20_Pos)                  /*!< 0x00100000 */
6475 #define EXTI_EMR_MR20             EXTI_EMR_MR20_Msk                            /*!< Event Mask on line 20 */
6476 #define EXTI_EMR_MR21_Pos         (21U)
6477 #define EXTI_EMR_MR21_Msk         (0x1UL << EXTI_EMR_MR21_Pos)                  /*!< 0x00200000 */
6478 #define EXTI_EMR_MR21             EXTI_EMR_MR21_Msk                            /*!< Event Mask on line 21 */
6479 #define EXTI_EMR_MR22_Pos         (22U)
6480 #define EXTI_EMR_MR22_Msk         (0x1UL << EXTI_EMR_MR22_Pos)                  /*!< 0x00400000 */
6481 #define EXTI_EMR_MR22             EXTI_EMR_MR22_Msk                            /*!< Event Mask on line 22 */
6482 #define EXTI_EMR_MR23_Pos         (23U)
6483 #define EXTI_EMR_MR23_Msk         (0x1UL << EXTI_EMR_MR23_Pos)                  /*!< 0x00800000 */
6484 #define EXTI_EMR_MR23             EXTI_EMR_MR23_Msk                            /*!< Event Mask on line 23 */
6485 
6486 /* Reference Defines */
6487 #define  EXTI_EMR_EM0                        EXTI_EMR_MR0
6488 #define  EXTI_EMR_EM1                        EXTI_EMR_MR1
6489 #define  EXTI_EMR_EM2                        EXTI_EMR_MR2
6490 #define  EXTI_EMR_EM3                        EXTI_EMR_MR3
6491 #define  EXTI_EMR_EM4                        EXTI_EMR_MR4
6492 #define  EXTI_EMR_EM5                        EXTI_EMR_MR5
6493 #define  EXTI_EMR_EM6                        EXTI_EMR_MR6
6494 #define  EXTI_EMR_EM7                        EXTI_EMR_MR7
6495 #define  EXTI_EMR_EM8                        EXTI_EMR_MR8
6496 #define  EXTI_EMR_EM9                        EXTI_EMR_MR9
6497 #define  EXTI_EMR_EM10                       EXTI_EMR_MR10
6498 #define  EXTI_EMR_EM11                       EXTI_EMR_MR11
6499 #define  EXTI_EMR_EM12                       EXTI_EMR_MR12
6500 #define  EXTI_EMR_EM13                       EXTI_EMR_MR13
6501 #define  EXTI_EMR_EM14                       EXTI_EMR_MR14
6502 #define  EXTI_EMR_EM15                       EXTI_EMR_MR15
6503 #define  EXTI_EMR_EM16                       EXTI_EMR_MR16
6504 #define  EXTI_EMR_EM17                       EXTI_EMR_MR17
6505 #define  EXTI_EMR_EM18                       EXTI_EMR_MR18
6506 #define  EXTI_EMR_EM19                       EXTI_EMR_MR19
6507 #define  EXTI_EMR_EM20                       EXTI_EMR_MR20
6508 #define  EXTI_EMR_EM21                       EXTI_EMR_MR21
6509 #define  EXTI_EMR_EM22                       EXTI_EMR_MR22
6510 #define  EXTI_EMR_EM23                       EXTI_EMR_MR23
6511 
6512 /******************  Bit definition for EXTI_RTSR register  *******************/
6513 #define EXTI_RTSR_TR0_Pos         (0U)
6514 #define EXTI_RTSR_TR0_Msk         (0x1UL << EXTI_RTSR_TR0_Pos)                  /*!< 0x00000001 */
6515 #define EXTI_RTSR_TR0             EXTI_RTSR_TR0_Msk                            /*!< Rising trigger event configuration bit of line 0 */
6516 #define EXTI_RTSR_TR1_Pos         (1U)
6517 #define EXTI_RTSR_TR1_Msk         (0x1UL << EXTI_RTSR_TR1_Pos)                  /*!< 0x00000002 */
6518 #define EXTI_RTSR_TR1             EXTI_RTSR_TR1_Msk                            /*!< Rising trigger event configuration bit of line 1 */
6519 #define EXTI_RTSR_TR2_Pos         (2U)
6520 #define EXTI_RTSR_TR2_Msk         (0x1UL << EXTI_RTSR_TR2_Pos)                  /*!< 0x00000004 */
6521 #define EXTI_RTSR_TR2             EXTI_RTSR_TR2_Msk                            /*!< Rising trigger event configuration bit of line 2 */
6522 #define EXTI_RTSR_TR3_Pos         (3U)
6523 #define EXTI_RTSR_TR3_Msk         (0x1UL << EXTI_RTSR_TR3_Pos)                  /*!< 0x00000008 */
6524 #define EXTI_RTSR_TR3             EXTI_RTSR_TR3_Msk                            /*!< Rising trigger event configuration bit of line 3 */
6525 #define EXTI_RTSR_TR4_Pos         (4U)
6526 #define EXTI_RTSR_TR4_Msk         (0x1UL << EXTI_RTSR_TR4_Pos)                  /*!< 0x00000010 */
6527 #define EXTI_RTSR_TR4             EXTI_RTSR_TR4_Msk                            /*!< Rising trigger event configuration bit of line 4 */
6528 #define EXTI_RTSR_TR5_Pos         (5U)
6529 #define EXTI_RTSR_TR5_Msk         (0x1UL << EXTI_RTSR_TR5_Pos)                  /*!< 0x00000020 */
6530 #define EXTI_RTSR_TR5             EXTI_RTSR_TR5_Msk                            /*!< Rising trigger event configuration bit of line 5 */
6531 #define EXTI_RTSR_TR6_Pos         (6U)
6532 #define EXTI_RTSR_TR6_Msk         (0x1UL << EXTI_RTSR_TR6_Pos)                  /*!< 0x00000040 */
6533 #define EXTI_RTSR_TR6             EXTI_RTSR_TR6_Msk                            /*!< Rising trigger event configuration bit of line 6 */
6534 #define EXTI_RTSR_TR7_Pos         (7U)
6535 #define EXTI_RTSR_TR7_Msk         (0x1UL << EXTI_RTSR_TR7_Pos)                  /*!< 0x00000080 */
6536 #define EXTI_RTSR_TR7             EXTI_RTSR_TR7_Msk                            /*!< Rising trigger event configuration bit of line 7 */
6537 #define EXTI_RTSR_TR8_Pos         (8U)
6538 #define EXTI_RTSR_TR8_Msk         (0x1UL << EXTI_RTSR_TR8_Pos)                  /*!< 0x00000100 */
6539 #define EXTI_RTSR_TR8             EXTI_RTSR_TR8_Msk                            /*!< Rising trigger event configuration bit of line 8 */
6540 #define EXTI_RTSR_TR9_Pos         (9U)
6541 #define EXTI_RTSR_TR9_Msk         (0x1UL << EXTI_RTSR_TR9_Pos)                  /*!< 0x00000200 */
6542 #define EXTI_RTSR_TR9             EXTI_RTSR_TR9_Msk                            /*!< Rising trigger event configuration bit of line 9 */
6543 #define EXTI_RTSR_TR10_Pos        (10U)
6544 #define EXTI_RTSR_TR10_Msk        (0x1UL << EXTI_RTSR_TR10_Pos)                 /*!< 0x00000400 */
6545 #define EXTI_RTSR_TR10            EXTI_RTSR_TR10_Msk                           /*!< Rising trigger event configuration bit of line 10 */
6546 #define EXTI_RTSR_TR11_Pos        (11U)
6547 #define EXTI_RTSR_TR11_Msk        (0x1UL << EXTI_RTSR_TR11_Pos)                 /*!< 0x00000800 */
6548 #define EXTI_RTSR_TR11            EXTI_RTSR_TR11_Msk                           /*!< Rising trigger event configuration bit of line 11 */
6549 #define EXTI_RTSR_TR12_Pos        (12U)
6550 #define EXTI_RTSR_TR12_Msk        (0x1UL << EXTI_RTSR_TR12_Pos)                 /*!< 0x00001000 */
6551 #define EXTI_RTSR_TR12            EXTI_RTSR_TR12_Msk                           /*!< Rising trigger event configuration bit of line 12 */
6552 #define EXTI_RTSR_TR13_Pos        (13U)
6553 #define EXTI_RTSR_TR13_Msk        (0x1UL << EXTI_RTSR_TR13_Pos)                 /*!< 0x00002000 */
6554 #define EXTI_RTSR_TR13            EXTI_RTSR_TR13_Msk                           /*!< Rising trigger event configuration bit of line 13 */
6555 #define EXTI_RTSR_TR14_Pos        (14U)
6556 #define EXTI_RTSR_TR14_Msk        (0x1UL << EXTI_RTSR_TR14_Pos)                 /*!< 0x00004000 */
6557 #define EXTI_RTSR_TR14            EXTI_RTSR_TR14_Msk                           /*!< Rising trigger event configuration bit of line 14 */
6558 #define EXTI_RTSR_TR15_Pos        (15U)
6559 #define EXTI_RTSR_TR15_Msk        (0x1UL << EXTI_RTSR_TR15_Pos)                 /*!< 0x00008000 */
6560 #define EXTI_RTSR_TR15            EXTI_RTSR_TR15_Msk                           /*!< Rising trigger event configuration bit of line 15 */
6561 #define EXTI_RTSR_TR16_Pos        (16U)
6562 #define EXTI_RTSR_TR16_Msk        (0x1UL << EXTI_RTSR_TR16_Pos)                 /*!< 0x00010000 */
6563 #define EXTI_RTSR_TR16            EXTI_RTSR_TR16_Msk                           /*!< Rising trigger event configuration bit of line 16 */
6564 #define EXTI_RTSR_TR17_Pos        (17U)
6565 #define EXTI_RTSR_TR17_Msk        (0x1UL << EXTI_RTSR_TR17_Pos)                 /*!< 0x00020000 */
6566 #define EXTI_RTSR_TR17            EXTI_RTSR_TR17_Msk                           /*!< Rising trigger event configuration bit of line 17 */
6567 #define EXTI_RTSR_TR18_Pos        (18U)
6568 #define EXTI_RTSR_TR18_Msk        (0x1UL << EXTI_RTSR_TR18_Pos)                 /*!< 0x00040000 */
6569 #define EXTI_RTSR_TR18            EXTI_RTSR_TR18_Msk                           /*!< Rising trigger event configuration bit of line 18 */
6570 #define EXTI_RTSR_TR19_Pos        (19U)
6571 #define EXTI_RTSR_TR19_Msk        (0x1UL << EXTI_RTSR_TR19_Pos)                 /*!< 0x00080000 */
6572 #define EXTI_RTSR_TR19            EXTI_RTSR_TR19_Msk                           /*!< Rising trigger event configuration bit of line 19 */
6573 #define EXTI_RTSR_TR20_Pos        (20U)
6574 #define EXTI_RTSR_TR20_Msk        (0x1UL << EXTI_RTSR_TR20_Pos)                 /*!< 0x00100000 */
6575 #define EXTI_RTSR_TR20            EXTI_RTSR_TR20_Msk                           /*!< Rising trigger event configuration bit of line 20 */
6576 #define EXTI_RTSR_TR21_Pos        (21U)
6577 #define EXTI_RTSR_TR21_Msk        (0x1UL << EXTI_RTSR_TR21_Pos)                 /*!< 0x00200000 */
6578 #define EXTI_RTSR_TR21            EXTI_RTSR_TR21_Msk                           /*!< Rising trigger event configuration bit of line 21 */
6579 #define EXTI_RTSR_TR22_Pos        (22U)
6580 #define EXTI_RTSR_TR22_Msk        (0x1UL << EXTI_RTSR_TR22_Pos)                 /*!< 0x00400000 */
6581 #define EXTI_RTSR_TR22            EXTI_RTSR_TR22_Msk                           /*!< Rising trigger event configuration bit of line 22 */
6582 #define EXTI_RTSR_TR23_Pos        (23U)
6583 #define EXTI_RTSR_TR23_Msk        (0x1UL << EXTI_RTSR_TR23_Pos)                 /*!< 0x00800000 */
6584 #define EXTI_RTSR_TR23            EXTI_RTSR_TR23_Msk                           /*!< Rising trigger event configuration bit of line 23 */
6585 
6586 /******************  Bit definition for EXTI_FTSR register  *******************/
6587 #define EXTI_FTSR_TR0_Pos         (0U)
6588 #define EXTI_FTSR_TR0_Msk         (0x1UL << EXTI_FTSR_TR0_Pos)                  /*!< 0x00000001 */
6589 #define EXTI_FTSR_TR0             EXTI_FTSR_TR0_Msk                            /*!< Falling trigger event configuration bit of line 0 */
6590 #define EXTI_FTSR_TR1_Pos         (1U)
6591 #define EXTI_FTSR_TR1_Msk         (0x1UL << EXTI_FTSR_TR1_Pos)                  /*!< 0x00000002 */
6592 #define EXTI_FTSR_TR1             EXTI_FTSR_TR1_Msk                            /*!< Falling trigger event configuration bit of line 1 */
6593 #define EXTI_FTSR_TR2_Pos         (2U)
6594 #define EXTI_FTSR_TR2_Msk         (0x1UL << EXTI_FTSR_TR2_Pos)                  /*!< 0x00000004 */
6595 #define EXTI_FTSR_TR2             EXTI_FTSR_TR2_Msk                            /*!< Falling trigger event configuration bit of line 2 */
6596 #define EXTI_FTSR_TR3_Pos         (3U)
6597 #define EXTI_FTSR_TR3_Msk         (0x1UL << EXTI_FTSR_TR3_Pos)                  /*!< 0x00000008 */
6598 #define EXTI_FTSR_TR3             EXTI_FTSR_TR3_Msk                            /*!< Falling trigger event configuration bit of line 3 */
6599 #define EXTI_FTSR_TR4_Pos         (4U)
6600 #define EXTI_FTSR_TR4_Msk         (0x1UL << EXTI_FTSR_TR4_Pos)                  /*!< 0x00000010 */
6601 #define EXTI_FTSR_TR4             EXTI_FTSR_TR4_Msk                            /*!< Falling trigger event configuration bit of line 4 */
6602 #define EXTI_FTSR_TR5_Pos         (5U)
6603 #define EXTI_FTSR_TR5_Msk         (0x1UL << EXTI_FTSR_TR5_Pos)                  /*!< 0x00000020 */
6604 #define EXTI_FTSR_TR5             EXTI_FTSR_TR5_Msk                            /*!< Falling trigger event configuration bit of line 5 */
6605 #define EXTI_FTSR_TR6_Pos         (6U)
6606 #define EXTI_FTSR_TR6_Msk         (0x1UL << EXTI_FTSR_TR6_Pos)                  /*!< 0x00000040 */
6607 #define EXTI_FTSR_TR6             EXTI_FTSR_TR6_Msk                            /*!< Falling trigger event configuration bit of line 6 */
6608 #define EXTI_FTSR_TR7_Pos         (7U)
6609 #define EXTI_FTSR_TR7_Msk         (0x1UL << EXTI_FTSR_TR7_Pos)                  /*!< 0x00000080 */
6610 #define EXTI_FTSR_TR7             EXTI_FTSR_TR7_Msk                            /*!< Falling trigger event configuration bit of line 7 */
6611 #define EXTI_FTSR_TR8_Pos         (8U)
6612 #define EXTI_FTSR_TR8_Msk         (0x1UL << EXTI_FTSR_TR8_Pos)                  /*!< 0x00000100 */
6613 #define EXTI_FTSR_TR8             EXTI_FTSR_TR8_Msk                            /*!< Falling trigger event configuration bit of line 8 */
6614 #define EXTI_FTSR_TR9_Pos         (9U)
6615 #define EXTI_FTSR_TR9_Msk         (0x1UL << EXTI_FTSR_TR9_Pos)                  /*!< 0x00000200 */
6616 #define EXTI_FTSR_TR9             EXTI_FTSR_TR9_Msk                            /*!< Falling trigger event configuration bit of line 9 */
6617 #define EXTI_FTSR_TR10_Pos        (10U)
6618 #define EXTI_FTSR_TR10_Msk        (0x1UL << EXTI_FTSR_TR10_Pos)                 /*!< 0x00000400 */
6619 #define EXTI_FTSR_TR10            EXTI_FTSR_TR10_Msk                           /*!< Falling trigger event configuration bit of line 10 */
6620 #define EXTI_FTSR_TR11_Pos        (11U)
6621 #define EXTI_FTSR_TR11_Msk        (0x1UL << EXTI_FTSR_TR11_Pos)                 /*!< 0x00000800 */
6622 #define EXTI_FTSR_TR11            EXTI_FTSR_TR11_Msk                           /*!< Falling trigger event configuration bit of line 11 */
6623 #define EXTI_FTSR_TR12_Pos        (12U)
6624 #define EXTI_FTSR_TR12_Msk        (0x1UL << EXTI_FTSR_TR12_Pos)                 /*!< 0x00001000 */
6625 #define EXTI_FTSR_TR12            EXTI_FTSR_TR12_Msk                           /*!< Falling trigger event configuration bit of line 12 */
6626 #define EXTI_FTSR_TR13_Pos        (13U)
6627 #define EXTI_FTSR_TR13_Msk        (0x1UL << EXTI_FTSR_TR13_Pos)                 /*!< 0x00002000 */
6628 #define EXTI_FTSR_TR13            EXTI_FTSR_TR13_Msk                           /*!< Falling trigger event configuration bit of line 13 */
6629 #define EXTI_FTSR_TR14_Pos        (14U)
6630 #define EXTI_FTSR_TR14_Msk        (0x1UL << EXTI_FTSR_TR14_Pos)                 /*!< 0x00004000 */
6631 #define EXTI_FTSR_TR14            EXTI_FTSR_TR14_Msk                           /*!< Falling trigger event configuration bit of line 14 */
6632 #define EXTI_FTSR_TR15_Pos        (15U)
6633 #define EXTI_FTSR_TR15_Msk        (0x1UL << EXTI_FTSR_TR15_Pos)                 /*!< 0x00008000 */
6634 #define EXTI_FTSR_TR15            EXTI_FTSR_TR15_Msk                           /*!< Falling trigger event configuration bit of line 15 */
6635 #define EXTI_FTSR_TR16_Pos        (16U)
6636 #define EXTI_FTSR_TR16_Msk        (0x1UL << EXTI_FTSR_TR16_Pos)                 /*!< 0x00010000 */
6637 #define EXTI_FTSR_TR16            EXTI_FTSR_TR16_Msk                           /*!< Falling trigger event configuration bit of line 16 */
6638 #define EXTI_FTSR_TR17_Pos        (17U)
6639 #define EXTI_FTSR_TR17_Msk        (0x1UL << EXTI_FTSR_TR17_Pos)                 /*!< 0x00020000 */
6640 #define EXTI_FTSR_TR17            EXTI_FTSR_TR17_Msk                           /*!< Falling trigger event configuration bit of line 17 */
6641 #define EXTI_FTSR_TR18_Pos        (18U)
6642 #define EXTI_FTSR_TR18_Msk        (0x1UL << EXTI_FTSR_TR18_Pos)                 /*!< 0x00040000 */
6643 #define EXTI_FTSR_TR18            EXTI_FTSR_TR18_Msk                           /*!< Falling trigger event configuration bit of line 18 */
6644 #define EXTI_FTSR_TR19_Pos        (19U)
6645 #define EXTI_FTSR_TR19_Msk        (0x1UL << EXTI_FTSR_TR19_Pos)                 /*!< 0x00080000 */
6646 #define EXTI_FTSR_TR19            EXTI_FTSR_TR19_Msk                           /*!< Falling trigger event configuration bit of line 19 */
6647 #define EXTI_FTSR_TR20_Pos        (20U)
6648 #define EXTI_FTSR_TR20_Msk        (0x1UL << EXTI_FTSR_TR20_Pos)                 /*!< 0x00100000 */
6649 #define EXTI_FTSR_TR20            EXTI_FTSR_TR20_Msk                           /*!< Falling trigger event configuration bit of line 20 */
6650 #define EXTI_FTSR_TR21_Pos        (21U)
6651 #define EXTI_FTSR_TR21_Msk        (0x1UL << EXTI_FTSR_TR21_Pos)                 /*!< 0x00200000 */
6652 #define EXTI_FTSR_TR21            EXTI_FTSR_TR21_Msk                           /*!< Falling trigger event configuration bit of line 21 */
6653 #define EXTI_FTSR_TR22_Pos        (22U)
6654 #define EXTI_FTSR_TR22_Msk        (0x1UL << EXTI_FTSR_TR22_Pos)                 /*!< 0x00400000 */
6655 #define EXTI_FTSR_TR22            EXTI_FTSR_TR22_Msk                           /*!< Falling trigger event configuration bit of line 22 */
6656 #define EXTI_FTSR_TR23_Pos        (23U)
6657 #define EXTI_FTSR_TR23_Msk        (0x1UL << EXTI_FTSR_TR23_Pos)                 /*!< 0x00800000 */
6658 #define EXTI_FTSR_TR23            EXTI_FTSR_TR23_Msk                           /*!< Falling trigger event configuration bit of line 23 */
6659 
6660 /******************  Bit definition for EXTI_SWIER register  ******************/
6661 #define EXTI_SWIER_SWIER0_Pos     (0U)
6662 #define EXTI_SWIER_SWIER0_Msk     (0x1UL << EXTI_SWIER_SWIER0_Pos)              /*!< 0x00000001 */
6663 #define EXTI_SWIER_SWIER0         EXTI_SWIER_SWIER0_Msk                        /*!< Software Interrupt on line 0 */
6664 #define EXTI_SWIER_SWIER1_Pos     (1U)
6665 #define EXTI_SWIER_SWIER1_Msk     (0x1UL << EXTI_SWIER_SWIER1_Pos)              /*!< 0x00000002 */
6666 #define EXTI_SWIER_SWIER1         EXTI_SWIER_SWIER1_Msk                        /*!< Software Interrupt on line 1 */
6667 #define EXTI_SWIER_SWIER2_Pos     (2U)
6668 #define EXTI_SWIER_SWIER2_Msk     (0x1UL << EXTI_SWIER_SWIER2_Pos)              /*!< 0x00000004 */
6669 #define EXTI_SWIER_SWIER2         EXTI_SWIER_SWIER2_Msk                        /*!< Software Interrupt on line 2 */
6670 #define EXTI_SWIER_SWIER3_Pos     (3U)
6671 #define EXTI_SWIER_SWIER3_Msk     (0x1UL << EXTI_SWIER_SWIER3_Pos)              /*!< 0x00000008 */
6672 #define EXTI_SWIER_SWIER3         EXTI_SWIER_SWIER3_Msk                        /*!< Software Interrupt on line 3 */
6673 #define EXTI_SWIER_SWIER4_Pos     (4U)
6674 #define EXTI_SWIER_SWIER4_Msk     (0x1UL << EXTI_SWIER_SWIER4_Pos)              /*!< 0x00000010 */
6675 #define EXTI_SWIER_SWIER4         EXTI_SWIER_SWIER4_Msk                        /*!< Software Interrupt on line 4 */
6676 #define EXTI_SWIER_SWIER5_Pos     (5U)
6677 #define EXTI_SWIER_SWIER5_Msk     (0x1UL << EXTI_SWIER_SWIER5_Pos)              /*!< 0x00000020 */
6678 #define EXTI_SWIER_SWIER5         EXTI_SWIER_SWIER5_Msk                        /*!< Software Interrupt on line 5 */
6679 #define EXTI_SWIER_SWIER6_Pos     (6U)
6680 #define EXTI_SWIER_SWIER6_Msk     (0x1UL << EXTI_SWIER_SWIER6_Pos)              /*!< 0x00000040 */
6681 #define EXTI_SWIER_SWIER6         EXTI_SWIER_SWIER6_Msk                        /*!< Software Interrupt on line 6 */
6682 #define EXTI_SWIER_SWIER7_Pos     (7U)
6683 #define EXTI_SWIER_SWIER7_Msk     (0x1UL << EXTI_SWIER_SWIER7_Pos)              /*!< 0x00000080 */
6684 #define EXTI_SWIER_SWIER7         EXTI_SWIER_SWIER7_Msk                        /*!< Software Interrupt on line 7 */
6685 #define EXTI_SWIER_SWIER8_Pos     (8U)
6686 #define EXTI_SWIER_SWIER8_Msk     (0x1UL << EXTI_SWIER_SWIER8_Pos)              /*!< 0x00000100 */
6687 #define EXTI_SWIER_SWIER8         EXTI_SWIER_SWIER8_Msk                        /*!< Software Interrupt on line 8 */
6688 #define EXTI_SWIER_SWIER9_Pos     (9U)
6689 #define EXTI_SWIER_SWIER9_Msk     (0x1UL << EXTI_SWIER_SWIER9_Pos)              /*!< 0x00000200 */
6690 #define EXTI_SWIER_SWIER9         EXTI_SWIER_SWIER9_Msk                        /*!< Software Interrupt on line 9 */
6691 #define EXTI_SWIER_SWIER10_Pos    (10U)
6692 #define EXTI_SWIER_SWIER10_Msk    (0x1UL << EXTI_SWIER_SWIER10_Pos)             /*!< 0x00000400 */
6693 #define EXTI_SWIER_SWIER10        EXTI_SWIER_SWIER10_Msk                       /*!< Software Interrupt on line 10 */
6694 #define EXTI_SWIER_SWIER11_Pos    (11U)
6695 #define EXTI_SWIER_SWIER11_Msk    (0x1UL << EXTI_SWIER_SWIER11_Pos)             /*!< 0x00000800 */
6696 #define EXTI_SWIER_SWIER11        EXTI_SWIER_SWIER11_Msk                       /*!< Software Interrupt on line 11 */
6697 #define EXTI_SWIER_SWIER12_Pos    (12U)
6698 #define EXTI_SWIER_SWIER12_Msk    (0x1UL << EXTI_SWIER_SWIER12_Pos)             /*!< 0x00001000 */
6699 #define EXTI_SWIER_SWIER12        EXTI_SWIER_SWIER12_Msk                       /*!< Software Interrupt on line 12 */
6700 #define EXTI_SWIER_SWIER13_Pos    (13U)
6701 #define EXTI_SWIER_SWIER13_Msk    (0x1UL << EXTI_SWIER_SWIER13_Pos)             /*!< 0x00002000 */
6702 #define EXTI_SWIER_SWIER13        EXTI_SWIER_SWIER13_Msk                       /*!< Software Interrupt on line 13 */
6703 #define EXTI_SWIER_SWIER14_Pos    (14U)
6704 #define EXTI_SWIER_SWIER14_Msk    (0x1UL << EXTI_SWIER_SWIER14_Pos)             /*!< 0x00004000 */
6705 #define EXTI_SWIER_SWIER14        EXTI_SWIER_SWIER14_Msk                       /*!< Software Interrupt on line 14 */
6706 #define EXTI_SWIER_SWIER15_Pos    (15U)
6707 #define EXTI_SWIER_SWIER15_Msk    (0x1UL << EXTI_SWIER_SWIER15_Pos)             /*!< 0x00008000 */
6708 #define EXTI_SWIER_SWIER15        EXTI_SWIER_SWIER15_Msk                       /*!< Software Interrupt on line 15 */
6709 #define EXTI_SWIER_SWIER16_Pos    (16U)
6710 #define EXTI_SWIER_SWIER16_Msk    (0x1UL << EXTI_SWIER_SWIER16_Pos)             /*!< 0x00010000 */
6711 #define EXTI_SWIER_SWIER16        EXTI_SWIER_SWIER16_Msk                       /*!< Software Interrupt on line 16 */
6712 #define EXTI_SWIER_SWIER17_Pos    (17U)
6713 #define EXTI_SWIER_SWIER17_Msk    (0x1UL << EXTI_SWIER_SWIER17_Pos)             /*!< 0x00020000 */
6714 #define EXTI_SWIER_SWIER17        EXTI_SWIER_SWIER17_Msk                       /*!< Software Interrupt on line 17 */
6715 #define EXTI_SWIER_SWIER18_Pos    (18U)
6716 #define EXTI_SWIER_SWIER18_Msk    (0x1UL << EXTI_SWIER_SWIER18_Pos)             /*!< 0x00040000 */
6717 #define EXTI_SWIER_SWIER18        EXTI_SWIER_SWIER18_Msk                       /*!< Software Interrupt on line 18 */
6718 #define EXTI_SWIER_SWIER19_Pos    (19U)
6719 #define EXTI_SWIER_SWIER19_Msk    (0x1UL << EXTI_SWIER_SWIER19_Pos)             /*!< 0x00080000 */
6720 #define EXTI_SWIER_SWIER19        EXTI_SWIER_SWIER19_Msk                       /*!< Software Interrupt on line 19 */
6721 #define EXTI_SWIER_SWIER20_Pos    (20U)
6722 #define EXTI_SWIER_SWIER20_Msk    (0x1UL << EXTI_SWIER_SWIER20_Pos)             /*!< 0x00100000 */
6723 #define EXTI_SWIER_SWIER20        EXTI_SWIER_SWIER20_Msk                       /*!< Software Interrupt on line 20 */
6724 #define EXTI_SWIER_SWIER21_Pos    (21U)
6725 #define EXTI_SWIER_SWIER21_Msk    (0x1UL << EXTI_SWIER_SWIER21_Pos)             /*!< 0x00200000 */
6726 #define EXTI_SWIER_SWIER21        EXTI_SWIER_SWIER21_Msk                       /*!< Software Interrupt on line 21 */
6727 #define EXTI_SWIER_SWIER22_Pos    (22U)
6728 #define EXTI_SWIER_SWIER22_Msk    (0x1UL << EXTI_SWIER_SWIER22_Pos)             /*!< 0x00400000 */
6729 #define EXTI_SWIER_SWIER22        EXTI_SWIER_SWIER22_Msk                       /*!< Software Interrupt on line 22 */
6730 #define EXTI_SWIER_SWIER23_Pos    (23U)
6731 #define EXTI_SWIER_SWIER23_Msk    (0x1UL << EXTI_SWIER_SWIER23_Pos)             /*!< 0x00800000 */
6732 #define EXTI_SWIER_SWIER23        EXTI_SWIER_SWIER23_Msk                       /*!< Software Interrupt on line 23 */
6733 
6734 /*******************  Bit definition for EXTI_PR register  ********************/
6735 #define EXTI_PR_PR0_Pos           (0U)
6736 #define EXTI_PR_PR0_Msk           (0x1UL << EXTI_PR_PR0_Pos)                    /*!< 0x00000001 */
6737 #define EXTI_PR_PR0               EXTI_PR_PR0_Msk                              /*!< Pending bit for line 0 */
6738 #define EXTI_PR_PR1_Pos           (1U)
6739 #define EXTI_PR_PR1_Msk           (0x1UL << EXTI_PR_PR1_Pos)                    /*!< 0x00000002 */
6740 #define EXTI_PR_PR1               EXTI_PR_PR1_Msk                              /*!< Pending bit for line 1 */
6741 #define EXTI_PR_PR2_Pos           (2U)
6742 #define EXTI_PR_PR2_Msk           (0x1UL << EXTI_PR_PR2_Pos)                    /*!< 0x00000004 */
6743 #define EXTI_PR_PR2               EXTI_PR_PR2_Msk                              /*!< Pending bit for line 2 */
6744 #define EXTI_PR_PR3_Pos           (3U)
6745 #define EXTI_PR_PR3_Msk           (0x1UL << EXTI_PR_PR3_Pos)                    /*!< 0x00000008 */
6746 #define EXTI_PR_PR3               EXTI_PR_PR3_Msk                              /*!< Pending bit for line 3 */
6747 #define EXTI_PR_PR4_Pos           (4U)
6748 #define EXTI_PR_PR4_Msk           (0x1UL << EXTI_PR_PR4_Pos)                    /*!< 0x00000010 */
6749 #define EXTI_PR_PR4               EXTI_PR_PR4_Msk                              /*!< Pending bit for line 4 */
6750 #define EXTI_PR_PR5_Pos           (5U)
6751 #define EXTI_PR_PR5_Msk           (0x1UL << EXTI_PR_PR5_Pos)                    /*!< 0x00000020 */
6752 #define EXTI_PR_PR5               EXTI_PR_PR5_Msk                              /*!< Pending bit for line 5 */
6753 #define EXTI_PR_PR6_Pos           (6U)
6754 #define EXTI_PR_PR6_Msk           (0x1UL << EXTI_PR_PR6_Pos)                    /*!< 0x00000040 */
6755 #define EXTI_PR_PR6               EXTI_PR_PR6_Msk                              /*!< Pending bit for line 6 */
6756 #define EXTI_PR_PR7_Pos           (7U)
6757 #define EXTI_PR_PR7_Msk           (0x1UL << EXTI_PR_PR7_Pos)                    /*!< 0x00000080 */
6758 #define EXTI_PR_PR7               EXTI_PR_PR7_Msk                              /*!< Pending bit for line 7 */
6759 #define EXTI_PR_PR8_Pos           (8U)
6760 #define EXTI_PR_PR8_Msk           (0x1UL << EXTI_PR_PR8_Pos)                    /*!< 0x00000100 */
6761 #define EXTI_PR_PR8               EXTI_PR_PR8_Msk                              /*!< Pending bit for line 8 */
6762 #define EXTI_PR_PR9_Pos           (9U)
6763 #define EXTI_PR_PR9_Msk           (0x1UL << EXTI_PR_PR9_Pos)                    /*!< 0x00000200 */
6764 #define EXTI_PR_PR9               EXTI_PR_PR9_Msk                              /*!< Pending bit for line 9 */
6765 #define EXTI_PR_PR10_Pos          (10U)
6766 #define EXTI_PR_PR10_Msk          (0x1UL << EXTI_PR_PR10_Pos)                   /*!< 0x00000400 */
6767 #define EXTI_PR_PR10              EXTI_PR_PR10_Msk                             /*!< Pending bit for line 10 */
6768 #define EXTI_PR_PR11_Pos          (11U)
6769 #define EXTI_PR_PR11_Msk          (0x1UL << EXTI_PR_PR11_Pos)                   /*!< 0x00000800 */
6770 #define EXTI_PR_PR11              EXTI_PR_PR11_Msk                             /*!< Pending bit for line 11 */
6771 #define EXTI_PR_PR12_Pos          (12U)
6772 #define EXTI_PR_PR12_Msk          (0x1UL << EXTI_PR_PR12_Pos)                   /*!< 0x00001000 */
6773 #define EXTI_PR_PR12              EXTI_PR_PR12_Msk                             /*!< Pending bit for line 12 */
6774 #define EXTI_PR_PR13_Pos          (13U)
6775 #define EXTI_PR_PR13_Msk          (0x1UL << EXTI_PR_PR13_Pos)                   /*!< 0x00002000 */
6776 #define EXTI_PR_PR13              EXTI_PR_PR13_Msk                             /*!< Pending bit for line 13 */
6777 #define EXTI_PR_PR14_Pos          (14U)
6778 #define EXTI_PR_PR14_Msk          (0x1UL << EXTI_PR_PR14_Pos)                   /*!< 0x00004000 */
6779 #define EXTI_PR_PR14              EXTI_PR_PR14_Msk                             /*!< Pending bit for line 14 */
6780 #define EXTI_PR_PR15_Pos          (15U)
6781 #define EXTI_PR_PR15_Msk          (0x1UL << EXTI_PR_PR15_Pos)                   /*!< 0x00008000 */
6782 #define EXTI_PR_PR15              EXTI_PR_PR15_Msk                             /*!< Pending bit for line 15 */
6783 #define EXTI_PR_PR16_Pos          (16U)
6784 #define EXTI_PR_PR16_Msk          (0x1UL << EXTI_PR_PR16_Pos)                   /*!< 0x00010000 */
6785 #define EXTI_PR_PR16              EXTI_PR_PR16_Msk                             /*!< Pending bit for line 16 */
6786 #define EXTI_PR_PR17_Pos          (17U)
6787 #define EXTI_PR_PR17_Msk          (0x1UL << EXTI_PR_PR17_Pos)                   /*!< 0x00020000 */
6788 #define EXTI_PR_PR17              EXTI_PR_PR17_Msk                             /*!< Pending bit for line 17 */
6789 #define EXTI_PR_PR18_Pos          (18U)
6790 #define EXTI_PR_PR18_Msk          (0x1UL << EXTI_PR_PR18_Pos)                   /*!< 0x00040000 */
6791 #define EXTI_PR_PR18              EXTI_PR_PR18_Msk                             /*!< Pending bit for line 18 */
6792 #define EXTI_PR_PR19_Pos          (19U)
6793 #define EXTI_PR_PR19_Msk          (0x1UL << EXTI_PR_PR19_Pos)                   /*!< 0x00080000 */
6794 #define EXTI_PR_PR19              EXTI_PR_PR19_Msk                             /*!< Pending bit for line 19 */
6795 #define EXTI_PR_PR20_Pos          (20U)
6796 #define EXTI_PR_PR20_Msk          (0x1UL << EXTI_PR_PR20_Pos)                   /*!< 0x00100000 */
6797 #define EXTI_PR_PR20              EXTI_PR_PR20_Msk                             /*!< Pending bit for line 20 */
6798 #define EXTI_PR_PR21_Pos          (21U)
6799 #define EXTI_PR_PR21_Msk          (0x1UL << EXTI_PR_PR21_Pos)                   /*!< 0x00200000 */
6800 #define EXTI_PR_PR21              EXTI_PR_PR21_Msk                             /*!< Pending bit for line 21 */
6801 #define EXTI_PR_PR22_Pos          (22U)
6802 #define EXTI_PR_PR22_Msk          (0x1UL << EXTI_PR_PR22_Pos)                   /*!< 0x00400000 */
6803 #define EXTI_PR_PR22              EXTI_PR_PR22_Msk                             /*!< Pending bit for line 22 */
6804 #define EXTI_PR_PR23_Pos          (23U)
6805 #define EXTI_PR_PR23_Msk          (0x1UL << EXTI_PR_PR23_Pos)                   /*!< 0x00800000 */
6806 #define EXTI_PR_PR23              EXTI_PR_PR23_Msk                             /*!< Pending bit for line 23 */
6807 
6808 /******************************************************************************/
6809 /*                                                                            */
6810 /*                                    FLASH                                   */
6811 /*                                                                            */
6812 /******************************************************************************/
6813 /*******************  Bits definition for FLASH_ACR register  *****************/
6814 #define FLASH_ACR_LATENCY_Pos          (0U)
6815 #define FLASH_ACR_LATENCY_Msk          (0xFUL << FLASH_ACR_LATENCY_Pos)         /*!< 0x0000000F */
6816 #define FLASH_ACR_LATENCY              FLASH_ACR_LATENCY_Msk
6817 #define FLASH_ACR_LATENCY_0WS          0x00000000U
6818 #define FLASH_ACR_LATENCY_1WS          0x00000001U
6819 #define FLASH_ACR_LATENCY_2WS          0x00000002U
6820 #define FLASH_ACR_LATENCY_3WS          0x00000003U
6821 #define FLASH_ACR_LATENCY_4WS          0x00000004U
6822 #define FLASH_ACR_LATENCY_5WS          0x00000005U
6823 #define FLASH_ACR_LATENCY_6WS          0x00000006U
6824 #define FLASH_ACR_LATENCY_7WS          0x00000007U
6825 
6826 #define FLASH_ACR_PRFTEN_Pos           (8U)
6827 #define FLASH_ACR_PRFTEN_Msk           (0x1UL << FLASH_ACR_PRFTEN_Pos)          /*!< 0x00000100 */
6828 #define FLASH_ACR_PRFTEN               FLASH_ACR_PRFTEN_Msk
6829 #define FLASH_ACR_ICEN_Pos             (9U)
6830 #define FLASH_ACR_ICEN_Msk             (0x1UL << FLASH_ACR_ICEN_Pos)            /*!< 0x00000200 */
6831 #define FLASH_ACR_ICEN                 FLASH_ACR_ICEN_Msk
6832 #define FLASH_ACR_DCEN_Pos             (10U)
6833 #define FLASH_ACR_DCEN_Msk             (0x1UL << FLASH_ACR_DCEN_Pos)            /*!< 0x00000400 */
6834 #define FLASH_ACR_DCEN                 FLASH_ACR_DCEN_Msk
6835 #define FLASH_ACR_ICRST_Pos            (11U)
6836 #define FLASH_ACR_ICRST_Msk            (0x1UL << FLASH_ACR_ICRST_Pos)           /*!< 0x00000800 */
6837 #define FLASH_ACR_ICRST                FLASH_ACR_ICRST_Msk
6838 #define FLASH_ACR_DCRST_Pos            (12U)
6839 #define FLASH_ACR_DCRST_Msk            (0x1UL << FLASH_ACR_DCRST_Pos)           /*!< 0x00001000 */
6840 #define FLASH_ACR_DCRST                FLASH_ACR_DCRST_Msk
6841 #define FLASH_ACR_BYTE0_ADDRESS_Pos    (10U)
6842 #define FLASH_ACR_BYTE0_ADDRESS_Msk    (0x10008FUL << FLASH_ACR_BYTE0_ADDRESS_Pos) /*!< 0x40023C00 */
6843 #define FLASH_ACR_BYTE0_ADDRESS        FLASH_ACR_BYTE0_ADDRESS_Msk
6844 #define FLASH_ACR_BYTE2_ADDRESS_Pos    (0U)
6845 #define FLASH_ACR_BYTE2_ADDRESS_Msk    (0x40023C03UL << FLASH_ACR_BYTE2_ADDRESS_Pos) /*!< 0x40023C03 */
6846 #define FLASH_ACR_BYTE2_ADDRESS        FLASH_ACR_BYTE2_ADDRESS_Msk
6847 
6848 /*******************  Bits definition for FLASH_SR register  ******************/
6849 #define FLASH_SR_EOP_Pos               (0U)
6850 #define FLASH_SR_EOP_Msk               (0x1UL << FLASH_SR_EOP_Pos)              /*!< 0x00000001 */
6851 #define FLASH_SR_EOP                   FLASH_SR_EOP_Msk
6852 #define FLASH_SR_SOP_Pos               (1U)
6853 #define FLASH_SR_SOP_Msk               (0x1UL << FLASH_SR_SOP_Pos)              /*!< 0x00000002 */
6854 #define FLASH_SR_SOP                   FLASH_SR_SOP_Msk
6855 #define FLASH_SR_WRPERR_Pos            (4U)
6856 #define FLASH_SR_WRPERR_Msk            (0x1UL << FLASH_SR_WRPERR_Pos)           /*!< 0x00000010 */
6857 #define FLASH_SR_WRPERR                FLASH_SR_WRPERR_Msk
6858 #define FLASH_SR_PGAERR_Pos            (5U)
6859 #define FLASH_SR_PGAERR_Msk            (0x1UL << FLASH_SR_PGAERR_Pos)           /*!< 0x00000020 */
6860 #define FLASH_SR_PGAERR                FLASH_SR_PGAERR_Msk
6861 #define FLASH_SR_PGPERR_Pos            (6U)
6862 #define FLASH_SR_PGPERR_Msk            (0x1UL << FLASH_SR_PGPERR_Pos)           /*!< 0x00000040 */
6863 #define FLASH_SR_PGPERR                FLASH_SR_PGPERR_Msk
6864 #define FLASH_SR_PGSERR_Pos            (7U)
6865 #define FLASH_SR_PGSERR_Msk            (0x1UL << FLASH_SR_PGSERR_Pos)           /*!< 0x00000080 */
6866 #define FLASH_SR_PGSERR                FLASH_SR_PGSERR_Msk
6867 #define FLASH_SR_RDERR_Pos            (8U)
6868 #define FLASH_SR_RDERR_Msk            (0x1UL << FLASH_SR_RDERR_Pos)             /*!< 0x00000100 */
6869 #define FLASH_SR_RDERR                FLASH_SR_RDERR_Msk
6870 #define FLASH_SR_BSY_Pos               (16U)
6871 #define FLASH_SR_BSY_Msk               (0x1UL << FLASH_SR_BSY_Pos)              /*!< 0x00010000 */
6872 #define FLASH_SR_BSY                   FLASH_SR_BSY_Msk
6873 
6874 /*******************  Bits definition for FLASH_CR register  ******************/
6875 #define FLASH_CR_PG_Pos                (0U)
6876 #define FLASH_CR_PG_Msk                (0x1UL << FLASH_CR_PG_Pos)               /*!< 0x00000001 */
6877 #define FLASH_CR_PG                    FLASH_CR_PG_Msk
6878 #define FLASH_CR_SER_Pos               (1U)
6879 #define FLASH_CR_SER_Msk               (0x1UL << FLASH_CR_SER_Pos)              /*!< 0x00000002 */
6880 #define FLASH_CR_SER                   FLASH_CR_SER_Msk
6881 #define FLASH_CR_MER_Pos               (2U)
6882 #define FLASH_CR_MER_Msk               (0x1UL << FLASH_CR_MER_Pos)              /*!< 0x00000004 */
6883 #define FLASH_CR_MER                   FLASH_CR_MER_Msk
6884 #define FLASH_CR_SNB_Pos               (3U)
6885 #define FLASH_CR_SNB_Msk               (0x0FUL << FLASH_CR_SNB_Pos)             /*!< 0x00000078 */
6886 #define FLASH_CR_SNB                   FLASH_CR_SNB_Msk
6887 #define FLASH_CR_SNB_0                 (0x01UL << FLASH_CR_SNB_Pos)             /*!< 0x00000008 */
6888 #define FLASH_CR_SNB_1                 (0x02UL << FLASH_CR_SNB_Pos)             /*!< 0x00000010 */
6889 #define FLASH_CR_SNB_2                 (0x04UL << FLASH_CR_SNB_Pos)             /*!< 0x00000020 */
6890 #define FLASH_CR_SNB_3                 (0x08UL << FLASH_CR_SNB_Pos)             /*!< 0x00000040 */
6891 #define FLASH_CR_PSIZE_Pos             (8U)
6892 #define FLASH_CR_PSIZE_Msk             (0x3UL << FLASH_CR_PSIZE_Pos)            /*!< 0x00000300 */
6893 #define FLASH_CR_PSIZE                 FLASH_CR_PSIZE_Msk
6894 #define FLASH_CR_PSIZE_0               (0x1UL << FLASH_CR_PSIZE_Pos)            /*!< 0x00000100 */
6895 #define FLASH_CR_PSIZE_1               (0x2UL << FLASH_CR_PSIZE_Pos)            /*!< 0x00000200 */
6896 #define FLASH_CR_STRT_Pos              (16U)
6897 #define FLASH_CR_STRT_Msk              (0x1UL << FLASH_CR_STRT_Pos)             /*!< 0x00010000 */
6898 #define FLASH_CR_STRT                  FLASH_CR_STRT_Msk
6899 #define FLASH_CR_EOPIE_Pos             (24U)
6900 #define FLASH_CR_EOPIE_Msk             (0x1UL << FLASH_CR_EOPIE_Pos)            /*!< 0x01000000 */
6901 #define FLASH_CR_EOPIE                 FLASH_CR_EOPIE_Msk
6902 #define FLASH_CR_LOCK_Pos              (31U)
6903 #define FLASH_CR_LOCK_Msk              (0x1UL << FLASH_CR_LOCK_Pos)             /*!< 0x80000000 */
6904 #define FLASH_CR_LOCK                  FLASH_CR_LOCK_Msk
6905 
6906 /*******************  Bits definition for FLASH_OPTCR register  ***************/
6907 #define FLASH_OPTCR_OPTLOCK_Pos        (0U)
6908 #define FLASH_OPTCR_OPTLOCK_Msk        (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)       /*!< 0x00000001 */
6909 #define FLASH_OPTCR_OPTLOCK            FLASH_OPTCR_OPTLOCK_Msk
6910 #define FLASH_OPTCR_OPTSTRT_Pos        (1U)
6911 #define FLASH_OPTCR_OPTSTRT_Msk        (0x1UL << FLASH_OPTCR_OPTSTRT_Pos)       /*!< 0x00000002 */
6912 #define FLASH_OPTCR_OPTSTRT            FLASH_OPTCR_OPTSTRT_Msk
6913 
6914 #define FLASH_OPTCR_BOR_LEV_0          0x00000004U
6915 #define FLASH_OPTCR_BOR_LEV_1          0x00000008U
6916 #define FLASH_OPTCR_BOR_LEV_Pos        (2U)
6917 #define FLASH_OPTCR_BOR_LEV_Msk        (0x3UL << FLASH_OPTCR_BOR_LEV_Pos)       /*!< 0x0000000C */
6918 #define FLASH_OPTCR_BOR_LEV            FLASH_OPTCR_BOR_LEV_Msk
6919 #define FLASH_OPTCR_WDG_SW_Pos         (5U)
6920 #define FLASH_OPTCR_WDG_SW_Msk         (0x1UL << FLASH_OPTCR_WDG_SW_Pos)        /*!< 0x00000020 */
6921 #define FLASH_OPTCR_WDG_SW             FLASH_OPTCR_WDG_SW_Msk
6922 #define FLASH_OPTCR_nRST_STOP_Pos      (6U)
6923 #define FLASH_OPTCR_nRST_STOP_Msk      (0x1UL << FLASH_OPTCR_nRST_STOP_Pos)     /*!< 0x00000040 */
6924 #define FLASH_OPTCR_nRST_STOP          FLASH_OPTCR_nRST_STOP_Msk
6925 #define FLASH_OPTCR_nRST_STDBY_Pos     (7U)
6926 #define FLASH_OPTCR_nRST_STDBY_Msk     (0x1UL << FLASH_OPTCR_nRST_STDBY_Pos)    /*!< 0x00000080 */
6927 #define FLASH_OPTCR_nRST_STDBY         FLASH_OPTCR_nRST_STDBY_Msk
6928 #define FLASH_OPTCR_RDP_Pos            (8U)
6929 #define FLASH_OPTCR_RDP_Msk            (0xFFUL << FLASH_OPTCR_RDP_Pos)          /*!< 0x0000FF00 */
6930 #define FLASH_OPTCR_RDP                FLASH_OPTCR_RDP_Msk
6931 #define FLASH_OPTCR_RDP_0              (0x01UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000100 */
6932 #define FLASH_OPTCR_RDP_1              (0x02UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000200 */
6933 #define FLASH_OPTCR_RDP_2              (0x04UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000400 */
6934 #define FLASH_OPTCR_RDP_3              (0x08UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000800 */
6935 #define FLASH_OPTCR_RDP_4              (0x10UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00001000 */
6936 #define FLASH_OPTCR_RDP_5              (0x20UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00002000 */
6937 #define FLASH_OPTCR_RDP_6              (0x40UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00004000 */
6938 #define FLASH_OPTCR_RDP_7              (0x80UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00008000 */
6939 #define FLASH_OPTCR_nWRP_Pos           (16U)
6940 #define FLASH_OPTCR_nWRP_Msk           (0x7FFFUL << FLASH_OPTCR_nWRP_Pos)       /*!< 0x7FFF0000 */
6941 #define FLASH_OPTCR_nWRP               FLASH_OPTCR_nWRP_Msk
6942 #define FLASH_OPTCR_nWRP_0             0x00010000U
6943 #define FLASH_OPTCR_nWRP_1             0x00020000U
6944 #define FLASH_OPTCR_nWRP_2             0x00040000U
6945 #define FLASH_OPTCR_nWRP_3             0x00080000U
6946 #define FLASH_OPTCR_nWRP_4             0x00100000U
6947 #define FLASH_OPTCR_nWRP_5             0x00200000U
6948 #define FLASH_OPTCR_nWRP_6             0x00400000U
6949 #define FLASH_OPTCR_nWRP_7             0x00800000U
6950 #define FLASH_OPTCR_nWRP_8             0x01000000U
6951 #define FLASH_OPTCR_nWRP_9             0x02000000U
6952 #define FLASH_OPTCR_nWRP_10            0x04000000U
6953 #define FLASH_OPTCR_nWRP_11            0x08000000U
6954 #define FLASH_OPTCR_nWRP_12            0x10000000U
6955 #define FLASH_OPTCR_nWRP_13            0x20000000U
6956 #define FLASH_OPTCR_nWRP_14            0x40000000U
6957 #define FLASH_OPTCR_nWRP_15            0x40000000U
6958 
6959 /******************  Bits definition for FLASH_OPTCR1 register  ***************/
6960 #define FLASH_OPTCR1_nWRP_Pos          (16U)
6961 #define FLASH_OPTCR1_nWRP_Msk          (0xFFFUL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x0FFF0000 */
6962 #define FLASH_OPTCR1_nWRP              FLASH_OPTCR1_nWRP_Msk
6963 #define FLASH_OPTCR1_nWRP_0            (0x001UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00010000 */
6964 #define FLASH_OPTCR1_nWRP_1            (0x002UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00020000 */
6965 #define FLASH_OPTCR1_nWRP_2            (0x004UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00040000 */
6966 #define FLASH_OPTCR1_nWRP_3            (0x008UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00080000 */
6967 #define FLASH_OPTCR1_nWRP_4            (0x010UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00100000 */
6968 #define FLASH_OPTCR1_nWRP_5            (0x020UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00200000 */
6969 #define FLASH_OPTCR1_nWRP_6            (0x040UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00400000 */
6970 #define FLASH_OPTCR1_nWRP_7            (0x080UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00800000 */
6971 #define FLASH_OPTCR1_nWRP_8            (0x100UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x01000000 */
6972 #define FLASH_OPTCR1_nWRP_9            (0x200UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x02000000 */
6973 #define FLASH_OPTCR1_nWRP_10           (0x400UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x04000000 */
6974 #define FLASH_OPTCR1_nWRP_11           (0x800UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x08000000 */
6975 
6976 /******************************************************************************/
6977 /*                                                                            */
6978 /*                   Flexible Static Memory Controller                        */
6979 /*                                                                            */
6980 /******************************************************************************/
6981 /******************  Bit definition for FSMC_BCR1 register  *******************/
6982 #define FSMC_BCR1_MBKEN_Pos          (0U)
6983 #define FSMC_BCR1_MBKEN_Msk          (0x1UL << FSMC_BCR1_MBKEN_Pos)             /*!< 0x00000001 */
6984 #define FSMC_BCR1_MBKEN              FSMC_BCR1_MBKEN_Msk                       /*!<Memory bank enable bit                 */
6985 #define FSMC_BCR1_MUXEN_Pos          (1U)
6986 #define FSMC_BCR1_MUXEN_Msk          (0x1UL << FSMC_BCR1_MUXEN_Pos)             /*!< 0x00000002 */
6987 #define FSMC_BCR1_MUXEN              FSMC_BCR1_MUXEN_Msk                       /*!<Address/data multiplexing enable bit   */
6988 
6989 #define FSMC_BCR1_MTYP_Pos           (2U)
6990 #define FSMC_BCR1_MTYP_Msk           (0x3UL << FSMC_BCR1_MTYP_Pos)              /*!< 0x0000000C */
6991 #define FSMC_BCR1_MTYP               FSMC_BCR1_MTYP_Msk                        /*!<MTYP[1:0] bits (Memory type)           */
6992 #define FSMC_BCR1_MTYP_0             (0x1UL << FSMC_BCR1_MTYP_Pos)              /*!< 0x00000004 */
6993 #define FSMC_BCR1_MTYP_1             (0x2UL << FSMC_BCR1_MTYP_Pos)              /*!< 0x00000008 */
6994 
6995 #define FSMC_BCR1_MWID_Pos           (4U)
6996 #define FSMC_BCR1_MWID_Msk           (0x3UL << FSMC_BCR1_MWID_Pos)              /*!< 0x00000030 */
6997 #define FSMC_BCR1_MWID               FSMC_BCR1_MWID_Msk                        /*!<MWID[1:0] bits (Memory data bus width) */
6998 #define FSMC_BCR1_MWID_0             (0x1UL << FSMC_BCR1_MWID_Pos)              /*!< 0x00000010 */
6999 #define FSMC_BCR1_MWID_1             (0x2UL << FSMC_BCR1_MWID_Pos)              /*!< 0x00000020 */
7000 
7001 #define FSMC_BCR1_FACCEN_Pos         (6U)
7002 #define FSMC_BCR1_FACCEN_Msk         (0x1UL << FSMC_BCR1_FACCEN_Pos)            /*!< 0x00000040 */
7003 #define FSMC_BCR1_FACCEN             FSMC_BCR1_FACCEN_Msk                      /*!<Flash access enable                    */
7004 #define FSMC_BCR1_BURSTEN_Pos        (8U)
7005 #define FSMC_BCR1_BURSTEN_Msk        (0x1UL << FSMC_BCR1_BURSTEN_Pos)           /*!< 0x00000100 */
7006 #define FSMC_BCR1_BURSTEN            FSMC_BCR1_BURSTEN_Msk                     /*!<Burst enable bit                       */
7007 #define FSMC_BCR1_WAITPOL_Pos        (9U)
7008 #define FSMC_BCR1_WAITPOL_Msk        (0x1UL << FSMC_BCR1_WAITPOL_Pos)           /*!< 0x00000200 */
7009 #define FSMC_BCR1_WAITPOL            FSMC_BCR1_WAITPOL_Msk                     /*!<Wait signal polarity bit               */
7010 #define FSMC_BCR1_WAITCFG_Pos        (11U)
7011 #define FSMC_BCR1_WAITCFG_Msk        (0x1UL << FSMC_BCR1_WAITCFG_Pos)           /*!< 0x00000800 */
7012 #define FSMC_BCR1_WAITCFG            FSMC_BCR1_WAITCFG_Msk                     /*!<Wait timing configuration              */
7013 #define FSMC_BCR1_WREN_Pos           (12U)
7014 #define FSMC_BCR1_WREN_Msk           (0x1UL << FSMC_BCR1_WREN_Pos)              /*!< 0x00001000 */
7015 #define FSMC_BCR1_WREN               FSMC_BCR1_WREN_Msk                        /*!<Write enable bit                       */
7016 #define FSMC_BCR1_WAITEN_Pos         (13U)
7017 #define FSMC_BCR1_WAITEN_Msk         (0x1UL << FSMC_BCR1_WAITEN_Pos)            /*!< 0x00002000 */
7018 #define FSMC_BCR1_WAITEN             FSMC_BCR1_WAITEN_Msk                      /*!<Wait enable bit                        */
7019 #define FSMC_BCR1_EXTMOD_Pos         (14U)
7020 #define FSMC_BCR1_EXTMOD_Msk         (0x1UL << FSMC_BCR1_EXTMOD_Pos)            /*!< 0x00004000 */
7021 #define FSMC_BCR1_EXTMOD             FSMC_BCR1_EXTMOD_Msk                      /*!<Extended mode enable                   */
7022 #define FSMC_BCR1_ASYNCWAIT_Pos      (15U)
7023 #define FSMC_BCR1_ASYNCWAIT_Msk      (0x1UL << FSMC_BCR1_ASYNCWAIT_Pos)         /*!< 0x00008000 */
7024 #define FSMC_BCR1_ASYNCWAIT          FSMC_BCR1_ASYNCWAIT_Msk                   /*!<Asynchronous wait                      */
7025 #define FSMC_BCR1_CPSIZE_Pos         (16U)
7026 #define FSMC_BCR1_CPSIZE_Msk         (0x7UL << FSMC_BCR1_CPSIZE_Pos)            /*!< 0x00070000 */
7027 #define FSMC_BCR1_CPSIZE             FSMC_BCR1_CPSIZE_Msk                      /*!<CRAM page size */
7028 #define FSMC_BCR1_CPSIZE_0           (0x1UL << FSMC_BCR1_CPSIZE_Pos)            /*!< 0x00010000 */
7029 #define FSMC_BCR1_CPSIZE_1           (0x2UL << FSMC_BCR1_CPSIZE_Pos)            /*!< 0x00020000 */
7030 #define FSMC_BCR1_CPSIZE_2           (0x4UL << FSMC_BCR1_CPSIZE_Pos)            /*!< 0x00040000 */
7031 #define FSMC_BCR1_CBURSTRW_Pos       (19U)
7032 #define FSMC_BCR1_CBURSTRW_Msk       (0x1UL << FSMC_BCR1_CBURSTRW_Pos)          /*!< 0x00080000 */
7033 #define FSMC_BCR1_CBURSTRW           FSMC_BCR1_CBURSTRW_Msk                    /*!<Write burst enable                     */
7034 #define FSMC_BCR1_CCLKEN_Pos         (20U)
7035 #define FSMC_BCR1_CCLKEN_Msk         (0x1UL << FSMC_BCR1_CCLKEN_Pos)            /*!< 0x00100000 */
7036 #define FSMC_BCR1_CCLKEN             FSMC_BCR1_CCLKEN_Msk                      /*!<Continous clock enable     */
7037 #define FSMC_BCR1_WFDIS_Pos          (21U)
7038 #define FSMC_BCR1_WFDIS_Msk          (0x1UL << FSMC_BCR1_WFDIS_Pos)             /*!< 0x00200000 */
7039 #define FSMC_BCR1_WFDIS              FSMC_BCR1_WFDIS_Msk                       /*!<Write FIFO Disable         */
7040 
7041 /******************  Bit definition for FSMC_BCR2 register  *******************/
7042 #define FSMC_BCR2_MBKEN_Pos          (0U)
7043 #define FSMC_BCR2_MBKEN_Msk          (0x1UL << FSMC_BCR2_MBKEN_Pos)             /*!< 0x00000001 */
7044 #define FSMC_BCR2_MBKEN              FSMC_BCR2_MBKEN_Msk                       /*!<Memory bank enable bit                */
7045 #define FSMC_BCR2_MUXEN_Pos          (1U)
7046 #define FSMC_BCR2_MUXEN_Msk          (0x1UL << FSMC_BCR2_MUXEN_Pos)             /*!< 0x00000002 */
7047 #define FSMC_BCR2_MUXEN              FSMC_BCR2_MUXEN_Msk                       /*!<Address/data multiplexing enable bit   */
7048 
7049 #define FSMC_BCR2_MTYP_Pos           (2U)
7050 #define FSMC_BCR2_MTYP_Msk           (0x3UL << FSMC_BCR2_MTYP_Pos)              /*!< 0x0000000C */
7051 #define FSMC_BCR2_MTYP               FSMC_BCR2_MTYP_Msk                        /*!<MTYP[1:0] bits (Memory type)           */
7052 #define FSMC_BCR2_MTYP_0             (0x1UL << FSMC_BCR2_MTYP_Pos)              /*!< 0x00000004 */
7053 #define FSMC_BCR2_MTYP_1             (0x2UL << FSMC_BCR2_MTYP_Pos)              /*!< 0x00000008 */
7054 
7055 #define FSMC_BCR2_MWID_Pos           (4U)
7056 #define FSMC_BCR2_MWID_Msk           (0x3UL << FSMC_BCR2_MWID_Pos)              /*!< 0x00000030 */
7057 #define FSMC_BCR2_MWID               FSMC_BCR2_MWID_Msk                        /*!<MWID[1:0] bits (Memory data bus width) */
7058 #define FSMC_BCR2_MWID_0             (0x1UL << FSMC_BCR2_MWID_Pos)              /*!< 0x00000010 */
7059 #define FSMC_BCR2_MWID_1             (0x2UL << FSMC_BCR2_MWID_Pos)              /*!< 0x00000020 */
7060 
7061 #define FSMC_BCR2_FACCEN_Pos         (6U)
7062 #define FSMC_BCR2_FACCEN_Msk         (0x1UL << FSMC_BCR2_FACCEN_Pos)            /*!< 0x00000040 */
7063 #define FSMC_BCR2_FACCEN             FSMC_BCR2_FACCEN_Msk                      /*!<Flash access enable                    */
7064 #define FSMC_BCR2_BURSTEN_Pos        (8U)
7065 #define FSMC_BCR2_BURSTEN_Msk        (0x1UL << FSMC_BCR2_BURSTEN_Pos)           /*!< 0x00000100 */
7066 #define FSMC_BCR2_BURSTEN            FSMC_BCR2_BURSTEN_Msk                     /*!<Burst enable bit                       */
7067 #define FSMC_BCR2_WAITPOL_Pos        (9U)
7068 #define FSMC_BCR2_WAITPOL_Msk        (0x1UL << FSMC_BCR2_WAITPOL_Pos)           /*!< 0x00000200 */
7069 #define FSMC_BCR2_WAITPOL            FSMC_BCR2_WAITPOL_Msk                     /*!<Wait signal polarity bit               */
7070 #define FSMC_BCR2_WAITCFG_Pos        (11U)
7071 #define FSMC_BCR2_WAITCFG_Msk        (0x1UL << FSMC_BCR2_WAITCFG_Pos)           /*!< 0x00000800 */
7072 #define FSMC_BCR2_WAITCFG            FSMC_BCR2_WAITCFG_Msk                     /*!<Wait timing configuration              */
7073 #define FSMC_BCR2_WREN_Pos           (12U)
7074 #define FSMC_BCR2_WREN_Msk           (0x1UL << FSMC_BCR2_WREN_Pos)              /*!< 0x00001000 */
7075 #define FSMC_BCR2_WREN               FSMC_BCR2_WREN_Msk                        /*!<Write enable bit                       */
7076 #define FSMC_BCR2_WAITEN_Pos         (13U)
7077 #define FSMC_BCR2_WAITEN_Msk         (0x1UL << FSMC_BCR2_WAITEN_Pos)            /*!< 0x00002000 */
7078 #define FSMC_BCR2_WAITEN             FSMC_BCR2_WAITEN_Msk                      /*!<Wait enable bit                        */
7079 #define FSMC_BCR2_EXTMOD_Pos         (14U)
7080 #define FSMC_BCR2_EXTMOD_Msk         (0x1UL << FSMC_BCR2_EXTMOD_Pos)            /*!< 0x00004000 */
7081 #define FSMC_BCR2_EXTMOD             FSMC_BCR2_EXTMOD_Msk                      /*!<Extended mode enable                   */
7082 #define FSMC_BCR2_ASYNCWAIT_Pos      (15U)
7083 #define FSMC_BCR2_ASYNCWAIT_Msk      (0x1UL << FSMC_BCR2_ASYNCWAIT_Pos)         /*!< 0x00008000 */
7084 #define FSMC_BCR2_ASYNCWAIT          FSMC_BCR2_ASYNCWAIT_Msk                   /*!<Asynchronous wait                      */
7085 #define FSMC_BCR2_CPSIZE_Pos         (16U)
7086 #define FSMC_BCR2_CPSIZE_Msk         (0x7UL << FSMC_BCR2_CPSIZE_Pos)            /*!< 0x00070000 */
7087 #define FSMC_BCR2_CPSIZE             FSMC_BCR2_CPSIZE_Msk                      /*!<CRAM page size */
7088 #define FSMC_BCR2_CPSIZE_0           (0x1UL << FSMC_BCR2_CPSIZE_Pos)            /*!< 0x00010000 */
7089 #define FSMC_BCR2_CPSIZE_1           (0x2UL << FSMC_BCR2_CPSIZE_Pos)            /*!< 0x00020000 */
7090 #define FSMC_BCR2_CPSIZE_2           (0x4UL << FSMC_BCR2_CPSIZE_Pos)            /*!< 0x00040000 */
7091 #define FSMC_BCR2_CBURSTRW_Pos       (19U)
7092 #define FSMC_BCR2_CBURSTRW_Msk       (0x1UL << FSMC_BCR2_CBURSTRW_Pos)          /*!< 0x00080000 */
7093 #define FSMC_BCR2_CBURSTRW           FSMC_BCR2_CBURSTRW_Msk                    /*!<Write burst enable                     */
7094 
7095 /******************  Bit definition for FSMC_BCR3 register  *******************/
7096 #define FSMC_BCR3_MBKEN_Pos          (0U)
7097 #define FSMC_BCR3_MBKEN_Msk          (0x1UL << FSMC_BCR3_MBKEN_Pos)             /*!< 0x00000001 */
7098 #define FSMC_BCR3_MBKEN              FSMC_BCR3_MBKEN_Msk                       /*!<Memory bank enable bit                 */
7099 #define FSMC_BCR3_MUXEN_Pos          (1U)
7100 #define FSMC_BCR3_MUXEN_Msk          (0x1UL << FSMC_BCR3_MUXEN_Pos)             /*!< 0x00000002 */
7101 #define FSMC_BCR3_MUXEN              FSMC_BCR3_MUXEN_Msk                       /*!<Address/data multiplexing enable bit   */
7102 
7103 #define FSMC_BCR3_MTYP_Pos           (2U)
7104 #define FSMC_BCR3_MTYP_Msk           (0x3UL << FSMC_BCR3_MTYP_Pos)              /*!< 0x0000000C */
7105 #define FSMC_BCR3_MTYP               FSMC_BCR3_MTYP_Msk                        /*!<MTYP[1:0] bits (Memory type)           */
7106 #define FSMC_BCR3_MTYP_0             (0x1UL << FSMC_BCR3_MTYP_Pos)              /*!< 0x00000004 */
7107 #define FSMC_BCR3_MTYP_1             (0x2UL << FSMC_BCR3_MTYP_Pos)              /*!< 0x00000008 */
7108 
7109 #define FSMC_BCR3_MWID_Pos           (4U)
7110 #define FSMC_BCR3_MWID_Msk           (0x3UL << FSMC_BCR3_MWID_Pos)              /*!< 0x00000030 */
7111 #define FSMC_BCR3_MWID               FSMC_BCR3_MWID_Msk                        /*!<MWID[1:0] bits (Memory data bus width) */
7112 #define FSMC_BCR3_MWID_0             (0x1UL << FSMC_BCR3_MWID_Pos)              /*!< 0x00000010 */
7113 #define FSMC_BCR3_MWID_1             (0x2UL << FSMC_BCR3_MWID_Pos)              /*!< 0x00000020 */
7114 
7115 #define FSMC_BCR3_FACCEN_Pos         (6U)
7116 #define FSMC_BCR3_FACCEN_Msk         (0x1UL << FSMC_BCR3_FACCEN_Pos)            /*!< 0x00000040 */
7117 #define FSMC_BCR3_FACCEN             FSMC_BCR3_FACCEN_Msk                      /*!<Flash access enable                    */
7118 #define FSMC_BCR3_BURSTEN_Pos        (8U)
7119 #define FSMC_BCR3_BURSTEN_Msk        (0x1UL << FSMC_BCR3_BURSTEN_Pos)           /*!< 0x00000100 */
7120 #define FSMC_BCR3_BURSTEN            FSMC_BCR3_BURSTEN_Msk                     /*!<Burst enable bit                       */
7121 #define FSMC_BCR3_WAITPOL_Pos        (9U)
7122 #define FSMC_BCR3_WAITPOL_Msk        (0x1UL << FSMC_BCR3_WAITPOL_Pos)           /*!< 0x00000200 */
7123 #define FSMC_BCR3_WAITPOL            FSMC_BCR3_WAITPOL_Msk                     /*!<Wait signal polarity bit               */
7124 #define FSMC_BCR3_WAITCFG_Pos        (11U)
7125 #define FSMC_BCR3_WAITCFG_Msk        (0x1UL << FSMC_BCR3_WAITCFG_Pos)           /*!< 0x00000800 */
7126 #define FSMC_BCR3_WAITCFG            FSMC_BCR3_WAITCFG_Msk                     /*!<Wait timing configuration              */
7127 #define FSMC_BCR3_WREN_Pos           (12U)
7128 #define FSMC_BCR3_WREN_Msk           (0x1UL << FSMC_BCR3_WREN_Pos)              /*!< 0x00001000 */
7129 #define FSMC_BCR3_WREN               FSMC_BCR3_WREN_Msk                        /*!<Write enable bit                       */
7130 #define FSMC_BCR3_WAITEN_Pos         (13U)
7131 #define FSMC_BCR3_WAITEN_Msk         (0x1UL << FSMC_BCR3_WAITEN_Pos)            /*!< 0x00002000 */
7132 #define FSMC_BCR3_WAITEN             FSMC_BCR3_WAITEN_Msk                      /*!<Wait enable bit                        */
7133 #define FSMC_BCR3_EXTMOD_Pos         (14U)
7134 #define FSMC_BCR3_EXTMOD_Msk         (0x1UL << FSMC_BCR3_EXTMOD_Pos)            /*!< 0x00004000 */
7135 #define FSMC_BCR3_EXTMOD             FSMC_BCR3_EXTMOD_Msk                      /*!<Extended mode enable                   */
7136 #define FSMC_BCR3_ASYNCWAIT_Pos      (15U)
7137 #define FSMC_BCR3_ASYNCWAIT_Msk      (0x1UL << FSMC_BCR3_ASYNCWAIT_Pos)         /*!< 0x00008000 */
7138 #define FSMC_BCR3_ASYNCWAIT          FSMC_BCR3_ASYNCWAIT_Msk                   /*!<Asynchronous wait                      */
7139 #define FSMC_BCR3_CPSIZE_Pos         (16U)
7140 #define FSMC_BCR3_CPSIZE_Msk         (0x7UL << FSMC_BCR3_CPSIZE_Pos)            /*!< 0x00070000 */
7141 #define FSMC_BCR3_CPSIZE             FSMC_BCR3_CPSIZE_Msk                      /*!<CRAM page size */
7142 #define FSMC_BCR3_CPSIZE_0           (0x1UL << FSMC_BCR3_CPSIZE_Pos)            /*!< 0x00010000 */
7143 #define FSMC_BCR3_CPSIZE_1           (0x2UL << FSMC_BCR3_CPSIZE_Pos)            /*!< 0x00020000 */
7144 #define FSMC_BCR3_CPSIZE_2           (0x4UL << FSMC_BCR3_CPSIZE_Pos)            /*!< 0x00040000 */
7145 #define FSMC_BCR3_CBURSTRW_Pos       (19U)
7146 #define FSMC_BCR3_CBURSTRW_Msk       (0x1UL << FSMC_BCR3_CBURSTRW_Pos)          /*!< 0x00080000 */
7147 #define FSMC_BCR3_CBURSTRW           FSMC_BCR3_CBURSTRW_Msk                    /*!<Write burst enable                     */
7148 
7149 /******************  Bit definition for FSMC_BCR4 register  *******************/
7150 #define FSMC_BCR4_MBKEN_Pos          (0U)
7151 #define FSMC_BCR4_MBKEN_Msk          (0x1UL << FSMC_BCR4_MBKEN_Pos)             /*!< 0x00000001 */
7152 #define FSMC_BCR4_MBKEN              FSMC_BCR4_MBKEN_Msk                       /*!<Memory bank enable bit */
7153 #define FSMC_BCR4_MUXEN_Pos          (1U)
7154 #define FSMC_BCR4_MUXEN_Msk          (0x1UL << FSMC_BCR4_MUXEN_Pos)             /*!< 0x00000002 */
7155 #define FSMC_BCR4_MUXEN              FSMC_BCR4_MUXEN_Msk                       /*!<Address/data multiplexing enable bit   */
7156 
7157 #define FSMC_BCR4_MTYP_Pos           (2U)
7158 #define FSMC_BCR4_MTYP_Msk           (0x3UL << FSMC_BCR4_MTYP_Pos)              /*!< 0x0000000C */
7159 #define FSMC_BCR4_MTYP               FSMC_BCR4_MTYP_Msk                        /*!<MTYP[1:0] bits (Memory type)           */
7160 #define FSMC_BCR4_MTYP_0             (0x1UL << FSMC_BCR4_MTYP_Pos)              /*!< 0x00000004 */
7161 #define FSMC_BCR4_MTYP_1             (0x2UL << FSMC_BCR4_MTYP_Pos)              /*!< 0x00000008 */
7162 
7163 #define FSMC_BCR4_MWID_Pos           (4U)
7164 #define FSMC_BCR4_MWID_Msk           (0x3UL << FSMC_BCR4_MWID_Pos)              /*!< 0x00000030 */
7165 #define FSMC_BCR4_MWID               FSMC_BCR4_MWID_Msk                        /*!<MWID[1:0] bits (Memory data bus width) */
7166 #define FSMC_BCR4_MWID_0             (0x1UL << FSMC_BCR4_MWID_Pos)              /*!< 0x00000010 */
7167 #define FSMC_BCR4_MWID_1             (0x2UL << FSMC_BCR4_MWID_Pos)              /*!< 0x00000020 */
7168 
7169 #define FSMC_BCR4_FACCEN_Pos         (6U)
7170 #define FSMC_BCR4_FACCEN_Msk         (0x1UL << FSMC_BCR4_FACCEN_Pos)            /*!< 0x00000040 */
7171 #define FSMC_BCR4_FACCEN             FSMC_BCR4_FACCEN_Msk                      /*!<Flash access enable                    */
7172 #define FSMC_BCR4_BURSTEN_Pos        (8U)
7173 #define FSMC_BCR4_BURSTEN_Msk        (0x1UL << FSMC_BCR4_BURSTEN_Pos)           /*!< 0x00000100 */
7174 #define FSMC_BCR4_BURSTEN            FSMC_BCR4_BURSTEN_Msk                     /*!<Burst enable bit                       */
7175 #define FSMC_BCR4_WAITPOL_Pos        (9U)
7176 #define FSMC_BCR4_WAITPOL_Msk        (0x1UL << FSMC_BCR4_WAITPOL_Pos)           /*!< 0x00000200 */
7177 #define FSMC_BCR4_WAITPOL            FSMC_BCR4_WAITPOL_Msk                     /*!<Wait signal polarity bit               */
7178 #define FSMC_BCR4_WAITCFG_Pos        (11U)
7179 #define FSMC_BCR4_WAITCFG_Msk        (0x1UL << FSMC_BCR4_WAITCFG_Pos)           /*!< 0x00000800 */
7180 #define FSMC_BCR4_WAITCFG            FSMC_BCR4_WAITCFG_Msk                     /*!<Wait timing configuration              */
7181 #define FSMC_BCR4_WREN_Pos           (12U)
7182 #define FSMC_BCR4_WREN_Msk           (0x1UL << FSMC_BCR4_WREN_Pos)              /*!< 0x00001000 */
7183 #define FSMC_BCR4_WREN               FSMC_BCR4_WREN_Msk                        /*!<Write enable bit                       */
7184 #define FSMC_BCR4_WAITEN_Pos         (13U)
7185 #define FSMC_BCR4_WAITEN_Msk         (0x1UL << FSMC_BCR4_WAITEN_Pos)            /*!< 0x00002000 */
7186 #define FSMC_BCR4_WAITEN             FSMC_BCR4_WAITEN_Msk                      /*!<Wait enable bit                        */
7187 #define FSMC_BCR4_EXTMOD_Pos         (14U)
7188 #define FSMC_BCR4_EXTMOD_Msk         (0x1UL << FSMC_BCR4_EXTMOD_Pos)            /*!< 0x00004000 */
7189 #define FSMC_BCR4_EXTMOD             FSMC_BCR4_EXTMOD_Msk                      /*!<Extended mode enable                   */
7190 #define FSMC_BCR4_ASYNCWAIT_Pos      (15U)
7191 #define FSMC_BCR4_ASYNCWAIT_Msk      (0x1UL << FSMC_BCR4_ASYNCWAIT_Pos)         /*!< 0x00008000 */
7192 #define FSMC_BCR4_ASYNCWAIT          FSMC_BCR4_ASYNCWAIT_Msk                   /*!<Asynchronous wait                      */
7193 #define FSMC_BCR4_CPSIZE_Pos         (16U)
7194 #define FSMC_BCR4_CPSIZE_Msk         (0x7UL << FSMC_BCR4_CPSIZE_Pos)            /*!< 0x00070000 */
7195 #define FSMC_BCR4_CPSIZE             FSMC_BCR4_CPSIZE_Msk                      /*!<CRAM page size */
7196 #define FSMC_BCR4_CPSIZE_0           (0x1UL << FSMC_BCR4_CPSIZE_Pos)            /*!< 0x00010000 */
7197 #define FSMC_BCR4_CPSIZE_1           (0x2UL << FSMC_BCR4_CPSIZE_Pos)            /*!< 0x00020000 */
7198 #define FSMC_BCR4_CPSIZE_2           (0x4UL << FSMC_BCR4_CPSIZE_Pos)            /*!< 0x00040000 */
7199 #define FSMC_BCR4_CBURSTRW_Pos       (19U)
7200 #define FSMC_BCR4_CBURSTRW_Msk       (0x1UL << FSMC_BCR4_CBURSTRW_Pos)          /*!< 0x00080000 */
7201 #define FSMC_BCR4_CBURSTRW           FSMC_BCR4_CBURSTRW_Msk                    /*!<Write burst enable                     */
7202 
7203 /******************  Bit definition for FSMC_BTR1 register  ******************/
7204 #define FSMC_BTR1_ADDSET_Pos         (0U)
7205 #define FSMC_BTR1_ADDSET_Msk         (0xFUL << FSMC_BTR1_ADDSET_Pos)            /*!< 0x0000000F */
7206 #define FSMC_BTR1_ADDSET             FSMC_BTR1_ADDSET_Msk                      /*!<ADDSET[3:0] bits (Address setup phase duration) */
7207 #define FSMC_BTR1_ADDSET_0           (0x1UL << FSMC_BTR1_ADDSET_Pos)            /*!< 0x00000001 */
7208 #define FSMC_BTR1_ADDSET_1           (0x2UL << FSMC_BTR1_ADDSET_Pos)            /*!< 0x00000002 */
7209 #define FSMC_BTR1_ADDSET_2           (0x4UL << FSMC_BTR1_ADDSET_Pos)            /*!< 0x00000004 */
7210 #define FSMC_BTR1_ADDSET_3           (0x8UL << FSMC_BTR1_ADDSET_Pos)            /*!< 0x00000008 */
7211 
7212 #define FSMC_BTR1_ADDHLD_Pos         (4U)
7213 #define FSMC_BTR1_ADDHLD_Msk         (0xFUL << FSMC_BTR1_ADDHLD_Pos)            /*!< 0x000000F0 */
7214 #define FSMC_BTR1_ADDHLD             FSMC_BTR1_ADDHLD_Msk                      /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7215 #define FSMC_BTR1_ADDHLD_0           (0x1UL << FSMC_BTR1_ADDHLD_Pos)            /*!< 0x00000010 */
7216 #define FSMC_BTR1_ADDHLD_1           (0x2UL << FSMC_BTR1_ADDHLD_Pos)            /*!< 0x00000020 */
7217 #define FSMC_BTR1_ADDHLD_2           (0x4UL << FSMC_BTR1_ADDHLD_Pos)            /*!< 0x00000040 */
7218 #define FSMC_BTR1_ADDHLD_3           (0x8UL << FSMC_BTR1_ADDHLD_Pos)            /*!< 0x00000080 */
7219 
7220 #define FSMC_BTR1_DATAST_Pos         (8U)
7221 #define FSMC_BTR1_DATAST_Msk         (0xFFUL << FSMC_BTR1_DATAST_Pos)           /*!< 0x0000FF00 */
7222 #define FSMC_BTR1_DATAST             FSMC_BTR1_DATAST_Msk                      /*!<DATAST [7:0] bits (Data-phase duration) */
7223 #define FSMC_BTR1_DATAST_0           (0x01UL << FSMC_BTR1_DATAST_Pos)           /*!< 0x00000100 */
7224 #define FSMC_BTR1_DATAST_1           (0x02UL << FSMC_BTR1_DATAST_Pos)           /*!< 0x00000200 */
7225 #define FSMC_BTR1_DATAST_2           (0x04UL << FSMC_BTR1_DATAST_Pos)           /*!< 0x00000400 */
7226 #define FSMC_BTR1_DATAST_3           (0x08UL << FSMC_BTR1_DATAST_Pos)           /*!< 0x00000800 */
7227 #define FSMC_BTR1_DATAST_4           (0x10UL << FSMC_BTR1_DATAST_Pos)           /*!< 0x00001000 */
7228 #define FSMC_BTR1_DATAST_5           (0x20UL << FSMC_BTR1_DATAST_Pos)           /*!< 0x00002000 */
7229 #define FSMC_BTR1_DATAST_6           (0x40UL << FSMC_BTR1_DATAST_Pos)           /*!< 0x00004000 */
7230 #define FSMC_BTR1_DATAST_7           (0x80UL << FSMC_BTR1_DATAST_Pos)           /*!< 0x00008000 */
7231 
7232 #define FSMC_BTR1_BUSTURN_Pos        (16U)
7233 #define FSMC_BTR1_BUSTURN_Msk        (0xFUL << FSMC_BTR1_BUSTURN_Pos)           /*!< 0x000F0000 */
7234 #define FSMC_BTR1_BUSTURN            FSMC_BTR1_BUSTURN_Msk                     /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
7235 #define FSMC_BTR1_BUSTURN_0          (0x1UL << FSMC_BTR1_BUSTURN_Pos)           /*!< 0x00010000 */
7236 #define FSMC_BTR1_BUSTURN_1          (0x2UL << FSMC_BTR1_BUSTURN_Pos)           /*!< 0x00020000 */
7237 #define FSMC_BTR1_BUSTURN_2          (0x4UL << FSMC_BTR1_BUSTURN_Pos)           /*!< 0x00040000 */
7238 #define FSMC_BTR1_BUSTURN_3          (0x8UL << FSMC_BTR1_BUSTURN_Pos)           /*!< 0x00080000 */
7239 
7240 #define FSMC_BTR1_CLKDIV_Pos         (20U)
7241 #define FSMC_BTR1_CLKDIV_Msk         (0xFUL << FSMC_BTR1_CLKDIV_Pos)            /*!< 0x00F00000 */
7242 #define FSMC_BTR1_CLKDIV             FSMC_BTR1_CLKDIV_Msk                      /*!<CLKDIV[3:0] bits (Clock divide ratio) */
7243 #define FSMC_BTR1_CLKDIV_0           (0x1UL << FSMC_BTR1_CLKDIV_Pos)            /*!< 0x00100000 */
7244 #define FSMC_BTR1_CLKDIV_1           (0x2UL << FSMC_BTR1_CLKDIV_Pos)            /*!< 0x00200000 */
7245 #define FSMC_BTR1_CLKDIV_2           (0x4UL << FSMC_BTR1_CLKDIV_Pos)            /*!< 0x00400000 */
7246 #define FSMC_BTR1_CLKDIV_3           (0x8UL << FSMC_BTR1_CLKDIV_Pos)            /*!< 0x00800000 */
7247 
7248 #define FSMC_BTR1_DATLAT_Pos         (24U)
7249 #define FSMC_BTR1_DATLAT_Msk         (0xFUL << FSMC_BTR1_DATLAT_Pos)            /*!< 0x0F000000 */
7250 #define FSMC_BTR1_DATLAT             FSMC_BTR1_DATLAT_Msk                      /*!<DATLA[3:0] bits (Data latency) */
7251 #define FSMC_BTR1_DATLAT_0           (0x1UL << FSMC_BTR1_DATLAT_Pos)            /*!< 0x01000000 */
7252 #define FSMC_BTR1_DATLAT_1           (0x2UL << FSMC_BTR1_DATLAT_Pos)            /*!< 0x02000000 */
7253 #define FSMC_BTR1_DATLAT_2           (0x4UL << FSMC_BTR1_DATLAT_Pos)            /*!< 0x04000000 */
7254 #define FSMC_BTR1_DATLAT_3           (0x8UL << FSMC_BTR1_DATLAT_Pos)            /*!< 0x08000000 */
7255 
7256 #define FSMC_BTR1_ACCMOD_Pos         (28U)
7257 #define FSMC_BTR1_ACCMOD_Msk         (0x3UL << FSMC_BTR1_ACCMOD_Pos)            /*!< 0x30000000 */
7258 #define FSMC_BTR1_ACCMOD             FSMC_BTR1_ACCMOD_Msk                      /*!<ACCMOD[1:0] bits (Access mode) */
7259 #define FSMC_BTR1_ACCMOD_0           (0x1UL << FSMC_BTR1_ACCMOD_Pos)            /*!< 0x10000000 */
7260 #define FSMC_BTR1_ACCMOD_1           (0x2UL << FSMC_BTR1_ACCMOD_Pos)            /*!< 0x20000000 */
7261 
7262 /******************  Bit definition for FSMC_BTR2 register  *******************/
7263 #define FSMC_BTR2_ADDSET_Pos         (0U)
7264 #define FSMC_BTR2_ADDSET_Msk         (0xFUL << FSMC_BTR2_ADDSET_Pos)            /*!< 0x0000000F */
7265 #define FSMC_BTR2_ADDSET             FSMC_BTR2_ADDSET_Msk                      /*!<ADDSET[3:0] bits (Address setup phase duration) */
7266 #define FSMC_BTR2_ADDSET_0           (0x1UL << FSMC_BTR2_ADDSET_Pos)            /*!< 0x00000001 */
7267 #define FSMC_BTR2_ADDSET_1           (0x2UL << FSMC_BTR2_ADDSET_Pos)            /*!< 0x00000002 */
7268 #define FSMC_BTR2_ADDSET_2           (0x4UL << FSMC_BTR2_ADDSET_Pos)            /*!< 0x00000004 */
7269 #define FSMC_BTR2_ADDSET_3           (0x8UL << FSMC_BTR2_ADDSET_Pos)            /*!< 0x00000008 */
7270 
7271 #define FSMC_BTR2_ADDHLD_Pos         (4U)
7272 #define FSMC_BTR2_ADDHLD_Msk         (0xFUL << FSMC_BTR2_ADDHLD_Pos)            /*!< 0x000000F0 */
7273 #define FSMC_BTR2_ADDHLD             FSMC_BTR2_ADDHLD_Msk                      /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7274 #define FSMC_BTR2_ADDHLD_0           (0x1UL << FSMC_BTR2_ADDHLD_Pos)            /*!< 0x00000010 */
7275 #define FSMC_BTR2_ADDHLD_1           (0x2UL << FSMC_BTR2_ADDHLD_Pos)            /*!< 0x00000020 */
7276 #define FSMC_BTR2_ADDHLD_2           (0x4UL << FSMC_BTR2_ADDHLD_Pos)            /*!< 0x00000040 */
7277 #define FSMC_BTR2_ADDHLD_3           (0x8UL << FSMC_BTR2_ADDHLD_Pos)            /*!< 0x00000080 */
7278 
7279 #define FSMC_BTR2_DATAST_Pos         (8U)
7280 #define FSMC_BTR2_DATAST_Msk         (0xFFUL << FSMC_BTR2_DATAST_Pos)           /*!< 0x0000FF00 */
7281 #define FSMC_BTR2_DATAST             FSMC_BTR2_DATAST_Msk                      /*!<DATAST [7:0] bits (Data-phase duration) */
7282 #define FSMC_BTR2_DATAST_0           (0x01UL << FSMC_BTR2_DATAST_Pos)           /*!< 0x00000100 */
7283 #define FSMC_BTR2_DATAST_1           (0x02UL << FSMC_BTR2_DATAST_Pos)           /*!< 0x00000200 */
7284 #define FSMC_BTR2_DATAST_2           (0x04UL << FSMC_BTR2_DATAST_Pos)           /*!< 0x00000400 */
7285 #define FSMC_BTR2_DATAST_3           (0x08UL << FSMC_BTR2_DATAST_Pos)           /*!< 0x00000800 */
7286 #define FSMC_BTR2_DATAST_4           (0x10UL << FSMC_BTR2_DATAST_Pos)           /*!< 0x00001000 */
7287 #define FSMC_BTR2_DATAST_5           (0x20UL << FSMC_BTR2_DATAST_Pos)           /*!< 0x00002000 */
7288 #define FSMC_BTR2_DATAST_6           (0x40UL << FSMC_BTR2_DATAST_Pos)           /*!< 0x00004000 */
7289 #define FSMC_BTR2_DATAST_7           (0x80UL << FSMC_BTR2_DATAST_Pos)           /*!< 0x00008000 */
7290 
7291 #define FSMC_BTR2_BUSTURN_Pos        (16U)
7292 #define FSMC_BTR2_BUSTURN_Msk        (0xFUL << FSMC_BTR2_BUSTURN_Pos)           /*!< 0x000F0000 */
7293 #define FSMC_BTR2_BUSTURN            FSMC_BTR2_BUSTURN_Msk                     /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
7294 #define FSMC_BTR2_BUSTURN_0          (0x1UL << FSMC_BTR2_BUSTURN_Pos)           /*!< 0x00010000 */
7295 #define FSMC_BTR2_BUSTURN_1          (0x2UL << FSMC_BTR2_BUSTURN_Pos)           /*!< 0x00020000 */
7296 #define FSMC_BTR2_BUSTURN_2          (0x4UL << FSMC_BTR2_BUSTURN_Pos)           /*!< 0x00040000 */
7297 #define FSMC_BTR2_BUSTURN_3          (0x8UL << FSMC_BTR2_BUSTURN_Pos)           /*!< 0x00080000 */
7298 
7299 #define FSMC_BTR2_CLKDIV_Pos         (20U)
7300 #define FSMC_BTR2_CLKDIV_Msk         (0xFUL << FSMC_BTR2_CLKDIV_Pos)            /*!< 0x00F00000 */
7301 #define FSMC_BTR2_CLKDIV             FSMC_BTR2_CLKDIV_Msk                      /*!<CLKDIV[3:0] bits (Clock divide ratio) */
7302 #define FSMC_BTR2_CLKDIV_0           (0x1UL << FSMC_BTR2_CLKDIV_Pos)            /*!< 0x00100000 */
7303 #define FSMC_BTR2_CLKDIV_1           (0x2UL << FSMC_BTR2_CLKDIV_Pos)            /*!< 0x00200000 */
7304 #define FSMC_BTR2_CLKDIV_2           (0x4UL << FSMC_BTR2_CLKDIV_Pos)            /*!< 0x00400000 */
7305 #define FSMC_BTR2_CLKDIV_3           (0x8UL << FSMC_BTR2_CLKDIV_Pos)            /*!< 0x00800000 */
7306 
7307 #define FSMC_BTR2_DATLAT_Pos         (24U)
7308 #define FSMC_BTR2_DATLAT_Msk         (0xFUL << FSMC_BTR2_DATLAT_Pos)            /*!< 0x0F000000 */
7309 #define FSMC_BTR2_DATLAT             FSMC_BTR2_DATLAT_Msk                      /*!<DATLA[3:0] bits (Data latency) */
7310 #define FSMC_BTR2_DATLAT_0           (0x1UL << FSMC_BTR2_DATLAT_Pos)            /*!< 0x01000000 */
7311 #define FSMC_BTR2_DATLAT_1           (0x2UL << FSMC_BTR2_DATLAT_Pos)            /*!< 0x02000000 */
7312 #define FSMC_BTR2_DATLAT_2           (0x4UL << FSMC_BTR2_DATLAT_Pos)            /*!< 0x04000000 */
7313 #define FSMC_BTR2_DATLAT_3           (0x8UL << FSMC_BTR2_DATLAT_Pos)            /*!< 0x08000000 */
7314 
7315 #define FSMC_BTR2_ACCMOD_Pos         (28U)
7316 #define FSMC_BTR2_ACCMOD_Msk         (0x3UL << FSMC_BTR2_ACCMOD_Pos)            /*!< 0x30000000 */
7317 #define FSMC_BTR2_ACCMOD             FSMC_BTR2_ACCMOD_Msk                      /*!<ACCMOD[1:0] bits (Access mode) */
7318 #define FSMC_BTR2_ACCMOD_0           (0x1UL << FSMC_BTR2_ACCMOD_Pos)            /*!< 0x10000000 */
7319 #define FSMC_BTR2_ACCMOD_1           (0x2UL << FSMC_BTR2_ACCMOD_Pos)            /*!< 0x20000000 */
7320 
7321 /*******************  Bit definition for FSMC_BTR3 register  *******************/
7322 #define FSMC_BTR3_ADDSET_Pos         (0U)
7323 #define FSMC_BTR3_ADDSET_Msk         (0xFUL << FSMC_BTR3_ADDSET_Pos)            /*!< 0x0000000F */
7324 #define FSMC_BTR3_ADDSET             FSMC_BTR3_ADDSET_Msk                      /*!<ADDSET[3:0] bits (Address setup phase duration) */
7325 #define FSMC_BTR3_ADDSET_0           (0x1UL << FSMC_BTR3_ADDSET_Pos)            /*!< 0x00000001 */
7326 #define FSMC_BTR3_ADDSET_1           (0x2UL << FSMC_BTR3_ADDSET_Pos)            /*!< 0x00000002 */
7327 #define FSMC_BTR3_ADDSET_2           (0x4UL << FSMC_BTR3_ADDSET_Pos)            /*!< 0x00000004 */
7328 #define FSMC_BTR3_ADDSET_3           (0x8UL << FSMC_BTR3_ADDSET_Pos)            /*!< 0x00000008 */
7329 
7330 #define FSMC_BTR3_ADDHLD_Pos         (4U)
7331 #define FSMC_BTR3_ADDHLD_Msk         (0xFUL << FSMC_BTR3_ADDHLD_Pos)            /*!< 0x000000F0 */
7332 #define FSMC_BTR3_ADDHLD             FSMC_BTR3_ADDHLD_Msk                      /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7333 #define FSMC_BTR3_ADDHLD_0           (0x1UL << FSMC_BTR3_ADDHLD_Pos)            /*!< 0x00000010 */
7334 #define FSMC_BTR3_ADDHLD_1           (0x2UL << FSMC_BTR3_ADDHLD_Pos)            /*!< 0x00000020 */
7335 #define FSMC_BTR3_ADDHLD_2           (0x4UL << FSMC_BTR3_ADDHLD_Pos)            /*!< 0x00000040 */
7336 #define FSMC_BTR3_ADDHLD_3           (0x8UL << FSMC_BTR3_ADDHLD_Pos)            /*!< 0x00000080 */
7337 
7338 #define FSMC_BTR3_DATAST_Pos         (8U)
7339 #define FSMC_BTR3_DATAST_Msk         (0xFFUL << FSMC_BTR3_DATAST_Pos)           /*!< 0x0000FF00 */
7340 #define FSMC_BTR3_DATAST             FSMC_BTR3_DATAST_Msk                      /*!<DATAST [7:0] bits (Data-phase duration) */
7341 #define FSMC_BTR3_DATAST_0           (0x01UL << FSMC_BTR3_DATAST_Pos)           /*!< 0x00000100 */
7342 #define FSMC_BTR3_DATAST_1           (0x02UL << FSMC_BTR3_DATAST_Pos)           /*!< 0x00000200 */
7343 #define FSMC_BTR3_DATAST_2           (0x04UL << FSMC_BTR3_DATAST_Pos)           /*!< 0x00000400 */
7344 #define FSMC_BTR3_DATAST_3           (0x08UL << FSMC_BTR3_DATAST_Pos)           /*!< 0x00000800 */
7345 #define FSMC_BTR3_DATAST_4           (0x10UL << FSMC_BTR3_DATAST_Pos)           /*!< 0x00001000 */
7346 #define FSMC_BTR3_DATAST_5           (0x20UL << FSMC_BTR3_DATAST_Pos)           /*!< 0x00002000 */
7347 #define FSMC_BTR3_DATAST_6           (0x40UL << FSMC_BTR3_DATAST_Pos)           /*!< 0x00004000 */
7348 #define FSMC_BTR3_DATAST_7           (0x80UL << FSMC_BTR3_DATAST_Pos)           /*!< 0x00008000 */
7349 
7350 #define FSMC_BTR3_BUSTURN_Pos        (16U)
7351 #define FSMC_BTR3_BUSTURN_Msk        (0xFUL << FSMC_BTR3_BUSTURN_Pos)           /*!< 0x000F0000 */
7352 #define FSMC_BTR3_BUSTURN            FSMC_BTR3_BUSTURN_Msk                     /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
7353 #define FSMC_BTR3_BUSTURN_0          (0x1UL << FSMC_BTR3_BUSTURN_Pos)           /*!< 0x00010000 */
7354 #define FSMC_BTR3_BUSTURN_1          (0x2UL << FSMC_BTR3_BUSTURN_Pos)           /*!< 0x00020000 */
7355 #define FSMC_BTR3_BUSTURN_2          (0x4UL << FSMC_BTR3_BUSTURN_Pos)           /*!< 0x00040000 */
7356 #define FSMC_BTR3_BUSTURN_3          (0x8UL << FSMC_BTR3_BUSTURN_Pos)           /*!< 0x00080000 */
7357 
7358 #define FSMC_BTR3_CLKDIV_Pos         (20U)
7359 #define FSMC_BTR3_CLKDIV_Msk         (0xFUL << FSMC_BTR3_CLKDIV_Pos)            /*!< 0x00F00000 */
7360 #define FSMC_BTR3_CLKDIV             FSMC_BTR3_CLKDIV_Msk                      /*!<CLKDIV[3:0] bits (Clock divide ratio) */
7361 #define FSMC_BTR3_CLKDIV_0           (0x1UL << FSMC_BTR3_CLKDIV_Pos)            /*!< 0x00100000 */
7362 #define FSMC_BTR3_CLKDIV_1           (0x2UL << FSMC_BTR3_CLKDIV_Pos)            /*!< 0x00200000 */
7363 #define FSMC_BTR3_CLKDIV_2           (0x4UL << FSMC_BTR3_CLKDIV_Pos)            /*!< 0x00400000 */
7364 #define FSMC_BTR3_CLKDIV_3           (0x8UL << FSMC_BTR3_CLKDIV_Pos)            /*!< 0x00800000 */
7365 
7366 #define FSMC_BTR3_DATLAT_Pos         (24U)
7367 #define FSMC_BTR3_DATLAT_Msk         (0xFUL << FSMC_BTR3_DATLAT_Pos)            /*!< 0x0F000000 */
7368 #define FSMC_BTR3_DATLAT             FSMC_BTR3_DATLAT_Msk                      /*!<DATLA[3:0] bits (Data latency) */
7369 #define FSMC_BTR3_DATLAT_0           (0x1UL << FSMC_BTR3_DATLAT_Pos)            /*!< 0x01000000 */
7370 #define FSMC_BTR3_DATLAT_1           (0x2UL << FSMC_BTR3_DATLAT_Pos)            /*!< 0x02000000 */
7371 #define FSMC_BTR3_DATLAT_2           (0x4UL << FSMC_BTR3_DATLAT_Pos)            /*!< 0x04000000 */
7372 #define FSMC_BTR3_DATLAT_3           (0x8UL << FSMC_BTR3_DATLAT_Pos)            /*!< 0x08000000 */
7373 
7374 #define FSMC_BTR3_ACCMOD_Pos         (28U)
7375 #define FSMC_BTR3_ACCMOD_Msk         (0x3UL << FSMC_BTR3_ACCMOD_Pos)            /*!< 0x30000000 */
7376 #define FSMC_BTR3_ACCMOD             FSMC_BTR3_ACCMOD_Msk                      /*!<ACCMOD[1:0] bits (Access mode) */
7377 #define FSMC_BTR3_ACCMOD_0           (0x1UL << FSMC_BTR3_ACCMOD_Pos)            /*!< 0x10000000 */
7378 #define FSMC_BTR3_ACCMOD_1           (0x2UL << FSMC_BTR3_ACCMOD_Pos)            /*!< 0x20000000 */
7379 
7380 /******************  Bit definition for FSMC_BTR4 register  *******************/
7381 #define FSMC_BTR4_ADDSET_Pos         (0U)
7382 #define FSMC_BTR4_ADDSET_Msk         (0xFUL << FSMC_BTR4_ADDSET_Pos)            /*!< 0x0000000F */
7383 #define FSMC_BTR4_ADDSET             FSMC_BTR4_ADDSET_Msk                      /*!<ADDSET[3:0] bits (Address setup phase duration) */
7384 #define FSMC_BTR4_ADDSET_0           (0x1UL << FSMC_BTR4_ADDSET_Pos)            /*!< 0x00000001 */
7385 #define FSMC_BTR4_ADDSET_1           (0x2UL << FSMC_BTR4_ADDSET_Pos)            /*!< 0x00000002 */
7386 #define FSMC_BTR4_ADDSET_2           (0x4UL << FSMC_BTR4_ADDSET_Pos)            /*!< 0x00000004 */
7387 #define FSMC_BTR4_ADDSET_3           (0x8UL << FSMC_BTR4_ADDSET_Pos)            /*!< 0x00000008 */
7388 
7389 #define FSMC_BTR4_ADDHLD_Pos         (4U)
7390 #define FSMC_BTR4_ADDHLD_Msk         (0xFUL << FSMC_BTR4_ADDHLD_Pos)            /*!< 0x000000F0 */
7391 #define FSMC_BTR4_ADDHLD             FSMC_BTR4_ADDHLD_Msk                      /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7392 #define FSMC_BTR4_ADDHLD_0           (0x1UL << FSMC_BTR4_ADDHLD_Pos)            /*!< 0x00000010 */
7393 #define FSMC_BTR4_ADDHLD_1           (0x2UL << FSMC_BTR4_ADDHLD_Pos)            /*!< 0x00000020 */
7394 #define FSMC_BTR4_ADDHLD_2           (0x4UL << FSMC_BTR4_ADDHLD_Pos)            /*!< 0x00000040 */
7395 #define FSMC_BTR4_ADDHLD_3           (0x8UL << FSMC_BTR4_ADDHLD_Pos)            /*!< 0x00000080 */
7396 
7397 #define FSMC_BTR4_DATAST_Pos         (8U)
7398 #define FSMC_BTR4_DATAST_Msk         (0xFFUL << FSMC_BTR4_DATAST_Pos)           /*!< 0x0000FF00 */
7399 #define FSMC_BTR4_DATAST             FSMC_BTR4_DATAST_Msk                      /*!<DATAST [7:0] bits (Data-phase duration) */
7400 #define FSMC_BTR4_DATAST_0           (0x01UL << FSMC_BTR4_DATAST_Pos)           /*!< 0x00000100 */
7401 #define FSMC_BTR4_DATAST_1           (0x02UL << FSMC_BTR4_DATAST_Pos)           /*!< 0x00000200 */
7402 #define FSMC_BTR4_DATAST_2           (0x04UL << FSMC_BTR4_DATAST_Pos)           /*!< 0x00000400 */
7403 #define FSMC_BTR4_DATAST_3           (0x08UL << FSMC_BTR4_DATAST_Pos)           /*!< 0x00000800 */
7404 #define FSMC_BTR4_DATAST_4           (0x10UL << FSMC_BTR4_DATAST_Pos)           /*!< 0x00001000 */
7405 #define FSMC_BTR4_DATAST_5           (0x20UL << FSMC_BTR4_DATAST_Pos)           /*!< 0x00002000 */
7406 #define FSMC_BTR4_DATAST_6           (0x40UL << FSMC_BTR4_DATAST_Pos)           /*!< 0x00004000 */
7407 #define FSMC_BTR4_DATAST_7           (0x80UL << FSMC_BTR4_DATAST_Pos)           /*!< 0x00008000 */
7408 
7409 #define FSMC_BTR4_BUSTURN_Pos        (16U)
7410 #define FSMC_BTR4_BUSTURN_Msk        (0xFUL << FSMC_BTR4_BUSTURN_Pos)           /*!< 0x000F0000 */
7411 #define FSMC_BTR4_BUSTURN            FSMC_BTR4_BUSTURN_Msk                     /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
7412 #define FSMC_BTR4_BUSTURN_0          (0x1UL << FSMC_BTR4_BUSTURN_Pos)           /*!< 0x00010000 */
7413 #define FSMC_BTR4_BUSTURN_1          (0x2UL << FSMC_BTR4_BUSTURN_Pos)           /*!< 0x00020000 */
7414 #define FSMC_BTR4_BUSTURN_2          (0x4UL << FSMC_BTR4_BUSTURN_Pos)           /*!< 0x00040000 */
7415 #define FSMC_BTR4_BUSTURN_3          (0x8UL << FSMC_BTR4_BUSTURN_Pos)           /*!< 0x00080000 */
7416 
7417 #define FSMC_BTR4_CLKDIV_Pos         (20U)
7418 #define FSMC_BTR4_CLKDIV_Msk         (0xFUL << FSMC_BTR4_CLKDIV_Pos)            /*!< 0x00F00000 */
7419 #define FSMC_BTR4_CLKDIV             FSMC_BTR4_CLKDIV_Msk                      /*!<CLKDIV[3:0] bits (Clock divide ratio) */
7420 #define FSMC_BTR4_CLKDIV_0           (0x1UL << FSMC_BTR4_CLKDIV_Pos)            /*!< 0x00100000 */
7421 #define FSMC_BTR4_CLKDIV_1           (0x2UL << FSMC_BTR4_CLKDIV_Pos)            /*!< 0x00200000 */
7422 #define FSMC_BTR4_CLKDIV_2           (0x4UL << FSMC_BTR4_CLKDIV_Pos)            /*!< 0x00400000 */
7423 #define FSMC_BTR4_CLKDIV_3           (0x8UL << FSMC_BTR4_CLKDIV_Pos)            /*!< 0x00800000 */
7424 
7425 #define FSMC_BTR4_DATLAT_Pos         (24U)
7426 #define FSMC_BTR4_DATLAT_Msk         (0xFUL << FSMC_BTR4_DATLAT_Pos)            /*!< 0x0F000000 */
7427 #define FSMC_BTR4_DATLAT             FSMC_BTR4_DATLAT_Msk                      /*!<DATLA[3:0] bits (Data latency) */
7428 #define FSMC_BTR4_DATLAT_0           (0x1UL << FSMC_BTR4_DATLAT_Pos)            /*!< 0x01000000 */
7429 #define FSMC_BTR4_DATLAT_1           (0x2UL << FSMC_BTR4_DATLAT_Pos)            /*!< 0x02000000 */
7430 #define FSMC_BTR4_DATLAT_2           (0x4UL << FSMC_BTR4_DATLAT_Pos)            /*!< 0x04000000 */
7431 #define FSMC_BTR4_DATLAT_3           (0x8UL << FSMC_BTR4_DATLAT_Pos)            /*!< 0x08000000 */
7432 
7433 #define FSMC_BTR4_ACCMOD_Pos         (28U)
7434 #define FSMC_BTR4_ACCMOD_Msk         (0x3UL << FSMC_BTR4_ACCMOD_Pos)            /*!< 0x30000000 */
7435 #define FSMC_BTR4_ACCMOD             FSMC_BTR4_ACCMOD_Msk                      /*!<ACCMOD[1:0] bits (Access mode) */
7436 #define FSMC_BTR4_ACCMOD_0           (0x1UL << FSMC_BTR4_ACCMOD_Pos)            /*!< 0x10000000 */
7437 #define FSMC_BTR4_ACCMOD_1           (0x2UL << FSMC_BTR4_ACCMOD_Pos)            /*!< 0x20000000 */
7438 
7439 /******************  Bit definition for FSMC_BWTR1 register  ******************/
7440 #define FSMC_BWTR1_ADDSET_Pos        (0U)
7441 #define FSMC_BWTR1_ADDSET_Msk        (0xFUL << FSMC_BWTR1_ADDSET_Pos)           /*!< 0x0000000F */
7442 #define FSMC_BWTR1_ADDSET            FSMC_BWTR1_ADDSET_Msk                     /*!<ADDSET[3:0] bits (Address setup phase duration) */
7443 #define FSMC_BWTR1_ADDSET_0          (0x1UL << FSMC_BWTR1_ADDSET_Pos)           /*!< 0x00000001 */
7444 #define FSMC_BWTR1_ADDSET_1          (0x2UL << FSMC_BWTR1_ADDSET_Pos)           /*!< 0x00000002 */
7445 #define FSMC_BWTR1_ADDSET_2          (0x4UL << FSMC_BWTR1_ADDSET_Pos)           /*!< 0x00000004 */
7446 #define FSMC_BWTR1_ADDSET_3          (0x8UL << FSMC_BWTR1_ADDSET_Pos)           /*!< 0x00000008 */
7447 
7448 #define FSMC_BWTR1_ADDHLD_Pos        (4U)
7449 #define FSMC_BWTR1_ADDHLD_Msk        (0xFUL << FSMC_BWTR1_ADDHLD_Pos)           /*!< 0x000000F0 */
7450 #define FSMC_BWTR1_ADDHLD            FSMC_BWTR1_ADDHLD_Msk                     /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7451 #define FSMC_BWTR1_ADDHLD_0          (0x1UL << FSMC_BWTR1_ADDHLD_Pos)           /*!< 0x00000010 */
7452 #define FSMC_BWTR1_ADDHLD_1          (0x2UL << FSMC_BWTR1_ADDHLD_Pos)           /*!< 0x00000020 */
7453 #define FSMC_BWTR1_ADDHLD_2          (0x4UL << FSMC_BWTR1_ADDHLD_Pos)           /*!< 0x00000040 */
7454 #define FSMC_BWTR1_ADDHLD_3          (0x8UL << FSMC_BWTR1_ADDHLD_Pos)           /*!< 0x00000080 */
7455 
7456 #define FSMC_BWTR1_DATAST_Pos        (8U)
7457 #define FSMC_BWTR1_DATAST_Msk        (0xFFUL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x0000FF00 */
7458 #define FSMC_BWTR1_DATAST            FSMC_BWTR1_DATAST_Msk                     /*!<DATAST [7:0] bits (Data-phase duration) */
7459 #define FSMC_BWTR1_DATAST_0          (0x01UL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00000100 */
7460 #define FSMC_BWTR1_DATAST_1          (0x02UL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00000200 */
7461 #define FSMC_BWTR1_DATAST_2          (0x04UL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00000400 */
7462 #define FSMC_BWTR1_DATAST_3          (0x08UL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00000800 */
7463 #define FSMC_BWTR1_DATAST_4          (0x10UL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00001000 */
7464 #define FSMC_BWTR1_DATAST_5          (0x20UL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00002000 */
7465 #define FSMC_BWTR1_DATAST_6          (0x40UL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00004000 */
7466 #define FSMC_BWTR1_DATAST_7          (0x80UL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00008000 */
7467 
7468 #define FSMC_BWTR1_BUSTURN_Pos       (16U)
7469 #define FSMC_BWTR1_BUSTURN_Msk       (0xFUL << FSMC_BWTR1_BUSTURN_Pos)          /*!< 0x000F0000 */
7470 #define FSMC_BWTR1_BUSTURN           FSMC_BWTR1_BUSTURN_Msk                    /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
7471 #define FSMC_BWTR1_BUSTURN_0         (0x1UL << FSMC_BWTR1_BUSTURN_Pos)          /*!< 0x00010000 */
7472 #define FSMC_BWTR1_BUSTURN_1         (0x2UL << FSMC_BWTR1_BUSTURN_Pos)          /*!< 0x00020000 */
7473 #define FSMC_BWTR1_BUSTURN_2         (0x4UL << FSMC_BWTR1_BUSTURN_Pos)          /*!< 0x00040000 */
7474 #define FSMC_BWTR1_BUSTURN_3         (0x8UL << FSMC_BWTR1_BUSTURN_Pos)          /*!< 0x00080000 */
7475 
7476 #define FSMC_BWTR1_ACCMOD_Pos        (28U)
7477 #define FSMC_BWTR1_ACCMOD_Msk        (0x3UL << FSMC_BWTR1_ACCMOD_Pos)           /*!< 0x30000000 */
7478 #define FSMC_BWTR1_ACCMOD            FSMC_BWTR1_ACCMOD_Msk                     /*!<ACCMOD[1:0] bits (Access mode) */
7479 #define FSMC_BWTR1_ACCMOD_0          (0x1UL << FSMC_BWTR1_ACCMOD_Pos)           /*!< 0x10000000 */
7480 #define FSMC_BWTR1_ACCMOD_1          (0x2UL << FSMC_BWTR1_ACCMOD_Pos)           /*!< 0x20000000 */
7481 
7482 /******************  Bit definition for FSMC_BWTR2 register  ******************/
7483 #define FSMC_BWTR2_ADDSET_Pos        (0U)
7484 #define FSMC_BWTR2_ADDSET_Msk        (0xFUL << FSMC_BWTR2_ADDSET_Pos)           /*!< 0x0000000F */
7485 #define FSMC_BWTR2_ADDSET            FSMC_BWTR2_ADDSET_Msk                     /*!<ADDSET[3:0] bits (Address setup phase duration) */
7486 #define FSMC_BWTR2_ADDSET_0          (0x1UL << FSMC_BWTR2_ADDSET_Pos)           /*!< 0x00000001 */
7487 #define FSMC_BWTR2_ADDSET_1          (0x2UL << FSMC_BWTR2_ADDSET_Pos)           /*!< 0x00000002 */
7488 #define FSMC_BWTR2_ADDSET_2          (0x4UL << FSMC_BWTR2_ADDSET_Pos)           /*!< 0x00000004 */
7489 #define FSMC_BWTR2_ADDSET_3          (0x8UL << FSMC_BWTR2_ADDSET_Pos)           /*!< 0x00000008 */
7490 
7491 #define FSMC_BWTR2_ADDHLD_Pos        (4U)
7492 #define FSMC_BWTR2_ADDHLD_Msk        (0xFUL << FSMC_BWTR2_ADDHLD_Pos)           /*!< 0x000000F0 */
7493 #define FSMC_BWTR2_ADDHLD            FSMC_BWTR2_ADDHLD_Msk                     /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7494 #define FSMC_BWTR2_ADDHLD_0          (0x1UL << FSMC_BWTR2_ADDHLD_Pos)           /*!< 0x00000010 */
7495 #define FSMC_BWTR2_ADDHLD_1          (0x2UL << FSMC_BWTR2_ADDHLD_Pos)           /*!< 0x00000020 */
7496 #define FSMC_BWTR2_ADDHLD_2          (0x4UL << FSMC_BWTR2_ADDHLD_Pos)           /*!< 0x00000040 */
7497 #define FSMC_BWTR2_ADDHLD_3          (0x8UL << FSMC_BWTR2_ADDHLD_Pos)           /*!< 0x00000080 */
7498 
7499 #define FSMC_BWTR2_DATAST_Pos        (8U)
7500 #define FSMC_BWTR2_DATAST_Msk        (0xFFUL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x0000FF00 */
7501 #define FSMC_BWTR2_DATAST            FSMC_BWTR2_DATAST_Msk                     /*!<DATAST [7:0] bits (Data-phase duration) */
7502 #define FSMC_BWTR2_DATAST_0          (0x01UL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00000100 */
7503 #define FSMC_BWTR2_DATAST_1          (0x02UL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00000200 */
7504 #define FSMC_BWTR2_DATAST_2          (0x04UL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00000400 */
7505 #define FSMC_BWTR2_DATAST_3          (0x08UL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00000800 */
7506 #define FSMC_BWTR2_DATAST_4          (0x10UL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00001000 */
7507 #define FSMC_BWTR2_DATAST_5          (0x20UL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00002000 */
7508 #define FSMC_BWTR2_DATAST_6          (0x40UL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00004000 */
7509 #define FSMC_BWTR2_DATAST_7          (0x80UL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00008000 */
7510 
7511 #define FSMC_BWTR2_BUSTURN_Pos       (16U)
7512 #define FSMC_BWTR2_BUSTURN_Msk       (0xFUL << FSMC_BWTR2_BUSTURN_Pos)          /*!< 0x000F0000 */
7513 #define FSMC_BWTR2_BUSTURN           FSMC_BWTR2_BUSTURN_Msk                    /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
7514 #define FSMC_BWTR2_BUSTURN_0         (0x1UL << FSMC_BWTR2_BUSTURN_Pos)          /*!< 0x00010000 */
7515 #define FSMC_BWTR2_BUSTURN_1         (0x2UL << FSMC_BWTR2_BUSTURN_Pos)          /*!< 0x00020000 */
7516 #define FSMC_BWTR2_BUSTURN_2         (0x4UL << FSMC_BWTR2_BUSTURN_Pos)          /*!< 0x00040000 */
7517 #define FSMC_BWTR2_BUSTURN_3         (0x8UL << FSMC_BWTR2_BUSTURN_Pos)          /*!< 0x00080000 */
7518 
7519 #define FSMC_BWTR2_ACCMOD_Pos        (28U)
7520 #define FSMC_BWTR2_ACCMOD_Msk        (0x3UL << FSMC_BWTR2_ACCMOD_Pos)           /*!< 0x30000000 */
7521 #define FSMC_BWTR2_ACCMOD            FSMC_BWTR2_ACCMOD_Msk                     /*!<ACCMOD[1:0] bits (Access mode) */
7522 #define FSMC_BWTR2_ACCMOD_0          (0x1UL << FSMC_BWTR2_ACCMOD_Pos)           /*!< 0x10000000 */
7523 #define FSMC_BWTR2_ACCMOD_1          (0x2UL << FSMC_BWTR2_ACCMOD_Pos)           /*!< 0x20000000 */
7524 
7525 /******************  Bit definition for FSMC_BWTR3 register  ******************/
7526 #define FSMC_BWTR3_ADDSET_Pos        (0U)
7527 #define FSMC_BWTR3_ADDSET_Msk        (0xFUL << FSMC_BWTR3_ADDSET_Pos)           /*!< 0x0000000F */
7528 #define FSMC_BWTR3_ADDSET            FSMC_BWTR3_ADDSET_Msk                     /*!<ADDSET[3:0] bits (Address setup phase duration) */
7529 #define FSMC_BWTR3_ADDSET_0          (0x1UL << FSMC_BWTR3_ADDSET_Pos)           /*!< 0x00000001 */
7530 #define FSMC_BWTR3_ADDSET_1          (0x2UL << FSMC_BWTR3_ADDSET_Pos)           /*!< 0x00000002 */
7531 #define FSMC_BWTR3_ADDSET_2          (0x4UL << FSMC_BWTR3_ADDSET_Pos)           /*!< 0x00000004 */
7532 #define FSMC_BWTR3_ADDSET_3          (0x8UL << FSMC_BWTR3_ADDSET_Pos)           /*!< 0x00000008 */
7533 
7534 #define FSMC_BWTR3_ADDHLD_Pos        (4U)
7535 #define FSMC_BWTR3_ADDHLD_Msk        (0xFUL << FSMC_BWTR3_ADDHLD_Pos)           /*!< 0x000000F0 */
7536 #define FSMC_BWTR3_ADDHLD            FSMC_BWTR3_ADDHLD_Msk                     /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7537 #define FSMC_BWTR3_ADDHLD_0          (0x1UL << FSMC_BWTR3_ADDHLD_Pos)           /*!< 0x00000010 */
7538 #define FSMC_BWTR3_ADDHLD_1          (0x2UL << FSMC_BWTR3_ADDHLD_Pos)           /*!< 0x00000020 */
7539 #define FSMC_BWTR3_ADDHLD_2          (0x4UL << FSMC_BWTR3_ADDHLD_Pos)           /*!< 0x00000040 */
7540 #define FSMC_BWTR3_ADDHLD_3          (0x8UL << FSMC_BWTR3_ADDHLD_Pos)           /*!< 0x00000080 */
7541 
7542 #define FSMC_BWTR3_DATAST_Pos        (8U)
7543 #define FSMC_BWTR3_DATAST_Msk        (0xFFUL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x0000FF00 */
7544 #define FSMC_BWTR3_DATAST            FSMC_BWTR3_DATAST_Msk                     /*!<DATAST [7:0] bits (Data-phase duration) */
7545 #define FSMC_BWTR3_DATAST_0          (0x01UL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00000100 */
7546 #define FSMC_BWTR3_DATAST_1          (0x02UL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00000200 */
7547 #define FSMC_BWTR3_DATAST_2          (0x04UL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00000400 */
7548 #define FSMC_BWTR3_DATAST_3          (0x08UL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00000800 */
7549 #define FSMC_BWTR3_DATAST_4          (0x10UL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00001000 */
7550 #define FSMC_BWTR3_DATAST_5          (0x20UL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00002000 */
7551 #define FSMC_BWTR3_DATAST_6          (0x40UL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00004000 */
7552 #define FSMC_BWTR3_DATAST_7          (0x80UL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00008000 */
7553 
7554 #define FSMC_BWTR3_BUSTURN_Pos       (16U)
7555 #define FSMC_BWTR3_BUSTURN_Msk       (0xFUL << FSMC_BWTR3_BUSTURN_Pos)          /*!< 0x000F0000 */
7556 #define FSMC_BWTR3_BUSTURN           FSMC_BWTR3_BUSTURN_Msk                    /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
7557 #define FSMC_BWTR3_BUSTURN_0         (0x1UL << FSMC_BWTR3_BUSTURN_Pos)          /*!< 0x00010000 */
7558 #define FSMC_BWTR3_BUSTURN_1         (0x2UL << FSMC_BWTR3_BUSTURN_Pos)          /*!< 0x00020000 */
7559 #define FSMC_BWTR3_BUSTURN_2         (0x4UL << FSMC_BWTR3_BUSTURN_Pos)          /*!< 0x00040000 */
7560 #define FSMC_BWTR3_BUSTURN_3         (0x8UL << FSMC_BWTR3_BUSTURN_Pos)          /*!< 0x00080000 */
7561 
7562 #define FSMC_BWTR3_ACCMOD_Pos        (28U)
7563 #define FSMC_BWTR3_ACCMOD_Msk        (0x3UL << FSMC_BWTR3_ACCMOD_Pos)           /*!< 0x30000000 */
7564 #define FSMC_BWTR3_ACCMOD            FSMC_BWTR3_ACCMOD_Msk                     /*!<ACCMOD[1:0] bits (Access mode) */
7565 #define FSMC_BWTR3_ACCMOD_0          (0x1UL << FSMC_BWTR3_ACCMOD_Pos)           /*!< 0x10000000 */
7566 #define FSMC_BWTR3_ACCMOD_1          (0x2UL << FSMC_BWTR3_ACCMOD_Pos)           /*!< 0x20000000 */
7567 
7568 /******************  Bit definition for FSMC_BWTR4 register  ******************/
7569 #define FSMC_BWTR4_ADDSET_Pos        (0U)
7570 #define FSMC_BWTR4_ADDSET_Msk        (0xFUL << FSMC_BWTR4_ADDSET_Pos)           /*!< 0x0000000F */
7571 #define FSMC_BWTR4_ADDSET            FSMC_BWTR4_ADDSET_Msk                     /*!<ADDSET[3:0] bits (Address setup phase duration) */
7572 #define FSMC_BWTR4_ADDSET_0          (0x1UL << FSMC_BWTR4_ADDSET_Pos)           /*!< 0x00000001 */
7573 #define FSMC_BWTR4_ADDSET_1          (0x2UL << FSMC_BWTR4_ADDSET_Pos)           /*!< 0x00000002 */
7574 #define FSMC_BWTR4_ADDSET_2          (0x4UL << FSMC_BWTR4_ADDSET_Pos)           /*!< 0x00000004 */
7575 #define FSMC_BWTR4_ADDSET_3          (0x8UL << FSMC_BWTR4_ADDSET_Pos)           /*!< 0x00000008 */
7576 
7577 #define FSMC_BWTR4_ADDHLD_Pos        (4U)
7578 #define FSMC_BWTR4_ADDHLD_Msk        (0xFUL << FSMC_BWTR4_ADDHLD_Pos)           /*!< 0x000000F0 */
7579 #define FSMC_BWTR4_ADDHLD            FSMC_BWTR4_ADDHLD_Msk                     /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7580 #define FSMC_BWTR4_ADDHLD_0          (0x1UL << FSMC_BWTR4_ADDHLD_Pos)           /*!< 0x00000010 */
7581 #define FSMC_BWTR4_ADDHLD_1          (0x2UL << FSMC_BWTR4_ADDHLD_Pos)           /*!< 0x00000020 */
7582 #define FSMC_BWTR4_ADDHLD_2          (0x4UL << FSMC_BWTR4_ADDHLD_Pos)           /*!< 0x00000040 */
7583 #define FSMC_BWTR4_ADDHLD_3          (0x8UL << FSMC_BWTR4_ADDHLD_Pos)           /*!< 0x00000080 */
7584 
7585 #define FSMC_BWTR4_DATAST_Pos        (8U)
7586 #define FSMC_BWTR4_DATAST_Msk        (0xFFUL << FSMC_BWTR4_DATAST_Pos)          /*!< 0x0000FF00 */
7587 #define FSMC_BWTR4_DATAST            FSMC_BWTR4_DATAST_Msk                     /*!<DATAST [3:0] bits (Data-phase duration) */
7588 #define FSMC_BWTR4_DATAST_0          0x00000100U                               /*!<Bit 0 */
7589 #define FSMC_BWTR4_DATAST_1          0x00000200U                               /*!<Bit 1 */
7590 #define FSMC_BWTR4_DATAST_2          0x00000400U                               /*!<Bit 2 */
7591 #define FSMC_BWTR4_DATAST_3          0x00000800U                               /*!<Bit 3 */
7592 #define FSMC_BWTR4_DATAST_4          0x00001000U                               /*!<Bit 4 */
7593 #define FSMC_BWTR4_DATAST_5          0x00002000U                               /*!<Bit 5 */
7594 #define FSMC_BWTR4_DATAST_6          0x00004000U                               /*!<Bit 6 */
7595 #define FSMC_BWTR4_DATAST_7          0x00008000U                               /*!<Bit 7 */
7596 
7597 #define FSMC_BWTR4_BUSTURN_Pos       (16U)
7598 #define FSMC_BWTR4_BUSTURN_Msk       (0xFUL << FSMC_BWTR4_BUSTURN_Pos)          /*!< 0x000F0000 */
7599 #define FSMC_BWTR4_BUSTURN           FSMC_BWTR4_BUSTURN_Msk                    /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
7600 #define FSMC_BWTR4_BUSTURN_0         (0x1UL << FSMC_BWTR4_BUSTURN_Pos)          /*!< 0x00010000 */
7601 #define FSMC_BWTR4_BUSTURN_1         (0x2UL << FSMC_BWTR4_BUSTURN_Pos)          /*!< 0x00020000 */
7602 #define FSMC_BWTR4_BUSTURN_2         (0x4UL << FSMC_BWTR4_BUSTURN_Pos)          /*!< 0x00040000 */
7603 #define FSMC_BWTR4_BUSTURN_3         (0x8UL << FSMC_BWTR4_BUSTURN_Pos)          /*!< 0x00080000 */
7604 
7605 #define FSMC_BWTR4_ACCMOD_Pos        (28U)
7606 #define FSMC_BWTR4_ACCMOD_Msk        (0x3UL << FSMC_BWTR4_ACCMOD_Pos)           /*!< 0x30000000 */
7607 #define FSMC_BWTR4_ACCMOD            FSMC_BWTR4_ACCMOD_Msk                     /*!<ACCMOD[1:0] bits (Access mode) */
7608 #define FSMC_BWTR4_ACCMOD_0          (0x1UL << FSMC_BWTR4_ACCMOD_Pos)           /*!< 0x10000000 */
7609 #define FSMC_BWTR4_ACCMOD_1          (0x2UL << FSMC_BWTR4_ACCMOD_Pos)           /*!< 0x20000000 */
7610 
7611 /******************************************************************************/
7612 /*                                                                            */
7613 /*                            General Purpose I/O                             */
7614 /*                                                                            */
7615 /******************************************************************************/
7616 /******************  Bits definition for GPIO_MODER register  *****************/
7617 #define GPIO_MODER_MODER0_Pos            (0U)
7618 #define GPIO_MODER_MODER0_Msk            (0x3UL << GPIO_MODER_MODER0_Pos)       /*!< 0x00000003 */
7619 #define GPIO_MODER_MODER0                GPIO_MODER_MODER0_Msk
7620 #define GPIO_MODER_MODER0_0              (0x1UL << GPIO_MODER_MODER0_Pos)       /*!< 0x00000001 */
7621 #define GPIO_MODER_MODER0_1              (0x2UL << GPIO_MODER_MODER0_Pos)       /*!< 0x00000002 */
7622 #define GPIO_MODER_MODER1_Pos            (2U)
7623 #define GPIO_MODER_MODER1_Msk            (0x3UL << GPIO_MODER_MODER1_Pos)       /*!< 0x0000000C */
7624 #define GPIO_MODER_MODER1                GPIO_MODER_MODER1_Msk
7625 #define GPIO_MODER_MODER1_0              (0x1UL << GPIO_MODER_MODER1_Pos)       /*!< 0x00000004 */
7626 #define GPIO_MODER_MODER1_1              (0x2UL << GPIO_MODER_MODER1_Pos)       /*!< 0x00000008 */
7627 #define GPIO_MODER_MODER2_Pos            (4U)
7628 #define GPIO_MODER_MODER2_Msk            (0x3UL << GPIO_MODER_MODER2_Pos)       /*!< 0x00000030 */
7629 #define GPIO_MODER_MODER2                GPIO_MODER_MODER2_Msk
7630 #define GPIO_MODER_MODER2_0              (0x1UL << GPIO_MODER_MODER2_Pos)       /*!< 0x00000010 */
7631 #define GPIO_MODER_MODER2_1              (0x2UL << GPIO_MODER_MODER2_Pos)       /*!< 0x00000020 */
7632 #define GPIO_MODER_MODER3_Pos            (6U)
7633 #define GPIO_MODER_MODER3_Msk            (0x3UL << GPIO_MODER_MODER3_Pos)       /*!< 0x000000C0 */
7634 #define GPIO_MODER_MODER3                GPIO_MODER_MODER3_Msk
7635 #define GPIO_MODER_MODER3_0              (0x1UL << GPIO_MODER_MODER3_Pos)       /*!< 0x00000040 */
7636 #define GPIO_MODER_MODER3_1              (0x2UL << GPIO_MODER_MODER3_Pos)       /*!< 0x00000080 */
7637 #define GPIO_MODER_MODER4_Pos            (8U)
7638 #define GPIO_MODER_MODER4_Msk            (0x3UL << GPIO_MODER_MODER4_Pos)       /*!< 0x00000300 */
7639 #define GPIO_MODER_MODER4                GPIO_MODER_MODER4_Msk
7640 #define GPIO_MODER_MODER4_0              (0x1UL << GPIO_MODER_MODER4_Pos)       /*!< 0x00000100 */
7641 #define GPIO_MODER_MODER4_1              (0x2UL << GPIO_MODER_MODER4_Pos)       /*!< 0x00000200 */
7642 #define GPIO_MODER_MODER5_Pos            (10U)
7643 #define GPIO_MODER_MODER5_Msk            (0x3UL << GPIO_MODER_MODER5_Pos)       /*!< 0x00000C00 */
7644 #define GPIO_MODER_MODER5                GPIO_MODER_MODER5_Msk
7645 #define GPIO_MODER_MODER5_0              (0x1UL << GPIO_MODER_MODER5_Pos)       /*!< 0x00000400 */
7646 #define GPIO_MODER_MODER5_1              (0x2UL << GPIO_MODER_MODER5_Pos)       /*!< 0x00000800 */
7647 #define GPIO_MODER_MODER6_Pos            (12U)
7648 #define GPIO_MODER_MODER6_Msk            (0x3UL << GPIO_MODER_MODER6_Pos)       /*!< 0x00003000 */
7649 #define GPIO_MODER_MODER6                GPIO_MODER_MODER6_Msk
7650 #define GPIO_MODER_MODER6_0              (0x1UL << GPIO_MODER_MODER6_Pos)       /*!< 0x00001000 */
7651 #define GPIO_MODER_MODER6_1              (0x2UL << GPIO_MODER_MODER6_Pos)       /*!< 0x00002000 */
7652 #define GPIO_MODER_MODER7_Pos            (14U)
7653 #define GPIO_MODER_MODER7_Msk            (0x3UL << GPIO_MODER_MODER7_Pos)       /*!< 0x0000C000 */
7654 #define GPIO_MODER_MODER7                GPIO_MODER_MODER7_Msk
7655 #define GPIO_MODER_MODER7_0              (0x1UL << GPIO_MODER_MODER7_Pos)       /*!< 0x00004000 */
7656 #define GPIO_MODER_MODER7_1              (0x2UL << GPIO_MODER_MODER7_Pos)       /*!< 0x00008000 */
7657 #define GPIO_MODER_MODER8_Pos            (16U)
7658 #define GPIO_MODER_MODER8_Msk            (0x3UL << GPIO_MODER_MODER8_Pos)       /*!< 0x00030000 */
7659 #define GPIO_MODER_MODER8                GPIO_MODER_MODER8_Msk
7660 #define GPIO_MODER_MODER8_0              (0x1UL << GPIO_MODER_MODER8_Pos)       /*!< 0x00010000 */
7661 #define GPIO_MODER_MODER8_1              (0x2UL << GPIO_MODER_MODER8_Pos)       /*!< 0x00020000 */
7662 #define GPIO_MODER_MODER9_Pos            (18U)
7663 #define GPIO_MODER_MODER9_Msk            (0x3UL << GPIO_MODER_MODER9_Pos)       /*!< 0x000C0000 */
7664 #define GPIO_MODER_MODER9                GPIO_MODER_MODER9_Msk
7665 #define GPIO_MODER_MODER9_0              (0x1UL << GPIO_MODER_MODER9_Pos)       /*!< 0x00040000 */
7666 #define GPIO_MODER_MODER9_1              (0x2UL << GPIO_MODER_MODER9_Pos)       /*!< 0x00080000 */
7667 #define GPIO_MODER_MODER10_Pos           (20U)
7668 #define GPIO_MODER_MODER10_Msk           (0x3UL << GPIO_MODER_MODER10_Pos)      /*!< 0x00300000 */
7669 #define GPIO_MODER_MODER10               GPIO_MODER_MODER10_Msk
7670 #define GPIO_MODER_MODER10_0             (0x1UL << GPIO_MODER_MODER10_Pos)      /*!< 0x00100000 */
7671 #define GPIO_MODER_MODER10_1             (0x2UL << GPIO_MODER_MODER10_Pos)      /*!< 0x00200000 */
7672 #define GPIO_MODER_MODER11_Pos           (22U)
7673 #define GPIO_MODER_MODER11_Msk           (0x3UL << GPIO_MODER_MODER11_Pos)      /*!< 0x00C00000 */
7674 #define GPIO_MODER_MODER11               GPIO_MODER_MODER11_Msk
7675 #define GPIO_MODER_MODER11_0             (0x1UL << GPIO_MODER_MODER11_Pos)      /*!< 0x00400000 */
7676 #define GPIO_MODER_MODER11_1             (0x2UL << GPIO_MODER_MODER11_Pos)      /*!< 0x00800000 */
7677 #define GPIO_MODER_MODER12_Pos           (24U)
7678 #define GPIO_MODER_MODER12_Msk           (0x3UL << GPIO_MODER_MODER12_Pos)      /*!< 0x03000000 */
7679 #define GPIO_MODER_MODER12               GPIO_MODER_MODER12_Msk
7680 #define GPIO_MODER_MODER12_0             (0x1UL << GPIO_MODER_MODER12_Pos)      /*!< 0x01000000 */
7681 #define GPIO_MODER_MODER12_1             (0x2UL << GPIO_MODER_MODER12_Pos)      /*!< 0x02000000 */
7682 #define GPIO_MODER_MODER13_Pos           (26U)
7683 #define GPIO_MODER_MODER13_Msk           (0x3UL << GPIO_MODER_MODER13_Pos)      /*!< 0x0C000000 */
7684 #define GPIO_MODER_MODER13               GPIO_MODER_MODER13_Msk
7685 #define GPIO_MODER_MODER13_0             (0x1UL << GPIO_MODER_MODER13_Pos)      /*!< 0x04000000 */
7686 #define GPIO_MODER_MODER13_1             (0x2UL << GPIO_MODER_MODER13_Pos)      /*!< 0x08000000 */
7687 #define GPIO_MODER_MODER14_Pos           (28U)
7688 #define GPIO_MODER_MODER14_Msk           (0x3UL << GPIO_MODER_MODER14_Pos)      /*!< 0x30000000 */
7689 #define GPIO_MODER_MODER14               GPIO_MODER_MODER14_Msk
7690 #define GPIO_MODER_MODER14_0             (0x1UL << GPIO_MODER_MODER14_Pos)      /*!< 0x10000000 */
7691 #define GPIO_MODER_MODER14_1             (0x2UL << GPIO_MODER_MODER14_Pos)      /*!< 0x20000000 */
7692 #define GPIO_MODER_MODER15_Pos           (30U)
7693 #define GPIO_MODER_MODER15_Msk           (0x3UL << GPIO_MODER_MODER15_Pos)      /*!< 0xC0000000 */
7694 #define GPIO_MODER_MODER15               GPIO_MODER_MODER15_Msk
7695 #define GPIO_MODER_MODER15_0             (0x1UL << GPIO_MODER_MODER15_Pos)      /*!< 0x40000000 */
7696 #define GPIO_MODER_MODER15_1             (0x2UL << GPIO_MODER_MODER15_Pos)      /*!< 0x80000000 */
7697 
7698 
7699 /******************  Bits definition for GPIO_OTYPER register  ****************/
7700 #define GPIO_OTYPER_OT0_Pos              (0U)
7701 #define GPIO_OTYPER_OT0_Msk              (0x1UL << GPIO_OTYPER_OT0_Pos)         /*!< 0x00000001 */
7702 #define GPIO_OTYPER_OT0                  GPIO_OTYPER_OT0_Msk
7703 #define GPIO_OTYPER_OT1_Pos              (1U)
7704 #define GPIO_OTYPER_OT1_Msk              (0x1UL << GPIO_OTYPER_OT1_Pos)         /*!< 0x00000002 */
7705 #define GPIO_OTYPER_OT1                  GPIO_OTYPER_OT1_Msk
7706 #define GPIO_OTYPER_OT2_Pos              (2U)
7707 #define GPIO_OTYPER_OT2_Msk              (0x1UL << GPIO_OTYPER_OT2_Pos)         /*!< 0x00000004 */
7708 #define GPIO_OTYPER_OT2                  GPIO_OTYPER_OT2_Msk
7709 #define GPIO_OTYPER_OT3_Pos              (3U)
7710 #define GPIO_OTYPER_OT3_Msk              (0x1UL << GPIO_OTYPER_OT3_Pos)         /*!< 0x00000008 */
7711 #define GPIO_OTYPER_OT3                  GPIO_OTYPER_OT3_Msk
7712 #define GPIO_OTYPER_OT4_Pos              (4U)
7713 #define GPIO_OTYPER_OT4_Msk              (0x1UL << GPIO_OTYPER_OT4_Pos)         /*!< 0x00000010 */
7714 #define GPIO_OTYPER_OT4                  GPIO_OTYPER_OT4_Msk
7715 #define GPIO_OTYPER_OT5_Pos              (5U)
7716 #define GPIO_OTYPER_OT5_Msk              (0x1UL << GPIO_OTYPER_OT5_Pos)         /*!< 0x00000020 */
7717 #define GPIO_OTYPER_OT5                  GPIO_OTYPER_OT5_Msk
7718 #define GPIO_OTYPER_OT6_Pos              (6U)
7719 #define GPIO_OTYPER_OT6_Msk              (0x1UL << GPIO_OTYPER_OT6_Pos)         /*!< 0x00000040 */
7720 #define GPIO_OTYPER_OT6                  GPIO_OTYPER_OT6_Msk
7721 #define GPIO_OTYPER_OT7_Pos              (7U)
7722 #define GPIO_OTYPER_OT7_Msk              (0x1UL << GPIO_OTYPER_OT7_Pos)         /*!< 0x00000080 */
7723 #define GPIO_OTYPER_OT7                  GPIO_OTYPER_OT7_Msk
7724 #define GPIO_OTYPER_OT8_Pos              (8U)
7725 #define GPIO_OTYPER_OT8_Msk              (0x1UL << GPIO_OTYPER_OT8_Pos)         /*!< 0x00000100 */
7726 #define GPIO_OTYPER_OT8                  GPIO_OTYPER_OT8_Msk
7727 #define GPIO_OTYPER_OT9_Pos              (9U)
7728 #define GPIO_OTYPER_OT9_Msk              (0x1UL << GPIO_OTYPER_OT9_Pos)         /*!< 0x00000200 */
7729 #define GPIO_OTYPER_OT9                  GPIO_OTYPER_OT9_Msk
7730 #define GPIO_OTYPER_OT10_Pos             (10U)
7731 #define GPIO_OTYPER_OT10_Msk             (0x1UL << GPIO_OTYPER_OT10_Pos)        /*!< 0x00000400 */
7732 #define GPIO_OTYPER_OT10                 GPIO_OTYPER_OT10_Msk
7733 #define GPIO_OTYPER_OT11_Pos             (11U)
7734 #define GPIO_OTYPER_OT11_Msk             (0x1UL << GPIO_OTYPER_OT11_Pos)        /*!< 0x00000800 */
7735 #define GPIO_OTYPER_OT11                 GPIO_OTYPER_OT11_Msk
7736 #define GPIO_OTYPER_OT12_Pos             (12U)
7737 #define GPIO_OTYPER_OT12_Msk             (0x1UL << GPIO_OTYPER_OT12_Pos)        /*!< 0x00001000 */
7738 #define GPIO_OTYPER_OT12                 GPIO_OTYPER_OT12_Msk
7739 #define GPIO_OTYPER_OT13_Pos             (13U)
7740 #define GPIO_OTYPER_OT13_Msk             (0x1UL << GPIO_OTYPER_OT13_Pos)        /*!< 0x00002000 */
7741 #define GPIO_OTYPER_OT13                 GPIO_OTYPER_OT13_Msk
7742 #define GPIO_OTYPER_OT14_Pos             (14U)
7743 #define GPIO_OTYPER_OT14_Msk             (0x1UL << GPIO_OTYPER_OT14_Pos)        /*!< 0x00004000 */
7744 #define GPIO_OTYPER_OT14                 GPIO_OTYPER_OT14_Msk
7745 #define GPIO_OTYPER_OT15_Pos             (15U)
7746 #define GPIO_OTYPER_OT15_Msk             (0x1UL << GPIO_OTYPER_OT15_Pos)        /*!< 0x00008000 */
7747 #define GPIO_OTYPER_OT15                 GPIO_OTYPER_OT15_Msk
7748 
7749 /* Legacy defines */
7750 #define GPIO_OTYPER_OT_0                 GPIO_OTYPER_OT0
7751 #define GPIO_OTYPER_OT_1                 GPIO_OTYPER_OT1
7752 #define GPIO_OTYPER_OT_2                 GPIO_OTYPER_OT2
7753 #define GPIO_OTYPER_OT_3                 GPIO_OTYPER_OT3
7754 #define GPIO_OTYPER_OT_4                 GPIO_OTYPER_OT4
7755 #define GPIO_OTYPER_OT_5                 GPIO_OTYPER_OT5
7756 #define GPIO_OTYPER_OT_6                 GPIO_OTYPER_OT6
7757 #define GPIO_OTYPER_OT_7                 GPIO_OTYPER_OT7
7758 #define GPIO_OTYPER_OT_8                 GPIO_OTYPER_OT8
7759 #define GPIO_OTYPER_OT_9                 GPIO_OTYPER_OT9
7760 #define GPIO_OTYPER_OT_10                GPIO_OTYPER_OT10
7761 #define GPIO_OTYPER_OT_11                GPIO_OTYPER_OT11
7762 #define GPIO_OTYPER_OT_12                GPIO_OTYPER_OT12
7763 #define GPIO_OTYPER_OT_13                GPIO_OTYPER_OT13
7764 #define GPIO_OTYPER_OT_14                GPIO_OTYPER_OT14
7765 #define GPIO_OTYPER_OT_15                GPIO_OTYPER_OT15
7766 
7767 /******************  Bits definition for GPIO_OSPEEDR register  ***************/
7768 #define GPIO_OSPEEDR_OSPEED0_Pos         (0U)
7769 #define GPIO_OSPEEDR_OSPEED0_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)    /*!< 0x00000003 */
7770 #define GPIO_OSPEEDR_OSPEED0             GPIO_OSPEEDR_OSPEED0_Msk
7771 #define GPIO_OSPEEDR_OSPEED0_0           (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)    /*!< 0x00000001 */
7772 #define GPIO_OSPEEDR_OSPEED0_1           (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)    /*!< 0x00000002 */
7773 #define GPIO_OSPEEDR_OSPEED1_Pos         (2U)
7774 #define GPIO_OSPEEDR_OSPEED1_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)    /*!< 0x0000000C */
7775 #define GPIO_OSPEEDR_OSPEED1             GPIO_OSPEEDR_OSPEED1_Msk
7776 #define GPIO_OSPEEDR_OSPEED1_0           (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)    /*!< 0x00000004 */
7777 #define GPIO_OSPEEDR_OSPEED1_1           (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)    /*!< 0x00000008 */
7778 #define GPIO_OSPEEDR_OSPEED2_Pos         (4U)
7779 #define GPIO_OSPEEDR_OSPEED2_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)    /*!< 0x00000030 */
7780 #define GPIO_OSPEEDR_OSPEED2             GPIO_OSPEEDR_OSPEED2_Msk
7781 #define GPIO_OSPEEDR_OSPEED2_0           (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)    /*!< 0x00000010 */
7782 #define GPIO_OSPEEDR_OSPEED2_1           (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)    /*!< 0x00000020 */
7783 #define GPIO_OSPEEDR_OSPEED3_Pos         (6U)
7784 #define GPIO_OSPEEDR_OSPEED3_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)    /*!< 0x000000C0 */
7785 #define GPIO_OSPEEDR_OSPEED3             GPIO_OSPEEDR_OSPEED3_Msk
7786 #define GPIO_OSPEEDR_OSPEED3_0           (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)    /*!< 0x00000040 */
7787 #define GPIO_OSPEEDR_OSPEED3_1           (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)    /*!< 0x00000080 */
7788 #define GPIO_OSPEEDR_OSPEED4_Pos         (8U)
7789 #define GPIO_OSPEEDR_OSPEED4_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)    /*!< 0x00000300 */
7790 #define GPIO_OSPEEDR_OSPEED4             GPIO_OSPEEDR_OSPEED4_Msk
7791 #define GPIO_OSPEEDR_OSPEED4_0           (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)    /*!< 0x00000100 */
7792 #define GPIO_OSPEEDR_OSPEED4_1           (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)    /*!< 0x00000200 */
7793 #define GPIO_OSPEEDR_OSPEED5_Pos         (10U)
7794 #define GPIO_OSPEEDR_OSPEED5_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)    /*!< 0x00000C00 */
7795 #define GPIO_OSPEEDR_OSPEED5             GPIO_OSPEEDR_OSPEED5_Msk
7796 #define GPIO_OSPEEDR_OSPEED5_0           (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)    /*!< 0x00000400 */
7797 #define GPIO_OSPEEDR_OSPEED5_1           (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)    /*!< 0x00000800 */
7798 #define GPIO_OSPEEDR_OSPEED6_Pos         (12U)
7799 #define GPIO_OSPEEDR_OSPEED6_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)    /*!< 0x00003000 */
7800 #define GPIO_OSPEEDR_OSPEED6             GPIO_OSPEEDR_OSPEED6_Msk
7801 #define GPIO_OSPEEDR_OSPEED6_0           (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)    /*!< 0x00001000 */
7802 #define GPIO_OSPEEDR_OSPEED6_1           (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)    /*!< 0x00002000 */
7803 #define GPIO_OSPEEDR_OSPEED7_Pos         (14U)
7804 #define GPIO_OSPEEDR_OSPEED7_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)    /*!< 0x0000C000 */
7805 #define GPIO_OSPEEDR_OSPEED7             GPIO_OSPEEDR_OSPEED7_Msk
7806 #define GPIO_OSPEEDR_OSPEED7_0           (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)    /*!< 0x00004000 */
7807 #define GPIO_OSPEEDR_OSPEED7_1           (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)    /*!< 0x00008000 */
7808 #define GPIO_OSPEEDR_OSPEED8_Pos         (16U)
7809 #define GPIO_OSPEEDR_OSPEED8_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)    /*!< 0x00030000 */
7810 #define GPIO_OSPEEDR_OSPEED8             GPIO_OSPEEDR_OSPEED8_Msk
7811 #define GPIO_OSPEEDR_OSPEED8_0           (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)    /*!< 0x00010000 */
7812 #define GPIO_OSPEEDR_OSPEED8_1           (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)    /*!< 0x00020000 */
7813 #define GPIO_OSPEEDR_OSPEED9_Pos         (18U)
7814 #define GPIO_OSPEEDR_OSPEED9_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)    /*!< 0x000C0000 */
7815 #define GPIO_OSPEEDR_OSPEED9             GPIO_OSPEEDR_OSPEED9_Msk
7816 #define GPIO_OSPEEDR_OSPEED9_0           (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)    /*!< 0x00040000 */
7817 #define GPIO_OSPEEDR_OSPEED9_1           (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)    /*!< 0x00080000 */
7818 #define GPIO_OSPEEDR_OSPEED10_Pos        (20U)
7819 #define GPIO_OSPEEDR_OSPEED10_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)   /*!< 0x00300000 */
7820 #define GPIO_OSPEEDR_OSPEED10            GPIO_OSPEEDR_OSPEED10_Msk
7821 #define GPIO_OSPEEDR_OSPEED10_0          (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)   /*!< 0x00100000 */
7822 #define GPIO_OSPEEDR_OSPEED10_1          (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)   /*!< 0x00200000 */
7823 #define GPIO_OSPEEDR_OSPEED11_Pos        (22U)
7824 #define GPIO_OSPEEDR_OSPEED11_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)   /*!< 0x00C00000 */
7825 #define GPIO_OSPEEDR_OSPEED11            GPIO_OSPEEDR_OSPEED11_Msk
7826 #define GPIO_OSPEEDR_OSPEED11_0          (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)   /*!< 0x00400000 */
7827 #define GPIO_OSPEEDR_OSPEED11_1          (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)   /*!< 0x00800000 */
7828 #define GPIO_OSPEEDR_OSPEED12_Pos        (24U)
7829 #define GPIO_OSPEEDR_OSPEED12_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)   /*!< 0x03000000 */
7830 #define GPIO_OSPEEDR_OSPEED12            GPIO_OSPEEDR_OSPEED12_Msk
7831 #define GPIO_OSPEEDR_OSPEED12_0          (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)   /*!< 0x01000000 */
7832 #define GPIO_OSPEEDR_OSPEED12_1          (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)   /*!< 0x02000000 */
7833 #define GPIO_OSPEEDR_OSPEED13_Pos        (26U)
7834 #define GPIO_OSPEEDR_OSPEED13_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)   /*!< 0x0C000000 */
7835 #define GPIO_OSPEEDR_OSPEED13            GPIO_OSPEEDR_OSPEED13_Msk
7836 #define GPIO_OSPEEDR_OSPEED13_0          (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)   /*!< 0x04000000 */
7837 #define GPIO_OSPEEDR_OSPEED13_1          (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)   /*!< 0x08000000 */
7838 #define GPIO_OSPEEDR_OSPEED14_Pos        (28U)
7839 #define GPIO_OSPEEDR_OSPEED14_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)   /*!< 0x30000000 */
7840 #define GPIO_OSPEEDR_OSPEED14            GPIO_OSPEEDR_OSPEED14_Msk
7841 #define GPIO_OSPEEDR_OSPEED14_0          (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)   /*!< 0x10000000 */
7842 #define GPIO_OSPEEDR_OSPEED14_1          (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)   /*!< 0x20000000 */
7843 #define GPIO_OSPEEDR_OSPEED15_Pos        (30U)
7844 #define GPIO_OSPEEDR_OSPEED15_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)   /*!< 0xC0000000 */
7845 #define GPIO_OSPEEDR_OSPEED15            GPIO_OSPEEDR_OSPEED15_Msk
7846 #define GPIO_OSPEEDR_OSPEED15_0          (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)   /*!< 0x40000000 */
7847 #define GPIO_OSPEEDR_OSPEED15_1          (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)   /*!< 0x80000000 */
7848 
7849 /* Legacy defines */
7850 #define GPIO_OSPEEDER_OSPEEDR0           GPIO_OSPEEDR_OSPEED0
7851 #define GPIO_OSPEEDER_OSPEEDR0_0         GPIO_OSPEEDR_OSPEED0_0
7852 #define GPIO_OSPEEDER_OSPEEDR0_1         GPIO_OSPEEDR_OSPEED0_1
7853 #define GPIO_OSPEEDER_OSPEEDR1           GPIO_OSPEEDR_OSPEED1
7854 #define GPIO_OSPEEDER_OSPEEDR1_0         GPIO_OSPEEDR_OSPEED1_0
7855 #define GPIO_OSPEEDER_OSPEEDR1_1         GPIO_OSPEEDR_OSPEED1_1
7856 #define GPIO_OSPEEDER_OSPEEDR2           GPIO_OSPEEDR_OSPEED2
7857 #define GPIO_OSPEEDER_OSPEEDR2_0         GPIO_OSPEEDR_OSPEED2_0
7858 #define GPIO_OSPEEDER_OSPEEDR2_1         GPIO_OSPEEDR_OSPEED2_1
7859 #define GPIO_OSPEEDER_OSPEEDR3           GPIO_OSPEEDR_OSPEED3
7860 #define GPIO_OSPEEDER_OSPEEDR3_0         GPIO_OSPEEDR_OSPEED3_0
7861 #define GPIO_OSPEEDER_OSPEEDR3_1         GPIO_OSPEEDR_OSPEED3_1
7862 #define GPIO_OSPEEDER_OSPEEDR4           GPIO_OSPEEDR_OSPEED4
7863 #define GPIO_OSPEEDER_OSPEEDR4_0         GPIO_OSPEEDR_OSPEED4_0
7864 #define GPIO_OSPEEDER_OSPEEDR4_1         GPIO_OSPEEDR_OSPEED4_1
7865 #define GPIO_OSPEEDER_OSPEEDR5           GPIO_OSPEEDR_OSPEED5
7866 #define GPIO_OSPEEDER_OSPEEDR5_0         GPIO_OSPEEDR_OSPEED5_0
7867 #define GPIO_OSPEEDER_OSPEEDR5_1         GPIO_OSPEEDR_OSPEED5_1
7868 #define GPIO_OSPEEDER_OSPEEDR6           GPIO_OSPEEDR_OSPEED6
7869 #define GPIO_OSPEEDER_OSPEEDR6_0         GPIO_OSPEEDR_OSPEED6_0
7870 #define GPIO_OSPEEDER_OSPEEDR6_1         GPIO_OSPEEDR_OSPEED6_1
7871 #define GPIO_OSPEEDER_OSPEEDR7           GPIO_OSPEEDR_OSPEED7
7872 #define GPIO_OSPEEDER_OSPEEDR7_0         GPIO_OSPEEDR_OSPEED7_0
7873 #define GPIO_OSPEEDER_OSPEEDR7_1         GPIO_OSPEEDR_OSPEED7_1
7874 #define GPIO_OSPEEDER_OSPEEDR8           GPIO_OSPEEDR_OSPEED8
7875 #define GPIO_OSPEEDER_OSPEEDR8_0         GPIO_OSPEEDR_OSPEED8_0
7876 #define GPIO_OSPEEDER_OSPEEDR8_1         GPIO_OSPEEDR_OSPEED8_1
7877 #define GPIO_OSPEEDER_OSPEEDR9           GPIO_OSPEEDR_OSPEED9
7878 #define GPIO_OSPEEDER_OSPEEDR9_0         GPIO_OSPEEDR_OSPEED9_0
7879 #define GPIO_OSPEEDER_OSPEEDR9_1         GPIO_OSPEEDR_OSPEED9_1
7880 #define GPIO_OSPEEDER_OSPEEDR10          GPIO_OSPEEDR_OSPEED10
7881 #define GPIO_OSPEEDER_OSPEEDR10_0        GPIO_OSPEEDR_OSPEED10_0
7882 #define GPIO_OSPEEDER_OSPEEDR10_1        GPIO_OSPEEDR_OSPEED10_1
7883 #define GPIO_OSPEEDER_OSPEEDR11          GPIO_OSPEEDR_OSPEED11
7884 #define GPIO_OSPEEDER_OSPEEDR11_0        GPIO_OSPEEDR_OSPEED11_0
7885 #define GPIO_OSPEEDER_OSPEEDR11_1        GPIO_OSPEEDR_OSPEED11_1
7886 #define GPIO_OSPEEDER_OSPEEDR12          GPIO_OSPEEDR_OSPEED12
7887 #define GPIO_OSPEEDER_OSPEEDR12_0        GPIO_OSPEEDR_OSPEED12_0
7888 #define GPIO_OSPEEDER_OSPEEDR12_1        GPIO_OSPEEDR_OSPEED12_1
7889 #define GPIO_OSPEEDER_OSPEEDR13          GPIO_OSPEEDR_OSPEED13
7890 #define GPIO_OSPEEDER_OSPEEDR13_0        GPIO_OSPEEDR_OSPEED13_0
7891 #define GPIO_OSPEEDER_OSPEEDR13_1        GPIO_OSPEEDR_OSPEED13_1
7892 #define GPIO_OSPEEDER_OSPEEDR14          GPIO_OSPEEDR_OSPEED14
7893 #define GPIO_OSPEEDER_OSPEEDR14_0        GPIO_OSPEEDR_OSPEED14_0
7894 #define GPIO_OSPEEDER_OSPEEDR14_1        GPIO_OSPEEDR_OSPEED14_1
7895 #define GPIO_OSPEEDER_OSPEEDR15          GPIO_OSPEEDR_OSPEED15
7896 #define GPIO_OSPEEDER_OSPEEDR15_0        GPIO_OSPEEDR_OSPEED15_0
7897 #define GPIO_OSPEEDER_OSPEEDR15_1        GPIO_OSPEEDR_OSPEED15_1
7898 
7899 /******************  Bits definition for GPIO_PUPDR register  *****************/
7900 #define GPIO_PUPDR_PUPD0_Pos             (0U)
7901 #define GPIO_PUPDR_PUPD0_Msk             (0x3UL << GPIO_PUPDR_PUPD0_Pos)        /*!< 0x00000003 */
7902 #define GPIO_PUPDR_PUPD0                 GPIO_PUPDR_PUPD0_Msk
7903 #define GPIO_PUPDR_PUPD0_0               (0x1UL << GPIO_PUPDR_PUPD0_Pos)        /*!< 0x00000001 */
7904 #define GPIO_PUPDR_PUPD0_1               (0x2UL << GPIO_PUPDR_PUPD0_Pos)        /*!< 0x00000002 */
7905 #define GPIO_PUPDR_PUPD1_Pos             (2U)
7906 #define GPIO_PUPDR_PUPD1_Msk             (0x3UL << GPIO_PUPDR_PUPD1_Pos)        /*!< 0x0000000C */
7907 #define GPIO_PUPDR_PUPD1                 GPIO_PUPDR_PUPD1_Msk
7908 #define GPIO_PUPDR_PUPD1_0               (0x1UL << GPIO_PUPDR_PUPD1_Pos)        /*!< 0x00000004 */
7909 #define GPIO_PUPDR_PUPD1_1               (0x2UL << GPIO_PUPDR_PUPD1_Pos)        /*!< 0x00000008 */
7910 #define GPIO_PUPDR_PUPD2_Pos             (4U)
7911 #define GPIO_PUPDR_PUPD2_Msk             (0x3UL << GPIO_PUPDR_PUPD2_Pos)        /*!< 0x00000030 */
7912 #define GPIO_PUPDR_PUPD2                 GPIO_PUPDR_PUPD2_Msk
7913 #define GPIO_PUPDR_PUPD2_0               (0x1UL << GPIO_PUPDR_PUPD2_Pos)        /*!< 0x00000010 */
7914 #define GPIO_PUPDR_PUPD2_1               (0x2UL << GPIO_PUPDR_PUPD2_Pos)        /*!< 0x00000020 */
7915 #define GPIO_PUPDR_PUPD3_Pos             (6U)
7916 #define GPIO_PUPDR_PUPD3_Msk             (0x3UL << GPIO_PUPDR_PUPD3_Pos)        /*!< 0x000000C0 */
7917 #define GPIO_PUPDR_PUPD3                 GPIO_PUPDR_PUPD3_Msk
7918 #define GPIO_PUPDR_PUPD3_0               (0x1UL << GPIO_PUPDR_PUPD3_Pos)        /*!< 0x00000040 */
7919 #define GPIO_PUPDR_PUPD3_1               (0x2UL << GPIO_PUPDR_PUPD3_Pos)        /*!< 0x00000080 */
7920 #define GPIO_PUPDR_PUPD4_Pos             (8U)
7921 #define GPIO_PUPDR_PUPD4_Msk             (0x3UL << GPIO_PUPDR_PUPD4_Pos)        /*!< 0x00000300 */
7922 #define GPIO_PUPDR_PUPD4                 GPIO_PUPDR_PUPD4_Msk
7923 #define GPIO_PUPDR_PUPD4_0               (0x1UL << GPIO_PUPDR_PUPD4_Pos)        /*!< 0x00000100 */
7924 #define GPIO_PUPDR_PUPD4_1               (0x2UL << GPIO_PUPDR_PUPD4_Pos)        /*!< 0x00000200 */
7925 #define GPIO_PUPDR_PUPD5_Pos             (10U)
7926 #define GPIO_PUPDR_PUPD5_Msk             (0x3UL << GPIO_PUPDR_PUPD5_Pos)        /*!< 0x00000C00 */
7927 #define GPIO_PUPDR_PUPD5                 GPIO_PUPDR_PUPD5_Msk
7928 #define GPIO_PUPDR_PUPD5_0               (0x1UL << GPIO_PUPDR_PUPD5_Pos)        /*!< 0x00000400 */
7929 #define GPIO_PUPDR_PUPD5_1               (0x2UL << GPIO_PUPDR_PUPD5_Pos)        /*!< 0x00000800 */
7930 #define GPIO_PUPDR_PUPD6_Pos             (12U)
7931 #define GPIO_PUPDR_PUPD6_Msk             (0x3UL << GPIO_PUPDR_PUPD6_Pos)        /*!< 0x00003000 */
7932 #define GPIO_PUPDR_PUPD6                 GPIO_PUPDR_PUPD6_Msk
7933 #define GPIO_PUPDR_PUPD6_0               (0x1UL << GPIO_PUPDR_PUPD6_Pos)        /*!< 0x00001000 */
7934 #define GPIO_PUPDR_PUPD6_1               (0x2UL << GPIO_PUPDR_PUPD6_Pos)        /*!< 0x00002000 */
7935 #define GPIO_PUPDR_PUPD7_Pos             (14U)
7936 #define GPIO_PUPDR_PUPD7_Msk             (0x3UL << GPIO_PUPDR_PUPD7_Pos)        /*!< 0x0000C000 */
7937 #define GPIO_PUPDR_PUPD7                 GPIO_PUPDR_PUPD7_Msk
7938 #define GPIO_PUPDR_PUPD7_0               (0x1UL << GPIO_PUPDR_PUPD7_Pos)        /*!< 0x00004000 */
7939 #define GPIO_PUPDR_PUPD7_1               (0x2UL << GPIO_PUPDR_PUPD7_Pos)        /*!< 0x00008000 */
7940 #define GPIO_PUPDR_PUPD8_Pos             (16U)
7941 #define GPIO_PUPDR_PUPD8_Msk             (0x3UL << GPIO_PUPDR_PUPD8_Pos)        /*!< 0x00030000 */
7942 #define GPIO_PUPDR_PUPD8                 GPIO_PUPDR_PUPD8_Msk
7943 #define GPIO_PUPDR_PUPD8_0               (0x1UL << GPIO_PUPDR_PUPD8_Pos)        /*!< 0x00010000 */
7944 #define GPIO_PUPDR_PUPD8_1               (0x2UL << GPIO_PUPDR_PUPD8_Pos)        /*!< 0x00020000 */
7945 #define GPIO_PUPDR_PUPD9_Pos             (18U)
7946 #define GPIO_PUPDR_PUPD9_Msk             (0x3UL << GPIO_PUPDR_PUPD9_Pos)        /*!< 0x000C0000 */
7947 #define GPIO_PUPDR_PUPD9                 GPIO_PUPDR_PUPD9_Msk
7948 #define GPIO_PUPDR_PUPD9_0               (0x1UL << GPIO_PUPDR_PUPD9_Pos)        /*!< 0x00040000 */
7949 #define GPIO_PUPDR_PUPD9_1               (0x2UL << GPIO_PUPDR_PUPD9_Pos)        /*!< 0x00080000 */
7950 #define GPIO_PUPDR_PUPD10_Pos            (20U)
7951 #define GPIO_PUPDR_PUPD10_Msk            (0x3UL << GPIO_PUPDR_PUPD10_Pos)       /*!< 0x00300000 */
7952 #define GPIO_PUPDR_PUPD10                GPIO_PUPDR_PUPD10_Msk
7953 #define GPIO_PUPDR_PUPD10_0              (0x1UL << GPIO_PUPDR_PUPD10_Pos)       /*!< 0x00100000 */
7954 #define GPIO_PUPDR_PUPD10_1              (0x2UL << GPIO_PUPDR_PUPD10_Pos)       /*!< 0x00200000 */
7955 #define GPIO_PUPDR_PUPD11_Pos            (22U)
7956 #define GPIO_PUPDR_PUPD11_Msk            (0x3UL << GPIO_PUPDR_PUPD11_Pos)       /*!< 0x00C00000 */
7957 #define GPIO_PUPDR_PUPD11                GPIO_PUPDR_PUPD11_Msk
7958 #define GPIO_PUPDR_PUPD11_0              (0x1UL << GPIO_PUPDR_PUPD11_Pos)       /*!< 0x00400000 */
7959 #define GPIO_PUPDR_PUPD11_1              (0x2UL << GPIO_PUPDR_PUPD11_Pos)       /*!< 0x00800000 */
7960 #define GPIO_PUPDR_PUPD12_Pos            (24U)
7961 #define GPIO_PUPDR_PUPD12_Msk            (0x3UL << GPIO_PUPDR_PUPD12_Pos)       /*!< 0x03000000 */
7962 #define GPIO_PUPDR_PUPD12                GPIO_PUPDR_PUPD12_Msk
7963 #define GPIO_PUPDR_PUPD12_0              (0x1UL << GPIO_PUPDR_PUPD12_Pos)       /*!< 0x01000000 */
7964 #define GPIO_PUPDR_PUPD12_1              (0x2UL << GPIO_PUPDR_PUPD12_Pos)       /*!< 0x02000000 */
7965 #define GPIO_PUPDR_PUPD13_Pos            (26U)
7966 #define GPIO_PUPDR_PUPD13_Msk            (0x3UL << GPIO_PUPDR_PUPD13_Pos)       /*!< 0x0C000000 */
7967 #define GPIO_PUPDR_PUPD13                GPIO_PUPDR_PUPD13_Msk
7968 #define GPIO_PUPDR_PUPD13_0              (0x1UL << GPIO_PUPDR_PUPD13_Pos)       /*!< 0x04000000 */
7969 #define GPIO_PUPDR_PUPD13_1              (0x2UL << GPIO_PUPDR_PUPD13_Pos)       /*!< 0x08000000 */
7970 #define GPIO_PUPDR_PUPD14_Pos            (28U)
7971 #define GPIO_PUPDR_PUPD14_Msk            (0x3UL << GPIO_PUPDR_PUPD14_Pos)       /*!< 0x30000000 */
7972 #define GPIO_PUPDR_PUPD14                GPIO_PUPDR_PUPD14_Msk
7973 #define GPIO_PUPDR_PUPD14_0              (0x1UL << GPIO_PUPDR_PUPD14_Pos)       /*!< 0x10000000 */
7974 #define GPIO_PUPDR_PUPD14_1              (0x2UL << GPIO_PUPDR_PUPD14_Pos)       /*!< 0x20000000 */
7975 #define GPIO_PUPDR_PUPD15_Pos            (30U)
7976 #define GPIO_PUPDR_PUPD15_Msk            (0x3UL << GPIO_PUPDR_PUPD15_Pos)       /*!< 0xC0000000 */
7977 #define GPIO_PUPDR_PUPD15                GPIO_PUPDR_PUPD15_Msk
7978 #define GPIO_PUPDR_PUPD15_0              (0x1UL << GPIO_PUPDR_PUPD15_Pos)       /*!< 0x40000000 */
7979 #define GPIO_PUPDR_PUPD15_1              (0x2UL << GPIO_PUPDR_PUPD15_Pos)       /*!< 0x80000000 */
7980 
7981 /* Legacy defines */
7982 #define GPIO_PUPDR_PUPDR0                GPIO_PUPDR_PUPD0
7983 #define GPIO_PUPDR_PUPDR0_0              GPIO_PUPDR_PUPD0_0
7984 #define GPIO_PUPDR_PUPDR0_1              GPIO_PUPDR_PUPD0_1
7985 #define GPIO_PUPDR_PUPDR1                GPIO_PUPDR_PUPD1
7986 #define GPIO_PUPDR_PUPDR1_0              GPIO_PUPDR_PUPD1_0
7987 #define GPIO_PUPDR_PUPDR1_1              GPIO_PUPDR_PUPD1_1
7988 #define GPIO_PUPDR_PUPDR2                GPIO_PUPDR_PUPD2
7989 #define GPIO_PUPDR_PUPDR2_0              GPIO_PUPDR_PUPD2_0
7990 #define GPIO_PUPDR_PUPDR2_1              GPIO_PUPDR_PUPD2_1
7991 #define GPIO_PUPDR_PUPDR3                GPIO_PUPDR_PUPD3
7992 #define GPIO_PUPDR_PUPDR3_0              GPIO_PUPDR_PUPD3_0
7993 #define GPIO_PUPDR_PUPDR3_1              GPIO_PUPDR_PUPD3_1
7994 #define GPIO_PUPDR_PUPDR4                GPIO_PUPDR_PUPD4
7995 #define GPIO_PUPDR_PUPDR4_0              GPIO_PUPDR_PUPD4_0
7996 #define GPIO_PUPDR_PUPDR4_1              GPIO_PUPDR_PUPD4_1
7997 #define GPIO_PUPDR_PUPDR5                GPIO_PUPDR_PUPD5
7998 #define GPIO_PUPDR_PUPDR5_0              GPIO_PUPDR_PUPD5_0
7999 #define GPIO_PUPDR_PUPDR5_1              GPIO_PUPDR_PUPD5_1
8000 #define GPIO_PUPDR_PUPDR6                GPIO_PUPDR_PUPD6
8001 #define GPIO_PUPDR_PUPDR6_0              GPIO_PUPDR_PUPD6_0
8002 #define GPIO_PUPDR_PUPDR6_1              GPIO_PUPDR_PUPD6_1
8003 #define GPIO_PUPDR_PUPDR7                GPIO_PUPDR_PUPD7
8004 #define GPIO_PUPDR_PUPDR7_0              GPIO_PUPDR_PUPD7_0
8005 #define GPIO_PUPDR_PUPDR7_1              GPIO_PUPDR_PUPD7_1
8006 #define GPIO_PUPDR_PUPDR8                GPIO_PUPDR_PUPD8
8007 #define GPIO_PUPDR_PUPDR8_0              GPIO_PUPDR_PUPD8_0
8008 #define GPIO_PUPDR_PUPDR8_1              GPIO_PUPDR_PUPD8_1
8009 #define GPIO_PUPDR_PUPDR9                GPIO_PUPDR_PUPD9
8010 #define GPIO_PUPDR_PUPDR9_0              GPIO_PUPDR_PUPD9_0
8011 #define GPIO_PUPDR_PUPDR9_1              GPIO_PUPDR_PUPD9_1
8012 #define GPIO_PUPDR_PUPDR10               GPIO_PUPDR_PUPD10
8013 #define GPIO_PUPDR_PUPDR10_0             GPIO_PUPDR_PUPD10_0
8014 #define GPIO_PUPDR_PUPDR10_1             GPIO_PUPDR_PUPD10_1
8015 #define GPIO_PUPDR_PUPDR11               GPIO_PUPDR_PUPD11
8016 #define GPIO_PUPDR_PUPDR11_0             GPIO_PUPDR_PUPD11_0
8017 #define GPIO_PUPDR_PUPDR11_1             GPIO_PUPDR_PUPD11_1
8018 #define GPIO_PUPDR_PUPDR12               GPIO_PUPDR_PUPD12
8019 #define GPIO_PUPDR_PUPDR12_0             GPIO_PUPDR_PUPD12_0
8020 #define GPIO_PUPDR_PUPDR12_1             GPIO_PUPDR_PUPD12_1
8021 #define GPIO_PUPDR_PUPDR13               GPIO_PUPDR_PUPD13
8022 #define GPIO_PUPDR_PUPDR13_0             GPIO_PUPDR_PUPD13_0
8023 #define GPIO_PUPDR_PUPDR13_1             GPIO_PUPDR_PUPD13_1
8024 #define GPIO_PUPDR_PUPDR14               GPIO_PUPDR_PUPD14
8025 #define GPIO_PUPDR_PUPDR14_0             GPIO_PUPDR_PUPD14_0
8026 #define GPIO_PUPDR_PUPDR14_1             GPIO_PUPDR_PUPD14_1
8027 #define GPIO_PUPDR_PUPDR15               GPIO_PUPDR_PUPD15
8028 #define GPIO_PUPDR_PUPDR15_0             GPIO_PUPDR_PUPD15_0
8029 #define GPIO_PUPDR_PUPDR15_1             GPIO_PUPDR_PUPD15_1
8030 
8031 /******************  Bits definition for GPIO_IDR register  *******************/
8032 #define GPIO_IDR_ID0_Pos                 (0U)
8033 #define GPIO_IDR_ID0_Msk                 (0x1UL << GPIO_IDR_ID0_Pos)            /*!< 0x00000001 */
8034 #define GPIO_IDR_ID0                     GPIO_IDR_ID0_Msk
8035 #define GPIO_IDR_ID1_Pos                 (1U)
8036 #define GPIO_IDR_ID1_Msk                 (0x1UL << GPIO_IDR_ID1_Pos)            /*!< 0x00000002 */
8037 #define GPIO_IDR_ID1                     GPIO_IDR_ID1_Msk
8038 #define GPIO_IDR_ID2_Pos                 (2U)
8039 #define GPIO_IDR_ID2_Msk                 (0x1UL << GPIO_IDR_ID2_Pos)            /*!< 0x00000004 */
8040 #define GPIO_IDR_ID2                     GPIO_IDR_ID2_Msk
8041 #define GPIO_IDR_ID3_Pos                 (3U)
8042 #define GPIO_IDR_ID3_Msk                 (0x1UL << GPIO_IDR_ID3_Pos)            /*!< 0x00000008 */
8043 #define GPIO_IDR_ID3                     GPIO_IDR_ID3_Msk
8044 #define GPIO_IDR_ID4_Pos                 (4U)
8045 #define GPIO_IDR_ID4_Msk                 (0x1UL << GPIO_IDR_ID4_Pos)            /*!< 0x00000010 */
8046 #define GPIO_IDR_ID4                     GPIO_IDR_ID4_Msk
8047 #define GPIO_IDR_ID5_Pos                 (5U)
8048 #define GPIO_IDR_ID5_Msk                 (0x1UL << GPIO_IDR_ID5_Pos)            /*!< 0x00000020 */
8049 #define GPIO_IDR_ID5                     GPIO_IDR_ID5_Msk
8050 #define GPIO_IDR_ID6_Pos                 (6U)
8051 #define GPIO_IDR_ID6_Msk                 (0x1UL << GPIO_IDR_ID6_Pos)            /*!< 0x00000040 */
8052 #define GPIO_IDR_ID6                     GPIO_IDR_ID6_Msk
8053 #define GPIO_IDR_ID7_Pos                 (7U)
8054 #define GPIO_IDR_ID7_Msk                 (0x1UL << GPIO_IDR_ID7_Pos)            /*!< 0x00000080 */
8055 #define GPIO_IDR_ID7                     GPIO_IDR_ID7_Msk
8056 #define GPIO_IDR_ID8_Pos                 (8U)
8057 #define GPIO_IDR_ID8_Msk                 (0x1UL << GPIO_IDR_ID8_Pos)            /*!< 0x00000100 */
8058 #define GPIO_IDR_ID8                     GPIO_IDR_ID8_Msk
8059 #define GPIO_IDR_ID9_Pos                 (9U)
8060 #define GPIO_IDR_ID9_Msk                 (0x1UL << GPIO_IDR_ID9_Pos)            /*!< 0x00000200 */
8061 #define GPIO_IDR_ID9                     GPIO_IDR_ID9_Msk
8062 #define GPIO_IDR_ID10_Pos                (10U)
8063 #define GPIO_IDR_ID10_Msk                (0x1UL << GPIO_IDR_ID10_Pos)           /*!< 0x00000400 */
8064 #define GPIO_IDR_ID10                    GPIO_IDR_ID10_Msk
8065 #define GPIO_IDR_ID11_Pos                (11U)
8066 #define GPIO_IDR_ID11_Msk                (0x1UL << GPIO_IDR_ID11_Pos)           /*!< 0x00000800 */
8067 #define GPIO_IDR_ID11                    GPIO_IDR_ID11_Msk
8068 #define GPIO_IDR_ID12_Pos                (12U)
8069 #define GPIO_IDR_ID12_Msk                (0x1UL << GPIO_IDR_ID12_Pos)           /*!< 0x00001000 */
8070 #define GPIO_IDR_ID12                    GPIO_IDR_ID12_Msk
8071 #define GPIO_IDR_ID13_Pos                (13U)
8072 #define GPIO_IDR_ID13_Msk                (0x1UL << GPIO_IDR_ID13_Pos)           /*!< 0x00002000 */
8073 #define GPIO_IDR_ID13                    GPIO_IDR_ID13_Msk
8074 #define GPIO_IDR_ID14_Pos                (14U)
8075 #define GPIO_IDR_ID14_Msk                (0x1UL << GPIO_IDR_ID14_Pos)           /*!< 0x00004000 */
8076 #define GPIO_IDR_ID14                    GPIO_IDR_ID14_Msk
8077 #define GPIO_IDR_ID15_Pos                (15U)
8078 #define GPIO_IDR_ID15_Msk                (0x1UL << GPIO_IDR_ID15_Pos)           /*!< 0x00008000 */
8079 #define GPIO_IDR_ID15                    GPIO_IDR_ID15_Msk
8080 
8081 /* Legacy defines */
8082 #define GPIO_IDR_IDR_0                   GPIO_IDR_ID0
8083 #define GPIO_IDR_IDR_1                   GPIO_IDR_ID1
8084 #define GPIO_IDR_IDR_2                   GPIO_IDR_ID2
8085 #define GPIO_IDR_IDR_3                   GPIO_IDR_ID3
8086 #define GPIO_IDR_IDR_4                   GPIO_IDR_ID4
8087 #define GPIO_IDR_IDR_5                   GPIO_IDR_ID5
8088 #define GPIO_IDR_IDR_6                   GPIO_IDR_ID6
8089 #define GPIO_IDR_IDR_7                   GPIO_IDR_ID7
8090 #define GPIO_IDR_IDR_8                   GPIO_IDR_ID8
8091 #define GPIO_IDR_IDR_9                   GPIO_IDR_ID9
8092 #define GPIO_IDR_IDR_10                  GPIO_IDR_ID10
8093 #define GPIO_IDR_IDR_11                  GPIO_IDR_ID11
8094 #define GPIO_IDR_IDR_12                  GPIO_IDR_ID12
8095 #define GPIO_IDR_IDR_13                  GPIO_IDR_ID13
8096 #define GPIO_IDR_IDR_14                  GPIO_IDR_ID14
8097 #define GPIO_IDR_IDR_15                  GPIO_IDR_ID15
8098 
8099 /******************  Bits definition for GPIO_ODR register  *******************/
8100 #define GPIO_ODR_OD0_Pos                 (0U)
8101 #define GPIO_ODR_OD0_Msk                 (0x1UL << GPIO_ODR_OD0_Pos)            /*!< 0x00000001 */
8102 #define GPIO_ODR_OD0                     GPIO_ODR_OD0_Msk
8103 #define GPIO_ODR_OD1_Pos                 (1U)
8104 #define GPIO_ODR_OD1_Msk                 (0x1UL << GPIO_ODR_OD1_Pos)            /*!< 0x00000002 */
8105 #define GPIO_ODR_OD1                     GPIO_ODR_OD1_Msk
8106 #define GPIO_ODR_OD2_Pos                 (2U)
8107 #define GPIO_ODR_OD2_Msk                 (0x1UL << GPIO_ODR_OD2_Pos)            /*!< 0x00000004 */
8108 #define GPIO_ODR_OD2                     GPIO_ODR_OD2_Msk
8109 #define GPIO_ODR_OD3_Pos                 (3U)
8110 #define GPIO_ODR_OD3_Msk                 (0x1UL << GPIO_ODR_OD3_Pos)            /*!< 0x00000008 */
8111 #define GPIO_ODR_OD3                     GPIO_ODR_OD3_Msk
8112 #define GPIO_ODR_OD4_Pos                 (4U)
8113 #define GPIO_ODR_OD4_Msk                 (0x1UL << GPIO_ODR_OD4_Pos)            /*!< 0x00000010 */
8114 #define GPIO_ODR_OD4                     GPIO_ODR_OD4_Msk
8115 #define GPIO_ODR_OD5_Pos                 (5U)
8116 #define GPIO_ODR_OD5_Msk                 (0x1UL << GPIO_ODR_OD5_Pos)            /*!< 0x00000020 */
8117 #define GPIO_ODR_OD5                     GPIO_ODR_OD5_Msk
8118 #define GPIO_ODR_OD6_Pos                 (6U)
8119 #define GPIO_ODR_OD6_Msk                 (0x1UL << GPIO_ODR_OD6_Pos)            /*!< 0x00000040 */
8120 #define GPIO_ODR_OD6                     GPIO_ODR_OD6_Msk
8121 #define GPIO_ODR_OD7_Pos                 (7U)
8122 #define GPIO_ODR_OD7_Msk                 (0x1UL << GPIO_ODR_OD7_Pos)            /*!< 0x00000080 */
8123 #define GPIO_ODR_OD7                     GPIO_ODR_OD7_Msk
8124 #define GPIO_ODR_OD8_Pos                 (8U)
8125 #define GPIO_ODR_OD8_Msk                 (0x1UL << GPIO_ODR_OD8_Pos)            /*!< 0x00000100 */
8126 #define GPIO_ODR_OD8                     GPIO_ODR_OD8_Msk
8127 #define GPIO_ODR_OD9_Pos                 (9U)
8128 #define GPIO_ODR_OD9_Msk                 (0x1UL << GPIO_ODR_OD9_Pos)            /*!< 0x00000200 */
8129 #define GPIO_ODR_OD9                     GPIO_ODR_OD9_Msk
8130 #define GPIO_ODR_OD10_Pos                (10U)
8131 #define GPIO_ODR_OD10_Msk                (0x1UL << GPIO_ODR_OD10_Pos)           /*!< 0x00000400 */
8132 #define GPIO_ODR_OD10                    GPIO_ODR_OD10_Msk
8133 #define GPIO_ODR_OD11_Pos                (11U)
8134 #define GPIO_ODR_OD11_Msk                (0x1UL << GPIO_ODR_OD11_Pos)           /*!< 0x00000800 */
8135 #define GPIO_ODR_OD11                    GPIO_ODR_OD11_Msk
8136 #define GPIO_ODR_OD12_Pos                (12U)
8137 #define GPIO_ODR_OD12_Msk                (0x1UL << GPIO_ODR_OD12_Pos)           /*!< 0x00001000 */
8138 #define GPIO_ODR_OD12                    GPIO_ODR_OD12_Msk
8139 #define GPIO_ODR_OD13_Pos                (13U)
8140 #define GPIO_ODR_OD13_Msk                (0x1UL << GPIO_ODR_OD13_Pos)           /*!< 0x00002000 */
8141 #define GPIO_ODR_OD13                    GPIO_ODR_OD13_Msk
8142 #define GPIO_ODR_OD14_Pos                (14U)
8143 #define GPIO_ODR_OD14_Msk                (0x1UL << GPIO_ODR_OD14_Pos)           /*!< 0x00004000 */
8144 #define GPIO_ODR_OD14                    GPIO_ODR_OD14_Msk
8145 #define GPIO_ODR_OD15_Pos                (15U)
8146 #define GPIO_ODR_OD15_Msk                (0x1UL << GPIO_ODR_OD15_Pos)           /*!< 0x00008000 */
8147 #define GPIO_ODR_OD15                    GPIO_ODR_OD15_Msk
8148 /* Legacy defines */
8149 #define GPIO_ODR_ODR_0                   GPIO_ODR_OD0
8150 #define GPIO_ODR_ODR_1                   GPIO_ODR_OD1
8151 #define GPIO_ODR_ODR_2                   GPIO_ODR_OD2
8152 #define GPIO_ODR_ODR_3                   GPIO_ODR_OD3
8153 #define GPIO_ODR_ODR_4                   GPIO_ODR_OD4
8154 #define GPIO_ODR_ODR_5                   GPIO_ODR_OD5
8155 #define GPIO_ODR_ODR_6                   GPIO_ODR_OD6
8156 #define GPIO_ODR_ODR_7                   GPIO_ODR_OD7
8157 #define GPIO_ODR_ODR_8                   GPIO_ODR_OD8
8158 #define GPIO_ODR_ODR_9                   GPIO_ODR_OD9
8159 #define GPIO_ODR_ODR_10                  GPIO_ODR_OD10
8160 #define GPIO_ODR_ODR_11                  GPIO_ODR_OD11
8161 #define GPIO_ODR_ODR_12                  GPIO_ODR_OD12
8162 #define GPIO_ODR_ODR_13                  GPIO_ODR_OD13
8163 #define GPIO_ODR_ODR_14                  GPIO_ODR_OD14
8164 #define GPIO_ODR_ODR_15                  GPIO_ODR_OD15
8165 
8166 /******************  Bits definition for GPIO_BSRR register  ******************/
8167 #define GPIO_BSRR_BS0_Pos                (0U)
8168 #define GPIO_BSRR_BS0_Msk                (0x1UL << GPIO_BSRR_BS0_Pos)           /*!< 0x00000001 */
8169 #define GPIO_BSRR_BS0                    GPIO_BSRR_BS0_Msk
8170 #define GPIO_BSRR_BS1_Pos                (1U)
8171 #define GPIO_BSRR_BS1_Msk                (0x1UL << GPIO_BSRR_BS1_Pos)           /*!< 0x00000002 */
8172 #define GPIO_BSRR_BS1                    GPIO_BSRR_BS1_Msk
8173 #define GPIO_BSRR_BS2_Pos                (2U)
8174 #define GPIO_BSRR_BS2_Msk                (0x1UL << GPIO_BSRR_BS2_Pos)           /*!< 0x00000004 */
8175 #define GPIO_BSRR_BS2                    GPIO_BSRR_BS2_Msk
8176 #define GPIO_BSRR_BS3_Pos                (3U)
8177 #define GPIO_BSRR_BS3_Msk                (0x1UL << GPIO_BSRR_BS3_Pos)           /*!< 0x00000008 */
8178 #define GPIO_BSRR_BS3                    GPIO_BSRR_BS3_Msk
8179 #define GPIO_BSRR_BS4_Pos                (4U)
8180 #define GPIO_BSRR_BS4_Msk                (0x1UL << GPIO_BSRR_BS4_Pos)           /*!< 0x00000010 */
8181 #define GPIO_BSRR_BS4                    GPIO_BSRR_BS4_Msk
8182 #define GPIO_BSRR_BS5_Pos                (5U)
8183 #define GPIO_BSRR_BS5_Msk                (0x1UL << GPIO_BSRR_BS5_Pos)           /*!< 0x00000020 */
8184 #define GPIO_BSRR_BS5                    GPIO_BSRR_BS5_Msk
8185 #define GPIO_BSRR_BS6_Pos                (6U)
8186 #define GPIO_BSRR_BS6_Msk                (0x1UL << GPIO_BSRR_BS6_Pos)           /*!< 0x00000040 */
8187 #define GPIO_BSRR_BS6                    GPIO_BSRR_BS6_Msk
8188 #define GPIO_BSRR_BS7_Pos                (7U)
8189 #define GPIO_BSRR_BS7_Msk                (0x1UL << GPIO_BSRR_BS7_Pos)           /*!< 0x00000080 */
8190 #define GPIO_BSRR_BS7                    GPIO_BSRR_BS7_Msk
8191 #define GPIO_BSRR_BS8_Pos                (8U)
8192 #define GPIO_BSRR_BS8_Msk                (0x1UL << GPIO_BSRR_BS8_Pos)           /*!< 0x00000100 */
8193 #define GPIO_BSRR_BS8                    GPIO_BSRR_BS8_Msk
8194 #define GPIO_BSRR_BS9_Pos                (9U)
8195 #define GPIO_BSRR_BS9_Msk                (0x1UL << GPIO_BSRR_BS9_Pos)           /*!< 0x00000200 */
8196 #define GPIO_BSRR_BS9                    GPIO_BSRR_BS9_Msk
8197 #define GPIO_BSRR_BS10_Pos               (10U)
8198 #define GPIO_BSRR_BS10_Msk               (0x1UL << GPIO_BSRR_BS10_Pos)          /*!< 0x00000400 */
8199 #define GPIO_BSRR_BS10                   GPIO_BSRR_BS10_Msk
8200 #define GPIO_BSRR_BS11_Pos               (11U)
8201 #define GPIO_BSRR_BS11_Msk               (0x1UL << GPIO_BSRR_BS11_Pos)          /*!< 0x00000800 */
8202 #define GPIO_BSRR_BS11                   GPIO_BSRR_BS11_Msk
8203 #define GPIO_BSRR_BS12_Pos               (12U)
8204 #define GPIO_BSRR_BS12_Msk               (0x1UL << GPIO_BSRR_BS12_Pos)          /*!< 0x00001000 */
8205 #define GPIO_BSRR_BS12                   GPIO_BSRR_BS12_Msk
8206 #define GPIO_BSRR_BS13_Pos               (13U)
8207 #define GPIO_BSRR_BS13_Msk               (0x1UL << GPIO_BSRR_BS13_Pos)          /*!< 0x00002000 */
8208 #define GPIO_BSRR_BS13                   GPIO_BSRR_BS13_Msk
8209 #define GPIO_BSRR_BS14_Pos               (14U)
8210 #define GPIO_BSRR_BS14_Msk               (0x1UL << GPIO_BSRR_BS14_Pos)          /*!< 0x00004000 */
8211 #define GPIO_BSRR_BS14                   GPIO_BSRR_BS14_Msk
8212 #define GPIO_BSRR_BS15_Pos               (15U)
8213 #define GPIO_BSRR_BS15_Msk               (0x1UL << GPIO_BSRR_BS15_Pos)          /*!< 0x00008000 */
8214 #define GPIO_BSRR_BS15                   GPIO_BSRR_BS15_Msk
8215 #define GPIO_BSRR_BR0_Pos                (16U)
8216 #define GPIO_BSRR_BR0_Msk                (0x1UL << GPIO_BSRR_BR0_Pos)           /*!< 0x00010000 */
8217 #define GPIO_BSRR_BR0                    GPIO_BSRR_BR0_Msk
8218 #define GPIO_BSRR_BR1_Pos                (17U)
8219 #define GPIO_BSRR_BR1_Msk                (0x1UL << GPIO_BSRR_BR1_Pos)           /*!< 0x00020000 */
8220 #define GPIO_BSRR_BR1                    GPIO_BSRR_BR1_Msk
8221 #define GPIO_BSRR_BR2_Pos                (18U)
8222 #define GPIO_BSRR_BR2_Msk                (0x1UL << GPIO_BSRR_BR2_Pos)           /*!< 0x00040000 */
8223 #define GPIO_BSRR_BR2                    GPIO_BSRR_BR2_Msk
8224 #define GPIO_BSRR_BR3_Pos                (19U)
8225 #define GPIO_BSRR_BR3_Msk                (0x1UL << GPIO_BSRR_BR3_Pos)           /*!< 0x00080000 */
8226 #define GPIO_BSRR_BR3                    GPIO_BSRR_BR3_Msk
8227 #define GPIO_BSRR_BR4_Pos                (20U)
8228 #define GPIO_BSRR_BR4_Msk                (0x1UL << GPIO_BSRR_BR4_Pos)           /*!< 0x00100000 */
8229 #define GPIO_BSRR_BR4                    GPIO_BSRR_BR4_Msk
8230 #define GPIO_BSRR_BR5_Pos                (21U)
8231 #define GPIO_BSRR_BR5_Msk                (0x1UL << GPIO_BSRR_BR5_Pos)           /*!< 0x00200000 */
8232 #define GPIO_BSRR_BR5                    GPIO_BSRR_BR5_Msk
8233 #define GPIO_BSRR_BR6_Pos                (22U)
8234 #define GPIO_BSRR_BR6_Msk                (0x1UL << GPIO_BSRR_BR6_Pos)           /*!< 0x00400000 */
8235 #define GPIO_BSRR_BR6                    GPIO_BSRR_BR6_Msk
8236 #define GPIO_BSRR_BR7_Pos                (23U)
8237 #define GPIO_BSRR_BR7_Msk                (0x1UL << GPIO_BSRR_BR7_Pos)           /*!< 0x00800000 */
8238 #define GPIO_BSRR_BR7                    GPIO_BSRR_BR7_Msk
8239 #define GPIO_BSRR_BR8_Pos                (24U)
8240 #define GPIO_BSRR_BR8_Msk                (0x1UL << GPIO_BSRR_BR8_Pos)           /*!< 0x01000000 */
8241 #define GPIO_BSRR_BR8                    GPIO_BSRR_BR8_Msk
8242 #define GPIO_BSRR_BR9_Pos                (25U)
8243 #define GPIO_BSRR_BR9_Msk                (0x1UL << GPIO_BSRR_BR9_Pos)           /*!< 0x02000000 */
8244 #define GPIO_BSRR_BR9                    GPIO_BSRR_BR9_Msk
8245 #define GPIO_BSRR_BR10_Pos               (26U)
8246 #define GPIO_BSRR_BR10_Msk               (0x1UL << GPIO_BSRR_BR10_Pos)          /*!< 0x04000000 */
8247 #define GPIO_BSRR_BR10                   GPIO_BSRR_BR10_Msk
8248 #define GPIO_BSRR_BR11_Pos               (27U)
8249 #define GPIO_BSRR_BR11_Msk               (0x1UL << GPIO_BSRR_BR11_Pos)          /*!< 0x08000000 */
8250 #define GPIO_BSRR_BR11                   GPIO_BSRR_BR11_Msk
8251 #define GPIO_BSRR_BR12_Pos               (28U)
8252 #define GPIO_BSRR_BR12_Msk               (0x1UL << GPIO_BSRR_BR12_Pos)          /*!< 0x10000000 */
8253 #define GPIO_BSRR_BR12                   GPIO_BSRR_BR12_Msk
8254 #define GPIO_BSRR_BR13_Pos               (29U)
8255 #define GPIO_BSRR_BR13_Msk               (0x1UL << GPIO_BSRR_BR13_Pos)          /*!< 0x20000000 */
8256 #define GPIO_BSRR_BR13                   GPIO_BSRR_BR13_Msk
8257 #define GPIO_BSRR_BR14_Pos               (30U)
8258 #define GPIO_BSRR_BR14_Msk               (0x1UL << GPIO_BSRR_BR14_Pos)          /*!< 0x40000000 */
8259 #define GPIO_BSRR_BR14                   GPIO_BSRR_BR14_Msk
8260 #define GPIO_BSRR_BR15_Pos               (31U)
8261 #define GPIO_BSRR_BR15_Msk               (0x1UL << GPIO_BSRR_BR15_Pos)          /*!< 0x80000000 */
8262 #define GPIO_BSRR_BR15                   GPIO_BSRR_BR15_Msk
8263 
8264 /* Legacy defines */
8265 #define GPIO_BSRR_BS_0                   GPIO_BSRR_BS0
8266 #define GPIO_BSRR_BS_1                   GPIO_BSRR_BS1
8267 #define GPIO_BSRR_BS_2                   GPIO_BSRR_BS2
8268 #define GPIO_BSRR_BS_3                   GPIO_BSRR_BS3
8269 #define GPIO_BSRR_BS_4                   GPIO_BSRR_BS4
8270 #define GPIO_BSRR_BS_5                   GPIO_BSRR_BS5
8271 #define GPIO_BSRR_BS_6                   GPIO_BSRR_BS6
8272 #define GPIO_BSRR_BS_7                   GPIO_BSRR_BS7
8273 #define GPIO_BSRR_BS_8                   GPIO_BSRR_BS8
8274 #define GPIO_BSRR_BS_9                   GPIO_BSRR_BS9
8275 #define GPIO_BSRR_BS_10                  GPIO_BSRR_BS10
8276 #define GPIO_BSRR_BS_11                  GPIO_BSRR_BS11
8277 #define GPIO_BSRR_BS_12                  GPIO_BSRR_BS12
8278 #define GPIO_BSRR_BS_13                  GPIO_BSRR_BS13
8279 #define GPIO_BSRR_BS_14                  GPIO_BSRR_BS14
8280 #define GPIO_BSRR_BS_15                  GPIO_BSRR_BS15
8281 #define GPIO_BSRR_BR_0                   GPIO_BSRR_BR0
8282 #define GPIO_BSRR_BR_1                   GPIO_BSRR_BR1
8283 #define GPIO_BSRR_BR_2                   GPIO_BSRR_BR2
8284 #define GPIO_BSRR_BR_3                   GPIO_BSRR_BR3
8285 #define GPIO_BSRR_BR_4                   GPIO_BSRR_BR4
8286 #define GPIO_BSRR_BR_5                   GPIO_BSRR_BR5
8287 #define GPIO_BSRR_BR_6                   GPIO_BSRR_BR6
8288 #define GPIO_BSRR_BR_7                   GPIO_BSRR_BR7
8289 #define GPIO_BSRR_BR_8                   GPIO_BSRR_BR8
8290 #define GPIO_BSRR_BR_9                   GPIO_BSRR_BR9
8291 #define GPIO_BSRR_BR_10                  GPIO_BSRR_BR10
8292 #define GPIO_BSRR_BR_11                  GPIO_BSRR_BR11
8293 #define GPIO_BSRR_BR_12                  GPIO_BSRR_BR12
8294 #define GPIO_BSRR_BR_13                  GPIO_BSRR_BR13
8295 #define GPIO_BSRR_BR_14                  GPIO_BSRR_BR14
8296 #define GPIO_BSRR_BR_15                  GPIO_BSRR_BR15
8297 #define GPIO_BRR_BR0                     GPIO_BSRR_BR0
8298 #define GPIO_BRR_BR0_Pos                 GPIO_BSRR_BR0_Pos
8299 #define GPIO_BRR_BR0_Msk                 GPIO_BSRR_BR0_Msk
8300 #define GPIO_BRR_BR1                     GPIO_BSRR_BR1
8301 #define GPIO_BRR_BR1_Pos                 GPIO_BSRR_BR1_Pos
8302 #define GPIO_BRR_BR1_Msk                 GPIO_BSRR_BR1_Msk
8303 #define GPIO_BRR_BR2                     GPIO_BSRR_BR2
8304 #define GPIO_BRR_BR2_Pos                 GPIO_BSRR_BR2_Pos
8305 #define GPIO_BRR_BR2_Msk                 GPIO_BSRR_BR2_Msk
8306 #define GPIO_BRR_BR3                     GPIO_BSRR_BR3
8307 #define GPIO_BRR_BR3_Pos                 GPIO_BSRR_BR3_Pos
8308 #define GPIO_BRR_BR3_Msk                 GPIO_BSRR_BR3_Msk
8309 #define GPIO_BRR_BR4                     GPIO_BSRR_BR4
8310 #define GPIO_BRR_BR4_Pos                 GPIO_BSRR_BR4_Pos
8311 #define GPIO_BRR_BR4_Msk                 GPIO_BSRR_BR4_Msk
8312 #define GPIO_BRR_BR5                     GPIO_BSRR_BR5
8313 #define GPIO_BRR_BR5_Pos                 GPIO_BSRR_BR5_Pos
8314 #define GPIO_BRR_BR5_Msk                 GPIO_BSRR_BR5_Msk
8315 #define GPIO_BRR_BR6                     GPIO_BSRR_BR6
8316 #define GPIO_BRR_BR6_Pos                 GPIO_BSRR_BR6_Pos
8317 #define GPIO_BRR_BR6_Msk                 GPIO_BSRR_BR6_Msk
8318 #define GPIO_BRR_BR7                     GPIO_BSRR_BR7
8319 #define GPIO_BRR_BR7_Pos                 GPIO_BSRR_BR7_Pos
8320 #define GPIO_BRR_BR7_Msk                 GPIO_BSRR_BR7_Msk
8321 #define GPIO_BRR_BR8                     GPIO_BSRR_BR8
8322 #define GPIO_BRR_BR8_Pos                 GPIO_BSRR_BR8_Pos
8323 #define GPIO_BRR_BR8_Msk                 GPIO_BSRR_BR8_Msk
8324 #define GPIO_BRR_BR9                     GPIO_BSRR_BR9
8325 #define GPIO_BRR_BR9_Pos                 GPIO_BSRR_BR9_Pos
8326 #define GPIO_BRR_BR9_Msk                 GPIO_BSRR_BR9_Msk
8327 #define GPIO_BRR_BR10                    GPIO_BSRR_BR10
8328 #define GPIO_BRR_BR10_Pos                GPIO_BSRR_BR10_Pos
8329 #define GPIO_BRR_BR10_Msk                GPIO_BSRR_BR10_Msk
8330 #define GPIO_BRR_BR11                    GPIO_BSRR_BR11
8331 #define GPIO_BRR_BR11_Pos                GPIO_BSRR_BR11_Pos
8332 #define GPIO_BRR_BR11_Msk                GPIO_BSRR_BR11_Msk
8333 #define GPIO_BRR_BR12                    GPIO_BSRR_BR12
8334 #define GPIO_BRR_BR12_Pos                GPIO_BSRR_BR12_Pos
8335 #define GPIO_BRR_BR12_Msk                GPIO_BSRR_BR12_Msk
8336 #define GPIO_BRR_BR13                    GPIO_BSRR_BR13
8337 #define GPIO_BRR_BR13_Pos                GPIO_BSRR_BR13_Pos
8338 #define GPIO_BRR_BR13_Msk                GPIO_BSRR_BR13_Msk
8339 #define GPIO_BRR_BR14                    GPIO_BSRR_BR14
8340 #define GPIO_BRR_BR14_Pos                GPIO_BSRR_BR14_Pos
8341 #define GPIO_BRR_BR14_Msk                GPIO_BSRR_BR14_Msk
8342 #define GPIO_BRR_BR15                    GPIO_BSRR_BR15
8343 #define GPIO_BRR_BR15_Pos                GPIO_BSRR_BR15_Pos
8344 #define GPIO_BRR_BR15_Msk                GPIO_BSRR_BR15_Msk
8345 /****************** Bit definition for GPIO_LCKR register *********************/
8346 #define GPIO_LCKR_LCK0_Pos               (0U)
8347 #define GPIO_LCKR_LCK0_Msk               (0x1UL << GPIO_LCKR_LCK0_Pos)          /*!< 0x00000001 */
8348 #define GPIO_LCKR_LCK0                   GPIO_LCKR_LCK0_Msk
8349 #define GPIO_LCKR_LCK1_Pos               (1U)
8350 #define GPIO_LCKR_LCK1_Msk               (0x1UL << GPIO_LCKR_LCK1_Pos)          /*!< 0x00000002 */
8351 #define GPIO_LCKR_LCK1                   GPIO_LCKR_LCK1_Msk
8352 #define GPIO_LCKR_LCK2_Pos               (2U)
8353 #define GPIO_LCKR_LCK2_Msk               (0x1UL << GPIO_LCKR_LCK2_Pos)          /*!< 0x00000004 */
8354 #define GPIO_LCKR_LCK2                   GPIO_LCKR_LCK2_Msk
8355 #define GPIO_LCKR_LCK3_Pos               (3U)
8356 #define GPIO_LCKR_LCK3_Msk               (0x1UL << GPIO_LCKR_LCK3_Pos)          /*!< 0x00000008 */
8357 #define GPIO_LCKR_LCK3                   GPIO_LCKR_LCK3_Msk
8358 #define GPIO_LCKR_LCK4_Pos               (4U)
8359 #define GPIO_LCKR_LCK4_Msk               (0x1UL << GPIO_LCKR_LCK4_Pos)          /*!< 0x00000010 */
8360 #define GPIO_LCKR_LCK4                   GPIO_LCKR_LCK4_Msk
8361 #define GPIO_LCKR_LCK5_Pos               (5U)
8362 #define GPIO_LCKR_LCK5_Msk               (0x1UL << GPIO_LCKR_LCK5_Pos)          /*!< 0x00000020 */
8363 #define GPIO_LCKR_LCK5                   GPIO_LCKR_LCK5_Msk
8364 #define GPIO_LCKR_LCK6_Pos               (6U)
8365 #define GPIO_LCKR_LCK6_Msk               (0x1UL << GPIO_LCKR_LCK6_Pos)          /*!< 0x00000040 */
8366 #define GPIO_LCKR_LCK6                   GPIO_LCKR_LCK6_Msk
8367 #define GPIO_LCKR_LCK7_Pos               (7U)
8368 #define GPIO_LCKR_LCK7_Msk               (0x1UL << GPIO_LCKR_LCK7_Pos)          /*!< 0x00000080 */
8369 #define GPIO_LCKR_LCK7                   GPIO_LCKR_LCK7_Msk
8370 #define GPIO_LCKR_LCK8_Pos               (8U)
8371 #define GPIO_LCKR_LCK8_Msk               (0x1UL << GPIO_LCKR_LCK8_Pos)          /*!< 0x00000100 */
8372 #define GPIO_LCKR_LCK8                   GPIO_LCKR_LCK8_Msk
8373 #define GPIO_LCKR_LCK9_Pos               (9U)
8374 #define GPIO_LCKR_LCK9_Msk               (0x1UL << GPIO_LCKR_LCK9_Pos)          /*!< 0x00000200 */
8375 #define GPIO_LCKR_LCK9                   GPIO_LCKR_LCK9_Msk
8376 #define GPIO_LCKR_LCK10_Pos              (10U)
8377 #define GPIO_LCKR_LCK10_Msk              (0x1UL << GPIO_LCKR_LCK10_Pos)         /*!< 0x00000400 */
8378 #define GPIO_LCKR_LCK10                  GPIO_LCKR_LCK10_Msk
8379 #define GPIO_LCKR_LCK11_Pos              (11U)
8380 #define GPIO_LCKR_LCK11_Msk              (0x1UL << GPIO_LCKR_LCK11_Pos)         /*!< 0x00000800 */
8381 #define GPIO_LCKR_LCK11                  GPIO_LCKR_LCK11_Msk
8382 #define GPIO_LCKR_LCK12_Pos              (12U)
8383 #define GPIO_LCKR_LCK12_Msk              (0x1UL << GPIO_LCKR_LCK12_Pos)         /*!< 0x00001000 */
8384 #define GPIO_LCKR_LCK12                  GPIO_LCKR_LCK12_Msk
8385 #define GPIO_LCKR_LCK13_Pos              (13U)
8386 #define GPIO_LCKR_LCK13_Msk              (0x1UL << GPIO_LCKR_LCK13_Pos)         /*!< 0x00002000 */
8387 #define GPIO_LCKR_LCK13                  GPIO_LCKR_LCK13_Msk
8388 #define GPIO_LCKR_LCK14_Pos              (14U)
8389 #define GPIO_LCKR_LCK14_Msk              (0x1UL << GPIO_LCKR_LCK14_Pos)         /*!< 0x00004000 */
8390 #define GPIO_LCKR_LCK14                  GPIO_LCKR_LCK14_Msk
8391 #define GPIO_LCKR_LCK15_Pos              (15U)
8392 #define GPIO_LCKR_LCK15_Msk              (0x1UL << GPIO_LCKR_LCK15_Pos)         /*!< 0x00008000 */
8393 #define GPIO_LCKR_LCK15                  GPIO_LCKR_LCK15_Msk
8394 #define GPIO_LCKR_LCKK_Pos               (16U)
8395 #define GPIO_LCKR_LCKK_Msk               (0x1UL << GPIO_LCKR_LCKK_Pos)          /*!< 0x00010000 */
8396 #define GPIO_LCKR_LCKK                   GPIO_LCKR_LCKK_Msk
8397 /****************** Bit definition for GPIO_AFRL register *********************/
8398 #define GPIO_AFRL_AFSEL0_Pos             (0U)
8399 #define GPIO_AFRL_AFSEL0_Msk             (0xFUL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x0000000F */
8400 #define GPIO_AFRL_AFSEL0                 GPIO_AFRL_AFSEL0_Msk
8401 #define GPIO_AFRL_AFSEL0_0               (0x1UL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000001 */
8402 #define GPIO_AFRL_AFSEL0_1               (0x2UL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000002 */
8403 #define GPIO_AFRL_AFSEL0_2               (0x4UL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000004 */
8404 #define GPIO_AFRL_AFSEL0_3               (0x8UL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000008 */
8405 #define GPIO_AFRL_AFSEL1_Pos             (4U)
8406 #define GPIO_AFRL_AFSEL1_Msk             (0xFUL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x000000F0 */
8407 #define GPIO_AFRL_AFSEL1                 GPIO_AFRL_AFSEL1_Msk
8408 #define GPIO_AFRL_AFSEL1_0               (0x1UL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000010 */
8409 #define GPIO_AFRL_AFSEL1_1               (0x2UL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000020 */
8410 #define GPIO_AFRL_AFSEL1_2               (0x4UL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000040 */
8411 #define GPIO_AFRL_AFSEL1_3               (0x8UL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000080 */
8412 #define GPIO_AFRL_AFSEL2_Pos             (8U)
8413 #define GPIO_AFRL_AFSEL2_Msk             (0xFUL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000F00 */
8414 #define GPIO_AFRL_AFSEL2                 GPIO_AFRL_AFSEL2_Msk
8415 #define GPIO_AFRL_AFSEL2_0               (0x1UL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000100 */
8416 #define GPIO_AFRL_AFSEL2_1               (0x2UL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000200 */
8417 #define GPIO_AFRL_AFSEL2_2               (0x4UL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000400 */
8418 #define GPIO_AFRL_AFSEL2_3               (0x8UL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000800 */
8419 #define GPIO_AFRL_AFSEL3_Pos             (12U)
8420 #define GPIO_AFRL_AFSEL3_Msk             (0xFUL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x0000F000 */
8421 #define GPIO_AFRL_AFSEL3                 GPIO_AFRL_AFSEL3_Msk
8422 #define GPIO_AFRL_AFSEL3_0               (0x1UL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00001000 */
8423 #define GPIO_AFRL_AFSEL3_1               (0x2UL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00002000 */
8424 #define GPIO_AFRL_AFSEL3_2               (0x4UL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00004000 */
8425 #define GPIO_AFRL_AFSEL3_3               (0x8UL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00008000 */
8426 #define GPIO_AFRL_AFSEL4_Pos             (16U)
8427 #define GPIO_AFRL_AFSEL4_Msk             (0xFUL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x000F0000 */
8428 #define GPIO_AFRL_AFSEL4                 GPIO_AFRL_AFSEL4_Msk
8429 #define GPIO_AFRL_AFSEL4_0               (0x1UL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00010000 */
8430 #define GPIO_AFRL_AFSEL4_1               (0x2UL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00020000 */
8431 #define GPIO_AFRL_AFSEL4_2               (0x4UL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00040000 */
8432 #define GPIO_AFRL_AFSEL4_3               (0x8UL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00080000 */
8433 #define GPIO_AFRL_AFSEL5_Pos             (20U)
8434 #define GPIO_AFRL_AFSEL5_Msk             (0xFUL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00F00000 */
8435 #define GPIO_AFRL_AFSEL5                 GPIO_AFRL_AFSEL5_Msk
8436 #define GPIO_AFRL_AFSEL5_0               (0x1UL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00100000 */
8437 #define GPIO_AFRL_AFSEL5_1               (0x2UL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00200000 */
8438 #define GPIO_AFRL_AFSEL5_2               (0x4UL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00400000 */
8439 #define GPIO_AFRL_AFSEL5_3               (0x8UL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00800000 */
8440 #define GPIO_AFRL_AFSEL6_Pos             (24U)
8441 #define GPIO_AFRL_AFSEL6_Msk             (0xFUL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x0F000000 */
8442 #define GPIO_AFRL_AFSEL6                 GPIO_AFRL_AFSEL6_Msk
8443 #define GPIO_AFRL_AFSEL6_0               (0x1UL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x01000000 */
8444 #define GPIO_AFRL_AFSEL6_1               (0x2UL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x02000000 */
8445 #define GPIO_AFRL_AFSEL6_2               (0x4UL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x04000000 */
8446 #define GPIO_AFRL_AFSEL6_3               (0x8UL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x08000000 */
8447 #define GPIO_AFRL_AFSEL7_Pos             (28U)
8448 #define GPIO_AFRL_AFSEL7_Msk             (0xFUL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0xF0000000 */
8449 #define GPIO_AFRL_AFSEL7                 GPIO_AFRL_AFSEL7_Msk
8450 #define GPIO_AFRL_AFSEL7_0               (0x1UL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x10000000 */
8451 #define GPIO_AFRL_AFSEL7_1               (0x2UL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x20000000 */
8452 #define GPIO_AFRL_AFSEL7_2               (0x4UL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x40000000 */
8453 #define GPIO_AFRL_AFSEL7_3               (0x8UL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x80000000 */
8454 
8455 /* Legacy defines */
8456 #define GPIO_AFRL_AFRL0                  GPIO_AFRL_AFSEL0
8457 #define GPIO_AFRL_AFRL0_0                GPIO_AFRL_AFSEL0_0
8458 #define GPIO_AFRL_AFRL0_1                GPIO_AFRL_AFSEL0_1
8459 #define GPIO_AFRL_AFRL0_2                GPIO_AFRL_AFSEL0_2
8460 #define GPIO_AFRL_AFRL0_3                GPIO_AFRL_AFSEL0_3
8461 #define GPIO_AFRL_AFRL1                  GPIO_AFRL_AFSEL1
8462 #define GPIO_AFRL_AFRL1_0                GPIO_AFRL_AFSEL1_0
8463 #define GPIO_AFRL_AFRL1_1                GPIO_AFRL_AFSEL1_1
8464 #define GPIO_AFRL_AFRL1_2                GPIO_AFRL_AFSEL1_2
8465 #define GPIO_AFRL_AFRL1_3                GPIO_AFRL_AFSEL1_3
8466 #define GPIO_AFRL_AFRL2                  GPIO_AFRL_AFSEL2
8467 #define GPIO_AFRL_AFRL2_0                GPIO_AFRL_AFSEL2_0
8468 #define GPIO_AFRL_AFRL2_1                GPIO_AFRL_AFSEL2_1
8469 #define GPIO_AFRL_AFRL2_2                GPIO_AFRL_AFSEL2_2
8470 #define GPIO_AFRL_AFRL2_3                GPIO_AFRL_AFSEL2_3
8471 #define GPIO_AFRL_AFRL3                  GPIO_AFRL_AFSEL3
8472 #define GPIO_AFRL_AFRL3_0                GPIO_AFRL_AFSEL3_0
8473 #define GPIO_AFRL_AFRL3_1                GPIO_AFRL_AFSEL3_1
8474 #define GPIO_AFRL_AFRL3_2                GPIO_AFRL_AFSEL3_2
8475 #define GPIO_AFRL_AFRL3_3                GPIO_AFRL_AFSEL3_3
8476 #define GPIO_AFRL_AFRL4                  GPIO_AFRL_AFSEL4
8477 #define GPIO_AFRL_AFRL4_0                GPIO_AFRL_AFSEL4_0
8478 #define GPIO_AFRL_AFRL4_1                GPIO_AFRL_AFSEL4_1
8479 #define GPIO_AFRL_AFRL4_2                GPIO_AFRL_AFSEL4_2
8480 #define GPIO_AFRL_AFRL4_3                GPIO_AFRL_AFSEL4_3
8481 #define GPIO_AFRL_AFRL5                  GPIO_AFRL_AFSEL5
8482 #define GPIO_AFRL_AFRL5_0                GPIO_AFRL_AFSEL5_0
8483 #define GPIO_AFRL_AFRL5_1                GPIO_AFRL_AFSEL5_1
8484 #define GPIO_AFRL_AFRL5_2                GPIO_AFRL_AFSEL5_2
8485 #define GPIO_AFRL_AFRL5_3                GPIO_AFRL_AFSEL5_3
8486 #define GPIO_AFRL_AFRL6                  GPIO_AFRL_AFSEL6
8487 #define GPIO_AFRL_AFRL6_0                GPIO_AFRL_AFSEL6_0
8488 #define GPIO_AFRL_AFRL6_1                GPIO_AFRL_AFSEL6_1
8489 #define GPIO_AFRL_AFRL6_2                GPIO_AFRL_AFSEL6_2
8490 #define GPIO_AFRL_AFRL6_3                GPIO_AFRL_AFSEL6_3
8491 #define GPIO_AFRL_AFRL7                  GPIO_AFRL_AFSEL7
8492 #define GPIO_AFRL_AFRL7_0                GPIO_AFRL_AFSEL7_0
8493 #define GPIO_AFRL_AFRL7_1                GPIO_AFRL_AFSEL7_1
8494 #define GPIO_AFRL_AFRL7_2                GPIO_AFRL_AFSEL7_2
8495 #define GPIO_AFRL_AFRL7_3                GPIO_AFRL_AFSEL7_3
8496 
8497 /****************** Bit definition for GPIO_AFRH register *********************/
8498 #define GPIO_AFRH_AFSEL8_Pos             (0U)
8499 #define GPIO_AFRH_AFSEL8_Msk             (0xFUL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x0000000F */
8500 #define GPIO_AFRH_AFSEL8                 GPIO_AFRH_AFSEL8_Msk
8501 #define GPIO_AFRH_AFSEL8_0               (0x1UL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000001 */
8502 #define GPIO_AFRH_AFSEL8_1               (0x2UL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000002 */
8503 #define GPIO_AFRH_AFSEL8_2               (0x4UL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000004 */
8504 #define GPIO_AFRH_AFSEL8_3               (0x8UL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000008 */
8505 #define GPIO_AFRH_AFSEL9_Pos             (4U)
8506 #define GPIO_AFRH_AFSEL9_Msk             (0xFUL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x000000F0 */
8507 #define GPIO_AFRH_AFSEL9                 GPIO_AFRH_AFSEL9_Msk
8508 #define GPIO_AFRH_AFSEL9_0               (0x1UL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000010 */
8509 #define GPIO_AFRH_AFSEL9_1               (0x2UL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000020 */
8510 #define GPIO_AFRH_AFSEL9_2               (0x4UL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000040 */
8511 #define GPIO_AFRH_AFSEL9_3               (0x8UL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000080 */
8512 #define GPIO_AFRH_AFSEL10_Pos            (8U)
8513 #define GPIO_AFRH_AFSEL10_Msk            (0xFUL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000F00 */
8514 #define GPIO_AFRH_AFSEL10                GPIO_AFRH_AFSEL10_Msk
8515 #define GPIO_AFRH_AFSEL10_0              (0x1UL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000100 */
8516 #define GPIO_AFRH_AFSEL10_1              (0x2UL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000200 */
8517 #define GPIO_AFRH_AFSEL10_2              (0x4UL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000400 */
8518 #define GPIO_AFRH_AFSEL10_3              (0x8UL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000800 */
8519 #define GPIO_AFRH_AFSEL11_Pos            (12U)
8520 #define GPIO_AFRH_AFSEL11_Msk            (0xFUL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x0000F000 */
8521 #define GPIO_AFRH_AFSEL11                GPIO_AFRH_AFSEL11_Msk
8522 #define GPIO_AFRH_AFSEL11_0              (0x1UL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00001000 */
8523 #define GPIO_AFRH_AFSEL11_1              (0x2UL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00002000 */
8524 #define GPIO_AFRH_AFSEL11_2              (0x4UL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00004000 */
8525 #define GPIO_AFRH_AFSEL11_3              (0x8UL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00008000 */
8526 #define GPIO_AFRH_AFSEL12_Pos            (16U)
8527 #define GPIO_AFRH_AFSEL12_Msk            (0xFUL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x000F0000 */
8528 #define GPIO_AFRH_AFSEL12                GPIO_AFRH_AFSEL12_Msk
8529 #define GPIO_AFRH_AFSEL12_0              (0x1UL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00010000 */
8530 #define GPIO_AFRH_AFSEL12_1              (0x2UL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00020000 */
8531 #define GPIO_AFRH_AFSEL12_2              (0x4UL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00040000 */
8532 #define GPIO_AFRH_AFSEL12_3              (0x8UL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00080000 */
8533 #define GPIO_AFRH_AFSEL13_Pos            (20U)
8534 #define GPIO_AFRH_AFSEL13_Msk            (0xFUL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00F00000 */
8535 #define GPIO_AFRH_AFSEL13                GPIO_AFRH_AFSEL13_Msk
8536 #define GPIO_AFRH_AFSEL13_0              (0x1UL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00100000 */
8537 #define GPIO_AFRH_AFSEL13_1              (0x2UL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00200000 */
8538 #define GPIO_AFRH_AFSEL13_2              (0x4UL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00400000 */
8539 #define GPIO_AFRH_AFSEL13_3              (0x8UL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00800000 */
8540 #define GPIO_AFRH_AFSEL14_Pos            (24U)
8541 #define GPIO_AFRH_AFSEL14_Msk            (0xFUL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x0F000000 */
8542 #define GPIO_AFRH_AFSEL14                GPIO_AFRH_AFSEL14_Msk
8543 #define GPIO_AFRH_AFSEL14_0              (0x1UL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x01000000 */
8544 #define GPIO_AFRH_AFSEL14_1              (0x2UL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x02000000 */
8545 #define GPIO_AFRH_AFSEL14_2              (0x4UL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x04000000 */
8546 #define GPIO_AFRH_AFSEL14_3              (0x8UL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x08000000 */
8547 #define GPIO_AFRH_AFSEL15_Pos            (28U)
8548 #define GPIO_AFRH_AFSEL15_Msk            (0xFUL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0xF0000000 */
8549 #define GPIO_AFRH_AFSEL15                GPIO_AFRH_AFSEL15_Msk
8550 #define GPIO_AFRH_AFSEL15_0              (0x1UL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x10000000 */
8551 #define GPIO_AFRH_AFSEL15_1              (0x2UL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x20000000 */
8552 #define GPIO_AFRH_AFSEL15_2              (0x4UL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x40000000 */
8553 #define GPIO_AFRH_AFSEL15_3              (0x8UL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x80000000 */
8554 
8555 /* Legacy defines */
8556 #define GPIO_AFRH_AFRH0                  GPIO_AFRH_AFSEL8
8557 #define GPIO_AFRH_AFRH0_0                GPIO_AFRH_AFSEL8_0
8558 #define GPIO_AFRH_AFRH0_1                GPIO_AFRH_AFSEL8_1
8559 #define GPIO_AFRH_AFRH0_2                GPIO_AFRH_AFSEL8_2
8560 #define GPIO_AFRH_AFRH0_3                GPIO_AFRH_AFSEL8_3
8561 #define GPIO_AFRH_AFRH1                  GPIO_AFRH_AFSEL9
8562 #define GPIO_AFRH_AFRH1_0                GPIO_AFRH_AFSEL9_0
8563 #define GPIO_AFRH_AFRH1_1                GPIO_AFRH_AFSEL9_1
8564 #define GPIO_AFRH_AFRH1_2                GPIO_AFRH_AFSEL9_2
8565 #define GPIO_AFRH_AFRH1_3                GPIO_AFRH_AFSEL9_3
8566 #define GPIO_AFRH_AFRH2                  GPIO_AFRH_AFSEL10
8567 #define GPIO_AFRH_AFRH2_0                GPIO_AFRH_AFSEL10_0
8568 #define GPIO_AFRH_AFRH2_1                GPIO_AFRH_AFSEL10_1
8569 #define GPIO_AFRH_AFRH2_2                GPIO_AFRH_AFSEL10_2
8570 #define GPIO_AFRH_AFRH2_3                GPIO_AFRH_AFSEL10_3
8571 #define GPIO_AFRH_AFRH3                  GPIO_AFRH_AFSEL11
8572 #define GPIO_AFRH_AFRH3_0                GPIO_AFRH_AFSEL11_0
8573 #define GPIO_AFRH_AFRH3_1                GPIO_AFRH_AFSEL11_1
8574 #define GPIO_AFRH_AFRH3_2                GPIO_AFRH_AFSEL11_2
8575 #define GPIO_AFRH_AFRH3_3                GPIO_AFRH_AFSEL11_3
8576 #define GPIO_AFRH_AFRH4                  GPIO_AFRH_AFSEL12
8577 #define GPIO_AFRH_AFRH4_0                GPIO_AFRH_AFSEL12_0
8578 #define GPIO_AFRH_AFRH4_1                GPIO_AFRH_AFSEL12_1
8579 #define GPIO_AFRH_AFRH4_2                GPIO_AFRH_AFSEL12_2
8580 #define GPIO_AFRH_AFRH4_3                GPIO_AFRH_AFSEL12_3
8581 #define GPIO_AFRH_AFRH5                  GPIO_AFRH_AFSEL13
8582 #define GPIO_AFRH_AFRH5_0                GPIO_AFRH_AFSEL13_0
8583 #define GPIO_AFRH_AFRH5_1                GPIO_AFRH_AFSEL13_1
8584 #define GPIO_AFRH_AFRH5_2                GPIO_AFRH_AFSEL13_2
8585 #define GPIO_AFRH_AFRH5_3                GPIO_AFRH_AFSEL13_3
8586 #define GPIO_AFRH_AFRH6                  GPIO_AFRH_AFSEL14
8587 #define GPIO_AFRH_AFRH6_0                GPIO_AFRH_AFSEL14_0
8588 #define GPIO_AFRH_AFRH6_1                GPIO_AFRH_AFSEL14_1
8589 #define GPIO_AFRH_AFRH6_2                GPIO_AFRH_AFSEL14_2
8590 #define GPIO_AFRH_AFRH6_3                GPIO_AFRH_AFSEL14_3
8591 #define GPIO_AFRH_AFRH7                  GPIO_AFRH_AFSEL15
8592 #define GPIO_AFRH_AFRH7_0                GPIO_AFRH_AFSEL15_0
8593 #define GPIO_AFRH_AFRH7_1                GPIO_AFRH_AFSEL15_1
8594 #define GPIO_AFRH_AFRH7_2                GPIO_AFRH_AFSEL15_2
8595 #define GPIO_AFRH_AFRH7_3                GPIO_AFRH_AFSEL15_3
8596 
8597 
8598 /******************************************************************************/
8599 /*                                                                            */
8600 /*                      Inter-integrated Circuit Interface                    */
8601 /*                                                                            */
8602 /******************************************************************************/
8603 /*******************  Bit definition for I2C_CR1 register  ********************/
8604 #define I2C_CR1_PE_Pos            (0U)
8605 #define I2C_CR1_PE_Msk            (0x1UL << I2C_CR1_PE_Pos)                     /*!< 0x00000001 */
8606 #define I2C_CR1_PE                I2C_CR1_PE_Msk                               /*!<Peripheral Enable                             */
8607 #define I2C_CR1_SMBUS_Pos         (1U)
8608 #define I2C_CR1_SMBUS_Msk         (0x1UL << I2C_CR1_SMBUS_Pos)                  /*!< 0x00000002 */
8609 #define I2C_CR1_SMBUS             I2C_CR1_SMBUS_Msk                            /*!<SMBus Mode                                    */
8610 #define I2C_CR1_SMBTYPE_Pos       (3U)
8611 #define I2C_CR1_SMBTYPE_Msk       (0x1UL << I2C_CR1_SMBTYPE_Pos)                /*!< 0x00000008 */
8612 #define I2C_CR1_SMBTYPE           I2C_CR1_SMBTYPE_Msk                          /*!<SMBus Type                                    */
8613 #define I2C_CR1_ENARP_Pos         (4U)
8614 #define I2C_CR1_ENARP_Msk         (0x1UL << I2C_CR1_ENARP_Pos)                  /*!< 0x00000010 */
8615 #define I2C_CR1_ENARP             I2C_CR1_ENARP_Msk                            /*!<ARP Enable                                    */
8616 #define I2C_CR1_ENPEC_Pos         (5U)
8617 #define I2C_CR1_ENPEC_Msk         (0x1UL << I2C_CR1_ENPEC_Pos)                  /*!< 0x00000020 */
8618 #define I2C_CR1_ENPEC             I2C_CR1_ENPEC_Msk                            /*!<PEC Enable                                    */
8619 #define I2C_CR1_ENGC_Pos          (6U)
8620 #define I2C_CR1_ENGC_Msk          (0x1UL << I2C_CR1_ENGC_Pos)                   /*!< 0x00000040 */
8621 #define I2C_CR1_ENGC              I2C_CR1_ENGC_Msk                             /*!<General Call Enable                           */
8622 #define I2C_CR1_NOSTRETCH_Pos     (7U)
8623 #define I2C_CR1_NOSTRETCH_Msk     (0x1UL << I2C_CR1_NOSTRETCH_Pos)              /*!< 0x00000080 */
8624 #define I2C_CR1_NOSTRETCH         I2C_CR1_NOSTRETCH_Msk                        /*!<Clock Stretching Disable (Slave mode)         */
8625 #define I2C_CR1_START_Pos         (8U)
8626 #define I2C_CR1_START_Msk         (0x1UL << I2C_CR1_START_Pos)                  /*!< 0x00000100 */
8627 #define I2C_CR1_START             I2C_CR1_START_Msk                            /*!<Start Generation                              */
8628 #define I2C_CR1_STOP_Pos          (9U)
8629 #define I2C_CR1_STOP_Msk          (0x1UL << I2C_CR1_STOP_Pos)                   /*!< 0x00000200 */
8630 #define I2C_CR1_STOP              I2C_CR1_STOP_Msk                             /*!<Stop Generation                               */
8631 #define I2C_CR1_ACK_Pos           (10U)
8632 #define I2C_CR1_ACK_Msk           (0x1UL << I2C_CR1_ACK_Pos)                    /*!< 0x00000400 */
8633 #define I2C_CR1_ACK               I2C_CR1_ACK_Msk                              /*!<Acknowledge Enable                            */
8634 #define I2C_CR1_POS_Pos           (11U)
8635 #define I2C_CR1_POS_Msk           (0x1UL << I2C_CR1_POS_Pos)                    /*!< 0x00000800 */
8636 #define I2C_CR1_POS               I2C_CR1_POS_Msk                              /*!<Acknowledge/PEC Position (for data reception) */
8637 #define I2C_CR1_PEC_Pos           (12U)
8638 #define I2C_CR1_PEC_Msk           (0x1UL << I2C_CR1_PEC_Pos)                    /*!< 0x00001000 */
8639 #define I2C_CR1_PEC               I2C_CR1_PEC_Msk                              /*!<Packet Error Checking                         */
8640 #define I2C_CR1_ALERT_Pos         (13U)
8641 #define I2C_CR1_ALERT_Msk         (0x1UL << I2C_CR1_ALERT_Pos)                  /*!< 0x00002000 */
8642 #define I2C_CR1_ALERT             I2C_CR1_ALERT_Msk                            /*!<SMBus Alert                                   */
8643 #define I2C_CR1_SWRST_Pos         (15U)
8644 #define I2C_CR1_SWRST_Msk         (0x1UL << I2C_CR1_SWRST_Pos)                  /*!< 0x00008000 */
8645 #define I2C_CR1_SWRST             I2C_CR1_SWRST_Msk                            /*!<Software Reset                                */
8646 
8647 /*******************  Bit definition for I2C_CR2 register  ********************/
8648 #define I2C_CR2_FREQ_Pos          (0U)
8649 #define I2C_CR2_FREQ_Msk          (0x3FUL << I2C_CR2_FREQ_Pos)                  /*!< 0x0000003F */
8650 #define I2C_CR2_FREQ              I2C_CR2_FREQ_Msk                             /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */
8651 #define I2C_CR2_FREQ_0            (0x01UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000001 */
8652 #define I2C_CR2_FREQ_1            (0x02UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000002 */
8653 #define I2C_CR2_FREQ_2            (0x04UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000004 */
8654 #define I2C_CR2_FREQ_3            (0x08UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000008 */
8655 #define I2C_CR2_FREQ_4            (0x10UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000010 */
8656 #define I2C_CR2_FREQ_5            (0x20UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000020 */
8657 
8658 #define I2C_CR2_ITERREN_Pos       (8U)
8659 #define I2C_CR2_ITERREN_Msk       (0x1UL << I2C_CR2_ITERREN_Pos)                /*!< 0x00000100 */
8660 #define I2C_CR2_ITERREN           I2C_CR2_ITERREN_Msk                          /*!<Error Interrupt Enable  */
8661 #define I2C_CR2_ITEVTEN_Pos       (9U)
8662 #define I2C_CR2_ITEVTEN_Msk       (0x1UL << I2C_CR2_ITEVTEN_Pos)                /*!< 0x00000200 */
8663 #define I2C_CR2_ITEVTEN           I2C_CR2_ITEVTEN_Msk                          /*!<Event Interrupt Enable  */
8664 #define I2C_CR2_ITBUFEN_Pos       (10U)
8665 #define I2C_CR2_ITBUFEN_Msk       (0x1UL << I2C_CR2_ITBUFEN_Pos)                /*!< 0x00000400 */
8666 #define I2C_CR2_ITBUFEN           I2C_CR2_ITBUFEN_Msk                          /*!<Buffer Interrupt Enable */
8667 #define I2C_CR2_DMAEN_Pos         (11U)
8668 #define I2C_CR2_DMAEN_Msk         (0x1UL << I2C_CR2_DMAEN_Pos)                  /*!< 0x00000800 */
8669 #define I2C_CR2_DMAEN             I2C_CR2_DMAEN_Msk                            /*!<DMA Requests Enable     */
8670 #define I2C_CR2_LAST_Pos          (12U)
8671 #define I2C_CR2_LAST_Msk          (0x1UL << I2C_CR2_LAST_Pos)                   /*!< 0x00001000 */
8672 #define I2C_CR2_LAST              I2C_CR2_LAST_Msk                             /*!<DMA Last Transfer       */
8673 
8674 /*******************  Bit definition for I2C_OAR1 register  *******************/
8675 #define I2C_OAR1_ADD1_7           0x000000FEU                                  /*!<Interface Address */
8676 #define I2C_OAR1_ADD8_9           0x00000300U                                  /*!<Interface Address */
8677 
8678 #define I2C_OAR1_ADD0_Pos         (0U)
8679 #define I2C_OAR1_ADD0_Msk         (0x1UL << I2C_OAR1_ADD0_Pos)                  /*!< 0x00000001 */
8680 #define I2C_OAR1_ADD0             I2C_OAR1_ADD0_Msk                            /*!<Bit 0 */
8681 #define I2C_OAR1_ADD1_Pos         (1U)
8682 #define I2C_OAR1_ADD1_Msk         (0x1UL << I2C_OAR1_ADD1_Pos)                  /*!< 0x00000002 */
8683 #define I2C_OAR1_ADD1             I2C_OAR1_ADD1_Msk                            /*!<Bit 1 */
8684 #define I2C_OAR1_ADD2_Pos         (2U)
8685 #define I2C_OAR1_ADD2_Msk         (0x1UL << I2C_OAR1_ADD2_Pos)                  /*!< 0x00000004 */
8686 #define I2C_OAR1_ADD2             I2C_OAR1_ADD2_Msk                            /*!<Bit 2 */
8687 #define I2C_OAR1_ADD3_Pos         (3U)
8688 #define I2C_OAR1_ADD3_Msk         (0x1UL << I2C_OAR1_ADD3_Pos)                  /*!< 0x00000008 */
8689 #define I2C_OAR1_ADD3             I2C_OAR1_ADD3_Msk                            /*!<Bit 3 */
8690 #define I2C_OAR1_ADD4_Pos         (4U)
8691 #define I2C_OAR1_ADD4_Msk         (0x1UL << I2C_OAR1_ADD4_Pos)                  /*!< 0x00000010 */
8692 #define I2C_OAR1_ADD4             I2C_OAR1_ADD4_Msk                            /*!<Bit 4 */
8693 #define I2C_OAR1_ADD5_Pos         (5U)
8694 #define I2C_OAR1_ADD5_Msk         (0x1UL << I2C_OAR1_ADD5_Pos)                  /*!< 0x00000020 */
8695 #define I2C_OAR1_ADD5             I2C_OAR1_ADD5_Msk                            /*!<Bit 5 */
8696 #define I2C_OAR1_ADD6_Pos         (6U)
8697 #define I2C_OAR1_ADD6_Msk         (0x1UL << I2C_OAR1_ADD6_Pos)                  /*!< 0x00000040 */
8698 #define I2C_OAR1_ADD6             I2C_OAR1_ADD6_Msk                            /*!<Bit 6 */
8699 #define I2C_OAR1_ADD7_Pos         (7U)
8700 #define I2C_OAR1_ADD7_Msk         (0x1UL << I2C_OAR1_ADD7_Pos)                  /*!< 0x00000080 */
8701 #define I2C_OAR1_ADD7             I2C_OAR1_ADD7_Msk                            /*!<Bit 7 */
8702 #define I2C_OAR1_ADD8_Pos         (8U)
8703 #define I2C_OAR1_ADD8_Msk         (0x1UL << I2C_OAR1_ADD8_Pos)                  /*!< 0x00000100 */
8704 #define I2C_OAR1_ADD8             I2C_OAR1_ADD8_Msk                            /*!<Bit 8 */
8705 #define I2C_OAR1_ADD9_Pos         (9U)
8706 #define I2C_OAR1_ADD9_Msk         (0x1UL << I2C_OAR1_ADD9_Pos)                  /*!< 0x00000200 */
8707 #define I2C_OAR1_ADD9             I2C_OAR1_ADD9_Msk                            /*!<Bit 9 */
8708 
8709 #define I2C_OAR1_ADDMODE_Pos      (15U)
8710 #define I2C_OAR1_ADDMODE_Msk      (0x1UL << I2C_OAR1_ADDMODE_Pos)               /*!< 0x00008000 */
8711 #define I2C_OAR1_ADDMODE          I2C_OAR1_ADDMODE_Msk                         /*!<Addressing Mode (Slave mode) */
8712 
8713 /*******************  Bit definition for I2C_OAR2 register  *******************/
8714 #define I2C_OAR2_ENDUAL_Pos       (0U)
8715 #define I2C_OAR2_ENDUAL_Msk       (0x1UL << I2C_OAR2_ENDUAL_Pos)                /*!< 0x00000001 */
8716 #define I2C_OAR2_ENDUAL           I2C_OAR2_ENDUAL_Msk                          /*!<Dual addressing mode enable */
8717 #define I2C_OAR2_ADD2_Pos         (1U)
8718 #define I2C_OAR2_ADD2_Msk         (0x7FUL << I2C_OAR2_ADD2_Pos)                 /*!< 0x000000FE */
8719 #define I2C_OAR2_ADD2             I2C_OAR2_ADD2_Msk                            /*!<Interface address           */
8720 
8721 /********************  Bit definition for I2C_DR register  ********************/
8722 #define I2C_DR_DR_Pos             (0U)
8723 #define I2C_DR_DR_Msk             (0xFFUL << I2C_DR_DR_Pos)                     /*!< 0x000000FF */
8724 #define I2C_DR_DR                 I2C_DR_DR_Msk                                /*!<8-bit Data Register         */
8725 
8726 /*******************  Bit definition for I2C_SR1 register  ********************/
8727 #define I2C_SR1_SB_Pos            (0U)
8728 #define I2C_SR1_SB_Msk            (0x1UL << I2C_SR1_SB_Pos)                     /*!< 0x00000001 */
8729 #define I2C_SR1_SB                I2C_SR1_SB_Msk                               /*!<Start Bit (Master mode)                         */
8730 #define I2C_SR1_ADDR_Pos          (1U)
8731 #define I2C_SR1_ADDR_Msk          (0x1UL << I2C_SR1_ADDR_Pos)                   /*!< 0x00000002 */
8732 #define I2C_SR1_ADDR              I2C_SR1_ADDR_Msk                             /*!<Address sent (master mode)/matched (slave mode) */
8733 #define I2C_SR1_BTF_Pos           (2U)
8734 #define I2C_SR1_BTF_Msk           (0x1UL << I2C_SR1_BTF_Pos)                    /*!< 0x00000004 */
8735 #define I2C_SR1_BTF               I2C_SR1_BTF_Msk                              /*!<Byte Transfer Finished                          */
8736 #define I2C_SR1_ADD10_Pos         (3U)
8737 #define I2C_SR1_ADD10_Msk         (0x1UL << I2C_SR1_ADD10_Pos)                  /*!< 0x00000008 */
8738 #define I2C_SR1_ADD10             I2C_SR1_ADD10_Msk                            /*!<10-bit header sent (Master mode)                */
8739 #define I2C_SR1_STOPF_Pos         (4U)
8740 #define I2C_SR1_STOPF_Msk         (0x1UL << I2C_SR1_STOPF_Pos)                  /*!< 0x00000010 */
8741 #define I2C_SR1_STOPF             I2C_SR1_STOPF_Msk                            /*!<Stop detection (Slave mode)                     */
8742 #define I2C_SR1_RXNE_Pos          (6U)
8743 #define I2C_SR1_RXNE_Msk          (0x1UL << I2C_SR1_RXNE_Pos)                   /*!< 0x00000040 */
8744 #define I2C_SR1_RXNE              I2C_SR1_RXNE_Msk                             /*!<Data Register not Empty (receivers)             */
8745 #define I2C_SR1_TXE_Pos           (7U)
8746 #define I2C_SR1_TXE_Msk           (0x1UL << I2C_SR1_TXE_Pos)                    /*!< 0x00000080 */
8747 #define I2C_SR1_TXE               I2C_SR1_TXE_Msk                              /*!<Data Register Empty (transmitters)              */
8748 #define I2C_SR1_BERR_Pos          (8U)
8749 #define I2C_SR1_BERR_Msk          (0x1UL << I2C_SR1_BERR_Pos)                   /*!< 0x00000100 */
8750 #define I2C_SR1_BERR              I2C_SR1_BERR_Msk                             /*!<Bus Error                                       */
8751 #define I2C_SR1_ARLO_Pos          (9U)
8752 #define I2C_SR1_ARLO_Msk          (0x1UL << I2C_SR1_ARLO_Pos)                   /*!< 0x00000200 */
8753 #define I2C_SR1_ARLO              I2C_SR1_ARLO_Msk                             /*!<Arbitration Lost (master mode)                  */
8754 #define I2C_SR1_AF_Pos            (10U)
8755 #define I2C_SR1_AF_Msk            (0x1UL << I2C_SR1_AF_Pos)                     /*!< 0x00000400 */
8756 #define I2C_SR1_AF                I2C_SR1_AF_Msk                               /*!<Acknowledge Failure                             */
8757 #define I2C_SR1_OVR_Pos           (11U)
8758 #define I2C_SR1_OVR_Msk           (0x1UL << I2C_SR1_OVR_Pos)                    /*!< 0x00000800 */
8759 #define I2C_SR1_OVR               I2C_SR1_OVR_Msk                              /*!<Overrun/Underrun                                */
8760 #define I2C_SR1_PECERR_Pos        (12U)
8761 #define I2C_SR1_PECERR_Msk        (0x1UL << I2C_SR1_PECERR_Pos)                 /*!< 0x00001000 */
8762 #define I2C_SR1_PECERR            I2C_SR1_PECERR_Msk                           /*!<PEC Error in reception                          */
8763 #define I2C_SR1_TIMEOUT_Pos       (14U)
8764 #define I2C_SR1_TIMEOUT_Msk       (0x1UL << I2C_SR1_TIMEOUT_Pos)                /*!< 0x00004000 */
8765 #define I2C_SR1_TIMEOUT           I2C_SR1_TIMEOUT_Msk                          /*!<Timeout or Tlow Error                           */
8766 #define I2C_SR1_SMBALERT_Pos      (15U)
8767 #define I2C_SR1_SMBALERT_Msk      (0x1UL << I2C_SR1_SMBALERT_Pos)               /*!< 0x00008000 */
8768 #define I2C_SR1_SMBALERT          I2C_SR1_SMBALERT_Msk                         /*!<SMBus Alert                                     */
8769 
8770 /*******************  Bit definition for I2C_SR2 register  ********************/
8771 #define I2C_SR2_MSL_Pos           (0U)
8772 #define I2C_SR2_MSL_Msk           (0x1UL << I2C_SR2_MSL_Pos)                    /*!< 0x00000001 */
8773 #define I2C_SR2_MSL               I2C_SR2_MSL_Msk                              /*!<Master/Slave                                    */
8774 #define I2C_SR2_BUSY_Pos          (1U)
8775 #define I2C_SR2_BUSY_Msk          (0x1UL << I2C_SR2_BUSY_Pos)                   /*!< 0x00000002 */
8776 #define I2C_SR2_BUSY              I2C_SR2_BUSY_Msk                             /*!<Bus Busy                                        */
8777 #define I2C_SR2_TRA_Pos           (2U)
8778 #define I2C_SR2_TRA_Msk           (0x1UL << I2C_SR2_TRA_Pos)                    /*!< 0x00000004 */
8779 #define I2C_SR2_TRA               I2C_SR2_TRA_Msk                              /*!<Transmitter/Receiver                            */
8780 #define I2C_SR2_GENCALL_Pos       (4U)
8781 #define I2C_SR2_GENCALL_Msk       (0x1UL << I2C_SR2_GENCALL_Pos)                /*!< 0x00000010 */
8782 #define I2C_SR2_GENCALL           I2C_SR2_GENCALL_Msk                          /*!<General Call Address (Slave mode)               */
8783 #define I2C_SR2_SMBDEFAULT_Pos    (5U)
8784 #define I2C_SR2_SMBDEFAULT_Msk    (0x1UL << I2C_SR2_SMBDEFAULT_Pos)             /*!< 0x00000020 */
8785 #define I2C_SR2_SMBDEFAULT        I2C_SR2_SMBDEFAULT_Msk                       /*!<SMBus Device Default Address (Slave mode)       */
8786 #define I2C_SR2_SMBHOST_Pos       (6U)
8787 #define I2C_SR2_SMBHOST_Msk       (0x1UL << I2C_SR2_SMBHOST_Pos)                /*!< 0x00000040 */
8788 #define I2C_SR2_SMBHOST           I2C_SR2_SMBHOST_Msk                          /*!<SMBus Host Header (Slave mode)                  */
8789 #define I2C_SR2_DUALF_Pos         (7U)
8790 #define I2C_SR2_DUALF_Msk         (0x1UL << I2C_SR2_DUALF_Pos)                  /*!< 0x00000080 */
8791 #define I2C_SR2_DUALF             I2C_SR2_DUALF_Msk                            /*!<Dual Flag (Slave mode)                          */
8792 #define I2C_SR2_PEC_Pos           (8U)
8793 #define I2C_SR2_PEC_Msk           (0xFFUL << I2C_SR2_PEC_Pos)                   /*!< 0x0000FF00 */
8794 #define I2C_SR2_PEC               I2C_SR2_PEC_Msk                              /*!<Packet Error Checking Register                  */
8795 
8796 /*******************  Bit definition for I2C_CCR register  ********************/
8797 #define I2C_CCR_CCR_Pos           (0U)
8798 #define I2C_CCR_CCR_Msk           (0xFFFUL << I2C_CCR_CCR_Pos)                  /*!< 0x00000FFF */
8799 #define I2C_CCR_CCR               I2C_CCR_CCR_Msk                              /*!<Clock Control Register in Fast/Standard mode (Master mode) */
8800 #define I2C_CCR_DUTY_Pos          (14U)
8801 #define I2C_CCR_DUTY_Msk          (0x1UL << I2C_CCR_DUTY_Pos)                   /*!< 0x00004000 */
8802 #define I2C_CCR_DUTY              I2C_CCR_DUTY_Msk                             /*!<Fast Mode Duty Cycle                                       */
8803 #define I2C_CCR_FS_Pos            (15U)
8804 #define I2C_CCR_FS_Msk            (0x1UL << I2C_CCR_FS_Pos)                     /*!< 0x00008000 */
8805 #define I2C_CCR_FS                I2C_CCR_FS_Msk                               /*!<I2C Master Mode Selection                                  */
8806 
8807 /******************  Bit definition for I2C_TRISE register  *******************/
8808 #define I2C_TRISE_TRISE_Pos       (0U)
8809 #define I2C_TRISE_TRISE_Msk       (0x3FUL << I2C_TRISE_TRISE_Pos)               /*!< 0x0000003F */
8810 #define I2C_TRISE_TRISE           I2C_TRISE_TRISE_Msk                          /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
8811 
8812 /******************  Bit definition for I2C_FLTR register  *******************/
8813 #define I2C_FLTR_DNF_Pos          (0U)
8814 #define I2C_FLTR_DNF_Msk          (0xFUL << I2C_FLTR_DNF_Pos)                   /*!< 0x0000000F */
8815 #define I2C_FLTR_DNF              I2C_FLTR_DNF_Msk                             /*!<Digital Noise Filter */
8816 #define I2C_FLTR_ANOFF_Pos        (4U)
8817 #define I2C_FLTR_ANOFF_Msk        (0x1UL << I2C_FLTR_ANOFF_Pos)                 /*!< 0x00000010 */
8818 #define I2C_FLTR_ANOFF            I2C_FLTR_ANOFF_Msk                           /*!<Analog Noise Filter OFF */
8819 
8820 /******************************************************************************/
8821 /*                                                                            */
8822 /*        Fast Mode Plus Inter-integrated Circuit Interface (I2C)             */
8823 /*                                                                            */
8824 /******************************************************************************/
8825 /*******************  Bit definition for I2C_CR1 register  *******************/
8826 #define FMPI2C_CR1_PE_Pos               (0U)
8827 #define FMPI2C_CR1_PE_Msk               (0x1UL << FMPI2C_CR1_PE_Pos)            /*!< 0x00000001 */
8828 #define FMPI2C_CR1_PE                   FMPI2C_CR1_PE_Msk                      /*!< Peripheral enable                   */
8829 #define FMPI2C_CR1_TXIE_Pos             (1U)
8830 #define FMPI2C_CR1_TXIE_Msk             (0x1UL << FMPI2C_CR1_TXIE_Pos)          /*!< 0x00000002 */
8831 #define FMPI2C_CR1_TXIE                 FMPI2C_CR1_TXIE_Msk                    /*!< TX interrupt enable                 */
8832 #define FMPI2C_CR1_RXIE_Pos             (2U)
8833 #define FMPI2C_CR1_RXIE_Msk             (0x1UL << FMPI2C_CR1_RXIE_Pos)          /*!< 0x00000004 */
8834 #define FMPI2C_CR1_RXIE                 FMPI2C_CR1_RXIE_Msk                    /*!< RX interrupt enable                 */
8835 #define FMPI2C_CR1_ADDRIE_Pos           (3U)
8836 #define FMPI2C_CR1_ADDRIE_Msk           (0x1UL << FMPI2C_CR1_ADDRIE_Pos)        /*!< 0x00000008 */
8837 #define FMPI2C_CR1_ADDRIE               FMPI2C_CR1_ADDRIE_Msk                  /*!< Address match interrupt enable      */
8838 #define FMPI2C_CR1_NACKIE_Pos           (4U)
8839 #define FMPI2C_CR1_NACKIE_Msk           (0x1UL << FMPI2C_CR1_NACKIE_Pos)        /*!< 0x00000010 */
8840 #define FMPI2C_CR1_NACKIE               FMPI2C_CR1_NACKIE_Msk                  /*!< NACK received interrupt enable      */
8841 #define FMPI2C_CR1_STOPIE_Pos           (5U)
8842 #define FMPI2C_CR1_STOPIE_Msk           (0x1UL << FMPI2C_CR1_STOPIE_Pos)        /*!< 0x00000020 */
8843 #define FMPI2C_CR1_STOPIE               FMPI2C_CR1_STOPIE_Msk                  /*!< STOP detection interrupt enable     */
8844 #define FMPI2C_CR1_TCIE_Pos             (6U)
8845 #define FMPI2C_CR1_TCIE_Msk             (0x1UL << FMPI2C_CR1_TCIE_Pos)          /*!< 0x00000040 */
8846 #define FMPI2C_CR1_TCIE                 FMPI2C_CR1_TCIE_Msk                    /*!< Transfer complete interrupt enable  */
8847 #define FMPI2C_CR1_ERRIE_Pos            (7U)
8848 #define FMPI2C_CR1_ERRIE_Msk            (0x1UL << FMPI2C_CR1_ERRIE_Pos)         /*!< 0x00000080 */
8849 #define FMPI2C_CR1_ERRIE                FMPI2C_CR1_ERRIE_Msk                   /*!< Errors interrupt enable             */
8850 #define FMPI2C_CR1_DNF_Pos              (8U)
8851 #define FMPI2C_CR1_DNF_Msk              (0xFUL << FMPI2C_CR1_DNF_Pos)           /*!< 0x00000F00 */
8852 #define FMPI2C_CR1_DNF                  FMPI2C_CR1_DNF_Msk                     /*!< Digital noise filter                */
8853 #define FMPI2C_CR1_ANFOFF_Pos           (12U)
8854 #define FMPI2C_CR1_ANFOFF_Msk           (0x1UL << FMPI2C_CR1_ANFOFF_Pos)        /*!< 0x00001000 */
8855 #define FMPI2C_CR1_ANFOFF               FMPI2C_CR1_ANFOFF_Msk                  /*!< Analog noise filter OFF             */
8856 #define FMPI2C_CR1_TXDMAEN_Pos          (14U)
8857 #define FMPI2C_CR1_TXDMAEN_Msk          (0x1UL << FMPI2C_CR1_TXDMAEN_Pos)       /*!< 0x00004000 */
8858 #define FMPI2C_CR1_TXDMAEN              FMPI2C_CR1_TXDMAEN_Msk                 /*!< DMA transmission requests enable    */
8859 #define FMPI2C_CR1_RXDMAEN_Pos          (15U)
8860 #define FMPI2C_CR1_RXDMAEN_Msk          (0x1UL << FMPI2C_CR1_RXDMAEN_Pos)       /*!< 0x00008000 */
8861 #define FMPI2C_CR1_RXDMAEN              FMPI2C_CR1_RXDMAEN_Msk                 /*!< DMA reception requests enable       */
8862 #define FMPI2C_CR1_SBC_Pos              (16U)
8863 #define FMPI2C_CR1_SBC_Msk              (0x1UL << FMPI2C_CR1_SBC_Pos)           /*!< 0x00010000 */
8864 #define FMPI2C_CR1_SBC                  FMPI2C_CR1_SBC_Msk                     /*!< Slave byte control                  */
8865 #define FMPI2C_CR1_NOSTRETCH_Pos        (17U)
8866 #define FMPI2C_CR1_NOSTRETCH_Msk        (0x1UL << FMPI2C_CR1_NOSTRETCH_Pos)     /*!< 0x00020000 */
8867 #define FMPI2C_CR1_NOSTRETCH            FMPI2C_CR1_NOSTRETCH_Msk               /*!< Clock stretching disable            */
8868 #define FMPI2C_CR1_GCEN_Pos             (19U)
8869 #define FMPI2C_CR1_GCEN_Msk             (0x1UL << FMPI2C_CR1_GCEN_Pos)          /*!< 0x00080000 */
8870 #define FMPI2C_CR1_GCEN                 FMPI2C_CR1_GCEN_Msk                    /*!< General call enable                 */
8871 #define FMPI2C_CR1_SMBHEN_Pos           (20U)
8872 #define FMPI2C_CR1_SMBHEN_Msk           (0x1UL << FMPI2C_CR1_SMBHEN_Pos)        /*!< 0x00100000 */
8873 #define FMPI2C_CR1_SMBHEN               FMPI2C_CR1_SMBHEN_Msk                  /*!< SMBus host address enable           */
8874 #define FMPI2C_CR1_SMBDEN_Pos           (21U)
8875 #define FMPI2C_CR1_SMBDEN_Msk           (0x1UL << FMPI2C_CR1_SMBDEN_Pos)        /*!< 0x00200000 */
8876 #define FMPI2C_CR1_SMBDEN               FMPI2C_CR1_SMBDEN_Msk                  /*!< SMBus device default address enable */
8877 #define FMPI2C_CR1_ALERTEN_Pos          (22U)
8878 #define FMPI2C_CR1_ALERTEN_Msk          (0x1UL << FMPI2C_CR1_ALERTEN_Pos)       /*!< 0x00400000 */
8879 #define FMPI2C_CR1_ALERTEN              FMPI2C_CR1_ALERTEN_Msk                 /*!< SMBus alert enable                  */
8880 #define FMPI2C_CR1_PECEN_Pos            (23U)
8881 #define FMPI2C_CR1_PECEN_Msk            (0x1UL << FMPI2C_CR1_PECEN_Pos)         /*!< 0x00800000 */
8882 #define FMPI2C_CR1_PECEN                FMPI2C_CR1_PECEN_Msk                   /*!< PEC enable                          */
8883 
8884 /* Legacy Defines */
8885 #define FMPI2C_CR1_DFN_Pos              FMPI2C_CR1_DNF_Pos
8886 #define FMPI2C_CR1_DFN_Msk              FMPI2C_CR1_DNF_Msk
8887 #define FMPI2C_CR1_DFN                  FMPI2C_CR1_DNF
8888 /******************  Bit definition for I2C_CR2 register  ********************/
8889 #define FMPI2C_CR2_SADD_Pos             (0U)
8890 #define FMPI2C_CR2_SADD_Msk             (0x3FFUL << FMPI2C_CR2_SADD_Pos)        /*!< 0x000003FF */
8891 #define FMPI2C_CR2_SADD                 FMPI2C_CR2_SADD_Msk                    /*!< Slave address (master mode)                             */
8892 #define FMPI2C_CR2_RD_WRN_Pos           (10U)
8893 #define FMPI2C_CR2_RD_WRN_Msk           (0x1UL << FMPI2C_CR2_RD_WRN_Pos)        /*!< 0x00000400 */
8894 #define FMPI2C_CR2_RD_WRN               FMPI2C_CR2_RD_WRN_Msk                  /*!< Transfer direction (master mode)                        */
8895 #define FMPI2C_CR2_ADD10_Pos            (11U)
8896 #define FMPI2C_CR2_ADD10_Msk            (0x1UL << FMPI2C_CR2_ADD10_Pos)         /*!< 0x00000800 */
8897 #define FMPI2C_CR2_ADD10                FMPI2C_CR2_ADD10_Msk                   /*!< 10-bit addressing mode (master mode)                    */
8898 #define FMPI2C_CR2_HEAD10R_Pos          (12U)
8899 #define FMPI2C_CR2_HEAD10R_Msk          (0x1UL << FMPI2C_CR2_HEAD10R_Pos)       /*!< 0x00001000 */
8900 #define FMPI2C_CR2_HEAD10R              FMPI2C_CR2_HEAD10R_Msk                 /*!< 10-bit address header only read direction (master mode) */
8901 #define FMPI2C_CR2_START_Pos            (13U)
8902 #define FMPI2C_CR2_START_Msk            (0x1UL << FMPI2C_CR2_START_Pos)         /*!< 0x00002000 */
8903 #define FMPI2C_CR2_START                FMPI2C_CR2_START_Msk                   /*!< START generation                                        */
8904 #define FMPI2C_CR2_STOP_Pos             (14U)
8905 #define FMPI2C_CR2_STOP_Msk             (0x1UL << FMPI2C_CR2_STOP_Pos)          /*!< 0x00004000 */
8906 #define FMPI2C_CR2_STOP                 FMPI2C_CR2_STOP_Msk                    /*!< STOP generation (master mode)                           */
8907 #define FMPI2C_CR2_NACK_Pos             (15U)
8908 #define FMPI2C_CR2_NACK_Msk             (0x1UL << FMPI2C_CR2_NACK_Pos)          /*!< 0x00008000 */
8909 #define FMPI2C_CR2_NACK                 FMPI2C_CR2_NACK_Msk                    /*!< NACK generation (slave mode)                            */
8910 #define FMPI2C_CR2_NBYTES_Pos           (16U)
8911 #define FMPI2C_CR2_NBYTES_Msk           (0xFFUL << FMPI2C_CR2_NBYTES_Pos)       /*!< 0x00FF0000 */
8912 #define FMPI2C_CR2_NBYTES               FMPI2C_CR2_NBYTES_Msk                  /*!< Number of bytes                                         */
8913 #define FMPI2C_CR2_RELOAD_Pos           (24U)
8914 #define FMPI2C_CR2_RELOAD_Msk           (0x1UL << FMPI2C_CR2_RELOAD_Pos)        /*!< 0x01000000 */
8915 #define FMPI2C_CR2_RELOAD               FMPI2C_CR2_RELOAD_Msk                  /*!< NBYTES reload mode                                      */
8916 #define FMPI2C_CR2_AUTOEND_Pos          (25U)
8917 #define FMPI2C_CR2_AUTOEND_Msk          (0x1UL << FMPI2C_CR2_AUTOEND_Pos)       /*!< 0x02000000 */
8918 #define FMPI2C_CR2_AUTOEND              FMPI2C_CR2_AUTOEND_Msk                 /*!< Automatic end mode (master mode)                        */
8919 #define FMPI2C_CR2_PECBYTE_Pos          (26U)
8920 #define FMPI2C_CR2_PECBYTE_Msk          (0x1UL << FMPI2C_CR2_PECBYTE_Pos)       /*!< 0x04000000 */
8921 #define FMPI2C_CR2_PECBYTE              FMPI2C_CR2_PECBYTE_Msk                 /*!< Packet error checking byte                              */
8922 
8923 /*******************  Bit definition for I2C_OAR1 register  ******************/
8924 #define FMPI2C_OAR1_OA1_Pos             (0U)
8925 #define FMPI2C_OAR1_OA1_Msk             (0x3FFUL << FMPI2C_OAR1_OA1_Pos)        /*!< 0x000003FF */
8926 #define FMPI2C_OAR1_OA1                 FMPI2C_OAR1_OA1_Msk                    /*!< Interface own address 1   */
8927 #define FMPI2C_OAR1_OA1MODE_Pos         (10U)
8928 #define FMPI2C_OAR1_OA1MODE_Msk         (0x1UL << FMPI2C_OAR1_OA1MODE_Pos)      /*!< 0x00000400 */
8929 #define FMPI2C_OAR1_OA1MODE             FMPI2C_OAR1_OA1MODE_Msk                /*!< Own address 1 10-bit mode */
8930 #define FMPI2C_OAR1_OA1EN_Pos           (15U)
8931 #define FMPI2C_OAR1_OA1EN_Msk           (0x1UL << FMPI2C_OAR1_OA1EN_Pos)        /*!< 0x00008000 */
8932 #define FMPI2C_OAR1_OA1EN               FMPI2C_OAR1_OA1EN_Msk                  /*!< Own address 1 enable      */
8933 
8934 /*******************  Bit definition for I2C_OAR2 register  ******************/
8935 #define FMPI2C_OAR2_OA2_Pos             (1U)
8936 #define FMPI2C_OAR2_OA2_Msk             (0x7FUL << FMPI2C_OAR2_OA2_Pos)         /*!< 0x000000FE */
8937 #define FMPI2C_OAR2_OA2                 FMPI2C_OAR2_OA2_Msk                    /*!< Interface own address 2 */
8938 #define FMPI2C_OAR2_OA2MSK_Pos          (8U)
8939 #define FMPI2C_OAR2_OA2MSK_Msk          (0x7UL << FMPI2C_OAR2_OA2MSK_Pos)       /*!< 0x00000700 */
8940 #define FMPI2C_OAR2_OA2MSK              FMPI2C_OAR2_OA2MSK_Msk                 /*!< Own address 2 masks     */
8941 #define FMPI2C_OAR2_OA2EN_Pos           (15U)
8942 #define FMPI2C_OAR2_OA2EN_Msk           (0x1UL << FMPI2C_OAR2_OA2EN_Pos)        /*!< 0x00008000 */
8943 #define FMPI2C_OAR2_OA2EN               FMPI2C_OAR2_OA2EN_Msk                  /*!< Own address 2 enable    */
8944 
8945 /*******************  Bit definition for I2C_TIMINGR register *******************/
8946 #define FMPI2C_TIMINGR_SCLL_Pos         (0U)
8947 #define FMPI2C_TIMINGR_SCLL_Msk         (0xFFUL << FMPI2C_TIMINGR_SCLL_Pos)     /*!< 0x000000FF */
8948 #define FMPI2C_TIMINGR_SCLL             FMPI2C_TIMINGR_SCLL_Msk                /*!< SCL low period (master mode)  */
8949 #define FMPI2C_TIMINGR_SCLH_Pos         (8U)
8950 #define FMPI2C_TIMINGR_SCLH_Msk         (0xFFUL << FMPI2C_TIMINGR_SCLH_Pos)     /*!< 0x0000FF00 */
8951 #define FMPI2C_TIMINGR_SCLH             FMPI2C_TIMINGR_SCLH_Msk                /*!< SCL high period (master mode) */
8952 #define FMPI2C_TIMINGR_SDADEL_Pos       (16U)
8953 #define FMPI2C_TIMINGR_SDADEL_Msk       (0xFUL << FMPI2C_TIMINGR_SDADEL_Pos)    /*!< 0x000F0000 */
8954 #define FMPI2C_TIMINGR_SDADEL           FMPI2C_TIMINGR_SDADEL_Msk              /*!< Data hold time                */
8955 #define FMPI2C_TIMINGR_SCLDEL_Pos       (20U)
8956 #define FMPI2C_TIMINGR_SCLDEL_Msk       (0xFUL << FMPI2C_TIMINGR_SCLDEL_Pos)    /*!< 0x00F00000 */
8957 #define FMPI2C_TIMINGR_SCLDEL           FMPI2C_TIMINGR_SCLDEL_Msk              /*!< Data setup time               */
8958 #define FMPI2C_TIMINGR_PRESC_Pos        (28U)
8959 #define FMPI2C_TIMINGR_PRESC_Msk        (0xFUL << FMPI2C_TIMINGR_PRESC_Pos)     /*!< 0xF0000000 */
8960 #define FMPI2C_TIMINGR_PRESC            FMPI2C_TIMINGR_PRESC_Msk               /*!< Timings prescaler             */
8961 
8962 /******************* Bit definition for I2C_TIMEOUTR register *******************/
8963 #define FMPI2C_TIMEOUTR_TIMEOUTA_Pos    (0U)
8964 #define FMPI2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFUL << FMPI2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
8965 #define FMPI2C_TIMEOUTR_TIMEOUTA        FMPI2C_TIMEOUTR_TIMEOUTA_Msk           /*!< Bus timeout A                 */
8966 #define FMPI2C_TIMEOUTR_TIDLE_Pos       (12U)
8967 #define FMPI2C_TIMEOUTR_TIDLE_Msk       (0x1UL << FMPI2C_TIMEOUTR_TIDLE_Pos)    /*!< 0x00001000 */
8968 #define FMPI2C_TIMEOUTR_TIDLE           FMPI2C_TIMEOUTR_TIDLE_Msk              /*!< Idle clock timeout detection  */
8969 #define FMPI2C_TIMEOUTR_TIMOUTEN_Pos    (15U)
8970 #define FMPI2C_TIMEOUTR_TIMOUTEN_Msk    (0x1UL << FMPI2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
8971 #define FMPI2C_TIMEOUTR_TIMOUTEN        FMPI2C_TIMEOUTR_TIMOUTEN_Msk           /*!< Clock timeout enable          */
8972 #define FMPI2C_TIMEOUTR_TIMEOUTB_Pos    (16U)
8973 #define FMPI2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFUL << FMPI2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
8974 #define FMPI2C_TIMEOUTR_TIMEOUTB        FMPI2C_TIMEOUTR_TIMEOUTB_Msk           /*!< Bus timeout B                 */
8975 #define FMPI2C_TIMEOUTR_TEXTEN_Pos      (31U)
8976 #define FMPI2C_TIMEOUTR_TEXTEN_Msk      (0x1UL << FMPI2C_TIMEOUTR_TEXTEN_Pos)   /*!< 0x80000000 */
8977 #define FMPI2C_TIMEOUTR_TEXTEN          FMPI2C_TIMEOUTR_TEXTEN_Msk             /*!< Extended clock timeout enable */
8978 
8979 /******************  Bit definition for I2C_ISR register  *********************/
8980 #define FMPI2C_ISR_TXE_Pos              (0U)
8981 #define FMPI2C_ISR_TXE_Msk              (0x1UL << FMPI2C_ISR_TXE_Pos)           /*!< 0x00000001 */
8982 #define FMPI2C_ISR_TXE                  FMPI2C_ISR_TXE_Msk                     /*!< Transmit data register empty     */
8983 #define FMPI2C_ISR_TXIS_Pos             (1U)
8984 #define FMPI2C_ISR_TXIS_Msk             (0x1UL << FMPI2C_ISR_TXIS_Pos)          /*!< 0x00000002 */
8985 #define FMPI2C_ISR_TXIS                 FMPI2C_ISR_TXIS_Msk                    /*!< Transmit interrupt status        */
8986 #define FMPI2C_ISR_RXNE_Pos             (2U)
8987 #define FMPI2C_ISR_RXNE_Msk             (0x1UL << FMPI2C_ISR_RXNE_Pos)          /*!< 0x00000004 */
8988 #define FMPI2C_ISR_RXNE                 FMPI2C_ISR_RXNE_Msk                    /*!< Receive data register not empty  */
8989 #define FMPI2C_ISR_ADDR_Pos             (3U)
8990 #define FMPI2C_ISR_ADDR_Msk             (0x1UL << FMPI2C_ISR_ADDR_Pos)          /*!< 0x00000008 */
8991 #define FMPI2C_ISR_ADDR                 FMPI2C_ISR_ADDR_Msk                    /*!< Address matched (slave mode)     */
8992 #define FMPI2C_ISR_NACKF_Pos            (4U)
8993 #define FMPI2C_ISR_NACKF_Msk            (0x1UL << FMPI2C_ISR_NACKF_Pos)         /*!< 0x00000010 */
8994 #define FMPI2C_ISR_NACKF                FMPI2C_ISR_NACKF_Msk                   /*!< NACK received flag               */
8995 #define FMPI2C_ISR_STOPF_Pos            (5U)
8996 #define FMPI2C_ISR_STOPF_Msk            (0x1UL << FMPI2C_ISR_STOPF_Pos)         /*!< 0x00000020 */
8997 #define FMPI2C_ISR_STOPF                FMPI2C_ISR_STOPF_Msk                   /*!< STOP detection flag              */
8998 #define FMPI2C_ISR_TC_Pos               (6U)
8999 #define FMPI2C_ISR_TC_Msk               (0x1UL << FMPI2C_ISR_TC_Pos)            /*!< 0x00000040 */
9000 #define FMPI2C_ISR_TC                   FMPI2C_ISR_TC_Msk                      /*!< Transfer complete (master mode)  */
9001 #define FMPI2C_ISR_TCR_Pos              (7U)
9002 #define FMPI2C_ISR_TCR_Msk              (0x1UL << FMPI2C_ISR_TCR_Pos)           /*!< 0x00000080 */
9003 #define FMPI2C_ISR_TCR                  FMPI2C_ISR_TCR_Msk                     /*!< Transfer complete reload         */
9004 #define FMPI2C_ISR_BERR_Pos             (8U)
9005 #define FMPI2C_ISR_BERR_Msk             (0x1UL << FMPI2C_ISR_BERR_Pos)          /*!< 0x00000100 */
9006 #define FMPI2C_ISR_BERR                 FMPI2C_ISR_BERR_Msk                    /*!< Bus error                        */
9007 #define FMPI2C_ISR_ARLO_Pos             (9U)
9008 #define FMPI2C_ISR_ARLO_Msk             (0x1UL << FMPI2C_ISR_ARLO_Pos)          /*!< 0x00000200 */
9009 #define FMPI2C_ISR_ARLO                 FMPI2C_ISR_ARLO_Msk                    /*!< Arbitration lost                 */
9010 #define FMPI2C_ISR_OVR_Pos              (10U)
9011 #define FMPI2C_ISR_OVR_Msk              (0x1UL << FMPI2C_ISR_OVR_Pos)           /*!< 0x00000400 */
9012 #define FMPI2C_ISR_OVR                  FMPI2C_ISR_OVR_Msk                     /*!< Overrun/Underrun                 */
9013 #define FMPI2C_ISR_PECERR_Pos           (11U)
9014 #define FMPI2C_ISR_PECERR_Msk           (0x1UL << FMPI2C_ISR_PECERR_Pos)        /*!< 0x00000800 */
9015 #define FMPI2C_ISR_PECERR               FMPI2C_ISR_PECERR_Msk                  /*!< PEC error in reception           */
9016 #define FMPI2C_ISR_TIMEOUT_Pos          (12U)
9017 #define FMPI2C_ISR_TIMEOUT_Msk          (0x1UL << FMPI2C_ISR_TIMEOUT_Pos)       /*!< 0x00001000 */
9018 #define FMPI2C_ISR_TIMEOUT              FMPI2C_ISR_TIMEOUT_Msk                 /*!< Timeout or Tlow detection flag   */
9019 #define FMPI2C_ISR_ALERT_Pos            (13U)
9020 #define FMPI2C_ISR_ALERT_Msk            (0x1UL << FMPI2C_ISR_ALERT_Pos)         /*!< 0x00002000 */
9021 #define FMPI2C_ISR_ALERT                FMPI2C_ISR_ALERT_Msk                   /*!< SMBus alert                      */
9022 #define FMPI2C_ISR_BUSY_Pos             (15U)
9023 #define FMPI2C_ISR_BUSY_Msk             (0x1UL << FMPI2C_ISR_BUSY_Pos)          /*!< 0x00008000 */
9024 #define FMPI2C_ISR_BUSY                 FMPI2C_ISR_BUSY_Msk                    /*!< Bus busy                         */
9025 #define FMPI2C_ISR_DIR_Pos              (16U)
9026 #define FMPI2C_ISR_DIR_Msk              (0x1UL << FMPI2C_ISR_DIR_Pos)           /*!< 0x00010000 */
9027 #define FMPI2C_ISR_DIR                  FMPI2C_ISR_DIR_Msk                     /*!< Transfer direction (slave mode)  */
9028 #define FMPI2C_ISR_ADDCODE_Pos          (17U)
9029 #define FMPI2C_ISR_ADDCODE_Msk          (0x7FUL << FMPI2C_ISR_ADDCODE_Pos)      /*!< 0x00FE0000 */
9030 #define FMPI2C_ISR_ADDCODE              FMPI2C_ISR_ADDCODE_Msk                 /*!< Address match code (slave mode)  */
9031 
9032 /******************  Bit definition for I2C_ICR register  *********************/
9033 #define FMPI2C_ICR_ADDRCF_Pos           (3U)
9034 #define FMPI2C_ICR_ADDRCF_Msk           (0x1UL << FMPI2C_ICR_ADDRCF_Pos)        /*!< 0x00000008 */
9035 #define FMPI2C_ICR_ADDRCF               FMPI2C_ICR_ADDRCF_Msk                  /*!< Address matched clear flag  */
9036 #define FMPI2C_ICR_NACKCF_Pos           (4U)
9037 #define FMPI2C_ICR_NACKCF_Msk           (0x1UL << FMPI2C_ICR_NACKCF_Pos)        /*!< 0x00000010 */
9038 #define FMPI2C_ICR_NACKCF               FMPI2C_ICR_NACKCF_Msk                  /*!< NACK clear flag             */
9039 #define FMPI2C_ICR_STOPCF_Pos           (5U)
9040 #define FMPI2C_ICR_STOPCF_Msk           (0x1UL << FMPI2C_ICR_STOPCF_Pos)        /*!< 0x00000020 */
9041 #define FMPI2C_ICR_STOPCF               FMPI2C_ICR_STOPCF_Msk                  /*!< STOP detection clear flag   */
9042 #define FMPI2C_ICR_BERRCF_Pos           (8U)
9043 #define FMPI2C_ICR_BERRCF_Msk           (0x1UL << FMPI2C_ICR_BERRCF_Pos)        /*!< 0x00000100 */
9044 #define FMPI2C_ICR_BERRCF               FMPI2C_ICR_BERRCF_Msk                  /*!< Bus error clear flag        */
9045 #define FMPI2C_ICR_ARLOCF_Pos           (9U)
9046 #define FMPI2C_ICR_ARLOCF_Msk           (0x1UL << FMPI2C_ICR_ARLOCF_Pos)        /*!< 0x00000200 */
9047 #define FMPI2C_ICR_ARLOCF               FMPI2C_ICR_ARLOCF_Msk                  /*!< Arbitration lost clear flag */
9048 #define FMPI2C_ICR_OVRCF_Pos            (10U)
9049 #define FMPI2C_ICR_OVRCF_Msk            (0x1UL << FMPI2C_ICR_OVRCF_Pos)         /*!< 0x00000400 */
9050 #define FMPI2C_ICR_OVRCF                FMPI2C_ICR_OVRCF_Msk                   /*!< Overrun/Underrun clear flag */
9051 #define FMPI2C_ICR_PECCF_Pos            (11U)
9052 #define FMPI2C_ICR_PECCF_Msk            (0x1UL << FMPI2C_ICR_PECCF_Pos)         /*!< 0x00000800 */
9053 #define FMPI2C_ICR_PECCF                FMPI2C_ICR_PECCF_Msk                   /*!< PAC error clear flag        */
9054 #define FMPI2C_ICR_TIMOUTCF_Pos         (12U)
9055 #define FMPI2C_ICR_TIMOUTCF_Msk         (0x1UL << FMPI2C_ICR_TIMOUTCF_Pos)      /*!< 0x00001000 */
9056 #define FMPI2C_ICR_TIMOUTCF             FMPI2C_ICR_TIMOUTCF_Msk                /*!< Timeout clear flag          */
9057 #define FMPI2C_ICR_ALERTCF_Pos          (13U)
9058 #define FMPI2C_ICR_ALERTCF_Msk          (0x1UL << FMPI2C_ICR_ALERTCF_Pos)       /*!< 0x00002000 */
9059 #define FMPI2C_ICR_ALERTCF              FMPI2C_ICR_ALERTCF_Msk                 /*!< Alert clear flag            */
9060 
9061 /******************  Bit definition for I2C_PECR register  *********************/
9062 #define FMPI2C_PECR_PEC_Pos             (0U)
9063 #define FMPI2C_PECR_PEC_Msk             (0xFFUL << FMPI2C_PECR_PEC_Pos)         /*!< 0x000000FF */
9064 #define FMPI2C_PECR_PEC                 FMPI2C_PECR_PEC_Msk                    /*!< PEC register */
9065 
9066 /******************  Bit definition for I2C_RXDR register  *********************/
9067 #define FMPI2C_RXDR_RXDATA_Pos          (0U)
9068 #define FMPI2C_RXDR_RXDATA_Msk          (0xFFUL << FMPI2C_RXDR_RXDATA_Pos)      /*!< 0x000000FF */
9069 #define FMPI2C_RXDR_RXDATA              FMPI2C_RXDR_RXDATA_Msk                 /*!< 8-bit receive data */
9070 
9071 /******************  Bit definition for I2C_TXDR register  *********************/
9072 #define FMPI2C_TXDR_TXDATA_Pos          (0U)
9073 #define FMPI2C_TXDR_TXDATA_Msk          (0xFFUL << FMPI2C_TXDR_TXDATA_Pos)      /*!< 0x000000FF */
9074 #define FMPI2C_TXDR_TXDATA              FMPI2C_TXDR_TXDATA_Msk                 /*!< 8-bit transmit data */
9075 
9076 
9077 
9078 /******************************************************************************/
9079 /*                                                                            */
9080 /*                           Independent WATCHDOG                             */
9081 /*                                                                            */
9082 /******************************************************************************/
9083 /*******************  Bit definition for IWDG_KR register  ********************/
9084 #define IWDG_KR_KEY_Pos     (0U)
9085 #define IWDG_KR_KEY_Msk     (0xFFFFUL << IWDG_KR_KEY_Pos)                       /*!< 0x0000FFFF */
9086 #define IWDG_KR_KEY         IWDG_KR_KEY_Msk                                    /*!<Key value (write only, read 0000h)  */
9087 
9088 /*******************  Bit definition for IWDG_PR register  ********************/
9089 #define IWDG_PR_PR_Pos      (0U)
9090 #define IWDG_PR_PR_Msk      (0x7UL << IWDG_PR_PR_Pos)                           /*!< 0x00000007 */
9091 #define IWDG_PR_PR          IWDG_PR_PR_Msk                                     /*!<PR[2:0] (Prescaler divider)         */
9092 #define IWDG_PR_PR_0        (0x1UL << IWDG_PR_PR_Pos)                           /*!< 0x01 */
9093 #define IWDG_PR_PR_1        (0x2UL << IWDG_PR_PR_Pos)                           /*!< 0x02 */
9094 #define IWDG_PR_PR_2        (0x4UL << IWDG_PR_PR_Pos)                           /*!< 0x04 */
9095 
9096 /*******************  Bit definition for IWDG_RLR register  *******************/
9097 #define IWDG_RLR_RL_Pos     (0U)
9098 #define IWDG_RLR_RL_Msk     (0xFFFUL << IWDG_RLR_RL_Pos)                        /*!< 0x00000FFF */
9099 #define IWDG_RLR_RL         IWDG_RLR_RL_Msk                                    /*!<Watchdog counter reload value        */
9100 
9101 /*******************  Bit definition for IWDG_SR register  ********************/
9102 #define IWDG_SR_PVU_Pos     (0U)
9103 #define IWDG_SR_PVU_Msk     (0x1UL << IWDG_SR_PVU_Pos)                          /*!< 0x00000001 */
9104 #define IWDG_SR_PVU         IWDG_SR_PVU_Msk                                    /*!<Watchdog prescaler value update      */
9105 #define IWDG_SR_RVU_Pos     (1U)
9106 #define IWDG_SR_RVU_Msk     (0x1UL << IWDG_SR_RVU_Pos)                          /*!< 0x00000002 */
9107 #define IWDG_SR_RVU         IWDG_SR_RVU_Msk                                    /*!<Watchdog counter reload value update */
9108 
9109 
9110 
9111 /******************************************************************************/
9112 /*                                                                            */
9113 /*                             Power Control                                  */
9114 /*                                                                            */
9115 /******************************************************************************/
9116 /********************  Bit definition for PWR_CR register  ********************/
9117 #define PWR_CR_LPDS_Pos        (0U)
9118 #define PWR_CR_LPDS_Msk        (0x1UL << PWR_CR_LPDS_Pos)                       /*!< 0x00000001 */
9119 #define PWR_CR_LPDS            PWR_CR_LPDS_Msk                                 /*!< Low-Power Deepsleep                 */
9120 #define PWR_CR_PDDS_Pos        (1U)
9121 #define PWR_CR_PDDS_Msk        (0x1UL << PWR_CR_PDDS_Pos)                       /*!< 0x00000002 */
9122 #define PWR_CR_PDDS            PWR_CR_PDDS_Msk                                 /*!< Power Down Deepsleep                */
9123 #define PWR_CR_CWUF_Pos        (2U)
9124 #define PWR_CR_CWUF_Msk        (0x1UL << PWR_CR_CWUF_Pos)                       /*!< 0x00000004 */
9125 #define PWR_CR_CWUF            PWR_CR_CWUF_Msk                                 /*!< Clear Wakeup Flag                   */
9126 #define PWR_CR_CSBF_Pos        (3U)
9127 #define PWR_CR_CSBF_Msk        (0x1UL << PWR_CR_CSBF_Pos)                       /*!< 0x00000008 */
9128 #define PWR_CR_CSBF            PWR_CR_CSBF_Msk                                 /*!< Clear Standby Flag                  */
9129 #define PWR_CR_PVDE_Pos        (4U)
9130 #define PWR_CR_PVDE_Msk        (0x1UL << PWR_CR_PVDE_Pos)                       /*!< 0x00000010 */
9131 #define PWR_CR_PVDE            PWR_CR_PVDE_Msk                                 /*!< Power Voltage Detector Enable       */
9132 
9133 #define PWR_CR_PLS_Pos         (5U)
9134 #define PWR_CR_PLS_Msk         (0x7UL << PWR_CR_PLS_Pos)                        /*!< 0x000000E0 */
9135 #define PWR_CR_PLS             PWR_CR_PLS_Msk                                  /*!< PLS[2:0] bits (PVD Level Selection) */
9136 #define PWR_CR_PLS_0           (0x1UL << PWR_CR_PLS_Pos)                        /*!< 0x00000020 */
9137 #define PWR_CR_PLS_1           (0x2UL << PWR_CR_PLS_Pos)                        /*!< 0x00000040 */
9138 #define PWR_CR_PLS_2           (0x4UL << PWR_CR_PLS_Pos)                        /*!< 0x00000080 */
9139 
9140 /*!< PVD level configuration */
9141 #define PWR_CR_PLS_LEV0        0x00000000U                                     /*!< PVD level 0 */
9142 #define PWR_CR_PLS_LEV1        0x00000020U                                     /*!< PVD level 1 */
9143 #define PWR_CR_PLS_LEV2        0x00000040U                                     /*!< PVD level 2 */
9144 #define PWR_CR_PLS_LEV3        0x00000060U                                     /*!< PVD level 3 */
9145 #define PWR_CR_PLS_LEV4        0x00000080U                                     /*!< PVD level 4 */
9146 #define PWR_CR_PLS_LEV5        0x000000A0U                                     /*!< PVD level 5 */
9147 #define PWR_CR_PLS_LEV6        0x000000C0U                                     /*!< PVD level 6 */
9148 #define PWR_CR_PLS_LEV7        0x000000E0U                                     /*!< PVD level 7 */
9149 #define PWR_CR_DBP_Pos         (8U)
9150 #define PWR_CR_DBP_Msk         (0x1UL << PWR_CR_DBP_Pos)                        /*!< 0x00000100 */
9151 #define PWR_CR_DBP             PWR_CR_DBP_Msk                                  /*!< Disable Backup Domain write protection                     */
9152 #define PWR_CR_FPDS_Pos        (9U)
9153 #define PWR_CR_FPDS_Msk        (0x1UL << PWR_CR_FPDS_Pos)                       /*!< 0x00000200 */
9154 #define PWR_CR_FPDS            PWR_CR_FPDS_Msk                                 /*!< Flash power down in Stop mode                              */
9155 #define PWR_CR_LPLVDS_Pos      (10U)
9156 #define PWR_CR_LPLVDS_Msk      (0x1UL << PWR_CR_LPLVDS_Pos)                     /*!< 0x00000400 */
9157 #define PWR_CR_LPLVDS          PWR_CR_LPLVDS_Msk                               /*!< Low Power Regulator Low Voltage in Deep Sleep mode         */
9158 #define PWR_CR_MRLVDS_Pos      (11U)
9159 #define PWR_CR_MRLVDS_Msk      (0x1UL << PWR_CR_MRLVDS_Pos)                     /*!< 0x00000800 */
9160 #define PWR_CR_MRLVDS          PWR_CR_MRLVDS_Msk                               /*!< Main Regulator Low Voltage in Deep Sleep mode              */
9161 #define PWR_CR_ADCDC1_Pos      (13U)
9162 #define PWR_CR_ADCDC1_Msk      (0x1UL << PWR_CR_ADCDC1_Pos)                     /*!< 0x00002000 */
9163 #define PWR_CR_ADCDC1          PWR_CR_ADCDC1_Msk                               /*!< Refer to AN4073 on how to use this bit                     */
9164 #define PWR_CR_VOS_Pos         (14U)
9165 #define PWR_CR_VOS_Msk         (0x3UL << PWR_CR_VOS_Pos)                        /*!< 0x0000C000 */
9166 #define PWR_CR_VOS             PWR_CR_VOS_Msk                                  /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
9167 #define PWR_CR_VOS_0           0x00004000U                                     /*!< Bit 0 */
9168 #define PWR_CR_VOS_1           0x00008000U                                     /*!< Bit 1 */
9169 #define PWR_CR_FMSSR_Pos       (20U)
9170 #define PWR_CR_FMSSR_Msk       (0x1UL << PWR_CR_FMSSR_Pos)                      /*!< 0x00100000 */
9171 #define PWR_CR_FMSSR           PWR_CR_FMSSR_Msk                                /*!< Flash Memory Sleep System Run        */
9172 #define PWR_CR_FISSR_Pos       (21U)
9173 #define PWR_CR_FISSR_Msk       (0x1UL << PWR_CR_FISSR_Pos)                      /*!< 0x00200000 */
9174 #define PWR_CR_FISSR           PWR_CR_FISSR_Msk                                /*!< Flash Interface Stop while System Run */
9175 
9176 
9177 /*******************  Bit definition for PWR_CSR register  ********************/
9178 #define PWR_CSR_WUF_Pos        (0U)
9179 #define PWR_CSR_WUF_Msk        (0x1UL << PWR_CSR_WUF_Pos)                       /*!< 0x00000001 */
9180 #define PWR_CSR_WUF            PWR_CSR_WUF_Msk                                 /*!< Wakeup Flag                                      */
9181 #define PWR_CSR_SBF_Pos        (1U)
9182 #define PWR_CSR_SBF_Msk        (0x1UL << PWR_CSR_SBF_Pos)                       /*!< 0x00000002 */
9183 #define PWR_CSR_SBF            PWR_CSR_SBF_Msk                                 /*!< Standby Flag                                     */
9184 #define PWR_CSR_PVDO_Pos       (2U)
9185 #define PWR_CSR_PVDO_Msk       (0x1UL << PWR_CSR_PVDO_Pos)                      /*!< 0x00000004 */
9186 #define PWR_CSR_PVDO           PWR_CSR_PVDO_Msk                                /*!< PVD Output                                       */
9187 #define PWR_CSR_BRR_Pos        (3U)
9188 #define PWR_CSR_BRR_Msk        (0x1UL << PWR_CSR_BRR_Pos)                       /*!< 0x00000008 */
9189 #define PWR_CSR_BRR            PWR_CSR_BRR_Msk                                 /*!< Backup regulator ready                           */
9190 #define PWR_CSR_EWUP3_Pos      (6U)
9191 #define PWR_CSR_EWUP3_Msk      (0x1UL << PWR_CSR_EWUP1_Pos)                     /*!< 0x00000040 */
9192 #define PWR_CSR_EWUP3          PWR_CSR_EWUP3_Msk                               /*!< Enable WKUP pin 3                                */
9193 #define PWR_CSR_EWUP2_Pos      (7U)
9194 #define PWR_CSR_EWUP2_Msk      (0x1UL << PWR_CSR_EWUP2_Pos)                     /*!< 0x00000080 */
9195 #define PWR_CSR_EWUP2          PWR_CSR_EWUP2_Msk                               /*!< Enable WKUP pin 2                                */
9196 #define PWR_CSR_EWUP1_Pos      (8U)
9197 #define PWR_CSR_EWUP1_Msk      (0x1UL << PWR_CSR_EWUP1_Pos)                     /*!< 0x00000100 */
9198 #define PWR_CSR_EWUP1          PWR_CSR_EWUP1_Msk                               /*!< Enable WKUP pin 1                                */
9199 #define PWR_CSR_BRE_Pos        (9U)
9200 #define PWR_CSR_BRE_Msk        (0x1UL << PWR_CSR_BRE_Pos)                       /*!< 0x00000200 */
9201 #define PWR_CSR_BRE            PWR_CSR_BRE_Msk                                 /*!< Backup regulator enable                          */
9202 #define PWR_CSR_VOSRDY_Pos     (14U)
9203 #define PWR_CSR_VOSRDY_Msk     (0x1UL << PWR_CSR_VOSRDY_Pos)                    /*!< 0x00004000 */
9204 #define PWR_CSR_VOSRDY         PWR_CSR_VOSRDY_Msk                              /*!< Regulator voltage scaling output selection ready */
9205 
9206 
9207 /******************************************************************************/
9208 /*                                                                            */
9209 /*                                    QUADSPI                                 */
9210 /*                                                                            */
9211 /******************************************************************************/
9212 /*****************  Bit definition for QUADSPI_CR register  *******************/
9213 #define QUADSPI_CR_EN_Pos                (0U)
9214 #define QUADSPI_CR_EN_Msk                (0x1UL << QUADSPI_CR_EN_Pos)           /*!< 0x00000001 */
9215 #define QUADSPI_CR_EN                    QUADSPI_CR_EN_Msk                     /*!< Enable                             */
9216 #define QUADSPI_CR_ABORT_Pos             (1U)
9217 #define QUADSPI_CR_ABORT_Msk             (0x1UL << QUADSPI_CR_ABORT_Pos)        /*!< 0x00000002 */
9218 #define QUADSPI_CR_ABORT                 QUADSPI_CR_ABORT_Msk                  /*!< Abort request                      */
9219 #define QUADSPI_CR_DMAEN_Pos             (2U)
9220 #define QUADSPI_CR_DMAEN_Msk             (0x1UL << QUADSPI_CR_DMAEN_Pos)        /*!< 0x00000004 */
9221 #define QUADSPI_CR_DMAEN                 QUADSPI_CR_DMAEN_Msk                  /*!< DMA Enable                         */
9222 #define QUADSPI_CR_TCEN_Pos              (3U)
9223 #define QUADSPI_CR_TCEN_Msk              (0x1UL << QUADSPI_CR_TCEN_Pos)         /*!< 0x00000008 */
9224 #define QUADSPI_CR_TCEN                  QUADSPI_CR_TCEN_Msk                   /*!< Timeout Counter Enable             */
9225 #define QUADSPI_CR_SSHIFT_Pos            (4U)
9226 #define QUADSPI_CR_SSHIFT_Msk            (0x1UL << QUADSPI_CR_SSHIFT_Pos)       /*!< 0x00000010 */
9227 #define QUADSPI_CR_SSHIFT                QUADSPI_CR_SSHIFT_Msk                 /*!< SSHIFT Sample Shift                */
9228 #define QUADSPI_CR_DFM_Pos               (6U)
9229 #define QUADSPI_CR_DFM_Msk               (0x1UL << QUADSPI_CR_DFM_Pos)          /*!< 0x00000040 */
9230 #define QUADSPI_CR_DFM                   QUADSPI_CR_DFM_Msk                    /*!< Dual Flash Mode                    */
9231 #define QUADSPI_CR_FSEL_Pos              (7U)
9232 #define QUADSPI_CR_FSEL_Msk              (0x1UL << QUADSPI_CR_FSEL_Pos)         /*!< 0x00000080 */
9233 #define QUADSPI_CR_FSEL                  QUADSPI_CR_FSEL_Msk                   /*!< Flash Select                       */
9234 #define QUADSPI_CR_FTHRES_Pos            (8U)
9235 #define QUADSPI_CR_FTHRES_Msk            (0x1FUL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00001F00 */
9236 #define QUADSPI_CR_FTHRES                QUADSPI_CR_FTHRES_Msk                 /*!< FTHRES[3:0] FIFO Level             */
9237 #define QUADSPI_CR_FTHRES_0              (0x01UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000100 */
9238 #define QUADSPI_CR_FTHRES_1              (0x02UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000200 */
9239 #define QUADSPI_CR_FTHRES_2              (0x04UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000400 */
9240 #define QUADSPI_CR_FTHRES_3              (0x08UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000800 */
9241 #define QUADSPI_CR_FTHRES_4              (0x10UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00001000 */
9242 #define QUADSPI_CR_TEIE_Pos              (16U)
9243 #define QUADSPI_CR_TEIE_Msk              (0x1UL << QUADSPI_CR_TEIE_Pos)         /*!< 0x00010000 */
9244 #define QUADSPI_CR_TEIE                  QUADSPI_CR_TEIE_Msk                   /*!< Transfer Error Interrupt Enable    */
9245 #define QUADSPI_CR_TCIE_Pos              (17U)
9246 #define QUADSPI_CR_TCIE_Msk              (0x1UL << QUADSPI_CR_TCIE_Pos)         /*!< 0x00020000 */
9247 #define QUADSPI_CR_TCIE                  QUADSPI_CR_TCIE_Msk                   /*!< Transfer Complete Interrupt Enable */
9248 #define QUADSPI_CR_FTIE_Pos              (18U)
9249 #define QUADSPI_CR_FTIE_Msk              (0x1UL << QUADSPI_CR_FTIE_Pos)         /*!< 0x00040000 */
9250 #define QUADSPI_CR_FTIE                  QUADSPI_CR_FTIE_Msk                   /*!< FIFO Threshold Interrupt Enable    */
9251 #define QUADSPI_CR_SMIE_Pos              (19U)
9252 #define QUADSPI_CR_SMIE_Msk              (0x1UL << QUADSPI_CR_SMIE_Pos)         /*!< 0x00080000 */
9253 #define QUADSPI_CR_SMIE                  QUADSPI_CR_SMIE_Msk                   /*!< Status Match Interrupt Enable      */
9254 #define QUADSPI_CR_TOIE_Pos              (20U)
9255 #define QUADSPI_CR_TOIE_Msk              (0x1UL << QUADSPI_CR_TOIE_Pos)         /*!< 0x00100000 */
9256 #define QUADSPI_CR_TOIE                  QUADSPI_CR_TOIE_Msk                   /*!< TimeOut Interrupt Enable           */
9257 #define QUADSPI_CR_APMS_Pos              (22U)
9258 #define QUADSPI_CR_APMS_Msk              (0x1UL << QUADSPI_CR_APMS_Pos)         /*!< 0x00400000 */
9259 #define QUADSPI_CR_APMS                  QUADSPI_CR_APMS_Msk                   /*!< Bit 1                              */
9260 #define QUADSPI_CR_PMM_Pos               (23U)
9261 #define QUADSPI_CR_PMM_Msk               (0x1UL << QUADSPI_CR_PMM_Pos)          /*!< 0x00800000 */
9262 #define QUADSPI_CR_PMM                   QUADSPI_CR_PMM_Msk                    /*!< Polling Match Mode                 */
9263 #define QUADSPI_CR_PRESCALER_Pos         (24U)
9264 #define QUADSPI_CR_PRESCALER_Msk         (0xFFUL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0xFF000000 */
9265 #define QUADSPI_CR_PRESCALER             QUADSPI_CR_PRESCALER_Msk              /*!< PRESCALER[7:0] Clock prescaler     */
9266 #define QUADSPI_CR_PRESCALER_0           (0x01UL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x01000000 */
9267 #define QUADSPI_CR_PRESCALER_1           (0x02UL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x02000000 */
9268 #define QUADSPI_CR_PRESCALER_2           (0x04UL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x04000000 */
9269 #define QUADSPI_CR_PRESCALER_3           (0x08UL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x08000000 */
9270 #define QUADSPI_CR_PRESCALER_4           (0x10UL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x10000000 */
9271 #define QUADSPI_CR_PRESCALER_5           (0x20UL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x20000000 */
9272 #define QUADSPI_CR_PRESCALER_6           (0x40UL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x40000000 */
9273 #define QUADSPI_CR_PRESCALER_7           (0x80UL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x80000000 */
9274 
9275 /*****************  Bit definition for QUADSPI_DCR register  ******************/
9276 #define QUADSPI_DCR_CKMODE_Pos           (0U)
9277 #define QUADSPI_DCR_CKMODE_Msk           (0x1UL << QUADSPI_DCR_CKMODE_Pos)      /*!< 0x00000001 */
9278 #define QUADSPI_DCR_CKMODE               QUADSPI_DCR_CKMODE_Msk                /*!< Mode 0 / Mode 3                 */
9279 #define QUADSPI_DCR_CSHT_Pos             (8U)
9280 #define QUADSPI_DCR_CSHT_Msk             (0x7UL << QUADSPI_DCR_CSHT_Pos)        /*!< 0x00000700 */
9281 #define QUADSPI_DCR_CSHT                 QUADSPI_DCR_CSHT_Msk                  /*!< CSHT[2:0]: ChipSelect High Time */
9282 #define QUADSPI_DCR_CSHT_0               (0x1UL << QUADSPI_DCR_CSHT_Pos)        /*!< 0x00000100 */
9283 #define QUADSPI_DCR_CSHT_1               (0x2UL << QUADSPI_DCR_CSHT_Pos)        /*!< 0x00000200 */
9284 #define QUADSPI_DCR_CSHT_2               (0x4UL << QUADSPI_DCR_CSHT_Pos)        /*!< 0x00000400 */
9285 #define QUADSPI_DCR_FSIZE_Pos            (16U)
9286 #define QUADSPI_DCR_FSIZE_Msk            (0x1FUL << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x001F0000 */
9287 #define QUADSPI_DCR_FSIZE                QUADSPI_DCR_FSIZE_Msk                 /*!< FSIZE[4:0]: Flash Size          */
9288 #define QUADSPI_DCR_FSIZE_0              (0x01UL << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x00010000 */
9289 #define QUADSPI_DCR_FSIZE_1              (0x02UL << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x00020000 */
9290 #define QUADSPI_DCR_FSIZE_2              (0x04UL << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x00040000 */
9291 #define QUADSPI_DCR_FSIZE_3              (0x08UL << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x00080000 */
9292 #define QUADSPI_DCR_FSIZE_4              (0x10UL << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x00100000 */
9293 
9294 /******************  Bit definition for QUADSPI_SR register  *******************/
9295 #define QUADSPI_SR_TEF_Pos               (0U)
9296 #define QUADSPI_SR_TEF_Msk               (0x1UL << QUADSPI_SR_TEF_Pos)          /*!< 0x00000001 */
9297 #define QUADSPI_SR_TEF                   QUADSPI_SR_TEF_Msk                    /*!< Transfer Error Flag    */
9298 #define QUADSPI_SR_TCF_Pos               (1U)
9299 #define QUADSPI_SR_TCF_Msk               (0x1UL << QUADSPI_SR_TCF_Pos)          /*!< 0x00000002 */
9300 #define QUADSPI_SR_TCF                   QUADSPI_SR_TCF_Msk                    /*!< Transfer Complete Flag */
9301 #define QUADSPI_SR_FTF_Pos               (2U)
9302 #define QUADSPI_SR_FTF_Msk               (0x1UL << QUADSPI_SR_FTF_Pos)          /*!< 0x00000004 */
9303 #define QUADSPI_SR_FTF                   QUADSPI_SR_FTF_Msk                    /*!< FIFO Threshlod Flag    */
9304 #define QUADSPI_SR_SMF_Pos               (3U)
9305 #define QUADSPI_SR_SMF_Msk               (0x1UL << QUADSPI_SR_SMF_Pos)          /*!< 0x00000008 */
9306 #define QUADSPI_SR_SMF                   QUADSPI_SR_SMF_Msk                    /*!< Status Match Flag      */
9307 #define QUADSPI_SR_TOF_Pos               (4U)
9308 #define QUADSPI_SR_TOF_Msk               (0x1UL << QUADSPI_SR_TOF_Pos)          /*!< 0x00000010 */
9309 #define QUADSPI_SR_TOF                   QUADSPI_SR_TOF_Msk                    /*!< Timeout Flag           */
9310 #define QUADSPI_SR_BUSY_Pos              (5U)
9311 #define QUADSPI_SR_BUSY_Msk              (0x1UL << QUADSPI_SR_BUSY_Pos)         /*!< 0x00000020 */
9312 #define QUADSPI_SR_BUSY                  QUADSPI_SR_BUSY_Msk                   /*!< Busy                   */
9313 #define QUADSPI_SR_FLEVEL_Pos            (8U)
9314 #define QUADSPI_SR_FLEVEL_Msk            (0x3FUL << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00003F00 */
9315 #define QUADSPI_SR_FLEVEL                QUADSPI_SR_FLEVEL_Msk                 /*!< FIFO Threshlod Flag    */
9316 #define QUADSPI_SR_FLEVEL_0              (0x01UL << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00000100 */
9317 #define QUADSPI_SR_FLEVEL_1              (0x02UL << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00000200 */
9318 #define QUADSPI_SR_FLEVEL_2              (0x04UL << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00000400 */
9319 #define QUADSPI_SR_FLEVEL_3              (0x08UL << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00000800 */
9320 #define QUADSPI_SR_FLEVEL_4              (0x10UL << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00001000 */
9321 #define QUADSPI_SR_FLEVEL_5              (0x20UL << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00002000 */
9322 
9323 /******************  Bit definition for QUADSPI_FCR register  ******************/
9324 #define QUADSPI_FCR_CTEF_Pos             (0U)
9325 #define QUADSPI_FCR_CTEF_Msk             (0x1UL << QUADSPI_FCR_CTEF_Pos)        /*!< 0x00000001 */
9326 #define QUADSPI_FCR_CTEF                 QUADSPI_FCR_CTEF_Msk                  /*!< Clear Transfer Error Flag    */
9327 #define QUADSPI_FCR_CTCF_Pos             (1U)
9328 #define QUADSPI_FCR_CTCF_Msk             (0x1UL << QUADSPI_FCR_CTCF_Pos)        /*!< 0x00000002 */
9329 #define QUADSPI_FCR_CTCF                 QUADSPI_FCR_CTCF_Msk                  /*!< Clear Transfer Complete Flag */
9330 #define QUADSPI_FCR_CSMF_Pos             (3U)
9331 #define QUADSPI_FCR_CSMF_Msk             (0x1UL << QUADSPI_FCR_CSMF_Pos)        /*!< 0x00000008 */
9332 #define QUADSPI_FCR_CSMF                 QUADSPI_FCR_CSMF_Msk                  /*!< Clear Status Match Flag      */
9333 #define QUADSPI_FCR_CTOF_Pos             (4U)
9334 #define QUADSPI_FCR_CTOF_Msk             (0x1UL << QUADSPI_FCR_CTOF_Pos)        /*!< 0x00000010 */
9335 #define QUADSPI_FCR_CTOF                 QUADSPI_FCR_CTOF_Msk                  /*!< Clear Timeout Flag           */
9336 
9337 /******************  Bit definition for QUADSPI_DLR register  ******************/
9338 #define QUADSPI_DLR_DL_Pos               (0U)
9339 #define QUADSPI_DLR_DL_Msk               (0xFFFFFFFFUL << QUADSPI_DLR_DL_Pos)   /*!< 0xFFFFFFFF */
9340 #define QUADSPI_DLR_DL                   QUADSPI_DLR_DL_Msk                    /*!< DL[31:0]: Data Length */
9341 
9342 /******************  Bit definition for QUADSPI_CCR register  ******************/
9343 #define QUADSPI_CCR_INSTRUCTION_Pos      (0U)
9344 #define QUADSPI_CCR_INSTRUCTION_Msk      (0xFFUL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */
9345 #define QUADSPI_CCR_INSTRUCTION          QUADSPI_CCR_INSTRUCTION_Msk           /*!< INSTRUCTION[7:0]: Instruction         */
9346 #define QUADSPI_CCR_INSTRUCTION_0        (0x01UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000001 */
9347 #define QUADSPI_CCR_INSTRUCTION_1        (0x02UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000002 */
9348 #define QUADSPI_CCR_INSTRUCTION_2        (0x04UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000004 */
9349 #define QUADSPI_CCR_INSTRUCTION_3        (0x08UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000008 */
9350 #define QUADSPI_CCR_INSTRUCTION_4        (0x10UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000010 */
9351 #define QUADSPI_CCR_INSTRUCTION_5        (0x20UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000020 */
9352 #define QUADSPI_CCR_INSTRUCTION_6        (0x40UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000040 */
9353 #define QUADSPI_CCR_INSTRUCTION_7        (0x80UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000080 */
9354 #define QUADSPI_CCR_IMODE_Pos            (8U)
9355 #define QUADSPI_CCR_IMODE_Msk            (0x3UL << QUADSPI_CCR_IMODE_Pos)       /*!< 0x00000300 */
9356 #define QUADSPI_CCR_IMODE                QUADSPI_CCR_IMODE_Msk                 /*!< IMODE[1:0]: Instruction Mode          */
9357 #define QUADSPI_CCR_IMODE_0              (0x1UL << QUADSPI_CCR_IMODE_Pos)       /*!< 0x00000100 */
9358 #define QUADSPI_CCR_IMODE_1              (0x2UL << QUADSPI_CCR_IMODE_Pos)       /*!< 0x00000200 */
9359 #define QUADSPI_CCR_ADMODE_Pos           (10U)
9360 #define QUADSPI_CCR_ADMODE_Msk           (0x3UL << QUADSPI_CCR_ADMODE_Pos)      /*!< 0x00000C00 */
9361 #define QUADSPI_CCR_ADMODE               QUADSPI_CCR_ADMODE_Msk                /*!< ADMODE[1:0]: Address Mode             */
9362 #define QUADSPI_CCR_ADMODE_0             (0x1UL << QUADSPI_CCR_ADMODE_Pos)      /*!< 0x00000400 */
9363 #define QUADSPI_CCR_ADMODE_1             (0x2UL << QUADSPI_CCR_ADMODE_Pos)      /*!< 0x00000800 */
9364 #define QUADSPI_CCR_ADSIZE_Pos           (12U)
9365 #define QUADSPI_CCR_ADSIZE_Msk           (0x3UL << QUADSPI_CCR_ADSIZE_Pos)      /*!< 0x00003000 */
9366 #define QUADSPI_CCR_ADSIZE               QUADSPI_CCR_ADSIZE_Msk                /*!< ADSIZE[1:0]: Address Size             */
9367 #define QUADSPI_CCR_ADSIZE_0             (0x1UL << QUADSPI_CCR_ADSIZE_Pos)      /*!< 0x00001000 */
9368 #define QUADSPI_CCR_ADSIZE_1             (0x2UL << QUADSPI_CCR_ADSIZE_Pos)      /*!< 0x00002000 */
9369 #define QUADSPI_CCR_ABMODE_Pos           (14U)
9370 #define QUADSPI_CCR_ABMODE_Msk           (0x3UL << QUADSPI_CCR_ABMODE_Pos)      /*!< 0x0000C000 */
9371 #define QUADSPI_CCR_ABMODE               QUADSPI_CCR_ABMODE_Msk                /*!< ABMODE[1:0]: Alternate Bytes Mode     */
9372 #define QUADSPI_CCR_ABMODE_0             (0x1UL << QUADSPI_CCR_ABMODE_Pos)      /*!< 0x00004000 */
9373 #define QUADSPI_CCR_ABMODE_1             (0x2UL << QUADSPI_CCR_ABMODE_Pos)      /*!< 0x00008000 */
9374 #define QUADSPI_CCR_ABSIZE_Pos           (16U)
9375 #define QUADSPI_CCR_ABSIZE_Msk           (0x3UL << QUADSPI_CCR_ABSIZE_Pos)      /*!< 0x00030000 */
9376 #define QUADSPI_CCR_ABSIZE               QUADSPI_CCR_ABSIZE_Msk                /*!< ABSIZE[1:0]: Instruction Mode         */
9377 #define QUADSPI_CCR_ABSIZE_0             (0x1UL << QUADSPI_CCR_ABSIZE_Pos)      /*!< 0x00010000 */
9378 #define QUADSPI_CCR_ABSIZE_1             (0x2UL << QUADSPI_CCR_ABSIZE_Pos)      /*!< 0x00020000 */
9379 #define QUADSPI_CCR_DCYC_Pos             (18U)
9380 #define QUADSPI_CCR_DCYC_Msk             (0x1FUL << QUADSPI_CCR_DCYC_Pos)       /*!< 0x007C0000 */
9381 #define QUADSPI_CCR_DCYC                 QUADSPI_CCR_DCYC_Msk                  /*!< DCYC[4:0]: Dummy Cycles               */
9382 #define QUADSPI_CCR_DCYC_0               (0x01UL << QUADSPI_CCR_DCYC_Pos)       /*!< 0x00040000 */
9383 #define QUADSPI_CCR_DCYC_1               (0x02UL << QUADSPI_CCR_DCYC_Pos)       /*!< 0x00080000 */
9384 #define QUADSPI_CCR_DCYC_2               (0x04UL << QUADSPI_CCR_DCYC_Pos)       /*!< 0x00100000 */
9385 #define QUADSPI_CCR_DCYC_3               (0x08UL << QUADSPI_CCR_DCYC_Pos)       /*!< 0x00200000 */
9386 #define QUADSPI_CCR_DCYC_4               (0x10UL << QUADSPI_CCR_DCYC_Pos)       /*!< 0x00400000 */
9387 #define QUADSPI_CCR_DMODE_Pos            (24U)
9388 #define QUADSPI_CCR_DMODE_Msk            (0x3UL << QUADSPI_CCR_DMODE_Pos)       /*!< 0x03000000 */
9389 #define QUADSPI_CCR_DMODE                QUADSPI_CCR_DMODE_Msk                 /*!< DMODE[1:0]: Data Mode                 */
9390 #define QUADSPI_CCR_DMODE_0              (0x1UL << QUADSPI_CCR_DMODE_Pos)       /*!< 0x01000000 */
9391 #define QUADSPI_CCR_DMODE_1              (0x2UL << QUADSPI_CCR_DMODE_Pos)       /*!< 0x02000000 */
9392 #define QUADSPI_CCR_FMODE_Pos            (26U)
9393 #define QUADSPI_CCR_FMODE_Msk            (0x3UL << QUADSPI_CCR_FMODE_Pos)       /*!< 0x0C000000 */
9394 #define QUADSPI_CCR_FMODE                QUADSPI_CCR_FMODE_Msk                 /*!< FMODE[1:0]: Functional Mode           */
9395 #define QUADSPI_CCR_FMODE_0              (0x1UL << QUADSPI_CCR_FMODE_Pos)       /*!< 0x04000000 */
9396 #define QUADSPI_CCR_FMODE_1              (0x2UL << QUADSPI_CCR_FMODE_Pos)       /*!< 0x08000000 */
9397 #define QUADSPI_CCR_SIOO_Pos             (28U)
9398 #define QUADSPI_CCR_SIOO_Msk             (0x1UL << QUADSPI_CCR_SIOO_Pos)        /*!< 0x10000000 */
9399 #define QUADSPI_CCR_SIOO                 QUADSPI_CCR_SIOO_Msk                  /*!< SIOO: Send Instruction Only Once Mode */
9400 #define QUADSPI_CCR_DHHC_Pos             (30U)
9401 #define QUADSPI_CCR_DHHC_Msk             (0x1UL << QUADSPI_CCR_DHHC_Pos)        /*!< 0x40000000 */
9402 #define QUADSPI_CCR_DHHC                 QUADSPI_CCR_DHHC_Msk                  /*!< DHHC: Delay Half Hclk Cycle           */
9403 #define QUADSPI_CCR_DDRM_Pos             (31U)
9404 #define QUADSPI_CCR_DDRM_Msk             (0x1UL << QUADSPI_CCR_DDRM_Pos)        /*!< 0x80000000 */
9405 #define QUADSPI_CCR_DDRM                 QUADSPI_CCR_DDRM_Msk                  /*!< DDRM: Double Data Rate Mode           */
9406 /******************  Bit definition for QUADSPI_AR register  *******************/
9407 #define QUADSPI_AR_ADDRESS_Pos           (0U)
9408 #define QUADSPI_AR_ADDRESS_Msk           (0xFFFFFFFFUL << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
9409 #define QUADSPI_AR_ADDRESS               QUADSPI_AR_ADDRESS_Msk                /*!< ADDRESS[31:0]: Address                */
9410 
9411 /******************  Bit definition for QUADSPI_ABR register  ******************/
9412 #define QUADSPI_ABR_ALTERNATE_Pos        (0U)
9413 #define QUADSPI_ABR_ALTERNATE_Msk        (0xFFFFFFFFUL << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
9414 #define QUADSPI_ABR_ALTERNATE            QUADSPI_ABR_ALTERNATE_Msk             /*!< ALTERNATE[31:0]: Alternate Bytes      */
9415 
9416 /******************  Bit definition for QUADSPI_DR register  *******************/
9417 #define QUADSPI_DR_DATA_Pos              (0U)
9418 #define QUADSPI_DR_DATA_Msk              (0xFFFFFFFFUL << QUADSPI_DR_DATA_Pos)  /*!< 0xFFFFFFFF */
9419 #define QUADSPI_DR_DATA                  QUADSPI_DR_DATA_Msk                   /*!< DATA[31:0]: Data                      */
9420 
9421 /******************  Bit definition for QUADSPI_PSMKR register  ****************/
9422 #define QUADSPI_PSMKR_MASK_Pos           (0U)
9423 #define QUADSPI_PSMKR_MASK_Msk           (0xFFFFFFFFUL << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */
9424 #define QUADSPI_PSMKR_MASK               QUADSPI_PSMKR_MASK_Msk                /*!< MASK[31:0]: Status Mask               */
9425 
9426 /******************  Bit definition for QUADSPI_PSMAR register  ****************/
9427 #define QUADSPI_PSMAR_MATCH_Pos          (0U)
9428 #define QUADSPI_PSMAR_MATCH_Msk          (0xFFFFFFFFUL << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */
9429 #define QUADSPI_PSMAR_MATCH              QUADSPI_PSMAR_MATCH_Msk               /*!< MATCH[31:0]: Status Match             */
9430 
9431 /******************  Bit definition for QUADSPI_PIR register  *****************/
9432 #define QUADSPI_PIR_INTERVAL_Pos         (0U)
9433 #define QUADSPI_PIR_INTERVAL_Msk         (0xFFFFUL << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */
9434 #define QUADSPI_PIR_INTERVAL             QUADSPI_PIR_INTERVAL_Msk              /*!< INTERVAL[15:0]: Polling Interval      */
9435 
9436 /******************  Bit definition for QUADSPI_LPTR register  *****************/
9437 #define QUADSPI_LPTR_TIMEOUT_Pos         (0U)
9438 #define QUADSPI_LPTR_TIMEOUT_Msk         (0xFFFFUL << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */
9439 #define QUADSPI_LPTR_TIMEOUT             QUADSPI_LPTR_TIMEOUT_Msk              /*!< TIMEOUT[15:0]: Timeout period         */
9440 
9441 /******************************************************************************/
9442 /*                                                                            */
9443 /*                         Reset and Clock Control                            */
9444 /*                                                                            */
9445 /******************************************************************************/
9446 /********************  Bit definition for RCC_CR register  ********************/
9447 #define RCC_CR_HSION_Pos                   (0U)
9448 #define RCC_CR_HSION_Msk                   (0x1UL << RCC_CR_HSION_Pos)          /*!< 0x00000001 */
9449 #define RCC_CR_HSION                       RCC_CR_HSION_Msk
9450 #define RCC_CR_HSIRDY_Pos                  (1U)
9451 #define RCC_CR_HSIRDY_Msk                  (0x1UL << RCC_CR_HSIRDY_Pos)         /*!< 0x00000002 */
9452 #define RCC_CR_HSIRDY                      RCC_CR_HSIRDY_Msk
9453 
9454 #define RCC_CR_HSITRIM_Pos                 (3U)
9455 #define RCC_CR_HSITRIM_Msk                 (0x1FUL << RCC_CR_HSITRIM_Pos)       /*!< 0x000000F8 */
9456 #define RCC_CR_HSITRIM                     RCC_CR_HSITRIM_Msk
9457 #define RCC_CR_HSITRIM_0                   (0x01UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000008 */
9458 #define RCC_CR_HSITRIM_1                   (0x02UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000010 */
9459 #define RCC_CR_HSITRIM_2                   (0x04UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000020 */
9460 #define RCC_CR_HSITRIM_3                   (0x08UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000040 */
9461 #define RCC_CR_HSITRIM_4                   (0x10UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000080 */
9462 
9463 #define RCC_CR_HSICAL_Pos                  (8U)
9464 #define RCC_CR_HSICAL_Msk                  (0xFFUL << RCC_CR_HSICAL_Pos)        /*!< 0x0000FF00 */
9465 #define RCC_CR_HSICAL                      RCC_CR_HSICAL_Msk
9466 #define RCC_CR_HSICAL_0                    (0x01UL << RCC_CR_HSICAL_Pos)        /*!< 0x00000100 */
9467 #define RCC_CR_HSICAL_1                    (0x02UL << RCC_CR_HSICAL_Pos)        /*!< 0x00000200 */
9468 #define RCC_CR_HSICAL_2                    (0x04UL << RCC_CR_HSICAL_Pos)        /*!< 0x00000400 */
9469 #define RCC_CR_HSICAL_3                    (0x08UL << RCC_CR_HSICAL_Pos)        /*!< 0x00000800 */
9470 #define RCC_CR_HSICAL_4                    (0x10UL << RCC_CR_HSICAL_Pos)        /*!< 0x00001000 */
9471 #define RCC_CR_HSICAL_5                    (0x20UL << RCC_CR_HSICAL_Pos)        /*!< 0x00002000 */
9472 #define RCC_CR_HSICAL_6                    (0x40UL << RCC_CR_HSICAL_Pos)        /*!< 0x00004000 */
9473 #define RCC_CR_HSICAL_7                    (0x80UL << RCC_CR_HSICAL_Pos)        /*!< 0x00008000 */
9474 
9475 #define RCC_CR_HSEON_Pos                   (16U)
9476 #define RCC_CR_HSEON_Msk                   (0x1UL << RCC_CR_HSEON_Pos)          /*!< 0x00010000 */
9477 #define RCC_CR_HSEON                       RCC_CR_HSEON_Msk
9478 #define RCC_CR_HSERDY_Pos                  (17U)
9479 #define RCC_CR_HSERDY_Msk                  (0x1UL << RCC_CR_HSERDY_Pos)         /*!< 0x00020000 */
9480 #define RCC_CR_HSERDY                      RCC_CR_HSERDY_Msk
9481 #define RCC_CR_HSEBYP_Pos                  (18U)
9482 #define RCC_CR_HSEBYP_Msk                  (0x1UL << RCC_CR_HSEBYP_Pos)         /*!< 0x00040000 */
9483 #define RCC_CR_HSEBYP                      RCC_CR_HSEBYP_Msk
9484 #define RCC_CR_CSSON_Pos                   (19U)
9485 #define RCC_CR_CSSON_Msk                   (0x1UL << RCC_CR_CSSON_Pos)          /*!< 0x00080000 */
9486 #define RCC_CR_CSSON                       RCC_CR_CSSON_Msk
9487 #define RCC_CR_PLLON_Pos                   (24U)
9488 #define RCC_CR_PLLON_Msk                   (0x1UL << RCC_CR_PLLON_Pos)          /*!< 0x01000000 */
9489 #define RCC_CR_PLLON                       RCC_CR_PLLON_Msk
9490 #define RCC_CR_PLLRDY_Pos                  (25U)
9491 #define RCC_CR_PLLRDY_Msk                  (0x1UL << RCC_CR_PLLRDY_Pos)         /*!< 0x02000000 */
9492 #define RCC_CR_PLLRDY                      RCC_CR_PLLRDY_Msk
9493 /*
9494  * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
9495  */
9496 #define RCC_PLLI2S_SUPPORT                                                     /*!< Support PLLI2S oscillator */
9497 
9498 #define RCC_CR_PLLI2SON_Pos                (26U)
9499 #define RCC_CR_PLLI2SON_Msk                (0x1UL << RCC_CR_PLLI2SON_Pos)       /*!< 0x04000000 */
9500 #define RCC_CR_PLLI2SON                    RCC_CR_PLLI2SON_Msk
9501 #define RCC_CR_PLLI2SRDY_Pos               (27U)
9502 #define RCC_CR_PLLI2SRDY_Msk               (0x1UL << RCC_CR_PLLI2SRDY_Pos)      /*!< 0x08000000 */
9503 #define RCC_CR_PLLI2SRDY                   RCC_CR_PLLI2SRDY_Msk
9504 
9505 /********************  Bit definition for RCC_PLLCFGR register  ***************/
9506 #define RCC_PLLCFGR_PLLM_Pos               (0U)
9507 #define RCC_PLLCFGR_PLLM_Msk               (0x3FUL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x0000003F */
9508 #define RCC_PLLCFGR_PLLM                   RCC_PLLCFGR_PLLM_Msk
9509 #define RCC_PLLCFGR_PLLM_0                 (0x01UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000001 */
9510 #define RCC_PLLCFGR_PLLM_1                 (0x02UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000002 */
9511 #define RCC_PLLCFGR_PLLM_2                 (0x04UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000004 */
9512 #define RCC_PLLCFGR_PLLM_3                 (0x08UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000008 */
9513 #define RCC_PLLCFGR_PLLM_4                 (0x10UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000010 */
9514 #define RCC_PLLCFGR_PLLM_5                 (0x20UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000020 */
9515 
9516 #define RCC_PLLCFGR_PLLN_Pos               (6U)
9517 #define RCC_PLLCFGR_PLLN_Msk               (0x1FFUL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00007FC0 */
9518 #define RCC_PLLCFGR_PLLN                   RCC_PLLCFGR_PLLN_Msk
9519 #define RCC_PLLCFGR_PLLN_0                 (0x001UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000040 */
9520 #define RCC_PLLCFGR_PLLN_1                 (0x002UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000080 */
9521 #define RCC_PLLCFGR_PLLN_2                 (0x004UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000100 */
9522 #define RCC_PLLCFGR_PLLN_3                 (0x008UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000200 */
9523 #define RCC_PLLCFGR_PLLN_4                 (0x010UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000400 */
9524 #define RCC_PLLCFGR_PLLN_5                 (0x020UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000800 */
9525 #define RCC_PLLCFGR_PLLN_6                 (0x040UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00001000 */
9526 #define RCC_PLLCFGR_PLLN_7                 (0x080UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00002000 */
9527 #define RCC_PLLCFGR_PLLN_8                 (0x100UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00004000 */
9528 
9529 #define RCC_PLLCFGR_PLLP_Pos               (16U)
9530 #define RCC_PLLCFGR_PLLP_Msk               (0x3UL << RCC_PLLCFGR_PLLP_Pos)      /*!< 0x00030000 */
9531 #define RCC_PLLCFGR_PLLP                   RCC_PLLCFGR_PLLP_Msk
9532 #define RCC_PLLCFGR_PLLP_0                 (0x1UL << RCC_PLLCFGR_PLLP_Pos)      /*!< 0x00010000 */
9533 #define RCC_PLLCFGR_PLLP_1                 (0x2UL << RCC_PLLCFGR_PLLP_Pos)      /*!< 0x00020000 */
9534 
9535 #define RCC_PLLCFGR_PLLSRC_Pos             (22U)
9536 #define RCC_PLLCFGR_PLLSRC_Msk             (0x1UL << RCC_PLLCFGR_PLLSRC_Pos)    /*!< 0x00400000 */
9537 #define RCC_PLLCFGR_PLLSRC                 RCC_PLLCFGR_PLLSRC_Msk
9538 #define RCC_PLLCFGR_PLLSRC_HSE_Pos         (22U)
9539 #define RCC_PLLCFGR_PLLSRC_HSE_Msk         (0x1UL << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */
9540 #define RCC_PLLCFGR_PLLSRC_HSE             RCC_PLLCFGR_PLLSRC_HSE_Msk
9541 #define RCC_PLLCFGR_PLLSRC_HSI             0x00000000U
9542 
9543 #define RCC_PLLCFGR_PLLQ_Pos               (24U)
9544 #define RCC_PLLCFGR_PLLQ_Msk               (0xFUL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x0F000000 */
9545 #define RCC_PLLCFGR_PLLQ                   RCC_PLLCFGR_PLLQ_Msk
9546 #define RCC_PLLCFGR_PLLQ_0                 (0x1UL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x01000000 */
9547 #define RCC_PLLCFGR_PLLQ_1                 (0x2UL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x02000000 */
9548 #define RCC_PLLCFGR_PLLQ_2                 (0x4UL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x04000000 */
9549 #define RCC_PLLCFGR_PLLQ_3                 (0x8UL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x08000000 */
9550 /*
9551  * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
9552  */
9553 #define RCC_PLLR_I2S_CLKSOURCE_SUPPORT     /*!< Support PLLR clock as I2S clock source */
9554 
9555 #define RCC_PLLCFGR_PLLR_Pos               (28U)
9556 #define RCC_PLLCFGR_PLLR_Msk               (0x7UL << RCC_PLLCFGR_PLLR_Pos)      /*!< 0x70000000 */
9557 #define RCC_PLLCFGR_PLLR                   RCC_PLLCFGR_PLLR_Msk
9558 #define RCC_PLLCFGR_PLLR_0                 (0x1UL << RCC_PLLCFGR_PLLR_Pos)      /*!< 0x10000000 */
9559 #define RCC_PLLCFGR_PLLR_1                 (0x2UL << RCC_PLLCFGR_PLLR_Pos)      /*!< 0x20000000 */
9560 #define RCC_PLLCFGR_PLLR_2                 (0x4UL << RCC_PLLCFGR_PLLR_Pos)      /*!< 0x40000000 */
9561 
9562 /********************  Bit definition for RCC_CFGR register  ******************/
9563 /*!< SW configuration */
9564 #define RCC_CFGR_SW_Pos                    (0U)
9565 #define RCC_CFGR_SW_Msk                    (0x3UL << RCC_CFGR_SW_Pos)           /*!< 0x00000003 */
9566 #define RCC_CFGR_SW                        RCC_CFGR_SW_Msk                     /*!< SW[1:0] bits (System clock Switch) */
9567 #define RCC_CFGR_SW_0                      (0x1UL << RCC_CFGR_SW_Pos)           /*!< 0x00000001 */
9568 #define RCC_CFGR_SW_1                      (0x2UL << RCC_CFGR_SW_Pos)           /*!< 0x00000002 */
9569 
9570 #define RCC_CFGR_SW_HSI                    0x00000000U                         /*!< HSI selected as system clock */
9571 #define RCC_CFGR_SW_HSE                    0x00000001U                         /*!< HSE selected as system clock */
9572 #define RCC_CFGR_SW_PLL                    0x00000002U                         /*!< PLL selected as system clock */
9573 
9574 /*!< SWS configuration */
9575 #define RCC_CFGR_SWS_Pos                   (2U)
9576 #define RCC_CFGR_SWS_Msk                   (0x3UL << RCC_CFGR_SWS_Pos)          /*!< 0x0000000C */
9577 #define RCC_CFGR_SWS                       RCC_CFGR_SWS_Msk                    /*!< SWS[1:0] bits (System Clock Switch Status) */
9578 #define RCC_CFGR_SWS_0                     (0x1UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000004 */
9579 #define RCC_CFGR_SWS_1                     (0x2UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000008 */
9580 
9581 #define RCC_CFGR_SWS_HSI                   0x00000000U                         /*!< HSI oscillator used as system clock        */
9582 #define RCC_CFGR_SWS_HSE                   0x00000004U                         /*!< HSE oscillator used as system clock        */
9583 #define RCC_CFGR_SWS_PLL                   0x00000008U                         /*!< PLL used as system clock                   */
9584 
9585 /*!< HPRE configuration */
9586 #define RCC_CFGR_HPRE_Pos                  (4U)
9587 #define RCC_CFGR_HPRE_Msk                  (0xFUL << RCC_CFGR_HPRE_Pos)         /*!< 0x000000F0 */
9588 #define RCC_CFGR_HPRE                      RCC_CFGR_HPRE_Msk                   /*!< HPRE[3:0] bits (AHB prescaler) */
9589 #define RCC_CFGR_HPRE_0                    (0x1UL << RCC_CFGR_HPRE_Pos)         /*!< 0x00000010 */
9590 #define RCC_CFGR_HPRE_1                    (0x2UL << RCC_CFGR_HPRE_Pos)         /*!< 0x00000020 */
9591 #define RCC_CFGR_HPRE_2                    (0x4UL << RCC_CFGR_HPRE_Pos)         /*!< 0x00000040 */
9592 #define RCC_CFGR_HPRE_3                    (0x8UL << RCC_CFGR_HPRE_Pos)         /*!< 0x00000080 */
9593 
9594 #define RCC_CFGR_HPRE_DIV1                 0x00000000U                         /*!< SYSCLK not divided    */
9595 #define RCC_CFGR_HPRE_DIV2                 0x00000080U                         /*!< SYSCLK divided by 2   */
9596 #define RCC_CFGR_HPRE_DIV4                 0x00000090U                         /*!< SYSCLK divided by 4   */
9597 #define RCC_CFGR_HPRE_DIV8                 0x000000A0U                         /*!< SYSCLK divided by 8   */
9598 #define RCC_CFGR_HPRE_DIV16                0x000000B0U                         /*!< SYSCLK divided by 16  */
9599 #define RCC_CFGR_HPRE_DIV64                0x000000C0U                         /*!< SYSCLK divided by 64  */
9600 #define RCC_CFGR_HPRE_DIV128               0x000000D0U                         /*!< SYSCLK divided by 128 */
9601 #define RCC_CFGR_HPRE_DIV256               0x000000E0U                         /*!< SYSCLK divided by 256 */
9602 #define RCC_CFGR_HPRE_DIV512               0x000000F0U                         /*!< SYSCLK divided by 512 */
9603 
9604 /*!< PPRE1 configuration */
9605 #define RCC_CFGR_PPRE1_Pos                 (10U)
9606 #define RCC_CFGR_PPRE1_Msk                 (0x7UL << RCC_CFGR_PPRE1_Pos)        /*!< 0x00001C00 */
9607 #define RCC_CFGR_PPRE1                     RCC_CFGR_PPRE1_Msk                  /*!< PRE1[2:0] bits (APB1 prescaler) */
9608 #define RCC_CFGR_PPRE1_0                   (0x1UL << RCC_CFGR_PPRE1_Pos)        /*!< 0x00000400 */
9609 #define RCC_CFGR_PPRE1_1                   (0x2UL << RCC_CFGR_PPRE1_Pos)        /*!< 0x00000800 */
9610 #define RCC_CFGR_PPRE1_2                   (0x4UL << RCC_CFGR_PPRE1_Pos)        /*!< 0x00001000 */
9611 
9612 #define RCC_CFGR_PPRE1_DIV1                0x00000000U                         /*!< HCLK not divided   */
9613 #define RCC_CFGR_PPRE1_DIV2                0x00001000U                         /*!< HCLK divided by 2  */
9614 #define RCC_CFGR_PPRE1_DIV4                0x00001400U                         /*!< HCLK divided by 4  */
9615 #define RCC_CFGR_PPRE1_DIV8                0x00001800U                         /*!< HCLK divided by 8  */
9616 #define RCC_CFGR_PPRE1_DIV16               0x00001C00U                         /*!< HCLK divided by 16 */
9617 
9618 /*!< PPRE2 configuration */
9619 #define RCC_CFGR_PPRE2_Pos                 (13U)
9620 #define RCC_CFGR_PPRE2_Msk                 (0x7UL << RCC_CFGR_PPRE2_Pos)        /*!< 0x0000E000 */
9621 #define RCC_CFGR_PPRE2                     RCC_CFGR_PPRE2_Msk                  /*!< PRE2[2:0] bits (APB2 prescaler) */
9622 #define RCC_CFGR_PPRE2_0                   (0x1UL << RCC_CFGR_PPRE2_Pos)        /*!< 0x00002000 */
9623 #define RCC_CFGR_PPRE2_1                   (0x2UL << RCC_CFGR_PPRE2_Pos)        /*!< 0x00004000 */
9624 #define RCC_CFGR_PPRE2_2                   (0x4UL << RCC_CFGR_PPRE2_Pos)        /*!< 0x00008000 */
9625 
9626 #define RCC_CFGR_PPRE2_DIV1                0x00000000U                         /*!< HCLK not divided   */
9627 #define RCC_CFGR_PPRE2_DIV2                0x00008000U                         /*!< HCLK divided by 2  */
9628 #define RCC_CFGR_PPRE2_DIV4                0x0000A000U                         /*!< HCLK divided by 4  */
9629 #define RCC_CFGR_PPRE2_DIV8                0x0000C000U                         /*!< HCLK divided by 8  */
9630 #define RCC_CFGR_PPRE2_DIV16               0x0000E000U                         /*!< HCLK divided by 16 */
9631 
9632 /*!< RTCPRE configuration */
9633 #define RCC_CFGR_RTCPRE_Pos                (16U)
9634 #define RCC_CFGR_RTCPRE_Msk                (0x1FUL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x001F0000 */
9635 #define RCC_CFGR_RTCPRE                    RCC_CFGR_RTCPRE_Msk
9636 #define RCC_CFGR_RTCPRE_0                  (0x01UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00010000 */
9637 #define RCC_CFGR_RTCPRE_1                  (0x02UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00020000 */
9638 #define RCC_CFGR_RTCPRE_2                  (0x04UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00040000 */
9639 #define RCC_CFGR_RTCPRE_3                  (0x08UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00080000 */
9640 #define RCC_CFGR_RTCPRE_4                  (0x10UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00100000 */
9641 
9642 /*!< MCO1 configuration */
9643 #define RCC_CFGR_MCO1_Pos                  (21U)
9644 #define RCC_CFGR_MCO1_Msk                  (0x3UL << RCC_CFGR_MCO1_Pos)         /*!< 0x00600000 */
9645 #define RCC_CFGR_MCO1                      RCC_CFGR_MCO1_Msk
9646 #define RCC_CFGR_MCO1_0                    (0x1UL << RCC_CFGR_MCO1_Pos)         /*!< 0x00200000 */
9647 #define RCC_CFGR_MCO1_1                    (0x2UL << RCC_CFGR_MCO1_Pos)         /*!< 0x00400000 */
9648 
9649 
9650 #define RCC_CFGR_MCO1PRE_Pos               (24U)
9651 #define RCC_CFGR_MCO1PRE_Msk               (0x7UL << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x07000000 */
9652 #define RCC_CFGR_MCO1PRE                   RCC_CFGR_MCO1PRE_Msk
9653 #define RCC_CFGR_MCO1PRE_0                 (0x1UL << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x01000000 */
9654 #define RCC_CFGR_MCO1PRE_1                 (0x2UL << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x02000000 */
9655 #define RCC_CFGR_MCO1PRE_2                 (0x4UL << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x04000000 */
9656 
9657 #define RCC_CFGR_MCO2PRE_Pos               (27U)
9658 #define RCC_CFGR_MCO2PRE_Msk               (0x7UL << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x38000000 */
9659 #define RCC_CFGR_MCO2PRE                   RCC_CFGR_MCO2PRE_Msk
9660 #define RCC_CFGR_MCO2PRE_0                 (0x1UL << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x08000000 */
9661 #define RCC_CFGR_MCO2PRE_1                 (0x2UL << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x10000000 */
9662 #define RCC_CFGR_MCO2PRE_2                 (0x4UL << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x20000000 */
9663 
9664 #define RCC_CFGR_MCO2_Pos                  (30U)
9665 #define RCC_CFGR_MCO2_Msk                  (0x3UL << RCC_CFGR_MCO2_Pos)         /*!< 0xC0000000 */
9666 #define RCC_CFGR_MCO2                      RCC_CFGR_MCO2_Msk
9667 #define RCC_CFGR_MCO2_0                    (0x1UL << RCC_CFGR_MCO2_Pos)         /*!< 0x40000000 */
9668 #define RCC_CFGR_MCO2_1                    (0x2UL << RCC_CFGR_MCO2_Pos)         /*!< 0x80000000 */
9669 
9670 /********************  Bit definition for RCC_CIR register  *******************/
9671 #define RCC_CIR_LSIRDYF_Pos                (0U)
9672 #define RCC_CIR_LSIRDYF_Msk                (0x1UL << RCC_CIR_LSIRDYF_Pos)       /*!< 0x00000001 */
9673 #define RCC_CIR_LSIRDYF                    RCC_CIR_LSIRDYF_Msk
9674 #define RCC_CIR_LSERDYF_Pos                (1U)
9675 #define RCC_CIR_LSERDYF_Msk                (0x1UL << RCC_CIR_LSERDYF_Pos)       /*!< 0x00000002 */
9676 #define RCC_CIR_LSERDYF                    RCC_CIR_LSERDYF_Msk
9677 #define RCC_CIR_HSIRDYF_Pos                (2U)
9678 #define RCC_CIR_HSIRDYF_Msk                (0x1UL << RCC_CIR_HSIRDYF_Pos)       /*!< 0x00000004 */
9679 #define RCC_CIR_HSIRDYF                    RCC_CIR_HSIRDYF_Msk
9680 #define RCC_CIR_HSERDYF_Pos                (3U)
9681 #define RCC_CIR_HSERDYF_Msk                (0x1UL << RCC_CIR_HSERDYF_Pos)       /*!< 0x00000008 */
9682 #define RCC_CIR_HSERDYF                    RCC_CIR_HSERDYF_Msk
9683 #define RCC_CIR_PLLRDYF_Pos                (4U)
9684 #define RCC_CIR_PLLRDYF_Msk                (0x1UL << RCC_CIR_PLLRDYF_Pos)       /*!< 0x00000010 */
9685 #define RCC_CIR_PLLRDYF                    RCC_CIR_PLLRDYF_Msk
9686 #define RCC_CIR_PLLI2SRDYF_Pos             (5U)
9687 #define RCC_CIR_PLLI2SRDYF_Msk             (0x1UL << RCC_CIR_PLLI2SRDYF_Pos)    /*!< 0x00000020 */
9688 #define RCC_CIR_PLLI2SRDYF                 RCC_CIR_PLLI2SRDYF_Msk
9689 
9690 #define RCC_CIR_CSSF_Pos                   (7U)
9691 #define RCC_CIR_CSSF_Msk                   (0x1UL << RCC_CIR_CSSF_Pos)          /*!< 0x00000080 */
9692 #define RCC_CIR_CSSF                       RCC_CIR_CSSF_Msk
9693 #define RCC_CIR_LSIRDYIE_Pos               (8U)
9694 #define RCC_CIR_LSIRDYIE_Msk               (0x1UL << RCC_CIR_LSIRDYIE_Pos)      /*!< 0x00000100 */
9695 #define RCC_CIR_LSIRDYIE                   RCC_CIR_LSIRDYIE_Msk
9696 #define RCC_CIR_LSERDYIE_Pos               (9U)
9697 #define RCC_CIR_LSERDYIE_Msk               (0x1UL << RCC_CIR_LSERDYIE_Pos)      /*!< 0x00000200 */
9698 #define RCC_CIR_LSERDYIE                   RCC_CIR_LSERDYIE_Msk
9699 #define RCC_CIR_HSIRDYIE_Pos               (10U)
9700 #define RCC_CIR_HSIRDYIE_Msk               (0x1UL << RCC_CIR_HSIRDYIE_Pos)      /*!< 0x00000400 */
9701 #define RCC_CIR_HSIRDYIE                   RCC_CIR_HSIRDYIE_Msk
9702 #define RCC_CIR_HSERDYIE_Pos               (11U)
9703 #define RCC_CIR_HSERDYIE_Msk               (0x1UL << RCC_CIR_HSERDYIE_Pos)      /*!< 0x00000800 */
9704 #define RCC_CIR_HSERDYIE                   RCC_CIR_HSERDYIE_Msk
9705 #define RCC_CIR_PLLRDYIE_Pos               (12U)
9706 #define RCC_CIR_PLLRDYIE_Msk               (0x1UL << RCC_CIR_PLLRDYIE_Pos)      /*!< 0x00001000 */
9707 #define RCC_CIR_PLLRDYIE                   RCC_CIR_PLLRDYIE_Msk
9708 #define RCC_CIR_PLLI2SRDYIE_Pos            (13U)
9709 #define RCC_CIR_PLLI2SRDYIE_Msk            (0x1UL << RCC_CIR_PLLI2SRDYIE_Pos)   /*!< 0x00002000 */
9710 #define RCC_CIR_PLLI2SRDYIE                RCC_CIR_PLLI2SRDYIE_Msk
9711 
9712 #define RCC_CIR_LSIRDYC_Pos                (16U)
9713 #define RCC_CIR_LSIRDYC_Msk                (0x1UL << RCC_CIR_LSIRDYC_Pos)       /*!< 0x00010000 */
9714 #define RCC_CIR_LSIRDYC                    RCC_CIR_LSIRDYC_Msk
9715 #define RCC_CIR_LSERDYC_Pos                (17U)
9716 #define RCC_CIR_LSERDYC_Msk                (0x1UL << RCC_CIR_LSERDYC_Pos)       /*!< 0x00020000 */
9717 #define RCC_CIR_LSERDYC                    RCC_CIR_LSERDYC_Msk
9718 #define RCC_CIR_HSIRDYC_Pos                (18U)
9719 #define RCC_CIR_HSIRDYC_Msk                (0x1UL << RCC_CIR_HSIRDYC_Pos)       /*!< 0x00040000 */
9720 #define RCC_CIR_HSIRDYC                    RCC_CIR_HSIRDYC_Msk
9721 #define RCC_CIR_HSERDYC_Pos                (19U)
9722 #define RCC_CIR_HSERDYC_Msk                (0x1UL << RCC_CIR_HSERDYC_Pos)       /*!< 0x00080000 */
9723 #define RCC_CIR_HSERDYC                    RCC_CIR_HSERDYC_Msk
9724 #define RCC_CIR_PLLRDYC_Pos                (20U)
9725 #define RCC_CIR_PLLRDYC_Msk                (0x1UL << RCC_CIR_PLLRDYC_Pos)       /*!< 0x00100000 */
9726 #define RCC_CIR_PLLRDYC                    RCC_CIR_PLLRDYC_Msk
9727 #define RCC_CIR_PLLI2SRDYC_Pos             (21U)
9728 #define RCC_CIR_PLLI2SRDYC_Msk             (0x1UL << RCC_CIR_PLLI2SRDYC_Pos)    /*!< 0x00200000 */
9729 #define RCC_CIR_PLLI2SRDYC                 RCC_CIR_PLLI2SRDYC_Msk
9730 
9731 #define RCC_CIR_CSSC_Pos                   (23U)
9732 #define RCC_CIR_CSSC_Msk                   (0x1UL << RCC_CIR_CSSC_Pos)          /*!< 0x00800000 */
9733 #define RCC_CIR_CSSC                       RCC_CIR_CSSC_Msk
9734 
9735 /********************  Bit definition for RCC_AHB1RSTR register  **************/
9736 #define RCC_AHB1RSTR_GPIOARST_Pos          (0U)
9737 #define RCC_AHB1RSTR_GPIOARST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */
9738 #define RCC_AHB1RSTR_GPIOARST              RCC_AHB1RSTR_GPIOARST_Msk
9739 #define RCC_AHB1RSTR_GPIOBRST_Pos          (1U)
9740 #define RCC_AHB1RSTR_GPIOBRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
9741 #define RCC_AHB1RSTR_GPIOBRST              RCC_AHB1RSTR_GPIOBRST_Msk
9742 #define RCC_AHB1RSTR_GPIOCRST_Pos          (2U)
9743 #define RCC_AHB1RSTR_GPIOCRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
9744 #define RCC_AHB1RSTR_GPIOCRST              RCC_AHB1RSTR_GPIOCRST_Msk
9745 #define RCC_AHB1RSTR_GPIODRST_Pos          (3U)
9746 #define RCC_AHB1RSTR_GPIODRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIODRST_Pos) /*!< 0x00000008 */
9747 #define RCC_AHB1RSTR_GPIODRST              RCC_AHB1RSTR_GPIODRST_Msk
9748 #define RCC_AHB1RSTR_GPIOERST_Pos          (4U)
9749 #define RCC_AHB1RSTR_GPIOERST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOERST_Pos) /*!< 0x00000010 */
9750 #define RCC_AHB1RSTR_GPIOERST              RCC_AHB1RSTR_GPIOERST_Msk
9751 #define RCC_AHB1RSTR_GPIOFRST_Pos          (5U)
9752 #define RCC_AHB1RSTR_GPIOFRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOFRST_Pos) /*!< 0x00000020 */
9753 #define RCC_AHB1RSTR_GPIOFRST              RCC_AHB1RSTR_GPIOFRST_Msk
9754 #define RCC_AHB1RSTR_GPIOGRST_Pos          (6U)
9755 #define RCC_AHB1RSTR_GPIOGRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOGRST_Pos) /*!< 0x00000040 */
9756 #define RCC_AHB1RSTR_GPIOGRST              RCC_AHB1RSTR_GPIOGRST_Msk
9757 #define RCC_AHB1RSTR_GPIOHRST_Pos          (7U)
9758 #define RCC_AHB1RSTR_GPIOHRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
9759 #define RCC_AHB1RSTR_GPIOHRST              RCC_AHB1RSTR_GPIOHRST_Msk
9760 #define RCC_AHB1RSTR_CRCRST_Pos            (12U)
9761 #define RCC_AHB1RSTR_CRCRST_Msk            (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)   /*!< 0x00001000 */
9762 #define RCC_AHB1RSTR_CRCRST                RCC_AHB1RSTR_CRCRST_Msk
9763 #define RCC_AHB1RSTR_DMA1RST_Pos           (21U)
9764 #define RCC_AHB1RSTR_DMA1RST_Msk           (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)  /*!< 0x00200000 */
9765 #define RCC_AHB1RSTR_DMA1RST               RCC_AHB1RSTR_DMA1RST_Msk
9766 #define RCC_AHB1RSTR_DMA2RST_Pos           (22U)
9767 #define RCC_AHB1RSTR_DMA2RST_Msk           (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)  /*!< 0x00400000 */
9768 #define RCC_AHB1RSTR_DMA2RST               RCC_AHB1RSTR_DMA2RST_Msk
9769 
9770 /********************  Bit definition for RCC_AHB2RSTR register  **************/
9771 #define RCC_AHB2RSTR_RNGRST_Pos            (6U)
9772 #define RCC_AHB2RSTR_RNGRST_Msk            (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)   /*!< 0x00000040 */
9773 #define RCC_AHB2RSTR_RNGRST                RCC_AHB2RSTR_RNGRST_Msk
9774 #define RCC_AHB2RSTR_OTGFSRST_Pos          (7U)
9775 #define RCC_AHB2RSTR_OTGFSRST_Msk          (0x1UL << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00000080 */
9776 #define RCC_AHB2RSTR_OTGFSRST              RCC_AHB2RSTR_OTGFSRST_Msk
9777 /********************  Bit definition for RCC_AHB3RSTR register  **************/
9778 #define RCC_AHB3RSTR_FSMCRST_Pos           (0U)
9779 #define RCC_AHB3RSTR_FSMCRST_Msk           (0x1UL << RCC_AHB3RSTR_FSMCRST_Pos)  /*!< 0x00000001 */
9780 #define RCC_AHB3RSTR_FSMCRST               RCC_AHB3RSTR_FSMCRST_Msk
9781 #define RCC_AHB3RSTR_QSPIRST_Pos           (1U)
9782 #define RCC_AHB3RSTR_QSPIRST_Msk           (0x1UL << RCC_AHB3RSTR_QSPIRST_Pos)  /*!< 0x00000002 */
9783 #define RCC_AHB3RSTR_QSPIRST               RCC_AHB3RSTR_QSPIRST_Msk
9784 
9785 
9786 /********************  Bit definition for RCC_APB1RSTR register  **************/
9787 #define RCC_APB1RSTR_TIM2RST_Pos           (0U)
9788 #define RCC_APB1RSTR_TIM2RST_Msk           (0x1UL << RCC_APB1RSTR_TIM2RST_Pos)  /*!< 0x00000001 */
9789 #define RCC_APB1RSTR_TIM2RST               RCC_APB1RSTR_TIM2RST_Msk
9790 #define RCC_APB1RSTR_TIM3RST_Pos           (1U)
9791 #define RCC_APB1RSTR_TIM3RST_Msk           (0x1UL << RCC_APB1RSTR_TIM3RST_Pos)  /*!< 0x00000002 */
9792 #define RCC_APB1RSTR_TIM3RST               RCC_APB1RSTR_TIM3RST_Msk
9793 #define RCC_APB1RSTR_TIM4RST_Pos           (2U)
9794 #define RCC_APB1RSTR_TIM4RST_Msk           (0x1UL << RCC_APB1RSTR_TIM4RST_Pos)  /*!< 0x00000004 */
9795 #define RCC_APB1RSTR_TIM4RST               RCC_APB1RSTR_TIM4RST_Msk
9796 #define RCC_APB1RSTR_TIM5RST_Pos           (3U)
9797 #define RCC_APB1RSTR_TIM5RST_Msk           (0x1UL << RCC_APB1RSTR_TIM5RST_Pos)  /*!< 0x00000008 */
9798 #define RCC_APB1RSTR_TIM5RST               RCC_APB1RSTR_TIM5RST_Msk
9799 #define RCC_APB1RSTR_TIM6RST_Pos           (4U)
9800 #define RCC_APB1RSTR_TIM6RST_Msk           (0x1UL << RCC_APB1RSTR_TIM6RST_Pos)  /*!< 0x00000010 */
9801 #define RCC_APB1RSTR_TIM6RST               RCC_APB1RSTR_TIM6RST_Msk
9802 #define RCC_APB1RSTR_TIM7RST_Pos           (5U)
9803 #define RCC_APB1RSTR_TIM7RST_Msk           (0x1UL << RCC_APB1RSTR_TIM7RST_Pos)  /*!< 0x00000020 */
9804 #define RCC_APB1RSTR_TIM7RST               RCC_APB1RSTR_TIM7RST_Msk
9805 #define RCC_APB1RSTR_TIM12RST_Pos          (6U)
9806 #define RCC_APB1RSTR_TIM12RST_Msk          (0x1UL << RCC_APB1RSTR_TIM12RST_Pos) /*!< 0x00000040 */
9807 #define RCC_APB1RSTR_TIM12RST              RCC_APB1RSTR_TIM12RST_Msk
9808 #define RCC_APB1RSTR_TIM13RST_Pos          (7U)
9809 #define RCC_APB1RSTR_TIM13RST_Msk          (0x1UL << RCC_APB1RSTR_TIM13RST_Pos) /*!< 0x00000080 */
9810 #define RCC_APB1RSTR_TIM13RST              RCC_APB1RSTR_TIM13RST_Msk
9811 #define RCC_APB1RSTR_TIM14RST_Pos          (8U)
9812 #define RCC_APB1RSTR_TIM14RST_Msk          (0x1UL << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */
9813 #define RCC_APB1RSTR_TIM14RST              RCC_APB1RSTR_TIM14RST_Msk
9814 #define RCC_APB1RSTR_LPTIM1RST_Pos         (9U)
9815 #define RCC_APB1RSTR_LPTIM1RST_Msk         (0x1UL << RCC_APB1RSTR_LPTIM1RST_Pos) /*!< 0x00000200 */
9816 #define RCC_APB1RSTR_LPTIM1RST             RCC_APB1RSTR_LPTIM1RST_Msk
9817 #define RCC_APB1RSTR_WWDGRST_Pos           (11U)
9818 #define RCC_APB1RSTR_WWDGRST_Msk           (0x1UL << RCC_APB1RSTR_WWDGRST_Pos)  /*!< 0x00000800 */
9819 #define RCC_APB1RSTR_WWDGRST               RCC_APB1RSTR_WWDGRST_Msk
9820 #define RCC_APB1RSTR_SPI2RST_Pos           (14U)
9821 #define RCC_APB1RSTR_SPI2RST_Msk           (0x1UL << RCC_APB1RSTR_SPI2RST_Pos)  /*!< 0x00004000 */
9822 #define RCC_APB1RSTR_SPI2RST               RCC_APB1RSTR_SPI2RST_Msk
9823 #define RCC_APB1RSTR_SPI3RST_Pos           (15U)
9824 #define RCC_APB1RSTR_SPI3RST_Msk           (0x1UL << RCC_APB1RSTR_SPI3RST_Pos)  /*!< 0x00008000 */
9825 #define RCC_APB1RSTR_SPI3RST               RCC_APB1RSTR_SPI3RST_Msk
9826 #define RCC_APB1RSTR_USART2RST_Pos         (17U)
9827 #define RCC_APB1RSTR_USART2RST_Msk         (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
9828 #define RCC_APB1RSTR_USART2RST             RCC_APB1RSTR_USART2RST_Msk
9829 #define RCC_APB1RSTR_USART3RST_Pos         (18U)
9830 #define RCC_APB1RSTR_USART3RST_Msk         (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
9831 #define RCC_APB1RSTR_USART3RST             RCC_APB1RSTR_USART3RST_Msk
9832 #define RCC_APB1RSTR_UART4RST_Pos          (19U)
9833 #define RCC_APB1RSTR_UART4RST_Msk          (0x1UL << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */
9834 #define RCC_APB1RSTR_UART4RST              RCC_APB1RSTR_UART4RST_Msk
9835 #define RCC_APB1RSTR_UART5RST_Pos          (20U)
9836 #define RCC_APB1RSTR_UART5RST_Msk          (0x1UL << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */
9837 #define RCC_APB1RSTR_UART5RST              RCC_APB1RSTR_UART5RST_Msk
9838 #define RCC_APB1RSTR_I2C1RST_Pos           (21U)
9839 #define RCC_APB1RSTR_I2C1RST_Msk           (0x1UL << RCC_APB1RSTR_I2C1RST_Pos)  /*!< 0x00200000 */
9840 #define RCC_APB1RSTR_I2C1RST               RCC_APB1RSTR_I2C1RST_Msk
9841 #define RCC_APB1RSTR_I2C2RST_Pos           (22U)
9842 #define RCC_APB1RSTR_I2C2RST_Msk           (0x1UL << RCC_APB1RSTR_I2C2RST_Pos)  /*!< 0x00400000 */
9843 #define RCC_APB1RSTR_I2C2RST               RCC_APB1RSTR_I2C2RST_Msk
9844 #define RCC_APB1RSTR_I2C3RST_Pos           (23U)
9845 #define RCC_APB1RSTR_I2C3RST_Msk           (0x1UL << RCC_APB1RSTR_I2C3RST_Pos)  /*!< 0x00800000 */
9846 #define RCC_APB1RSTR_I2C3RST               RCC_APB1RSTR_I2C3RST_Msk
9847 #define RCC_APB1RSTR_FMPI2C1RST_Pos        (24U)
9848 #define RCC_APB1RSTR_FMPI2C1RST_Msk        (0x1UL << RCC_APB1RSTR_FMPI2C1RST_Pos) /*!< 0x01000000 */
9849 #define RCC_APB1RSTR_FMPI2C1RST            RCC_APB1RSTR_FMPI2C1RST_Msk
9850 #define RCC_APB1RSTR_CAN1RST_Pos           (25U)
9851 #define RCC_APB1RSTR_CAN1RST_Msk           (0x1UL << RCC_APB1RSTR_CAN1RST_Pos)  /*!< 0x02000000 */
9852 #define RCC_APB1RSTR_CAN1RST               RCC_APB1RSTR_CAN1RST_Msk
9853 #define RCC_APB1RSTR_CAN2RST_Pos           (26U)
9854 #define RCC_APB1RSTR_CAN2RST_Msk           (0x1UL << RCC_APB1RSTR_CAN2RST_Pos)  /*!< 0x04000000 */
9855 #define RCC_APB1RSTR_CAN2RST               RCC_APB1RSTR_CAN2RST_Msk
9856 #define RCC_APB1RSTR_CAN3RST_Pos           (27U)
9857 #define RCC_APB1RSTR_CAN3RST_Msk           (0x1UL << RCC_APB1RSTR_CAN3RST_Pos)  /*!< 0x08000000 */
9858 #define RCC_APB1RSTR_CAN3RST               RCC_APB1RSTR_CAN3RST_Msk
9859 #define RCC_APB1RSTR_PWRRST_Pos            (28U)
9860 #define RCC_APB1RSTR_PWRRST_Msk            (0x1UL << RCC_APB1RSTR_PWRRST_Pos)   /*!< 0x10000000 */
9861 #define RCC_APB1RSTR_PWRRST                RCC_APB1RSTR_PWRRST_Msk
9862 #define RCC_APB1RSTR_DACRST_Pos            (29U)
9863 #define RCC_APB1RSTR_DACRST_Msk            (0x1UL << RCC_APB1RSTR_DACRST_Pos)   /*!< 0x20000000 */
9864 #define RCC_APB1RSTR_DACRST                RCC_APB1RSTR_DACRST_Msk
9865 #define RCC_APB1RSTR_UART7RST_Pos          (30U)
9866 #define RCC_APB1RSTR_UART7RST_Msk          (0x1UL << RCC_APB1RSTR_UART7RST_Pos) /*!< 0x40000000 */
9867 #define RCC_APB1RSTR_UART7RST              RCC_APB1RSTR_UART7RST_Msk
9868 #define RCC_APB1RSTR_UART8RST_Pos          (31U)
9869 #define RCC_APB1RSTR_UART8RST_Msk          (0x1UL << RCC_APB1RSTR_UART8RST_Pos) /*!< 0x80000000 */
9870 #define RCC_APB1RSTR_UART8RST              RCC_APB1RSTR_UART8RST_Msk
9871 
9872 /********************  Bit definition for RCC_APB2RSTR register  **************/
9873 #define RCC_APB2RSTR_TIM1RST_Pos           (0U)
9874 #define RCC_APB2RSTR_TIM1RST_Msk           (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)  /*!< 0x00000001 */
9875 #define RCC_APB2RSTR_TIM1RST               RCC_APB2RSTR_TIM1RST_Msk
9876 #define RCC_APB2RSTR_TIM8RST_Pos           (1U)
9877 #define RCC_APB2RSTR_TIM8RST_Msk           (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)  /*!< 0x00000002 */
9878 #define RCC_APB2RSTR_TIM8RST               RCC_APB2RSTR_TIM8RST_Msk
9879 #define RCC_APB2RSTR_USART1RST_Pos         (4U)
9880 #define RCC_APB2RSTR_USART1RST_Msk         (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
9881 #define RCC_APB2RSTR_USART1RST             RCC_APB2RSTR_USART1RST_Msk
9882 #define RCC_APB2RSTR_USART6RST_Pos         (5U)
9883 #define RCC_APB2RSTR_USART6RST_Msk         (0x1UL << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
9884 #define RCC_APB2RSTR_USART6RST             RCC_APB2RSTR_USART6RST_Msk
9885 #define RCC_APB2RSTR_UART9RST_Pos          (6U)
9886 #define RCC_APB2RSTR_UART9RST_Msk          (0x1UL << RCC_APB2RSTR_UART9RST_Pos) /*!< 0x00000040 */
9887 #define RCC_APB2RSTR_UART9RST              RCC_APB2RSTR_UART9RST_Msk
9888 #define RCC_APB2RSTR_UART10RST_Pos         (7U)
9889 #define RCC_APB2RSTR_UART10RST_Msk         (0x1UL << RCC_APB2RSTR_UART10RST_Pos) /*!< 0x00000080 */
9890 #define RCC_APB2RSTR_UART10RST             RCC_APB2RSTR_UART10RST_Msk
9891 #define RCC_APB2RSTR_ADCRST_Pos            (8U)
9892 #define RCC_APB2RSTR_ADCRST_Msk            (0x1UL << RCC_APB2RSTR_ADCRST_Pos)   /*!< 0x00000100 */
9893 #define RCC_APB2RSTR_ADCRST                RCC_APB2RSTR_ADCRST_Msk
9894 #define RCC_APB2RSTR_SDIORST_Pos           (11U)
9895 #define RCC_APB2RSTR_SDIORST_Msk           (0x1UL << RCC_APB2RSTR_SDIORST_Pos)  /*!< 0x00000800 */
9896 #define RCC_APB2RSTR_SDIORST               RCC_APB2RSTR_SDIORST_Msk
9897 #define RCC_APB2RSTR_SPI1RST_Pos           (12U)
9898 #define RCC_APB2RSTR_SPI1RST_Msk           (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)  /*!< 0x00001000 */
9899 #define RCC_APB2RSTR_SPI1RST               RCC_APB2RSTR_SPI1RST_Msk
9900 #define RCC_APB2RSTR_SPI4RST_Pos           (13U)
9901 #define RCC_APB2RSTR_SPI4RST_Msk           (0x1UL << RCC_APB2RSTR_SPI4RST_Pos)  /*!< 0x00002000 */
9902 #define RCC_APB2RSTR_SPI4RST               RCC_APB2RSTR_SPI4RST_Msk
9903 #define RCC_APB2RSTR_SYSCFGRST_Pos         (14U)
9904 #define RCC_APB2RSTR_SYSCFGRST_Msk         (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */
9905 #define RCC_APB2RSTR_SYSCFGRST             RCC_APB2RSTR_SYSCFGRST_Msk
9906 #define RCC_APB2RSTR_TIM9RST_Pos           (16U)
9907 #define RCC_APB2RSTR_TIM9RST_Msk           (0x1UL << RCC_APB2RSTR_TIM9RST_Pos)  /*!< 0x00010000 */
9908 #define RCC_APB2RSTR_TIM9RST               RCC_APB2RSTR_TIM9RST_Msk
9909 #define RCC_APB2RSTR_TIM10RST_Pos          (17U)
9910 #define RCC_APB2RSTR_TIM10RST_Msk          (0x1UL << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00020000 */
9911 #define RCC_APB2RSTR_TIM10RST              RCC_APB2RSTR_TIM10RST_Msk
9912 #define RCC_APB2RSTR_TIM11RST_Pos          (18U)
9913 #define RCC_APB2RSTR_TIM11RST_Msk          (0x1UL << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */
9914 #define RCC_APB2RSTR_TIM11RST              RCC_APB2RSTR_TIM11RST_Msk
9915 #define RCC_APB2RSTR_SPI5RST_Pos           (20U)
9916 #define RCC_APB2RSTR_SPI5RST_Msk           (0x1UL << RCC_APB2RSTR_SPI5RST_Pos)  /*!< 0x00100000 */
9917 #define RCC_APB2RSTR_SPI5RST               RCC_APB2RSTR_SPI5RST_Msk
9918 #define RCC_APB2RSTR_SAI1RST_Pos           (22U)
9919 #define RCC_APB2RSTR_SAI1RST_Msk           (0x1UL << RCC_APB2RSTR_SAI1RST_Pos)  /*!< 0x00400000 */
9920 #define RCC_APB2RSTR_SAI1RST               RCC_APB2RSTR_SAI1RST_Msk
9921 #define RCC_APB2RSTR_DFSDM1RST_Pos         (24U)
9922 #define RCC_APB2RSTR_DFSDM1RST_Msk         (0x1UL << RCC_APB2RSTR_DFSDM1RST_Pos) /*!< 0x01000000 */
9923 #define RCC_APB2RSTR_DFSDM1RST             RCC_APB2RSTR_DFSDM1RST_Msk
9924 #define RCC_APB2RSTR_DFSDM2RST_Pos         (25U)
9925 #define RCC_APB2RSTR_DFSDM2RST_Msk         (0x1UL << RCC_APB2RSTR_DFSDM2RST_Pos) /*!< 0x02000000 */
9926 #define RCC_APB2RSTR_DFSDM2RST             RCC_APB2RSTR_DFSDM2RST_Msk
9927 
9928 /********************  Bit definition for RCC_AHB1ENR register  ***************/
9929 #define RCC_AHB1ENR_GPIOAEN_Pos            (0U)
9930 #define RCC_AHB1ENR_GPIOAEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOAEN_Pos)   /*!< 0x00000001 */
9931 #define RCC_AHB1ENR_GPIOAEN                RCC_AHB1ENR_GPIOAEN_Msk
9932 #define RCC_AHB1ENR_GPIOBEN_Pos            (1U)
9933 #define RCC_AHB1ENR_GPIOBEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOBEN_Pos)   /*!< 0x00000002 */
9934 #define RCC_AHB1ENR_GPIOBEN                RCC_AHB1ENR_GPIOBEN_Msk
9935 #define RCC_AHB1ENR_GPIOCEN_Pos            (2U)
9936 #define RCC_AHB1ENR_GPIOCEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOCEN_Pos)   /*!< 0x00000004 */
9937 #define RCC_AHB1ENR_GPIOCEN                RCC_AHB1ENR_GPIOCEN_Msk
9938 #define RCC_AHB1ENR_GPIODEN_Pos            (3U)
9939 #define RCC_AHB1ENR_GPIODEN_Msk            (0x1UL << RCC_AHB1ENR_GPIODEN_Pos)   /*!< 0x00000008 */
9940 #define RCC_AHB1ENR_GPIODEN                RCC_AHB1ENR_GPIODEN_Msk
9941 #define RCC_AHB1ENR_GPIOEEN_Pos            (4U)
9942 #define RCC_AHB1ENR_GPIOEEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOEEN_Pos)   /*!< 0x00000010 */
9943 #define RCC_AHB1ENR_GPIOEEN                RCC_AHB1ENR_GPIOEEN_Msk
9944 #define RCC_AHB1ENR_GPIOFEN_Pos            (5U)
9945 #define RCC_AHB1ENR_GPIOFEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOFEN_Pos)   /*!< 0x00000020 */
9946 #define RCC_AHB1ENR_GPIOFEN                RCC_AHB1ENR_GPIOFEN_Msk
9947 #define RCC_AHB1ENR_GPIOGEN_Pos            (6U)
9948 #define RCC_AHB1ENR_GPIOGEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOGEN_Pos)   /*!< 0x00000040 */
9949 #define RCC_AHB1ENR_GPIOGEN                RCC_AHB1ENR_GPIOGEN_Msk
9950 #define RCC_AHB1ENR_GPIOHEN_Pos            (7U)
9951 #define RCC_AHB1ENR_GPIOHEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOHEN_Pos)   /*!< 0x00000080 */
9952 #define RCC_AHB1ENR_GPIOHEN                RCC_AHB1ENR_GPIOHEN_Msk
9953 #define RCC_AHB1ENR_CRCEN_Pos              (12U)
9954 #define RCC_AHB1ENR_CRCEN_Msk              (0x1UL << RCC_AHB1ENR_CRCEN_Pos)     /*!< 0x00001000 */
9955 #define RCC_AHB1ENR_CRCEN                  RCC_AHB1ENR_CRCEN_Msk
9956 #define RCC_AHB1ENR_DMA1EN_Pos             (21U)
9957 #define RCC_AHB1ENR_DMA1EN_Msk             (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)    /*!< 0x00200000 */
9958 #define RCC_AHB1ENR_DMA1EN                 RCC_AHB1ENR_DMA1EN_Msk
9959 #define RCC_AHB1ENR_DMA2EN_Pos             (22U)
9960 #define RCC_AHB1ENR_DMA2EN_Msk             (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)    /*!< 0x00400000 */
9961 #define RCC_AHB1ENR_DMA2EN                 RCC_AHB1ENR_DMA2EN_Msk
9962 /********************  Bit definition for RCC_AHB2ENR register  ***************/
9963 /*
9964  * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
9965  */
9966 #define RCC_AHB2_SUPPORT                   /*!< AHB2 Bus is supported */
9967 
9968 #define RCC_AHB2ENR_RNGEN_Pos              (6U)
9969 #define RCC_AHB2ENR_RNGEN_Msk              (0x1UL << RCC_AHB2ENR_RNGEN_Pos)     /*!< 0x00000040 */
9970 #define RCC_AHB2ENR_RNGEN                  RCC_AHB2ENR_RNGEN_Msk
9971 #define RCC_AHB2ENR_OTGFSEN_Pos            (7U)
9972 #define RCC_AHB2ENR_OTGFSEN_Msk            (0x1UL << RCC_AHB2ENR_OTGFSEN_Pos)   /*!< 0x00000080 */
9973 #define RCC_AHB2ENR_OTGFSEN                RCC_AHB2ENR_OTGFSEN_Msk
9974 
9975 /********************  Bit definition for RCC_AHB3ENR register  ***************/
9976 /*
9977  * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
9978  */
9979 #define RCC_AHB3_SUPPORT                   /*!< AHB3 Bus is supported */
9980 
9981 #define RCC_AHB3ENR_FSMCEN_Pos             (0U)
9982 #define RCC_AHB3ENR_FSMCEN_Msk             (0x1UL << RCC_AHB3ENR_FSMCEN_Pos)    /*!< 0x00000001 */
9983 #define RCC_AHB3ENR_FSMCEN                 RCC_AHB3ENR_FSMCEN_Msk
9984 #define RCC_AHB3ENR_QSPIEN_Pos             (1U)
9985 #define RCC_AHB3ENR_QSPIEN_Msk             (0x1UL << RCC_AHB3ENR_QSPIEN_Pos)    /*!< 0x00000002 */
9986 #define RCC_AHB3ENR_QSPIEN                 RCC_AHB3ENR_QSPIEN_Msk
9987 
9988 /********************  Bit definition for RCC_APB1ENR register  ***************/
9989 #define RCC_APB1ENR_TIM2EN_Pos             (0U)
9990 #define RCC_APB1ENR_TIM2EN_Msk             (0x1UL << RCC_APB1ENR_TIM2EN_Pos)    /*!< 0x00000001 */
9991 #define RCC_APB1ENR_TIM2EN                 RCC_APB1ENR_TIM2EN_Msk
9992 #define RCC_APB1ENR_TIM3EN_Pos             (1U)
9993 #define RCC_APB1ENR_TIM3EN_Msk             (0x1UL << RCC_APB1ENR_TIM3EN_Pos)    /*!< 0x00000002 */
9994 #define RCC_APB1ENR_TIM3EN                 RCC_APB1ENR_TIM3EN_Msk
9995 #define RCC_APB1ENR_TIM4EN_Pos             (2U)
9996 #define RCC_APB1ENR_TIM4EN_Msk             (0x1UL << RCC_APB1ENR_TIM4EN_Pos)    /*!< 0x00000004 */
9997 #define RCC_APB1ENR_TIM4EN                 RCC_APB1ENR_TIM4EN_Msk
9998 #define RCC_APB1ENR_TIM5EN_Pos             (3U)
9999 #define RCC_APB1ENR_TIM5EN_Msk             (0x1UL << RCC_APB1ENR_TIM5EN_Pos)    /*!< 0x00000008 */
10000 #define RCC_APB1ENR_TIM5EN                 RCC_APB1ENR_TIM5EN_Msk
10001 #define RCC_APB1ENR_TIM6EN_Pos             (4U)
10002 #define RCC_APB1ENR_TIM6EN_Msk             (0x1UL << RCC_APB1ENR_TIM6EN_Pos)    /*!< 0x00000010 */
10003 #define RCC_APB1ENR_TIM6EN                 RCC_APB1ENR_TIM6EN_Msk
10004 #define RCC_APB1ENR_TIM7EN_Pos             (5U)
10005 #define RCC_APB1ENR_TIM7EN_Msk             (0x1UL << RCC_APB1ENR_TIM7EN_Pos)    /*!< 0x00000020 */
10006 #define RCC_APB1ENR_TIM7EN                 RCC_APB1ENR_TIM7EN_Msk
10007 #define RCC_APB1ENR_TIM12EN_Pos            (6U)
10008 #define RCC_APB1ENR_TIM12EN_Msk            (0x1UL << RCC_APB1ENR_TIM12EN_Pos)   /*!< 0x00000040 */
10009 #define RCC_APB1ENR_TIM12EN                RCC_APB1ENR_TIM12EN_Msk
10010 #define RCC_APB1ENR_TIM13EN_Pos            (7U)
10011 #define RCC_APB1ENR_TIM13EN_Msk            (0x1UL << RCC_APB1ENR_TIM13EN_Pos)   /*!< 0x00000080 */
10012 #define RCC_APB1ENR_TIM13EN                RCC_APB1ENR_TIM13EN_Msk
10013 #define RCC_APB1ENR_TIM14EN_Pos            (8U)
10014 #define RCC_APB1ENR_TIM14EN_Msk            (0x1UL << RCC_APB1ENR_TIM14EN_Pos)   /*!< 0x00000100 */
10015 #define RCC_APB1ENR_TIM14EN                RCC_APB1ENR_TIM14EN_Msk
10016 #define RCC_APB1ENR_LPTIM1EN_Pos           (9U)
10017 #define RCC_APB1ENR_LPTIM1EN_Msk           (0x1UL << RCC_APB1ENR_LPTIM1EN_Pos)  /*!< 0x00000200 */
10018 #define RCC_APB1ENR_LPTIM1EN               RCC_APB1ENR_LPTIM1EN_Msk
10019 #define RCC_APB1ENR_RTCAPBEN_Pos           (10U)
10020 #define RCC_APB1ENR_RTCAPBEN_Msk           (0x1UL << RCC_APB1ENR_RTCAPBEN_Pos)  /*!< 0x00000400 */
10021 #define RCC_APB1ENR_RTCAPBEN               RCC_APB1ENR_RTCAPBEN_Msk
10022 #define RCC_APB1ENR_WWDGEN_Pos             (11U)
10023 #define RCC_APB1ENR_WWDGEN_Msk             (0x1UL << RCC_APB1ENR_WWDGEN_Pos)    /*!< 0x00000800 */
10024 #define RCC_APB1ENR_WWDGEN                 RCC_APB1ENR_WWDGEN_Msk
10025 #define RCC_APB1ENR_SPI2EN_Pos             (14U)
10026 #define RCC_APB1ENR_SPI2EN_Msk             (0x1UL << RCC_APB1ENR_SPI2EN_Pos)    /*!< 0x00004000 */
10027 #define RCC_APB1ENR_SPI2EN                 RCC_APB1ENR_SPI2EN_Msk
10028 #define RCC_APB1ENR_SPI3EN_Pos             (15U)
10029 #define RCC_APB1ENR_SPI3EN_Msk             (0x1UL << RCC_APB1ENR_SPI3EN_Pos)    /*!< 0x00008000 */
10030 #define RCC_APB1ENR_SPI3EN                 RCC_APB1ENR_SPI3EN_Msk
10031 #define RCC_APB1ENR_USART2EN_Pos           (17U)
10032 #define RCC_APB1ENR_USART2EN_Msk           (0x1UL << RCC_APB1ENR_USART2EN_Pos)  /*!< 0x00020000 */
10033 #define RCC_APB1ENR_USART2EN               RCC_APB1ENR_USART2EN_Msk
10034 #define RCC_APB1ENR_USART3EN_Pos           (18U)
10035 #define RCC_APB1ENR_USART3EN_Msk           (0x1UL << RCC_APB1ENR_USART3EN_Pos)  /*!< 0x00040000 */
10036 #define RCC_APB1ENR_USART3EN               RCC_APB1ENR_USART3EN_Msk
10037 #define RCC_APB1ENR_UART4EN_Pos            (19U)
10038 #define RCC_APB1ENR_UART4EN_Msk            (0x1UL << RCC_APB1ENR_UART4EN_Pos)   /*!< 0x00080000 */
10039 #define RCC_APB1ENR_UART4EN                RCC_APB1ENR_UART4EN_Msk
10040 #define RCC_APB1ENR_UART5EN_Pos            (20U)
10041 #define RCC_APB1ENR_UART5EN_Msk            (0x1UL << RCC_APB1ENR_UART5EN_Pos)   /*!< 0x00100000 */
10042 #define RCC_APB1ENR_UART5EN                RCC_APB1ENR_UART5EN_Msk
10043 #define RCC_APB1ENR_I2C1EN_Pos             (21U)
10044 #define RCC_APB1ENR_I2C1EN_Msk             (0x1UL << RCC_APB1ENR_I2C1EN_Pos)    /*!< 0x00200000 */
10045 #define RCC_APB1ENR_I2C1EN                 RCC_APB1ENR_I2C1EN_Msk
10046 #define RCC_APB1ENR_I2C2EN_Pos             (22U)
10047 #define RCC_APB1ENR_I2C2EN_Msk             (0x1UL << RCC_APB1ENR_I2C2EN_Pos)    /*!< 0x00400000 */
10048 #define RCC_APB1ENR_I2C2EN                 RCC_APB1ENR_I2C2EN_Msk
10049 #define RCC_APB1ENR_I2C3EN_Pos             (23U)
10050 #define RCC_APB1ENR_I2C3EN_Msk             (0x1UL << RCC_APB1ENR_I2C3EN_Pos)    /*!< 0x00800000 */
10051 #define RCC_APB1ENR_I2C3EN                 RCC_APB1ENR_I2C3EN_Msk
10052 #define RCC_APB1ENR_FMPI2C1EN_Pos          (24U)
10053 #define RCC_APB1ENR_FMPI2C1EN_Msk          (0x1UL << RCC_APB1ENR_FMPI2C1EN_Pos) /*!< 0x01000000 */
10054 #define RCC_APB1ENR_FMPI2C1EN              RCC_APB1ENR_FMPI2C1EN_Msk
10055 #define RCC_APB1ENR_CAN1EN_Pos             (25U)
10056 #define RCC_APB1ENR_CAN1EN_Msk             (0x1UL << RCC_APB1ENR_CAN1EN_Pos)    /*!< 0x02000000 */
10057 #define RCC_APB1ENR_CAN1EN                 RCC_APB1ENR_CAN1EN_Msk
10058 #define RCC_APB1ENR_CAN2EN_Pos             (26U)
10059 #define RCC_APB1ENR_CAN2EN_Msk             (0x1UL << RCC_APB1ENR_CAN2EN_Pos)    /*!< 0x04000000 */
10060 #define RCC_APB1ENR_CAN2EN                 RCC_APB1ENR_CAN2EN_Msk
10061 #define RCC_APB1ENR_CAN3EN_Pos             (27U)
10062 #define RCC_APB1ENR_CAN3EN_Msk             (0x1UL << RCC_APB1ENR_CAN3EN_Pos)    /*!< 0x08000000 */
10063 #define RCC_APB1ENR_CAN3EN                 RCC_APB1ENR_CAN3EN_Msk
10064 #define RCC_APB1ENR_PWREN_Pos              (28U)
10065 #define RCC_APB1ENR_PWREN_Msk              (0x1UL << RCC_APB1ENR_PWREN_Pos)     /*!< 0x10000000 */
10066 #define RCC_APB1ENR_PWREN                  RCC_APB1ENR_PWREN_Msk
10067 #define RCC_APB1ENR_DACEN_Pos              (29U)
10068 #define RCC_APB1ENR_DACEN_Msk              (0x1UL << RCC_APB1ENR_DACEN_Pos)     /*!< 0x20000000 */
10069 #define RCC_APB1ENR_DACEN                  RCC_APB1ENR_DACEN_Msk
10070 #define RCC_APB1ENR_UART7EN_Pos            (30U)
10071 #define RCC_APB1ENR_UART7EN_Msk            (0x1UL << RCC_APB1ENR_UART7EN_Pos)   /*!< 0x40000000 */
10072 #define RCC_APB1ENR_UART7EN                RCC_APB1ENR_UART7EN_Msk
10073 #define RCC_APB1ENR_UART8EN_Pos            (31U)
10074 #define RCC_APB1ENR_UART8EN_Msk            (0x1UL << RCC_APB1ENR_UART8EN_Pos)   /*!< 0x80000000 */
10075 #define RCC_APB1ENR_UART8EN                RCC_APB1ENR_UART8EN_Msk
10076 
10077 /********************  Bit definition for RCC_APB2ENR register  ***************/
10078 #define RCC_APB2ENR_TIM1EN_Pos             (0U)
10079 #define RCC_APB2ENR_TIM1EN_Msk             (0x1UL << RCC_APB2ENR_TIM1EN_Pos)    /*!< 0x00000001 */
10080 #define RCC_APB2ENR_TIM1EN                 RCC_APB2ENR_TIM1EN_Msk
10081 #define RCC_APB2ENR_TIM8EN_Pos             (1U)
10082 #define RCC_APB2ENR_TIM8EN_Msk             (0x1UL << RCC_APB2ENR_TIM8EN_Pos)    /*!< 0x00000002 */
10083 #define RCC_APB2ENR_TIM8EN                 RCC_APB2ENR_TIM8EN_Msk
10084 #define RCC_APB2ENR_USART1EN_Pos           (4U)
10085 #define RCC_APB2ENR_USART1EN_Msk           (0x1UL << RCC_APB2ENR_USART1EN_Pos)  /*!< 0x00000010 */
10086 #define RCC_APB2ENR_USART1EN               RCC_APB2ENR_USART1EN_Msk
10087 #define RCC_APB2ENR_USART6EN_Pos           (5U)
10088 #define RCC_APB2ENR_USART6EN_Msk           (0x1UL << RCC_APB2ENR_USART6EN_Pos)  /*!< 0x00000020 */
10089 #define RCC_APB2ENR_USART6EN               RCC_APB2ENR_USART6EN_Msk
10090 #define RCC_APB2ENR_UART9EN_Pos            (6U)
10091 #define RCC_APB2ENR_UART9EN_Msk            (0x1UL << RCC_APB2ENR_UART9EN_Pos)   /*!< 0x00000040 */
10092 #define RCC_APB2ENR_UART9EN                RCC_APB2ENR_UART9EN_Msk
10093 #define RCC_APB2ENR_UART10EN_Pos           (7U)
10094 #define RCC_APB2ENR_UART10EN_Msk           (0x1UL << RCC_APB2ENR_UART10EN_Pos)  /*!< 0x00000080 */
10095 #define RCC_APB2ENR_UART10EN               RCC_APB2ENR_UART10EN_Msk
10096 #define RCC_APB2ENR_ADC1EN_Pos             (8U)
10097 #define RCC_APB2ENR_ADC1EN_Msk             (0x1UL << RCC_APB2ENR_ADC1EN_Pos)    /*!< 0x00000100 */
10098 #define RCC_APB2ENR_ADC1EN                 RCC_APB2ENR_ADC1EN_Msk
10099 #define RCC_APB2ENR_SDIOEN_Pos             (11U)
10100 #define RCC_APB2ENR_SDIOEN_Msk             (0x1UL << RCC_APB2ENR_SDIOEN_Pos)    /*!< 0x00000800 */
10101 #define RCC_APB2ENR_SDIOEN                 RCC_APB2ENR_SDIOEN_Msk
10102 #define RCC_APB2ENR_SPI1EN_Pos             (12U)
10103 #define RCC_APB2ENR_SPI1EN_Msk             (0x1UL << RCC_APB2ENR_SPI1EN_Pos)    /*!< 0x00001000 */
10104 #define RCC_APB2ENR_SPI1EN                 RCC_APB2ENR_SPI1EN_Msk
10105 #define RCC_APB2ENR_SPI4EN_Pos             (13U)
10106 #define RCC_APB2ENR_SPI4EN_Msk             (0x1UL << RCC_APB2ENR_SPI4EN_Pos)    /*!< 0x00002000 */
10107 #define RCC_APB2ENR_SPI4EN                 RCC_APB2ENR_SPI4EN_Msk
10108 #define RCC_APB2ENR_SYSCFGEN_Pos           (14U)
10109 #define RCC_APB2ENR_SYSCFGEN_Msk           (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)  /*!< 0x00004000 */
10110 #define RCC_APB2ENR_SYSCFGEN               RCC_APB2ENR_SYSCFGEN_Msk
10111 #define RCC_APB2ENR_EXTITEN_Pos            (15U)
10112 #define RCC_APB2ENR_EXTITEN_Msk            (0x1UL << RCC_APB2ENR_EXTITEN_Pos)   /*!< 0x00008000 */
10113 #define RCC_APB2ENR_EXTITEN                RCC_APB2ENR_EXTITEN_Msk
10114 #define RCC_APB2ENR_TIM9EN_Pos             (16U)
10115 #define RCC_APB2ENR_TIM9EN_Msk             (0x1UL << RCC_APB2ENR_TIM9EN_Pos)    /*!< 0x00010000 */
10116 #define RCC_APB2ENR_TIM9EN                 RCC_APB2ENR_TIM9EN_Msk
10117 #define RCC_APB2ENR_TIM10EN_Pos            (17U)
10118 #define RCC_APB2ENR_TIM10EN_Msk            (0x1UL << RCC_APB2ENR_TIM10EN_Pos)   /*!< 0x00020000 */
10119 #define RCC_APB2ENR_TIM10EN                RCC_APB2ENR_TIM10EN_Msk
10120 #define RCC_APB2ENR_TIM11EN_Pos            (18U)
10121 #define RCC_APB2ENR_TIM11EN_Msk            (0x1UL << RCC_APB2ENR_TIM11EN_Pos)   /*!< 0x00040000 */
10122 #define RCC_APB2ENR_TIM11EN                RCC_APB2ENR_TIM11EN_Msk
10123 #define RCC_APB2ENR_SPI5EN_Pos             (20U)
10124 #define RCC_APB2ENR_SPI5EN_Msk             (0x1UL << RCC_APB2ENR_SPI5EN_Pos)    /*!< 0x00100000 */
10125 #define RCC_APB2ENR_SPI5EN                 RCC_APB2ENR_SPI5EN_Msk
10126 #define RCC_APB2ENR_SAI1EN_Pos             (22U)
10127 #define RCC_APB2ENR_SAI1EN_Msk             (0x1UL << RCC_APB2ENR_SAI1EN_Pos)    /*!< 0x00400000 */
10128 #define RCC_APB2ENR_SAI1EN                 RCC_APB2ENR_SAI1EN_Msk
10129 #define RCC_APB2ENR_DFSDM1EN_Pos           (24U)
10130 #define RCC_APB2ENR_DFSDM1EN_Msk           (0x1UL << RCC_APB2ENR_DFSDM1EN_Pos)  /*!< 0x01000000 */
10131 #define RCC_APB2ENR_DFSDM1EN               RCC_APB2ENR_DFSDM1EN_Msk
10132 #define RCC_APB2ENR_DFSDM2EN_Pos           (25U)
10133 #define RCC_APB2ENR_DFSDM2EN_Msk           (0x1UL << RCC_APB2ENR_DFSDM2EN_Pos)  /*!< 0x02000000 */
10134 #define RCC_APB2ENR_DFSDM2EN               RCC_APB2ENR_DFSDM2EN_Msk
10135 
10136 /********************  Bit definition for RCC_AHB1LPENR register  *************/
10137 #define RCC_AHB1LPENR_GPIOALPEN_Pos        (0U)
10138 #define RCC_AHB1LPENR_GPIOALPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
10139 #define RCC_AHB1LPENR_GPIOALPEN            RCC_AHB1LPENR_GPIOALPEN_Msk
10140 #define RCC_AHB1LPENR_GPIOBLPEN_Pos        (1U)
10141 #define RCC_AHB1LPENR_GPIOBLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
10142 #define RCC_AHB1LPENR_GPIOBLPEN            RCC_AHB1LPENR_GPIOBLPEN_Msk
10143 #define RCC_AHB1LPENR_GPIOCLPEN_Pos        (2U)
10144 #define RCC_AHB1LPENR_GPIOCLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
10145 #define RCC_AHB1LPENR_GPIOCLPEN            RCC_AHB1LPENR_GPIOCLPEN_Msk
10146 #define RCC_AHB1LPENR_GPIODLPEN_Pos        (3U)
10147 #define RCC_AHB1LPENR_GPIODLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
10148 #define RCC_AHB1LPENR_GPIODLPEN            RCC_AHB1LPENR_GPIODLPEN_Msk
10149 #define RCC_AHB1LPENR_GPIOELPEN_Pos        (4U)
10150 #define RCC_AHB1LPENR_GPIOELPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
10151 #define RCC_AHB1LPENR_GPIOELPEN            RCC_AHB1LPENR_GPIOELPEN_Msk
10152 #define RCC_AHB1LPENR_GPIOFLPEN_Pos        (5U)
10153 #define RCC_AHB1LPENR_GPIOFLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */
10154 #define RCC_AHB1LPENR_GPIOFLPEN            RCC_AHB1LPENR_GPIOFLPEN_Msk
10155 #define RCC_AHB1LPENR_GPIOGLPEN_Pos        (6U)
10156 #define RCC_AHB1LPENR_GPIOGLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */
10157 #define RCC_AHB1LPENR_GPIOGLPEN            RCC_AHB1LPENR_GPIOGLPEN_Msk
10158 #define RCC_AHB1LPENR_GPIOHLPEN_Pos        (7U)
10159 #define RCC_AHB1LPENR_GPIOHLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */
10160 #define RCC_AHB1LPENR_GPIOHLPEN            RCC_AHB1LPENR_GPIOHLPEN_Msk
10161 #define RCC_AHB1LPENR_CRCLPEN_Pos          (12U)
10162 #define RCC_AHB1LPENR_CRCLPEN_Msk          (0x1UL << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */
10163 #define RCC_AHB1LPENR_CRCLPEN              RCC_AHB1LPENR_CRCLPEN_Msk
10164 #define RCC_AHB1LPENR_FLITFLPEN_Pos        (15U)
10165 #define RCC_AHB1LPENR_FLITFLPEN_Msk        (0x1UL << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
10166 #define RCC_AHB1LPENR_FLITFLPEN            RCC_AHB1LPENR_FLITFLPEN_Msk
10167 #define RCC_AHB1LPENR_SRAM1LPEN_Pos        (16U)
10168 #define RCC_AHB1LPENR_SRAM1LPEN_Msk        (0x1UL << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */
10169 #define RCC_AHB1LPENR_SRAM1LPEN            RCC_AHB1LPENR_SRAM1LPEN_Msk
10170 #define RCC_AHB1LPENR_SRAM2LPEN_Pos        (17U)
10171 #define RCC_AHB1LPENR_SRAM2LPEN_Msk        (0x1UL << RCC_AHB1LPENR_SRAM2LPEN_Pos) /*!< 0x00020000 */
10172 #define RCC_AHB1LPENR_SRAM2LPEN            RCC_AHB1LPENR_SRAM2LPEN_Msk
10173 #define RCC_AHB1LPENR_DMA1LPEN_Pos         (21U)
10174 #define RCC_AHB1LPENR_DMA1LPEN_Msk         (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */
10175 #define RCC_AHB1LPENR_DMA1LPEN             RCC_AHB1LPENR_DMA1LPEN_Msk
10176 #define RCC_AHB1LPENR_DMA2LPEN_Pos         (22U)
10177 #define RCC_AHB1LPENR_DMA2LPEN_Msk         (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */
10178 #define RCC_AHB1LPENR_DMA2LPEN             RCC_AHB1LPENR_DMA2LPEN_Msk
10179 
10180 
10181 /********************  Bit definition for RCC_AHB2LPENR register  *************/
10182 #define RCC_AHB2LPENR_RNGLPEN_Pos          (6U)
10183 #define RCC_AHB2LPENR_RNGLPEN_Msk          (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */
10184 #define RCC_AHB2LPENR_RNGLPEN              RCC_AHB2LPENR_RNGLPEN_Msk
10185 #define RCC_AHB2LPENR_OTGFSLPEN_Pos        (7U)
10186 #define RCC_AHB2LPENR_OTGFSLPEN_Msk        (0x1UL << RCC_AHB2LPENR_OTGFSLPEN_Pos) /*!< 0x00000080 */
10187 #define RCC_AHB2LPENR_OTGFSLPEN            RCC_AHB2LPENR_OTGFSLPEN_Msk
10188 
10189 /********************  Bit definition for RCC_AHB3LPENR register  *************/
10190 #define RCC_AHB3LPENR_FSMCLPEN_Pos         (0U)
10191 #define RCC_AHB3LPENR_FSMCLPEN_Msk         (0x1UL << RCC_AHB3LPENR_FSMCLPEN_Pos) /*!< 0x00000001 */
10192 #define RCC_AHB3LPENR_FSMCLPEN             RCC_AHB3LPENR_FSMCLPEN_Msk
10193 #define RCC_AHB3LPENR_QSPILPEN_Pos         (1U)
10194 #define RCC_AHB3LPENR_QSPILPEN_Msk         (0x1UL << RCC_AHB3LPENR_QSPILPEN_Pos) /*!< 0x00000002 */
10195 #define RCC_AHB3LPENR_QSPILPEN             RCC_AHB3LPENR_QSPILPEN_Msk
10196 
10197 /********************  Bit definition for RCC_APB1LPENR register  *************/
10198 #define RCC_APB1LPENR_TIM2LPEN_Pos         (0U)
10199 #define RCC_APB1LPENR_TIM2LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
10200 #define RCC_APB1LPENR_TIM2LPEN             RCC_APB1LPENR_TIM2LPEN_Msk
10201 #define RCC_APB1LPENR_TIM3LPEN_Pos         (1U)
10202 #define RCC_APB1LPENR_TIM3LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
10203 #define RCC_APB1LPENR_TIM3LPEN             RCC_APB1LPENR_TIM3LPEN_Msk
10204 #define RCC_APB1LPENR_TIM4LPEN_Pos         (2U)
10205 #define RCC_APB1LPENR_TIM4LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
10206 #define RCC_APB1LPENR_TIM4LPEN             RCC_APB1LPENR_TIM4LPEN_Msk
10207 #define RCC_APB1LPENR_TIM5LPEN_Pos         (3U)
10208 #define RCC_APB1LPENR_TIM5LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
10209 #define RCC_APB1LPENR_TIM5LPEN             RCC_APB1LPENR_TIM5LPEN_Msk
10210 #define RCC_APB1LPENR_TIM6LPEN_Pos         (4U)
10211 #define RCC_APB1LPENR_TIM6LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
10212 #define RCC_APB1LPENR_TIM6LPEN             RCC_APB1LPENR_TIM6LPEN_Msk
10213 #define RCC_APB1LPENR_TIM7LPEN_Pos         (5U)
10214 #define RCC_APB1LPENR_TIM7LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
10215 #define RCC_APB1LPENR_TIM7LPEN             RCC_APB1LPENR_TIM7LPEN_Msk
10216 #define RCC_APB1LPENR_TIM12LPEN_Pos        (6U)
10217 #define RCC_APB1LPENR_TIM12LPEN_Msk        (0x1UL << RCC_APB1LPENR_TIM12LPEN_Pos) /*!< 0x00000040 */
10218 #define RCC_APB1LPENR_TIM12LPEN            RCC_APB1LPENR_TIM12LPEN_Msk
10219 #define RCC_APB1LPENR_TIM13LPEN_Pos        (7U)
10220 #define RCC_APB1LPENR_TIM13LPEN_Msk        (0x1UL << RCC_APB1LPENR_TIM13LPEN_Pos) /*!< 0x00000080 */
10221 #define RCC_APB1LPENR_TIM13LPEN            RCC_APB1LPENR_TIM13LPEN_Msk
10222 #define RCC_APB1LPENR_TIM14LPEN_Pos        (8U)
10223 #define RCC_APB1LPENR_TIM14LPEN_Msk        (0x1UL << RCC_APB1LPENR_TIM14LPEN_Pos) /*!< 0x00000100 */
10224 #define RCC_APB1LPENR_TIM14LPEN            RCC_APB1LPENR_TIM14LPEN_Msk
10225 #define RCC_APB1LPENR_LPTIM1LPEN_Pos       (9U)
10226 #define RCC_APB1LPENR_LPTIM1LPEN_Msk       (0x1UL << RCC_APB1LPENR_LPTIM1LPEN_Pos) /*!< 0x00000200 */
10227 #define RCC_APB1LPENR_LPTIM1LPEN           RCC_APB1LPENR_LPTIM1LPEN_Msk
10228 #define RCC_APB1LPENR_RTCAPBLPEN_Pos       (10U)
10229 #define RCC_APB1LPENR_RTCAPBLPEN_Msk       (0x1UL << RCC_APB1LPENR_RTCAPBLPEN_Pos) /*!< 0x00000400 */
10230 #define RCC_APB1LPENR_RTCAPBLPEN           RCC_APB1LPENR_RTCAPBLPEN_Msk
10231 #define RCC_APB1LPENR_WWDGLPEN_Pos         (11U)
10232 #define RCC_APB1LPENR_WWDGLPEN_Msk         (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
10233 #define RCC_APB1LPENR_WWDGLPEN             RCC_APB1LPENR_WWDGLPEN_Msk
10234 #define RCC_APB1LPENR_SPI2LPEN_Pos         (14U)
10235 #define RCC_APB1LPENR_SPI2LPEN_Msk         (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
10236 #define RCC_APB1LPENR_SPI2LPEN             RCC_APB1LPENR_SPI2LPEN_Msk
10237 #define RCC_APB1LPENR_SPI3LPEN_Pos         (15U)
10238 #define RCC_APB1LPENR_SPI3LPEN_Msk         (0x1UL << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
10239 #define RCC_APB1LPENR_SPI3LPEN             RCC_APB1LPENR_SPI3LPEN_Msk
10240 #define RCC_APB1LPENR_USART2LPEN_Pos       (17U)
10241 #define RCC_APB1LPENR_USART2LPEN_Msk       (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
10242 #define RCC_APB1LPENR_USART2LPEN           RCC_APB1LPENR_USART2LPEN_Msk
10243 #define RCC_APB1LPENR_USART3LPEN_Pos       (18U)
10244 #define RCC_APB1LPENR_USART3LPEN_Msk       (0x1UL << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */
10245 #define RCC_APB1LPENR_USART3LPEN           RCC_APB1LPENR_USART3LPEN_Msk
10246 #define RCC_APB1LPENR_UART4LPEN_Pos        (19U)
10247 #define RCC_APB1LPENR_UART4LPEN_Msk        (0x1UL << RCC_APB1LPENR_UART4LPEN_Pos) /*!< 0x00080000 */
10248 #define RCC_APB1LPENR_UART4LPEN            RCC_APB1LPENR_UART4LPEN_Msk
10249 #define RCC_APB1LPENR_UART5LPEN_Pos        (20U)
10250 #define RCC_APB1LPENR_UART5LPEN_Msk        (0x1UL << RCC_APB1LPENR_UART5LPEN_Pos) /*!< 0x00100000 */
10251 #define RCC_APB1LPENR_UART5LPEN            RCC_APB1LPENR_UART5LPEN_Msk
10252 #define RCC_APB1LPENR_I2C1LPEN_Pos         (21U)
10253 #define RCC_APB1LPENR_I2C1LPEN_Msk         (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
10254 #define RCC_APB1LPENR_I2C1LPEN             RCC_APB1LPENR_I2C1LPEN_Msk
10255 #define RCC_APB1LPENR_I2C2LPEN_Pos         (22U)
10256 #define RCC_APB1LPENR_I2C2LPEN_Msk         (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
10257 #define RCC_APB1LPENR_I2C2LPEN             RCC_APB1LPENR_I2C2LPEN_Msk
10258 #define RCC_APB1LPENR_I2C3LPEN_Pos         (23U)
10259 #define RCC_APB1LPENR_I2C3LPEN_Msk         (0x1UL << RCC_APB1LPENR_I2C3LPEN_Pos) /*!< 0x00800000 */
10260 #define RCC_APB1LPENR_I2C3LPEN             RCC_APB1LPENR_I2C3LPEN_Msk
10261 #define RCC_APB1LPENR_FMPI2C1LPEN_Pos      (24U)
10262 #define RCC_APB1LPENR_FMPI2C1LPEN_Msk      (0x1UL << RCC_APB1LPENR_FMPI2C1LPEN_Pos) /*!< 0x01000000 */
10263 #define RCC_APB1LPENR_FMPI2C1LPEN          RCC_APB1LPENR_FMPI2C1LPEN_Msk
10264 #define RCC_APB1LPENR_CAN1LPEN_Pos         (25U)
10265 #define RCC_APB1LPENR_CAN1LPEN_Msk         (0x1UL << RCC_APB1LPENR_CAN1LPEN_Pos) /*!< 0x02000000 */
10266 #define RCC_APB1LPENR_CAN1LPEN             RCC_APB1LPENR_CAN1LPEN_Msk
10267 #define RCC_APB1LPENR_CAN2LPEN_Pos         (26U)
10268 #define RCC_APB1LPENR_CAN2LPEN_Msk         (0x1UL << RCC_APB1LPENR_CAN2LPEN_Pos) /*!< 0x04000000 */
10269 #define RCC_APB1LPENR_CAN2LPEN             RCC_APB1LPENR_CAN2LPEN_Msk
10270 #define RCC_APB1LPENR_CAN3LPEN_Pos         (27U)
10271 #define RCC_APB1LPENR_CAN3LPEN_Msk         (0x1UL << RCC_APB1LPENR_CAN3LPEN_Pos) /*!< 0x08000000 */
10272 #define RCC_APB1LPENR_CAN3LPEN             RCC_APB1LPENR_CAN3LPEN_Msk
10273 #define RCC_APB1LPENR_PWRLPEN_Pos          (28U)
10274 #define RCC_APB1LPENR_PWRLPEN_Msk          (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
10275 #define RCC_APB1LPENR_PWRLPEN              RCC_APB1LPENR_PWRLPEN_Msk
10276 #define RCC_APB1LPENR_DACLPEN_Pos          (29U)
10277 #define RCC_APB1LPENR_DACLPEN_Msk          (0x1UL << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */
10278 #define RCC_APB1LPENR_DACLPEN              RCC_APB1LPENR_DACLPEN_Msk
10279 #define RCC_APB1LPENR_UART7LPEN_Pos        (30U)
10280 #define RCC_APB1LPENR_UART7LPEN_Msk        (0x1UL << RCC_APB1LPENR_UART7LPEN_Pos) /*!< 0x40000000 */
10281 #define RCC_APB1LPENR_UART7LPEN            RCC_APB1LPENR_UART7LPEN_Msk
10282 #define RCC_APB1LPENR_UART8LPEN_Pos        (31U)
10283 #define RCC_APB1LPENR_UART8LPEN_Msk        (0x1UL << RCC_APB1LPENR_UART8LPEN_Pos) /*!< 0x80000000 */
10284 #define RCC_APB1LPENR_UART8LPEN            RCC_APB1LPENR_UART8LPEN_Msk
10285 
10286 /********************  Bit definition for RCC_APB2LPENR register  *************/
10287 #define RCC_APB2LPENR_TIM1LPEN_Pos         (0U)
10288 #define RCC_APB2LPENR_TIM1LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
10289 #define RCC_APB2LPENR_TIM1LPEN             RCC_APB2LPENR_TIM1LPEN_Msk
10290 #define RCC_APB2LPENR_TIM8LPEN_Pos         (1U)
10291 #define RCC_APB2LPENR_TIM8LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */
10292 #define RCC_APB2LPENR_TIM8LPEN             RCC_APB2LPENR_TIM8LPEN_Msk
10293 #define RCC_APB2LPENR_USART1LPEN_Pos       (4U)
10294 #define RCC_APB2LPENR_USART1LPEN_Msk       (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
10295 #define RCC_APB2LPENR_USART1LPEN           RCC_APB2LPENR_USART1LPEN_Msk
10296 #define RCC_APB2LPENR_USART6LPEN_Pos       (5U)
10297 #define RCC_APB2LPENR_USART6LPEN_Msk       (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
10298 #define RCC_APB2LPENR_USART6LPEN           RCC_APB2LPENR_USART6LPEN_Msk
10299 #define RCC_APB2LPENR_UART9LPEN_Pos        (6U)
10300 #define RCC_APB2LPENR_UART9LPEN_Msk        (0x1UL << RCC_APB2LPENR_UART9LPEN_Pos) /*!< 0x00000040 */
10301 #define RCC_APB2LPENR_UART9LPEN            RCC_APB2LPENR_UART9LPEN_Msk
10302 #define RCC_APB2LPENR_UART10LPEN_Pos       (7U)
10303 #define RCC_APB2LPENR_UART10LPEN_Msk       (0x1UL << RCC_APB2LPENR_UART10LPEN_Pos) /*!< 0x00000080 */
10304 #define RCC_APB2LPENR_UART10LPEN           RCC_APB2LPENR_UART10LPEN_Msk
10305 #define RCC_APB2LPENR_ADC1LPEN_Pos         (8U)
10306 #define RCC_APB2LPENR_ADC1LPEN_Msk         (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */
10307 #define RCC_APB2LPENR_ADC1LPEN             RCC_APB2LPENR_ADC1LPEN_Msk
10308 #define RCC_APB2LPENR_SDIOLPEN_Pos         (11U)
10309 #define RCC_APB2LPENR_SDIOLPEN_Msk         (0x1UL << RCC_APB2LPENR_SDIOLPEN_Pos) /*!< 0x00000800 */
10310 #define RCC_APB2LPENR_SDIOLPEN             RCC_APB2LPENR_SDIOLPEN_Msk
10311 #define RCC_APB2LPENR_SPI1LPEN_Pos         (12U)
10312 #define RCC_APB2LPENR_SPI1LPEN_Msk         (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
10313 #define RCC_APB2LPENR_SPI1LPEN             RCC_APB2LPENR_SPI1LPEN_Msk
10314 #define RCC_APB2LPENR_SPI4LPEN_Pos         (13U)
10315 #define RCC_APB2LPENR_SPI4LPEN_Msk         (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */
10316 #define RCC_APB2LPENR_SPI4LPEN             RCC_APB2LPENR_SPI4LPEN_Msk
10317 #define RCC_APB2LPENR_SYSCFGLPEN_Pos       (14U)
10318 #define RCC_APB2LPENR_SYSCFGLPEN_Msk       (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */
10319 #define RCC_APB2LPENR_SYSCFGLPEN           RCC_APB2LPENR_SYSCFGLPEN_Msk
10320 #define RCC_APB2LPENR_EXTITLPEN_Pos        (15U)
10321 #define RCC_APB2LPENR_EXTITLPEN_Msk        (0x1UL << RCC_APB2LPENR_EXTITLPEN_Pos) /*!< 0x00008000 */
10322 #define RCC_APB2LPENR_EXTITLPEN            RCC_APB2LPENR_EXTITLPEN_Msk
10323 #define RCC_APB2LPENR_TIM9LPEN_Pos         (16U)
10324 #define RCC_APB2LPENR_TIM9LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */
10325 #define RCC_APB2LPENR_TIM9LPEN             RCC_APB2LPENR_TIM9LPEN_Msk
10326 #define RCC_APB2LPENR_TIM10LPEN_Pos        (17U)
10327 #define RCC_APB2LPENR_TIM10LPEN_Msk        (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00020000 */
10328 #define RCC_APB2LPENR_TIM10LPEN            RCC_APB2LPENR_TIM10LPEN_Msk
10329 #define RCC_APB2LPENR_TIM11LPEN_Pos        (18U)
10330 #define RCC_APB2LPENR_TIM11LPEN_Msk        (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */
10331 #define RCC_APB2LPENR_TIM11LPEN            RCC_APB2LPENR_TIM11LPEN_Msk
10332 #define RCC_APB2LPENR_SPI5LPEN_Pos         (20U)
10333 #define RCC_APB2LPENR_SPI5LPEN_Msk         (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */
10334 #define RCC_APB2LPENR_SPI5LPEN             RCC_APB2LPENR_SPI5LPEN_Msk
10335 #define RCC_APB2LPENR_SAI1LPEN_Pos         (22U)
10336 #define RCC_APB2LPENR_SAI1LPEN_Msk         (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */
10337 #define RCC_APB2LPENR_SAI1LPEN             RCC_APB2LPENR_SAI1LPEN_Msk
10338 #define RCC_APB2LPENR_DFSDM1LPEN_Pos       (24U)
10339 #define RCC_APB2LPENR_DFSDM1LPEN_Msk       (0x1UL << RCC_APB2LPENR_DFSDM1LPEN_Pos) /*!< 0x01000000 */
10340 #define RCC_APB2LPENR_DFSDM1LPEN           RCC_APB2LPENR_DFSDM1LPEN_Msk
10341 #define RCC_APB2LPENR_DFSDM2LPEN_Pos       (25U)
10342 #define RCC_APB2LPENR_DFSDM2LPEN_Msk       (0x1UL << RCC_APB2LPENR_DFSDM2LPEN_Pos) /*!< 0x02000000 */
10343 #define RCC_APB2LPENR_DFSDM2LPEN           RCC_APB2LPENR_DFSDM2LPEN_Msk
10344 
10345 /********************  Bit definition for RCC_BDCR register  ******************/
10346 #define RCC_BDCR_LSEON_Pos                 (0U)
10347 #define RCC_BDCR_LSEON_Msk                 (0x1UL << RCC_BDCR_LSEON_Pos)        /*!< 0x00000001 */
10348 #define RCC_BDCR_LSEON                     RCC_BDCR_LSEON_Msk
10349 #define RCC_BDCR_LSERDY_Pos                (1U)
10350 #define RCC_BDCR_LSERDY_Msk                (0x1UL << RCC_BDCR_LSERDY_Pos)       /*!< 0x00000002 */
10351 #define RCC_BDCR_LSERDY                    RCC_BDCR_LSERDY_Msk
10352 #define RCC_BDCR_LSEBYP_Pos                (2U)
10353 #define RCC_BDCR_LSEBYP_Msk                (0x1UL << RCC_BDCR_LSEBYP_Pos)       /*!< 0x00000004 */
10354 #define RCC_BDCR_LSEBYP                    RCC_BDCR_LSEBYP_Msk
10355 #define RCC_BDCR_LSEMOD_Pos                (3U)
10356 #define RCC_BDCR_LSEMOD_Msk                (0x1UL << RCC_BDCR_LSEMOD_Pos)       /*!< 0x00000008 */
10357 #define RCC_BDCR_LSEMOD                    RCC_BDCR_LSEMOD_Msk
10358 
10359 #define RCC_BDCR_RTCSEL_Pos                (8U)
10360 #define RCC_BDCR_RTCSEL_Msk                (0x3UL << RCC_BDCR_RTCSEL_Pos)       /*!< 0x00000300 */
10361 #define RCC_BDCR_RTCSEL                    RCC_BDCR_RTCSEL_Msk
10362 #define RCC_BDCR_RTCSEL_0                  (0x1UL << RCC_BDCR_RTCSEL_Pos)       /*!< 0x00000100 */
10363 #define RCC_BDCR_RTCSEL_1                  (0x2UL << RCC_BDCR_RTCSEL_Pos)       /*!< 0x00000200 */
10364 
10365 #define RCC_BDCR_RTCEN_Pos                 (15U)
10366 #define RCC_BDCR_RTCEN_Msk                 (0x1UL << RCC_BDCR_RTCEN_Pos)        /*!< 0x00008000 */
10367 #define RCC_BDCR_RTCEN                     RCC_BDCR_RTCEN_Msk
10368 #define RCC_BDCR_BDRST_Pos                 (16U)
10369 #define RCC_BDCR_BDRST_Msk                 (0x1UL << RCC_BDCR_BDRST_Pos)        /*!< 0x00010000 */
10370 #define RCC_BDCR_BDRST                     RCC_BDCR_BDRST_Msk
10371 
10372 /********************  Bit definition for RCC_CSR register  *******************/
10373 #define RCC_CSR_LSION_Pos                  (0U)
10374 #define RCC_CSR_LSION_Msk                  (0x1UL << RCC_CSR_LSION_Pos)         /*!< 0x00000001 */
10375 #define RCC_CSR_LSION                      RCC_CSR_LSION_Msk
10376 #define RCC_CSR_LSIRDY_Pos                 (1U)
10377 #define RCC_CSR_LSIRDY_Msk                 (0x1UL << RCC_CSR_LSIRDY_Pos)        /*!< 0x00000002 */
10378 #define RCC_CSR_LSIRDY                     RCC_CSR_LSIRDY_Msk
10379 #define RCC_CSR_RMVF_Pos                   (24U)
10380 #define RCC_CSR_RMVF_Msk                   (0x1UL << RCC_CSR_RMVF_Pos)          /*!< 0x01000000 */
10381 #define RCC_CSR_RMVF                       RCC_CSR_RMVF_Msk
10382 #define RCC_CSR_BORRSTF_Pos                (25U)
10383 #define RCC_CSR_BORRSTF_Msk                (0x1UL << RCC_CSR_BORRSTF_Pos)       /*!< 0x02000000 */
10384 #define RCC_CSR_BORRSTF                    RCC_CSR_BORRSTF_Msk
10385 #define RCC_CSR_PINRSTF_Pos                (26U)
10386 #define RCC_CSR_PINRSTF_Msk                (0x1UL << RCC_CSR_PINRSTF_Pos)       /*!< 0x04000000 */
10387 #define RCC_CSR_PINRSTF                    RCC_CSR_PINRSTF_Msk
10388 #define RCC_CSR_PORRSTF_Pos                (27U)
10389 #define RCC_CSR_PORRSTF_Msk                (0x1UL << RCC_CSR_PORRSTF_Pos)       /*!< 0x08000000 */
10390 #define RCC_CSR_PORRSTF                    RCC_CSR_PORRSTF_Msk
10391 #define RCC_CSR_SFTRSTF_Pos                (28U)
10392 #define RCC_CSR_SFTRSTF_Msk                (0x1UL << RCC_CSR_SFTRSTF_Pos)       /*!< 0x10000000 */
10393 #define RCC_CSR_SFTRSTF                    RCC_CSR_SFTRSTF_Msk
10394 #define RCC_CSR_IWDGRSTF_Pos               (29U)
10395 #define RCC_CSR_IWDGRSTF_Msk               (0x1UL << RCC_CSR_IWDGRSTF_Pos)      /*!< 0x20000000 */
10396 #define RCC_CSR_IWDGRSTF                   RCC_CSR_IWDGRSTF_Msk
10397 #define RCC_CSR_WWDGRSTF_Pos               (30U)
10398 #define RCC_CSR_WWDGRSTF_Msk               (0x1UL << RCC_CSR_WWDGRSTF_Pos)      /*!< 0x40000000 */
10399 #define RCC_CSR_WWDGRSTF                   RCC_CSR_WWDGRSTF_Msk
10400 #define RCC_CSR_LPWRRSTF_Pos               (31U)
10401 #define RCC_CSR_LPWRRSTF_Msk               (0x1UL << RCC_CSR_LPWRRSTF_Pos)      /*!< 0x80000000 */
10402 #define RCC_CSR_LPWRRSTF                   RCC_CSR_LPWRRSTF_Msk
10403 /* Legacy defines */
10404 #define RCC_CSR_PADRSTF                    RCC_CSR_PINRSTF
10405 #define RCC_CSR_WDGRSTF                    RCC_CSR_IWDGRSTF
10406 
10407 /********************  Bit definition for RCC_SSCGR register  *****************/
10408 #define RCC_SSCGR_MODPER_Pos               (0U)
10409 #define RCC_SSCGR_MODPER_Msk               (0x1FFFUL << RCC_SSCGR_MODPER_Pos)   /*!< 0x00001FFF */
10410 #define RCC_SSCGR_MODPER                   RCC_SSCGR_MODPER_Msk
10411 #define RCC_SSCGR_INCSTEP_Pos              (13U)
10412 #define RCC_SSCGR_INCSTEP_Msk              (0x7FFFUL << RCC_SSCGR_INCSTEP_Pos)  /*!< 0x0FFFE000 */
10413 #define RCC_SSCGR_INCSTEP                  RCC_SSCGR_INCSTEP_Msk
10414 #define RCC_SSCGR_SPREADSEL_Pos            (30U)
10415 #define RCC_SSCGR_SPREADSEL_Msk            (0x1UL << RCC_SSCGR_SPREADSEL_Pos)   /*!< 0x40000000 */
10416 #define RCC_SSCGR_SPREADSEL                RCC_SSCGR_SPREADSEL_Msk
10417 #define RCC_SSCGR_SSCGEN_Pos               (31U)
10418 #define RCC_SSCGR_SSCGEN_Msk               (0x1UL << RCC_SSCGR_SSCGEN_Pos)      /*!< 0x80000000 */
10419 #define RCC_SSCGR_SSCGEN                   RCC_SSCGR_SSCGEN_Msk
10420 
10421 /********************  Bit definition for RCC_PLLI2SCFGR register  ************/
10422 #define RCC_PLLI2SCFGR_PLLI2SM_Pos         (0U)
10423 #define RCC_PLLI2SCFGR_PLLI2SM_Msk         (0x3FUL << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x0000003F */
10424 #define RCC_PLLI2SCFGR_PLLI2SM             RCC_PLLI2SCFGR_PLLI2SM_Msk
10425 #define RCC_PLLI2SCFGR_PLLI2SM_0           (0x01UL << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000001 */
10426 #define RCC_PLLI2SCFGR_PLLI2SM_1           (0x02UL << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000002 */
10427 #define RCC_PLLI2SCFGR_PLLI2SM_2           (0x04UL << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000004 */
10428 #define RCC_PLLI2SCFGR_PLLI2SM_3           (0x08UL << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000008 */
10429 #define RCC_PLLI2SCFGR_PLLI2SM_4           (0x10UL << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000010 */
10430 #define RCC_PLLI2SCFGR_PLLI2SM_5           (0x20UL << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000020 */
10431 
10432 #define RCC_PLLI2SCFGR_PLLI2SN_Pos         (6U)
10433 #define RCC_PLLI2SCFGR_PLLI2SN_Msk         (0x1FFUL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00007FC0 */
10434 #define RCC_PLLI2SCFGR_PLLI2SN             RCC_PLLI2SCFGR_PLLI2SN_Msk
10435 #define RCC_PLLI2SCFGR_PLLI2SN_0           (0x001UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000040 */
10436 #define RCC_PLLI2SCFGR_PLLI2SN_1           (0x002UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000080 */
10437 #define RCC_PLLI2SCFGR_PLLI2SN_2           (0x004UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000100 */
10438 #define RCC_PLLI2SCFGR_PLLI2SN_3           (0x008UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000200 */
10439 #define RCC_PLLI2SCFGR_PLLI2SN_4           (0x010UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000400 */
10440 #define RCC_PLLI2SCFGR_PLLI2SN_5           (0x020UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000800 */
10441 #define RCC_PLLI2SCFGR_PLLI2SN_6           (0x040UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00001000 */
10442 #define RCC_PLLI2SCFGR_PLLI2SN_7           (0x080UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00002000 */
10443 #define RCC_PLLI2SCFGR_PLLI2SN_8           (0x100UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00004000 */
10444 
10445 #define RCC_PLLI2SCFGR_PLLI2SSRC_Pos       (22U)
10446 #define RCC_PLLI2SCFGR_PLLI2SSRC_Msk       (0x1UL << RCC_PLLI2SCFGR_PLLI2SSRC_Pos) /*!< 0x00400000 */
10447 #define RCC_PLLI2SCFGR_PLLI2SSRC           RCC_PLLI2SCFGR_PLLI2SSRC_Msk
10448 #define RCC_PLLI2SCFGR_PLLI2SQ_Pos         (24U)
10449 #define RCC_PLLI2SCFGR_PLLI2SQ_Msk         (0xFUL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x0F000000 */
10450 #define RCC_PLLI2SCFGR_PLLI2SQ             RCC_PLLI2SCFGR_PLLI2SQ_Msk
10451 #define RCC_PLLI2SCFGR_PLLI2SQ_0           (0x1UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x01000000 */
10452 #define RCC_PLLI2SCFGR_PLLI2SQ_1           (0x2UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x02000000 */
10453 #define RCC_PLLI2SCFGR_PLLI2SQ_2           (0x4UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x04000000 */
10454 #define RCC_PLLI2SCFGR_PLLI2SQ_3           (0x8UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x08000000 */
10455 #define RCC_PLLI2SCFGR_PLLI2SR_Pos         (28U)
10456 #define RCC_PLLI2SCFGR_PLLI2SR_Msk         (0x7UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x70000000 */
10457 #define RCC_PLLI2SCFGR_PLLI2SR             RCC_PLLI2SCFGR_PLLI2SR_Msk
10458 #define RCC_PLLI2SCFGR_PLLI2SR_0           (0x1UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x10000000 */
10459 #define RCC_PLLI2SCFGR_PLLI2SR_1           (0x2UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x20000000 */
10460 #define RCC_PLLI2SCFGR_PLLI2SR_2           (0x4UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x40000000 */
10461 
10462 
10463 
10464 /********************  Bit definition for RCC_DCKCFGR register  ***************/
10465 #define RCC_DCKCFGR_PLLI2SDIVR_Pos         (0U)
10466 #define RCC_DCKCFGR_PLLI2SDIVR_Msk         (0x1FUL << RCC_DCKCFGR_PLLI2SDIVR_Pos) /*!< 0x0000001F */
10467 #define RCC_DCKCFGR_PLLI2SDIVR             RCC_DCKCFGR_PLLI2SDIVR_Msk
10468 #define RCC_DCKCFGR_PLLI2SDIVR_0           (0x01UL << RCC_DCKCFGR_PLLI2SDIVR_Pos) /*!< 0x00000001 */
10469 #define RCC_DCKCFGR_PLLI2SDIVR_1           (0x02UL << RCC_DCKCFGR_PLLI2SDIVR_Pos) /*!< 0x00000002 */
10470 #define RCC_DCKCFGR_PLLI2SDIVR_2           (0x04UL << RCC_DCKCFGR_PLLI2SDIVR_Pos) /*!< 0x00000004 */
10471 #define RCC_DCKCFGR_PLLI2SDIVR_3           (0x08UL << RCC_DCKCFGR_PLLI2SDIVR_Pos) /*!< 0x00000008 */
10472 #define RCC_DCKCFGR_PLLI2SDIVR_4           (0x10UL << RCC_DCKCFGR_PLLI2SDIVR_Pos) /*!< 0x00000010 */
10473 
10474 #define RCC_DCKCFGR_PLLDIVR_Pos            (8U)
10475 #define RCC_DCKCFGR_PLLDIVR_Msk            (0x1FUL << RCC_DCKCFGR_PLLDIVR_Pos)  /*!< 0x00001F00 */
10476 #define RCC_DCKCFGR_PLLDIVR                RCC_DCKCFGR_PLLDIVR_Msk
10477 #define RCC_DCKCFGR_PLLDIVR_0              (0x01UL << RCC_DCKCFGR_PLLDIVR_Pos)  /*!< 0x00000100 */
10478 #define RCC_DCKCFGR_PLLDIVR_1              (0x02UL << RCC_DCKCFGR_PLLDIVR_Pos)  /*!< 0x00000200 */
10479 #define RCC_DCKCFGR_PLLDIVR_2              (0x04UL << RCC_DCKCFGR_PLLDIVR_Pos)  /*!< 0x00000400 */
10480 #define RCC_DCKCFGR_PLLDIVR_3              (0x08UL << RCC_DCKCFGR_PLLDIVR_Pos)  /*!< 0x00000800 */
10481 #define RCC_DCKCFGR_PLLDIVR_4              (0x10UL << RCC_DCKCFGR_PLLDIVR_Pos)  /*!< 0x00001000 */
10482 
10483 #define RCC_DCKCFGR_CKDFSDM2ASEL_Pos       (14U)
10484 #define RCC_DCKCFGR_CKDFSDM2ASEL_Msk       (0x1UL << RCC_DCKCFGR_CKDFSDM2ASEL_Pos) /*!< 0x00004000 */
10485 #define RCC_DCKCFGR_CKDFSDM2ASEL           RCC_DCKCFGR_CKDFSDM2ASEL_Msk
10486 #define RCC_DCKCFGR_CKDFSDM1ASEL_Pos       (15U)
10487 #define RCC_DCKCFGR_CKDFSDM1ASEL_Msk       (0x1UL << RCC_DCKCFGR_CKDFSDM1ASEL_Pos) /*!< 0x00008000 */
10488 #define RCC_DCKCFGR_CKDFSDM1ASEL           RCC_DCKCFGR_CKDFSDM1ASEL_Msk
10489 
10490 /*
10491  * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
10492  */
10493 #define  RCC_SAI1A_PLLSOURCE_SUPPORT      /*!< SAI1 block A PLL Main source clock support */
10494 #define  RCC_SAI1B_PLLSOURCE_SUPPORT      /*!< SAI1 block B PLL Main source clock support */
10495 
10496 #define RCC_DCKCFGR_SAI1ASRC_Pos           (20U)
10497 #define RCC_DCKCFGR_SAI1ASRC_Msk           (0x3UL << RCC_DCKCFGR_SAI1ASRC_Pos)  /*!< 0x00300000 */
10498 #define RCC_DCKCFGR_SAI1ASRC               RCC_DCKCFGR_SAI1ASRC_Msk
10499 #define RCC_DCKCFGR_SAI1ASRC_0             (0x1UL << RCC_DCKCFGR_SAI1ASRC_Pos)  /*!< 0x00100000 */
10500 #define RCC_DCKCFGR_SAI1ASRC_1             (0x2UL << RCC_DCKCFGR_SAI1ASRC_Pos)  /*!< 0x00200000 */
10501 #define RCC_DCKCFGR_SAI1BSRC_Pos           (22U)
10502 #define RCC_DCKCFGR_SAI1BSRC_Msk           (0x3UL << RCC_DCKCFGR_SAI1BSRC_Pos)  /*!< 0x00C00000 */
10503 #define RCC_DCKCFGR_SAI1BSRC               RCC_DCKCFGR_SAI1BSRC_Msk
10504 #define RCC_DCKCFGR_SAI1BSRC_0             (0x1UL << RCC_DCKCFGR_SAI1BSRC_Pos)  /*!< 0x00400000 */
10505 #define RCC_DCKCFGR_SAI1BSRC_1             (0x2UL << RCC_DCKCFGR_SAI1BSRC_Pos)  /*!< 0x00800000 */
10506 #define RCC_DCKCFGR_TIMPRE_Pos             (24U)
10507 #define RCC_DCKCFGR_TIMPRE_Msk             (0x1UL << RCC_DCKCFGR_TIMPRE_Pos)    /*!< 0x01000000 */
10508 #define RCC_DCKCFGR_TIMPRE                 RCC_DCKCFGR_TIMPRE_Msk
10509 #define RCC_DCKCFGR_I2S1SRC_Pos            (25U)
10510 #define RCC_DCKCFGR_I2S1SRC_Msk            (0x3UL << RCC_DCKCFGR_I2S1SRC_Pos)   /*!< 0x06000000 */
10511 #define RCC_DCKCFGR_I2S1SRC                RCC_DCKCFGR_I2S1SRC_Msk
10512 #define RCC_DCKCFGR_I2S1SRC_0              (0x1UL << RCC_DCKCFGR_I2S1SRC_Pos)   /*!< 0x02000000 */
10513 #define RCC_DCKCFGR_I2S1SRC_1              (0x2UL << RCC_DCKCFGR_I2S1SRC_Pos)   /*!< 0x04000000 */
10514 
10515 #define RCC_DCKCFGR_I2S2SRC_Pos            (27U)
10516 #define RCC_DCKCFGR_I2S2SRC_Msk            (0x3UL << RCC_DCKCFGR_I2S2SRC_Pos)   /*!< 0x18000000 */
10517 #define RCC_DCKCFGR_I2S2SRC                RCC_DCKCFGR_I2S2SRC_Msk
10518 #define RCC_DCKCFGR_I2S2SRC_0              (0x1UL << RCC_DCKCFGR_I2S2SRC_Pos)   /*!< 0x08000000 */
10519 #define RCC_DCKCFGR_I2S2SRC_1              (0x2UL << RCC_DCKCFGR_I2S2SRC_Pos)   /*!< 0x10000000 */
10520 #define RCC_DCKCFGR_CKDFSDM1SEL_Pos        (31U)
10521 #define RCC_DCKCFGR_CKDFSDM1SEL_Msk        (0x1UL << RCC_DCKCFGR_CKDFSDM1SEL_Pos) /*!< 0x80000000 */
10522 #define RCC_DCKCFGR_CKDFSDM1SEL            RCC_DCKCFGR_CKDFSDM1SEL_Msk
10523 
10524 /********************  Bit definition for RCC_CKGATENR register  ***************/
10525 #define RCC_CKGATENR_AHB2APB1_CKEN_Pos     (0U)
10526 #define RCC_CKGATENR_AHB2APB1_CKEN_Msk     (0x1UL << RCC_CKGATENR_AHB2APB1_CKEN_Pos) /*!< 0x00000001 */
10527 #define RCC_CKGATENR_AHB2APB1_CKEN         RCC_CKGATENR_AHB2APB1_CKEN_Msk
10528 #define RCC_CKGATENR_AHB2APB2_CKEN_Pos     (1U)
10529 #define RCC_CKGATENR_AHB2APB2_CKEN_Msk     (0x1UL << RCC_CKGATENR_AHB2APB2_CKEN_Pos) /*!< 0x00000002 */
10530 #define RCC_CKGATENR_AHB2APB2_CKEN         RCC_CKGATENR_AHB2APB2_CKEN_Msk
10531 #define RCC_CKGATENR_CM4DBG_CKEN_Pos       (2U)
10532 #define RCC_CKGATENR_CM4DBG_CKEN_Msk       (0x1UL << RCC_CKGATENR_CM4DBG_CKEN_Pos) /*!< 0x00000004 */
10533 #define RCC_CKGATENR_CM4DBG_CKEN           RCC_CKGATENR_CM4DBG_CKEN_Msk
10534 #define RCC_CKGATENR_SPARE_CKEN_Pos        (3U)
10535 #define RCC_CKGATENR_SPARE_CKEN_Msk        (0x1UL << RCC_CKGATENR_SPARE_CKEN_Pos) /*!< 0x00000008 */
10536 #define RCC_CKGATENR_SPARE_CKEN            RCC_CKGATENR_SPARE_CKEN_Msk
10537 #define RCC_CKGATENR_SRAM_CKEN_Pos         (4U)
10538 #define RCC_CKGATENR_SRAM_CKEN_Msk         (0x1UL << RCC_CKGATENR_SRAM_CKEN_Pos) /*!< 0x00000010 */
10539 #define RCC_CKGATENR_SRAM_CKEN             RCC_CKGATENR_SRAM_CKEN_Msk
10540 #define RCC_CKGATENR_FLITF_CKEN_Pos        (5U)
10541 #define RCC_CKGATENR_FLITF_CKEN_Msk        (0x1UL << RCC_CKGATENR_FLITF_CKEN_Pos) /*!< 0x00000020 */
10542 #define RCC_CKGATENR_FLITF_CKEN            RCC_CKGATENR_FLITF_CKEN_Msk
10543 #define RCC_CKGATENR_RCC_CKEN_Pos          (6U)
10544 #define RCC_CKGATENR_RCC_CKEN_Msk          (0x1UL << RCC_CKGATENR_RCC_CKEN_Pos) /*!< 0x00000040 */
10545 #define RCC_CKGATENR_RCC_CKEN              RCC_CKGATENR_RCC_CKEN_Msk
10546 #define RCC_CKGATENR_RCC_EVTCTL_Pos        (7U)
10547 #define RCC_CKGATENR_RCC_EVTCTL_Msk        (0x1UL << RCC_CKGATENR_RCC_EVTCTL_Pos) /*!< 0x00000080 */
10548 #define RCC_CKGATENR_RCC_EVTCTL            RCC_CKGATENR_RCC_EVTCTL_Msk
10549 
10550 /********************  Bit definition for RCC_DCKCFGR2 register  ***************/
10551 #define RCC_DCKCFGR2_FMPI2C1SEL_Pos        (22U)
10552 #define RCC_DCKCFGR2_FMPI2C1SEL_Msk        (0x3UL << RCC_DCKCFGR2_FMPI2C1SEL_Pos) /*!< 0x00C00000 */
10553 #define RCC_DCKCFGR2_FMPI2C1SEL            RCC_DCKCFGR2_FMPI2C1SEL_Msk
10554 #define RCC_DCKCFGR2_FMPI2C1SEL_0          (0x1UL << RCC_DCKCFGR2_FMPI2C1SEL_Pos) /*!< 0x00400000 */
10555 #define RCC_DCKCFGR2_FMPI2C1SEL_1          (0x2UL << RCC_DCKCFGR2_FMPI2C1SEL_Pos) /*!< 0x00800000 */
10556 #define RCC_DCKCFGR2_CK48MSEL_Pos          (27U)
10557 #define RCC_DCKCFGR2_CK48MSEL_Msk          (0x1UL << RCC_DCKCFGR2_CK48MSEL_Pos) /*!< 0x08000000 */
10558 #define RCC_DCKCFGR2_CK48MSEL              RCC_DCKCFGR2_CK48MSEL_Msk
10559 #define RCC_DCKCFGR2_SDIOSEL_Pos           (28U)
10560 #define RCC_DCKCFGR2_SDIOSEL_Msk           (0x1UL << RCC_DCKCFGR2_SDIOSEL_Pos)  /*!< 0x10000000 */
10561 #define RCC_DCKCFGR2_SDIOSEL               RCC_DCKCFGR2_SDIOSEL_Msk
10562 #define RCC_DCKCFGR2_LPTIM1SEL_Pos         (30U)
10563 #define RCC_DCKCFGR2_LPTIM1SEL_Msk         (0x3UL << RCC_DCKCFGR2_LPTIM1SEL_Pos) /*!< 0xC0000000 */
10564 #define RCC_DCKCFGR2_LPTIM1SEL             RCC_DCKCFGR2_LPTIM1SEL_Msk
10565 #define RCC_DCKCFGR2_LPTIM1SEL_0           (0x1UL << RCC_DCKCFGR2_LPTIM1SEL_Pos) /*!< 0x40000000 */
10566 #define RCC_DCKCFGR2_LPTIM1SEL_1           (0x2UL << RCC_DCKCFGR2_LPTIM1SEL_Pos) /*!< 0x80000000 */
10567 
10568 
10569 /******************************************************************************/
10570 /*                                                                            */
10571 /*                                    RNG                                     */
10572 /*                                                                            */
10573 /******************************************************************************/
10574 /********************  Bits definition for RNG_CR register  *******************/
10575 #define RNG_CR_RNGEN_Pos    (2U)
10576 #define RNG_CR_RNGEN_Msk    (0x1UL << RNG_CR_RNGEN_Pos)                         /*!< 0x00000004 */
10577 #define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk
10578 #define RNG_CR_IE_Pos       (3U)
10579 #define RNG_CR_IE_Msk       (0x1UL << RNG_CR_IE_Pos)                            /*!< 0x00000008 */
10580 #define RNG_CR_IE           RNG_CR_IE_Msk
10581 
10582 /********************  Bits definition for RNG_SR register  *******************/
10583 #define RNG_SR_DRDY_Pos     (0U)
10584 #define RNG_SR_DRDY_Msk     (0x1UL << RNG_SR_DRDY_Pos)                          /*!< 0x00000001 */
10585 #define RNG_SR_DRDY         RNG_SR_DRDY_Msk
10586 #define RNG_SR_CECS_Pos     (1U)
10587 #define RNG_SR_CECS_Msk     (0x1UL << RNG_SR_CECS_Pos)                          /*!< 0x00000002 */
10588 #define RNG_SR_CECS         RNG_SR_CECS_Msk
10589 #define RNG_SR_SECS_Pos     (2U)
10590 #define RNG_SR_SECS_Msk     (0x1UL << RNG_SR_SECS_Pos)                          /*!< 0x00000004 */
10591 #define RNG_SR_SECS         RNG_SR_SECS_Msk
10592 #define RNG_SR_CEIS_Pos     (5U)
10593 #define RNG_SR_CEIS_Msk     (0x1UL << RNG_SR_CEIS_Pos)                          /*!< 0x00000020 */
10594 #define RNG_SR_CEIS         RNG_SR_CEIS_Msk
10595 #define RNG_SR_SEIS_Pos     (6U)
10596 #define RNG_SR_SEIS_Msk     (0x1UL << RNG_SR_SEIS_Pos)                          /*!< 0x00000040 */
10597 #define RNG_SR_SEIS         RNG_SR_SEIS_Msk
10598 
10599 /******************************************************************************/
10600 /*                                                                            */
10601 /*                           Real-Time Clock (RTC)                            */
10602 /*                                                                            */
10603 /******************************************************************************/
10604 /********************  Bits definition for RTC_TR register  *******************/
10605 #define RTC_TR_PM_Pos                 (22U)
10606 #define RTC_TR_PM_Msk                 (0x1UL << RTC_TR_PM_Pos)                  /*!< 0x00400000 */
10607 #define RTC_TR_PM                     RTC_TR_PM_Msk
10608 #define RTC_TR_HT_Pos                 (20U)
10609 #define RTC_TR_HT_Msk                 (0x3UL << RTC_TR_HT_Pos)                  /*!< 0x00300000 */
10610 #define RTC_TR_HT                     RTC_TR_HT_Msk
10611 #define RTC_TR_HT_0                   (0x1UL << RTC_TR_HT_Pos)                  /*!< 0x00100000 */
10612 #define RTC_TR_HT_1                   (0x2UL << RTC_TR_HT_Pos)                  /*!< 0x00200000 */
10613 #define RTC_TR_HU_Pos                 (16U)
10614 #define RTC_TR_HU_Msk                 (0xFUL << RTC_TR_HU_Pos)                  /*!< 0x000F0000 */
10615 #define RTC_TR_HU                     RTC_TR_HU_Msk
10616 #define RTC_TR_HU_0                   (0x1UL << RTC_TR_HU_Pos)                  /*!< 0x00010000 */
10617 #define RTC_TR_HU_1                   (0x2UL << RTC_TR_HU_Pos)                  /*!< 0x00020000 */
10618 #define RTC_TR_HU_2                   (0x4UL << RTC_TR_HU_Pos)                  /*!< 0x00040000 */
10619 #define RTC_TR_HU_3                   (0x8UL << RTC_TR_HU_Pos)                  /*!< 0x00080000 */
10620 #define RTC_TR_MNT_Pos                (12U)
10621 #define RTC_TR_MNT_Msk                (0x7UL << RTC_TR_MNT_Pos)                 /*!< 0x00007000 */
10622 #define RTC_TR_MNT                    RTC_TR_MNT_Msk
10623 #define RTC_TR_MNT_0                  (0x1UL << RTC_TR_MNT_Pos)                 /*!< 0x00001000 */
10624 #define RTC_TR_MNT_1                  (0x2UL << RTC_TR_MNT_Pos)                 /*!< 0x00002000 */
10625 #define RTC_TR_MNT_2                  (0x4UL << RTC_TR_MNT_Pos)                 /*!< 0x00004000 */
10626 #define RTC_TR_MNU_Pos                (8U)
10627 #define RTC_TR_MNU_Msk                (0xFUL << RTC_TR_MNU_Pos)                 /*!< 0x00000F00 */
10628 #define RTC_TR_MNU                    RTC_TR_MNU_Msk
10629 #define RTC_TR_MNU_0                  (0x1UL << RTC_TR_MNU_Pos)                 /*!< 0x00000100 */
10630 #define RTC_TR_MNU_1                  (0x2UL << RTC_TR_MNU_Pos)                 /*!< 0x00000200 */
10631 #define RTC_TR_MNU_2                  (0x4UL << RTC_TR_MNU_Pos)                 /*!< 0x00000400 */
10632 #define RTC_TR_MNU_3                  (0x8UL << RTC_TR_MNU_Pos)                 /*!< 0x00000800 */
10633 #define RTC_TR_ST_Pos                 (4U)
10634 #define RTC_TR_ST_Msk                 (0x7UL << RTC_TR_ST_Pos)                  /*!< 0x00000070 */
10635 #define RTC_TR_ST                     RTC_TR_ST_Msk
10636 #define RTC_TR_ST_0                   (0x1UL << RTC_TR_ST_Pos)                  /*!< 0x00000010 */
10637 #define RTC_TR_ST_1                   (0x2UL << RTC_TR_ST_Pos)                  /*!< 0x00000020 */
10638 #define RTC_TR_ST_2                   (0x4UL << RTC_TR_ST_Pos)                  /*!< 0x00000040 */
10639 #define RTC_TR_SU_Pos                 (0U)
10640 #define RTC_TR_SU_Msk                 (0xFUL << RTC_TR_SU_Pos)                  /*!< 0x0000000F */
10641 #define RTC_TR_SU                     RTC_TR_SU_Msk
10642 #define RTC_TR_SU_0                   (0x1UL << RTC_TR_SU_Pos)                  /*!< 0x00000001 */
10643 #define RTC_TR_SU_1                   (0x2UL << RTC_TR_SU_Pos)                  /*!< 0x00000002 */
10644 #define RTC_TR_SU_2                   (0x4UL << RTC_TR_SU_Pos)                  /*!< 0x00000004 */
10645 #define RTC_TR_SU_3                   (0x8UL << RTC_TR_SU_Pos)                  /*!< 0x00000008 */
10646 
10647 /********************  Bits definition for RTC_DR register  *******************/
10648 #define RTC_DR_YT_Pos                 (20U)
10649 #define RTC_DR_YT_Msk                 (0xFUL << RTC_DR_YT_Pos)                  /*!< 0x00F00000 */
10650 #define RTC_DR_YT                     RTC_DR_YT_Msk
10651 #define RTC_DR_YT_0                   (0x1UL << RTC_DR_YT_Pos)                  /*!< 0x00100000 */
10652 #define RTC_DR_YT_1                   (0x2UL << RTC_DR_YT_Pos)                  /*!< 0x00200000 */
10653 #define RTC_DR_YT_2                   (0x4UL << RTC_DR_YT_Pos)                  /*!< 0x00400000 */
10654 #define RTC_DR_YT_3                   (0x8UL << RTC_DR_YT_Pos)                  /*!< 0x00800000 */
10655 #define RTC_DR_YU_Pos                 (16U)
10656 #define RTC_DR_YU_Msk                 (0xFUL << RTC_DR_YU_Pos)                  /*!< 0x000F0000 */
10657 #define RTC_DR_YU                     RTC_DR_YU_Msk
10658 #define RTC_DR_YU_0                   (0x1UL << RTC_DR_YU_Pos)                  /*!< 0x00010000 */
10659 #define RTC_DR_YU_1                   (0x2UL << RTC_DR_YU_Pos)                  /*!< 0x00020000 */
10660 #define RTC_DR_YU_2                   (0x4UL << RTC_DR_YU_Pos)                  /*!< 0x00040000 */
10661 #define RTC_DR_YU_3                   (0x8UL << RTC_DR_YU_Pos)                  /*!< 0x00080000 */
10662 #define RTC_DR_WDU_Pos                (13U)
10663 #define RTC_DR_WDU_Msk                (0x7UL << RTC_DR_WDU_Pos)                 /*!< 0x0000E000 */
10664 #define RTC_DR_WDU                    RTC_DR_WDU_Msk
10665 #define RTC_DR_WDU_0                  (0x1UL << RTC_DR_WDU_Pos)                 /*!< 0x00002000 */
10666 #define RTC_DR_WDU_1                  (0x2UL << RTC_DR_WDU_Pos)                 /*!< 0x00004000 */
10667 #define RTC_DR_WDU_2                  (0x4UL << RTC_DR_WDU_Pos)                 /*!< 0x00008000 */
10668 #define RTC_DR_MT_Pos                 (12U)
10669 #define RTC_DR_MT_Msk                 (0x1UL << RTC_DR_MT_Pos)                  /*!< 0x00001000 */
10670 #define RTC_DR_MT                     RTC_DR_MT_Msk
10671 #define RTC_DR_MU_Pos                 (8U)
10672 #define RTC_DR_MU_Msk                 (0xFUL << RTC_DR_MU_Pos)                  /*!< 0x00000F00 */
10673 #define RTC_DR_MU                     RTC_DR_MU_Msk
10674 #define RTC_DR_MU_0                   (0x1UL << RTC_DR_MU_Pos)                  /*!< 0x00000100 */
10675 #define RTC_DR_MU_1                   (0x2UL << RTC_DR_MU_Pos)                  /*!< 0x00000200 */
10676 #define RTC_DR_MU_2                   (0x4UL << RTC_DR_MU_Pos)                  /*!< 0x00000400 */
10677 #define RTC_DR_MU_3                   (0x8UL << RTC_DR_MU_Pos)                  /*!< 0x00000800 */
10678 #define RTC_DR_DT_Pos                 (4U)
10679 #define RTC_DR_DT_Msk                 (0x3UL << RTC_DR_DT_Pos)                  /*!< 0x00000030 */
10680 #define RTC_DR_DT                     RTC_DR_DT_Msk
10681 #define RTC_DR_DT_0                   (0x1UL << RTC_DR_DT_Pos)                  /*!< 0x00000010 */
10682 #define RTC_DR_DT_1                   (0x2UL << RTC_DR_DT_Pos)                  /*!< 0x00000020 */
10683 #define RTC_DR_DU_Pos                 (0U)
10684 #define RTC_DR_DU_Msk                 (0xFUL << RTC_DR_DU_Pos)                  /*!< 0x0000000F */
10685 #define RTC_DR_DU                     RTC_DR_DU_Msk
10686 #define RTC_DR_DU_0                   (0x1UL << RTC_DR_DU_Pos)                  /*!< 0x00000001 */
10687 #define RTC_DR_DU_1                   (0x2UL << RTC_DR_DU_Pos)                  /*!< 0x00000002 */
10688 #define RTC_DR_DU_2                   (0x4UL << RTC_DR_DU_Pos)                  /*!< 0x00000004 */
10689 #define RTC_DR_DU_3                   (0x8UL << RTC_DR_DU_Pos)                  /*!< 0x00000008 */
10690 
10691 /********************  Bits definition for RTC_CR register  *******************/
10692 #define RTC_CR_COE_Pos                (23U)
10693 #define RTC_CR_COE_Msk                (0x1UL << RTC_CR_COE_Pos)                 /*!< 0x00800000 */
10694 #define RTC_CR_COE                    RTC_CR_COE_Msk
10695 #define RTC_CR_OSEL_Pos               (21U)
10696 #define RTC_CR_OSEL_Msk               (0x3UL << RTC_CR_OSEL_Pos)                /*!< 0x00600000 */
10697 #define RTC_CR_OSEL                   RTC_CR_OSEL_Msk
10698 #define RTC_CR_OSEL_0                 (0x1UL << RTC_CR_OSEL_Pos)                /*!< 0x00200000 */
10699 #define RTC_CR_OSEL_1                 (0x2UL << RTC_CR_OSEL_Pos)                /*!< 0x00400000 */
10700 #define RTC_CR_POL_Pos                (20U)
10701 #define RTC_CR_POL_Msk                (0x1UL << RTC_CR_POL_Pos)                 /*!< 0x00100000 */
10702 #define RTC_CR_POL                    RTC_CR_POL_Msk
10703 #define RTC_CR_COSEL_Pos              (19U)
10704 #define RTC_CR_COSEL_Msk              (0x1UL << RTC_CR_COSEL_Pos)               /*!< 0x00080000 */
10705 #define RTC_CR_COSEL                  RTC_CR_COSEL_Msk
10706 #define RTC_CR_BKP_Pos                 (18U)
10707 #define RTC_CR_BKP_Msk                 (0x1UL << RTC_CR_BKP_Pos)                /*!< 0x00040000 */
10708 #define RTC_CR_BKP                     RTC_CR_BKP_Msk
10709 #define RTC_CR_SUB1H_Pos              (17U)
10710 #define RTC_CR_SUB1H_Msk              (0x1UL << RTC_CR_SUB1H_Pos)               /*!< 0x00020000 */
10711 #define RTC_CR_SUB1H                  RTC_CR_SUB1H_Msk
10712 #define RTC_CR_ADD1H_Pos              (16U)
10713 #define RTC_CR_ADD1H_Msk              (0x1UL << RTC_CR_ADD1H_Pos)               /*!< 0x00010000 */
10714 #define RTC_CR_ADD1H                  RTC_CR_ADD1H_Msk
10715 #define RTC_CR_TSIE_Pos               (15U)
10716 #define RTC_CR_TSIE_Msk               (0x1UL << RTC_CR_TSIE_Pos)                /*!< 0x00008000 */
10717 #define RTC_CR_TSIE                   RTC_CR_TSIE_Msk
10718 #define RTC_CR_WUTIE_Pos              (14U)
10719 #define RTC_CR_WUTIE_Msk              (0x1UL << RTC_CR_WUTIE_Pos)               /*!< 0x00004000 */
10720 #define RTC_CR_WUTIE                  RTC_CR_WUTIE_Msk
10721 #define RTC_CR_ALRBIE_Pos             (13U)
10722 #define RTC_CR_ALRBIE_Msk             (0x1UL << RTC_CR_ALRBIE_Pos)              /*!< 0x00002000 */
10723 #define RTC_CR_ALRBIE                 RTC_CR_ALRBIE_Msk
10724 #define RTC_CR_ALRAIE_Pos             (12U)
10725 #define RTC_CR_ALRAIE_Msk             (0x1UL << RTC_CR_ALRAIE_Pos)              /*!< 0x00001000 */
10726 #define RTC_CR_ALRAIE                 RTC_CR_ALRAIE_Msk
10727 #define RTC_CR_TSE_Pos                (11U)
10728 #define RTC_CR_TSE_Msk                (0x1UL << RTC_CR_TSE_Pos)                 /*!< 0x00000800 */
10729 #define RTC_CR_TSE                    RTC_CR_TSE_Msk
10730 #define RTC_CR_WUTE_Pos               (10U)
10731 #define RTC_CR_WUTE_Msk               (0x1UL << RTC_CR_WUTE_Pos)                /*!< 0x00000400 */
10732 #define RTC_CR_WUTE                   RTC_CR_WUTE_Msk
10733 #define RTC_CR_ALRBE_Pos              (9U)
10734 #define RTC_CR_ALRBE_Msk              (0x1UL << RTC_CR_ALRBE_Pos)               /*!< 0x00000200 */
10735 #define RTC_CR_ALRBE                  RTC_CR_ALRBE_Msk
10736 #define RTC_CR_ALRAE_Pos              (8U)
10737 #define RTC_CR_ALRAE_Msk              (0x1UL << RTC_CR_ALRAE_Pos)               /*!< 0x00000100 */
10738 #define RTC_CR_ALRAE                  RTC_CR_ALRAE_Msk
10739 #define RTC_CR_DCE_Pos                (7U)
10740 #define RTC_CR_DCE_Msk                (0x1UL << RTC_CR_DCE_Pos)                 /*!< 0x00000080 */
10741 #define RTC_CR_DCE                    RTC_CR_DCE_Msk
10742 #define RTC_CR_FMT_Pos                (6U)
10743 #define RTC_CR_FMT_Msk                (0x1UL << RTC_CR_FMT_Pos)                 /*!< 0x00000040 */
10744 #define RTC_CR_FMT                    RTC_CR_FMT_Msk
10745 #define RTC_CR_BYPSHAD_Pos            (5U)
10746 #define RTC_CR_BYPSHAD_Msk            (0x1UL << RTC_CR_BYPSHAD_Pos)             /*!< 0x00000020 */
10747 #define RTC_CR_BYPSHAD                RTC_CR_BYPSHAD_Msk
10748 #define RTC_CR_REFCKON_Pos            (4U)
10749 #define RTC_CR_REFCKON_Msk            (0x1UL << RTC_CR_REFCKON_Pos)             /*!< 0x00000010 */
10750 #define RTC_CR_REFCKON                RTC_CR_REFCKON_Msk
10751 #define RTC_CR_TSEDGE_Pos             (3U)
10752 #define RTC_CR_TSEDGE_Msk             (0x1UL << RTC_CR_TSEDGE_Pos)              /*!< 0x00000008 */
10753 #define RTC_CR_TSEDGE                 RTC_CR_TSEDGE_Msk
10754 #define RTC_CR_WUCKSEL_Pos            (0U)
10755 #define RTC_CR_WUCKSEL_Msk            (0x7UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000007 */
10756 #define RTC_CR_WUCKSEL                RTC_CR_WUCKSEL_Msk
10757 #define RTC_CR_WUCKSEL_0              (0x1UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000001 */
10758 #define RTC_CR_WUCKSEL_1              (0x2UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000002 */
10759 #define RTC_CR_WUCKSEL_2              (0x4UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000004 */
10760 
10761 /* Legacy defines */
10762 #define RTC_CR_BCK                     RTC_CR_BKP
10763 
10764 /********************  Bits definition for RTC_ISR register  ******************/
10765 #define RTC_ISR_RECALPF_Pos           (16U)
10766 #define RTC_ISR_RECALPF_Msk           (0x1UL << RTC_ISR_RECALPF_Pos)            /*!< 0x00010000 */
10767 #define RTC_ISR_RECALPF               RTC_ISR_RECALPF_Msk
10768 #define RTC_ISR_TAMP1F_Pos            (13U)
10769 #define RTC_ISR_TAMP1F_Msk            (0x1UL << RTC_ISR_TAMP1F_Pos)             /*!< 0x00002000 */
10770 #define RTC_ISR_TAMP1F                RTC_ISR_TAMP1F_Msk
10771 #define RTC_ISR_TAMP2F_Pos            (14U)
10772 #define RTC_ISR_TAMP2F_Msk            (0x1UL << RTC_ISR_TAMP2F_Pos)             /*!< 0x00004000 */
10773 #define RTC_ISR_TAMP2F                RTC_ISR_TAMP2F_Msk
10774 #define RTC_ISR_TSOVF_Pos             (12U)
10775 #define RTC_ISR_TSOVF_Msk             (0x1UL << RTC_ISR_TSOVF_Pos)              /*!< 0x00001000 */
10776 #define RTC_ISR_TSOVF                 RTC_ISR_TSOVF_Msk
10777 #define RTC_ISR_TSF_Pos               (11U)
10778 #define RTC_ISR_TSF_Msk               (0x1UL << RTC_ISR_TSF_Pos)                /*!< 0x00000800 */
10779 #define RTC_ISR_TSF                   RTC_ISR_TSF_Msk
10780 #define RTC_ISR_WUTF_Pos              (10U)
10781 #define RTC_ISR_WUTF_Msk              (0x1UL << RTC_ISR_WUTF_Pos)               /*!< 0x00000400 */
10782 #define RTC_ISR_WUTF                  RTC_ISR_WUTF_Msk
10783 #define RTC_ISR_ALRBF_Pos             (9U)
10784 #define RTC_ISR_ALRBF_Msk             (0x1UL << RTC_ISR_ALRBF_Pos)              /*!< 0x00000200 */
10785 #define RTC_ISR_ALRBF                 RTC_ISR_ALRBF_Msk
10786 #define RTC_ISR_ALRAF_Pos             (8U)
10787 #define RTC_ISR_ALRAF_Msk             (0x1UL << RTC_ISR_ALRAF_Pos)              /*!< 0x00000100 */
10788 #define RTC_ISR_ALRAF                 RTC_ISR_ALRAF_Msk
10789 #define RTC_ISR_INIT_Pos              (7U)
10790 #define RTC_ISR_INIT_Msk              (0x1UL << RTC_ISR_INIT_Pos)               /*!< 0x00000080 */
10791 #define RTC_ISR_INIT                  RTC_ISR_INIT_Msk
10792 #define RTC_ISR_INITF_Pos             (6U)
10793 #define RTC_ISR_INITF_Msk             (0x1UL << RTC_ISR_INITF_Pos)              /*!< 0x00000040 */
10794 #define RTC_ISR_INITF                 RTC_ISR_INITF_Msk
10795 #define RTC_ISR_RSF_Pos               (5U)
10796 #define RTC_ISR_RSF_Msk               (0x1UL << RTC_ISR_RSF_Pos)                /*!< 0x00000020 */
10797 #define RTC_ISR_RSF                   RTC_ISR_RSF_Msk
10798 #define RTC_ISR_INITS_Pos             (4U)
10799 #define RTC_ISR_INITS_Msk             (0x1UL << RTC_ISR_INITS_Pos)              /*!< 0x00000010 */
10800 #define RTC_ISR_INITS                 RTC_ISR_INITS_Msk
10801 #define RTC_ISR_SHPF_Pos              (3U)
10802 #define RTC_ISR_SHPF_Msk              (0x1UL << RTC_ISR_SHPF_Pos)               /*!< 0x00000008 */
10803 #define RTC_ISR_SHPF                  RTC_ISR_SHPF_Msk
10804 #define RTC_ISR_WUTWF_Pos             (2U)
10805 #define RTC_ISR_WUTWF_Msk             (0x1UL << RTC_ISR_WUTWF_Pos)              /*!< 0x00000004 */
10806 #define RTC_ISR_WUTWF                 RTC_ISR_WUTWF_Msk
10807 #define RTC_ISR_ALRBWF_Pos            (1U)
10808 #define RTC_ISR_ALRBWF_Msk            (0x1UL << RTC_ISR_ALRBWF_Pos)             /*!< 0x00000002 */
10809 #define RTC_ISR_ALRBWF                RTC_ISR_ALRBWF_Msk
10810 #define RTC_ISR_ALRAWF_Pos            (0U)
10811 #define RTC_ISR_ALRAWF_Msk            (0x1UL << RTC_ISR_ALRAWF_Pos)             /*!< 0x00000001 */
10812 #define RTC_ISR_ALRAWF                RTC_ISR_ALRAWF_Msk
10813 
10814 /********************  Bits definition for RTC_PRER register  *****************/
10815 #define RTC_PRER_PREDIV_A_Pos         (16U)
10816 #define RTC_PRER_PREDIV_A_Msk         (0x7FUL << RTC_PRER_PREDIV_A_Pos)         /*!< 0x007F0000 */
10817 #define RTC_PRER_PREDIV_A             RTC_PRER_PREDIV_A_Msk
10818 #define RTC_PRER_PREDIV_S_Pos         (0U)
10819 #define RTC_PRER_PREDIV_S_Msk         (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)       /*!< 0x00007FFF */
10820 #define RTC_PRER_PREDIV_S             RTC_PRER_PREDIV_S_Msk
10821 
10822 /********************  Bits definition for RTC_WUTR register  *****************/
10823 #define RTC_WUTR_WUT_Pos              (0U)
10824 #define RTC_WUTR_WUT_Msk              (0xFFFFUL << RTC_WUTR_WUT_Pos)            /*!< 0x0000FFFF */
10825 #define RTC_WUTR_WUT                  RTC_WUTR_WUT_Msk
10826 
10827 /********************  Bits definition for RTC_CALIBR register  ***************/
10828 #define RTC_CALIBR_DCS_Pos            (7U)
10829 #define RTC_CALIBR_DCS_Msk            (0x1UL << RTC_CALIBR_DCS_Pos)             /*!< 0x00000080 */
10830 #define RTC_CALIBR_DCS                RTC_CALIBR_DCS_Msk
10831 #define RTC_CALIBR_DC_Pos             (0U)
10832 #define RTC_CALIBR_DC_Msk             (0x1FUL << RTC_CALIBR_DC_Pos)             /*!< 0x0000001F */
10833 #define RTC_CALIBR_DC                 RTC_CALIBR_DC_Msk
10834 
10835 /********************  Bits definition for RTC_ALRMAR register  ***************/
10836 #define RTC_ALRMAR_MSK4_Pos           (31U)
10837 #define RTC_ALRMAR_MSK4_Msk           (0x1UL << RTC_ALRMAR_MSK4_Pos)            /*!< 0x80000000 */
10838 #define RTC_ALRMAR_MSK4               RTC_ALRMAR_MSK4_Msk
10839 #define RTC_ALRMAR_WDSEL_Pos          (30U)
10840 #define RTC_ALRMAR_WDSEL_Msk          (0x1UL << RTC_ALRMAR_WDSEL_Pos)           /*!< 0x40000000 */
10841 #define RTC_ALRMAR_WDSEL              RTC_ALRMAR_WDSEL_Msk
10842 #define RTC_ALRMAR_DT_Pos             (28U)
10843 #define RTC_ALRMAR_DT_Msk             (0x3UL << RTC_ALRMAR_DT_Pos)              /*!< 0x30000000 */
10844 #define RTC_ALRMAR_DT                 RTC_ALRMAR_DT_Msk
10845 #define RTC_ALRMAR_DT_0               (0x1UL << RTC_ALRMAR_DT_Pos)              /*!< 0x10000000 */
10846 #define RTC_ALRMAR_DT_1               (0x2UL << RTC_ALRMAR_DT_Pos)              /*!< 0x20000000 */
10847 #define RTC_ALRMAR_DU_Pos             (24U)
10848 #define RTC_ALRMAR_DU_Msk             (0xFUL << RTC_ALRMAR_DU_Pos)              /*!< 0x0F000000 */
10849 #define RTC_ALRMAR_DU                 RTC_ALRMAR_DU_Msk
10850 #define RTC_ALRMAR_DU_0               (0x1UL << RTC_ALRMAR_DU_Pos)              /*!< 0x01000000 */
10851 #define RTC_ALRMAR_DU_1               (0x2UL << RTC_ALRMAR_DU_Pos)              /*!< 0x02000000 */
10852 #define RTC_ALRMAR_DU_2               (0x4UL << RTC_ALRMAR_DU_Pos)              /*!< 0x04000000 */
10853 #define RTC_ALRMAR_DU_3               (0x8UL << RTC_ALRMAR_DU_Pos)              /*!< 0x08000000 */
10854 #define RTC_ALRMAR_MSK3_Pos           (23U)
10855 #define RTC_ALRMAR_MSK3_Msk           (0x1UL << RTC_ALRMAR_MSK3_Pos)            /*!< 0x00800000 */
10856 #define RTC_ALRMAR_MSK3               RTC_ALRMAR_MSK3_Msk
10857 #define RTC_ALRMAR_PM_Pos             (22U)
10858 #define RTC_ALRMAR_PM_Msk             (0x1UL << RTC_ALRMAR_PM_Pos)              /*!< 0x00400000 */
10859 #define RTC_ALRMAR_PM                 RTC_ALRMAR_PM_Msk
10860 #define RTC_ALRMAR_HT_Pos             (20U)
10861 #define RTC_ALRMAR_HT_Msk             (0x3UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00300000 */
10862 #define RTC_ALRMAR_HT                 RTC_ALRMAR_HT_Msk
10863 #define RTC_ALRMAR_HT_0               (0x1UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00100000 */
10864 #define RTC_ALRMAR_HT_1               (0x2UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00200000 */
10865 #define RTC_ALRMAR_HU_Pos             (16U)
10866 #define RTC_ALRMAR_HU_Msk             (0xFUL << RTC_ALRMAR_HU_Pos)              /*!< 0x000F0000 */
10867 #define RTC_ALRMAR_HU                 RTC_ALRMAR_HU_Msk
10868 #define RTC_ALRMAR_HU_0               (0x1UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00010000 */
10869 #define RTC_ALRMAR_HU_1               (0x2UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00020000 */
10870 #define RTC_ALRMAR_HU_2               (0x4UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00040000 */
10871 #define RTC_ALRMAR_HU_3               (0x8UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00080000 */
10872 #define RTC_ALRMAR_MSK2_Pos           (15U)
10873 #define RTC_ALRMAR_MSK2_Msk           (0x1UL << RTC_ALRMAR_MSK2_Pos)            /*!< 0x00008000 */
10874 #define RTC_ALRMAR_MSK2               RTC_ALRMAR_MSK2_Msk
10875 #define RTC_ALRMAR_MNT_Pos            (12U)
10876 #define RTC_ALRMAR_MNT_Msk            (0x7UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00007000 */
10877 #define RTC_ALRMAR_MNT                RTC_ALRMAR_MNT_Msk
10878 #define RTC_ALRMAR_MNT_0              (0x1UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00001000 */
10879 #define RTC_ALRMAR_MNT_1              (0x2UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00002000 */
10880 #define RTC_ALRMAR_MNT_2              (0x4UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00004000 */
10881 #define RTC_ALRMAR_MNU_Pos            (8U)
10882 #define RTC_ALRMAR_MNU_Msk            (0xFUL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000F00 */
10883 #define RTC_ALRMAR_MNU                RTC_ALRMAR_MNU_Msk
10884 #define RTC_ALRMAR_MNU_0              (0x1UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000100 */
10885 #define RTC_ALRMAR_MNU_1              (0x2UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000200 */
10886 #define RTC_ALRMAR_MNU_2              (0x4UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000400 */
10887 #define RTC_ALRMAR_MNU_3              (0x8UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000800 */
10888 #define RTC_ALRMAR_MSK1_Pos           (7U)
10889 #define RTC_ALRMAR_MSK1_Msk           (0x1UL << RTC_ALRMAR_MSK1_Pos)            /*!< 0x00000080 */
10890 #define RTC_ALRMAR_MSK1               RTC_ALRMAR_MSK1_Msk
10891 #define RTC_ALRMAR_ST_Pos             (4U)
10892 #define RTC_ALRMAR_ST_Msk             (0x7UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000070 */
10893 #define RTC_ALRMAR_ST                 RTC_ALRMAR_ST_Msk
10894 #define RTC_ALRMAR_ST_0               (0x1UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000010 */
10895 #define RTC_ALRMAR_ST_1               (0x2UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000020 */
10896 #define RTC_ALRMAR_ST_2               (0x4UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000040 */
10897 #define RTC_ALRMAR_SU_Pos             (0U)
10898 #define RTC_ALRMAR_SU_Msk             (0xFUL << RTC_ALRMAR_SU_Pos)              /*!< 0x0000000F */
10899 #define RTC_ALRMAR_SU                 RTC_ALRMAR_SU_Msk
10900 #define RTC_ALRMAR_SU_0               (0x1UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000001 */
10901 #define RTC_ALRMAR_SU_1               (0x2UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000002 */
10902 #define RTC_ALRMAR_SU_2               (0x4UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000004 */
10903 #define RTC_ALRMAR_SU_3               (0x8UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000008 */
10904 
10905 /********************  Bits definition for RTC_ALRMBR register  ***************/
10906 #define RTC_ALRMBR_MSK4_Pos           (31U)
10907 #define RTC_ALRMBR_MSK4_Msk           (0x1UL << RTC_ALRMBR_MSK4_Pos)            /*!< 0x80000000 */
10908 #define RTC_ALRMBR_MSK4               RTC_ALRMBR_MSK4_Msk
10909 #define RTC_ALRMBR_WDSEL_Pos          (30U)
10910 #define RTC_ALRMBR_WDSEL_Msk          (0x1UL << RTC_ALRMBR_WDSEL_Pos)           /*!< 0x40000000 */
10911 #define RTC_ALRMBR_WDSEL              RTC_ALRMBR_WDSEL_Msk
10912 #define RTC_ALRMBR_DT_Pos             (28U)
10913 #define RTC_ALRMBR_DT_Msk             (0x3UL << RTC_ALRMBR_DT_Pos)              /*!< 0x30000000 */
10914 #define RTC_ALRMBR_DT                 RTC_ALRMBR_DT_Msk
10915 #define RTC_ALRMBR_DT_0               (0x1UL << RTC_ALRMBR_DT_Pos)              /*!< 0x10000000 */
10916 #define RTC_ALRMBR_DT_1               (0x2UL << RTC_ALRMBR_DT_Pos)              /*!< 0x20000000 */
10917 #define RTC_ALRMBR_DU_Pos             (24U)
10918 #define RTC_ALRMBR_DU_Msk             (0xFUL << RTC_ALRMBR_DU_Pos)              /*!< 0x0F000000 */
10919 #define RTC_ALRMBR_DU                 RTC_ALRMBR_DU_Msk
10920 #define RTC_ALRMBR_DU_0               (0x1UL << RTC_ALRMBR_DU_Pos)              /*!< 0x01000000 */
10921 #define RTC_ALRMBR_DU_1               (0x2UL << RTC_ALRMBR_DU_Pos)              /*!< 0x02000000 */
10922 #define RTC_ALRMBR_DU_2               (0x4UL << RTC_ALRMBR_DU_Pos)              /*!< 0x04000000 */
10923 #define RTC_ALRMBR_DU_3               (0x8UL << RTC_ALRMBR_DU_Pos)              /*!< 0x08000000 */
10924 #define RTC_ALRMBR_MSK3_Pos           (23U)
10925 #define RTC_ALRMBR_MSK3_Msk           (0x1UL << RTC_ALRMBR_MSK3_Pos)            /*!< 0x00800000 */
10926 #define RTC_ALRMBR_MSK3               RTC_ALRMBR_MSK3_Msk
10927 #define RTC_ALRMBR_PM_Pos             (22U)
10928 #define RTC_ALRMBR_PM_Msk             (0x1UL << RTC_ALRMBR_PM_Pos)              /*!< 0x00400000 */
10929 #define RTC_ALRMBR_PM                 RTC_ALRMBR_PM_Msk
10930 #define RTC_ALRMBR_HT_Pos             (20U)
10931 #define RTC_ALRMBR_HT_Msk             (0x3UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00300000 */
10932 #define RTC_ALRMBR_HT                 RTC_ALRMBR_HT_Msk
10933 #define RTC_ALRMBR_HT_0               (0x1UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00100000 */
10934 #define RTC_ALRMBR_HT_1               (0x2UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00200000 */
10935 #define RTC_ALRMBR_HU_Pos             (16U)
10936 #define RTC_ALRMBR_HU_Msk             (0xFUL << RTC_ALRMBR_HU_Pos)              /*!< 0x000F0000 */
10937 #define RTC_ALRMBR_HU                 RTC_ALRMBR_HU_Msk
10938 #define RTC_ALRMBR_HU_0               (0x1UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00010000 */
10939 #define RTC_ALRMBR_HU_1               (0x2UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00020000 */
10940 #define RTC_ALRMBR_HU_2               (0x4UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00040000 */
10941 #define RTC_ALRMBR_HU_3               (0x8UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00080000 */
10942 #define RTC_ALRMBR_MSK2_Pos           (15U)
10943 #define RTC_ALRMBR_MSK2_Msk           (0x1UL << RTC_ALRMBR_MSK2_Pos)            /*!< 0x00008000 */
10944 #define RTC_ALRMBR_MSK2               RTC_ALRMBR_MSK2_Msk
10945 #define RTC_ALRMBR_MNT_Pos            (12U)
10946 #define RTC_ALRMBR_MNT_Msk            (0x7UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00007000 */
10947 #define RTC_ALRMBR_MNT                RTC_ALRMBR_MNT_Msk
10948 #define RTC_ALRMBR_MNT_0              (0x1UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00001000 */
10949 #define RTC_ALRMBR_MNT_1              (0x2UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00002000 */
10950 #define RTC_ALRMBR_MNT_2              (0x4UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00004000 */
10951 #define RTC_ALRMBR_MNU_Pos            (8U)
10952 #define RTC_ALRMBR_MNU_Msk            (0xFUL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000F00 */
10953 #define RTC_ALRMBR_MNU                RTC_ALRMBR_MNU_Msk
10954 #define RTC_ALRMBR_MNU_0              (0x1UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000100 */
10955 #define RTC_ALRMBR_MNU_1              (0x2UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000200 */
10956 #define RTC_ALRMBR_MNU_2              (0x4UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000400 */
10957 #define RTC_ALRMBR_MNU_3              (0x8UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000800 */
10958 #define RTC_ALRMBR_MSK1_Pos           (7U)
10959 #define RTC_ALRMBR_MSK1_Msk           (0x1UL << RTC_ALRMBR_MSK1_Pos)            /*!< 0x00000080 */
10960 #define RTC_ALRMBR_MSK1               RTC_ALRMBR_MSK1_Msk
10961 #define RTC_ALRMBR_ST_Pos             (4U)
10962 #define RTC_ALRMBR_ST_Msk             (0x7UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000070 */
10963 #define RTC_ALRMBR_ST                 RTC_ALRMBR_ST_Msk
10964 #define RTC_ALRMBR_ST_0               (0x1UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000010 */
10965 #define RTC_ALRMBR_ST_1               (0x2UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000020 */
10966 #define RTC_ALRMBR_ST_2               (0x4UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000040 */
10967 #define RTC_ALRMBR_SU_Pos             (0U)
10968 #define RTC_ALRMBR_SU_Msk             (0xFUL << RTC_ALRMBR_SU_Pos)              /*!< 0x0000000F */
10969 #define RTC_ALRMBR_SU                 RTC_ALRMBR_SU_Msk
10970 #define RTC_ALRMBR_SU_0               (0x1UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000001 */
10971 #define RTC_ALRMBR_SU_1               (0x2UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000002 */
10972 #define RTC_ALRMBR_SU_2               (0x4UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000004 */
10973 #define RTC_ALRMBR_SU_3               (0x8UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000008 */
10974 
10975 /********************  Bits definition for RTC_WPR register  ******************/
10976 #define RTC_WPR_KEY_Pos               (0U)
10977 #define RTC_WPR_KEY_Msk               (0xFFUL << RTC_WPR_KEY_Pos)               /*!< 0x000000FF */
10978 #define RTC_WPR_KEY                   RTC_WPR_KEY_Msk
10979 
10980 /********************  Bits definition for RTC_SSR register  ******************/
10981 #define RTC_SSR_SS_Pos                (0U)
10982 #define RTC_SSR_SS_Msk                (0xFFFFUL << RTC_SSR_SS_Pos)              /*!< 0x0000FFFF */
10983 #define RTC_SSR_SS                    RTC_SSR_SS_Msk
10984 
10985 /********************  Bits definition for RTC_SHIFTR register  ***************/
10986 #define RTC_SHIFTR_SUBFS_Pos          (0U)
10987 #define RTC_SHIFTR_SUBFS_Msk          (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)        /*!< 0x00007FFF */
10988 #define RTC_SHIFTR_SUBFS              RTC_SHIFTR_SUBFS_Msk
10989 #define RTC_SHIFTR_ADD1S_Pos          (31U)
10990 #define RTC_SHIFTR_ADD1S_Msk          (0x1UL << RTC_SHIFTR_ADD1S_Pos)           /*!< 0x80000000 */
10991 #define RTC_SHIFTR_ADD1S              RTC_SHIFTR_ADD1S_Msk
10992 
10993 /********************  Bits definition for RTC_TSTR register  *****************/
10994 #define RTC_TSTR_PM_Pos               (22U)
10995 #define RTC_TSTR_PM_Msk               (0x1UL << RTC_TSTR_PM_Pos)                /*!< 0x00400000 */
10996 #define RTC_TSTR_PM                   RTC_TSTR_PM_Msk
10997 #define RTC_TSTR_HT_Pos               (20U)
10998 #define RTC_TSTR_HT_Msk               (0x3UL << RTC_TSTR_HT_Pos)                /*!< 0x00300000 */
10999 #define RTC_TSTR_HT                   RTC_TSTR_HT_Msk
11000 #define RTC_TSTR_HT_0                 (0x1UL << RTC_TSTR_HT_Pos)                /*!< 0x00100000 */
11001 #define RTC_TSTR_HT_1                 (0x2UL << RTC_TSTR_HT_Pos)                /*!< 0x00200000 */
11002 #define RTC_TSTR_HU_Pos               (16U)
11003 #define RTC_TSTR_HU_Msk               (0xFUL << RTC_TSTR_HU_Pos)                /*!< 0x000F0000 */
11004 #define RTC_TSTR_HU                   RTC_TSTR_HU_Msk
11005 #define RTC_TSTR_HU_0                 (0x1UL << RTC_TSTR_HU_Pos)                /*!< 0x00010000 */
11006 #define RTC_TSTR_HU_1                 (0x2UL << RTC_TSTR_HU_Pos)                /*!< 0x00020000 */
11007 #define RTC_TSTR_HU_2                 (0x4UL << RTC_TSTR_HU_Pos)                /*!< 0x00040000 */
11008 #define RTC_TSTR_HU_3                 (0x8UL << RTC_TSTR_HU_Pos)                /*!< 0x00080000 */
11009 #define RTC_TSTR_MNT_Pos              (12U)
11010 #define RTC_TSTR_MNT_Msk              (0x7UL << RTC_TSTR_MNT_Pos)               /*!< 0x00007000 */
11011 #define RTC_TSTR_MNT                  RTC_TSTR_MNT_Msk
11012 #define RTC_TSTR_MNT_0                (0x1UL << RTC_TSTR_MNT_Pos)               /*!< 0x00001000 */
11013 #define RTC_TSTR_MNT_1                (0x2UL << RTC_TSTR_MNT_Pos)               /*!< 0x00002000 */
11014 #define RTC_TSTR_MNT_2                (0x4UL << RTC_TSTR_MNT_Pos)               /*!< 0x00004000 */
11015 #define RTC_TSTR_MNU_Pos              (8U)
11016 #define RTC_TSTR_MNU_Msk              (0xFUL << RTC_TSTR_MNU_Pos)               /*!< 0x00000F00 */
11017 #define RTC_TSTR_MNU                  RTC_TSTR_MNU_Msk
11018 #define RTC_TSTR_MNU_0                (0x1UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000100 */
11019 #define RTC_TSTR_MNU_1                (0x2UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000200 */
11020 #define RTC_TSTR_MNU_2                (0x4UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000400 */
11021 #define RTC_TSTR_MNU_3                (0x8UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000800 */
11022 #define RTC_TSTR_ST_Pos               (4U)
11023 #define RTC_TSTR_ST_Msk               (0x7UL << RTC_TSTR_ST_Pos)                /*!< 0x00000070 */
11024 #define RTC_TSTR_ST                   RTC_TSTR_ST_Msk
11025 #define RTC_TSTR_ST_0                 (0x1UL << RTC_TSTR_ST_Pos)                /*!< 0x00000010 */
11026 #define RTC_TSTR_ST_1                 (0x2UL << RTC_TSTR_ST_Pos)                /*!< 0x00000020 */
11027 #define RTC_TSTR_ST_2                 (0x4UL << RTC_TSTR_ST_Pos)                /*!< 0x00000040 */
11028 #define RTC_TSTR_SU_Pos               (0U)
11029 #define RTC_TSTR_SU_Msk               (0xFUL << RTC_TSTR_SU_Pos)                /*!< 0x0000000F */
11030 #define RTC_TSTR_SU                   RTC_TSTR_SU_Msk
11031 #define RTC_TSTR_SU_0                 (0x1UL << RTC_TSTR_SU_Pos)                /*!< 0x00000001 */
11032 #define RTC_TSTR_SU_1                 (0x2UL << RTC_TSTR_SU_Pos)                /*!< 0x00000002 */
11033 #define RTC_TSTR_SU_2                 (0x4UL << RTC_TSTR_SU_Pos)                /*!< 0x00000004 */
11034 #define RTC_TSTR_SU_3                 (0x8UL << RTC_TSTR_SU_Pos)                /*!< 0x00000008 */
11035 
11036 /********************  Bits definition for RTC_TSDR register  *****************/
11037 #define RTC_TSDR_WDU_Pos              (13U)
11038 #define RTC_TSDR_WDU_Msk              (0x7UL << RTC_TSDR_WDU_Pos)               /*!< 0x0000E000 */
11039 #define RTC_TSDR_WDU                  RTC_TSDR_WDU_Msk
11040 #define RTC_TSDR_WDU_0                (0x1UL << RTC_TSDR_WDU_Pos)               /*!< 0x00002000 */
11041 #define RTC_TSDR_WDU_1                (0x2UL << RTC_TSDR_WDU_Pos)               /*!< 0x00004000 */
11042 #define RTC_TSDR_WDU_2                (0x4UL << RTC_TSDR_WDU_Pos)               /*!< 0x00008000 */
11043 #define RTC_TSDR_MT_Pos               (12U)
11044 #define RTC_TSDR_MT_Msk               (0x1UL << RTC_TSDR_MT_Pos)                /*!< 0x00001000 */
11045 #define RTC_TSDR_MT                   RTC_TSDR_MT_Msk
11046 #define RTC_TSDR_MU_Pos               (8U)
11047 #define RTC_TSDR_MU_Msk               (0xFUL << RTC_TSDR_MU_Pos)                /*!< 0x00000F00 */
11048 #define RTC_TSDR_MU                   RTC_TSDR_MU_Msk
11049 #define RTC_TSDR_MU_0                 (0x1UL << RTC_TSDR_MU_Pos)                /*!< 0x00000100 */
11050 #define RTC_TSDR_MU_1                 (0x2UL << RTC_TSDR_MU_Pos)                /*!< 0x00000200 */
11051 #define RTC_TSDR_MU_2                 (0x4UL << RTC_TSDR_MU_Pos)                /*!< 0x00000400 */
11052 #define RTC_TSDR_MU_3                 (0x8UL << RTC_TSDR_MU_Pos)                /*!< 0x00000800 */
11053 #define RTC_TSDR_DT_Pos               (4U)
11054 #define RTC_TSDR_DT_Msk               (0x3UL << RTC_TSDR_DT_Pos)                /*!< 0x00000030 */
11055 #define RTC_TSDR_DT                   RTC_TSDR_DT_Msk
11056 #define RTC_TSDR_DT_0                 (0x1UL << RTC_TSDR_DT_Pos)                /*!< 0x00000010 */
11057 #define RTC_TSDR_DT_1                 (0x2UL << RTC_TSDR_DT_Pos)                /*!< 0x00000020 */
11058 #define RTC_TSDR_DU_Pos               (0U)
11059 #define RTC_TSDR_DU_Msk               (0xFUL << RTC_TSDR_DU_Pos)                /*!< 0x0000000F */
11060 #define RTC_TSDR_DU                   RTC_TSDR_DU_Msk
11061 #define RTC_TSDR_DU_0                 (0x1UL << RTC_TSDR_DU_Pos)                /*!< 0x00000001 */
11062 #define RTC_TSDR_DU_1                 (0x2UL << RTC_TSDR_DU_Pos)                /*!< 0x00000002 */
11063 #define RTC_TSDR_DU_2                 (0x4UL << RTC_TSDR_DU_Pos)                /*!< 0x00000004 */
11064 #define RTC_TSDR_DU_3                 (0x8UL << RTC_TSDR_DU_Pos)                /*!< 0x00000008 */
11065 
11066 /********************  Bits definition for RTC_TSSSR register  ****************/
11067 #define RTC_TSSSR_SS_Pos              (0U)
11068 #define RTC_TSSSR_SS_Msk              (0xFFFFUL << RTC_TSSSR_SS_Pos)            /*!< 0x0000FFFF */
11069 #define RTC_TSSSR_SS                  RTC_TSSSR_SS_Msk
11070 
11071 /********************  Bits definition for RTC_CAL register  *****************/
11072 #define RTC_CALR_CALP_Pos             (15U)
11073 #define RTC_CALR_CALP_Msk             (0x1UL << RTC_CALR_CALP_Pos)              /*!< 0x00008000 */
11074 #define RTC_CALR_CALP                 RTC_CALR_CALP_Msk
11075 #define RTC_CALR_CALW8_Pos            (14U)
11076 #define RTC_CALR_CALW8_Msk            (0x1UL << RTC_CALR_CALW8_Pos)             /*!< 0x00004000 */
11077 #define RTC_CALR_CALW8                RTC_CALR_CALW8_Msk
11078 #define RTC_CALR_CALW16_Pos           (13U)
11079 #define RTC_CALR_CALW16_Msk           (0x1UL << RTC_CALR_CALW16_Pos)            /*!< 0x00002000 */
11080 #define RTC_CALR_CALW16               RTC_CALR_CALW16_Msk
11081 #define RTC_CALR_CALM_Pos             (0U)
11082 #define RTC_CALR_CALM_Msk             (0x1FFUL << RTC_CALR_CALM_Pos)            /*!< 0x000001FF */
11083 #define RTC_CALR_CALM                 RTC_CALR_CALM_Msk
11084 #define RTC_CALR_CALM_0               (0x001UL << RTC_CALR_CALM_Pos)            /*!< 0x00000001 */
11085 #define RTC_CALR_CALM_1               (0x002UL << RTC_CALR_CALM_Pos)            /*!< 0x00000002 */
11086 #define RTC_CALR_CALM_2               (0x004UL << RTC_CALR_CALM_Pos)            /*!< 0x00000004 */
11087 #define RTC_CALR_CALM_3               (0x008UL << RTC_CALR_CALM_Pos)            /*!< 0x00000008 */
11088 #define RTC_CALR_CALM_4               (0x010UL << RTC_CALR_CALM_Pos)            /*!< 0x00000010 */
11089 #define RTC_CALR_CALM_5               (0x020UL << RTC_CALR_CALM_Pos)            /*!< 0x00000020 */
11090 #define RTC_CALR_CALM_6               (0x040UL << RTC_CALR_CALM_Pos)            /*!< 0x00000040 */
11091 #define RTC_CALR_CALM_7               (0x080UL << RTC_CALR_CALM_Pos)            /*!< 0x00000080 */
11092 #define RTC_CALR_CALM_8               (0x100UL << RTC_CALR_CALM_Pos)            /*!< 0x00000100 */
11093 
11094 /********************  Bits definition for RTC_TAFCR register  ****************/
11095 #define RTC_TAFCR_ALARMOUTTYPE_Pos    (18U)
11096 #define RTC_TAFCR_ALARMOUTTYPE_Msk    (0x1UL << RTC_TAFCR_ALARMOUTTYPE_Pos)     /*!< 0x00040000 */
11097 #define RTC_TAFCR_ALARMOUTTYPE        RTC_TAFCR_ALARMOUTTYPE_Msk
11098 #define RTC_TAFCR_TSINSEL_Pos         (17U)
11099 #define RTC_TAFCR_TSINSEL_Msk         (0x1UL << RTC_TAFCR_TSINSEL_Pos)          /*!< 0x00020000 */
11100 #define RTC_TAFCR_TSINSEL             RTC_TAFCR_TSINSEL_Msk
11101 #define RTC_TAFCR_TAMP1INSEL_Pos      (16U)
11102 #define RTC_TAFCR_TAMP1INSEL_Msk      (0x1UL << RTC_TAFCR_TAMP1INSEL_Pos)        /*!< 0x00010000 */
11103 #define RTC_TAFCR_TAMP1INSEL          RTC_TAFCR_TAMP1INSEL_Msk
11104 #define RTC_TAFCR_TAMPPUDIS_Pos       (15U)
11105 #define RTC_TAFCR_TAMPPUDIS_Msk       (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos)        /*!< 0x00008000 */
11106 #define RTC_TAFCR_TAMPPUDIS           RTC_TAFCR_TAMPPUDIS_Msk
11107 #define RTC_TAFCR_TAMPPRCH_Pos        (13U)
11108 #define RTC_TAFCR_TAMPPRCH_Msk        (0x3UL << RTC_TAFCR_TAMPPRCH_Pos)         /*!< 0x00006000 */
11109 #define RTC_TAFCR_TAMPPRCH            RTC_TAFCR_TAMPPRCH_Msk
11110 #define RTC_TAFCR_TAMPPRCH_0          (0x1UL << RTC_TAFCR_TAMPPRCH_Pos)         /*!< 0x00002000 */
11111 #define RTC_TAFCR_TAMPPRCH_1          (0x2UL << RTC_TAFCR_TAMPPRCH_Pos)         /*!< 0x00004000 */
11112 #define RTC_TAFCR_TAMPFLT_Pos         (11U)
11113 #define RTC_TAFCR_TAMPFLT_Msk         (0x3UL << RTC_TAFCR_TAMPFLT_Pos)          /*!< 0x00001800 */
11114 #define RTC_TAFCR_TAMPFLT             RTC_TAFCR_TAMPFLT_Msk
11115 #define RTC_TAFCR_TAMPFLT_0           (0x1UL << RTC_TAFCR_TAMPFLT_Pos)          /*!< 0x00000800 */
11116 #define RTC_TAFCR_TAMPFLT_1           (0x2UL << RTC_TAFCR_TAMPFLT_Pos)          /*!< 0x00001000 */
11117 #define RTC_TAFCR_TAMPFREQ_Pos        (8U)
11118 #define RTC_TAFCR_TAMPFREQ_Msk        (0x7UL << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000700 */
11119 #define RTC_TAFCR_TAMPFREQ            RTC_TAFCR_TAMPFREQ_Msk
11120 #define RTC_TAFCR_TAMPFREQ_0          (0x1UL << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000100 */
11121 #define RTC_TAFCR_TAMPFREQ_1          (0x2UL << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000200 */
11122 #define RTC_TAFCR_TAMPFREQ_2          (0x4UL << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000400 */
11123 #define RTC_TAFCR_TAMPTS_Pos          (7U)
11124 #define RTC_TAFCR_TAMPTS_Msk          (0x1UL << RTC_TAFCR_TAMPTS_Pos)           /*!< 0x00000080 */
11125 #define RTC_TAFCR_TAMPTS              RTC_TAFCR_TAMPTS_Msk
11126 #define RTC_TAFCR_TAMP2TRG_Pos        (4U)
11127 #define RTC_TAFCR_TAMP2TRG_Msk        (0x1UL << RTC_TAFCR_TAMP2TRG_Pos)         /*!< 0x00000010 */
11128 #define RTC_TAFCR_TAMP2TRG            RTC_TAFCR_TAMP2TRG_Msk
11129 #define RTC_TAFCR_TAMP2E_Pos          (3U)
11130 #define RTC_TAFCR_TAMP2E_Msk          (0x1UL << RTC_TAFCR_TAMP2E_Pos)           /*!< 0x00000008 */
11131 #define RTC_TAFCR_TAMP2E              RTC_TAFCR_TAMP2E_Msk
11132 #define RTC_TAFCR_TAMPIE_Pos          (2U)
11133 #define RTC_TAFCR_TAMPIE_Msk          (0x1UL << RTC_TAFCR_TAMPIE_Pos)           /*!< 0x00000004 */
11134 #define RTC_TAFCR_TAMPIE              RTC_TAFCR_TAMPIE_Msk
11135 #define RTC_TAFCR_TAMP1TRG_Pos        (1U)
11136 #define RTC_TAFCR_TAMP1TRG_Msk        (0x1UL << RTC_TAFCR_TAMP1TRG_Pos)         /*!< 0x00000002 */
11137 #define RTC_TAFCR_TAMP1TRG            RTC_TAFCR_TAMP1TRG_Msk
11138 #define RTC_TAFCR_TAMP1E_Pos          (0U)
11139 #define RTC_TAFCR_TAMP1E_Msk          (0x1UL << RTC_TAFCR_TAMP1E_Pos)           /*!< 0x00000001 */
11140 #define RTC_TAFCR_TAMP1E              RTC_TAFCR_TAMP1E_Msk
11141 
11142 /* Legacy defines */
11143 #define RTC_TAFCR_TAMPINSEL           RTC_TAFCR_TAMP1INSEL
11144 
11145 /********************  Bits definition for RTC_ALRMASSR register  *************/
11146 #define RTC_ALRMASSR_MASKSS_Pos       (24U)
11147 #define RTC_ALRMASSR_MASKSS_Msk       (0xFUL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x0F000000 */
11148 #define RTC_ALRMASSR_MASKSS           RTC_ALRMASSR_MASKSS_Msk
11149 #define RTC_ALRMASSR_MASKSS_0         (0x1UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x01000000 */
11150 #define RTC_ALRMASSR_MASKSS_1         (0x2UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x02000000 */
11151 #define RTC_ALRMASSR_MASKSS_2         (0x4UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x04000000 */
11152 #define RTC_ALRMASSR_MASKSS_3         (0x8UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x08000000 */
11153 #define RTC_ALRMASSR_SS_Pos           (0U)
11154 #define RTC_ALRMASSR_SS_Msk           (0x7FFFUL << RTC_ALRMASSR_SS_Pos)         /*!< 0x00007FFF */
11155 #define RTC_ALRMASSR_SS               RTC_ALRMASSR_SS_Msk
11156 
11157 /********************  Bits definition for RTC_ALRMBSSR register  *************/
11158 #define RTC_ALRMBSSR_MASKSS_Pos       (24U)
11159 #define RTC_ALRMBSSR_MASKSS_Msk       (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x0F000000 */
11160 #define RTC_ALRMBSSR_MASKSS           RTC_ALRMBSSR_MASKSS_Msk
11161 #define RTC_ALRMBSSR_MASKSS_0         (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x01000000 */
11162 #define RTC_ALRMBSSR_MASKSS_1         (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x02000000 */
11163 #define RTC_ALRMBSSR_MASKSS_2         (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x04000000 */
11164 #define RTC_ALRMBSSR_MASKSS_3         (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x08000000 */
11165 #define RTC_ALRMBSSR_SS_Pos           (0U)
11166 #define RTC_ALRMBSSR_SS_Msk           (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)         /*!< 0x00007FFF */
11167 #define RTC_ALRMBSSR_SS               RTC_ALRMBSSR_SS_Msk
11168 
11169 /********************  Bits definition for RTC_BKP0R register  ****************/
11170 #define RTC_BKP0R_Pos                 (0U)
11171 #define RTC_BKP0R_Msk                 (0xFFFFFFFFUL << RTC_BKP0R_Pos)           /*!< 0xFFFFFFFF */
11172 #define RTC_BKP0R                     RTC_BKP0R_Msk
11173 
11174 /********************  Bits definition for RTC_BKP1R register  ****************/
11175 #define RTC_BKP1R_Pos                 (0U)
11176 #define RTC_BKP1R_Msk                 (0xFFFFFFFFUL << RTC_BKP1R_Pos)           /*!< 0xFFFFFFFF */
11177 #define RTC_BKP1R                     RTC_BKP1R_Msk
11178 
11179 /********************  Bits definition for RTC_BKP2R register  ****************/
11180 #define RTC_BKP2R_Pos                 (0U)
11181 #define RTC_BKP2R_Msk                 (0xFFFFFFFFUL << RTC_BKP2R_Pos)           /*!< 0xFFFFFFFF */
11182 #define RTC_BKP2R                     RTC_BKP2R_Msk
11183 
11184 /********************  Bits definition for RTC_BKP3R register  ****************/
11185 #define RTC_BKP3R_Pos                 (0U)
11186 #define RTC_BKP3R_Msk                 (0xFFFFFFFFUL << RTC_BKP3R_Pos)           /*!< 0xFFFFFFFF */
11187 #define RTC_BKP3R                     RTC_BKP3R_Msk
11188 
11189 /********************  Bits definition for RTC_BKP4R register  ****************/
11190 #define RTC_BKP4R_Pos                 (0U)
11191 #define RTC_BKP4R_Msk                 (0xFFFFFFFFUL << RTC_BKP4R_Pos)           /*!< 0xFFFFFFFF */
11192 #define RTC_BKP4R                     RTC_BKP4R_Msk
11193 
11194 /********************  Bits definition for RTC_BKP5R register  ****************/
11195 #define RTC_BKP5R_Pos                 (0U)
11196 #define RTC_BKP5R_Msk                 (0xFFFFFFFFUL << RTC_BKP5R_Pos)           /*!< 0xFFFFFFFF */
11197 #define RTC_BKP5R                     RTC_BKP5R_Msk
11198 
11199 /********************  Bits definition for RTC_BKP6R register  ****************/
11200 #define RTC_BKP6R_Pos                 (0U)
11201 #define RTC_BKP6R_Msk                 (0xFFFFFFFFUL << RTC_BKP6R_Pos)           /*!< 0xFFFFFFFF */
11202 #define RTC_BKP6R                     RTC_BKP6R_Msk
11203 
11204 /********************  Bits definition for RTC_BKP7R register  ****************/
11205 #define RTC_BKP7R_Pos                 (0U)
11206 #define RTC_BKP7R_Msk                 (0xFFFFFFFFUL << RTC_BKP7R_Pos)           /*!< 0xFFFFFFFF */
11207 #define RTC_BKP7R                     RTC_BKP7R_Msk
11208 
11209 /********************  Bits definition for RTC_BKP8R register  ****************/
11210 #define RTC_BKP8R_Pos                 (0U)
11211 #define RTC_BKP8R_Msk                 (0xFFFFFFFFUL << RTC_BKP8R_Pos)           /*!< 0xFFFFFFFF */
11212 #define RTC_BKP8R                     RTC_BKP8R_Msk
11213 
11214 /********************  Bits definition for RTC_BKP9R register  ****************/
11215 #define RTC_BKP9R_Pos                 (0U)
11216 #define RTC_BKP9R_Msk                 (0xFFFFFFFFUL << RTC_BKP9R_Pos)           /*!< 0xFFFFFFFF */
11217 #define RTC_BKP9R                     RTC_BKP9R_Msk
11218 
11219 /********************  Bits definition for RTC_BKP10R register  ***************/
11220 #define RTC_BKP10R_Pos                (0U)
11221 #define RTC_BKP10R_Msk                (0xFFFFFFFFUL << RTC_BKP10R_Pos)          /*!< 0xFFFFFFFF */
11222 #define RTC_BKP10R                    RTC_BKP10R_Msk
11223 
11224 /********************  Bits definition for RTC_BKP11R register  ***************/
11225 #define RTC_BKP11R_Pos                (0U)
11226 #define RTC_BKP11R_Msk                (0xFFFFFFFFUL << RTC_BKP11R_Pos)          /*!< 0xFFFFFFFF */
11227 #define RTC_BKP11R                    RTC_BKP11R_Msk
11228 
11229 /********************  Bits definition for RTC_BKP12R register  ***************/
11230 #define RTC_BKP12R_Pos                (0U)
11231 #define RTC_BKP12R_Msk                (0xFFFFFFFFUL << RTC_BKP12R_Pos)          /*!< 0xFFFFFFFF */
11232 #define RTC_BKP12R                    RTC_BKP12R_Msk
11233 
11234 /********************  Bits definition for RTC_BKP13R register  ***************/
11235 #define RTC_BKP13R_Pos                (0U)
11236 #define RTC_BKP13R_Msk                (0xFFFFFFFFUL << RTC_BKP13R_Pos)          /*!< 0xFFFFFFFF */
11237 #define RTC_BKP13R                    RTC_BKP13R_Msk
11238 
11239 /********************  Bits definition for RTC_BKP14R register  ***************/
11240 #define RTC_BKP14R_Pos                (0U)
11241 #define RTC_BKP14R_Msk                (0xFFFFFFFFUL << RTC_BKP14R_Pos)          /*!< 0xFFFFFFFF */
11242 #define RTC_BKP14R                    RTC_BKP14R_Msk
11243 
11244 /********************  Bits definition for RTC_BKP15R register  ***************/
11245 #define RTC_BKP15R_Pos                (0U)
11246 #define RTC_BKP15R_Msk                (0xFFFFFFFFUL << RTC_BKP15R_Pos)          /*!< 0xFFFFFFFF */
11247 #define RTC_BKP15R                    RTC_BKP15R_Msk
11248 
11249 /********************  Bits definition for RTC_BKP16R register  ***************/
11250 #define RTC_BKP16R_Pos                (0U)
11251 #define RTC_BKP16R_Msk                (0xFFFFFFFFUL << RTC_BKP16R_Pos)          /*!< 0xFFFFFFFF */
11252 #define RTC_BKP16R                    RTC_BKP16R_Msk
11253 
11254 /********************  Bits definition for RTC_BKP17R register  ***************/
11255 #define RTC_BKP17R_Pos                (0U)
11256 #define RTC_BKP17R_Msk                (0xFFFFFFFFUL << RTC_BKP17R_Pos)          /*!< 0xFFFFFFFF */
11257 #define RTC_BKP17R                    RTC_BKP17R_Msk
11258 
11259 /********************  Bits definition for RTC_BKP18R register  ***************/
11260 #define RTC_BKP18R_Pos                (0U)
11261 #define RTC_BKP18R_Msk                (0xFFFFFFFFUL << RTC_BKP18R_Pos)          /*!< 0xFFFFFFFF */
11262 #define RTC_BKP18R                    RTC_BKP18R_Msk
11263 
11264 /********************  Bits definition for RTC_BKP19R register  ***************/
11265 #define RTC_BKP19R_Pos                (0U)
11266 #define RTC_BKP19R_Msk                (0xFFFFFFFFUL << RTC_BKP19R_Pos)          /*!< 0xFFFFFFFF */
11267 #define RTC_BKP19R                    RTC_BKP19R_Msk
11268 
11269 /******************** Number of backup registers ******************************/
11270 #define RTC_BKP_NUMBER                       0x000000014U
11271 
11272 /******************************************************************************/
11273 /*                                                                            */
11274 /*                          Serial Audio Interface                            */
11275 /*                                                                            */
11276 /******************************************************************************/
11277 /********************  Bit definition for SAI_GCR register  *******************/
11278 #define SAI_GCR_SYNCIN_Pos         (0U)
11279 #define SAI_GCR_SYNCIN_Msk         (0x3UL << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000003 */
11280 #define SAI_GCR_SYNCIN             SAI_GCR_SYNCIN_Msk                          /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */
11281 #define SAI_GCR_SYNCIN_0           (0x1UL << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000001 */
11282 #define SAI_GCR_SYNCIN_1           (0x2UL << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000002 */
11283 
11284 #define SAI_GCR_SYNCOUT_Pos        (4U)
11285 #define SAI_GCR_SYNCOUT_Msk        (0x3UL << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000030 */
11286 #define SAI_GCR_SYNCOUT            SAI_GCR_SYNCOUT_Msk                         /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
11287 #define SAI_GCR_SYNCOUT_0          (0x1UL << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000010 */
11288 #define SAI_GCR_SYNCOUT_1          (0x2UL << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000020 */
11289 
11290 /*******************  Bit definition for SAI_xCR1 register  *******************/
11291 #define SAI_xCR1_MODE_Pos          (0U)
11292 #define SAI_xCR1_MODE_Msk          (0x3UL << SAI_xCR1_MODE_Pos)                 /*!< 0x00000003 */
11293 #define SAI_xCR1_MODE              SAI_xCR1_MODE_Msk                           /*!<MODE[1:0] bits (Audio Block Mode)           */
11294 #define SAI_xCR1_MODE_0            (0x1UL << SAI_xCR1_MODE_Pos)                 /*!< 0x00000001 */
11295 #define SAI_xCR1_MODE_1            (0x2UL << SAI_xCR1_MODE_Pos)                 /*!< 0x00000002 */
11296 
11297 #define SAI_xCR1_PRTCFG_Pos        (2U)
11298 #define SAI_xCR1_PRTCFG_Msk        (0x3UL << SAI_xCR1_PRTCFG_Pos)               /*!< 0x0000000C */
11299 #define SAI_xCR1_PRTCFG            SAI_xCR1_PRTCFG_Msk                         /*!<PRTCFG[1:0] bits (Protocol Configuration)   */
11300 #define SAI_xCR1_PRTCFG_0          (0x1UL << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000004 */
11301 #define SAI_xCR1_PRTCFG_1          (0x2UL << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000008 */
11302 
11303 #define SAI_xCR1_DS_Pos            (5U)
11304 #define SAI_xCR1_DS_Msk            (0x7UL << SAI_xCR1_DS_Pos)                   /*!< 0x000000E0 */
11305 #define SAI_xCR1_DS                SAI_xCR1_DS_Msk                             /*!<DS[1:0] bits (Data Size) */
11306 #define SAI_xCR1_DS_0              (0x1UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000020 */
11307 #define SAI_xCR1_DS_1              (0x2UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000040 */
11308 #define SAI_xCR1_DS_2              (0x4UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000080 */
11309 
11310 #define SAI_xCR1_LSBFIRST_Pos      (8U)
11311 #define SAI_xCR1_LSBFIRST_Msk      (0x1UL << SAI_xCR1_LSBFIRST_Pos)             /*!< 0x00000100 */
11312 #define SAI_xCR1_LSBFIRST          SAI_xCR1_LSBFIRST_Msk                       /*!<LSB First Configuration  */
11313 #define SAI_xCR1_CKSTR_Pos         (9U)
11314 #define SAI_xCR1_CKSTR_Msk         (0x1UL << SAI_xCR1_CKSTR_Pos)                /*!< 0x00000200 */
11315 #define SAI_xCR1_CKSTR             SAI_xCR1_CKSTR_Msk                          /*!<ClocK STRobing edge      */
11316 
11317 #define SAI_xCR1_SYNCEN_Pos        (10U)
11318 #define SAI_xCR1_SYNCEN_Msk        (0x3UL << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000C00 */
11319 #define SAI_xCR1_SYNCEN            SAI_xCR1_SYNCEN_Msk                         /*!<SYNCEN[1:0](SYNChronization ENable) */
11320 #define SAI_xCR1_SYNCEN_0          (0x1UL << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000400 */
11321 #define SAI_xCR1_SYNCEN_1          (0x2UL << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000800 */
11322 
11323 #define SAI_xCR1_MONO_Pos          (12U)
11324 #define SAI_xCR1_MONO_Msk          (0x1UL << SAI_xCR1_MONO_Pos)                 /*!< 0x00001000 */
11325 #define SAI_xCR1_MONO              SAI_xCR1_MONO_Msk                           /*!<Mono mode                  */
11326 #define SAI_xCR1_OUTDRIV_Pos       (13U)
11327 #define SAI_xCR1_OUTDRIV_Msk       (0x1UL << SAI_xCR1_OUTDRIV_Pos)              /*!< 0x00002000 */
11328 #define SAI_xCR1_OUTDRIV           SAI_xCR1_OUTDRIV_Msk                        /*!<Output Drive               */
11329 #define SAI_xCR1_SAIEN_Pos         (16U)
11330 #define SAI_xCR1_SAIEN_Msk         (0x1UL << SAI_xCR1_SAIEN_Pos)                /*!< 0x00010000 */
11331 #define SAI_xCR1_SAIEN             SAI_xCR1_SAIEN_Msk                          /*!<Audio Block enable         */
11332 #define SAI_xCR1_DMAEN_Pos         (17U)
11333 #define SAI_xCR1_DMAEN_Msk         (0x1UL << SAI_xCR1_DMAEN_Pos)                /*!< 0x00020000 */
11334 #define SAI_xCR1_DMAEN             SAI_xCR1_DMAEN_Msk                          /*!<DMA enable                 */
11335 #define SAI_xCR1_NODIV_Pos         (19U)
11336 #define SAI_xCR1_NODIV_Msk         (0x1UL << SAI_xCR1_NODIV_Pos)                /*!< 0x00080000 */
11337 #define SAI_xCR1_NODIV             SAI_xCR1_NODIV_Msk                          /*!<No Divider Configuration   */
11338 
11339 #define SAI_xCR1_MCKDIV_Pos        (20U)
11340 #define SAI_xCR1_MCKDIV_Msk        (0xFUL << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00F00000 */
11341 #define SAI_xCR1_MCKDIV            SAI_xCR1_MCKDIV_Msk                         /*!<MCKDIV[3:0] (Master ClocK Divider)  */
11342 #define SAI_xCR1_MCKDIV_0          (0x1UL << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00100000 */
11343 #define SAI_xCR1_MCKDIV_1          (0x2UL << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00200000 */
11344 #define SAI_xCR1_MCKDIV_2          (0x4UL << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00400000 */
11345 #define SAI_xCR1_MCKDIV_3          (0x8UL << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00800000 */
11346 
11347 /*******************  Bit definition for SAI_xCR2 register  *******************/
11348 #define SAI_xCR2_FTH_Pos           (0U)
11349 #define SAI_xCR2_FTH_Msk           (0x7UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000007 */
11350 #define SAI_xCR2_FTH               SAI_xCR2_FTH_Msk                            /*!<FTH[2:0](Fifo THreshold)  */
11351 #define SAI_xCR2_FTH_0             (0x1UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000001 */
11352 #define SAI_xCR2_FTH_1             (0x2UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000002 */
11353 #define SAI_xCR2_FTH_2             (0x4UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000004 */
11354 
11355 #define SAI_xCR2_FFLUSH_Pos        (3U)
11356 #define SAI_xCR2_FFLUSH_Msk        (0x1UL << SAI_xCR2_FFLUSH_Pos)               /*!< 0x00000008 */
11357 #define SAI_xCR2_FFLUSH            SAI_xCR2_FFLUSH_Msk                         /*!<Fifo FLUSH                       */
11358 #define SAI_xCR2_TRIS_Pos          (4U)
11359 #define SAI_xCR2_TRIS_Msk          (0x1UL << SAI_xCR2_TRIS_Pos)                 /*!< 0x00000010 */
11360 #define SAI_xCR2_TRIS              SAI_xCR2_TRIS_Msk                           /*!<TRIState Management on data line */
11361 #define SAI_xCR2_MUTE_Pos          (5U)
11362 #define SAI_xCR2_MUTE_Msk          (0x1UL << SAI_xCR2_MUTE_Pos)                 /*!< 0x00000020 */
11363 #define SAI_xCR2_MUTE              SAI_xCR2_MUTE_Msk                           /*!<Mute mode                        */
11364 #define SAI_xCR2_MUTEVAL_Pos       (6U)
11365 #define SAI_xCR2_MUTEVAL_Msk       (0x1UL << SAI_xCR2_MUTEVAL_Pos)              /*!< 0x00000040 */
11366 #define SAI_xCR2_MUTEVAL           SAI_xCR2_MUTEVAL_Msk                        /*!<Muate value                      */
11367 
11368 #define SAI_xCR2_MUTECNT_Pos       (7U)
11369 #define SAI_xCR2_MUTECNT_Msk       (0x3FUL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00001F80 */
11370 #define SAI_xCR2_MUTECNT           SAI_xCR2_MUTECNT_Msk                        /*!<MUTECNT[5:0] (MUTE counter) */
11371 #define SAI_xCR2_MUTECNT_0         (0x01UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000080 */
11372 #define SAI_xCR2_MUTECNT_1         (0x02UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000100 */
11373 #define SAI_xCR2_MUTECNT_2         (0x04UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000200 */
11374 #define SAI_xCR2_MUTECNT_3         (0x08UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000400 */
11375 #define SAI_xCR2_MUTECNT_4         (0x10UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000800 */
11376 #define SAI_xCR2_MUTECNT_5         (0x20UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00001000 */
11377 
11378 #define SAI_xCR2_CPL_Pos           (13U)
11379 #define SAI_xCR2_CPL_Msk           (0x1UL << SAI_xCR2_CPL_Pos)                  /*!< 0x00002000 */
11380 #define SAI_xCR2_CPL               SAI_xCR2_CPL_Msk                            /*!< Complement Bit             */
11381 
11382 #define SAI_xCR2_COMP_Pos          (14U)
11383 #define SAI_xCR2_COMP_Msk          (0x3UL << SAI_xCR2_COMP_Pos)                 /*!< 0x0000C000 */
11384 #define SAI_xCR2_COMP              SAI_xCR2_COMP_Msk                           /*!<COMP[1:0] (Companding mode) */
11385 #define SAI_xCR2_COMP_0            (0x1UL << SAI_xCR2_COMP_Pos)                 /*!< 0x00004000 */
11386 #define SAI_xCR2_COMP_1            (0x2UL << SAI_xCR2_COMP_Pos)                 /*!< 0x00008000 */
11387 
11388 /******************  Bit definition for SAI_xFRCR register  *******************/
11389 #define SAI_xFRCR_FRL_Pos          (0U)
11390 #define SAI_xFRCR_FRL_Msk          (0xFFUL << SAI_xFRCR_FRL_Pos)                /*!< 0x000000FF */
11391 #define SAI_xFRCR_FRL              SAI_xFRCR_FRL_Msk                           /*!<FRL[7:0](Frame length)  */
11392 #define SAI_xFRCR_FRL_0            (0x01UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000001 */
11393 #define SAI_xFRCR_FRL_1            (0x02UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000002 */
11394 #define SAI_xFRCR_FRL_2            (0x04UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000004 */
11395 #define SAI_xFRCR_FRL_3            (0x08UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000008 */
11396 #define SAI_xFRCR_FRL_4            (0x10UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000010 */
11397 #define SAI_xFRCR_FRL_5            (0x20UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000020 */
11398 #define SAI_xFRCR_FRL_6            (0x40UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000040 */
11399 #define SAI_xFRCR_FRL_7            (0x80UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000080 */
11400 
11401 #define SAI_xFRCR_FSALL_Pos        (8U)
11402 #define SAI_xFRCR_FSALL_Msk        (0x7FUL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00007F00 */
11403 #define SAI_xFRCR_FSALL            SAI_xFRCR_FSALL_Msk                         /*!<FRL[6:0] (Frame synchronization active level length)  */
11404 #define SAI_xFRCR_FSALL_0          (0x01UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000100 */
11405 #define SAI_xFRCR_FSALL_1          (0x02UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000200 */
11406 #define SAI_xFRCR_FSALL_2          (0x04UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000400 */
11407 #define SAI_xFRCR_FSALL_3          (0x08UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000800 */
11408 #define SAI_xFRCR_FSALL_4          (0x10UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00001000 */
11409 #define SAI_xFRCR_FSALL_5          (0x20UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00002000 */
11410 #define SAI_xFRCR_FSALL_6          (0x40UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00004000 */
11411 
11412 #define SAI_xFRCR_FSDEF_Pos        (16U)
11413 #define SAI_xFRCR_FSDEF_Msk        (0x1UL << SAI_xFRCR_FSDEF_Pos)               /*!< 0x00010000 */
11414 #define SAI_xFRCR_FSDEF            SAI_xFRCR_FSDEF_Msk                         /*!< Frame Synchronization Definition */
11415 #define SAI_xFRCR_FSPOL_Pos        (17U)
11416 #define SAI_xFRCR_FSPOL_Msk        (0x1UL << SAI_xFRCR_FSPOL_Pos)               /*!< 0x00020000 */
11417 #define SAI_xFRCR_FSPOL            SAI_xFRCR_FSPOL_Msk                         /*!<Frame Synchronization POLarity    */
11418 #define SAI_xFRCR_FSOFF_Pos        (18U)
11419 #define SAI_xFRCR_FSOFF_Msk        (0x1UL << SAI_xFRCR_FSOFF_Pos)               /*!< 0x00040000 */
11420 #define SAI_xFRCR_FSOFF            SAI_xFRCR_FSOFF_Msk                         /*!<Frame Synchronization OFFset      */
11421 /* Legacy defines */
11422 #define  SAI_xFRCR_FSPO                   SAI_xFRCR_FSPOL
11423 
11424 /******************  Bit definition for SAI_xSLOTR register  *******************/
11425 #define SAI_xSLOTR_FBOFF_Pos       (0U)
11426 #define SAI_xSLOTR_FBOFF_Msk       (0x1FUL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x0000001F */
11427 #define SAI_xSLOTR_FBOFF           SAI_xSLOTR_FBOFF_Msk                        /*!<FRL[4:0](First Bit Offset)  */
11428 #define SAI_xSLOTR_FBOFF_0         (0x01UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000001 */
11429 #define SAI_xSLOTR_FBOFF_1         (0x02UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000002 */
11430 #define SAI_xSLOTR_FBOFF_2         (0x04UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000004 */
11431 #define SAI_xSLOTR_FBOFF_3         (0x08UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000008 */
11432 #define SAI_xSLOTR_FBOFF_4         (0x10UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000010 */
11433 
11434 #define SAI_xSLOTR_SLOTSZ_Pos      (6U)
11435 #define SAI_xSLOTR_SLOTSZ_Msk      (0x3UL << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x000000C0 */
11436 #define SAI_xSLOTR_SLOTSZ          SAI_xSLOTR_SLOTSZ_Msk                       /*!<SLOTSZ[1:0] (Slot size)  */
11437 #define SAI_xSLOTR_SLOTSZ_0        (0x1UL << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000040 */
11438 #define SAI_xSLOTR_SLOTSZ_1        (0x2UL << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000080 */
11439 
11440 #define SAI_xSLOTR_NBSLOT_Pos      (8U)
11441 #define SAI_xSLOTR_NBSLOT_Msk      (0xFUL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000F00 */
11442 #define SAI_xSLOTR_NBSLOT          SAI_xSLOTR_NBSLOT_Msk                       /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */
11443 #define SAI_xSLOTR_NBSLOT_0        (0x1UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000100 */
11444 #define SAI_xSLOTR_NBSLOT_1        (0x2UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000200 */
11445 #define SAI_xSLOTR_NBSLOT_2        (0x4UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000400 */
11446 #define SAI_xSLOTR_NBSLOT_3        (0x8UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000800 */
11447 
11448 #define SAI_xSLOTR_SLOTEN_Pos      (16U)
11449 #define SAI_xSLOTR_SLOTEN_Msk      (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos)          /*!< 0xFFFF0000 */
11450 #define SAI_xSLOTR_SLOTEN          SAI_xSLOTR_SLOTEN_Msk                       /*!<SLOTEN[15:0] (Slot Enable)  */
11451 
11452 /*******************  Bit definition for SAI_xIMR register  *******************/
11453 #define SAI_xIMR_OVRUDRIE_Pos      (0U)
11454 #define SAI_xIMR_OVRUDRIE_Msk      (0x1UL << SAI_xIMR_OVRUDRIE_Pos)             /*!< 0x00000001 */
11455 #define SAI_xIMR_OVRUDRIE          SAI_xIMR_OVRUDRIE_Msk                       /*!<Overrun underrun interrupt enable                              */
11456 #define SAI_xIMR_MUTEDETIE_Pos     (1U)
11457 #define SAI_xIMR_MUTEDETIE_Msk     (0x1UL << SAI_xIMR_MUTEDETIE_Pos)            /*!< 0x00000002 */
11458 #define SAI_xIMR_MUTEDETIE         SAI_xIMR_MUTEDETIE_Msk                      /*!<Mute detection interrupt enable                                */
11459 #define SAI_xIMR_WCKCFGIE_Pos      (2U)
11460 #define SAI_xIMR_WCKCFGIE_Msk      (0x1UL << SAI_xIMR_WCKCFGIE_Pos)             /*!< 0x00000004 */
11461 #define SAI_xIMR_WCKCFGIE          SAI_xIMR_WCKCFGIE_Msk                       /*!<Wrong Clock Configuration interrupt enable                     */
11462 #define SAI_xIMR_FREQIE_Pos        (3U)
11463 #define SAI_xIMR_FREQIE_Msk        (0x1UL << SAI_xIMR_FREQIE_Pos)               /*!< 0x00000008 */
11464 #define SAI_xIMR_FREQIE            SAI_xIMR_FREQIE_Msk                         /*!<FIFO request interrupt enable                                  */
11465 #define SAI_xIMR_CNRDYIE_Pos       (4U)
11466 #define SAI_xIMR_CNRDYIE_Msk       (0x1UL << SAI_xIMR_CNRDYIE_Pos)              /*!< 0x00000010 */
11467 #define SAI_xIMR_CNRDYIE           SAI_xIMR_CNRDYIE_Msk                        /*!<Codec not ready interrupt enable                               */
11468 #define SAI_xIMR_AFSDETIE_Pos      (5U)
11469 #define SAI_xIMR_AFSDETIE_Msk      (0x1UL << SAI_xIMR_AFSDETIE_Pos)             /*!< 0x00000020 */
11470 #define SAI_xIMR_AFSDETIE          SAI_xIMR_AFSDETIE_Msk                       /*!<Anticipated frame synchronization detection interrupt enable   */
11471 #define SAI_xIMR_LFSDETIE_Pos      (6U)
11472 #define SAI_xIMR_LFSDETIE_Msk      (0x1UL << SAI_xIMR_LFSDETIE_Pos)             /*!< 0x00000040 */
11473 #define SAI_xIMR_LFSDETIE          SAI_xIMR_LFSDETIE_Msk                       /*!<Late frame synchronization detection interrupt enable          */
11474 
11475 /********************  Bit definition for SAI_xSR register  *******************/
11476 #define SAI_xSR_OVRUDR_Pos         (0U)
11477 #define SAI_xSR_OVRUDR_Msk         (0x1UL << SAI_xSR_OVRUDR_Pos)                /*!< 0x00000001 */
11478 #define SAI_xSR_OVRUDR             SAI_xSR_OVRUDR_Msk                          /*!<Overrun underrun                               */
11479 #define SAI_xSR_MUTEDET_Pos        (1U)
11480 #define SAI_xSR_MUTEDET_Msk        (0x1UL << SAI_xSR_MUTEDET_Pos)               /*!< 0x00000002 */
11481 #define SAI_xSR_MUTEDET            SAI_xSR_MUTEDET_Msk                         /*!<Mute detection                                 */
11482 #define SAI_xSR_WCKCFG_Pos         (2U)
11483 #define SAI_xSR_WCKCFG_Msk         (0x1UL << SAI_xSR_WCKCFG_Pos)                /*!< 0x00000004 */
11484 #define SAI_xSR_WCKCFG             SAI_xSR_WCKCFG_Msk                          /*!<Wrong Clock Configuration                      */
11485 #define SAI_xSR_FREQ_Pos           (3U)
11486 #define SAI_xSR_FREQ_Msk           (0x1UL << SAI_xSR_FREQ_Pos)                  /*!< 0x00000008 */
11487 #define SAI_xSR_FREQ               SAI_xSR_FREQ_Msk                            /*!<FIFO request                                   */
11488 #define SAI_xSR_CNRDY_Pos          (4U)
11489 #define SAI_xSR_CNRDY_Msk          (0x1UL << SAI_xSR_CNRDY_Pos)                 /*!< 0x00000010 */
11490 #define SAI_xSR_CNRDY              SAI_xSR_CNRDY_Msk                           /*!<Codec not ready                                */
11491 #define SAI_xSR_AFSDET_Pos         (5U)
11492 #define SAI_xSR_AFSDET_Msk         (0x1UL << SAI_xSR_AFSDET_Pos)                /*!< 0x00000020 */
11493 #define SAI_xSR_AFSDET             SAI_xSR_AFSDET_Msk                          /*!<Anticipated frame synchronization detection    */
11494 #define SAI_xSR_LFSDET_Pos         (6U)
11495 #define SAI_xSR_LFSDET_Msk         (0x1UL << SAI_xSR_LFSDET_Pos)                /*!< 0x00000040 */
11496 #define SAI_xSR_LFSDET             SAI_xSR_LFSDET_Msk                          /*!<Late frame synchronization detection           */
11497 
11498 #define SAI_xSR_FLVL_Pos           (16U)
11499 #define SAI_xSR_FLVL_Msk           (0x7UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00070000 */
11500 #define SAI_xSR_FLVL               SAI_xSR_FLVL_Msk                            /*!<FLVL[2:0] (FIFO Level Threshold)               */
11501 #define SAI_xSR_FLVL_0             (0x1UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00010000 */
11502 #define SAI_xSR_FLVL_1             (0x2UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00020000 */
11503 #define SAI_xSR_FLVL_2             (0x4UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00040000 */
11504 
11505 /******************  Bit definition for SAI_xCLRFR register  ******************/
11506 #define SAI_xCLRFR_COVRUDR_Pos     (0U)
11507 #define SAI_xCLRFR_COVRUDR_Msk     (0x1UL << SAI_xCLRFR_COVRUDR_Pos)            /*!< 0x00000001 */
11508 #define SAI_xCLRFR_COVRUDR         SAI_xCLRFR_COVRUDR_Msk                      /*!<Clear Overrun underrun                               */
11509 #define SAI_xCLRFR_CMUTEDET_Pos    (1U)
11510 #define SAI_xCLRFR_CMUTEDET_Msk    (0x1UL << SAI_xCLRFR_CMUTEDET_Pos)           /*!< 0x00000002 */
11511 #define SAI_xCLRFR_CMUTEDET        SAI_xCLRFR_CMUTEDET_Msk                     /*!<Clear Mute detection                                 */
11512 #define SAI_xCLRFR_CWCKCFG_Pos     (2U)
11513 #define SAI_xCLRFR_CWCKCFG_Msk     (0x1UL << SAI_xCLRFR_CWCKCFG_Pos)            /*!< 0x00000004 */
11514 #define SAI_xCLRFR_CWCKCFG         SAI_xCLRFR_CWCKCFG_Msk                      /*!<Clear Wrong Clock Configuration                      */
11515 #define SAI_xCLRFR_CFREQ_Pos       (3U)
11516 #define SAI_xCLRFR_CFREQ_Msk       (0x1UL << SAI_xCLRFR_CFREQ_Pos)              /*!< 0x00000008 */
11517 #define SAI_xCLRFR_CFREQ           SAI_xCLRFR_CFREQ_Msk                        /*!<Clear FIFO request                                   */
11518 #define SAI_xCLRFR_CCNRDY_Pos      (4U)
11519 #define SAI_xCLRFR_CCNRDY_Msk      (0x1UL << SAI_xCLRFR_CCNRDY_Pos)             /*!< 0x00000010 */
11520 #define SAI_xCLRFR_CCNRDY          SAI_xCLRFR_CCNRDY_Msk                       /*!<Clear Codec not ready                                */
11521 #define SAI_xCLRFR_CAFSDET_Pos     (5U)
11522 #define SAI_xCLRFR_CAFSDET_Msk     (0x1UL << SAI_xCLRFR_CAFSDET_Pos)            /*!< 0x00000020 */
11523 #define SAI_xCLRFR_CAFSDET         SAI_xCLRFR_CAFSDET_Msk                      /*!<Clear Anticipated frame synchronization detection    */
11524 #define SAI_xCLRFR_CLFSDET_Pos     (6U)
11525 #define SAI_xCLRFR_CLFSDET_Msk     (0x1UL << SAI_xCLRFR_CLFSDET_Pos)            /*!< 0x00000040 */
11526 #define SAI_xCLRFR_CLFSDET         SAI_xCLRFR_CLFSDET_Msk                      /*!<Clear Late frame synchronization detection           */
11527 
11528 /******************  Bit definition for SAI_xDR register  ******************/
11529 #define SAI_xDR_DATA_Pos           (0U)
11530 #define SAI_xDR_DATA_Msk           (0xFFFFFFFFUL << SAI_xDR_DATA_Pos)           /*!< 0xFFFFFFFF */
11531 #define SAI_xDR_DATA               SAI_xDR_DATA_Msk
11532 
11533 
11534 /******************************************************************************/
11535 /*                                                                            */
11536 /*                          SD host Interface                                 */
11537 /*                                                                            */
11538 /******************************************************************************/
11539 /******************  Bit definition for SDIO_POWER register  ******************/
11540 #define SDIO_POWER_PWRCTRL_Pos         (0U)
11541 #define SDIO_POWER_PWRCTRL_Msk         (0x3UL << SDIO_POWER_PWRCTRL_Pos)        /*!< 0x00000003 */
11542 #define SDIO_POWER_PWRCTRL             SDIO_POWER_PWRCTRL_Msk                  /*!<PWRCTRL[1:0] bits (Power supply control bits) */
11543 #define SDIO_POWER_PWRCTRL_0           (0x1UL << SDIO_POWER_PWRCTRL_Pos)        /*!< 0x01 */
11544 #define SDIO_POWER_PWRCTRL_1           (0x2UL << SDIO_POWER_PWRCTRL_Pos)        /*!< 0x02 */
11545 
11546 /******************  Bit definition for SDIO_CLKCR register  ******************/
11547 #define SDIO_CLKCR_CLKDIV_Pos          (0U)
11548 #define SDIO_CLKCR_CLKDIV_Msk          (0xFFUL << SDIO_CLKCR_CLKDIV_Pos)        /*!< 0x000000FF */
11549 #define SDIO_CLKCR_CLKDIV              SDIO_CLKCR_CLKDIV_Msk                   /*!<Clock divide factor             */
11550 #define SDIO_CLKCR_CLKEN_Pos           (8U)
11551 #define SDIO_CLKCR_CLKEN_Msk           (0x1UL << SDIO_CLKCR_CLKEN_Pos)          /*!< 0x00000100 */
11552 #define SDIO_CLKCR_CLKEN               SDIO_CLKCR_CLKEN_Msk                    /*!<Clock enable bit                */
11553 #define SDIO_CLKCR_PWRSAV_Pos          (9U)
11554 #define SDIO_CLKCR_PWRSAV_Msk          (0x1UL << SDIO_CLKCR_PWRSAV_Pos)         /*!< 0x00000200 */
11555 #define SDIO_CLKCR_PWRSAV              SDIO_CLKCR_PWRSAV_Msk                   /*!<Power saving configuration bit  */
11556 #define SDIO_CLKCR_BYPASS_Pos          (10U)
11557 #define SDIO_CLKCR_BYPASS_Msk          (0x1UL << SDIO_CLKCR_BYPASS_Pos)         /*!< 0x00000400 */
11558 #define SDIO_CLKCR_BYPASS              SDIO_CLKCR_BYPASS_Msk                   /*!<Clock divider bypass enable bit */
11559 
11560 #define SDIO_CLKCR_WIDBUS_Pos          (11U)
11561 #define SDIO_CLKCR_WIDBUS_Msk          (0x3UL << SDIO_CLKCR_WIDBUS_Pos)         /*!< 0x00001800 */
11562 #define SDIO_CLKCR_WIDBUS              SDIO_CLKCR_WIDBUS_Msk                   /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
11563 #define SDIO_CLKCR_WIDBUS_0            (0x1UL << SDIO_CLKCR_WIDBUS_Pos)         /*!< 0x0800 */
11564 #define SDIO_CLKCR_WIDBUS_1            (0x2UL << SDIO_CLKCR_WIDBUS_Pos)         /*!< 0x1000 */
11565 
11566 #define SDIO_CLKCR_NEGEDGE_Pos         (13U)
11567 #define SDIO_CLKCR_NEGEDGE_Msk         (0x1UL << SDIO_CLKCR_NEGEDGE_Pos)        /*!< 0x00002000 */
11568 #define SDIO_CLKCR_NEGEDGE             SDIO_CLKCR_NEGEDGE_Msk                  /*!<SDIO_CK dephasing selection bit */
11569 #define SDIO_CLKCR_HWFC_EN_Pos         (14U)
11570 #define SDIO_CLKCR_HWFC_EN_Msk         (0x1UL << SDIO_CLKCR_HWFC_EN_Pos)        /*!< 0x00004000 */
11571 #define SDIO_CLKCR_HWFC_EN             SDIO_CLKCR_HWFC_EN_Msk                  /*!<HW Flow Control enable          */
11572 
11573 /*******************  Bit definition for SDIO_ARG register  *******************/
11574 #define SDIO_ARG_CMDARG_Pos            (0U)
11575 #define SDIO_ARG_CMDARG_Msk            (0xFFFFFFFFUL << SDIO_ARG_CMDARG_Pos)    /*!< 0xFFFFFFFF */
11576 #define SDIO_ARG_CMDARG                SDIO_ARG_CMDARG_Msk                     /*!<Command argument */
11577 
11578 /*******************  Bit definition for SDIO_CMD register  *******************/
11579 #define SDIO_CMD_CMDINDEX_Pos          (0U)
11580 #define SDIO_CMD_CMDINDEX_Msk          (0x3FUL << SDIO_CMD_CMDINDEX_Pos)        /*!< 0x0000003F */
11581 #define SDIO_CMD_CMDINDEX              SDIO_CMD_CMDINDEX_Msk                   /*!<Command Index                               */
11582 
11583 #define SDIO_CMD_WAITRESP_Pos          (6U)
11584 #define SDIO_CMD_WAITRESP_Msk          (0x3UL << SDIO_CMD_WAITRESP_Pos)         /*!< 0x000000C0 */
11585 #define SDIO_CMD_WAITRESP              SDIO_CMD_WAITRESP_Msk                   /*!<WAITRESP[1:0] bits (Wait for response bits) */
11586 #define SDIO_CMD_WAITRESP_0            (0x1UL << SDIO_CMD_WAITRESP_Pos)         /*!< 0x0040 */
11587 #define SDIO_CMD_WAITRESP_1            (0x2UL << SDIO_CMD_WAITRESP_Pos)         /*!< 0x0080 */
11588 
11589 #define SDIO_CMD_WAITINT_Pos           (8U)
11590 #define SDIO_CMD_WAITINT_Msk           (0x1UL << SDIO_CMD_WAITINT_Pos)          /*!< 0x00000100 */
11591 #define SDIO_CMD_WAITINT               SDIO_CMD_WAITINT_Msk                    /*!<CPSM Waits for Interrupt Request                               */
11592 #define SDIO_CMD_WAITPEND_Pos          (9U)
11593 #define SDIO_CMD_WAITPEND_Msk          (0x1UL << SDIO_CMD_WAITPEND_Pos)         /*!< 0x00000200 */
11594 #define SDIO_CMD_WAITPEND              SDIO_CMD_WAITPEND_Msk                   /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
11595 #define SDIO_CMD_CPSMEN_Pos            (10U)
11596 #define SDIO_CMD_CPSMEN_Msk            (0x1UL << SDIO_CMD_CPSMEN_Pos)           /*!< 0x00000400 */
11597 #define SDIO_CMD_CPSMEN                SDIO_CMD_CPSMEN_Msk                     /*!<Command path state machine (CPSM) Enable bit                   */
11598 #define SDIO_CMD_SDIOSUSPEND_Pos       (11U)
11599 #define SDIO_CMD_SDIOSUSPEND_Msk       (0x1UL << SDIO_CMD_SDIOSUSPEND_Pos)      /*!< 0x00000800 */
11600 #define SDIO_CMD_SDIOSUSPEND           SDIO_CMD_SDIOSUSPEND_Msk                /*!<SD I/O suspend command                                         */
11601 
11602 /*****************  Bit definition for SDIO_RESPCMD register  *****************/
11603 #define SDIO_RESPCMD_RESPCMD_Pos       (0U)
11604 #define SDIO_RESPCMD_RESPCMD_Msk       (0x3FUL << SDIO_RESPCMD_RESPCMD_Pos)     /*!< 0x0000003F */
11605 #define SDIO_RESPCMD_RESPCMD           SDIO_RESPCMD_RESPCMD_Msk                /*!<Response command index */
11606 
11607 /******************  Bit definition for SDIO_RESP0 register  ******************/
11608 #define SDIO_RESP0_CARDSTATUS0_Pos     (0U)
11609 #define SDIO_RESP0_CARDSTATUS0_Msk     (0xFFFFFFFFUL << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
11610 #define SDIO_RESP0_CARDSTATUS0         SDIO_RESP0_CARDSTATUS0_Msk              /*!<Card Status */
11611 
11612 /******************  Bit definition for SDIO_RESP1 register  ******************/
11613 #define SDIO_RESP1_CARDSTATUS1_Pos     (0U)
11614 #define SDIO_RESP1_CARDSTATUS1_Msk     (0xFFFFFFFFUL << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
11615 #define SDIO_RESP1_CARDSTATUS1         SDIO_RESP1_CARDSTATUS1_Msk              /*!<Card Status */
11616 
11617 /******************  Bit definition for SDIO_RESP2 register  ******************/
11618 #define SDIO_RESP2_CARDSTATUS2_Pos     (0U)
11619 #define SDIO_RESP2_CARDSTATUS2_Msk     (0xFFFFFFFFUL << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
11620 #define SDIO_RESP2_CARDSTATUS2         SDIO_RESP2_CARDSTATUS2_Msk              /*!<Card Status */
11621 
11622 /******************  Bit definition for SDIO_RESP3 register  ******************/
11623 #define SDIO_RESP3_CARDSTATUS3_Pos     (0U)
11624 #define SDIO_RESP3_CARDSTATUS3_Msk     (0xFFFFFFFFUL << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
11625 #define SDIO_RESP3_CARDSTATUS3         SDIO_RESP3_CARDSTATUS3_Msk              /*!<Card Status */
11626 
11627 /******************  Bit definition for SDIO_RESP4 register  ******************/
11628 #define SDIO_RESP4_CARDSTATUS4_Pos     (0U)
11629 #define SDIO_RESP4_CARDSTATUS4_Msk     (0xFFFFFFFFUL << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
11630 #define SDIO_RESP4_CARDSTATUS4         SDIO_RESP4_CARDSTATUS4_Msk              /*!<Card Status */
11631 
11632 /******************  Bit definition for SDIO_DTIMER register  *****************/
11633 #define SDIO_DTIMER_DATATIME_Pos       (0U)
11634 #define SDIO_DTIMER_DATATIME_Msk       (0xFFFFFFFFUL << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
11635 #define SDIO_DTIMER_DATATIME           SDIO_DTIMER_DATATIME_Msk                /*!<Data timeout period. */
11636 
11637 /******************  Bit definition for SDIO_DLEN register  *******************/
11638 #define SDIO_DLEN_DATALENGTH_Pos       (0U)
11639 #define SDIO_DLEN_DATALENGTH_Msk       (0x1FFFFFFUL << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
11640 #define SDIO_DLEN_DATALENGTH           SDIO_DLEN_DATALENGTH_Msk                /*!<Data length value    */
11641 
11642 /******************  Bit definition for SDIO_DCTRL register  ******************/
11643 #define SDIO_DCTRL_DTEN_Pos            (0U)
11644 #define SDIO_DCTRL_DTEN_Msk            (0x1UL << SDIO_DCTRL_DTEN_Pos)           /*!< 0x00000001 */
11645 #define SDIO_DCTRL_DTEN                SDIO_DCTRL_DTEN_Msk                     /*!<Data transfer enabled bit         */
11646 #define SDIO_DCTRL_DTDIR_Pos           (1U)
11647 #define SDIO_DCTRL_DTDIR_Msk           (0x1UL << SDIO_DCTRL_DTDIR_Pos)          /*!< 0x00000002 */
11648 #define SDIO_DCTRL_DTDIR               SDIO_DCTRL_DTDIR_Msk                    /*!<Data transfer direction selection */
11649 #define SDIO_DCTRL_DTMODE_Pos          (2U)
11650 #define SDIO_DCTRL_DTMODE_Msk          (0x1UL << SDIO_DCTRL_DTMODE_Pos)         /*!< 0x00000004 */
11651 #define SDIO_DCTRL_DTMODE              SDIO_DCTRL_DTMODE_Msk                   /*!<Data transfer mode selection      */
11652 #define SDIO_DCTRL_DMAEN_Pos           (3U)
11653 #define SDIO_DCTRL_DMAEN_Msk           (0x1UL << SDIO_DCTRL_DMAEN_Pos)          /*!< 0x00000008 */
11654 #define SDIO_DCTRL_DMAEN               SDIO_DCTRL_DMAEN_Msk                    /*!<DMA enabled bit                   */
11655 
11656 #define SDIO_DCTRL_DBLOCKSIZE_Pos      (4U)
11657 #define SDIO_DCTRL_DBLOCKSIZE_Msk      (0xFUL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x000000F0 */
11658 #define SDIO_DCTRL_DBLOCKSIZE          SDIO_DCTRL_DBLOCKSIZE_Msk               /*!<DBLOCKSIZE[3:0] bits (Data block size) */
11659 #define SDIO_DCTRL_DBLOCKSIZE_0        (0x1UL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0010 */
11660 #define SDIO_DCTRL_DBLOCKSIZE_1        (0x2UL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0020 */
11661 #define SDIO_DCTRL_DBLOCKSIZE_2        (0x4UL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0040 */
11662 #define SDIO_DCTRL_DBLOCKSIZE_3        (0x8UL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0080 */
11663 
11664 #define SDIO_DCTRL_RWSTART_Pos         (8U)
11665 #define SDIO_DCTRL_RWSTART_Msk         (0x1UL << SDIO_DCTRL_RWSTART_Pos)        /*!< 0x00000100 */
11666 #define SDIO_DCTRL_RWSTART             SDIO_DCTRL_RWSTART_Msk                  /*!<Read wait start         */
11667 #define SDIO_DCTRL_RWSTOP_Pos          (9U)
11668 #define SDIO_DCTRL_RWSTOP_Msk          (0x1UL << SDIO_DCTRL_RWSTOP_Pos)         /*!< 0x00000200 */
11669 #define SDIO_DCTRL_RWSTOP              SDIO_DCTRL_RWSTOP_Msk                   /*!<Read wait stop          */
11670 #define SDIO_DCTRL_RWMOD_Pos           (10U)
11671 #define SDIO_DCTRL_RWMOD_Msk           (0x1UL << SDIO_DCTRL_RWMOD_Pos)          /*!< 0x00000400 */
11672 #define SDIO_DCTRL_RWMOD               SDIO_DCTRL_RWMOD_Msk                    /*!<Read wait mode          */
11673 #define SDIO_DCTRL_SDIOEN_Pos          (11U)
11674 #define SDIO_DCTRL_SDIOEN_Msk          (0x1UL << SDIO_DCTRL_SDIOEN_Pos)         /*!< 0x00000800 */
11675 #define SDIO_DCTRL_SDIOEN              SDIO_DCTRL_SDIOEN_Msk                   /*!<SD I/O enable functions */
11676 
11677 /******************  Bit definition for SDIO_DCOUNT register  *****************/
11678 #define SDIO_DCOUNT_DATACOUNT_Pos      (0U)
11679 #define SDIO_DCOUNT_DATACOUNT_Msk      (0x1FFFFFFUL << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
11680 #define SDIO_DCOUNT_DATACOUNT          SDIO_DCOUNT_DATACOUNT_Msk               /*!<Data count value */
11681 
11682 /******************  Bit definition for SDIO_STA register  ********************/
11683 #define SDIO_STA_CCRCFAIL_Pos          (0U)
11684 #define SDIO_STA_CCRCFAIL_Msk          (0x1UL << SDIO_STA_CCRCFAIL_Pos)         /*!< 0x00000001 */
11685 #define SDIO_STA_CCRCFAIL              SDIO_STA_CCRCFAIL_Msk                   /*!<Command response received (CRC check failed)  */
11686 #define SDIO_STA_DCRCFAIL_Pos          (1U)
11687 #define SDIO_STA_DCRCFAIL_Msk          (0x1UL << SDIO_STA_DCRCFAIL_Pos)         /*!< 0x00000002 */
11688 #define SDIO_STA_DCRCFAIL              SDIO_STA_DCRCFAIL_Msk                   /*!<Data block sent/received (CRC check failed)   */
11689 #define SDIO_STA_CTIMEOUT_Pos          (2U)
11690 #define SDIO_STA_CTIMEOUT_Msk          (0x1UL << SDIO_STA_CTIMEOUT_Pos)         /*!< 0x00000004 */
11691 #define SDIO_STA_CTIMEOUT              SDIO_STA_CTIMEOUT_Msk                   /*!<Command response timeout                      */
11692 #define SDIO_STA_DTIMEOUT_Pos          (3U)
11693 #define SDIO_STA_DTIMEOUT_Msk          (0x1UL << SDIO_STA_DTIMEOUT_Pos)         /*!< 0x00000008 */
11694 #define SDIO_STA_DTIMEOUT              SDIO_STA_DTIMEOUT_Msk                   /*!<Data timeout                                  */
11695 #define SDIO_STA_TXUNDERR_Pos          (4U)
11696 #define SDIO_STA_TXUNDERR_Msk          (0x1UL << SDIO_STA_TXUNDERR_Pos)         /*!< 0x00000010 */
11697 #define SDIO_STA_TXUNDERR              SDIO_STA_TXUNDERR_Msk                   /*!<Transmit FIFO underrun error                  */
11698 #define SDIO_STA_RXOVERR_Pos           (5U)
11699 #define SDIO_STA_RXOVERR_Msk           (0x1UL << SDIO_STA_RXOVERR_Pos)          /*!< 0x00000020 */
11700 #define SDIO_STA_RXOVERR               SDIO_STA_RXOVERR_Msk                    /*!<Received FIFO overrun error                   */
11701 #define SDIO_STA_CMDREND_Pos           (6U)
11702 #define SDIO_STA_CMDREND_Msk           (0x1UL << SDIO_STA_CMDREND_Pos)          /*!< 0x00000040 */
11703 #define SDIO_STA_CMDREND               SDIO_STA_CMDREND_Msk                    /*!<Command response received (CRC check passed)  */
11704 #define SDIO_STA_CMDSENT_Pos           (7U)
11705 #define SDIO_STA_CMDSENT_Msk           (0x1UL << SDIO_STA_CMDSENT_Pos)          /*!< 0x00000080 */
11706 #define SDIO_STA_CMDSENT               SDIO_STA_CMDSENT_Msk                    /*!<Command sent (no response required)           */
11707 #define SDIO_STA_DATAEND_Pos           (8U)
11708 #define SDIO_STA_DATAEND_Msk           (0x1UL << SDIO_STA_DATAEND_Pos)          /*!< 0x00000100 */
11709 #define SDIO_STA_DATAEND               SDIO_STA_DATAEND_Msk                    /*!<Data end (data counter, SDIDCOUNT, is zero)   */
11710 #define SDIO_STA_DBCKEND_Pos           (10U)
11711 #define SDIO_STA_DBCKEND_Msk           (0x1UL << SDIO_STA_DBCKEND_Pos)          /*!< 0x00000400 */
11712 #define SDIO_STA_DBCKEND               SDIO_STA_DBCKEND_Msk                    /*!<Data block sent/received (CRC check passed)   */
11713 #define SDIO_STA_CMDACT_Pos            (11U)
11714 #define SDIO_STA_CMDACT_Msk            (0x1UL << SDIO_STA_CMDACT_Pos)           /*!< 0x00000800 */
11715 #define SDIO_STA_CMDACT                SDIO_STA_CMDACT_Msk                     /*!<Command transfer in progress                  */
11716 #define SDIO_STA_TXACT_Pos             (12U)
11717 #define SDIO_STA_TXACT_Msk             (0x1UL << SDIO_STA_TXACT_Pos)            /*!< 0x00001000 */
11718 #define SDIO_STA_TXACT                 SDIO_STA_TXACT_Msk                      /*!<Data transmit in progress                     */
11719 #define SDIO_STA_RXACT_Pos             (13U)
11720 #define SDIO_STA_RXACT_Msk             (0x1UL << SDIO_STA_RXACT_Pos)            /*!< 0x00002000 */
11721 #define SDIO_STA_RXACT                 SDIO_STA_RXACT_Msk                      /*!<Data receive in progress                      */
11722 #define SDIO_STA_TXFIFOHE_Pos          (14U)
11723 #define SDIO_STA_TXFIFOHE_Msk          (0x1UL << SDIO_STA_TXFIFOHE_Pos)         /*!< 0x00004000 */
11724 #define SDIO_STA_TXFIFOHE              SDIO_STA_TXFIFOHE_Msk                   /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
11725 #define SDIO_STA_RXFIFOHF_Pos          (15U)
11726 #define SDIO_STA_RXFIFOHF_Msk          (0x1UL << SDIO_STA_RXFIFOHF_Pos)         /*!< 0x00008000 */
11727 #define SDIO_STA_RXFIFOHF              SDIO_STA_RXFIFOHF_Msk                   /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
11728 #define SDIO_STA_TXFIFOF_Pos           (16U)
11729 #define SDIO_STA_TXFIFOF_Msk           (0x1UL << SDIO_STA_TXFIFOF_Pos)          /*!< 0x00010000 */
11730 #define SDIO_STA_TXFIFOF               SDIO_STA_TXFIFOF_Msk                    /*!<Transmit FIFO full                            */
11731 #define SDIO_STA_RXFIFOF_Pos           (17U)
11732 #define SDIO_STA_RXFIFOF_Msk           (0x1UL << SDIO_STA_RXFIFOF_Pos)          /*!< 0x00020000 */
11733 #define SDIO_STA_RXFIFOF               SDIO_STA_RXFIFOF_Msk                    /*!<Receive FIFO full                             */
11734 #define SDIO_STA_TXFIFOE_Pos           (18U)
11735 #define SDIO_STA_TXFIFOE_Msk           (0x1UL << SDIO_STA_TXFIFOE_Pos)          /*!< 0x00040000 */
11736 #define SDIO_STA_TXFIFOE               SDIO_STA_TXFIFOE_Msk                    /*!<Transmit FIFO empty                           */
11737 #define SDIO_STA_RXFIFOE_Pos           (19U)
11738 #define SDIO_STA_RXFIFOE_Msk           (0x1UL << SDIO_STA_RXFIFOE_Pos)          /*!< 0x00080000 */
11739 #define SDIO_STA_RXFIFOE               SDIO_STA_RXFIFOE_Msk                    /*!<Receive FIFO empty                            */
11740 #define SDIO_STA_TXDAVL_Pos            (20U)
11741 #define SDIO_STA_TXDAVL_Msk            (0x1UL << SDIO_STA_TXDAVL_Pos)           /*!< 0x00100000 */
11742 #define SDIO_STA_TXDAVL                SDIO_STA_TXDAVL_Msk                     /*!<Data available in transmit FIFO               */
11743 #define SDIO_STA_RXDAVL_Pos            (21U)
11744 #define SDIO_STA_RXDAVL_Msk            (0x1UL << SDIO_STA_RXDAVL_Pos)           /*!< 0x00200000 */
11745 #define SDIO_STA_RXDAVL                SDIO_STA_RXDAVL_Msk                     /*!<Data available in receive FIFO                */
11746 #define SDIO_STA_SDIOIT_Pos            (22U)
11747 #define SDIO_STA_SDIOIT_Msk            (0x1UL << SDIO_STA_SDIOIT_Pos)           /*!< 0x00400000 */
11748 #define SDIO_STA_SDIOIT                SDIO_STA_SDIOIT_Msk                     /*!<SDIO interrupt received                       */
11749 
11750 /*******************  Bit definition for SDIO_ICR register  *******************/
11751 #define SDIO_ICR_CCRCFAILC_Pos         (0U)
11752 #define SDIO_ICR_CCRCFAILC_Msk         (0x1UL << SDIO_ICR_CCRCFAILC_Pos)        /*!< 0x00000001 */
11753 #define SDIO_ICR_CCRCFAILC             SDIO_ICR_CCRCFAILC_Msk                  /*!<CCRCFAIL flag clear bit */
11754 #define SDIO_ICR_DCRCFAILC_Pos         (1U)
11755 #define SDIO_ICR_DCRCFAILC_Msk         (0x1UL << SDIO_ICR_DCRCFAILC_Pos)        /*!< 0x00000002 */
11756 #define SDIO_ICR_DCRCFAILC             SDIO_ICR_DCRCFAILC_Msk                  /*!<DCRCFAIL flag clear bit */
11757 #define SDIO_ICR_CTIMEOUTC_Pos         (2U)
11758 #define SDIO_ICR_CTIMEOUTC_Msk         (0x1UL << SDIO_ICR_CTIMEOUTC_Pos)        /*!< 0x00000004 */
11759 #define SDIO_ICR_CTIMEOUTC             SDIO_ICR_CTIMEOUTC_Msk                  /*!<CTIMEOUT flag clear bit */
11760 #define SDIO_ICR_DTIMEOUTC_Pos         (3U)
11761 #define SDIO_ICR_DTIMEOUTC_Msk         (0x1UL << SDIO_ICR_DTIMEOUTC_Pos)        /*!< 0x00000008 */
11762 #define SDIO_ICR_DTIMEOUTC             SDIO_ICR_DTIMEOUTC_Msk                  /*!<DTIMEOUT flag clear bit */
11763 #define SDIO_ICR_TXUNDERRC_Pos         (4U)
11764 #define SDIO_ICR_TXUNDERRC_Msk         (0x1UL << SDIO_ICR_TXUNDERRC_Pos)        /*!< 0x00000010 */
11765 #define SDIO_ICR_TXUNDERRC             SDIO_ICR_TXUNDERRC_Msk                  /*!<TXUNDERR flag clear bit */
11766 #define SDIO_ICR_RXOVERRC_Pos          (5U)
11767 #define SDIO_ICR_RXOVERRC_Msk          (0x1UL << SDIO_ICR_RXOVERRC_Pos)         /*!< 0x00000020 */
11768 #define SDIO_ICR_RXOVERRC              SDIO_ICR_RXOVERRC_Msk                   /*!<RXOVERR flag clear bit  */
11769 #define SDIO_ICR_CMDRENDC_Pos          (6U)
11770 #define SDIO_ICR_CMDRENDC_Msk          (0x1UL << SDIO_ICR_CMDRENDC_Pos)         /*!< 0x00000040 */
11771 #define SDIO_ICR_CMDRENDC              SDIO_ICR_CMDRENDC_Msk                   /*!<CMDREND flag clear bit  */
11772 #define SDIO_ICR_CMDSENTC_Pos          (7U)
11773 #define SDIO_ICR_CMDSENTC_Msk          (0x1UL << SDIO_ICR_CMDSENTC_Pos)         /*!< 0x00000080 */
11774 #define SDIO_ICR_CMDSENTC              SDIO_ICR_CMDSENTC_Msk                   /*!<CMDSENT flag clear bit  */
11775 #define SDIO_ICR_DATAENDC_Pos          (8U)
11776 #define SDIO_ICR_DATAENDC_Msk          (0x1UL << SDIO_ICR_DATAENDC_Pos)         /*!< 0x00000100 */
11777 #define SDIO_ICR_DATAENDC              SDIO_ICR_DATAENDC_Msk                   /*!<DATAEND flag clear bit  */
11778 #define SDIO_ICR_DBCKENDC_Pos          (10U)
11779 #define SDIO_ICR_DBCKENDC_Msk          (0x1UL << SDIO_ICR_DBCKENDC_Pos)         /*!< 0x00000400 */
11780 #define SDIO_ICR_DBCKENDC              SDIO_ICR_DBCKENDC_Msk                   /*!<DBCKEND flag clear bit  */
11781 #define SDIO_ICR_SDIOITC_Pos           (22U)
11782 #define SDIO_ICR_SDIOITC_Msk           (0x1UL << SDIO_ICR_SDIOITC_Pos)          /*!< 0x00400000 */
11783 #define SDIO_ICR_SDIOITC               SDIO_ICR_SDIOITC_Msk                    /*!<SDIOIT flag clear bit   */
11784 
11785 /******************  Bit definition for SDIO_MASK register  *******************/
11786 #define SDIO_MASK_CCRCFAILIE_Pos       (0U)
11787 #define SDIO_MASK_CCRCFAILIE_Msk       (0x1UL << SDIO_MASK_CCRCFAILIE_Pos)      /*!< 0x00000001 */
11788 #define SDIO_MASK_CCRCFAILIE           SDIO_MASK_CCRCFAILIE_Msk                /*!<Command CRC Fail Interrupt Enable          */
11789 #define SDIO_MASK_DCRCFAILIE_Pos       (1U)
11790 #define SDIO_MASK_DCRCFAILIE_Msk       (0x1UL << SDIO_MASK_DCRCFAILIE_Pos)      /*!< 0x00000002 */
11791 #define SDIO_MASK_DCRCFAILIE           SDIO_MASK_DCRCFAILIE_Msk                /*!<Data CRC Fail Interrupt Enable             */
11792 #define SDIO_MASK_CTIMEOUTIE_Pos       (2U)
11793 #define SDIO_MASK_CTIMEOUTIE_Msk       (0x1UL << SDIO_MASK_CTIMEOUTIE_Pos)      /*!< 0x00000004 */
11794 #define SDIO_MASK_CTIMEOUTIE           SDIO_MASK_CTIMEOUTIE_Msk                /*!<Command TimeOut Interrupt Enable           */
11795 #define SDIO_MASK_DTIMEOUTIE_Pos       (3U)
11796 #define SDIO_MASK_DTIMEOUTIE_Msk       (0x1UL << SDIO_MASK_DTIMEOUTIE_Pos)      /*!< 0x00000008 */
11797 #define SDIO_MASK_DTIMEOUTIE           SDIO_MASK_DTIMEOUTIE_Msk                /*!<Data TimeOut Interrupt Enable              */
11798 #define SDIO_MASK_TXUNDERRIE_Pos       (4U)
11799 #define SDIO_MASK_TXUNDERRIE_Msk       (0x1UL << SDIO_MASK_TXUNDERRIE_Pos)      /*!< 0x00000010 */
11800 #define SDIO_MASK_TXUNDERRIE           SDIO_MASK_TXUNDERRIE_Msk                /*!<Tx FIFO UnderRun Error Interrupt Enable    */
11801 #define SDIO_MASK_RXOVERRIE_Pos        (5U)
11802 #define SDIO_MASK_RXOVERRIE_Msk        (0x1UL << SDIO_MASK_RXOVERRIE_Pos)       /*!< 0x00000020 */
11803 #define SDIO_MASK_RXOVERRIE            SDIO_MASK_RXOVERRIE_Msk                 /*!<Rx FIFO OverRun Error Interrupt Enable     */
11804 #define SDIO_MASK_CMDRENDIE_Pos        (6U)
11805 #define SDIO_MASK_CMDRENDIE_Msk        (0x1UL << SDIO_MASK_CMDRENDIE_Pos)       /*!< 0x00000040 */
11806 #define SDIO_MASK_CMDRENDIE            SDIO_MASK_CMDRENDIE_Msk                 /*!<Command Response Received Interrupt Enable */
11807 #define SDIO_MASK_CMDSENTIE_Pos        (7U)
11808 #define SDIO_MASK_CMDSENTIE_Msk        (0x1UL << SDIO_MASK_CMDSENTIE_Pos)       /*!< 0x00000080 */
11809 #define SDIO_MASK_CMDSENTIE            SDIO_MASK_CMDSENTIE_Msk                 /*!<Command Sent Interrupt Enable              */
11810 #define SDIO_MASK_DATAENDIE_Pos        (8U)
11811 #define SDIO_MASK_DATAENDIE_Msk        (0x1UL << SDIO_MASK_DATAENDIE_Pos)       /*!< 0x00000100 */
11812 #define SDIO_MASK_DATAENDIE            SDIO_MASK_DATAENDIE_Msk                 /*!<Data End Interrupt Enable                  */
11813 #define SDIO_MASK_DBCKENDIE_Pos        (10U)
11814 #define SDIO_MASK_DBCKENDIE_Msk        (0x1UL << SDIO_MASK_DBCKENDIE_Pos)       /*!< 0x00000400 */
11815 #define SDIO_MASK_DBCKENDIE            SDIO_MASK_DBCKENDIE_Msk                 /*!<Data Block End Interrupt Enable            */
11816 #define SDIO_MASK_CMDACTIE_Pos         (11U)
11817 #define SDIO_MASK_CMDACTIE_Msk         (0x1UL << SDIO_MASK_CMDACTIE_Pos)        /*!< 0x00000800 */
11818 #define SDIO_MASK_CMDACTIE             SDIO_MASK_CMDACTIE_Msk                  /*!<CCommand Acting Interrupt Enable           */
11819 #define SDIO_MASK_TXACTIE_Pos          (12U)
11820 #define SDIO_MASK_TXACTIE_Msk          (0x1UL << SDIO_MASK_TXACTIE_Pos)         /*!< 0x00001000 */
11821 #define SDIO_MASK_TXACTIE              SDIO_MASK_TXACTIE_Msk                   /*!<Data Transmit Acting Interrupt Enable      */
11822 #define SDIO_MASK_RXACTIE_Pos          (13U)
11823 #define SDIO_MASK_RXACTIE_Msk          (0x1UL << SDIO_MASK_RXACTIE_Pos)         /*!< 0x00002000 */
11824 #define SDIO_MASK_RXACTIE              SDIO_MASK_RXACTIE_Msk                   /*!<Data receive acting interrupt enabled      */
11825 #define SDIO_MASK_TXFIFOHEIE_Pos       (14U)
11826 #define SDIO_MASK_TXFIFOHEIE_Msk       (0x1UL << SDIO_MASK_TXFIFOHEIE_Pos)      /*!< 0x00004000 */
11827 #define SDIO_MASK_TXFIFOHEIE           SDIO_MASK_TXFIFOHEIE_Msk                /*!<Tx FIFO Half Empty interrupt Enable        */
11828 #define SDIO_MASK_RXFIFOHFIE_Pos       (15U)
11829 #define SDIO_MASK_RXFIFOHFIE_Msk       (0x1UL << SDIO_MASK_RXFIFOHFIE_Pos)      /*!< 0x00008000 */
11830 #define SDIO_MASK_RXFIFOHFIE           SDIO_MASK_RXFIFOHFIE_Msk                /*!<Rx FIFO Half Full interrupt Enable         */
11831 #define SDIO_MASK_TXFIFOFIE_Pos        (16U)
11832 #define SDIO_MASK_TXFIFOFIE_Msk        (0x1UL << SDIO_MASK_TXFIFOFIE_Pos)       /*!< 0x00010000 */
11833 #define SDIO_MASK_TXFIFOFIE            SDIO_MASK_TXFIFOFIE_Msk                 /*!<Tx FIFO Full interrupt Enable              */
11834 #define SDIO_MASK_RXFIFOFIE_Pos        (17U)
11835 #define SDIO_MASK_RXFIFOFIE_Msk        (0x1UL << SDIO_MASK_RXFIFOFIE_Pos)       /*!< 0x00020000 */
11836 #define SDIO_MASK_RXFIFOFIE            SDIO_MASK_RXFIFOFIE_Msk                 /*!<Rx FIFO Full interrupt Enable              */
11837 #define SDIO_MASK_TXFIFOEIE_Pos        (18U)
11838 #define SDIO_MASK_TXFIFOEIE_Msk        (0x1UL << SDIO_MASK_TXFIFOEIE_Pos)       /*!< 0x00040000 */
11839 #define SDIO_MASK_TXFIFOEIE            SDIO_MASK_TXFIFOEIE_Msk                 /*!<Tx FIFO Empty interrupt Enable             */
11840 #define SDIO_MASK_RXFIFOEIE_Pos        (19U)
11841 #define SDIO_MASK_RXFIFOEIE_Msk        (0x1UL << SDIO_MASK_RXFIFOEIE_Pos)       /*!< 0x00080000 */
11842 #define SDIO_MASK_RXFIFOEIE            SDIO_MASK_RXFIFOEIE_Msk                 /*!<Rx FIFO Empty interrupt Enable             */
11843 #define SDIO_MASK_TXDAVLIE_Pos         (20U)
11844 #define SDIO_MASK_TXDAVLIE_Msk         (0x1UL << SDIO_MASK_TXDAVLIE_Pos)        /*!< 0x00100000 */
11845 #define SDIO_MASK_TXDAVLIE             SDIO_MASK_TXDAVLIE_Msk                  /*!<Data available in Tx FIFO interrupt Enable */
11846 #define SDIO_MASK_RXDAVLIE_Pos         (21U)
11847 #define SDIO_MASK_RXDAVLIE_Msk         (0x1UL << SDIO_MASK_RXDAVLIE_Pos)        /*!< 0x00200000 */
11848 #define SDIO_MASK_RXDAVLIE             SDIO_MASK_RXDAVLIE_Msk                  /*!<Data available in Rx FIFO interrupt Enable */
11849 #define SDIO_MASK_SDIOITIE_Pos         (22U)
11850 #define SDIO_MASK_SDIOITIE_Msk         (0x1UL << SDIO_MASK_SDIOITIE_Pos)        /*!< 0x00400000 */
11851 #define SDIO_MASK_SDIOITIE             SDIO_MASK_SDIOITIE_Msk                  /*!<SDIO Mode Interrupt Received interrupt Enable */
11852 
11853 /*****************  Bit definition for SDIO_FIFOCNT register  *****************/
11854 #define SDIO_FIFOCNT_FIFOCOUNT_Pos     (0U)
11855 #define SDIO_FIFOCNT_FIFOCOUNT_Msk     (0xFFFFFFUL << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
11856 #define SDIO_FIFOCNT_FIFOCOUNT         SDIO_FIFOCNT_FIFOCOUNT_Msk              /*!<Remaining number of words to be written to or read from the FIFO */
11857 
11858 /******************  Bit definition for SDIO_FIFO register  *******************/
11859 #define SDIO_FIFO_FIFODATA_Pos         (0U)
11860 #define SDIO_FIFO_FIFODATA_Msk         (0xFFFFFFFFUL << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
11861 #define SDIO_FIFO_FIFODATA             SDIO_FIFO_FIFODATA_Msk                  /*!<Receive and transmit FIFO data */
11862 
11863 /******************************************************************************/
11864 /*                                                                            */
11865 /*                        Serial Peripheral Interface                         */
11866 /*                                                                            */
11867 /******************************************************************************/
11868 #define SPI_I2S_FULLDUPLEX_SUPPORT                                             /*!< I2S Full-Duplex support */
11869 #define I2S_APB1_APB2_FEATURE                                                  /*!< I2S IP's are splited between RCC APB1 and APB2 interfaces */
11870 
11871 /*******************  Bit definition for SPI_CR1 register  ********************/
11872 #define SPI_CR1_CPHA_Pos            (0U)
11873 #define SPI_CR1_CPHA_Msk            (0x1UL << SPI_CR1_CPHA_Pos)                 /*!< 0x00000001 */
11874 #define SPI_CR1_CPHA                SPI_CR1_CPHA_Msk                           /*!<Clock Phase      */
11875 #define SPI_CR1_CPOL_Pos            (1U)
11876 #define SPI_CR1_CPOL_Msk            (0x1UL << SPI_CR1_CPOL_Pos)                 /*!< 0x00000002 */
11877 #define SPI_CR1_CPOL                SPI_CR1_CPOL_Msk                           /*!<Clock Polarity   */
11878 #define SPI_CR1_MSTR_Pos            (2U)
11879 #define SPI_CR1_MSTR_Msk            (0x1UL << SPI_CR1_MSTR_Pos)                 /*!< 0x00000004 */
11880 #define SPI_CR1_MSTR                SPI_CR1_MSTR_Msk                           /*!<Master Selection */
11881 
11882 #define SPI_CR1_BR_Pos              (3U)
11883 #define SPI_CR1_BR_Msk              (0x7UL << SPI_CR1_BR_Pos)                   /*!< 0x00000038 */
11884 #define SPI_CR1_BR                  SPI_CR1_BR_Msk                             /*!<BR[2:0] bits (Baud Rate Control) */
11885 #define SPI_CR1_BR_0                (0x1UL << SPI_CR1_BR_Pos)                   /*!< 0x00000008 */
11886 #define SPI_CR1_BR_1                (0x2UL << SPI_CR1_BR_Pos)                   /*!< 0x00000010 */
11887 #define SPI_CR1_BR_2                (0x4UL << SPI_CR1_BR_Pos)                   /*!< 0x00000020 */
11888 
11889 #define SPI_CR1_SPE_Pos             (6U)
11890 #define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                  /*!< 0x00000040 */
11891 #define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!<SPI Enable                          */
11892 #define SPI_CR1_LSBFIRST_Pos        (7U)
11893 #define SPI_CR1_LSBFIRST_Msk        (0x1UL << SPI_CR1_LSBFIRST_Pos)             /*!< 0x00000080 */
11894 #define SPI_CR1_LSBFIRST            SPI_CR1_LSBFIRST_Msk                       /*!<Frame Format                        */
11895 #define SPI_CR1_SSI_Pos             (8U)
11896 #define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                  /*!< 0x00000100 */
11897 #define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!<Internal slave select               */
11898 #define SPI_CR1_SSM_Pos             (9U)
11899 #define SPI_CR1_SSM_Msk             (0x1UL << SPI_CR1_SSM_Pos)                  /*!< 0x00000200 */
11900 #define SPI_CR1_SSM                 SPI_CR1_SSM_Msk                            /*!<Software slave management           */
11901 #define SPI_CR1_RXONLY_Pos          (10U)
11902 #define SPI_CR1_RXONLY_Msk          (0x1UL << SPI_CR1_RXONLY_Pos)               /*!< 0x00000400 */
11903 #define SPI_CR1_RXONLY              SPI_CR1_RXONLY_Msk                         /*!<Receive only                        */
11904 #define SPI_CR1_DFF_Pos             (11U)
11905 #define SPI_CR1_DFF_Msk             (0x1UL << SPI_CR1_DFF_Pos)                  /*!< 0x00000800 */
11906 #define SPI_CR1_DFF                 SPI_CR1_DFF_Msk                            /*!<Data Frame Format                   */
11907 #define SPI_CR1_CRCNEXT_Pos         (12U)
11908 #define SPI_CR1_CRCNEXT_Msk         (0x1UL << SPI_CR1_CRCNEXT_Pos)              /*!< 0x00001000 */
11909 #define SPI_CR1_CRCNEXT             SPI_CR1_CRCNEXT_Msk                        /*!<Transmit CRC next                   */
11910 #define SPI_CR1_CRCEN_Pos           (13U)
11911 #define SPI_CR1_CRCEN_Msk           (0x1UL << SPI_CR1_CRCEN_Pos)                /*!< 0x00002000 */
11912 #define SPI_CR1_CRCEN               SPI_CR1_CRCEN_Msk                          /*!<Hardware CRC calculation enable     */
11913 #define SPI_CR1_BIDIOE_Pos          (14U)
11914 #define SPI_CR1_BIDIOE_Msk          (0x1UL << SPI_CR1_BIDIOE_Pos)               /*!< 0x00004000 */
11915 #define SPI_CR1_BIDIOE              SPI_CR1_BIDIOE_Msk                         /*!<Output enable in bidirectional mode */
11916 #define SPI_CR1_BIDIMODE_Pos        (15U)
11917 #define SPI_CR1_BIDIMODE_Msk        (0x1UL << SPI_CR1_BIDIMODE_Pos)             /*!< 0x00008000 */
11918 #define SPI_CR1_BIDIMODE            SPI_CR1_BIDIMODE_Msk                       /*!<Bidirectional data mode enable      */
11919 
11920 /*******************  Bit definition for SPI_CR2 register  ********************/
11921 #define SPI_CR2_RXDMAEN_Pos         (0U)
11922 #define SPI_CR2_RXDMAEN_Msk         (0x1UL << SPI_CR2_RXDMAEN_Pos)              /*!< 0x00000001 */
11923 #define SPI_CR2_RXDMAEN             SPI_CR2_RXDMAEN_Msk                        /*!<Rx Buffer DMA Enable                 */
11924 #define SPI_CR2_TXDMAEN_Pos         (1U)
11925 #define SPI_CR2_TXDMAEN_Msk         (0x1UL << SPI_CR2_TXDMAEN_Pos)              /*!< 0x00000002 */
11926 #define SPI_CR2_TXDMAEN             SPI_CR2_TXDMAEN_Msk                        /*!<Tx Buffer DMA Enable                 */
11927 #define SPI_CR2_SSOE_Pos            (2U)
11928 #define SPI_CR2_SSOE_Msk            (0x1UL << SPI_CR2_SSOE_Pos)                 /*!< 0x00000004 */
11929 #define SPI_CR2_SSOE                SPI_CR2_SSOE_Msk                           /*!<SS Output Enable                     */
11930 #define SPI_CR2_FRF_Pos             (4U)
11931 #define SPI_CR2_FRF_Msk             (0x1UL << SPI_CR2_FRF_Pos)                  /*!< 0x00000010 */
11932 #define SPI_CR2_FRF                 SPI_CR2_FRF_Msk                            /*!<Frame Format                         */
11933 #define SPI_CR2_ERRIE_Pos           (5U)
11934 #define SPI_CR2_ERRIE_Msk           (0x1UL << SPI_CR2_ERRIE_Pos)                /*!< 0x00000020 */
11935 #define SPI_CR2_ERRIE               SPI_CR2_ERRIE_Msk                          /*!<Error Interrupt Enable               */
11936 #define SPI_CR2_RXNEIE_Pos          (6U)
11937 #define SPI_CR2_RXNEIE_Msk          (0x1UL << SPI_CR2_RXNEIE_Pos)               /*!< 0x00000040 */
11938 #define SPI_CR2_RXNEIE              SPI_CR2_RXNEIE_Msk                         /*!<RX buffer Not Empty Interrupt Enable */
11939 #define SPI_CR2_TXEIE_Pos           (7U)
11940 #define SPI_CR2_TXEIE_Msk           (0x1UL << SPI_CR2_TXEIE_Pos)                /*!< 0x00000080 */
11941 #define SPI_CR2_TXEIE               SPI_CR2_TXEIE_Msk                          /*!<Tx buffer Empty Interrupt Enable     */
11942 
11943 /********************  Bit definition for SPI_SR register  ********************/
11944 #define SPI_SR_RXNE_Pos             (0U)
11945 #define SPI_SR_RXNE_Msk             (0x1UL << SPI_SR_RXNE_Pos)                  /*!< 0x00000001 */
11946 #define SPI_SR_RXNE                 SPI_SR_RXNE_Msk                            /*!<Receive buffer Not Empty */
11947 #define SPI_SR_TXE_Pos              (1U)
11948 #define SPI_SR_TXE_Msk              (0x1UL << SPI_SR_TXE_Pos)                   /*!< 0x00000002 */
11949 #define SPI_SR_TXE                  SPI_SR_TXE_Msk                             /*!<Transmit buffer Empty    */
11950 #define SPI_SR_CHSIDE_Pos           (2U)
11951 #define SPI_SR_CHSIDE_Msk           (0x1UL << SPI_SR_CHSIDE_Pos)                /*!< 0x00000004 */
11952 #define SPI_SR_CHSIDE               SPI_SR_CHSIDE_Msk                          /*!<Channel side             */
11953 #define SPI_SR_UDR_Pos              (3U)
11954 #define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                   /*!< 0x00000008 */
11955 #define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!<Underrun flag            */
11956 #define SPI_SR_CRCERR_Pos           (4U)
11957 #define SPI_SR_CRCERR_Msk           (0x1UL << SPI_SR_CRCERR_Pos)                /*!< 0x00000010 */
11958 #define SPI_SR_CRCERR               SPI_SR_CRCERR_Msk                          /*!<CRC Error flag           */
11959 #define SPI_SR_MODF_Pos             (5U)
11960 #define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                  /*!< 0x00000020 */
11961 #define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!<Mode fault               */
11962 #define SPI_SR_OVR_Pos              (6U)
11963 #define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                   /*!< 0x00000040 */
11964 #define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!<Overrun flag             */
11965 #define SPI_SR_BSY_Pos              (7U)
11966 #define SPI_SR_BSY_Msk              (0x1UL << SPI_SR_BSY_Pos)                   /*!< 0x00000080 */
11967 #define SPI_SR_BSY                  SPI_SR_BSY_Msk                             /*!<Busy flag                */
11968 #define SPI_SR_FRE_Pos              (8U)
11969 #define SPI_SR_FRE_Msk              (0x1UL << SPI_SR_FRE_Pos)                   /*!< 0x00000100 */
11970 #define SPI_SR_FRE                  SPI_SR_FRE_Msk                             /*!<Frame format error flag  */
11971 
11972 /********************  Bit definition for SPI_DR register  ********************/
11973 #define SPI_DR_DR_Pos               (0U)
11974 #define SPI_DR_DR_Msk               (0xFFFFUL << SPI_DR_DR_Pos)                 /*!< 0x0000FFFF */
11975 #define SPI_DR_DR                   SPI_DR_DR_Msk                              /*!<Data Register           */
11976 
11977 /*******************  Bit definition for SPI_CRCPR register  ******************/
11978 #define SPI_CRCPR_CRCPOLY_Pos       (0U)
11979 #define SPI_CRCPR_CRCPOLY_Msk       (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)         /*!< 0x0000FFFF */
11980 #define SPI_CRCPR_CRCPOLY           SPI_CRCPR_CRCPOLY_Msk                      /*!<CRC polynomial register */
11981 
11982 /******************  Bit definition for SPI_RXCRCR register  ******************/
11983 #define SPI_RXCRCR_RXCRC_Pos        (0U)
11984 #define SPI_RXCRCR_RXCRC_Msk        (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)          /*!< 0x0000FFFF */
11985 #define SPI_RXCRCR_RXCRC            SPI_RXCRCR_RXCRC_Msk                       /*!<Rx CRC Register         */
11986 
11987 /******************  Bit definition for SPI_TXCRCR register  ******************/
11988 #define SPI_TXCRCR_TXCRC_Pos        (0U)
11989 #define SPI_TXCRCR_TXCRC_Msk        (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)          /*!< 0x0000FFFF */
11990 #define SPI_TXCRCR_TXCRC            SPI_TXCRCR_TXCRC_Msk                       /*!<Tx CRC Register         */
11991 
11992 /******************  Bit definition for SPI_I2SCFGR register  *****************/
11993 #define SPI_I2SCFGR_CHLEN_Pos       (0U)
11994 #define SPI_I2SCFGR_CHLEN_Msk       (0x1UL << SPI_I2SCFGR_CHLEN_Pos)            /*!< 0x00000001 */
11995 #define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */
11996 
11997 #define SPI_I2SCFGR_DATLEN_Pos      (1U)
11998 #define SPI_I2SCFGR_DATLEN_Msk      (0x3UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000006 */
11999 #define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] bits (Data length to be transferred)  */
12000 #define SPI_I2SCFGR_DATLEN_0        (0x1UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000002 */
12001 #define SPI_I2SCFGR_DATLEN_1        (0x2UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000004 */
12002 
12003 #define SPI_I2SCFGR_CKPOL_Pos       (3U)
12004 #define SPI_I2SCFGR_CKPOL_Msk       (0x1UL << SPI_I2SCFGR_CKPOL_Pos)            /*!< 0x00000008 */
12005 #define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<steady state clock polarity               */
12006 
12007 #define SPI_I2SCFGR_I2SSTD_Pos      (4U)
12008 #define SPI_I2SCFGR_I2SSTD_Msk      (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000030 */
12009 #define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] bits (I2S standard selection) */
12010 #define SPI_I2SCFGR_I2SSTD_0        (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000010 */
12011 #define SPI_I2SCFGR_I2SSTD_1        (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000020 */
12012 
12013 #define SPI_I2SCFGR_PCMSYNC_Pos     (7U)
12014 #define SPI_I2SCFGR_PCMSYNC_Msk     (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)          /*!< 0x00000080 */
12015 #define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization                 */
12016 
12017 #define SPI_I2SCFGR_I2SCFG_Pos      (8U)
12018 #define SPI_I2SCFGR_I2SCFG_Msk      (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000300 */
12019 #define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[1:0] bits (I2S configuration mode) */
12020 #define SPI_I2SCFGR_I2SCFG_0        (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000100 */
12021 #define SPI_I2SCFGR_I2SCFG_1        (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000200 */
12022 
12023 #define SPI_I2SCFGR_I2SE_Pos        (10U)
12024 #define SPI_I2SCFGR_I2SE_Msk        (0x1UL << SPI_I2SCFGR_I2SE_Pos)             /*!< 0x00000400 */
12025 #define SPI_I2SCFGR_I2SE            SPI_I2SCFGR_I2SE_Msk                       /*!<I2S Enable         */
12026 #define SPI_I2SCFGR_I2SMOD_Pos      (11U)
12027 #define SPI_I2SCFGR_I2SMOD_Msk      (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)           /*!< 0x00000800 */
12028 #define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */
12029 #define SPI_I2SCFGR_ASTRTEN_Pos     (12U)
12030 #define SPI_I2SCFGR_ASTRTEN_Msk     (0x1UL << SPI_I2SCFGR_ASTRTEN_Pos)          /*!< 0x00001000 */
12031 #define SPI_I2SCFGR_ASTRTEN         SPI_I2SCFGR_ASTRTEN_Msk                    /*!<Asynchronous start enable */
12032 
12033 /******************  Bit definition for SPI_I2SPR register  *******************/
12034 #define SPI_I2SPR_I2SDIV_Pos        (0U)
12035 #define SPI_I2SPR_I2SDIV_Msk        (0xFFUL << SPI_I2SPR_I2SDIV_Pos)            /*!< 0x000000FF */
12036 #define SPI_I2SPR_I2SDIV            SPI_I2SPR_I2SDIV_Msk                       /*!<I2S Linear prescaler         */
12037 #define SPI_I2SPR_ODD_Pos           (8U)
12038 #define SPI_I2SPR_ODD_Msk           (0x1UL << SPI_I2SPR_ODD_Pos)                /*!< 0x00000100 */
12039 #define SPI_I2SPR_ODD               SPI_I2SPR_ODD_Msk                          /*!<Odd factor for the prescaler */
12040 #define SPI_I2SPR_MCKOE_Pos         (9U)
12041 #define SPI_I2SPR_MCKOE_Msk         (0x1UL << SPI_I2SPR_MCKOE_Pos)              /*!< 0x00000200 */
12042 #define SPI_I2SPR_MCKOE             SPI_I2SPR_MCKOE_Msk                        /*!<Master Clock Output Enable   */
12043 
12044 /******************************************************************************/
12045 /*                                                                            */
12046 /*                                 SYSCFG                                     */
12047 /*                                                                            */
12048 /******************************************************************************/
12049 /******************  Bit definition for SYSCFG_MEMRMP register  ***************/
12050 #define SYSCFG_MEMRMP_MEM_MODE_Pos           (0U)
12051 #define SYSCFG_MEMRMP_MEM_MODE_Msk           (0x3UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000003 */
12052 #define SYSCFG_MEMRMP_MEM_MODE               SYSCFG_MEMRMP_MEM_MODE_Msk        /*!< SYSCFG_Memory Remap Config */
12053 #define SYSCFG_MEMRMP_MEM_MODE_0             (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
12054 #define SYSCFG_MEMRMP_MEM_MODE_1             (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
12055 /******************  Bit definition for SYSCFG_PMC register  ******************/
12056 #define SYSCFG_PMC_ADC1DC2_Pos               (16U)
12057 #define SYSCFG_PMC_ADC1DC2_Msk               (0x1UL << SYSCFG_PMC_ADC1DC2_Pos)  /*!< 0x00010000 */
12058 #define SYSCFG_PMC_ADC1DC2                   SYSCFG_PMC_ADC1DC2_Msk            /*!< Refer to AN4073 on how to use this bit  */
12059 
12060 /*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
12061 #define SYSCFG_EXTICR1_EXTI0_Pos             (0U)
12062 #define SYSCFG_EXTICR1_EXTI0_Msk             (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
12063 #define SYSCFG_EXTICR1_EXTI0                 SYSCFG_EXTICR1_EXTI0_Msk          /*!<EXTI 0 configuration */
12064 #define SYSCFG_EXTICR1_EXTI1_Pos             (4U)
12065 #define SYSCFG_EXTICR1_EXTI1_Msk             (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
12066 #define SYSCFG_EXTICR1_EXTI1                 SYSCFG_EXTICR1_EXTI1_Msk          /*!<EXTI 1 configuration */
12067 #define SYSCFG_EXTICR1_EXTI2_Pos             (8U)
12068 #define SYSCFG_EXTICR1_EXTI2_Msk             (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
12069 #define SYSCFG_EXTICR1_EXTI2                 SYSCFG_EXTICR1_EXTI2_Msk          /*!<EXTI 2 configuration */
12070 #define SYSCFG_EXTICR1_EXTI3_Pos             (12U)
12071 #define SYSCFG_EXTICR1_EXTI3_Msk             (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
12072 #define SYSCFG_EXTICR1_EXTI3                 SYSCFG_EXTICR1_EXTI3_Msk          /*!<EXTI 3 configuration */
12073 /**
12074   * @brief   EXTI0 configuration
12075   */
12076 #define SYSCFG_EXTICR1_EXTI0_PA              0x0000U                           /*!<PA[0] pin */
12077 #define SYSCFG_EXTICR1_EXTI0_PB              0x0001U                           /*!<PB[0] pin */
12078 #define SYSCFG_EXTICR1_EXTI0_PC              0x0002U                           /*!<PC[0] pin */
12079 #define SYSCFG_EXTICR1_EXTI0_PD              0x0003U                           /*!<PD[0] pin */
12080 #define SYSCFG_EXTICR1_EXTI0_PE              0x0004U                           /*!<PE[0] pin */
12081 #define SYSCFG_EXTICR1_EXTI0_PF              0x0005U                           /*!<PF[0] pin */
12082 #define SYSCFG_EXTICR1_EXTI0_PG              0x0006U                           /*!<PG[0] pin */
12083 #define SYSCFG_EXTICR1_EXTI0_PH              0x0007U                           /*!<PH[0] pin */
12084 
12085 /**
12086   * @brief   EXTI1 configuration
12087   */
12088 #define SYSCFG_EXTICR1_EXTI1_PA              0x0000U                           /*!<PA[1] pin */
12089 #define SYSCFG_EXTICR1_EXTI1_PB              0x0010U                           /*!<PB[1] pin */
12090 #define SYSCFG_EXTICR1_EXTI1_PC              0x0020U                           /*!<PC[1] pin */
12091 #define SYSCFG_EXTICR1_EXTI1_PD              0x0030U                           /*!<PD[1] pin */
12092 #define SYSCFG_EXTICR1_EXTI1_PE              0x0040U                           /*!<PE[1] pin */
12093 #define SYSCFG_EXTICR1_EXTI1_PF              0x0050U                           /*!<PF[1] pin */
12094 #define SYSCFG_EXTICR1_EXTI1_PG              0x0060U                           /*!<PG[1] pin */
12095 #define SYSCFG_EXTICR1_EXTI1_PH              0x0070U                           /*!<PH[1] pin */
12096 
12097 /**
12098   * @brief   EXTI2 configuration
12099   */
12100 #define SYSCFG_EXTICR1_EXTI2_PA              0x0000U                           /*!<PA[2] pin */
12101 #define SYSCFG_EXTICR1_EXTI2_PB              0x0100U                           /*!<PB[2] pin */
12102 #define SYSCFG_EXTICR1_EXTI2_PC              0x0200U                           /*!<PC[2] pin */
12103 #define SYSCFG_EXTICR1_EXTI2_PD              0x0300U                           /*!<PD[2] pin */
12104 #define SYSCFG_EXTICR1_EXTI2_PE              0x0400U                           /*!<PE[2] pin */
12105 #define SYSCFG_EXTICR1_EXTI2_PF              0x0500U                           /*!<PF[2] pin */
12106 #define SYSCFG_EXTICR1_EXTI2_PG              0x0600U                           /*!<PG[2] pin */
12107 #define SYSCFG_EXTICR1_EXTI2_PH              0x0700U                           /*!<PH[2] pin */
12108 
12109 /**
12110   * @brief   EXTI3 configuration
12111   */
12112 #define SYSCFG_EXTICR1_EXTI3_PA              0x0000U                           /*!<PA[3] pin */
12113 #define SYSCFG_EXTICR1_EXTI3_PB              0x1000U                           /*!<PB[3] pin */
12114 #define SYSCFG_EXTICR1_EXTI3_PC              0x2000U                           /*!<PC[3] pin */
12115 #define SYSCFG_EXTICR1_EXTI3_PD              0x3000U                           /*!<PD[3] pin */
12116 #define SYSCFG_EXTICR1_EXTI3_PE              0x4000U                           /*!<PE[3] pin */
12117 #define SYSCFG_EXTICR1_EXTI3_PF              0x5000U                           /*!<PF[3] pin */
12118 #define SYSCFG_EXTICR1_EXTI3_PG              0x6000U                           /*!<PG[3] pin */
12119 #define SYSCFG_EXTICR1_EXTI3_PH              0x7000U                           /*!<PH[3] pin */
12120 
12121 /*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
12122 #define SYSCFG_EXTICR2_EXTI4_Pos             (0U)
12123 #define SYSCFG_EXTICR2_EXTI4_Msk             (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
12124 #define SYSCFG_EXTICR2_EXTI4                 SYSCFG_EXTICR2_EXTI4_Msk          /*!<EXTI 4 configuration */
12125 #define SYSCFG_EXTICR2_EXTI5_Pos             (4U)
12126 #define SYSCFG_EXTICR2_EXTI5_Msk             (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
12127 #define SYSCFG_EXTICR2_EXTI5                 SYSCFG_EXTICR2_EXTI5_Msk          /*!<EXTI 5 configuration */
12128 #define SYSCFG_EXTICR2_EXTI6_Pos             (8U)
12129 #define SYSCFG_EXTICR2_EXTI6_Msk             (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
12130 #define SYSCFG_EXTICR2_EXTI6                 SYSCFG_EXTICR2_EXTI6_Msk          /*!<EXTI 6 configuration */
12131 #define SYSCFG_EXTICR2_EXTI7_Pos             (12U)
12132 #define SYSCFG_EXTICR2_EXTI7_Msk             (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
12133 #define SYSCFG_EXTICR2_EXTI7                 SYSCFG_EXTICR2_EXTI7_Msk          /*!<EXTI 7 configuration */
12134 
12135 /**
12136   * @brief   EXTI4 configuration
12137   */
12138 #define SYSCFG_EXTICR2_EXTI4_PA              0x0000U                           /*!<PA[4] pin */
12139 #define SYSCFG_EXTICR2_EXTI4_PB              0x0001U                           /*!<PB[4] pin */
12140 #define SYSCFG_EXTICR2_EXTI4_PC              0x0002U                           /*!<PC[4] pin */
12141 #define SYSCFG_EXTICR2_EXTI4_PD              0x0003U                           /*!<PD[4] pin */
12142 #define SYSCFG_EXTICR2_EXTI4_PE              0x0004U                           /*!<PE[4] pin */
12143 #define SYSCFG_EXTICR2_EXTI4_PF              0x0005U                           /*!<PF[4] pin */
12144 #define SYSCFG_EXTICR2_EXTI4_PG              0x0006U                           /*!<PG[4] pin */
12145 #define SYSCFG_EXTICR2_EXTI4_PH              0x0007U                           /*!<PH[4] pin */
12146 
12147 /**
12148   * @brief   EXTI5 configuration
12149   */
12150 #define SYSCFG_EXTICR2_EXTI5_PA              0x0000U                           /*!<PA[5] pin */
12151 #define SYSCFG_EXTICR2_EXTI5_PB              0x0010U                           /*!<PB[5] pin */
12152 #define SYSCFG_EXTICR2_EXTI5_PC              0x0020U                           /*!<PC[5] pin */
12153 #define SYSCFG_EXTICR2_EXTI5_PD              0x0030U                           /*!<PD[5] pin */
12154 #define SYSCFG_EXTICR2_EXTI5_PE              0x0040U                           /*!<PE[5] pin */
12155 #define SYSCFG_EXTICR2_EXTI5_PF              0x0050U                           /*!<PF[5] pin */
12156 #define SYSCFG_EXTICR2_EXTI5_PG              0x0060U                           /*!<PG[5] pin */
12157 #define SYSCFG_EXTICR2_EXTI5_PH              0x0070U                           /*!<PH[5] pin */
12158 
12159 /**
12160   * @brief   EXTI6 configuration
12161   */
12162 #define SYSCFG_EXTICR2_EXTI6_PA              0x0000U                           /*!<PA[6] pin */
12163 #define SYSCFG_EXTICR2_EXTI6_PB              0x0100U                           /*!<PB[6] pin */
12164 #define SYSCFG_EXTICR2_EXTI6_PC              0x0200U                           /*!<PC[6] pin */
12165 #define SYSCFG_EXTICR2_EXTI6_PD              0x0300U                           /*!<PD[6] pin */
12166 #define SYSCFG_EXTICR2_EXTI6_PE              0x0400U                           /*!<PE[6] pin */
12167 #define SYSCFG_EXTICR2_EXTI6_PF              0x0500U                           /*!<PF[6] pin */
12168 #define SYSCFG_EXTICR2_EXTI6_PG              0x0600U                           /*!<PG[6] pin */
12169 #define SYSCFG_EXTICR2_EXTI6_PH              0x0700U                           /*!<PH[6] pin */
12170 
12171 /**
12172   * @brief   EXTI7 configuration
12173   */
12174 #define SYSCFG_EXTICR2_EXTI7_PA              0x0000U                           /*!<PA[7] pin */
12175 #define SYSCFG_EXTICR2_EXTI7_PB              0x1000U                           /*!<PB[7] pin */
12176 #define SYSCFG_EXTICR2_EXTI7_PC              0x2000U                           /*!<PC[7] pin */
12177 #define SYSCFG_EXTICR2_EXTI7_PD              0x3000U                           /*!<PD[7] pin */
12178 #define SYSCFG_EXTICR2_EXTI7_PE              0x4000U                           /*!<PE[7] pin */
12179 #define SYSCFG_EXTICR2_EXTI7_PF              0x5000U                           /*!<PF[7] pin */
12180 #define SYSCFG_EXTICR2_EXTI7_PG              0x6000U                           /*!<PG[7] pin */
12181 #define SYSCFG_EXTICR2_EXTI7_PH              0x7000U                           /*!<PH[7] pin */
12182 
12183 /*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
12184 #define SYSCFG_EXTICR3_EXTI8_Pos             (0U)
12185 #define SYSCFG_EXTICR3_EXTI8_Msk             (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
12186 #define SYSCFG_EXTICR3_EXTI8                 SYSCFG_EXTICR3_EXTI8_Msk          /*!<EXTI 8 configuration */
12187 #define SYSCFG_EXTICR3_EXTI9_Pos             (4U)
12188 #define SYSCFG_EXTICR3_EXTI9_Msk             (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
12189 #define SYSCFG_EXTICR3_EXTI9                 SYSCFG_EXTICR3_EXTI9_Msk          /*!<EXTI 9 configuration */
12190 #define SYSCFG_EXTICR3_EXTI10_Pos            (8U)
12191 #define SYSCFG_EXTICR3_EXTI10_Msk            (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
12192 #define SYSCFG_EXTICR3_EXTI10                SYSCFG_EXTICR3_EXTI10_Msk         /*!<EXTI 10 configuration */
12193 #define SYSCFG_EXTICR3_EXTI11_Pos            (12U)
12194 #define SYSCFG_EXTICR3_EXTI11_Msk            (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
12195 #define SYSCFG_EXTICR3_EXTI11                SYSCFG_EXTICR3_EXTI11_Msk         /*!<EXTI 11 configuration */
12196 
12197 /**
12198   * @brief   EXTI8 configuration
12199   */
12200 #define SYSCFG_EXTICR3_EXTI8_PA              0x0000U                           /*!<PA[8] pin */
12201 #define SYSCFG_EXTICR3_EXTI8_PB              0x0001U                           /*!<PB[8] pin */
12202 #define SYSCFG_EXTICR3_EXTI8_PC              0x0002U                           /*!<PC[8] pin */
12203 #define SYSCFG_EXTICR3_EXTI8_PD              0x0003U                           /*!<PD[8] pin */
12204 #define SYSCFG_EXTICR3_EXTI8_PE              0x0004U                           /*!<PE[8] pin */
12205 #define SYSCFG_EXTICR3_EXTI8_PF              0x0005U                           /*!<PF[8] pin */
12206 #define SYSCFG_EXTICR3_EXTI8_PG              0x0006U                           /*!<PG[8] pin */
12207 #define SYSCFG_EXTICR3_EXTI8_PH              0x0007U                           /*!<PH[8] pin */
12208 
12209 /**
12210   * @brief   EXTI9 configuration
12211   */
12212 #define SYSCFG_EXTICR3_EXTI9_PA              0x0000U                           /*!<PA[9] pin */
12213 #define SYSCFG_EXTICR3_EXTI9_PB              0x0010U                           /*!<PB[9] pin */
12214 #define SYSCFG_EXTICR3_EXTI9_PC              0x0020U                           /*!<PC[9] pin */
12215 #define SYSCFG_EXTICR3_EXTI9_PD              0x0030U                           /*!<PD[9] pin */
12216 #define SYSCFG_EXTICR3_EXTI9_PE              0x0040U                           /*!<PE[9] pin */
12217 #define SYSCFG_EXTICR3_EXTI9_PF              0x0050U                           /*!<PF[9] pin */
12218 #define SYSCFG_EXTICR3_EXTI9_PG              0x0060U                           /*!<PG[9] pin */
12219 #define SYSCFG_EXTICR3_EXTI9_PH              0x0070U                           /*!<PH[9] pin */
12220 
12221 /**
12222   * @brief   EXTI10 configuration
12223   */
12224 #define SYSCFG_EXTICR3_EXTI10_PA             0x0000U                           /*!<PA[10] pin */
12225 #define SYSCFG_EXTICR3_EXTI10_PB             0x0100U                           /*!<PB[10] pin */
12226 #define SYSCFG_EXTICR3_EXTI10_PC             0x0200U                           /*!<PC[10] pin */
12227 #define SYSCFG_EXTICR3_EXTI10_PD             0x0300U                           /*!<PD[10] pin */
12228 #define SYSCFG_EXTICR3_EXTI10_PE             0x0400U                           /*!<PE[10] pin */
12229 #define SYSCFG_EXTICR3_EXTI10_PF             0x0500U                           /*!<PF[10] pin */
12230 #define SYSCFG_EXTICR3_EXTI10_PG             0x0600U                           /*!<PG[10] pin */
12231 #define SYSCFG_EXTICR3_EXTI10_PH             0x0700U                           /*!<PH[10] pin */
12232 
12233 /**
12234   * @brief   EXTI11 configuration
12235   */
12236 #define SYSCFG_EXTICR3_EXTI11_PA             0x0000U                           /*!<PA[11] pin */
12237 #define SYSCFG_EXTICR3_EXTI11_PB             0x1000U                           /*!<PB[11] pin */
12238 #define SYSCFG_EXTICR3_EXTI11_PC             0x2000U                           /*!<PC[11] pin */
12239 #define SYSCFG_EXTICR3_EXTI11_PD             0x3000U                           /*!<PD[11] pin */
12240 #define SYSCFG_EXTICR3_EXTI11_PE             0x4000U                           /*!<PE[11] pin */
12241 #define SYSCFG_EXTICR3_EXTI11_PF             0x5000U                           /*!<PF[11] pin */
12242 #define SYSCFG_EXTICR3_EXTI11_PG             0x6000U                           /*!<PG[11] pin */
12243 #define SYSCFG_EXTICR3_EXTI11_PH             0x7000U                           /*!<PH[11] pin */
12244 
12245 /*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
12246 #define SYSCFG_EXTICR4_EXTI12_Pos            (0U)
12247 #define SYSCFG_EXTICR4_EXTI12_Msk            (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
12248 #define SYSCFG_EXTICR4_EXTI12                SYSCFG_EXTICR4_EXTI12_Msk         /*!<EXTI 12 configuration */
12249 #define SYSCFG_EXTICR4_EXTI13_Pos            (4U)
12250 #define SYSCFG_EXTICR4_EXTI13_Msk            (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
12251 #define SYSCFG_EXTICR4_EXTI13                SYSCFG_EXTICR4_EXTI13_Msk         /*!<EXTI 13 configuration */
12252 #define SYSCFG_EXTICR4_EXTI14_Pos            (8U)
12253 #define SYSCFG_EXTICR4_EXTI14_Msk            (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
12254 #define SYSCFG_EXTICR4_EXTI14                SYSCFG_EXTICR4_EXTI14_Msk         /*!<EXTI 14 configuration */
12255 #define SYSCFG_EXTICR4_EXTI15_Pos            (12U)
12256 #define SYSCFG_EXTICR4_EXTI15_Msk            (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
12257 #define SYSCFG_EXTICR4_EXTI15                SYSCFG_EXTICR4_EXTI15_Msk         /*!<EXTI 15 configuration */
12258 
12259 /**
12260   * @brief   EXTI12 configuration
12261   */
12262 #define SYSCFG_EXTICR4_EXTI12_PA             0x0000U                           /*!<PA[12] pin */
12263 #define SYSCFG_EXTICR4_EXTI12_PB             0x0001U                           /*!<PB[12] pin */
12264 #define SYSCFG_EXTICR4_EXTI12_PC             0x0002U                           /*!<PC[12] pin */
12265 #define SYSCFG_EXTICR4_EXTI12_PD             0x0003U                           /*!<PD[12] pin */
12266 #define SYSCFG_EXTICR4_EXTI12_PE             0x0004U                           /*!<PE[12] pin */
12267 #define SYSCFG_EXTICR4_EXTI12_PF             0x0005U                           /*!<PF[12] pin */
12268 #define SYSCFG_EXTICR4_EXTI12_PG             0x0006U                           /*!<PG[12] pin */
12269 #define SYSCFG_EXTICR4_EXTI12_PH             0x0007U                           /*!<PH[12] pin */
12270 
12271 /**
12272   * @brief   EXTI13 configuration
12273   */
12274 #define SYSCFG_EXTICR4_EXTI13_PA             0x0000U                           /*!<PA[13] pin */
12275 #define SYSCFG_EXTICR4_EXTI13_PB             0x0010U                           /*!<PB[13] pin */
12276 #define SYSCFG_EXTICR4_EXTI13_PC             0x0020U                           /*!<PC[13] pin */
12277 #define SYSCFG_EXTICR4_EXTI13_PD             0x0030U                           /*!<PD[13] pin */
12278 #define SYSCFG_EXTICR4_EXTI13_PE             0x0040U                           /*!<PE[13] pin */
12279 #define SYSCFG_EXTICR4_EXTI13_PF             0x0050U                           /*!<PF[13] pin */
12280 #define SYSCFG_EXTICR4_EXTI13_PG             0x0060U                           /*!<PG[13] pin */
12281 #define SYSCFG_EXTICR4_EXTI13_PH             0x0070U                           /*!<PH[13] pin */
12282 
12283 /**
12284   * @brief   EXTI14 configuration
12285   */
12286 #define SYSCFG_EXTICR4_EXTI14_PA             0x0000U                           /*!<PA[14] pin */
12287 #define SYSCFG_EXTICR4_EXTI14_PB             0x0100U                           /*!<PB[14] pin */
12288 #define SYSCFG_EXTICR4_EXTI14_PC             0x0200U                           /*!<PC[14] pin */
12289 #define SYSCFG_EXTICR4_EXTI14_PD             0x0300U                           /*!<PD[14] pin */
12290 #define SYSCFG_EXTICR4_EXTI14_PE             0x0400U                           /*!<PE[14] pin */
12291 #define SYSCFG_EXTICR4_EXTI14_PF             0x0500U                           /*!<PF[14] pin */
12292 #define SYSCFG_EXTICR4_EXTI14_PG             0x0600U                           /*!<PG[14] pin */
12293 #define SYSCFG_EXTICR4_EXTI14_PH             0x0700U                           /*!<PH[14] pin */
12294 
12295 /**
12296   * @brief   EXTI15 configuration
12297   */
12298 #define SYSCFG_EXTICR4_EXTI15_PA             0x0000U                           /*!<PA[15] pin */
12299 #define SYSCFG_EXTICR4_EXTI15_PB             0x1000U                           /*!<PB[15] pin */
12300 #define SYSCFG_EXTICR4_EXTI15_PC             0x2000U                           /*!<PC[15] pin */
12301 #define SYSCFG_EXTICR4_EXTI15_PD             0x3000U                           /*!<PD[15] pin */
12302 #define SYSCFG_EXTICR4_EXTI15_PE             0x4000U                           /*!<PE[15] pin */
12303 #define SYSCFG_EXTICR4_EXTI15_PF             0x5000U                           /*!<PF[15] pin */
12304 #define SYSCFG_EXTICR4_EXTI15_PG             0x6000U                           /*!<PG[15] pin */
12305 #define SYSCFG_EXTICR4_EXTI15_PH             0x7000U                           /*!<PH[15] pin */
12306 
12307 /******************  Bit definition for SYSCFG_CMPCR register  ****************/
12308 #define SYSCFG_CMPCR_CMP_PD_Pos              (0U)
12309 #define SYSCFG_CMPCR_CMP_PD_Msk              (0x1UL << SYSCFG_CMPCR_CMP_PD_Pos) /*!< 0x00000001 */
12310 #define SYSCFG_CMPCR_CMP_PD                  SYSCFG_CMPCR_CMP_PD_Msk           /*!<Compensation cell ready flag */
12311 #define SYSCFG_CMPCR_READY_Pos               (8U)
12312 #define SYSCFG_CMPCR_READY_Msk               (0x1UL << SYSCFG_CMPCR_READY_Pos)  /*!< 0x00000100 */
12313 #define SYSCFG_CMPCR_READY                   SYSCFG_CMPCR_READY_Msk            /*!<Compensation cell power-down */
12314 /******************  Bit definition for SYSCFG_CFGR register  *****************/
12315 #define SYSCFG_CFGR_FMPI2C1_SCL_Pos          (0U)
12316 #define SYSCFG_CFGR_FMPI2C1_SCL_Msk          (0x1UL << SYSCFG_CFGR_FMPI2C1_SCL_Pos) /*!< 0x00000001 */
12317 #define SYSCFG_CFGR_FMPI2C1_SCL              SYSCFG_CFGR_FMPI2C1_SCL_Msk       /*!<FM+ drive capability for FMPI2C1_SCL pin */
12318 #define SYSCFG_CFGR_FMPI2C1_SDA_Pos          (1U)
12319 #define SYSCFG_CFGR_FMPI2C1_SDA_Msk          (0x1UL << SYSCFG_CFGR_FMPI2C1_SDA_Pos) /*!< 0x00000002 */
12320 #define SYSCFG_CFGR_FMPI2C1_SDA              SYSCFG_CFGR_FMPI2C1_SDA_Msk       /*!<FM+ drive capability for FMPI2C1_SDA pin */
12321 
12322 /******************  Bit definition for SYSCFG_CFGR2 register  *****************/
12323 #define SYSCFG_CFGR2_LOCKUP_LOCK_Pos         (0U)
12324 #define SYSCFG_CFGR2_LOCKUP_LOCK_Msk         (0x1UL << SYSCFG_CFGR2_LOCKUP_LOCK_Pos) /*!< 0x00000001 */
12325 #define SYSCFG_CFGR2_LOCKUP_LOCK             SYSCFG_CFGR2_LOCKUP_LOCK_Msk      /*!<Core Lockup lock */
12326 #define SYSCFG_CFGR2_PVD_LOCK_Pos            (2U)
12327 #define SYSCFG_CFGR2_PVD_LOCK_Msk            (0x1UL << SYSCFG_CFGR2_PVD_LOCK_Pos) /*!< 0x00000004 */
12328 #define SYSCFG_CFGR2_PVD_LOCK                SYSCFG_CFGR2_PVD_LOCK_Msk         /*!<PVD Lock         */
12329 /******************  Bit definition for SYSCFG_MCHDLYCR register  *****************/
12330 #define SYSCFG_MCHDLYCR_BSCKSEL_Pos          (0U)
12331 #define SYSCFG_MCHDLYCR_BSCKSEL_Msk          (0x1UL << SYSCFG_MCHDLYCR_BSCKSEL_Pos) /*!< 0x00000001 */
12332 #define SYSCFG_MCHDLYCR_BSCKSEL              SYSCFG_MCHDLYCR_BSCKSEL_Msk       /*!<Bitstream clock source selection                     */
12333 #define SYSCFG_MCHDLYCR_MCHDLY1EN_Pos        (1U)
12334 #define SYSCFG_MCHDLYCR_MCHDLY1EN_Msk        (0x1UL << SYSCFG_MCHDLYCR_MCHDLY1EN_Pos) /*!< 0x00000002 */
12335 #define SYSCFG_MCHDLYCR_MCHDLY1EN            SYSCFG_MCHDLYCR_MCHDLY1EN_Msk     /*!<MCHDLY clock enable for DFSDM1                       */
12336 #define SYSCFG_MCHDLYCR_DFSDM1D0SEL_Pos      (2U)
12337 #define SYSCFG_MCHDLYCR_DFSDM1D0SEL_Msk      (0x1UL << SYSCFG_MCHDLYCR_DFSDM1D0SEL_Pos) /*!< 0x00000004 */
12338 #define SYSCFG_MCHDLYCR_DFSDM1D0SEL          SYSCFG_MCHDLYCR_DFSDM1D0SEL_Msk   /*!<Source selection for DatIn0 for DFSDM1               */
12339 #define SYSCFG_MCHDLYCR_DFSDM1D2SEL_Pos      (3U)
12340 #define SYSCFG_MCHDLYCR_DFSDM1D2SEL_Msk      (0x1UL << SYSCFG_MCHDLYCR_DFSDM1D2SEL_Pos) /*!< 0x00000008 */
12341 #define SYSCFG_MCHDLYCR_DFSDM1D2SEL          SYSCFG_MCHDLYCR_DFSDM1D2SEL_Msk   /*!<Source selection for DatIn2 for DFSDM1               */
12342 #define SYSCFG_MCHDLYCR_DFSDM1CK02SEL_Pos    (4U)
12343 #define SYSCFG_MCHDLYCR_DFSDM1CK02SEL_Msk    (0x1UL << SYSCFG_MCHDLYCR_DFSDM1CK02SEL_Pos) /*!< 0x00000010 */
12344 #define SYSCFG_MCHDLYCR_DFSDM1CK02SEL        SYSCFG_MCHDLYCR_DFSDM1CK02SEL_Msk /*!<Distribution of the bitstreamclock gated by TIM4 OC2 */
12345 #define SYSCFG_MCHDLYCR_DFSDM1CK13SEL_Pos    (5U)
12346 #define SYSCFG_MCHDLYCR_DFSDM1CK13SEL_Msk    (0x1UL << SYSCFG_MCHDLYCR_DFSDM1CK13SEL_Pos) /*!< 0x00000020 */
12347 #define SYSCFG_MCHDLYCR_DFSDM1CK13SEL        SYSCFG_MCHDLYCR_DFSDM1CK13SEL_Msk /*!<Distribution of the bitstreamclock gated by TIM4 OC1 */
12348 #define SYSCFG_MCHDLYCR_DFSDM1CFG_Pos        (6U)
12349 #define SYSCFG_MCHDLYCR_DFSDM1CFG_Msk        (0x1UL << SYSCFG_MCHDLYCR_DFSDM1CFG_Pos) /*!< 0x00000040 */
12350 #define SYSCFG_MCHDLYCR_DFSDM1CFG            SYSCFG_MCHDLYCR_DFSDM1CFG_Msk     /*!<Source selection for DFSDM1                          */
12351 #define SYSCFG_MCHDLYCR_DFSDM1CKOSEL_Pos     (7U)
12352 #define SYSCFG_MCHDLYCR_DFSDM1CKOSEL_Msk     (0x1UL << SYSCFG_MCHDLYCR_DFSDM1CKOSEL_Pos) /*!< 0x00000080 */
12353 #define SYSCFG_MCHDLYCR_DFSDM1CKOSEL         SYSCFG_MCHDLYCR_DFSDM1CKOSEL_Msk  /*!<Source selection for 1_CKOUT                         */
12354 #define SYSCFG_MCHDLYCR_MCHDLY2EN_Pos        (8U)
12355 #define SYSCFG_MCHDLYCR_MCHDLY2EN_Msk        (0x1UL << SYSCFG_MCHDLYCR_MCHDLY2EN_Pos) /*!< 0x00000100 */
12356 #define SYSCFG_MCHDLYCR_MCHDLY2EN            SYSCFG_MCHDLYCR_MCHDLY2EN_Msk     /*!<MCHDLY clock enable for DFSDM2                       */
12357 #define SYSCFG_MCHDLYCR_DFSDM2D0SEL_Pos      (9U)
12358 #define SYSCFG_MCHDLYCR_DFSDM2D0SEL_Msk      (0x1UL << SYSCFG_MCHDLYCR_DFSDM2D0SEL_Pos) /*!< 0x00000200 */
12359 #define SYSCFG_MCHDLYCR_DFSDM2D0SEL          SYSCFG_MCHDLYCR_DFSDM2D0SEL_Msk   /*!<Source selection for DatIn0 for DFSDM2               */
12360 #define SYSCFG_MCHDLYCR_DFSDM2D2SEL_Pos      (10U)
12361 #define SYSCFG_MCHDLYCR_DFSDM2D2SEL_Msk      (0x1UL << SYSCFG_MCHDLYCR_DFSDM2D2SEL_Pos) /*!< 0x00000400 */
12362 #define SYSCFG_MCHDLYCR_DFSDM2D2SEL          SYSCFG_MCHDLYCR_DFSDM2D2SEL_Msk   /*!<Source selection for DatIn2 for DFSDM2               */
12363 #define SYSCFG_MCHDLYCR_DFSDM2D4SEL_Pos      (11U)
12364 #define SYSCFG_MCHDLYCR_DFSDM2D4SEL_Msk      (0x1UL << SYSCFG_MCHDLYCR_DFSDM2D4SEL_Pos) /*!< 0x00000800 */
12365 #define SYSCFG_MCHDLYCR_DFSDM2D4SEL          SYSCFG_MCHDLYCR_DFSDM2D4SEL_Msk   /*!<Source selection for DatIn4 for DFSDM2               */
12366 #define SYSCFG_MCHDLYCR_DFSDM2D6SEL_Pos      (12U)
12367 #define SYSCFG_MCHDLYCR_DFSDM2D6SEL_Msk      (0x1UL << SYSCFG_MCHDLYCR_DFSDM2D6SEL_Pos) /*!< 0x00001000 */
12368 #define SYSCFG_MCHDLYCR_DFSDM2D6SEL          SYSCFG_MCHDLYCR_DFSDM2D6SEL_Msk   /*!<Source selection for DatIn6 for DFSDM2               */
12369 #define SYSCFG_MCHDLYCR_DFSDM2CK04SEL_Pos    (13U)
12370 #define SYSCFG_MCHDLYCR_DFSDM2CK04SEL_Msk    (0x1UL << SYSCFG_MCHDLYCR_DFSDM2CK04SEL_Pos) /*!< 0x00002000 */
12371 #define SYSCFG_MCHDLYCR_DFSDM2CK04SEL        SYSCFG_MCHDLYCR_DFSDM2CK04SEL_Msk /*!<Distribution of the bitstreamclock gated by TIM3 OC4 */
12372 #define SYSCFG_MCHDLYCR_DFSDM2CK15SEL_Pos    (14U)
12373 #define SYSCFG_MCHDLYCR_DFSDM2CK15SEL_Msk    (0x1UL << SYSCFG_MCHDLYCR_DFSDM2CK15SEL_Pos) /*!< 0x00004000 */
12374 #define SYSCFG_MCHDLYCR_DFSDM2CK15SEL        SYSCFG_MCHDLYCR_DFSDM2CK15SEL_Msk /*!<Distribution of the bitstreamclock gated by TIM3 OC3 */
12375 #define SYSCFG_MCHDLYCR_DFSDM2CK26SEL_Pos    (15U)
12376 #define SYSCFG_MCHDLYCR_DFSDM2CK26SEL_Msk    (0x1UL << SYSCFG_MCHDLYCR_DFSDM2CK26SEL_Pos) /*!< 0x00008000 */
12377 #define SYSCFG_MCHDLYCR_DFSDM2CK26SEL        SYSCFG_MCHDLYCR_DFSDM2CK26SEL_Msk /*!Distribution of the bitstreamclock gated by TIM3 OC2  */
12378 #define SYSCFG_MCHDLYCR_DFSDM2CK37SEL_Pos    (16U)
12379 #define SYSCFG_MCHDLYCR_DFSDM2CK37SEL_Msk    (0x1UL << SYSCFG_MCHDLYCR_DFSDM2CK37SEL_Pos) /*!< 0x00010000 */
12380 #define SYSCFG_MCHDLYCR_DFSDM2CK37SEL        SYSCFG_MCHDLYCR_DFSDM2CK37SEL_Msk /*!<Distribution of the bitstreamclock gated by TIM3 OC1 */
12381 #define SYSCFG_MCHDLYCR_DFSDM2CFG_Pos        (17U)
12382 #define SYSCFG_MCHDLYCR_DFSDM2CFG_Msk        (0x1UL << SYSCFG_MCHDLYCR_DFSDM2CFG_Pos) /*!< 0x00020000 */
12383 #define SYSCFG_MCHDLYCR_DFSDM2CFG            SYSCFG_MCHDLYCR_DFSDM2CFG_Msk     /*!<Source selection for DFSDM2                          */
12384 #define SYSCFG_MCHDLYCR_DFSDM2CKOSEL_Pos     (18U)
12385 #define SYSCFG_MCHDLYCR_DFSDM2CKOSEL_Msk     (0x1UL << SYSCFG_MCHDLYCR_DFSDM2CKOSEL_Pos) /*!< 0x00040000 */
12386 #define SYSCFG_MCHDLYCR_DFSDM2CKOSEL         SYSCFG_MCHDLYCR_DFSDM2CKOSEL_Msk  /*!<Source selection for 2_CKOUT                         */
12387 
12388 /******************************************************************************/
12389 /*                                                                            */
12390 /*                                    TIM                                     */
12391 /*                                                                            */
12392 /******************************************************************************/
12393 /*******************  Bit definition for TIM_CR1 register  ********************/
12394 #define TIM_CR1_CEN_Pos           (0U)
12395 #define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                    /*!< 0x00000001 */
12396 #define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable        */
12397 #define TIM_CR1_UDIS_Pos          (1U)
12398 #define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                   /*!< 0x00000002 */
12399 #define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable        */
12400 #define TIM_CR1_URS_Pos           (2U)
12401 #define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                    /*!< 0x00000004 */
12402 #define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
12403 #define TIM_CR1_OPM_Pos           (3U)
12404 #define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                    /*!< 0x00000008 */
12405 #define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode        */
12406 #define TIM_CR1_DIR_Pos           (4U)
12407 #define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                    /*!< 0x00000010 */
12408 #define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction             */
12409 
12410 #define TIM_CR1_CMS_Pos           (5U)
12411 #define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000060 */
12412 #define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
12413 #define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                    /*!< 0x0020 */
12414 #define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                    /*!< 0x0040 */
12415 
12416 #define TIM_CR1_ARPE_Pos          (7U)
12417 #define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                   /*!< 0x00000080 */
12418 #define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable     */
12419 
12420 #define TIM_CR1_CKD_Pos           (8U)
12421 #define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000300 */
12422 #define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
12423 #define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                    /*!< 0x0100 */
12424 #define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                    /*!< 0x0200 */
12425 
12426 /*******************  Bit definition for TIM_CR2 register  ********************/
12427 #define TIM_CR2_CCPC_Pos          (0U)
12428 #define TIM_CR2_CCPC_Msk          (0x1UL << TIM_CR2_CCPC_Pos)                   /*!< 0x00000001 */
12429 #define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control        */
12430 #define TIM_CR2_CCUS_Pos          (2U)
12431 #define TIM_CR2_CCUS_Msk          (0x1UL << TIM_CR2_CCUS_Pos)                   /*!< 0x00000004 */
12432 #define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */
12433 #define TIM_CR2_CCDS_Pos          (3U)
12434 #define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                   /*!< 0x00000008 */
12435 #define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection            */
12436 
12437 #define TIM_CR2_MMS_Pos           (4U)
12438 #define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000070 */
12439 #define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */
12440 #define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                    /*!< 0x0010 */
12441 #define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                    /*!< 0x0020 */
12442 #define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                    /*!< 0x0040 */
12443 
12444 #define TIM_CR2_TI1S_Pos          (7U)
12445 #define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                   /*!< 0x00000080 */
12446 #define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
12447 #define TIM_CR2_OIS1_Pos          (8U)
12448 #define TIM_CR2_OIS1_Msk          (0x1UL << TIM_CR2_OIS1_Pos)                   /*!< 0x00000100 */
12449 #define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output)  */
12450 #define TIM_CR2_OIS1N_Pos         (9U)
12451 #define TIM_CR2_OIS1N_Msk         (0x1UL << TIM_CR2_OIS1N_Pos)                  /*!< 0x00000200 */
12452 #define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */
12453 #define TIM_CR2_OIS2_Pos          (10U)
12454 #define TIM_CR2_OIS2_Msk          (0x1UL << TIM_CR2_OIS2_Pos)                   /*!< 0x00000400 */
12455 #define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output)  */
12456 #define TIM_CR2_OIS2N_Pos         (11U)
12457 #define TIM_CR2_OIS2N_Msk         (0x1UL << TIM_CR2_OIS2N_Pos)                  /*!< 0x00000800 */
12458 #define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */
12459 #define TIM_CR2_OIS3_Pos          (12U)
12460 #define TIM_CR2_OIS3_Msk          (0x1UL << TIM_CR2_OIS3_Pos)                   /*!< 0x00001000 */
12461 #define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output)  */
12462 #define TIM_CR2_OIS3N_Pos         (13U)
12463 #define TIM_CR2_OIS3N_Msk         (0x1UL << TIM_CR2_OIS3N_Pos)                  /*!< 0x00002000 */
12464 #define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */
12465 #define TIM_CR2_OIS4_Pos          (14U)
12466 #define TIM_CR2_OIS4_Msk          (0x1UL << TIM_CR2_OIS4_Pos)                   /*!< 0x00004000 */
12467 #define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output)  */
12468 
12469 /*******************  Bit definition for TIM_SMCR register  *******************/
12470 #define TIM_SMCR_SMS_Pos          (0U)
12471 #define TIM_SMCR_SMS_Msk          (0x7UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000007 */
12472 #define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection)    */
12473 #define TIM_SMCR_SMS_0            (0x1UL << TIM_SMCR_SMS_Pos)                   /*!< 0x0001 */
12474 #define TIM_SMCR_SMS_1            (0x2UL << TIM_SMCR_SMS_Pos)                   /*!< 0x0002 */
12475 #define TIM_SMCR_SMS_2            (0x4UL << TIM_SMCR_SMS_Pos)                   /*!< 0x0004 */
12476 
12477 #define TIM_SMCR_TS_Pos           (4U)
12478 #define TIM_SMCR_TS_Msk           (0x7UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000070 */
12479 #define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection)        */
12480 #define TIM_SMCR_TS_0             (0x1UL << TIM_SMCR_TS_Pos)                    /*!< 0x0010 */
12481 #define TIM_SMCR_TS_1             (0x2UL << TIM_SMCR_TS_Pos)                    /*!< 0x0020 */
12482 #define TIM_SMCR_TS_2             (0x4UL << TIM_SMCR_TS_Pos)                    /*!< 0x0040 */
12483 
12484 #define TIM_SMCR_MSM_Pos          (7U)
12485 #define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                   /*!< 0x00000080 */
12486 #define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode                       */
12487 
12488 #define TIM_SMCR_ETF_Pos          (8U)
12489 #define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000F00 */
12490 #define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
12491 #define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                   /*!< 0x0100 */
12492 #define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                   /*!< 0x0200 */
12493 #define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                   /*!< 0x0400 */
12494 #define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                   /*!< 0x0800 */
12495 
12496 #define TIM_SMCR_ETPS_Pos         (12U)
12497 #define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00003000 */
12498 #define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
12499 #define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x1000 */
12500 #define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x2000 */
12501 
12502 #define TIM_SMCR_ECE_Pos          (14U)
12503 #define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                   /*!< 0x00004000 */
12504 #define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable     */
12505 #define TIM_SMCR_ETP_Pos          (15U)
12506 #define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                   /*!< 0x00008000 */
12507 #define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
12508 
12509 /*******************  Bit definition for TIM_DIER register  *******************/
12510 #define TIM_DIER_UIE_Pos          (0U)
12511 #define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                   /*!< 0x00000001 */
12512 #define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
12513 #define TIM_DIER_CC1IE_Pos        (1U)
12514 #define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                 /*!< 0x00000002 */
12515 #define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable   */
12516 #define TIM_DIER_CC2IE_Pos        (2U)
12517 #define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                 /*!< 0x00000004 */
12518 #define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable   */
12519 #define TIM_DIER_CC3IE_Pos        (3U)
12520 #define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                 /*!< 0x00000008 */
12521 #define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable   */
12522 #define TIM_DIER_CC4IE_Pos        (4U)
12523 #define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                 /*!< 0x00000010 */
12524 #define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable   */
12525 #define TIM_DIER_COMIE_Pos        (5U)
12526 #define TIM_DIER_COMIE_Msk        (0x1UL << TIM_DIER_COMIE_Pos)                 /*!< 0x00000020 */
12527 #define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable                 */
12528 #define TIM_DIER_TIE_Pos          (6U)
12529 #define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                   /*!< 0x00000040 */
12530 #define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable             */
12531 #define TIM_DIER_BIE_Pos          (7U)
12532 #define TIM_DIER_BIE_Msk          (0x1UL << TIM_DIER_BIE_Pos)                   /*!< 0x00000080 */
12533 #define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable               */
12534 #define TIM_DIER_UDE_Pos          (8U)
12535 #define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                   /*!< 0x00000100 */
12536 #define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable            */
12537 #define TIM_DIER_CC1DE_Pos        (9U)
12538 #define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                 /*!< 0x00000200 */
12539 #define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
12540 #define TIM_DIER_CC2DE_Pos        (10U)
12541 #define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                 /*!< 0x00000400 */
12542 #define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
12543 #define TIM_DIER_CC3DE_Pos        (11U)
12544 #define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                 /*!< 0x00000800 */
12545 #define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
12546 #define TIM_DIER_CC4DE_Pos        (12U)
12547 #define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                 /*!< 0x00001000 */
12548 #define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
12549 #define TIM_DIER_COMDE_Pos        (13U)
12550 #define TIM_DIER_COMDE_Msk        (0x1UL << TIM_DIER_COMDE_Pos)                 /*!< 0x00002000 */
12551 #define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable               */
12552 #define TIM_DIER_TDE_Pos          (14U)
12553 #define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                   /*!< 0x00004000 */
12554 #define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable           */
12555 
12556 /********************  Bit definition for TIM_SR register  ********************/
12557 #define TIM_SR_UIF_Pos            (0U)
12558 #define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                     /*!< 0x00000001 */
12559 #define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag              */
12560 #define TIM_SR_CC1IF_Pos          (1U)
12561 #define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                   /*!< 0x00000002 */
12562 #define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag   */
12563 #define TIM_SR_CC2IF_Pos          (2U)
12564 #define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                   /*!< 0x00000004 */
12565 #define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag   */
12566 #define TIM_SR_CC3IF_Pos          (3U)
12567 #define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                   /*!< 0x00000008 */
12568 #define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag   */
12569 #define TIM_SR_CC4IF_Pos          (4U)
12570 #define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                   /*!< 0x00000010 */
12571 #define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag   */
12572 #define TIM_SR_COMIF_Pos          (5U)
12573 #define TIM_SR_COMIF_Msk          (0x1UL << TIM_SR_COMIF_Pos)                   /*!< 0x00000020 */
12574 #define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag                 */
12575 #define TIM_SR_TIF_Pos            (6U)
12576 #define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                     /*!< 0x00000040 */
12577 #define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag             */
12578 #define TIM_SR_BIF_Pos            (7U)
12579 #define TIM_SR_BIF_Msk            (0x1UL << TIM_SR_BIF_Pos)                     /*!< 0x00000080 */
12580 #define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag               */
12581 #define TIM_SR_CC1OF_Pos          (9U)
12582 #define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                   /*!< 0x00000200 */
12583 #define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
12584 #define TIM_SR_CC2OF_Pos          (10U)
12585 #define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                   /*!< 0x00000400 */
12586 #define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
12587 #define TIM_SR_CC3OF_Pos          (11U)
12588 #define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                   /*!< 0x00000800 */
12589 #define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
12590 #define TIM_SR_CC4OF_Pos          (12U)
12591 #define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                   /*!< 0x00001000 */
12592 #define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
12593 
12594 /*******************  Bit definition for TIM_EGR register  ********************/
12595 #define TIM_EGR_UG_Pos            (0U)
12596 #define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                     /*!< 0x00000001 */
12597 #define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation                         */
12598 #define TIM_EGR_CC1G_Pos          (1U)
12599 #define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                   /*!< 0x00000002 */
12600 #define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation              */
12601 #define TIM_EGR_CC2G_Pos          (2U)
12602 #define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                   /*!< 0x00000004 */
12603 #define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation              */
12604 #define TIM_EGR_CC3G_Pos          (3U)
12605 #define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                   /*!< 0x00000008 */
12606 #define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation              */
12607 #define TIM_EGR_CC4G_Pos          (4U)
12608 #define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                   /*!< 0x00000010 */
12609 #define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation              */
12610 #define TIM_EGR_COMG_Pos          (5U)
12611 #define TIM_EGR_COMG_Msk          (0x1UL << TIM_EGR_COMG_Pos)                   /*!< 0x00000020 */
12612 #define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */
12613 #define TIM_EGR_TG_Pos            (6U)
12614 #define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                     /*!< 0x00000040 */
12615 #define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation                        */
12616 #define TIM_EGR_BG_Pos            (7U)
12617 #define TIM_EGR_BG_Msk            (0x1UL << TIM_EGR_BG_Pos)                     /*!< 0x00000080 */
12618 #define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation                          */
12619 
12620 /******************  Bit definition for TIM_CCMR1 register  *******************/
12621 #define TIM_CCMR1_CC1S_Pos        (0U)
12622 #define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000003 */
12623 #define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
12624 #define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x0001 */
12625 #define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x0002 */
12626 
12627 #define TIM_CCMR1_OC1FE_Pos       (2U)
12628 #define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)                /*!< 0x00000004 */
12629 #define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable                 */
12630 #define TIM_CCMR1_OC1PE_Pos       (3U)
12631 #define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)                /*!< 0x00000008 */
12632 #define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable              */
12633 
12634 #define TIM_CCMR1_OC1M_Pos        (4U)
12635 #define TIM_CCMR1_OC1M_Msk        (0x7UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000070 */
12636 #define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
12637 #define TIM_CCMR1_OC1M_0          (0x1UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x0010 */
12638 #define TIM_CCMR1_OC1M_1          (0x2UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x0020 */
12639 #define TIM_CCMR1_OC1M_2          (0x4UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x0040 */
12640 
12641 #define TIM_CCMR1_OC1CE_Pos       (7U)
12642 #define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)                /*!< 0x00000080 */
12643 #define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable                 */
12644 
12645 #define TIM_CCMR1_CC2S_Pos        (8U)
12646 #define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000300 */
12647 #define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
12648 #define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x0100 */
12649 #define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x0200 */
12650 
12651 #define TIM_CCMR1_OC2FE_Pos       (10U)
12652 #define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)                /*!< 0x00000400 */
12653 #define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable                 */
12654 #define TIM_CCMR1_OC2PE_Pos       (11U)
12655 #define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)                /*!< 0x00000800 */
12656 #define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable              */
12657 
12658 #define TIM_CCMR1_OC2M_Pos        (12U)
12659 #define TIM_CCMR1_OC2M_Msk        (0x7UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00007000 */
12660 #define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */
12661 #define TIM_CCMR1_OC2M_0          (0x1UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x1000 */
12662 #define TIM_CCMR1_OC2M_1          (0x2UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x2000 */
12663 #define TIM_CCMR1_OC2M_2          (0x4UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x4000 */
12664 
12665 #define TIM_CCMR1_OC2CE_Pos       (15U)
12666 #define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)                /*!< 0x00008000 */
12667 #define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
12668 
12669 /*----------------------------------------------------------------------------*/
12670 
12671 #define TIM_CCMR1_IC1PSC_Pos      (2U)
12672 #define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0000000C */
12673 #define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
12674 #define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0004 */
12675 #define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0008 */
12676 
12677 #define TIM_CCMR1_IC1F_Pos        (4U)
12678 #define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x000000F0 */
12679 #define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
12680 #define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0010 */
12681 #define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0020 */
12682 #define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0040 */
12683 #define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0080 */
12684 
12685 #define TIM_CCMR1_IC2PSC_Pos      (10U)
12686 #define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000C00 */
12687 #define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
12688 #define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x0400 */
12689 #define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x0800 */
12690 
12691 #define TIM_CCMR1_IC2F_Pos        (12U)
12692 #define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x0000F000 */
12693 #define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
12694 #define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x1000 */
12695 #define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x2000 */
12696 #define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x4000 */
12697 #define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x8000 */
12698 
12699 /******************  Bit definition for TIM_CCMR2 register  *******************/
12700 #define TIM_CCMR2_CC3S_Pos        (0U)
12701 #define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000003 */
12702 #define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
12703 #define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x0001 */
12704 #define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x0002 */
12705 
12706 #define TIM_CCMR2_OC3FE_Pos       (2U)
12707 #define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)                /*!< 0x00000004 */
12708 #define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable           */
12709 #define TIM_CCMR2_OC3PE_Pos       (3U)
12710 #define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)                /*!< 0x00000008 */
12711 #define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable        */
12712 
12713 #define TIM_CCMR2_OC3M_Pos        (4U)
12714 #define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000070 */
12715 #define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
12716 #define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x0010 */
12717 #define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x0020 */
12718 #define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x0040 */
12719 
12720 #define TIM_CCMR2_OC3CE_Pos       (7U)
12721 #define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)                /*!< 0x00000080 */
12722 #define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
12723 
12724 #define TIM_CCMR2_CC4S_Pos        (8U)
12725 #define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000300 */
12726 #define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
12727 #define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x0100 */
12728 #define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x0200 */
12729 
12730 #define TIM_CCMR2_OC4FE_Pos       (10U)
12731 #define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)                /*!< 0x00000400 */
12732 #define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable    */
12733 #define TIM_CCMR2_OC4PE_Pos       (11U)
12734 #define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)                /*!< 0x00000800 */
12735 #define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
12736 
12737 #define TIM_CCMR2_OC4M_Pos        (12U)
12738 #define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00007000 */
12739 #define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
12740 #define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x1000 */
12741 #define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x2000 */
12742 #define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x4000 */
12743 
12744 #define TIM_CCMR2_OC4CE_Pos       (15U)
12745 #define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)                /*!< 0x00008000 */
12746 #define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
12747 
12748 /*----------------------------------------------------------------------------*/
12749 
12750 #define TIM_CCMR2_IC3PSC_Pos      (2U)
12751 #define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0000000C */
12752 #define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
12753 #define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0004 */
12754 #define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0008 */
12755 
12756 #define TIM_CCMR2_IC3F_Pos        (4U)
12757 #define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x000000F0 */
12758 #define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
12759 #define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0010 */
12760 #define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0020 */
12761 #define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0040 */
12762 #define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0080 */
12763 
12764 #define TIM_CCMR2_IC4PSC_Pos      (10U)
12765 #define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000C00 */
12766 #define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
12767 #define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x0400 */
12768 #define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x0800 */
12769 
12770 #define TIM_CCMR2_IC4F_Pos        (12U)
12771 #define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x0000F000 */
12772 #define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
12773 #define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x1000 */
12774 #define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x2000 */
12775 #define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x4000 */
12776 #define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x8000 */
12777 
12778 /*******************  Bit definition for TIM_CCER register  *******************/
12779 #define TIM_CCER_CC1E_Pos         (0U)
12780 #define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                  /*!< 0x00000001 */
12781 #define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable                 */
12782 #define TIM_CCER_CC1P_Pos         (1U)
12783 #define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                  /*!< 0x00000002 */
12784 #define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity               */
12785 #define TIM_CCER_CC1NE_Pos        (2U)
12786 #define TIM_CCER_CC1NE_Msk        (0x1UL << TIM_CCER_CC1NE_Pos)                 /*!< 0x00000004 */
12787 #define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable   */
12788 #define TIM_CCER_CC1NP_Pos        (3U)
12789 #define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                 /*!< 0x00000008 */
12790 #define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
12791 #define TIM_CCER_CC2E_Pos         (4U)
12792 #define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                  /*!< 0x00000010 */
12793 #define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable                 */
12794 #define TIM_CCER_CC2P_Pos         (5U)
12795 #define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                  /*!< 0x00000020 */
12796 #define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity               */
12797 #define TIM_CCER_CC2NE_Pos        (6U)
12798 #define TIM_CCER_CC2NE_Msk        (0x1UL << TIM_CCER_CC2NE_Pos)                 /*!< 0x00000040 */
12799 #define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable   */
12800 #define TIM_CCER_CC2NP_Pos        (7U)
12801 #define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                 /*!< 0x00000080 */
12802 #define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
12803 #define TIM_CCER_CC3E_Pos         (8U)
12804 #define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                  /*!< 0x00000100 */
12805 #define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable                 */
12806 #define TIM_CCER_CC3P_Pos         (9U)
12807 #define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                  /*!< 0x00000200 */
12808 #define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity               */
12809 #define TIM_CCER_CC3NE_Pos        (10U)
12810 #define TIM_CCER_CC3NE_Msk        (0x1UL << TIM_CCER_CC3NE_Pos)                 /*!< 0x00000400 */
12811 #define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable   */
12812 #define TIM_CCER_CC3NP_Pos        (11U)
12813 #define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                 /*!< 0x00000800 */
12814 #define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
12815 #define TIM_CCER_CC4E_Pos         (12U)
12816 #define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                  /*!< 0x00001000 */
12817 #define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable                 */
12818 #define TIM_CCER_CC4P_Pos         (13U)
12819 #define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                  /*!< 0x00002000 */
12820 #define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity               */
12821 #define TIM_CCER_CC4NP_Pos        (15U)
12822 #define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                 /*!< 0x00008000 */
12823 #define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
12824 
12825 /*******************  Bit definition for TIM_CNT register  ********************/
12826 #define TIM_CNT_CNT_Pos           (0U)
12827 #define TIM_CNT_CNT_Msk           (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)                 /*!< 0xFFFFFFFF */
12828 #define TIM_CNT_CNT               TIM_CNT_CNT_Msk                                  /*!<Counter Value            */
12829 
12830 /*******************  Bit definition for TIM_PSC register  ********************/
12831 #define TIM_PSC_PSC_Pos           (0U)
12832 #define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                 /*!< 0x0000FFFF */
12833 #define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value          */
12834 
12835 /*******************  Bit definition for TIM_ARR register  ********************/
12836 #define TIM_ARR_ARR_Pos           (0U)
12837 #define TIM_ARR_ARR_Msk           (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)             /*!< 0xFFFFFFFF */
12838 #define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */
12839 
12840 /*******************  Bit definition for TIM_RCR register  ********************/
12841 #define TIM_RCR_REP_Pos           (0U)
12842 #define TIM_RCR_REP_Msk           (0xFFUL << TIM_RCR_REP_Pos)                   /*!< 0x000000FF */
12843 #define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */
12844 
12845 /*******************  Bit definition for TIM_CCR1 register  *******************/
12846 #define TIM_CCR1_CCR1_Pos         (0U)
12847 #define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)               /*!< 0x0000FFFF */
12848 #define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value  */
12849 
12850 /*******************  Bit definition for TIM_CCR2 register  *******************/
12851 #define TIM_CCR2_CCR2_Pos         (0U)
12852 #define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)               /*!< 0x0000FFFF */
12853 #define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value  */
12854 
12855 /*******************  Bit definition for TIM_CCR3 register  *******************/
12856 #define TIM_CCR3_CCR3_Pos         (0U)
12857 #define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)               /*!< 0x0000FFFF */
12858 #define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value  */
12859 
12860 /*******************  Bit definition for TIM_CCR4 register  *******************/
12861 #define TIM_CCR4_CCR4_Pos         (0U)
12862 #define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)               /*!< 0x0000FFFF */
12863 #define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value  */
12864 
12865 /*******************  Bit definition for TIM_BDTR register  *******************/
12866 #define TIM_BDTR_DTG_Pos          (0U)
12867 #define TIM_BDTR_DTG_Msk          (0xFFUL << TIM_BDTR_DTG_Pos)                  /*!< 0x000000FF */
12868 #define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
12869 #define TIM_BDTR_DTG_0            (0x01UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0001 */
12870 #define TIM_BDTR_DTG_1            (0x02UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0002 */
12871 #define TIM_BDTR_DTG_2            (0x04UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0004 */
12872 #define TIM_BDTR_DTG_3            (0x08UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0008 */
12873 #define TIM_BDTR_DTG_4            (0x10UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0010 */
12874 #define TIM_BDTR_DTG_5            (0x20UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0020 */
12875 #define TIM_BDTR_DTG_6            (0x40UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0040 */
12876 #define TIM_BDTR_DTG_7            (0x80UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0080 */
12877 
12878 #define TIM_BDTR_LOCK_Pos         (8U)
12879 #define TIM_BDTR_LOCK_Msk         (0x3UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000300 */
12880 #define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */
12881 #define TIM_BDTR_LOCK_0           (0x1UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x0100 */
12882 #define TIM_BDTR_LOCK_1           (0x2UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x0200 */
12883 
12884 #define TIM_BDTR_OSSI_Pos         (10U)
12885 #define TIM_BDTR_OSSI_Msk         (0x1UL << TIM_BDTR_OSSI_Pos)                  /*!< 0x00000400 */
12886 #define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */
12887 #define TIM_BDTR_OSSR_Pos         (11U)
12888 #define TIM_BDTR_OSSR_Msk         (0x1UL << TIM_BDTR_OSSR_Pos)                  /*!< 0x00000800 */
12889 #define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode  */
12890 #define TIM_BDTR_BKE_Pos          (12U)
12891 #define TIM_BDTR_BKE_Msk          (0x1UL << TIM_BDTR_BKE_Pos)                   /*!< 0x00001000 */
12892 #define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable                      */
12893 #define TIM_BDTR_BKP_Pos          (13U)
12894 #define TIM_BDTR_BKP_Msk          (0x1UL << TIM_BDTR_BKP_Pos)                   /*!< 0x00002000 */
12895 #define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity                    */
12896 #define TIM_BDTR_AOE_Pos          (14U)
12897 #define TIM_BDTR_AOE_Msk          (0x1UL << TIM_BDTR_AOE_Pos)                   /*!< 0x00004000 */
12898 #define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable           */
12899 #define TIM_BDTR_MOE_Pos          (15U)
12900 #define TIM_BDTR_MOE_Msk          (0x1UL << TIM_BDTR_MOE_Pos)                   /*!< 0x00008000 */
12901 #define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable                */
12902 
12903 /*******************  Bit definition for TIM_DCR register  ********************/
12904 #define TIM_DCR_DBA_Pos           (0U)
12905 #define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                   /*!< 0x0000001F */
12906 #define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
12907 #define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                   /*!< 0x0001 */
12908 #define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                   /*!< 0x0002 */
12909 #define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                   /*!< 0x0004 */
12910 #define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                   /*!< 0x0008 */
12911 #define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                   /*!< 0x0010 */
12912 
12913 #define TIM_DCR_DBL_Pos           (8U)
12914 #define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                   /*!< 0x00001F00 */
12915 #define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
12916 #define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                   /*!< 0x0100 */
12917 #define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                   /*!< 0x0200 */
12918 #define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                   /*!< 0x0400 */
12919 #define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                   /*!< 0x0800 */
12920 #define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                   /*!< 0x1000 */
12921 
12922 /*******************  Bit definition for TIM_DMAR register  *******************/
12923 #define TIM_DMAR_DMAB_Pos         (0U)
12924 #define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)               /*!< 0x0000FFFF */
12925 #define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses                    */
12926 
12927 /*******************  Bit definition for TIM_OR register  *********************/
12928 #define TIM_OR_TI1_RMP_Pos        (0U)
12929 #define TIM_OR_TI1_RMP_Msk        (0x3UL << TIM_OR_TI1_RMP_Pos)                 /*!< 0x00000003 */
12930 #define TIM_OR_TI1_RMP            TIM_OR_TI1_RMP_Msk                           /*!< TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap) */
12931 #define TIM_OR_TI1_RMP_0          (0x1UL << TIM_OR_TI1_RMP_Pos)                 /*!< 0x00000001 */
12932 #define TIM_OR_TI1_RMP_1          (0x2UL << TIM_OR_TI1_RMP_Pos)                 /*!< 0x00000002 */
12933 
12934 #define TIM_OR_TI4_RMP_Pos        (6U)
12935 #define TIM_OR_TI4_RMP_Msk        (0x3UL << TIM_OR_TI4_RMP_Pos)                 /*!< 0x000000C0 */
12936 #define TIM_OR_TI4_RMP            TIM_OR_TI4_RMP_Msk                           /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */
12937 #define TIM_OR_TI4_RMP_0          (0x1UL << TIM_OR_TI4_RMP_Pos)                 /*!< 0x0040 */
12938 #define TIM_OR_TI4_RMP_1          (0x2UL << TIM_OR_TI4_RMP_Pos)                 /*!< 0x0080 */
12939 #define TIM_OR_ITR1_RMP_Pos       (10U)
12940 #define TIM_OR_ITR1_RMP_Msk       (0x3UL << TIM_OR_ITR1_RMP_Pos)                /*!< 0x00000C00 */
12941 #define TIM_OR_ITR1_RMP           TIM_OR_ITR1_RMP_Msk                          /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
12942 #define TIM_OR_ITR1_RMP_0         (0x1UL << TIM_OR_ITR1_RMP_Pos)                /*!< 0x0400 */
12943 #define TIM_OR_ITR1_RMP_1         (0x2UL << TIM_OR_ITR1_RMP_Pos)                /*!< 0x0800 */
12944 
12945 /******************************************************************************/
12946 /*                                                                            */
12947 /*                         Low Power Timer (LPTIM)                            */
12948 /*                                                                            */
12949 /******************************************************************************/
12950 /******************  Bit definition for LPTIM_ISR register  *******************/
12951 #define LPTIM_ISR_CMPM_Pos            (0U)
12952 #define LPTIM_ISR_CMPM_Msk            (0x1UL << LPTIM_ISR_CMPM_Pos)             /*!< 0x00000001 */
12953 #define LPTIM_ISR_CMPM                LPTIM_ISR_CMPM_Msk                       /*!< Compare match                       */
12954 #define LPTIM_ISR_ARRM_Pos            (1U)
12955 #define LPTIM_ISR_ARRM_Msk            (0x1UL << LPTIM_ISR_ARRM_Pos)             /*!< 0x00000002 */
12956 #define LPTIM_ISR_ARRM                LPTIM_ISR_ARRM_Msk                       /*!< Autoreload match                    */
12957 #define LPTIM_ISR_EXTTRIG_Pos         (2U)
12958 #define LPTIM_ISR_EXTTRIG_Msk         (0x1UL << LPTIM_ISR_EXTTRIG_Pos)          /*!< 0x00000004 */
12959 #define LPTIM_ISR_EXTTRIG             LPTIM_ISR_EXTTRIG_Msk                    /*!< External trigger edge event         */
12960 #define LPTIM_ISR_CMPOK_Pos           (3U)
12961 #define LPTIM_ISR_CMPOK_Msk           (0x1UL << LPTIM_ISR_CMPOK_Pos)            /*!< 0x00000008 */
12962 #define LPTIM_ISR_CMPOK               LPTIM_ISR_CMPOK_Msk                      /*!< Compare register update OK          */
12963 #define LPTIM_ISR_ARROK_Pos           (4U)
12964 #define LPTIM_ISR_ARROK_Msk           (0x1UL << LPTIM_ISR_ARROK_Pos)            /*!< 0x00000010 */
12965 #define LPTIM_ISR_ARROK               LPTIM_ISR_ARROK_Msk                      /*!< Autoreload register update OK       */
12966 #define LPTIM_ISR_UP_Pos              (5U)
12967 #define LPTIM_ISR_UP_Msk              (0x1UL << LPTIM_ISR_UP_Pos)               /*!< 0x00000020 */
12968 #define LPTIM_ISR_UP                  LPTIM_ISR_UP_Msk                         /*!< Counter direction change down to up */
12969 #define LPTIM_ISR_DOWN_Pos            (6U)
12970 #define LPTIM_ISR_DOWN_Msk            (0x1UL << LPTIM_ISR_DOWN_Pos)             /*!< 0x00000040 */
12971 #define LPTIM_ISR_DOWN                LPTIM_ISR_DOWN_Msk                       /*!< Counter direction change up to down */
12972 
12973 /******************  Bit definition for LPTIM_ICR register  *******************/
12974 #define LPTIM_ICR_CMPMCF_Pos          (0U)
12975 #define LPTIM_ICR_CMPMCF_Msk          (0x1UL << LPTIM_ICR_CMPMCF_Pos)           /*!< 0x00000001 */
12976 #define LPTIM_ICR_CMPMCF              LPTIM_ICR_CMPMCF_Msk                     /*!< Compare match Clear Flag                       */
12977 #define LPTIM_ICR_ARRMCF_Pos          (1U)
12978 #define LPTIM_ICR_ARRMCF_Msk          (0x1UL << LPTIM_ICR_ARRMCF_Pos)           /*!< 0x00000002 */
12979 #define LPTIM_ICR_ARRMCF              LPTIM_ICR_ARRMCF_Msk                     /*!< Autoreload match Clear Flag                    */
12980 #define LPTIM_ICR_EXTTRIGCF_Pos       (2U)
12981 #define LPTIM_ICR_EXTTRIGCF_Msk       (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)        /*!< 0x00000004 */
12982 #define LPTIM_ICR_EXTTRIGCF           LPTIM_ICR_EXTTRIGCF_Msk                  /*!< External trigger edge event Clear Flag         */
12983 #define LPTIM_ICR_CMPOKCF_Pos         (3U)
12984 #define LPTIM_ICR_CMPOKCF_Msk         (0x1UL << LPTIM_ICR_CMPOKCF_Pos)          /*!< 0x00000008 */
12985 #define LPTIM_ICR_CMPOKCF             LPTIM_ICR_CMPOKCF_Msk                    /*!< Compare register update OK Clear Flag          */
12986 #define LPTIM_ICR_ARROKCF_Pos         (4U)
12987 #define LPTIM_ICR_ARROKCF_Msk         (0x1UL << LPTIM_ICR_ARROKCF_Pos)          /*!< 0x00000010 */
12988 #define LPTIM_ICR_ARROKCF             LPTIM_ICR_ARROKCF_Msk                    /*!< Autoreload register update OK Clear Flag       */
12989 #define LPTIM_ICR_UPCF_Pos            (5U)
12990 #define LPTIM_ICR_UPCF_Msk            (0x1UL << LPTIM_ICR_UPCF_Pos)             /*!< 0x00000020 */
12991 #define LPTIM_ICR_UPCF                LPTIM_ICR_UPCF_Msk                       /*!< Counter direction change down to up Clear Flag */
12992 #define LPTIM_ICR_DOWNCF_Pos          (6U)
12993 #define LPTIM_ICR_DOWNCF_Msk          (0x1UL << LPTIM_ICR_DOWNCF_Pos)           /*!< 0x00000040 */
12994 #define LPTIM_ICR_DOWNCF              LPTIM_ICR_DOWNCF_Msk                     /*!< Counter direction change up to down Clear Flag */
12995 
12996 /******************  Bit definition for LPTIM_IER register ********************/
12997 #define LPTIM_IER_CMPMIE_Pos          (0U)
12998 #define LPTIM_IER_CMPMIE_Msk          (0x1UL << LPTIM_IER_CMPMIE_Pos)           /*!< 0x00000001 */
12999 #define LPTIM_IER_CMPMIE              LPTIM_IER_CMPMIE_Msk                     /*!< Compare match Interrupt Enable                       */
13000 #define LPTIM_IER_ARRMIE_Pos          (1U)
13001 #define LPTIM_IER_ARRMIE_Msk          (0x1UL << LPTIM_IER_ARRMIE_Pos)           /*!< 0x00000002 */
13002 #define LPTIM_IER_ARRMIE              LPTIM_IER_ARRMIE_Msk                     /*!< Autoreload match Interrupt Enable                    */
13003 #define LPTIM_IER_EXTTRIGIE_Pos       (2U)
13004 #define LPTIM_IER_EXTTRIGIE_Msk       (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)        /*!< 0x00000004 */
13005 #define LPTIM_IER_EXTTRIGIE           LPTIM_IER_EXTTRIGIE_Msk                  /*!< External trigger edge event Interrupt Enable         */
13006 #define LPTIM_IER_CMPOKIE_Pos         (3U)
13007 #define LPTIM_IER_CMPOKIE_Msk         (0x1UL << LPTIM_IER_CMPOKIE_Pos)          /*!< 0x00000008 */
13008 #define LPTIM_IER_CMPOKIE             LPTIM_IER_CMPOKIE_Msk                    /*!< Compare register update OK Interrupt Enable          */
13009 #define LPTIM_IER_ARROKIE_Pos         (4U)
13010 #define LPTIM_IER_ARROKIE_Msk         (0x1UL << LPTIM_IER_ARROKIE_Pos)          /*!< 0x00000010 */
13011 #define LPTIM_IER_ARROKIE             LPTIM_IER_ARROKIE_Msk                    /*!< Autoreload register update OK Interrupt Enable       */
13012 #define LPTIM_IER_UPIE_Pos            (5U)
13013 #define LPTIM_IER_UPIE_Msk            (0x1UL << LPTIM_IER_UPIE_Pos)             /*!< 0x00000020 */
13014 #define LPTIM_IER_UPIE                LPTIM_IER_UPIE_Msk                       /*!< Counter direction change down to up Interrupt Enable */
13015 #define LPTIM_IER_DOWNIE_Pos          (6U)
13016 #define LPTIM_IER_DOWNIE_Msk          (0x1UL << LPTIM_IER_DOWNIE_Pos)           /*!< 0x00000040 */
13017 #define LPTIM_IER_DOWNIE              LPTIM_IER_DOWNIE_Msk                     /*!< Counter direction change up to down Interrupt Enable */
13018 
13019 /******************  Bit definition for LPTIM_CFGR register *******************/
13020 #define LPTIM_CFGR_CKSEL_Pos          (0U)
13021 #define LPTIM_CFGR_CKSEL_Msk          (0x1UL << LPTIM_CFGR_CKSEL_Pos)           /*!< 0x00000001 */
13022 #define LPTIM_CFGR_CKSEL              LPTIM_CFGR_CKSEL_Msk                     /*!< Clock selector */
13023 
13024 #define LPTIM_CFGR_CKPOL_Pos          (1U)
13025 #define LPTIM_CFGR_CKPOL_Msk          (0x3UL << LPTIM_CFGR_CKPOL_Pos)           /*!< 0x00000006 */
13026 #define LPTIM_CFGR_CKPOL              LPTIM_CFGR_CKPOL_Msk                     /*!< CKPOL[1:0] bits (Clock polarity) */
13027 #define LPTIM_CFGR_CKPOL_0            (0x1UL << LPTIM_CFGR_CKPOL_Pos)           /*!< 0x00000002 */
13028 #define LPTIM_CFGR_CKPOL_1            (0x2UL << LPTIM_CFGR_CKPOL_Pos)           /*!< 0x00000004 */
13029 
13030 #define LPTIM_CFGR_CKFLT_Pos          (3U)
13031 #define LPTIM_CFGR_CKFLT_Msk          (0x3UL << LPTIM_CFGR_CKFLT_Pos)           /*!< 0x00000018 */
13032 #define LPTIM_CFGR_CKFLT              LPTIM_CFGR_CKFLT_Msk                     /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
13033 #define LPTIM_CFGR_CKFLT_0            (0x1UL << LPTIM_CFGR_CKFLT_Pos)           /*!< 0x00000008 */
13034 #define LPTIM_CFGR_CKFLT_1            (0x2UL << LPTIM_CFGR_CKFLT_Pos)           /*!< 0x00000010 */
13035 
13036 #define LPTIM_CFGR_TRGFLT_Pos         (6U)
13037 #define LPTIM_CFGR_TRGFLT_Msk         (0x3UL << LPTIM_CFGR_TRGFLT_Pos)          /*!< 0x000000C0 */
13038 #define LPTIM_CFGR_TRGFLT             LPTIM_CFGR_TRGFLT_Msk                    /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
13039 #define LPTIM_CFGR_TRGFLT_0           (0x1UL << LPTIM_CFGR_TRGFLT_Pos)          /*!< 0x00000040 */
13040 #define LPTIM_CFGR_TRGFLT_1           (0x2UL << LPTIM_CFGR_TRGFLT_Pos)          /*!< 0x00000080 */
13041 
13042 #define LPTIM_CFGR_PRESC_Pos          (9U)
13043 #define LPTIM_CFGR_PRESC_Msk          (0x7UL << LPTIM_CFGR_PRESC_Pos)           /*!< 0x00000E00 */
13044 #define LPTIM_CFGR_PRESC              LPTIM_CFGR_PRESC_Msk                     /*!< PRESC[2:0] bits (Clock prescaler) */
13045 #define LPTIM_CFGR_PRESC_0            (0x1UL << LPTIM_CFGR_PRESC_Pos)           /*!< 0x00000200 */
13046 #define LPTIM_CFGR_PRESC_1            (0x2UL << LPTIM_CFGR_PRESC_Pos)           /*!< 0x00000400 */
13047 #define LPTIM_CFGR_PRESC_2            (0x4UL << LPTIM_CFGR_PRESC_Pos)           /*!< 0x00000800 */
13048 
13049 #define LPTIM_CFGR_TRIGSEL_Pos        (13U)
13050 #define LPTIM_CFGR_TRIGSEL_Msk        (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)         /*!< 0x0000E000 */
13051 #define LPTIM_CFGR_TRIGSEL            LPTIM_CFGR_TRIGSEL_Msk                   /*!< TRIGSEL[2:0]] bits (Trigger selector) */
13052 #define LPTIM_CFGR_TRIGSEL_0          (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)         /*!< 0x00002000 */
13053 #define LPTIM_CFGR_TRIGSEL_1          (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)         /*!< 0x00004000 */
13054 #define LPTIM_CFGR_TRIGSEL_2          (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)         /*!< 0x00008000 */
13055 
13056 #define LPTIM_CFGR_TRIGEN_Pos         (17U)
13057 #define LPTIM_CFGR_TRIGEN_Msk         (0x3UL << LPTIM_CFGR_TRIGEN_Pos)          /*!< 0x00060000 */
13058 #define LPTIM_CFGR_TRIGEN             LPTIM_CFGR_TRIGEN_Msk                    /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
13059 #define LPTIM_CFGR_TRIGEN_0           (0x1UL << LPTIM_CFGR_TRIGEN_Pos)          /*!< 0x00020000 */
13060 #define LPTIM_CFGR_TRIGEN_1           (0x2UL << LPTIM_CFGR_TRIGEN_Pos)          /*!< 0x00040000 */
13061 
13062 #define LPTIM_CFGR_TIMOUT_Pos         (19U)
13063 #define LPTIM_CFGR_TIMOUT_Msk         (0x1UL << LPTIM_CFGR_TIMOUT_Pos)          /*!< 0x00080000 */
13064 #define LPTIM_CFGR_TIMOUT             LPTIM_CFGR_TIMOUT_Msk                    /*!< Timout enable           */
13065 #define LPTIM_CFGR_WAVE_Pos           (20U)
13066 #define LPTIM_CFGR_WAVE_Msk           (0x1UL << LPTIM_CFGR_WAVE_Pos)            /*!< 0x00100000 */
13067 #define LPTIM_CFGR_WAVE               LPTIM_CFGR_WAVE_Msk                      /*!< Waveform shape          */
13068 #define LPTIM_CFGR_WAVPOL_Pos         (21U)
13069 #define LPTIM_CFGR_WAVPOL_Msk         (0x1UL << LPTIM_CFGR_WAVPOL_Pos)          /*!< 0x00200000 */
13070 #define LPTIM_CFGR_WAVPOL             LPTIM_CFGR_WAVPOL_Msk                    /*!< Waveform shape polarity */
13071 #define LPTIM_CFGR_PRELOAD_Pos        (22U)
13072 #define LPTIM_CFGR_PRELOAD_Msk        (0x1UL << LPTIM_CFGR_PRELOAD_Pos)         /*!< 0x00400000 */
13073 #define LPTIM_CFGR_PRELOAD            LPTIM_CFGR_PRELOAD_Msk                   /*!< Reg update mode         */
13074 #define LPTIM_CFGR_COUNTMODE_Pos      (23U)
13075 #define LPTIM_CFGR_COUNTMODE_Msk      (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)       /*!< 0x00800000 */
13076 #define LPTIM_CFGR_COUNTMODE          LPTIM_CFGR_COUNTMODE_Msk                 /*!< Counter mode enable     */
13077 #define LPTIM_CFGR_ENC_Pos            (24U)
13078 #define LPTIM_CFGR_ENC_Msk            (0x1UL << LPTIM_CFGR_ENC_Pos)             /*!< 0x01000000 */
13079 #define LPTIM_CFGR_ENC                LPTIM_CFGR_ENC_Msk                       /*!< Encoder mode enable     */
13080 
13081 /******************  Bit definition for LPTIM_CR register  ********************/
13082 #define LPTIM_CR_ENABLE_Pos           (0U)
13083 #define LPTIM_CR_ENABLE_Msk           (0x1UL << LPTIM_CR_ENABLE_Pos)            /*!< 0x00000001 */
13084 #define LPTIM_CR_ENABLE               LPTIM_CR_ENABLE_Msk                      /*!< LPTIMer enable                 */
13085 #define LPTIM_CR_SNGSTRT_Pos          (1U)
13086 #define LPTIM_CR_SNGSTRT_Msk          (0x1UL << LPTIM_CR_SNGSTRT_Pos)           /*!< 0x00000002 */
13087 #define LPTIM_CR_SNGSTRT              LPTIM_CR_SNGSTRT_Msk                     /*!< Timer start in single mode     */
13088 #define LPTIM_CR_CNTSTRT_Pos          (2U)
13089 #define LPTIM_CR_CNTSTRT_Msk          (0x1UL << LPTIM_CR_CNTSTRT_Pos)           /*!< 0x00000004 */
13090 #define LPTIM_CR_CNTSTRT              LPTIM_CR_CNTSTRT_Msk                     /*!< Timer start in continuous mode */
13091 
13092 /******************  Bit definition for LPTIM_CMP register  *******************/
13093 #define LPTIM_CMP_CMP_Pos             (0U)
13094 #define LPTIM_CMP_CMP_Msk             (0xFFFFUL << LPTIM_CMP_CMP_Pos)           /*!< 0x0000FFFF */
13095 #define LPTIM_CMP_CMP                 LPTIM_CMP_CMP_Msk                        /*!< Compare register     */
13096 
13097 /******************  Bit definition for LPTIM_ARR register  *******************/
13098 #define LPTIM_ARR_ARR_Pos             (0U)
13099 #define LPTIM_ARR_ARR_Msk             (0xFFFFUL << LPTIM_ARR_ARR_Pos)           /*!< 0x0000FFFF */
13100 #define LPTIM_ARR_ARR                 LPTIM_ARR_ARR_Msk                        /*!< Auto reload register */
13101 
13102 /******************  Bit definition for LPTIM_CNT register  *******************/
13103 #define LPTIM_CNT_CNT_Pos             (0U)
13104 #define LPTIM_CNT_CNT_Msk             (0xFFFFUL << LPTIM_CNT_CNT_Pos)           /*!< 0x0000FFFF */
13105 #define LPTIM_CNT_CNT                 LPTIM_CNT_CNT_Msk                        /*!< Counter register     */
13106 
13107 /******************  Bit definition for LPTIM_OR register  *******************/
13108 #define LPTIM_OR_LPT_IN1_RMP_Pos      (0U)
13109 #define LPTIM_OR_LPT_IN1_RMP_Msk      (0x3UL << LPTIM_OR_LPT_IN1_RMP_Pos)       /*!< 0x00000003 */
13110 #define LPTIM_OR_LPT_IN1_RMP          LPTIM_OR_LPT_IN1_RMP_Msk                 /*!< LPTIMER[1:0] bits (Remap selection) */
13111 #define LPTIM_OR_LPT_IN1_RMP_0        (0x1UL << LPTIM_OR_LPT_IN1_RMP_Pos)       /*!< 0x00000001 */
13112 #define LPTIM_OR_LPT_IN1_RMP_1        (0x2UL << LPTIM_OR_LPT_IN1_RMP_Pos)       /*!< 0x00000002 */
13113 #define LPTIM_OR_TIM1_ITR2_RMP_Pos    (2U)
13114 #define LPTIM_OR_TIM1_ITR2_RMP_Msk    (0x1UL << LPTIM_OR_TIM1_ITR2_RMP_Pos)     /*!< 0x00000004 */
13115 #define LPTIM_OR_TIM1_ITR2_RMP        LPTIM_OR_TIM1_ITR2_RMP_Msk               /*!< Bit 2 */
13116 #define LPTIM_OR_TIM5_ITR1_RMP_Pos    (3U)
13117 #define LPTIM_OR_TIM5_ITR1_RMP_Msk    (0x1UL << LPTIM_OR_TIM5_ITR1_RMP_Pos)     /*!< 0x00000008 */
13118 #define LPTIM_OR_TIM5_ITR1_RMP        LPTIM_OR_TIM5_ITR1_RMP_Msk               /*!< Bit 3 */
13119 #define LPTIM_OR_TIM9_ITR1_RMP_Pos    (4U)
13120 #define LPTIM_OR_TIM9_ITR1_RMP_Msk    (0x1UL << LPTIM_OR_TIM9_ITR1_RMP_Pos)     /*!< 0x00000010 */
13121 #define LPTIM_OR_TIM9_ITR1_RMP        LPTIM_OR_TIM9_ITR1_RMP_Msk               /*!< Bit 4 */
13122 
13123 /* Legacy Defines */
13124 #define  LPTIM_OR_OR                           LPTIM_OR_LPT_IN1_RMP
13125 #define  LPTIM_OR_OR_0                         LPTIM_OR_LPT_IN1_RMP_0
13126 #define  LPTIM_OR_OR_1                         LPTIM_OR_LPT_IN1_RMP_1
13127 
13128 
13129 /******************************************************************************/
13130 /*                                                                            */
13131 /*         Universal Synchronous Asynchronous Receiver Transmitter            */
13132 /*                                                                            */
13133 /******************************************************************************/
13134 /*******************  Bit definition for USART_SR register  *******************/
13135 #define USART_SR_PE_Pos               (0U)
13136 #define USART_SR_PE_Msk               (0x1UL << USART_SR_PE_Pos)                /*!< 0x00000001 */
13137 #define USART_SR_PE                   USART_SR_PE_Msk                          /*!<Parity Error                 */
13138 #define USART_SR_FE_Pos               (1U)
13139 #define USART_SR_FE_Msk               (0x1UL << USART_SR_FE_Pos)                /*!< 0x00000002 */
13140 #define USART_SR_FE                   USART_SR_FE_Msk                          /*!<Framing Error                */
13141 #define USART_SR_NE_Pos               (2U)
13142 #define USART_SR_NE_Msk               (0x1UL << USART_SR_NE_Pos)                /*!< 0x00000004 */
13143 #define USART_SR_NE                   USART_SR_NE_Msk                          /*!<Noise Error Flag             */
13144 #define USART_SR_ORE_Pos              (3U)
13145 #define USART_SR_ORE_Msk              (0x1UL << USART_SR_ORE_Pos)               /*!< 0x00000008 */
13146 #define USART_SR_ORE                  USART_SR_ORE_Msk                         /*!<OverRun Error                */
13147 #define USART_SR_IDLE_Pos             (4U)
13148 #define USART_SR_IDLE_Msk             (0x1UL << USART_SR_IDLE_Pos)              /*!< 0x00000010 */
13149 #define USART_SR_IDLE                 USART_SR_IDLE_Msk                        /*!<IDLE line detected           */
13150 #define USART_SR_RXNE_Pos             (5U)
13151 #define USART_SR_RXNE_Msk             (0x1UL << USART_SR_RXNE_Pos)              /*!< 0x00000020 */
13152 #define USART_SR_RXNE                 USART_SR_RXNE_Msk                        /*!<Read Data Register Not Empty */
13153 #define USART_SR_TC_Pos               (6U)
13154 #define USART_SR_TC_Msk               (0x1UL << USART_SR_TC_Pos)                /*!< 0x00000040 */
13155 #define USART_SR_TC                   USART_SR_TC_Msk                          /*!<Transmission Complete        */
13156 #define USART_SR_TXE_Pos              (7U)
13157 #define USART_SR_TXE_Msk              (0x1UL << USART_SR_TXE_Pos)               /*!< 0x00000080 */
13158 #define USART_SR_TXE                  USART_SR_TXE_Msk                         /*!<Transmit Data Register Empty */
13159 #define USART_SR_LBD_Pos              (8U)
13160 #define USART_SR_LBD_Msk              (0x1UL << USART_SR_LBD_Pos)               /*!< 0x00000100 */
13161 #define USART_SR_LBD                  USART_SR_LBD_Msk                         /*!<LIN Break Detection Flag     */
13162 #define USART_SR_CTS_Pos              (9U)
13163 #define USART_SR_CTS_Msk              (0x1UL << USART_SR_CTS_Pos)               /*!< 0x00000200 */
13164 #define USART_SR_CTS                  USART_SR_CTS_Msk                         /*!<CTS Flag                     */
13165 
13166 /*******************  Bit definition for USART_DR register  *******************/
13167 #define USART_DR_DR_Pos               (0U)
13168 #define USART_DR_DR_Msk               (0x1FFUL << USART_DR_DR_Pos)              /*!< 0x000001FF */
13169 #define USART_DR_DR                   USART_DR_DR_Msk                          /*!<Data value */
13170 
13171 /******************  Bit definition for USART_BRR register  *******************/
13172 #define USART_BRR_DIV_Fraction_Pos    (0U)
13173 #define USART_BRR_DIV_Fraction_Msk    (0xFUL << USART_BRR_DIV_Fraction_Pos)     /*!< 0x0000000F */
13174 #define USART_BRR_DIV_Fraction        USART_BRR_DIV_Fraction_Msk               /*!<Fraction of USARTDIV */
13175 #define USART_BRR_DIV_Mantissa_Pos    (4U)
13176 #define USART_BRR_DIV_Mantissa_Msk    (0xFFFUL << USART_BRR_DIV_Mantissa_Pos)   /*!< 0x0000FFF0 */
13177 #define USART_BRR_DIV_Mantissa        USART_BRR_DIV_Mantissa_Msk               /*!<Mantissa of USARTDIV */
13178 
13179 /******************  Bit definition for USART_CR1 register  *******************/
13180 #define USART_CR1_SBK_Pos             (0U)
13181 #define USART_CR1_SBK_Msk             (0x1UL << USART_CR1_SBK_Pos)              /*!< 0x00000001 */
13182 #define USART_CR1_SBK                 USART_CR1_SBK_Msk                        /*!<Send Break                             */
13183 #define USART_CR1_RWU_Pos             (1U)
13184 #define USART_CR1_RWU_Msk             (0x1UL << USART_CR1_RWU_Pos)              /*!< 0x00000002 */
13185 #define USART_CR1_RWU                 USART_CR1_RWU_Msk                        /*!<Receiver wakeup                        */
13186 #define USART_CR1_RE_Pos              (2U)
13187 #define USART_CR1_RE_Msk              (0x1UL << USART_CR1_RE_Pos)               /*!< 0x00000004 */
13188 #define USART_CR1_RE                  USART_CR1_RE_Msk                         /*!<Receiver Enable                        */
13189 #define USART_CR1_TE_Pos              (3U)
13190 #define USART_CR1_TE_Msk              (0x1UL << USART_CR1_TE_Pos)               /*!< 0x00000008 */
13191 #define USART_CR1_TE                  USART_CR1_TE_Msk                         /*!<Transmitter Enable                     */
13192 #define USART_CR1_IDLEIE_Pos          (4U)
13193 #define USART_CR1_IDLEIE_Msk          (0x1UL << USART_CR1_IDLEIE_Pos)           /*!< 0x00000010 */
13194 #define USART_CR1_IDLEIE              USART_CR1_IDLEIE_Msk                     /*!<IDLE Interrupt Enable                  */
13195 #define USART_CR1_RXNEIE_Pos          (5U)
13196 #define USART_CR1_RXNEIE_Msk          (0x1UL << USART_CR1_RXNEIE_Pos)           /*!< 0x00000020 */
13197 #define USART_CR1_RXNEIE              USART_CR1_RXNEIE_Msk                     /*!<RXNE Interrupt Enable                  */
13198 #define USART_CR1_TCIE_Pos            (6U)
13199 #define USART_CR1_TCIE_Msk            (0x1UL << USART_CR1_TCIE_Pos)             /*!< 0x00000040 */
13200 #define USART_CR1_TCIE                USART_CR1_TCIE_Msk                       /*!<Transmission Complete Interrupt Enable */
13201 #define USART_CR1_TXEIE_Pos           (7U)
13202 #define USART_CR1_TXEIE_Msk           (0x1UL << USART_CR1_TXEIE_Pos)            /*!< 0x00000080 */
13203 #define USART_CR1_TXEIE               USART_CR1_TXEIE_Msk                      /*!<TXE Interrupt Enable                   */
13204 #define USART_CR1_PEIE_Pos            (8U)
13205 #define USART_CR1_PEIE_Msk            (0x1UL << USART_CR1_PEIE_Pos)             /*!< 0x00000100 */
13206 #define USART_CR1_PEIE                USART_CR1_PEIE_Msk                       /*!<PE Interrupt Enable                    */
13207 #define USART_CR1_PS_Pos              (9U)
13208 #define USART_CR1_PS_Msk              (0x1UL << USART_CR1_PS_Pos)               /*!< 0x00000200 */
13209 #define USART_CR1_PS                  USART_CR1_PS_Msk                         /*!<Parity Selection                       */
13210 #define USART_CR1_PCE_Pos             (10U)
13211 #define USART_CR1_PCE_Msk             (0x1UL << USART_CR1_PCE_Pos)              /*!< 0x00000400 */
13212 #define USART_CR1_PCE                 USART_CR1_PCE_Msk                        /*!<Parity Control Enable                  */
13213 #define USART_CR1_WAKE_Pos            (11U)
13214 #define USART_CR1_WAKE_Msk            (0x1UL << USART_CR1_WAKE_Pos)             /*!< 0x00000800 */
13215 #define USART_CR1_WAKE                USART_CR1_WAKE_Msk                       /*!<Wakeup method                          */
13216 #define USART_CR1_M_Pos               (12U)
13217 #define USART_CR1_M_Msk               (0x1UL << USART_CR1_M_Pos)                /*!< 0x00001000 */
13218 #define USART_CR1_M                   USART_CR1_M_Msk                          /*!<Word length                            */
13219 #define USART_CR1_UE_Pos              (13U)
13220 #define USART_CR1_UE_Msk              (0x1UL << USART_CR1_UE_Pos)               /*!< 0x00002000 */
13221 #define USART_CR1_UE                  USART_CR1_UE_Msk                         /*!<USART Enable                           */
13222 #define USART_CR1_OVER8_Pos           (15U)
13223 #define USART_CR1_OVER8_Msk           (0x1UL << USART_CR1_OVER8_Pos)            /*!< 0x00008000 */
13224 #define USART_CR1_OVER8               USART_CR1_OVER8_Msk                      /*!<USART Oversampling by 8 enable         */
13225 
13226 /******************  Bit definition for USART_CR2 register  *******************/
13227 #define USART_CR2_ADD_Pos             (0U)
13228 #define USART_CR2_ADD_Msk             (0xFUL << USART_CR2_ADD_Pos)              /*!< 0x0000000F */
13229 #define USART_CR2_ADD                 USART_CR2_ADD_Msk                        /*!<Address of the USART node            */
13230 #define USART_CR2_LBDL_Pos            (5U)
13231 #define USART_CR2_LBDL_Msk            (0x1UL << USART_CR2_LBDL_Pos)             /*!< 0x00000020 */
13232 #define USART_CR2_LBDL                USART_CR2_LBDL_Msk                       /*!<LIN Break Detection Length           */
13233 #define USART_CR2_LBDIE_Pos           (6U)
13234 #define USART_CR2_LBDIE_Msk           (0x1UL << USART_CR2_LBDIE_Pos)            /*!< 0x00000040 */
13235 #define USART_CR2_LBDIE               USART_CR2_LBDIE_Msk                      /*!<LIN Break Detection Interrupt Enable */
13236 #define USART_CR2_LBCL_Pos            (8U)
13237 #define USART_CR2_LBCL_Msk            (0x1UL << USART_CR2_LBCL_Pos)             /*!< 0x00000100 */
13238 #define USART_CR2_LBCL                USART_CR2_LBCL_Msk                       /*!<Last Bit Clock pulse                 */
13239 #define USART_CR2_CPHA_Pos            (9U)
13240 #define USART_CR2_CPHA_Msk            (0x1UL << USART_CR2_CPHA_Pos)             /*!< 0x00000200 */
13241 #define USART_CR2_CPHA                USART_CR2_CPHA_Msk                       /*!<Clock Phase                          */
13242 #define USART_CR2_CPOL_Pos            (10U)
13243 #define USART_CR2_CPOL_Msk            (0x1UL << USART_CR2_CPOL_Pos)             /*!< 0x00000400 */
13244 #define USART_CR2_CPOL                USART_CR2_CPOL_Msk                       /*!<Clock Polarity                       */
13245 #define USART_CR2_CLKEN_Pos           (11U)
13246 #define USART_CR2_CLKEN_Msk           (0x1UL << USART_CR2_CLKEN_Pos)            /*!< 0x00000800 */
13247 #define USART_CR2_CLKEN               USART_CR2_CLKEN_Msk                      /*!<Clock Enable                         */
13248 
13249 #define USART_CR2_STOP_Pos            (12U)
13250 #define USART_CR2_STOP_Msk            (0x3UL << USART_CR2_STOP_Pos)             /*!< 0x00003000 */
13251 #define USART_CR2_STOP                USART_CR2_STOP_Msk                       /*!<STOP[1:0] bits (STOP bits) */
13252 #define USART_CR2_STOP_0              (0x1UL << USART_CR2_STOP_Pos)             /*!< 0x1000 */
13253 #define USART_CR2_STOP_1              (0x2UL << USART_CR2_STOP_Pos)             /*!< 0x2000 */
13254 
13255 #define USART_CR2_LINEN_Pos           (14U)
13256 #define USART_CR2_LINEN_Msk           (0x1UL << USART_CR2_LINEN_Pos)            /*!< 0x00004000 */
13257 #define USART_CR2_LINEN               USART_CR2_LINEN_Msk                      /*!<LIN mode enable */
13258 
13259 /******************  Bit definition for USART_CR3 register  *******************/
13260 #define USART_CR3_EIE_Pos             (0U)
13261 #define USART_CR3_EIE_Msk             (0x1UL << USART_CR3_EIE_Pos)              /*!< 0x00000001 */
13262 #define USART_CR3_EIE                 USART_CR3_EIE_Msk                        /*!<Error Interrupt Enable      */
13263 #define USART_CR3_IREN_Pos            (1U)
13264 #define USART_CR3_IREN_Msk            (0x1UL << USART_CR3_IREN_Pos)             /*!< 0x00000002 */
13265 #define USART_CR3_IREN                USART_CR3_IREN_Msk                       /*!<IrDA mode Enable            */
13266 #define USART_CR3_IRLP_Pos            (2U)
13267 #define USART_CR3_IRLP_Msk            (0x1UL << USART_CR3_IRLP_Pos)             /*!< 0x00000004 */
13268 #define USART_CR3_IRLP                USART_CR3_IRLP_Msk                       /*!<IrDA Low-Power              */
13269 #define USART_CR3_HDSEL_Pos           (3U)
13270 #define USART_CR3_HDSEL_Msk           (0x1UL << USART_CR3_HDSEL_Pos)            /*!< 0x00000008 */
13271 #define USART_CR3_HDSEL               USART_CR3_HDSEL_Msk                      /*!<Half-Duplex Selection       */
13272 #define USART_CR3_NACK_Pos            (4U)
13273 #define USART_CR3_NACK_Msk            (0x1UL << USART_CR3_NACK_Pos)             /*!< 0x00000010 */
13274 #define USART_CR3_NACK                USART_CR3_NACK_Msk                       /*!<Smartcard NACK enable       */
13275 #define USART_CR3_SCEN_Pos            (5U)
13276 #define USART_CR3_SCEN_Msk            (0x1UL << USART_CR3_SCEN_Pos)             /*!< 0x00000020 */
13277 #define USART_CR3_SCEN                USART_CR3_SCEN_Msk                       /*!<Smartcard mode enable       */
13278 #define USART_CR3_DMAR_Pos            (6U)
13279 #define USART_CR3_DMAR_Msk            (0x1UL << USART_CR3_DMAR_Pos)             /*!< 0x00000040 */
13280 #define USART_CR3_DMAR                USART_CR3_DMAR_Msk                       /*!<DMA Enable Receiver         */
13281 #define USART_CR3_DMAT_Pos            (7U)
13282 #define USART_CR3_DMAT_Msk            (0x1UL << USART_CR3_DMAT_Pos)             /*!< 0x00000080 */
13283 #define USART_CR3_DMAT                USART_CR3_DMAT_Msk                       /*!<DMA Enable Transmitter      */
13284 #define USART_CR3_RTSE_Pos            (8U)
13285 #define USART_CR3_RTSE_Msk            (0x1UL << USART_CR3_RTSE_Pos)             /*!< 0x00000100 */
13286 #define USART_CR3_RTSE                USART_CR3_RTSE_Msk                       /*!<RTS Enable                  */
13287 #define USART_CR3_CTSE_Pos            (9U)
13288 #define USART_CR3_CTSE_Msk            (0x1UL << USART_CR3_CTSE_Pos)             /*!< 0x00000200 */
13289 #define USART_CR3_CTSE                USART_CR3_CTSE_Msk                       /*!<CTS Enable                  */
13290 #define USART_CR3_CTSIE_Pos           (10U)
13291 #define USART_CR3_CTSIE_Msk           (0x1UL << USART_CR3_CTSIE_Pos)            /*!< 0x00000400 */
13292 #define USART_CR3_CTSIE               USART_CR3_CTSIE_Msk                      /*!<CTS Interrupt Enable        */
13293 #define USART_CR3_ONEBIT_Pos          (11U)
13294 #define USART_CR3_ONEBIT_Msk          (0x1UL << USART_CR3_ONEBIT_Pos)           /*!< 0x00000800 */
13295 #define USART_CR3_ONEBIT              USART_CR3_ONEBIT_Msk                     /*!<USART One bit method enable */
13296 
13297 /******************  Bit definition for USART_GTPR register  ******************/
13298 #define USART_GTPR_PSC_Pos            (0U)
13299 #define USART_GTPR_PSC_Msk            (0xFFUL << USART_GTPR_PSC_Pos)            /*!< 0x000000FF */
13300 #define USART_GTPR_PSC                USART_GTPR_PSC_Msk                       /*!<PSC[7:0] bits (Prescaler value) */
13301 #define USART_GTPR_PSC_0              (0x01UL << USART_GTPR_PSC_Pos)            /*!< 0x0001 */
13302 #define USART_GTPR_PSC_1              (0x02UL << USART_GTPR_PSC_Pos)            /*!< 0x0002 */
13303 #define USART_GTPR_PSC_2              (0x04UL << USART_GTPR_PSC_Pos)            /*!< 0x0004 */
13304 #define USART_GTPR_PSC_3              (0x08UL << USART_GTPR_PSC_Pos)            /*!< 0x0008 */
13305 #define USART_GTPR_PSC_4              (0x10UL << USART_GTPR_PSC_Pos)            /*!< 0x0010 */
13306 #define USART_GTPR_PSC_5              (0x20UL << USART_GTPR_PSC_Pos)            /*!< 0x0020 */
13307 #define USART_GTPR_PSC_6              (0x40UL << USART_GTPR_PSC_Pos)            /*!< 0x0040 */
13308 #define USART_GTPR_PSC_7              (0x80UL << USART_GTPR_PSC_Pos)            /*!< 0x0080 */
13309 
13310 #define USART_GTPR_GT_Pos             (8U)
13311 #define USART_GTPR_GT_Msk             (0xFFUL << USART_GTPR_GT_Pos)             /*!< 0x0000FF00 */
13312 #define USART_GTPR_GT                 USART_GTPR_GT_Msk                        /*!<Guard time value */
13313 
13314 /******************************************************************************/
13315 /*                                                                            */
13316 /*                            Window WATCHDOG                                 */
13317 /*                                                                            */
13318 /******************************************************************************/
13319 /*******************  Bit definition for WWDG_CR register  ********************/
13320 #define WWDG_CR_T_Pos           (0U)
13321 #define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                       /*!< 0x0000007F */
13322 #define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
13323 #define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                       /*!< 0x01 */
13324 #define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                       /*!< 0x02 */
13325 #define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                       /*!< 0x04 */
13326 #define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                       /*!< 0x08 */
13327 #define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                       /*!< 0x10 */
13328 #define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                       /*!< 0x20 */
13329 #define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                       /*!< 0x40 */
13330 /* Legacy defines */
13331 #define  WWDG_CR_T0                          WWDG_CR_T_0
13332 #define  WWDG_CR_T1                          WWDG_CR_T_1
13333 #define  WWDG_CR_T2                          WWDG_CR_T_2
13334 #define  WWDG_CR_T3                          WWDG_CR_T_3
13335 #define  WWDG_CR_T4                          WWDG_CR_T_4
13336 #define  WWDG_CR_T5                          WWDG_CR_T_5
13337 #define  WWDG_CR_T6                          WWDG_CR_T_6
13338 
13339 #define WWDG_CR_WDGA_Pos        (7U)
13340 #define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                     /*!< 0x00000080 */
13341 #define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */
13342 
13343 /*******************  Bit definition for WWDG_CFR register  *******************/
13344 #define WWDG_CFR_W_Pos          (0U)
13345 #define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                      /*!< 0x0000007F */
13346 #define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */
13347 #define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                      /*!< 0x0001 */
13348 #define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                      /*!< 0x0002 */
13349 #define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                      /*!< 0x0004 */
13350 #define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                      /*!< 0x0008 */
13351 #define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                      /*!< 0x0010 */
13352 #define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                      /*!< 0x0020 */
13353 #define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                      /*!< 0x0040 */
13354 /* Legacy defines */
13355 #define  WWDG_CFR_W0                         WWDG_CFR_W_0
13356 #define  WWDG_CFR_W1                         WWDG_CFR_W_1
13357 #define  WWDG_CFR_W2                         WWDG_CFR_W_2
13358 #define  WWDG_CFR_W3                         WWDG_CFR_W_3
13359 #define  WWDG_CFR_W4                         WWDG_CFR_W_4
13360 #define  WWDG_CFR_W5                         WWDG_CFR_W_5
13361 #define  WWDG_CFR_W6                         WWDG_CFR_W_6
13362 
13363 #define WWDG_CFR_WDGTB_Pos      (7U)
13364 #define WWDG_CFR_WDGTB_Msk      (0x3UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000180 */
13365 #define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[1:0] bits (Timer Base) */
13366 #define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x0080 */
13367 #define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x0100 */
13368 /* Legacy defines */
13369 #define  WWDG_CFR_WDGTB0                     WWDG_CFR_WDGTB_0
13370 #define  WWDG_CFR_WDGTB1                     WWDG_CFR_WDGTB_1
13371 
13372 #define WWDG_CFR_EWI_Pos        (9U)
13373 #define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                     /*!< 0x00000200 */
13374 #define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */
13375 
13376 /*******************  Bit definition for WWDG_SR register  ********************/
13377 #define WWDG_SR_EWIF_Pos        (0U)
13378 #define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                     /*!< 0x00000001 */
13379 #define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */
13380 
13381 
13382 /******************************************************************************/
13383 /*                                                                            */
13384 /*                                DBG                                         */
13385 /*                                                                            */
13386 /******************************************************************************/
13387 /********************  Bit definition for DBGMCU_IDCODE register  *************/
13388 #define DBGMCU_IDCODE_DEV_ID_Pos                     (0U)
13389 #define DBGMCU_IDCODE_DEV_ID_Msk                     (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
13390 #define DBGMCU_IDCODE_DEV_ID                         DBGMCU_IDCODE_DEV_ID_Msk
13391 #define DBGMCU_IDCODE_REV_ID_Pos                     (16U)
13392 #define DBGMCU_IDCODE_REV_ID_Msk                     (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
13393 #define DBGMCU_IDCODE_REV_ID                         DBGMCU_IDCODE_REV_ID_Msk
13394 
13395 /********************  Bit definition for DBGMCU_CR register  *****************/
13396 #define DBGMCU_CR_DBG_SLEEP_Pos                      (0U)
13397 #define DBGMCU_CR_DBG_SLEEP_Msk                      (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
13398 #define DBGMCU_CR_DBG_SLEEP                          DBGMCU_CR_DBG_SLEEP_Msk
13399 #define DBGMCU_CR_DBG_STOP_Pos                       (1U)
13400 #define DBGMCU_CR_DBG_STOP_Msk                       (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
13401 #define DBGMCU_CR_DBG_STOP                           DBGMCU_CR_DBG_STOP_Msk
13402 #define DBGMCU_CR_DBG_STANDBY_Pos                    (2U)
13403 #define DBGMCU_CR_DBG_STANDBY_Msk                    (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
13404 #define DBGMCU_CR_DBG_STANDBY                        DBGMCU_CR_DBG_STANDBY_Msk
13405 #define DBGMCU_CR_TRACE_IOEN_Pos                     (5U)
13406 #define DBGMCU_CR_TRACE_IOEN_Msk                     (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
13407 #define DBGMCU_CR_TRACE_IOEN                         DBGMCU_CR_TRACE_IOEN_Msk
13408 
13409 #define DBGMCU_CR_TRACE_MODE_Pos                     (6U)
13410 #define DBGMCU_CR_TRACE_MODE_Msk                     (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
13411 #define DBGMCU_CR_TRACE_MODE                         DBGMCU_CR_TRACE_MODE_Msk
13412 #define DBGMCU_CR_TRACE_MODE_0                       (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
13413 #define DBGMCU_CR_TRACE_MODE_1                       (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
13414 
13415 /********************  Bit definition for DBGMCU_APB1_FZ register  ************/
13416 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos             (0U)
13417 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
13418 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP                 DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
13419 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos             (1U)
13420 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
13421 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP                 DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
13422 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos             (2U)
13423 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
13424 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP                 DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
13425 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos             (3U)
13426 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
13427 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP                 DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
13428 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos             (4U)
13429 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
13430 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP                 DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
13431 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos             (5U)
13432 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
13433 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP                 DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
13434 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos            (6U)
13435 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk            (0x1UL << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */
13436 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP                DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk
13437 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos            (7U)
13438 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk            (0x1UL << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos) /*!< 0x00000080 */
13439 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP                DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk
13440 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos            (8U)
13441 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk            (0x1UL << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */
13442 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP                DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk
13443 #define DBGMCU_APB1_FZ_DBG_LPTIM_STOP_Pos            (9U)
13444 #define DBGMCU_APB1_FZ_DBG_LPTIM_STOP_Msk            (0x1UL << DBGMCU_APB1_FZ_DBG_LPTIM_STOP_Pos) /*!< 0x00000200 */
13445 #define DBGMCU_APB1_FZ_DBG_LPTIM_STOP                DBGMCU_APB1_FZ_DBG_LPTIM_STOP_Msk
13446 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos              (10U)
13447 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk              (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
13448 #define DBGMCU_APB1_FZ_DBG_RTC_STOP                  DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
13449 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos             (11U)
13450 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
13451 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP                 DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
13452 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos             (12U)
13453 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
13454 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP                 DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
13455 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos    (21U)
13456 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
13457 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
13458 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos    (22U)
13459 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
13460 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
13461 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos    (23U)
13462 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) /*!< 0x00800000 */
13463 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk
13464 #define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos    (24U)
13465 #define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos) /*!< 0x01000000 */
13466 #define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk
13467 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos             (25U)
13468 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos) /*!< 0x02000000 */
13469 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP                 DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk
13470 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos             (26U)
13471 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos) /*!< 0x04000000 */
13472 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP                 DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk
13473 #define DBGMCU_APB1_FZ_DBG_CAN3_STOP_Pos             (27U)
13474 #define DBGMCU_APB1_FZ_DBG_CAN3_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_CAN3_STOP_Pos) /*!< 0x08000000 */
13475 #define DBGMCU_APB1_FZ_DBG_CAN3_STOP                 DBGMCU_APB1_FZ_DBG_CAN3_STOP_Msk
13476 
13477 /********************  Bit definition for DBGMCU_APB2_FZ register  ************/
13478 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos             (0U)
13479 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk             (0x1UL << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */
13480 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP                 DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
13481 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos             (1U)
13482 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk             (0x1UL << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos) /*!< 0x00000002 */
13483 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP                 DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk
13484 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos             (16U)
13485 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk             (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */
13486 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP                 DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
13487 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos            (17U)
13488 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk            (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00020000 */
13489 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP                DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk
13490 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos            (18U)
13491 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk            (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */
13492 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP                DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
13493 
13494 /******************************************************************************/
13495 /*                                                                            */
13496 /*                                       USB_OTG                              */
13497 /*                                                                            */
13498 /******************************************************************************/
13499 /********************  Bit definition for USB_OTG_GOTGCTL register  ***********/
13500 #define USB_OTG_GOTGCTL_SRQSCS_Pos               (0U)
13501 #define USB_OTG_GOTGCTL_SRQSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
13502 #define USB_OTG_GOTGCTL_SRQSCS                   USB_OTG_GOTGCTL_SRQSCS_Msk    /*!< Session request success */
13503 #define USB_OTG_GOTGCTL_SRQ_Pos                  (1U)
13504 #define USB_OTG_GOTGCTL_SRQ_Msk                  (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
13505 #define USB_OTG_GOTGCTL_SRQ                      USB_OTG_GOTGCTL_SRQ_Msk       /*!< Session request */
13506 #define USB_OTG_GOTGCTL_VBVALOEN_Pos             (2U)
13507 #define USB_OTG_GOTGCTL_VBVALOEN_Msk             (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */
13508 #define USB_OTG_GOTGCTL_VBVALOEN                 USB_OTG_GOTGCTL_VBVALOEN_Msk  /*!< VBUS valid override enable */
13509 #define USB_OTG_GOTGCTL_VBVALOVAL_Pos            (3U)
13510 #define USB_OTG_GOTGCTL_VBVALOVAL_Msk            (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */
13511 #define USB_OTG_GOTGCTL_VBVALOVAL                USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */
13512 #define USB_OTG_GOTGCTL_AVALOEN_Pos              (4U)
13513 #define USB_OTG_GOTGCTL_AVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */
13514 #define USB_OTG_GOTGCTL_AVALOEN                  USB_OTG_GOTGCTL_AVALOEN_Msk   /*!< A-peripheral session valid override enable */
13515 #define USB_OTG_GOTGCTL_AVALOVAL_Pos             (5U)
13516 #define USB_OTG_GOTGCTL_AVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */
13517 #define USB_OTG_GOTGCTL_AVALOVAL                 USB_OTG_GOTGCTL_AVALOVAL_Msk  /*!< A-peripheral session valid override value */
13518 #define USB_OTG_GOTGCTL_BVALOEN_Pos              (6U)
13519 #define USB_OTG_GOTGCTL_BVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */
13520 #define USB_OTG_GOTGCTL_BVALOEN                  USB_OTG_GOTGCTL_BVALOEN_Msk   /*!< B-peripheral session valid override enable */
13521 #define USB_OTG_GOTGCTL_BVALOVAL_Pos             (7U)
13522 #define USB_OTG_GOTGCTL_BVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */
13523 #define USB_OTG_GOTGCTL_BVALOVAL                 USB_OTG_GOTGCTL_BVALOVAL_Msk  /*!< B-peripheral session valid override value  */
13524 #define USB_OTG_GOTGCTL_HNGSCS_Pos               (8U)
13525 #define USB_OTG_GOTGCTL_HNGSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
13526 #define USB_OTG_GOTGCTL_HNGSCS                   USB_OTG_GOTGCTL_HNGSCS_Msk    /*!< Host set HNP enable */
13527 #define USB_OTG_GOTGCTL_HNPRQ_Pos                (9U)
13528 #define USB_OTG_GOTGCTL_HNPRQ_Msk                (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
13529 #define USB_OTG_GOTGCTL_HNPRQ                    USB_OTG_GOTGCTL_HNPRQ_Msk     /*!< HNP request */
13530 #define USB_OTG_GOTGCTL_HSHNPEN_Pos              (10U)
13531 #define USB_OTG_GOTGCTL_HSHNPEN_Msk              (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
13532 #define USB_OTG_GOTGCTL_HSHNPEN                  USB_OTG_GOTGCTL_HSHNPEN_Msk   /*!< Host set HNP enable */
13533 #define USB_OTG_GOTGCTL_DHNPEN_Pos               (11U)
13534 #define USB_OTG_GOTGCTL_DHNPEN_Msk               (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
13535 #define USB_OTG_GOTGCTL_DHNPEN                   USB_OTG_GOTGCTL_DHNPEN_Msk    /*!< Device HNP enabled */
13536 #define USB_OTG_GOTGCTL_EHEN_Pos                 (12U)
13537 #define USB_OTG_GOTGCTL_EHEN_Msk                 (0x1UL << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */
13538 #define USB_OTG_GOTGCTL_EHEN                     USB_OTG_GOTGCTL_EHEN_Msk      /*!< Embedded host enable */
13539 #define USB_OTG_GOTGCTL_CIDSTS_Pos               (16U)
13540 #define USB_OTG_GOTGCTL_CIDSTS_Msk               (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
13541 #define USB_OTG_GOTGCTL_CIDSTS                   USB_OTG_GOTGCTL_CIDSTS_Msk    /*!< Connector ID status */
13542 #define USB_OTG_GOTGCTL_DBCT_Pos                 (17U)
13543 #define USB_OTG_GOTGCTL_DBCT_Msk                 (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
13544 #define USB_OTG_GOTGCTL_DBCT                     USB_OTG_GOTGCTL_DBCT_Msk      /*!< Long/short debounce time */
13545 #define USB_OTG_GOTGCTL_ASVLD_Pos                (18U)
13546 #define USB_OTG_GOTGCTL_ASVLD_Msk                (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
13547 #define USB_OTG_GOTGCTL_ASVLD                    USB_OTG_GOTGCTL_ASVLD_Msk     /*!< A-session valid  */
13548 #define USB_OTG_GOTGCTL_BSESVLD_Pos              (19U)
13549 #define USB_OTG_GOTGCTL_BSESVLD_Msk              (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */
13550 #define USB_OTG_GOTGCTL_BSESVLD                  USB_OTG_GOTGCTL_BSESVLD_Msk   /*!< B-session valid */
13551 #define USB_OTG_GOTGCTL_OTGVER_Pos               (20U)
13552 #define USB_OTG_GOTGCTL_OTGVER_Msk               (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
13553 #define USB_OTG_GOTGCTL_OTGVER                   USB_OTG_GOTGCTL_OTGVER_Msk    /*!< OTG version  */
13554 
13555 /********************  Bit definition forUSB_OTG_HCFG register  ********************/
13556 
13557 #define USB_OTG_HCFG_FSLSPCS_Pos                 (0U)
13558 #define USB_OTG_HCFG_FSLSPCS_Msk                 (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
13559 #define USB_OTG_HCFG_FSLSPCS                     USB_OTG_HCFG_FSLSPCS_Msk      /*!< FS/LS PHY clock select  */
13560 #define USB_OTG_HCFG_FSLSPCS_0                   (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
13561 #define USB_OTG_HCFG_FSLSPCS_1                   (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
13562 #define USB_OTG_HCFG_FSLSS_Pos                   (2U)
13563 #define USB_OTG_HCFG_FSLSS_Msk                   (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
13564 #define USB_OTG_HCFG_FSLSS                       USB_OTG_HCFG_FSLSS_Msk        /*!< FS- and LS-only support */
13565 
13566 /********************  Bit definition for USB_OTG_DCFG register  ********************/
13567 
13568 #define USB_OTG_DCFG_DSPD_Pos                    (0U)
13569 #define USB_OTG_DCFG_DSPD_Msk                    (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
13570 #define USB_OTG_DCFG_DSPD                        USB_OTG_DCFG_DSPD_Msk         /*!< Device speed */
13571 #define USB_OTG_DCFG_DSPD_0                      (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
13572 #define USB_OTG_DCFG_DSPD_1                      (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
13573 #define USB_OTG_DCFG_NZLSOHSK_Pos                (2U)
13574 #define USB_OTG_DCFG_NZLSOHSK_Msk                (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
13575 #define USB_OTG_DCFG_NZLSOHSK                    USB_OTG_DCFG_NZLSOHSK_Msk     /*!< Nonzero-length status OUT handshake */
13576 
13577 #define USB_OTG_DCFG_DAD_Pos                     (4U)
13578 #define USB_OTG_DCFG_DAD_Msk                     (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
13579 #define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk          /*!< Device address */
13580 #define USB_OTG_DCFG_DAD_0                       (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
13581 #define USB_OTG_DCFG_DAD_1                       (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
13582 #define USB_OTG_DCFG_DAD_2                       (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
13583 #define USB_OTG_DCFG_DAD_3                       (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
13584 #define USB_OTG_DCFG_DAD_4                       (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
13585 #define USB_OTG_DCFG_DAD_5                       (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
13586 #define USB_OTG_DCFG_DAD_6                       (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
13587 
13588 #define USB_OTG_DCFG_PFIVL_Pos                   (11U)
13589 #define USB_OTG_DCFG_PFIVL_Msk                   (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
13590 #define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk        /*!< Periodic (micro)frame interval */
13591 #define USB_OTG_DCFG_PFIVL_0                     (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
13592 #define USB_OTG_DCFG_PFIVL_1                     (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
13593 
13594 #define USB_OTG_DCFG_XCVRDLY_Pos                 (14U)
13595 #define USB_OTG_DCFG_XCVRDLY_Msk                 (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */
13596 #define USB_OTG_DCFG_XCVRDLY                     USB_OTG_DCFG_XCVRDLY_Msk        /*!< Transceiver delay */
13597 
13598 #define USB_OTG_DCFG_ERRATIM_Pos                 (15U)
13599 #define USB_OTG_DCFG_ERRATIM_Msk                 (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */
13600 #define USB_OTG_DCFG_ERRATIM                     USB_OTG_DCFG_ERRATIM_Msk        /*!< Erratic error interrupt mask */
13601 
13602 #define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)
13603 #define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
13604 #define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk    /*!< Periodic scheduling interval */
13605 #define USB_OTG_DCFG_PERSCHIVL_0                 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
13606 #define USB_OTG_DCFG_PERSCHIVL_1                 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
13607 
13608 /********************  Bit definition for USB_OTG_PCGCR register  ********************/
13609 #define USB_OTG_PCGCR_STPPCLK_Pos                (0U)
13610 #define USB_OTG_PCGCR_STPPCLK_Msk                (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
13611 #define USB_OTG_PCGCR_STPPCLK                    USB_OTG_PCGCR_STPPCLK_Msk     /*!< Stop PHY clock */
13612 #define USB_OTG_PCGCR_GATEHCLK_Pos               (1U)
13613 #define USB_OTG_PCGCR_GATEHCLK_Msk               (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
13614 #define USB_OTG_PCGCR_GATEHCLK                   USB_OTG_PCGCR_GATEHCLK_Msk    /*!< Gate HCLK */
13615 #define USB_OTG_PCGCR_PHYSUSP_Pos                (4U)
13616 #define USB_OTG_PCGCR_PHYSUSP_Msk                (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
13617 #define USB_OTG_PCGCR_PHYSUSP                    USB_OTG_PCGCR_PHYSUSP_Msk     /*!< PHY suspended */
13618 
13619 /********************  Bit definition for USB_OTG_GOTGINT register  ********************/
13620 #define USB_OTG_GOTGINT_SEDET_Pos                (2U)
13621 #define USB_OTG_GOTGINT_SEDET_Msk                (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
13622 #define USB_OTG_GOTGINT_SEDET                    USB_OTG_GOTGINT_SEDET_Msk     /*!< Session end detected                   */
13623 #define USB_OTG_GOTGINT_SRSSCHG_Pos              (8U)
13624 #define USB_OTG_GOTGINT_SRSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
13625 #define USB_OTG_GOTGINT_SRSSCHG                  USB_OTG_GOTGINT_SRSSCHG_Msk   /*!< Session request success status change  */
13626 #define USB_OTG_GOTGINT_HNSSCHG_Pos              (9U)
13627 #define USB_OTG_GOTGINT_HNSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
13628 #define USB_OTG_GOTGINT_HNSSCHG                  USB_OTG_GOTGINT_HNSSCHG_Msk   /*!< Host negotiation success status change */
13629 #define USB_OTG_GOTGINT_HNGDET_Pos               (17U)
13630 #define USB_OTG_GOTGINT_HNGDET_Msk               (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
13631 #define USB_OTG_GOTGINT_HNGDET                   USB_OTG_GOTGINT_HNGDET_Msk    /*!< Host negotiation detected              */
13632 #define USB_OTG_GOTGINT_ADTOCHG_Pos              (18U)
13633 #define USB_OTG_GOTGINT_ADTOCHG_Msk              (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
13634 #define USB_OTG_GOTGINT_ADTOCHG                  USB_OTG_GOTGINT_ADTOCHG_Msk   /*!< A-device timeout change                */
13635 #define USB_OTG_GOTGINT_DBCDNE_Pos               (19U)
13636 #define USB_OTG_GOTGINT_DBCDNE_Msk               (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
13637 #define USB_OTG_GOTGINT_DBCDNE                   USB_OTG_GOTGINT_DBCDNE_Msk    /*!< Debounce done                          */
13638 #define USB_OTG_GOTGINT_IDCHNG_Pos               (20U)
13639 #define USB_OTG_GOTGINT_IDCHNG_Msk               (0x1UL << USB_OTG_GOTGINT_IDCHNG_Pos) /*!< 0x00100000 */
13640 #define USB_OTG_GOTGINT_IDCHNG                   USB_OTG_GOTGINT_IDCHNG_Msk    /*!< Change in ID pin input value           */
13641 
13642 /********************  Bit definition for USB_OTG_DCTL register  ********************/
13643 #define USB_OTG_DCTL_RWUSIG_Pos                  (0U)
13644 #define USB_OTG_DCTL_RWUSIG_Msk                  (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
13645 #define USB_OTG_DCTL_RWUSIG                      USB_OTG_DCTL_RWUSIG_Msk       /*!< Remote wakeup signaling */
13646 #define USB_OTG_DCTL_SDIS_Pos                    (1U)
13647 #define USB_OTG_DCTL_SDIS_Msk                    (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
13648 #define USB_OTG_DCTL_SDIS                        USB_OTG_DCTL_SDIS_Msk         /*!< Soft disconnect         */
13649 #define USB_OTG_DCTL_GINSTS_Pos                  (2U)
13650 #define USB_OTG_DCTL_GINSTS_Msk                  (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
13651 #define USB_OTG_DCTL_GINSTS                      USB_OTG_DCTL_GINSTS_Msk       /*!< Global IN NAK status    */
13652 #define USB_OTG_DCTL_GONSTS_Pos                  (3U)
13653 #define USB_OTG_DCTL_GONSTS_Msk                  (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
13654 #define USB_OTG_DCTL_GONSTS                      USB_OTG_DCTL_GONSTS_Msk       /*!< Global OUT NAK status   */
13655 
13656 #define USB_OTG_DCTL_TCTL_Pos                    (4U)
13657 #define USB_OTG_DCTL_TCTL_Msk                    (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
13658 #define USB_OTG_DCTL_TCTL                        USB_OTG_DCTL_TCTL_Msk         /*!< Test control */
13659 #define USB_OTG_DCTL_TCTL_0                      (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
13660 #define USB_OTG_DCTL_TCTL_1                      (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
13661 #define USB_OTG_DCTL_TCTL_2                      (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
13662 #define USB_OTG_DCTL_SGINAK_Pos                  (7U)
13663 #define USB_OTG_DCTL_SGINAK_Msk                  (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
13664 #define USB_OTG_DCTL_SGINAK                      USB_OTG_DCTL_SGINAK_Msk       /*!< Set global IN NAK         */
13665 #define USB_OTG_DCTL_CGINAK_Pos                  (8U)
13666 #define USB_OTG_DCTL_CGINAK_Msk                  (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
13667 #define USB_OTG_DCTL_CGINAK                      USB_OTG_DCTL_CGINAK_Msk       /*!< Clear global IN NAK       */
13668 #define USB_OTG_DCTL_SGONAK_Pos                  (9U)
13669 #define USB_OTG_DCTL_SGONAK_Msk                  (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
13670 #define USB_OTG_DCTL_SGONAK                      USB_OTG_DCTL_SGONAK_Msk       /*!< Set global OUT NAK        */
13671 #define USB_OTG_DCTL_CGONAK_Pos                  (10U)
13672 #define USB_OTG_DCTL_CGONAK_Msk                  (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
13673 #define USB_OTG_DCTL_CGONAK                      USB_OTG_DCTL_CGONAK_Msk       /*!< Clear global OUT NAK      */
13674 #define USB_OTG_DCTL_POPRGDNE_Pos                (11U)
13675 #define USB_OTG_DCTL_POPRGDNE_Msk                (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
13676 #define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */
13677 
13678 /********************  Bit definition for USB_OTG_HFIR register  ********************/
13679 #define USB_OTG_HFIR_FRIVL_Pos                   (0U)
13680 #define USB_OTG_HFIR_FRIVL_Msk                   (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
13681 #define USB_OTG_HFIR_FRIVL                       USB_OTG_HFIR_FRIVL_Msk        /*!< Frame interval */
13682 
13683 /********************  Bit definition for USB_OTG_HFNUM register  ********************/
13684 #define USB_OTG_HFNUM_FRNUM_Pos                  (0U)
13685 #define USB_OTG_HFNUM_FRNUM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
13686 #define USB_OTG_HFNUM_FRNUM                      USB_OTG_HFNUM_FRNUM_Msk       /*!< Frame number         */
13687 #define USB_OTG_HFNUM_FTREM_Pos                  (16U)
13688 #define USB_OTG_HFNUM_FTREM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
13689 #define USB_OTG_HFNUM_FTREM                      USB_OTG_HFNUM_FTREM_Msk       /*!< Frame time remaining */
13690 
13691 /********************  Bit definition for USB_OTG_DSTS register  ********************/
13692 #define USB_OTG_DSTS_SUSPSTS_Pos                 (0U)
13693 #define USB_OTG_DSTS_SUSPSTS_Msk                 (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
13694 #define USB_OTG_DSTS_SUSPSTS                     USB_OTG_DSTS_SUSPSTS_Msk      /*!< Suspend status   */
13695 
13696 #define USB_OTG_DSTS_ENUMSPD_Pos                 (1U)
13697 #define USB_OTG_DSTS_ENUMSPD_Msk                 (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
13698 #define USB_OTG_DSTS_ENUMSPD                     USB_OTG_DSTS_ENUMSPD_Msk      /*!< Enumerated speed */
13699 #define USB_OTG_DSTS_ENUMSPD_0                   (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
13700 #define USB_OTG_DSTS_ENUMSPD_1                   (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
13701 #define USB_OTG_DSTS_EERR_Pos                    (3U)
13702 #define USB_OTG_DSTS_EERR_Msk                    (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
13703 #define USB_OTG_DSTS_EERR                        USB_OTG_DSTS_EERR_Msk         /*!< Erratic error     */
13704 #define USB_OTG_DSTS_FNSOF_Pos                   (8U)
13705 #define USB_OTG_DSTS_FNSOF_Msk                   (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
13706 #define USB_OTG_DSTS_FNSOF                       USB_OTG_DSTS_FNSOF_Msk        /*!< Frame number of the received SOF */
13707 
13708 /********************  Bit definition for USB_OTG_GAHBCFG register  ********************/
13709 #define USB_OTG_GAHBCFG_GINT_Pos                 (0U)
13710 #define USB_OTG_GAHBCFG_GINT_Msk                 (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
13711 #define USB_OTG_GAHBCFG_GINT                     USB_OTG_GAHBCFG_GINT_Msk      /*!< Global interrupt mask */
13712 #define USB_OTG_GAHBCFG_HBSTLEN_Pos              (1U)
13713 #define USB_OTG_GAHBCFG_HBSTLEN_Msk              (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
13714 #define USB_OTG_GAHBCFG_HBSTLEN                  USB_OTG_GAHBCFG_HBSTLEN_Msk   /*!< Burst length/type */
13715 #define USB_OTG_GAHBCFG_HBSTLEN_0                (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
13716 #define USB_OTG_GAHBCFG_HBSTLEN_1                (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
13717 #define USB_OTG_GAHBCFG_HBSTLEN_2                (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
13718 #define USB_OTG_GAHBCFG_HBSTLEN_3                (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
13719 #define USB_OTG_GAHBCFG_HBSTLEN_4                (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
13720 #define USB_OTG_GAHBCFG_DMAEN_Pos                (5U)
13721 #define USB_OTG_GAHBCFG_DMAEN_Msk                (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
13722 #define USB_OTG_GAHBCFG_DMAEN                    USB_OTG_GAHBCFG_DMAEN_Msk     /*!< DMA enable */
13723 #define USB_OTG_GAHBCFG_TXFELVL_Pos              (7U)
13724 #define USB_OTG_GAHBCFG_TXFELVL_Msk              (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
13725 #define USB_OTG_GAHBCFG_TXFELVL                  USB_OTG_GAHBCFG_TXFELVL_Msk   /*!< TxFIFO empty level */
13726 #define USB_OTG_GAHBCFG_PTXFELVL_Pos             (8U)
13727 #define USB_OTG_GAHBCFG_PTXFELVL_Msk             (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
13728 #define USB_OTG_GAHBCFG_PTXFELVL                 USB_OTG_GAHBCFG_PTXFELVL_Msk  /*!< Periodic TxFIFO empty level */
13729 
13730 /********************  Bit definition for USB_OTG_GUSBCFG register  ********************/
13731 
13732 #define USB_OTG_GUSBCFG_TOCAL_Pos                (0U)
13733 #define USB_OTG_GUSBCFG_TOCAL_Msk                (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
13734 #define USB_OTG_GUSBCFG_TOCAL                    USB_OTG_GUSBCFG_TOCAL_Msk     /*!< FS timeout calibration */
13735 #define USB_OTG_GUSBCFG_TOCAL_0                  (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
13736 #define USB_OTG_GUSBCFG_TOCAL_1                  (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
13737 #define USB_OTG_GUSBCFG_TOCAL_2                  (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
13738 #define USB_OTG_GUSBCFG_PHYSEL_Pos               (6U)
13739 #define USB_OTG_GUSBCFG_PHYSEL_Msk               (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
13740 #define USB_OTG_GUSBCFG_PHYSEL                   USB_OTG_GUSBCFG_PHYSEL_Msk    /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
13741 #define USB_OTG_GUSBCFG_SRPCAP_Pos               (8U)
13742 #define USB_OTG_GUSBCFG_SRPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
13743 #define USB_OTG_GUSBCFG_SRPCAP                   USB_OTG_GUSBCFG_SRPCAP_Msk    /*!< SRP-capable */
13744 #define USB_OTG_GUSBCFG_HNPCAP_Pos               (9U)
13745 #define USB_OTG_GUSBCFG_HNPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
13746 #define USB_OTG_GUSBCFG_HNPCAP                   USB_OTG_GUSBCFG_HNPCAP_Msk    /*!< HNP-capable */
13747 #define USB_OTG_GUSBCFG_TRDT_Pos                 (10U)
13748 #define USB_OTG_GUSBCFG_TRDT_Msk                 (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
13749 #define USB_OTG_GUSBCFG_TRDT                     USB_OTG_GUSBCFG_TRDT_Msk      /*!< USB turnaround time */
13750 #define USB_OTG_GUSBCFG_TRDT_0                   (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
13751 #define USB_OTG_GUSBCFG_TRDT_1                   (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
13752 #define USB_OTG_GUSBCFG_TRDT_2                   (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
13753 #define USB_OTG_GUSBCFG_TRDT_3                   (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
13754 #define USB_OTG_GUSBCFG_PHYLPCS_Pos              (15U)
13755 #define USB_OTG_GUSBCFG_PHYLPCS_Msk              (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
13756 #define USB_OTG_GUSBCFG_PHYLPCS                  USB_OTG_GUSBCFG_PHYLPCS_Msk   /*!< PHY Low-power clock select */
13757 #define USB_OTG_GUSBCFG_ULPIFSLS_Pos             (17U)
13758 #define USB_OTG_GUSBCFG_ULPIFSLS_Msk             (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
13759 #define USB_OTG_GUSBCFG_ULPIFSLS                 USB_OTG_GUSBCFG_ULPIFSLS_Msk  /*!< ULPI FS/LS select               */
13760 #define USB_OTG_GUSBCFG_ULPIAR_Pos               (18U)
13761 #define USB_OTG_GUSBCFG_ULPIAR_Msk               (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
13762 #define USB_OTG_GUSBCFG_ULPIAR                   USB_OTG_GUSBCFG_ULPIAR_Msk    /*!< ULPI Auto-resume                */
13763 #define USB_OTG_GUSBCFG_ULPICSM_Pos              (19U)
13764 #define USB_OTG_GUSBCFG_ULPICSM_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
13765 #define USB_OTG_GUSBCFG_ULPICSM                  USB_OTG_GUSBCFG_ULPICSM_Msk   /*!< ULPI Clock SuspendM             */
13766 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos           (20U)
13767 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
13768 #define USB_OTG_GUSBCFG_ULPIEVBUSD               USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive        */
13769 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos           (21U)
13770 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
13771 #define USB_OTG_GUSBCFG_ULPIEVBUSI               USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator    */
13772 #define USB_OTG_GUSBCFG_TSDPS_Pos                (22U)
13773 #define USB_OTG_GUSBCFG_TSDPS_Msk                (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
13774 #define USB_OTG_GUSBCFG_TSDPS                    USB_OTG_GUSBCFG_TSDPS_Msk     /*!< TermSel DLine pulsing selection */
13775 #define USB_OTG_GUSBCFG_PCCI_Pos                 (23U)
13776 #define USB_OTG_GUSBCFG_PCCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
13777 #define USB_OTG_GUSBCFG_PCCI                     USB_OTG_GUSBCFG_PCCI_Msk      /*!< Indicator complement            */
13778 #define USB_OTG_GUSBCFG_PTCI_Pos                 (24U)
13779 #define USB_OTG_GUSBCFG_PTCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
13780 #define USB_OTG_GUSBCFG_PTCI                     USB_OTG_GUSBCFG_PTCI_Msk      /*!< Indicator pass through          */
13781 #define USB_OTG_GUSBCFG_ULPIIPD_Pos              (25U)
13782 #define USB_OTG_GUSBCFG_ULPIIPD_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
13783 #define USB_OTG_GUSBCFG_ULPIIPD                  USB_OTG_GUSBCFG_ULPIIPD_Msk   /*!< ULPI interface protect disable  */
13784 #define USB_OTG_GUSBCFG_FHMOD_Pos                (29U)
13785 #define USB_OTG_GUSBCFG_FHMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
13786 #define USB_OTG_GUSBCFG_FHMOD                    USB_OTG_GUSBCFG_FHMOD_Msk     /*!< Forced host mode                */
13787 #define USB_OTG_GUSBCFG_FDMOD_Pos                (30U)
13788 #define USB_OTG_GUSBCFG_FDMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
13789 #define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode          */
13790 #define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)
13791 #define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
13792 #define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet               */
13793 
13794 /********************  Bit definition for USB_OTG_GRSTCTL register  ********************/
13795 #define USB_OTG_GRSTCTL_CSRST_Pos                (0U)
13796 #define USB_OTG_GRSTCTL_CSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
13797 #define USB_OTG_GRSTCTL_CSRST                    USB_OTG_GRSTCTL_CSRST_Msk     /*!< Core soft reset          */
13798 #define USB_OTG_GRSTCTL_HSRST_Pos                (1U)
13799 #define USB_OTG_GRSTCTL_HSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
13800 #define USB_OTG_GRSTCTL_HSRST                    USB_OTG_GRSTCTL_HSRST_Msk     /*!< HCLK soft reset          */
13801 #define USB_OTG_GRSTCTL_FCRST_Pos                (2U)
13802 #define USB_OTG_GRSTCTL_FCRST_Msk                (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
13803 #define USB_OTG_GRSTCTL_FCRST                    USB_OTG_GRSTCTL_FCRST_Msk     /*!< Host frame counter reset */
13804 #define USB_OTG_GRSTCTL_RXFFLSH_Pos              (4U)
13805 #define USB_OTG_GRSTCTL_RXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
13806 #define USB_OTG_GRSTCTL_RXFFLSH                  USB_OTG_GRSTCTL_RXFFLSH_Msk   /*!< RxFIFO flush             */
13807 #define USB_OTG_GRSTCTL_TXFFLSH_Pos              (5U)
13808 #define USB_OTG_GRSTCTL_TXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
13809 #define USB_OTG_GRSTCTL_TXFFLSH                  USB_OTG_GRSTCTL_TXFFLSH_Msk   /*!< TxFIFO flush             */
13810 
13811 
13812 #define USB_OTG_GRSTCTL_TXFNUM_Pos               (6U)
13813 #define USB_OTG_GRSTCTL_TXFNUM_Msk               (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
13814 #define USB_OTG_GRSTCTL_TXFNUM                   USB_OTG_GRSTCTL_TXFNUM_Msk    /*!< TxFIFO number */
13815 #define USB_OTG_GRSTCTL_TXFNUM_0                 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
13816 #define USB_OTG_GRSTCTL_TXFNUM_1                 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
13817 #define USB_OTG_GRSTCTL_TXFNUM_2                 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
13818 #define USB_OTG_GRSTCTL_TXFNUM_3                 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
13819 #define USB_OTG_GRSTCTL_TXFNUM_4                 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
13820 #define USB_OTG_GRSTCTL_DMAREQ_Pos               (30U)
13821 #define USB_OTG_GRSTCTL_DMAREQ_Msk               (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
13822 #define USB_OTG_GRSTCTL_DMAREQ                   USB_OTG_GRSTCTL_DMAREQ_Msk    /*!< DMA request signal */
13823 #define USB_OTG_GRSTCTL_AHBIDL_Pos               (31U)
13824 #define USB_OTG_GRSTCTL_AHBIDL_Msk               (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
13825 #define USB_OTG_GRSTCTL_AHBIDL                   USB_OTG_GRSTCTL_AHBIDL_Msk    /*!< AHB master idle */
13826 
13827 /********************  Bit definition for USB_OTG_DIEPMSK register  ********************/
13828 #define USB_OTG_DIEPMSK_XFRCM_Pos                (0U)
13829 #define USB_OTG_DIEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
13830 #define USB_OTG_DIEPMSK_XFRCM                    USB_OTG_DIEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask                 */
13831 #define USB_OTG_DIEPMSK_EPDM_Pos                 (1U)
13832 #define USB_OTG_DIEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
13833 #define USB_OTG_DIEPMSK_EPDM                     USB_OTG_DIEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask                  */
13834 #define USB_OTG_DIEPMSK_TOM_Pos                  (3U)
13835 #define USB_OTG_DIEPMSK_TOM_Msk                  (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
13836 #define USB_OTG_DIEPMSK_TOM                      USB_OTG_DIEPMSK_TOM_Msk       /*!< Timeout condition mask (nonisochronous endpoints) */
13837 #define USB_OTG_DIEPMSK_ITTXFEMSK_Pos            (4U)
13838 #define USB_OTG_DIEPMSK_ITTXFEMSK_Msk            (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
13839 #define USB_OTG_DIEPMSK_ITTXFEMSK                USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */
13840 #define USB_OTG_DIEPMSK_INEPNMM_Pos              (5U)
13841 #define USB_OTG_DIEPMSK_INEPNMM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
13842 #define USB_OTG_DIEPMSK_INEPNMM                  USB_OTG_DIEPMSK_INEPNMM_Msk   /*!< IN token received with EP mismatch mask           */
13843 #define USB_OTG_DIEPMSK_INEPNEM_Pos              (6U)
13844 #define USB_OTG_DIEPMSK_INEPNEM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
13845 #define USB_OTG_DIEPMSK_INEPNEM                  USB_OTG_DIEPMSK_INEPNEM_Msk   /*!< IN endpoint NAK effective mask                    */
13846 #define USB_OTG_DIEPMSK_TXFURM_Pos               (8U)
13847 #define USB_OTG_DIEPMSK_TXFURM_Msk               (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
13848 #define USB_OTG_DIEPMSK_TXFURM                   USB_OTG_DIEPMSK_TXFURM_Msk    /*!< FIFO underrun mask                                */
13849 #define USB_OTG_DIEPMSK_BIM_Pos                  (9U)
13850 #define USB_OTG_DIEPMSK_BIM_Msk                  (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
13851 #define USB_OTG_DIEPMSK_BIM                      USB_OTG_DIEPMSK_BIM_Msk       /*!< BNA interrupt mask                                */
13852 
13853 /********************  Bit definition for USB_OTG_HPTXSTS register  ********************/
13854 #define USB_OTG_HPTXSTS_PTXFSAVL_Pos             (0U)
13855 #define USB_OTG_HPTXSTS_PTXFSAVL_Msk             (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
13856 #define USB_OTG_HPTXSTS_PTXFSAVL                 USB_OTG_HPTXSTS_PTXFSAVL_Msk  /*!< Periodic transmit data FIFO space available     */
13857 #define USB_OTG_HPTXSTS_PTXQSAV_Pos              (16U)
13858 #define USB_OTG_HPTXSTS_PTXQSAV_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
13859 #define USB_OTG_HPTXSTS_PTXQSAV                  USB_OTG_HPTXSTS_PTXQSAV_Msk   /*!< Periodic transmit request queue space available */
13860 #define USB_OTG_HPTXSTS_PTXQSAV_0                (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
13861 #define USB_OTG_HPTXSTS_PTXQSAV_1                (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
13862 #define USB_OTG_HPTXSTS_PTXQSAV_2                (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
13863 #define USB_OTG_HPTXSTS_PTXQSAV_3                (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
13864 #define USB_OTG_HPTXSTS_PTXQSAV_4                (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
13865 #define USB_OTG_HPTXSTS_PTXQSAV_5                (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
13866 #define USB_OTG_HPTXSTS_PTXQSAV_6                (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
13867 #define USB_OTG_HPTXSTS_PTXQSAV_7                (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
13868 
13869 #define USB_OTG_HPTXSTS_PTXQTOP_Pos              (24U)
13870 #define USB_OTG_HPTXSTS_PTXQTOP_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
13871 #define USB_OTG_HPTXSTS_PTXQTOP                  USB_OTG_HPTXSTS_PTXQTOP_Msk   /*!< Top of the periodic transmit request queue */
13872 #define USB_OTG_HPTXSTS_PTXQTOP_0                (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
13873 #define USB_OTG_HPTXSTS_PTXQTOP_1                (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
13874 #define USB_OTG_HPTXSTS_PTXQTOP_2                (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
13875 #define USB_OTG_HPTXSTS_PTXQTOP_3                (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
13876 #define USB_OTG_HPTXSTS_PTXQTOP_4                (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
13877 #define USB_OTG_HPTXSTS_PTXQTOP_5                (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
13878 #define USB_OTG_HPTXSTS_PTXQTOP_6                (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
13879 #define USB_OTG_HPTXSTS_PTXQTOP_7                (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
13880 
13881 /********************  Bit definition for USB_OTG_HAINT register  ********************/
13882 #define USB_OTG_HAINT_HAINT_Pos                  (0U)
13883 #define USB_OTG_HAINT_HAINT_Msk                  (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
13884 #define USB_OTG_HAINT_HAINT                      USB_OTG_HAINT_HAINT_Msk       /*!< Channel interrupts */
13885 
13886 /********************  Bit definition for USB_OTG_DOEPMSK register  ********************/
13887 #define USB_OTG_DOEPMSK_XFRCM_Pos                (0U)
13888 #define USB_OTG_DOEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
13889 #define USB_OTG_DOEPMSK_XFRCM                    USB_OTG_DOEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask              */
13890 #define USB_OTG_DOEPMSK_EPDM_Pos                 (1U)
13891 #define USB_OTG_DOEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
13892 #define USB_OTG_DOEPMSK_EPDM                     USB_OTG_DOEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask               */
13893 #define USB_OTG_DOEPMSK_AHBERRM_Pos              (2U)
13894 #define USB_OTG_DOEPMSK_AHBERRM_Msk              (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */
13895 #define USB_OTG_DOEPMSK_AHBERRM                  USB_OTG_DOEPMSK_AHBERRM_Msk   /*!< OUT transaction AHB Error interrupt mask       */
13896 #define USB_OTG_DOEPMSK_STUPM_Pos                (3U)
13897 #define USB_OTG_DOEPMSK_STUPM_Msk                (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
13898 #define USB_OTG_DOEPMSK_STUPM                    USB_OTG_DOEPMSK_STUPM_Msk     /*!< SETUP phase done mask                          */
13899 #define USB_OTG_DOEPMSK_OTEPDM_Pos               (4U)
13900 #define USB_OTG_DOEPMSK_OTEPDM_Msk               (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
13901 #define USB_OTG_DOEPMSK_OTEPDM                   USB_OTG_DOEPMSK_OTEPDM_Msk    /*!< OUT token received when endpoint disabled mask */
13902 #define USB_OTG_DOEPMSK_OTEPSPRM_Pos             (5U)
13903 #define USB_OTG_DOEPMSK_OTEPSPRM_Msk             (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */
13904 #define USB_OTG_DOEPMSK_OTEPSPRM                 USB_OTG_DOEPMSK_OTEPSPRM_Msk  /*!< Status Phase Received mask                     */
13905 #define USB_OTG_DOEPMSK_B2BSTUP_Pos              (6U)
13906 #define USB_OTG_DOEPMSK_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
13907 #define USB_OTG_DOEPMSK_B2BSTUP                  USB_OTG_DOEPMSK_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received mask       */
13908 #define USB_OTG_DOEPMSK_OPEM_Pos                 (8U)
13909 #define USB_OTG_DOEPMSK_OPEM_Msk                 (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
13910 #define USB_OTG_DOEPMSK_OPEM                     USB_OTG_DOEPMSK_OPEM_Msk      /*!< OUT packet error mask                          */
13911 #define USB_OTG_DOEPMSK_BOIM_Pos                 (9U)
13912 #define USB_OTG_DOEPMSK_BOIM_Msk                 (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
13913 #define USB_OTG_DOEPMSK_BOIM                     USB_OTG_DOEPMSK_BOIM_Msk      /*!< BNA interrupt mask                             */
13914 #define USB_OTG_DOEPMSK_BERRM_Pos                (12U)
13915 #define USB_OTG_DOEPMSK_BERRM_Msk                (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */
13916 #define USB_OTG_DOEPMSK_BERRM                    USB_OTG_DOEPMSK_BERRM_Msk      /*!< Babble error interrupt mask                   */
13917 #define USB_OTG_DOEPMSK_NAKM_Pos                 (13U)
13918 #define USB_OTG_DOEPMSK_NAKM_Msk                 (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */
13919 #define USB_OTG_DOEPMSK_NAKM                     USB_OTG_DOEPMSK_NAKM_Msk      /*!< OUT Packet NAK interrupt mask                  */
13920 #define USB_OTG_DOEPMSK_NYETM_Pos                (14U)
13921 #define USB_OTG_DOEPMSK_NYETM_Msk                (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */
13922 #define USB_OTG_DOEPMSK_NYETM                    USB_OTG_DOEPMSK_NYETM_Msk     /*!< NYET interrupt mask                            */
13923 /********************  Bit definition for USB_OTG_GINTSTS register  ********************/
13924 #define USB_OTG_GINTSTS_CMOD_Pos                 (0U)
13925 #define USB_OTG_GINTSTS_CMOD_Msk                 (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
13926 #define USB_OTG_GINTSTS_CMOD                     USB_OTG_GINTSTS_CMOD_Msk      /*!< Current mode of operation                      */
13927 #define USB_OTG_GINTSTS_MMIS_Pos                 (1U)
13928 #define USB_OTG_GINTSTS_MMIS_Msk                 (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
13929 #define USB_OTG_GINTSTS_MMIS                     USB_OTG_GINTSTS_MMIS_Msk      /*!< Mode mismatch interrupt                        */
13930 #define USB_OTG_GINTSTS_OTGINT_Pos               (2U)
13931 #define USB_OTG_GINTSTS_OTGINT_Msk               (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
13932 #define USB_OTG_GINTSTS_OTGINT                   USB_OTG_GINTSTS_OTGINT_Msk    /*!< OTG interrupt                                  */
13933 #define USB_OTG_GINTSTS_SOF_Pos                  (3U)
13934 #define USB_OTG_GINTSTS_SOF_Msk                  (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
13935 #define USB_OTG_GINTSTS_SOF                      USB_OTG_GINTSTS_SOF_Msk       /*!< Start of frame                                 */
13936 #define USB_OTG_GINTSTS_RXFLVL_Pos               (4U)
13937 #define USB_OTG_GINTSTS_RXFLVL_Msk               (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
13938 #define USB_OTG_GINTSTS_RXFLVL                   USB_OTG_GINTSTS_RXFLVL_Msk    /*!< RxFIFO nonempty                                */
13939 #define USB_OTG_GINTSTS_NPTXFE_Pos               (5U)
13940 #define USB_OTG_GINTSTS_NPTXFE_Msk               (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
13941 #define USB_OTG_GINTSTS_NPTXFE                   USB_OTG_GINTSTS_NPTXFE_Msk    /*!< Nonperiodic TxFIFO empty                       */
13942 #define USB_OTG_GINTSTS_GINAKEFF_Pos             (6U)
13943 #define USB_OTG_GINTSTS_GINAKEFF_Msk             (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
13944 #define USB_OTG_GINTSTS_GINAKEFF                 USB_OTG_GINTSTS_GINAKEFF_Msk  /*!< Global IN nonperiodic NAK effective            */
13945 #define USB_OTG_GINTSTS_BOUTNAKEFF_Pos           (7U)
13946 #define USB_OTG_GINTSTS_BOUTNAKEFF_Msk           (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
13947 #define USB_OTG_GINTSTS_BOUTNAKEFF               USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective                       */
13948 #define USB_OTG_GINTSTS_ESUSP_Pos                (10U)
13949 #define USB_OTG_GINTSTS_ESUSP_Msk                (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
13950 #define USB_OTG_GINTSTS_ESUSP                    USB_OTG_GINTSTS_ESUSP_Msk     /*!< Early suspend                                  */
13951 #define USB_OTG_GINTSTS_USBSUSP_Pos              (11U)
13952 #define USB_OTG_GINTSTS_USBSUSP_Msk              (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
13953 #define USB_OTG_GINTSTS_USBSUSP                  USB_OTG_GINTSTS_USBSUSP_Msk   /*!< USB suspend                                    */
13954 #define USB_OTG_GINTSTS_USBRST_Pos               (12U)
13955 #define USB_OTG_GINTSTS_USBRST_Msk               (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
13956 #define USB_OTG_GINTSTS_USBRST                   USB_OTG_GINTSTS_USBRST_Msk    /*!< USB reset                                      */
13957 #define USB_OTG_GINTSTS_ENUMDNE_Pos              (13U)
13958 #define USB_OTG_GINTSTS_ENUMDNE_Msk              (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
13959 #define USB_OTG_GINTSTS_ENUMDNE                  USB_OTG_GINTSTS_ENUMDNE_Msk   /*!< Enumeration done                               */
13960 #define USB_OTG_GINTSTS_ISOODRP_Pos              (14U)
13961 #define USB_OTG_GINTSTS_ISOODRP_Msk              (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
13962 #define USB_OTG_GINTSTS_ISOODRP                  USB_OTG_GINTSTS_ISOODRP_Msk   /*!< Isochronous OUT packet dropped interrupt       */
13963 #define USB_OTG_GINTSTS_EOPF_Pos                 (15U)
13964 #define USB_OTG_GINTSTS_EOPF_Msk                 (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
13965 #define USB_OTG_GINTSTS_EOPF                     USB_OTG_GINTSTS_EOPF_Msk      /*!< End of periodic frame interrupt                */
13966 #define USB_OTG_GINTSTS_IEPINT_Pos               (18U)
13967 #define USB_OTG_GINTSTS_IEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
13968 #define USB_OTG_GINTSTS_IEPINT                   USB_OTG_GINTSTS_IEPINT_Msk    /*!< IN endpoint interrupt                          */
13969 #define USB_OTG_GINTSTS_OEPINT_Pos               (19U)
13970 #define USB_OTG_GINTSTS_OEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
13971 #define USB_OTG_GINTSTS_OEPINT                   USB_OTG_GINTSTS_OEPINT_Msk    /*!< OUT endpoint interrupt                         */
13972 #define USB_OTG_GINTSTS_IISOIXFR_Pos             (20U)
13973 #define USB_OTG_GINTSTS_IISOIXFR_Msk             (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
13974 #define USB_OTG_GINTSTS_IISOIXFR                 USB_OTG_GINTSTS_IISOIXFR_Msk  /*!< Incomplete isochronous IN transfer             */
13975 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos    (21U)
13976 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk    (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
13977 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT        USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer                   */
13978 #define USB_OTG_GINTSTS_DATAFSUSP_Pos            (22U)
13979 #define USB_OTG_GINTSTS_DATAFSUSP_Msk            (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
13980 #define USB_OTG_GINTSTS_DATAFSUSP                USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended                           */
13981 #define USB_OTG_GINTSTS_RSTDET_Pos               (23U)
13982 #define USB_OTG_GINTSTS_RSTDET_Msk               (0x1UL << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */
13983 #define USB_OTG_GINTSTS_RSTDET                   USB_OTG_GINTSTS_RSTDET_Msk    /*!< Reset detected interrupt                       */
13984 #define USB_OTG_GINTSTS_HPRTINT_Pos              (24U)
13985 #define USB_OTG_GINTSTS_HPRTINT_Msk              (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
13986 #define USB_OTG_GINTSTS_HPRTINT                  USB_OTG_GINTSTS_HPRTINT_Msk   /*!< Host port interrupt                            */
13987 #define USB_OTG_GINTSTS_HCINT_Pos                (25U)
13988 #define USB_OTG_GINTSTS_HCINT_Msk                (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
13989 #define USB_OTG_GINTSTS_HCINT                    USB_OTG_GINTSTS_HCINT_Msk     /*!< Host channels interrupt                        */
13990 #define USB_OTG_GINTSTS_PTXFE_Pos                (26U)
13991 #define USB_OTG_GINTSTS_PTXFE_Msk                (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
13992 #define USB_OTG_GINTSTS_PTXFE                    USB_OTG_GINTSTS_PTXFE_Msk     /*!< Periodic TxFIFO empty                          */
13993 #define USB_OTG_GINTSTS_LPMINT_Pos               (27U)
13994 #define USB_OTG_GINTSTS_LPMINT_Msk               (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */
13995 #define USB_OTG_GINTSTS_LPMINT                   USB_OTG_GINTSTS_LPMINT_Msk    /*!< LPM interrupt                                  */
13996 #define USB_OTG_GINTSTS_CIDSCHG_Pos              (28U)
13997 #define USB_OTG_GINTSTS_CIDSCHG_Msk              (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
13998 #define USB_OTG_GINTSTS_CIDSCHG                  USB_OTG_GINTSTS_CIDSCHG_Msk   /*!< Connector ID status change                     */
13999 #define USB_OTG_GINTSTS_DISCINT_Pos              (29U)
14000 #define USB_OTG_GINTSTS_DISCINT_Msk              (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
14001 #define USB_OTG_GINTSTS_DISCINT                  USB_OTG_GINTSTS_DISCINT_Msk   /*!< Disconnect detected interrupt                  */
14002 #define USB_OTG_GINTSTS_SRQINT_Pos               (30U)
14003 #define USB_OTG_GINTSTS_SRQINT_Msk               (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
14004 #define USB_OTG_GINTSTS_SRQINT                   USB_OTG_GINTSTS_SRQINT_Msk    /*!< Session request/new session detected interrupt */
14005 #define USB_OTG_GINTSTS_WKUINT_Pos               (31U)
14006 #define USB_OTG_GINTSTS_WKUINT_Msk               (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
14007 #define USB_OTG_GINTSTS_WKUINT                   USB_OTG_GINTSTS_WKUINT_Msk    /*!< Resume/remote wakeup detected interrupt        */
14008 
14009 /********************  Bit definition for USB_OTG_GINTMSK register  ********************/
14010 #define USB_OTG_GINTMSK_MMISM_Pos                (1U)
14011 #define USB_OTG_GINTMSK_MMISM_Msk                (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
14012 #define USB_OTG_GINTMSK_MMISM                    USB_OTG_GINTMSK_MMISM_Msk     /*!< Mode mismatch interrupt mask                        */
14013 #define USB_OTG_GINTMSK_OTGINT_Pos               (2U)
14014 #define USB_OTG_GINTMSK_OTGINT_Msk               (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
14015 #define USB_OTG_GINTMSK_OTGINT                   USB_OTG_GINTMSK_OTGINT_Msk    /*!< OTG interrupt mask                                  */
14016 #define USB_OTG_GINTMSK_SOFM_Pos                 (3U)
14017 #define USB_OTG_GINTMSK_SOFM_Msk                 (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
14018 #define USB_OTG_GINTMSK_SOFM                     USB_OTG_GINTMSK_SOFM_Msk      /*!< Start of frame mask                                 */
14019 #define USB_OTG_GINTMSK_RXFLVLM_Pos              (4U)
14020 #define USB_OTG_GINTMSK_RXFLVLM_Msk              (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
14021 #define USB_OTG_GINTMSK_RXFLVLM                  USB_OTG_GINTMSK_RXFLVLM_Msk   /*!< Receive FIFO nonempty mask                          */
14022 #define USB_OTG_GINTMSK_NPTXFEM_Pos              (5U)
14023 #define USB_OTG_GINTMSK_NPTXFEM_Msk              (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
14024 #define USB_OTG_GINTMSK_NPTXFEM                  USB_OTG_GINTMSK_NPTXFEM_Msk   /*!< Nonperiodic TxFIFO empty mask                       */
14025 #define USB_OTG_GINTMSK_GINAKEFFM_Pos            (6U)
14026 #define USB_OTG_GINTMSK_GINAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
14027 #define USB_OTG_GINTMSK_GINAKEFFM                USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask            */
14028 #define USB_OTG_GINTMSK_GONAKEFFM_Pos            (7U)
14029 #define USB_OTG_GINTMSK_GONAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
14030 #define USB_OTG_GINTMSK_GONAKEFFM                USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask                       */
14031 #define USB_OTG_GINTMSK_ESUSPM_Pos               (10U)
14032 #define USB_OTG_GINTMSK_ESUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
14033 #define USB_OTG_GINTMSK_ESUSPM                   USB_OTG_GINTMSK_ESUSPM_Msk    /*!< Early suspend mask                                  */
14034 #define USB_OTG_GINTMSK_USBSUSPM_Pos             (11U)
14035 #define USB_OTG_GINTMSK_USBSUSPM_Msk             (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
14036 #define USB_OTG_GINTMSK_USBSUSPM                 USB_OTG_GINTMSK_USBSUSPM_Msk  /*!< USB suspend mask                                    */
14037 #define USB_OTG_GINTMSK_USBRST_Pos               (12U)
14038 #define USB_OTG_GINTMSK_USBRST_Msk               (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
14039 #define USB_OTG_GINTMSK_USBRST                   USB_OTG_GINTMSK_USBRST_Msk    /*!< USB reset mask                                      */
14040 #define USB_OTG_GINTMSK_ENUMDNEM_Pos             (13U)
14041 #define USB_OTG_GINTMSK_ENUMDNEM_Msk             (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
14042 #define USB_OTG_GINTMSK_ENUMDNEM                 USB_OTG_GINTMSK_ENUMDNEM_Msk  /*!< Enumeration done mask                               */
14043 #define USB_OTG_GINTMSK_ISOODRPM_Pos             (14U)
14044 #define USB_OTG_GINTMSK_ISOODRPM_Msk             (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
14045 #define USB_OTG_GINTMSK_ISOODRPM                 USB_OTG_GINTMSK_ISOODRPM_Msk  /*!< Isochronous OUT packet dropped interrupt mask       */
14046 #define USB_OTG_GINTMSK_EOPFM_Pos                (15U)
14047 #define USB_OTG_GINTMSK_EOPFM_Msk                (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
14048 #define USB_OTG_GINTMSK_EOPFM                    USB_OTG_GINTMSK_EOPFM_Msk     /*!< End of periodic frame interrupt mask                */
14049 #define USB_OTG_GINTMSK_EPMISM_Pos               (17U)
14050 #define USB_OTG_GINTMSK_EPMISM_Msk               (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
14051 #define USB_OTG_GINTMSK_EPMISM                   USB_OTG_GINTMSK_EPMISM_Msk    /*!< Endpoint mismatch interrupt mask                    */
14052 #define USB_OTG_GINTMSK_IEPINT_Pos               (18U)
14053 #define USB_OTG_GINTMSK_IEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
14054 #define USB_OTG_GINTMSK_IEPINT                   USB_OTG_GINTMSK_IEPINT_Msk    /*!< IN endpoints interrupt mask                         */
14055 #define USB_OTG_GINTMSK_OEPINT_Pos               (19U)
14056 #define USB_OTG_GINTMSK_OEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
14057 #define USB_OTG_GINTMSK_OEPINT                   USB_OTG_GINTMSK_OEPINT_Msk    /*!< OUT endpoints interrupt mask                        */
14058 #define USB_OTG_GINTMSK_IISOIXFRM_Pos            (20U)
14059 #define USB_OTG_GINTMSK_IISOIXFRM_Msk            (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
14060 #define USB_OTG_GINTMSK_IISOIXFRM                USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask             */
14061 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos      (21U)
14062 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk      (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
14063 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM          USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask                   */
14064 #define USB_OTG_GINTMSK_FSUSPM_Pos               (22U)
14065 #define USB_OTG_GINTMSK_FSUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
14066 #define USB_OTG_GINTMSK_FSUSPM                   USB_OTG_GINTMSK_FSUSPM_Msk    /*!< Data fetch suspended mask                           */
14067 #define USB_OTG_GINTMSK_RSTDETM_Pos              (23U)
14068 #define USB_OTG_GINTMSK_RSTDETM_Msk              (0x1UL << USB_OTG_GINTMSK_RSTDETM_Pos) /*!< 0x00800000 */
14069 #define USB_OTG_GINTMSK_RSTDETM                  USB_OTG_GINTMSK_RSTDETM_Msk   /*!< Reset detected interrupt mask */
14070 #define USB_OTG_GINTMSK_PRTIM_Pos                (24U)
14071 #define USB_OTG_GINTMSK_PRTIM_Msk                (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
14072 #define USB_OTG_GINTMSK_PRTIM                    USB_OTG_GINTMSK_PRTIM_Msk     /*!< Host port interrupt mask                            */
14073 #define USB_OTG_GINTMSK_HCIM_Pos                 (25U)
14074 #define USB_OTG_GINTMSK_HCIM_Msk                 (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
14075 #define USB_OTG_GINTMSK_HCIM                     USB_OTG_GINTMSK_HCIM_Msk      /*!< Host channels interrupt mask                        */
14076 #define USB_OTG_GINTMSK_PTXFEM_Pos               (26U)
14077 #define USB_OTG_GINTMSK_PTXFEM_Msk               (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
14078 #define USB_OTG_GINTMSK_PTXFEM                   USB_OTG_GINTMSK_PTXFEM_Msk    /*!< Periodic TxFIFO empty mask                          */
14079 #define USB_OTG_GINTMSK_LPMINTM_Pos              (27U)
14080 #define USB_OTG_GINTMSK_LPMINTM_Msk              (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */
14081 #define USB_OTG_GINTMSK_LPMINTM                  USB_OTG_GINTMSK_LPMINTM_Msk   /*!< LPM interrupt Mask                                  */
14082 #define USB_OTG_GINTMSK_CIDSCHGM_Pos             (28U)
14083 #define USB_OTG_GINTMSK_CIDSCHGM_Msk             (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
14084 #define USB_OTG_GINTMSK_CIDSCHGM                 USB_OTG_GINTMSK_CIDSCHGM_Msk  /*!< Connector ID status change mask                     */
14085 #define USB_OTG_GINTMSK_DISCINT_Pos              (29U)
14086 #define USB_OTG_GINTMSK_DISCINT_Msk              (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
14087 #define USB_OTG_GINTMSK_DISCINT                  USB_OTG_GINTMSK_DISCINT_Msk   /*!< Disconnect detected interrupt mask                  */
14088 #define USB_OTG_GINTMSK_SRQIM_Pos                (30U)
14089 #define USB_OTG_GINTMSK_SRQIM_Msk                (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
14090 #define USB_OTG_GINTMSK_SRQIM                    USB_OTG_GINTMSK_SRQIM_Msk     /*!< Session request/new session detected interrupt mask */
14091 #define USB_OTG_GINTMSK_WUIM_Pos                 (31U)
14092 #define USB_OTG_GINTMSK_WUIM_Msk                 (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
14093 #define USB_OTG_GINTMSK_WUIM                     USB_OTG_GINTMSK_WUIM_Msk      /*!< Resume/remote wakeup detected interrupt mask        */
14094 
14095 /********************  Bit definition for USB_OTG_DAINT register  ********************/
14096 #define USB_OTG_DAINT_IEPINT_Pos                 (0U)
14097 #define USB_OTG_DAINT_IEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
14098 #define USB_OTG_DAINT_IEPINT                     USB_OTG_DAINT_IEPINT_Msk      /*!< IN endpoint interrupt bits  */
14099 #define USB_OTG_DAINT_OEPINT_Pos                 (16U)
14100 #define USB_OTG_DAINT_OEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
14101 #define USB_OTG_DAINT_OEPINT                     USB_OTG_DAINT_OEPINT_Msk      /*!< OUT endpoint interrupt bits */
14102 
14103 /********************  Bit definition for USB_OTG_HAINTMSK register  ********************/
14104 #define USB_OTG_HAINTMSK_HAINTM_Pos              (0U)
14105 #define USB_OTG_HAINTMSK_HAINTM_Msk              (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
14106 #define USB_OTG_HAINTMSK_HAINTM                  USB_OTG_HAINTMSK_HAINTM_Msk   /*!< Channel interrupt mask */
14107 
14108 /********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
14109 #define USB_OTG_GRXSTSP_EPNUM_Pos                (0U)
14110 #define USB_OTG_GRXSTSP_EPNUM_Msk                (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
14111 #define USB_OTG_GRXSTSP_EPNUM                    USB_OTG_GRXSTSP_EPNUM_Msk     /*!< IN EP interrupt mask bits  */
14112 #define USB_OTG_GRXSTSP_BCNT_Pos                 (4U)
14113 #define USB_OTG_GRXSTSP_BCNT_Msk                 (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
14114 #define USB_OTG_GRXSTSP_BCNT                     USB_OTG_GRXSTSP_BCNT_Msk      /*!< OUT EP interrupt mask bits */
14115 #define USB_OTG_GRXSTSP_DPID_Pos                 (15U)
14116 #define USB_OTG_GRXSTSP_DPID_Msk                 (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
14117 #define USB_OTG_GRXSTSP_DPID                     USB_OTG_GRXSTSP_DPID_Msk      /*!< OUT EP interrupt mask bits */
14118 #define USB_OTG_GRXSTSP_PKTSTS_Pos               (17U)
14119 #define USB_OTG_GRXSTSP_PKTSTS_Msk               (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
14120 #define USB_OTG_GRXSTSP_PKTSTS                   USB_OTG_GRXSTSP_PKTSTS_Msk    /*!< OUT EP interrupt mask bits */
14121 
14122 /********************  Bit definition for USB_OTG_DAINTMSK register  ********************/
14123 #define USB_OTG_DAINTMSK_IEPM_Pos                (0U)
14124 #define USB_OTG_DAINTMSK_IEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
14125 #define USB_OTG_DAINTMSK_IEPM                    USB_OTG_DAINTMSK_IEPM_Msk     /*!< IN EP interrupt mask bits */
14126 #define USB_OTG_DAINTMSK_OEPM_Pos                (16U)
14127 #define USB_OTG_DAINTMSK_OEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
14128 #define USB_OTG_DAINTMSK_OEPM                    USB_OTG_DAINTMSK_OEPM_Msk     /*!< OUT EP interrupt mask bits */
14129 
14130 /********************  Bit definition for USB_OTG_GRXFSIZ register  ********************/
14131 #define USB_OTG_GRXFSIZ_RXFD_Pos                 (0U)
14132 #define USB_OTG_GRXFSIZ_RXFD_Msk                 (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
14133 #define USB_OTG_GRXFSIZ_RXFD                     USB_OTG_GRXFSIZ_RXFD_Msk      /*!< RxFIFO depth */
14134 
14135 /********************  Bit definition for USB_OTG_DVBUSDIS register  ********************/
14136 #define USB_OTG_DVBUSDIS_VBUSDT_Pos              (0U)
14137 #define USB_OTG_DVBUSDIS_VBUSDT_Msk              (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
14138 #define USB_OTG_DVBUSDIS_VBUSDT                  USB_OTG_DVBUSDIS_VBUSDT_Msk   /*!< Device VBUS discharge time */
14139 
14140 /********************  Bit definition for OTG register  ********************/
14141 #define USB_OTG_NPTXFSA_Pos                      (0U)
14142 #define USB_OTG_NPTXFSA_Msk                      (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
14143 #define USB_OTG_NPTXFSA                          USB_OTG_NPTXFSA_Msk           /*!< Nonperiodic transmit RAM start address */
14144 #define USB_OTG_NPTXFD_Pos                       (16U)
14145 #define USB_OTG_NPTXFD_Msk                       (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
14146 #define USB_OTG_NPTXFD                           USB_OTG_NPTXFD_Msk            /*!< Nonperiodic TxFIFO depth               */
14147 #define USB_OTG_TX0FSA_Pos                       (0U)
14148 #define USB_OTG_TX0FSA_Msk                       (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
14149 #define USB_OTG_TX0FSA                           USB_OTG_TX0FSA_Msk            /*!< Endpoint 0 transmit RAM start address  */
14150 #define USB_OTG_TX0FD_Pos                        (16U)
14151 #define USB_OTG_TX0FD_Msk                        (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
14152 #define USB_OTG_TX0FD                            USB_OTG_TX0FD_Msk             /*!< Endpoint 0 TxFIFO depth                */
14153 
14154 /********************  Bit definition forUSB_OTG_DVBUSPULSE register  ********************/
14155 #define USB_OTG_DVBUSPULSE_DVBUSP_Pos            (0U)
14156 #define USB_OTG_DVBUSPULSE_DVBUSP_Msk            (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
14157 #define USB_OTG_DVBUSPULSE_DVBUSP                USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
14158 
14159 /********************  Bit definition for USB_OTG_GNPTXSTS register  ********************/
14160 #define USB_OTG_GNPTXSTS_NPTXFSAV_Pos            (0U)
14161 #define USB_OTG_GNPTXSTS_NPTXFSAV_Msk            (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
14162 #define USB_OTG_GNPTXSTS_NPTXFSAV                USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
14163 
14164 #define USB_OTG_GNPTXSTS_NPTQXSAV_Pos            (16U)
14165 #define USB_OTG_GNPTXSTS_NPTQXSAV_Msk            (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
14166 #define USB_OTG_GNPTXSTS_NPTQXSAV                USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
14167 #define USB_OTG_GNPTXSTS_NPTQXSAV_0              (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
14168 #define USB_OTG_GNPTXSTS_NPTQXSAV_1              (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
14169 #define USB_OTG_GNPTXSTS_NPTQXSAV_2              (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
14170 #define USB_OTG_GNPTXSTS_NPTQXSAV_3              (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
14171 #define USB_OTG_GNPTXSTS_NPTQXSAV_4              (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
14172 #define USB_OTG_GNPTXSTS_NPTQXSAV_5              (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
14173 #define USB_OTG_GNPTXSTS_NPTQXSAV_6              (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
14174 #define USB_OTG_GNPTXSTS_NPTQXSAV_7              (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
14175 
14176 #define USB_OTG_GNPTXSTS_NPTXQTOP_Pos            (24U)
14177 #define USB_OTG_GNPTXSTS_NPTXQTOP_Msk            (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
14178 #define USB_OTG_GNPTXSTS_NPTXQTOP                USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
14179 #define USB_OTG_GNPTXSTS_NPTXQTOP_0              (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
14180 #define USB_OTG_GNPTXSTS_NPTXQTOP_1              (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
14181 #define USB_OTG_GNPTXSTS_NPTXQTOP_2              (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
14182 #define USB_OTG_GNPTXSTS_NPTXQTOP_3              (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
14183 #define USB_OTG_GNPTXSTS_NPTXQTOP_4              (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
14184 #define USB_OTG_GNPTXSTS_NPTXQTOP_5              (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
14185 #define USB_OTG_GNPTXSTS_NPTXQTOP_6              (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
14186 
14187 /********************  Bit definition for USB_OTG_DTHRCTL register  ********************/
14188 #define USB_OTG_DTHRCTL_NONISOTHREN_Pos          (0U)
14189 #define USB_OTG_DTHRCTL_NONISOTHREN_Msk          (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
14190 #define USB_OTG_DTHRCTL_NONISOTHREN              USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
14191 #define USB_OTG_DTHRCTL_ISOTHREN_Pos             (1U)
14192 #define USB_OTG_DTHRCTL_ISOTHREN_Msk             (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
14193 #define USB_OTG_DTHRCTL_ISOTHREN                 USB_OTG_DTHRCTL_ISOTHREN_Msk  /*!< ISO IN endpoint threshold enable */
14194 
14195 #define USB_OTG_DTHRCTL_TXTHRLEN_Pos             (2U)
14196 #define USB_OTG_DTHRCTL_TXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
14197 #define USB_OTG_DTHRCTL_TXTHRLEN                 USB_OTG_DTHRCTL_TXTHRLEN_Msk  /*!< Transmit threshold length */
14198 #define USB_OTG_DTHRCTL_TXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
14199 #define USB_OTG_DTHRCTL_TXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
14200 #define USB_OTG_DTHRCTL_TXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
14201 #define USB_OTG_DTHRCTL_TXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
14202 #define USB_OTG_DTHRCTL_TXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
14203 #define USB_OTG_DTHRCTL_TXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
14204 #define USB_OTG_DTHRCTL_TXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
14205 #define USB_OTG_DTHRCTL_TXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
14206 #define USB_OTG_DTHRCTL_TXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
14207 #define USB_OTG_DTHRCTL_RXTHREN_Pos              (16U)
14208 #define USB_OTG_DTHRCTL_RXTHREN_Msk              (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
14209 #define USB_OTG_DTHRCTL_RXTHREN                  USB_OTG_DTHRCTL_RXTHREN_Msk   /*!< Receive threshold enable */
14210 
14211 #define USB_OTG_DTHRCTL_RXTHRLEN_Pos             (17U)
14212 #define USB_OTG_DTHRCTL_RXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
14213 #define USB_OTG_DTHRCTL_RXTHRLEN                 USB_OTG_DTHRCTL_RXTHRLEN_Msk  /*!< Receive threshold length */
14214 #define USB_OTG_DTHRCTL_RXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
14215 #define USB_OTG_DTHRCTL_RXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
14216 #define USB_OTG_DTHRCTL_RXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
14217 #define USB_OTG_DTHRCTL_RXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
14218 #define USB_OTG_DTHRCTL_RXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
14219 #define USB_OTG_DTHRCTL_RXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
14220 #define USB_OTG_DTHRCTL_RXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
14221 #define USB_OTG_DTHRCTL_RXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
14222 #define USB_OTG_DTHRCTL_RXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
14223 #define USB_OTG_DTHRCTL_ARPEN_Pos                (27U)
14224 #define USB_OTG_DTHRCTL_ARPEN_Msk                (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
14225 #define USB_OTG_DTHRCTL_ARPEN                    USB_OTG_DTHRCTL_ARPEN_Msk     /*!< Arbiter parking enable */
14226 
14227 /********************  Bit definition for USB_OTG_DIEPEMPMSK register  ********************/
14228 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos         (0U)
14229 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk         (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
14230 #define USB_OTG_DIEPEMPMSK_INEPTXFEM             USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
14231 
14232 /********************  Bit definition for USB_OTG_DEACHINT register  ********************/
14233 #define USB_OTG_DEACHINT_IEP1INT_Pos             (1U)
14234 #define USB_OTG_DEACHINT_IEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
14235 #define USB_OTG_DEACHINT_IEP1INT                 USB_OTG_DEACHINT_IEP1INT_Msk  /*!< IN endpoint 1interrupt bit   */
14236 #define USB_OTG_DEACHINT_OEP1INT_Pos             (17U)
14237 #define USB_OTG_DEACHINT_OEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
14238 #define USB_OTG_DEACHINT_OEP1INT                 USB_OTG_DEACHINT_OEP1INT_Msk  /*!< OUT endpoint 1 interrupt bit */
14239 
14240 /********************  Bit definition for USB_OTG_GCCFG register  ********************/
14241 #define USB_OTG_GCCFG_DCDET_Pos                  (0U)
14242 #define USB_OTG_GCCFG_DCDET_Msk                  (0x1UL << USB_OTG_GCCFG_DCDET_Pos) /*!< 0x00000001 */
14243 #define USB_OTG_GCCFG_DCDET                      USB_OTG_GCCFG_DCDET_Msk       /*!< Data contact detection (DCD) status */
14244 #define USB_OTG_GCCFG_PDET_Pos                   (1U)
14245 #define USB_OTG_GCCFG_PDET_Msk                   (0x1UL << USB_OTG_GCCFG_PDET_Pos) /*!< 0x00000002 */
14246 #define USB_OTG_GCCFG_PDET                       USB_OTG_GCCFG_PDET_Msk        /*!< Primary detection (PD) status */
14247 #define USB_OTG_GCCFG_SDET_Pos                   (2U)
14248 #define USB_OTG_GCCFG_SDET_Msk                   (0x1UL << USB_OTG_GCCFG_SDET_Pos) /*!< 0x00000004 */
14249 #define USB_OTG_GCCFG_SDET                       USB_OTG_GCCFG_SDET_Msk        /*!< Secondary detection (SD) status */
14250 #define USB_OTG_GCCFG_PS2DET_Pos                 (3U)
14251 #define USB_OTG_GCCFG_PS2DET_Msk                 (0x1UL << USB_OTG_GCCFG_PS2DET_Pos) /*!< 0x00000008 */
14252 #define USB_OTG_GCCFG_PS2DET                     USB_OTG_GCCFG_PS2DET_Msk      /*!< DM pull-up detection status */
14253 #define USB_OTG_GCCFG_PWRDWN_Pos                 (16U)
14254 #define USB_OTG_GCCFG_PWRDWN_Msk                 (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
14255 #define USB_OTG_GCCFG_PWRDWN                     USB_OTG_GCCFG_PWRDWN_Msk      /*!< Power down */
14256 #define USB_OTG_GCCFG_BCDEN_Pos                  (17U)
14257 #define USB_OTG_GCCFG_BCDEN_Msk                  (0x1UL << USB_OTG_GCCFG_BCDEN_Pos) /*!< 0x00020000 */
14258 #define USB_OTG_GCCFG_BCDEN                      USB_OTG_GCCFG_BCDEN_Msk       /*!< Battery charging detector (BCD) enable */
14259 #define USB_OTG_GCCFG_DCDEN_Pos                  (18U)
14260 #define USB_OTG_GCCFG_DCDEN_Msk                  (0x1UL << USB_OTG_GCCFG_DCDEN_Pos) /*!< 0x00040000 */
14261 #define USB_OTG_GCCFG_DCDEN                      USB_OTG_GCCFG_DCDEN_Msk       /*!< Data contact detection (DCD) mode enable*/
14262 #define USB_OTG_GCCFG_PDEN_Pos                   (19U)
14263 #define USB_OTG_GCCFG_PDEN_Msk                   (0x1UL << USB_OTG_GCCFG_PDEN_Pos) /*!< 0x00080000 */
14264 #define USB_OTG_GCCFG_PDEN                       USB_OTG_GCCFG_PDEN_Msk        /*!< Primary detection (PD) mode enable*/
14265 #define USB_OTG_GCCFG_SDEN_Pos                   (20U)
14266 #define USB_OTG_GCCFG_SDEN_Msk                   (0x1UL << USB_OTG_GCCFG_SDEN_Pos) /*!< 0x00100000 */
14267 #define USB_OTG_GCCFG_SDEN                       USB_OTG_GCCFG_SDEN_Msk        /*!< Secondary detection (SD) mode enable */
14268 #define USB_OTG_GCCFG_VBDEN_Pos                  (21U)
14269 #define USB_OTG_GCCFG_VBDEN_Msk                  (0x1UL << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */
14270 #define USB_OTG_GCCFG_VBDEN                      USB_OTG_GCCFG_VBDEN_Msk       /*!< USB VBUS Detection Enable */
14271 
14272 /********************  Bit definition forUSB_OTG_DEACHINTMSK register  ********************/
14273 #define USB_OTG_DEACHINTMSK_IEP1INTM_Pos         (1U)
14274 #define USB_OTG_DEACHINTMSK_IEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
14275 #define USB_OTG_DEACHINTMSK_IEP1INTM             USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit  */
14276 #define USB_OTG_DEACHINTMSK_OEP1INTM_Pos         (17U)
14277 #define USB_OTG_DEACHINTMSK_OEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
14278 #define USB_OTG_DEACHINTMSK_OEP1INTM             USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
14279 
14280 /********************  Bit definition for USB_OTG_CID register  ********************/
14281 #define USB_OTG_CID_PRODUCT_ID_Pos               (0U)
14282 #define USB_OTG_CID_PRODUCT_ID_Msk               (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
14283 #define USB_OTG_CID_PRODUCT_ID                   USB_OTG_CID_PRODUCT_ID_Msk    /*!< Product ID field */
14284 
14285 /********************  Bit definition for USB_OTG_GLPMCFG register  ********************/
14286 #define USB_OTG_GLPMCFG_LPMEN_Pos                (0U)
14287 #define USB_OTG_GLPMCFG_LPMEN_Msk                (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */
14288 #define USB_OTG_GLPMCFG_LPMEN                    USB_OTG_GLPMCFG_LPMEN_Msk     /*!< LPM support enable                                     */
14289 #define USB_OTG_GLPMCFG_LPMACK_Pos               (1U)
14290 #define USB_OTG_GLPMCFG_LPMACK_Msk               (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */
14291 #define USB_OTG_GLPMCFG_LPMACK                   USB_OTG_GLPMCFG_LPMACK_Msk    /*!< LPM Token acknowledge enable                           */
14292 #define USB_OTG_GLPMCFG_BESL_Pos                 (2U)
14293 #define USB_OTG_GLPMCFG_BESL_Msk                 (0xFUL << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */
14294 #define USB_OTG_GLPMCFG_BESL                     USB_OTG_GLPMCFG_BESL_Msk      /*!< BESL value received with last ACKed LPM Token          */
14295 #define USB_OTG_GLPMCFG_REMWAKE_Pos              (6U)
14296 #define USB_OTG_GLPMCFG_REMWAKE_Msk              (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */
14297 #define USB_OTG_GLPMCFG_REMWAKE                  USB_OTG_GLPMCFG_REMWAKE_Msk   /*!< bRemoteWake value received with last ACKed LPM Token   */
14298 #define USB_OTG_GLPMCFG_L1SSEN_Pos               (7U)
14299 #define USB_OTG_GLPMCFG_L1SSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */
14300 #define USB_OTG_GLPMCFG_L1SSEN                   USB_OTG_GLPMCFG_L1SSEN_Msk    /*!< L1 shallow sleep enable                                */
14301 #define USB_OTG_GLPMCFG_BESLTHRS_Pos             (8U)
14302 #define USB_OTG_GLPMCFG_BESLTHRS_Msk             (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */
14303 #define USB_OTG_GLPMCFG_BESLTHRS                 USB_OTG_GLPMCFG_BESLTHRS_Msk  /*!< BESL threshold                                         */
14304 #define USB_OTG_GLPMCFG_L1DSEN_Pos               (12U)
14305 #define USB_OTG_GLPMCFG_L1DSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */
14306 #define USB_OTG_GLPMCFG_L1DSEN                   USB_OTG_GLPMCFG_L1DSEN_Msk    /*!< L1 deep sleep enable                                   */
14307 #define USB_OTG_GLPMCFG_LPMRSP_Pos               (13U)
14308 #define USB_OTG_GLPMCFG_LPMRSP_Msk               (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */
14309 #define USB_OTG_GLPMCFG_LPMRSP                   USB_OTG_GLPMCFG_LPMRSP_Msk    /*!< LPM response                                           */
14310 #define USB_OTG_GLPMCFG_SLPSTS_Pos               (15U)
14311 #define USB_OTG_GLPMCFG_SLPSTS_Msk               (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */
14312 #define USB_OTG_GLPMCFG_SLPSTS                   USB_OTG_GLPMCFG_SLPSTS_Msk    /*!< Port sleep status                                      */
14313 #define USB_OTG_GLPMCFG_L1RSMOK_Pos              (16U)
14314 #define USB_OTG_GLPMCFG_L1RSMOK_Msk              (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */
14315 #define USB_OTG_GLPMCFG_L1RSMOK                  USB_OTG_GLPMCFG_L1RSMOK_Msk   /*!< Sleep State Resume OK                                  */
14316 #define USB_OTG_GLPMCFG_LPMCHIDX_Pos             (17U)
14317 #define USB_OTG_GLPMCFG_LPMCHIDX_Msk             (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */
14318 #define USB_OTG_GLPMCFG_LPMCHIDX                 USB_OTG_GLPMCFG_LPMCHIDX_Msk  /*!< LPM Channel Index                                      */
14319 #define USB_OTG_GLPMCFG_LPMRCNT_Pos              (21U)
14320 #define USB_OTG_GLPMCFG_LPMRCNT_Msk              (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */
14321 #define USB_OTG_GLPMCFG_LPMRCNT                  USB_OTG_GLPMCFG_LPMRCNT_Msk   /*!< LPM retry count                                        */
14322 #define USB_OTG_GLPMCFG_SNDLPM_Pos               (24U)
14323 #define USB_OTG_GLPMCFG_SNDLPM_Msk               (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */
14324 #define USB_OTG_GLPMCFG_SNDLPM                   USB_OTG_GLPMCFG_SNDLPM_Msk    /*!< Send LPM transaction                                   */
14325 #define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos           (25U)
14326 #define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk           (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */
14327 #define USB_OTG_GLPMCFG_LPMRCNTSTS               USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status                                 */
14328 #define USB_OTG_GLPMCFG_ENBESL_Pos               (28U)
14329 #define USB_OTG_GLPMCFG_ENBESL_Msk               (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */
14330 #define USB_OTG_GLPMCFG_ENBESL                   USB_OTG_GLPMCFG_ENBESL_Msk    /*!< Enable best effort service latency                     */
14331 
14332 /********************  Bit definition for USB_OTG_DIEPEACHMSK1 register  ********************/
14333 #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos           (0U)
14334 #define USB_OTG_DIEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
14335 #define USB_OTG_DIEPEACHMSK1_XFRCM               USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask                 */
14336 #define USB_OTG_DIEPEACHMSK1_EPDM_Pos            (1U)
14337 #define USB_OTG_DIEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
14338 #define USB_OTG_DIEPEACHMSK1_EPDM                USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask                  */
14339 #define USB_OTG_DIEPEACHMSK1_TOM_Pos             (3U)
14340 #define USB_OTG_DIEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
14341 #define USB_OTG_DIEPEACHMSK1_TOM                 USB_OTG_DIEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask (nonisochronous endpoints) */
14342 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos       (4U)
14343 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
14344 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK           USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */
14345 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos         (5U)
14346 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
14347 #define USB_OTG_DIEPEACHMSK1_INEPNMM             USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask           */
14348 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos         (6U)
14349 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
14350 #define USB_OTG_DIEPEACHMSK1_INEPNEM             USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask                    */
14351 #define USB_OTG_DIEPEACHMSK1_TXFURM_Pos          (8U)
14352 #define USB_OTG_DIEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
14353 #define USB_OTG_DIEPEACHMSK1_TXFURM              USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask                                */
14354 #define USB_OTG_DIEPEACHMSK1_BIM_Pos             (9U)
14355 #define USB_OTG_DIEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
14356 #define USB_OTG_DIEPEACHMSK1_BIM                 USB_OTG_DIEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask                                */
14357 #define USB_OTG_DIEPEACHMSK1_NAKM_Pos            (13U)
14358 #define USB_OTG_DIEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
14359 #define USB_OTG_DIEPEACHMSK1_NAKM                USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask                                */
14360 
14361 /********************  Bit definition for USB_OTG_HPRT register  ********************/
14362 #define USB_OTG_HPRT_PCSTS_Pos                   (0U)
14363 #define USB_OTG_HPRT_PCSTS_Msk                   (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
14364 #define USB_OTG_HPRT_PCSTS                       USB_OTG_HPRT_PCSTS_Msk        /*!< Port connect status        */
14365 #define USB_OTG_HPRT_PCDET_Pos                   (1U)
14366 #define USB_OTG_HPRT_PCDET_Msk                   (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
14367 #define USB_OTG_HPRT_PCDET                       USB_OTG_HPRT_PCDET_Msk        /*!< Port connect detected      */
14368 #define USB_OTG_HPRT_PENA_Pos                    (2U)
14369 #define USB_OTG_HPRT_PENA_Msk                    (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
14370 #define USB_OTG_HPRT_PENA                        USB_OTG_HPRT_PENA_Msk         /*!< Port enable                */
14371 #define USB_OTG_HPRT_PENCHNG_Pos                 (3U)
14372 #define USB_OTG_HPRT_PENCHNG_Msk                 (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
14373 #define USB_OTG_HPRT_PENCHNG                     USB_OTG_HPRT_PENCHNG_Msk      /*!< Port enable/disable change */
14374 #define USB_OTG_HPRT_POCA_Pos                    (4U)
14375 #define USB_OTG_HPRT_POCA_Msk                    (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
14376 #define USB_OTG_HPRT_POCA                        USB_OTG_HPRT_POCA_Msk         /*!< Port overcurrent active    */
14377 #define USB_OTG_HPRT_POCCHNG_Pos                 (5U)
14378 #define USB_OTG_HPRT_POCCHNG_Msk                 (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
14379 #define USB_OTG_HPRT_POCCHNG                     USB_OTG_HPRT_POCCHNG_Msk      /*!< Port overcurrent change    */
14380 #define USB_OTG_HPRT_PRES_Pos                    (6U)
14381 #define USB_OTG_HPRT_PRES_Msk                    (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
14382 #define USB_OTG_HPRT_PRES                        USB_OTG_HPRT_PRES_Msk         /*!< Port resume                */
14383 #define USB_OTG_HPRT_PSUSP_Pos                   (7U)
14384 #define USB_OTG_HPRT_PSUSP_Msk                   (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
14385 #define USB_OTG_HPRT_PSUSP                       USB_OTG_HPRT_PSUSP_Msk        /*!< Port suspend               */
14386 #define USB_OTG_HPRT_PRST_Pos                    (8U)
14387 #define USB_OTG_HPRT_PRST_Msk                    (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
14388 #define USB_OTG_HPRT_PRST                        USB_OTG_HPRT_PRST_Msk         /*!< Port reset                 */
14389 
14390 #define USB_OTG_HPRT_PLSTS_Pos                   (10U)
14391 #define USB_OTG_HPRT_PLSTS_Msk                   (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
14392 #define USB_OTG_HPRT_PLSTS                       USB_OTG_HPRT_PLSTS_Msk        /*!< Port line status           */
14393 #define USB_OTG_HPRT_PLSTS_0                     (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
14394 #define USB_OTG_HPRT_PLSTS_1                     (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
14395 #define USB_OTG_HPRT_PPWR_Pos                    (12U)
14396 #define USB_OTG_HPRT_PPWR_Msk                    (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
14397 #define USB_OTG_HPRT_PPWR                        USB_OTG_HPRT_PPWR_Msk         /*!< Port power                 */
14398 
14399 #define USB_OTG_HPRT_PTCTL_Pos                   (13U)
14400 #define USB_OTG_HPRT_PTCTL_Msk                   (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
14401 #define USB_OTG_HPRT_PTCTL                       USB_OTG_HPRT_PTCTL_Msk        /*!< Port test control          */
14402 #define USB_OTG_HPRT_PTCTL_0                     (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
14403 #define USB_OTG_HPRT_PTCTL_1                     (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
14404 #define USB_OTG_HPRT_PTCTL_2                     (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
14405 #define USB_OTG_HPRT_PTCTL_3                     (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
14406 
14407 #define USB_OTG_HPRT_PSPD_Pos                    (17U)
14408 #define USB_OTG_HPRT_PSPD_Msk                    (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
14409 #define USB_OTG_HPRT_PSPD                        USB_OTG_HPRT_PSPD_Msk         /*!< Port speed                 */
14410 #define USB_OTG_HPRT_PSPD_0                      (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
14411 #define USB_OTG_HPRT_PSPD_1                      (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
14412 
14413 /********************  Bit definition for USB_OTG_DOEPEACHMSK1 register  ********************/
14414 #define USB_OTG_DOEPEACHMSK1_XFRCM_Pos           (0U)
14415 #define USB_OTG_DOEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
14416 #define USB_OTG_DOEPEACHMSK1_XFRCM               USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask         */
14417 #define USB_OTG_DOEPEACHMSK1_EPDM_Pos            (1U)
14418 #define USB_OTG_DOEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
14419 #define USB_OTG_DOEPEACHMSK1_EPDM                USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask          */
14420 #define USB_OTG_DOEPEACHMSK1_TOM_Pos             (3U)
14421 #define USB_OTG_DOEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
14422 #define USB_OTG_DOEPEACHMSK1_TOM                 USB_OTG_DOEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask                    */
14423 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos       (4U)
14424 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
14425 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK           USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask  */
14426 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos         (5U)
14427 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
14428 #define USB_OTG_DOEPEACHMSK1_INEPNMM             USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask   */
14429 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos         (6U)
14430 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
14431 #define USB_OTG_DOEPEACHMSK1_INEPNEM             USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask            */
14432 #define USB_OTG_DOEPEACHMSK1_TXFURM_Pos          (8U)
14433 #define USB_OTG_DOEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
14434 #define USB_OTG_DOEPEACHMSK1_TXFURM              USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask                     */
14435 #define USB_OTG_DOEPEACHMSK1_BIM_Pos             (9U)
14436 #define USB_OTG_DOEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
14437 #define USB_OTG_DOEPEACHMSK1_BIM                 USB_OTG_DOEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask                        */
14438 #define USB_OTG_DOEPEACHMSK1_BERRM_Pos           (12U)
14439 #define USB_OTG_DOEPEACHMSK1_BERRM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
14440 #define USB_OTG_DOEPEACHMSK1_BERRM               USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask               */
14441 #define USB_OTG_DOEPEACHMSK1_NAKM_Pos            (13U)
14442 #define USB_OTG_DOEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
14443 #define USB_OTG_DOEPEACHMSK1_NAKM                USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask                        */
14444 #define USB_OTG_DOEPEACHMSK1_NYETM_Pos           (14U)
14445 #define USB_OTG_DOEPEACHMSK1_NYETM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
14446 #define USB_OTG_DOEPEACHMSK1_NYETM               USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask                       */
14447 
14448 /********************  Bit definition for USB_OTG_HPTXFSIZ register  ********************/
14449 #define USB_OTG_HPTXFSIZ_PTXSA_Pos               (0U)
14450 #define USB_OTG_HPTXFSIZ_PTXSA_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
14451 #define USB_OTG_HPTXFSIZ_PTXSA                   USB_OTG_HPTXFSIZ_PTXSA_Msk    /*!< Host periodic TxFIFO start address            */
14452 #define USB_OTG_HPTXFSIZ_PTXFD_Pos               (16U)
14453 #define USB_OTG_HPTXFSIZ_PTXFD_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
14454 #define USB_OTG_HPTXFSIZ_PTXFD                   USB_OTG_HPTXFSIZ_PTXFD_Msk    /*!< Host periodic TxFIFO depth                    */
14455 
14456 /********************  Bit definition for USB_OTG_DIEPCTL register  ********************/
14457 #define USB_OTG_DIEPCTL_MPSIZ_Pos                (0U)
14458 #define USB_OTG_DIEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
14459 #define USB_OTG_DIEPCTL_MPSIZ                    USB_OTG_DIEPCTL_MPSIZ_Msk     /*!< Maximum packet size              */
14460 #define USB_OTG_DIEPCTL_USBAEP_Pos               (15U)
14461 #define USB_OTG_DIEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
14462 #define USB_OTG_DIEPCTL_USBAEP                   USB_OTG_DIEPCTL_USBAEP_Msk    /*!< USB active endpoint              */
14463 #define USB_OTG_DIEPCTL_EONUM_DPID_Pos           (16U)
14464 #define USB_OTG_DIEPCTL_EONUM_DPID_Msk           (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
14465 #define USB_OTG_DIEPCTL_EONUM_DPID               USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame                   */
14466 #define USB_OTG_DIEPCTL_NAKSTS_Pos               (17U)
14467 #define USB_OTG_DIEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
14468 #define USB_OTG_DIEPCTL_NAKSTS                   USB_OTG_DIEPCTL_NAKSTS_Msk    /*!< NAK status                       */
14469 
14470 #define USB_OTG_DIEPCTL_EPTYP_Pos                (18U)
14471 #define USB_OTG_DIEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
14472 #define USB_OTG_DIEPCTL_EPTYP                    USB_OTG_DIEPCTL_EPTYP_Msk     /*!< Endpoint type                    */
14473 #define USB_OTG_DIEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
14474 #define USB_OTG_DIEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
14475 #define USB_OTG_DIEPCTL_STALL_Pos                (21U)
14476 #define USB_OTG_DIEPCTL_STALL_Msk                (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
14477 #define USB_OTG_DIEPCTL_STALL                    USB_OTG_DIEPCTL_STALL_Msk     /*!< STALL handshake                  */
14478 
14479 #define USB_OTG_DIEPCTL_TXFNUM_Pos               (22U)
14480 #define USB_OTG_DIEPCTL_TXFNUM_Msk               (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
14481 #define USB_OTG_DIEPCTL_TXFNUM                   USB_OTG_DIEPCTL_TXFNUM_Msk    /*!< TxFIFO number                    */
14482 #define USB_OTG_DIEPCTL_TXFNUM_0                 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
14483 #define USB_OTG_DIEPCTL_TXFNUM_1                 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
14484 #define USB_OTG_DIEPCTL_TXFNUM_2                 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
14485 #define USB_OTG_DIEPCTL_TXFNUM_3                 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
14486 #define USB_OTG_DIEPCTL_CNAK_Pos                 (26U)
14487 #define USB_OTG_DIEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
14488 #define USB_OTG_DIEPCTL_CNAK                     USB_OTG_DIEPCTL_CNAK_Msk      /*!< Clear NAK                        */
14489 #define USB_OTG_DIEPCTL_SNAK_Pos                 (27U)
14490 #define USB_OTG_DIEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
14491 #define USB_OTG_DIEPCTL_SNAK                     USB_OTG_DIEPCTL_SNAK_Msk      /*!< Set NAK */
14492 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos       (28U)
14493 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
14494 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM           USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID                    */
14495 #define USB_OTG_DIEPCTL_SODDFRM_Pos              (29U)
14496 #define USB_OTG_DIEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
14497 #define USB_OTG_DIEPCTL_SODDFRM                  USB_OTG_DIEPCTL_SODDFRM_Msk   /*!< Set odd frame                    */
14498 #define USB_OTG_DIEPCTL_EPDIS_Pos                (30U)
14499 #define USB_OTG_DIEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
14500 #define USB_OTG_DIEPCTL_EPDIS                    USB_OTG_DIEPCTL_EPDIS_Msk     /*!< Endpoint disable                 */
14501 #define USB_OTG_DIEPCTL_EPENA_Pos                (31U)
14502 #define USB_OTG_DIEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
14503 #define USB_OTG_DIEPCTL_EPENA                    USB_OTG_DIEPCTL_EPENA_Msk     /*!< Endpoint enable                  */
14504 
14505 /********************  Bit definition for USB_OTG_HCCHAR register  ********************/
14506 #define USB_OTG_HCCHAR_MPSIZ_Pos                 (0U)
14507 #define USB_OTG_HCCHAR_MPSIZ_Msk                 (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
14508 #define USB_OTG_HCCHAR_MPSIZ                     USB_OTG_HCCHAR_MPSIZ_Msk      /*!< Maximum packet size */
14509 
14510 #define USB_OTG_HCCHAR_EPNUM_Pos                 (11U)
14511 #define USB_OTG_HCCHAR_EPNUM_Msk                 (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
14512 #define USB_OTG_HCCHAR_EPNUM                     USB_OTG_HCCHAR_EPNUM_Msk      /*!< Endpoint number */
14513 #define USB_OTG_HCCHAR_EPNUM_0                   (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
14514 #define USB_OTG_HCCHAR_EPNUM_1                   (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
14515 #define USB_OTG_HCCHAR_EPNUM_2                   (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
14516 #define USB_OTG_HCCHAR_EPNUM_3                   (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
14517 #define USB_OTG_HCCHAR_EPDIR_Pos                 (15U)
14518 #define USB_OTG_HCCHAR_EPDIR_Msk                 (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
14519 #define USB_OTG_HCCHAR_EPDIR                     USB_OTG_HCCHAR_EPDIR_Msk      /*!< Endpoint direction */
14520 #define USB_OTG_HCCHAR_LSDEV_Pos                 (17U)
14521 #define USB_OTG_HCCHAR_LSDEV_Msk                 (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
14522 #define USB_OTG_HCCHAR_LSDEV                     USB_OTG_HCCHAR_LSDEV_Msk      /*!< Low-speed device */
14523 
14524 #define USB_OTG_HCCHAR_EPTYP_Pos                 (18U)
14525 #define USB_OTG_HCCHAR_EPTYP_Msk                 (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
14526 #define USB_OTG_HCCHAR_EPTYP                     USB_OTG_HCCHAR_EPTYP_Msk      /*!< Endpoint type */
14527 #define USB_OTG_HCCHAR_EPTYP_0                   (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
14528 #define USB_OTG_HCCHAR_EPTYP_1                   (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
14529 
14530 #define USB_OTG_HCCHAR_MC_Pos                    (20U)
14531 #define USB_OTG_HCCHAR_MC_Msk                    (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
14532 #define USB_OTG_HCCHAR_MC                        USB_OTG_HCCHAR_MC_Msk         /*!< Multi Count (MC) / Error Count (EC) */
14533 #define USB_OTG_HCCHAR_MC_0                      (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
14534 #define USB_OTG_HCCHAR_MC_1                      (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
14535 
14536 #define USB_OTG_HCCHAR_DAD_Pos                   (22U)
14537 #define USB_OTG_HCCHAR_DAD_Msk                   (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
14538 #define USB_OTG_HCCHAR_DAD                       USB_OTG_HCCHAR_DAD_Msk        /*!< Device address */
14539 #define USB_OTG_HCCHAR_DAD_0                     (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
14540 #define USB_OTG_HCCHAR_DAD_1                     (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
14541 #define USB_OTG_HCCHAR_DAD_2                     (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
14542 #define USB_OTG_HCCHAR_DAD_3                     (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
14543 #define USB_OTG_HCCHAR_DAD_4                     (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
14544 #define USB_OTG_HCCHAR_DAD_5                     (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
14545 #define USB_OTG_HCCHAR_DAD_6                     (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
14546 #define USB_OTG_HCCHAR_ODDFRM_Pos                (29U)
14547 #define USB_OTG_HCCHAR_ODDFRM_Msk                (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
14548 #define USB_OTG_HCCHAR_ODDFRM                    USB_OTG_HCCHAR_ODDFRM_Msk     /*!< Odd frame */
14549 #define USB_OTG_HCCHAR_CHDIS_Pos                 (30U)
14550 #define USB_OTG_HCCHAR_CHDIS_Msk                 (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
14551 #define USB_OTG_HCCHAR_CHDIS                     USB_OTG_HCCHAR_CHDIS_Msk      /*!< Channel disable */
14552 #define USB_OTG_HCCHAR_CHENA_Pos                 (31U)
14553 #define USB_OTG_HCCHAR_CHENA_Msk                 (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
14554 #define USB_OTG_HCCHAR_CHENA                     USB_OTG_HCCHAR_CHENA_Msk      /*!< Channel enable */
14555 
14556 /********************  Bit definition for USB_OTG_HCSPLT register  ********************/
14557 
14558 #define USB_OTG_HCSPLT_PRTADDR_Pos               (0U)
14559 #define USB_OTG_HCSPLT_PRTADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
14560 #define USB_OTG_HCSPLT_PRTADDR                   USB_OTG_HCSPLT_PRTADDR_Msk    /*!< Port address */
14561 #define USB_OTG_HCSPLT_PRTADDR_0                 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
14562 #define USB_OTG_HCSPLT_PRTADDR_1                 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
14563 #define USB_OTG_HCSPLT_PRTADDR_2                 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
14564 #define USB_OTG_HCSPLT_PRTADDR_3                 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
14565 #define USB_OTG_HCSPLT_PRTADDR_4                 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
14566 #define USB_OTG_HCSPLT_PRTADDR_5                 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
14567 #define USB_OTG_HCSPLT_PRTADDR_6                 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
14568 
14569 #define USB_OTG_HCSPLT_HUBADDR_Pos               (7U)
14570 #define USB_OTG_HCSPLT_HUBADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
14571 #define USB_OTG_HCSPLT_HUBADDR                   USB_OTG_HCSPLT_HUBADDR_Msk    /*!< Hub address */
14572 #define USB_OTG_HCSPLT_HUBADDR_0                 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
14573 #define USB_OTG_HCSPLT_HUBADDR_1                 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
14574 #define USB_OTG_HCSPLT_HUBADDR_2                 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
14575 #define USB_OTG_HCSPLT_HUBADDR_3                 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
14576 #define USB_OTG_HCSPLT_HUBADDR_4                 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
14577 #define USB_OTG_HCSPLT_HUBADDR_5                 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
14578 #define USB_OTG_HCSPLT_HUBADDR_6                 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
14579 
14580 #define USB_OTG_HCSPLT_XACTPOS_Pos               (14U)
14581 #define USB_OTG_HCSPLT_XACTPOS_Msk               (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
14582 #define USB_OTG_HCSPLT_XACTPOS                   USB_OTG_HCSPLT_XACTPOS_Msk    /*!< XACTPOS */
14583 #define USB_OTG_HCSPLT_XACTPOS_0                 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
14584 #define USB_OTG_HCSPLT_XACTPOS_1                 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
14585 #define USB_OTG_HCSPLT_COMPLSPLT_Pos             (16U)
14586 #define USB_OTG_HCSPLT_COMPLSPLT_Msk             (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
14587 #define USB_OTG_HCSPLT_COMPLSPLT                 USB_OTG_HCSPLT_COMPLSPLT_Msk  /*!< Do complete split */
14588 #define USB_OTG_HCSPLT_SPLITEN_Pos               (31U)
14589 #define USB_OTG_HCSPLT_SPLITEN_Msk               (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
14590 #define USB_OTG_HCSPLT_SPLITEN                   USB_OTG_HCSPLT_SPLITEN_Msk    /*!< Split enable */
14591 
14592 /********************  Bit definition for USB_OTG_HCINT register  ********************/
14593 #define USB_OTG_HCINT_XFRC_Pos                   (0U)
14594 #define USB_OTG_HCINT_XFRC_Msk                   (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
14595 #define USB_OTG_HCINT_XFRC                       USB_OTG_HCINT_XFRC_Msk        /*!< Transfer completed */
14596 #define USB_OTG_HCINT_CHH_Pos                    (1U)
14597 #define USB_OTG_HCINT_CHH_Msk                    (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
14598 #define USB_OTG_HCINT_CHH                        USB_OTG_HCINT_CHH_Msk         /*!< Channel halted */
14599 #define USB_OTG_HCINT_AHBERR_Pos                 (2U)
14600 #define USB_OTG_HCINT_AHBERR_Msk                 (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
14601 #define USB_OTG_HCINT_AHBERR                     USB_OTG_HCINT_AHBERR_Msk      /*!< AHB error */
14602 #define USB_OTG_HCINT_STALL_Pos                  (3U)
14603 #define USB_OTG_HCINT_STALL_Msk                  (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
14604 #define USB_OTG_HCINT_STALL                      USB_OTG_HCINT_STALL_Msk       /*!< STALL response received interrupt */
14605 #define USB_OTG_HCINT_NAK_Pos                    (4U)
14606 #define USB_OTG_HCINT_NAK_Msk                    (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
14607 #define USB_OTG_HCINT_NAK                        USB_OTG_HCINT_NAK_Msk         /*!< NAK response received interrupt */
14608 #define USB_OTG_HCINT_ACK_Pos                    (5U)
14609 #define USB_OTG_HCINT_ACK_Msk                    (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
14610 #define USB_OTG_HCINT_ACK                        USB_OTG_HCINT_ACK_Msk         /*!< ACK response received/transmitted interrupt */
14611 #define USB_OTG_HCINT_NYET_Pos                   (6U)
14612 #define USB_OTG_HCINT_NYET_Msk                   (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
14613 #define USB_OTG_HCINT_NYET                       USB_OTG_HCINT_NYET_Msk        /*!< Response received interrupt */
14614 #define USB_OTG_HCINT_TXERR_Pos                  (7U)
14615 #define USB_OTG_HCINT_TXERR_Msk                  (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
14616 #define USB_OTG_HCINT_TXERR                      USB_OTG_HCINT_TXERR_Msk       /*!< Transaction error */
14617 #define USB_OTG_HCINT_BBERR_Pos                  (8U)
14618 #define USB_OTG_HCINT_BBERR_Msk                  (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
14619 #define USB_OTG_HCINT_BBERR                      USB_OTG_HCINT_BBERR_Msk       /*!< Babble error */
14620 #define USB_OTG_HCINT_FRMOR_Pos                  (9U)
14621 #define USB_OTG_HCINT_FRMOR_Msk                  (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
14622 #define USB_OTG_HCINT_FRMOR                      USB_OTG_HCINT_FRMOR_Msk       /*!< Frame overrun */
14623 #define USB_OTG_HCINT_DTERR_Pos                  (10U)
14624 #define USB_OTG_HCINT_DTERR_Msk                  (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
14625 #define USB_OTG_HCINT_DTERR                      USB_OTG_HCINT_DTERR_Msk       /*!< Data toggle error */
14626 
14627 /********************  Bit definition for USB_OTG_DIEPINT register  ********************/
14628 #define USB_OTG_DIEPINT_XFRC_Pos                 (0U)
14629 #define USB_OTG_DIEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
14630 #define USB_OTG_DIEPINT_XFRC                     USB_OTG_DIEPINT_XFRC_Msk      /*!< Transfer completed interrupt */
14631 #define USB_OTG_DIEPINT_EPDISD_Pos               (1U)
14632 #define USB_OTG_DIEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
14633 #define USB_OTG_DIEPINT_EPDISD                   USB_OTG_DIEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */
14634 #define USB_OTG_DIEPINT_AHBERR_Pos               (2U)
14635 #define USB_OTG_DIEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */
14636 #define USB_OTG_DIEPINT_AHBERR                   USB_OTG_DIEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an IN transaction */
14637 #define USB_OTG_DIEPINT_TOC_Pos                  (3U)
14638 #define USB_OTG_DIEPINT_TOC_Msk                  (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
14639 #define USB_OTG_DIEPINT_TOC                      USB_OTG_DIEPINT_TOC_Msk       /*!< Timeout condition */
14640 #define USB_OTG_DIEPINT_ITTXFE_Pos               (4U)
14641 #define USB_OTG_DIEPINT_ITTXFE_Msk               (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
14642 #define USB_OTG_DIEPINT_ITTXFE                   USB_OTG_DIEPINT_ITTXFE_Msk    /*!< IN token received when TxFIFO is empty */
14643 #define USB_OTG_DIEPINT_INEPNM_Pos               (5U)
14644 #define USB_OTG_DIEPINT_INEPNM_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000004 */
14645 #define USB_OTG_DIEPINT_INEPNM                   USB_OTG_DIEPINT_INEPNM_Msk   /*!< IN token received with EP mismatch */
14646 #define USB_OTG_DIEPINT_INEPNE_Pos               (6U)
14647 #define USB_OTG_DIEPINT_INEPNE_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
14648 #define USB_OTG_DIEPINT_INEPNE                   USB_OTG_DIEPINT_INEPNE_Msk    /*!< IN endpoint NAK effective */
14649 #define USB_OTG_DIEPINT_TXFE_Pos                 (7U)
14650 #define USB_OTG_DIEPINT_TXFE_Msk                 (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
14651 #define USB_OTG_DIEPINT_TXFE                     USB_OTG_DIEPINT_TXFE_Msk      /*!< Transmit FIFO empty */
14652 #define USB_OTG_DIEPINT_TXFIFOUDRN_Pos           (8U)
14653 #define USB_OTG_DIEPINT_TXFIFOUDRN_Msk           (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
14654 #define USB_OTG_DIEPINT_TXFIFOUDRN               USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
14655 #define USB_OTG_DIEPINT_BNA_Pos                  (9U)
14656 #define USB_OTG_DIEPINT_BNA_Msk                  (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
14657 #define USB_OTG_DIEPINT_BNA                      USB_OTG_DIEPINT_BNA_Msk       /*!< Buffer not available interrupt */
14658 #define USB_OTG_DIEPINT_PKTDRPSTS_Pos            (11U)
14659 #define USB_OTG_DIEPINT_PKTDRPSTS_Msk            (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
14660 #define USB_OTG_DIEPINT_PKTDRPSTS                USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
14661 #define USB_OTG_DIEPINT_BERR_Pos                 (12U)
14662 #define USB_OTG_DIEPINT_BERR_Msk                 (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
14663 #define USB_OTG_DIEPINT_BERR                     USB_OTG_DIEPINT_BERR_Msk      /*!< Babble error interrupt */
14664 #define USB_OTG_DIEPINT_NAK_Pos                  (13U)
14665 #define USB_OTG_DIEPINT_NAK_Msk                  (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
14666 #define USB_OTG_DIEPINT_NAK                      USB_OTG_DIEPINT_NAK_Msk       /*!< NAK interrupt */
14667 
14668 /********************  Bit definition forUSB_OTG_HCINTMSK register  ********************/
14669 #define USB_OTG_HCINTMSK_XFRCM_Pos               (0U)
14670 #define USB_OTG_HCINTMSK_XFRCM_Msk               (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
14671 #define USB_OTG_HCINTMSK_XFRCM                   USB_OTG_HCINTMSK_XFRCM_Msk    /*!< Transfer completed mask */
14672 #define USB_OTG_HCINTMSK_CHHM_Pos                (1U)
14673 #define USB_OTG_HCINTMSK_CHHM_Msk                (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
14674 #define USB_OTG_HCINTMSK_CHHM                    USB_OTG_HCINTMSK_CHHM_Msk     /*!< Channel halted mask */
14675 #define USB_OTG_HCINTMSK_AHBERR_Pos              (2U)
14676 #define USB_OTG_HCINTMSK_AHBERR_Msk              (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
14677 #define USB_OTG_HCINTMSK_AHBERR                  USB_OTG_HCINTMSK_AHBERR_Msk   /*!< AHB error */
14678 #define USB_OTG_HCINTMSK_STALLM_Pos              (3U)
14679 #define USB_OTG_HCINTMSK_STALLM_Msk              (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
14680 #define USB_OTG_HCINTMSK_STALLM                  USB_OTG_HCINTMSK_STALLM_Msk   /*!< STALL response received interrupt mask */
14681 #define USB_OTG_HCINTMSK_NAKM_Pos                (4U)
14682 #define USB_OTG_HCINTMSK_NAKM_Msk                (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
14683 #define USB_OTG_HCINTMSK_NAKM                    USB_OTG_HCINTMSK_NAKM_Msk     /*!< NAK response received interrupt mask */
14684 #define USB_OTG_HCINTMSK_ACKM_Pos                (5U)
14685 #define USB_OTG_HCINTMSK_ACKM_Msk                (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
14686 #define USB_OTG_HCINTMSK_ACKM                    USB_OTG_HCINTMSK_ACKM_Msk     /*!< ACK response received/transmitted interrupt mask */
14687 #define USB_OTG_HCINTMSK_NYET_Pos                (6U)
14688 #define USB_OTG_HCINTMSK_NYET_Msk                (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
14689 #define USB_OTG_HCINTMSK_NYET                    USB_OTG_HCINTMSK_NYET_Msk     /*!< response received interrupt mask */
14690 #define USB_OTG_HCINTMSK_TXERRM_Pos              (7U)
14691 #define USB_OTG_HCINTMSK_TXERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
14692 #define USB_OTG_HCINTMSK_TXERRM                  USB_OTG_HCINTMSK_TXERRM_Msk   /*!< Transaction error mask */
14693 #define USB_OTG_HCINTMSK_BBERRM_Pos              (8U)
14694 #define USB_OTG_HCINTMSK_BBERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
14695 #define USB_OTG_HCINTMSK_BBERRM                  USB_OTG_HCINTMSK_BBERRM_Msk   /*!< Babble error mask */
14696 #define USB_OTG_HCINTMSK_FRMORM_Pos              (9U)
14697 #define USB_OTG_HCINTMSK_FRMORM_Msk              (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
14698 #define USB_OTG_HCINTMSK_FRMORM                  USB_OTG_HCINTMSK_FRMORM_Msk   /*!< Frame overrun mask */
14699 #define USB_OTG_HCINTMSK_DTERRM_Pos              (10U)
14700 #define USB_OTG_HCINTMSK_DTERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
14701 #define USB_OTG_HCINTMSK_DTERRM                  USB_OTG_HCINTMSK_DTERRM_Msk   /*!< Data toggle error mask */
14702 
14703 /********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
14704 
14705 #define USB_OTG_DIEPTSIZ_XFRSIZ_Pos              (0U)
14706 #define USB_OTG_DIEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
14707 #define USB_OTG_DIEPTSIZ_XFRSIZ                  USB_OTG_DIEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */
14708 #define USB_OTG_DIEPTSIZ_PKTCNT_Pos              (19U)
14709 #define USB_OTG_DIEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
14710 #define USB_OTG_DIEPTSIZ_PKTCNT                  USB_OTG_DIEPTSIZ_PKTCNT_Msk   /*!< Packet count */
14711 #define USB_OTG_DIEPTSIZ_MULCNT_Pos              (29U)
14712 #define USB_OTG_DIEPTSIZ_MULCNT_Msk              (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
14713 #define USB_OTG_DIEPTSIZ_MULCNT                  USB_OTG_DIEPTSIZ_MULCNT_Msk   /*!< Packet count */
14714 /********************  Bit definition for USB_OTG_HCTSIZ register  ********************/
14715 #define USB_OTG_HCTSIZ_XFRSIZ_Pos                (0U)
14716 #define USB_OTG_HCTSIZ_XFRSIZ_Msk                (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
14717 #define USB_OTG_HCTSIZ_XFRSIZ                    USB_OTG_HCTSIZ_XFRSIZ_Msk     /*!< Transfer size */
14718 #define USB_OTG_HCTSIZ_PKTCNT_Pos                (19U)
14719 #define USB_OTG_HCTSIZ_PKTCNT_Msk                (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
14720 #define USB_OTG_HCTSIZ_PKTCNT                    USB_OTG_HCTSIZ_PKTCNT_Msk     /*!< Packet count */
14721 #define USB_OTG_HCTSIZ_DOPING_Pos                (31U)
14722 #define USB_OTG_HCTSIZ_DOPING_Msk                (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
14723 #define USB_OTG_HCTSIZ_DOPING                    USB_OTG_HCTSIZ_DOPING_Msk     /*!< Do PING */
14724 #define USB_OTG_HCTSIZ_DPID_Pos                  (29U)
14725 #define USB_OTG_HCTSIZ_DPID_Msk                  (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
14726 #define USB_OTG_HCTSIZ_DPID                      USB_OTG_HCTSIZ_DPID_Msk       /*!< Data PID */
14727 #define USB_OTG_HCTSIZ_DPID_0                    (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
14728 #define USB_OTG_HCTSIZ_DPID_1                    (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
14729 
14730 /********************  Bit definition for USB_OTG_DIEPDMA register  ********************/
14731 #define USB_OTG_DIEPDMA_DMAADDR_Pos              (0U)
14732 #define USB_OTG_DIEPDMA_DMAADDR_Msk              (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
14733 #define USB_OTG_DIEPDMA_DMAADDR                  USB_OTG_DIEPDMA_DMAADDR_Msk   /*!< DMA address */
14734 
14735 /********************  Bit definition for USB_OTG_HCDMA register  ********************/
14736 #define USB_OTG_HCDMA_DMAADDR_Pos                (0U)
14737 #define USB_OTG_HCDMA_DMAADDR_Msk                (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
14738 #define USB_OTG_HCDMA_DMAADDR                    USB_OTG_HCDMA_DMAADDR_Msk     /*!< DMA address */
14739 
14740 /********************  Bit definition for USB_OTG_DTXFSTS register  ********************/
14741 #define USB_OTG_DTXFSTS_INEPTFSAV_Pos            (0U)
14742 #define USB_OTG_DTXFSTS_INEPTFSAV_Msk            (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
14743 #define USB_OTG_DTXFSTS_INEPTFSAV                USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
14744 
14745 /********************  Bit definition for USB_OTG_DIEPTXF register  ********************/
14746 #define USB_OTG_DIEPTXF_INEPTXSA_Pos             (0U)
14747 #define USB_OTG_DIEPTXF_INEPTXSA_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
14748 #define USB_OTG_DIEPTXF_INEPTXSA                 USB_OTG_DIEPTXF_INEPTXSA_Msk  /*!< IN endpoint FIFOx transmit RAM start address */
14749 #define USB_OTG_DIEPTXF_INEPTXFD_Pos             (16U)
14750 #define USB_OTG_DIEPTXF_INEPTXFD_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
14751 #define USB_OTG_DIEPTXF_INEPTXFD                 USB_OTG_DIEPTXF_INEPTXFD_Msk  /*!< IN endpoint TxFIFO depth */
14752 
14753 /********************  Bit definition for USB_OTG_DOEPCTL register  ********************/
14754 
14755 #define USB_OTG_DOEPCTL_MPSIZ_Pos                (0U)
14756 #define USB_OTG_DOEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
14757 #define USB_OTG_DOEPCTL_MPSIZ                    USB_OTG_DOEPCTL_MPSIZ_Msk     /*!< Maximum packet size */          /*!<Bit 1 */
14758 #define USB_OTG_DOEPCTL_USBAEP_Pos               (15U)
14759 #define USB_OTG_DOEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
14760 #define USB_OTG_DOEPCTL_USBAEP                   USB_OTG_DOEPCTL_USBAEP_Msk    /*!< USB active endpoint */
14761 #define USB_OTG_DOEPCTL_NAKSTS_Pos               (17U)
14762 #define USB_OTG_DOEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
14763 #define USB_OTG_DOEPCTL_NAKSTS                   USB_OTG_DOEPCTL_NAKSTS_Msk    /*!< NAK status */
14764 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos       (28U)
14765 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
14766 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM           USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
14767 #define USB_OTG_DOEPCTL_SODDFRM_Pos              (29U)
14768 #define USB_OTG_DOEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
14769 #define USB_OTG_DOEPCTL_SODDFRM                  USB_OTG_DOEPCTL_SODDFRM_Msk   /*!< Set odd frame */
14770 #define USB_OTG_DOEPCTL_EPTYP_Pos                (18U)
14771 #define USB_OTG_DOEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
14772 #define USB_OTG_DOEPCTL_EPTYP                    USB_OTG_DOEPCTL_EPTYP_Msk     /*!< Endpoint type */
14773 #define USB_OTG_DOEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
14774 #define USB_OTG_DOEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
14775 #define USB_OTG_DOEPCTL_SNPM_Pos                 (20U)
14776 #define USB_OTG_DOEPCTL_SNPM_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
14777 #define USB_OTG_DOEPCTL_SNPM                     USB_OTG_DOEPCTL_SNPM_Msk      /*!< Snoop mode */
14778 #define USB_OTG_DOEPCTL_STALL_Pos                (21U)
14779 #define USB_OTG_DOEPCTL_STALL_Msk                (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
14780 #define USB_OTG_DOEPCTL_STALL                    USB_OTG_DOEPCTL_STALL_Msk     /*!< STALL handshake */
14781 #define USB_OTG_DOEPCTL_CNAK_Pos                 (26U)
14782 #define USB_OTG_DOEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
14783 #define USB_OTG_DOEPCTL_CNAK                     USB_OTG_DOEPCTL_CNAK_Msk      /*!< Clear NAK */
14784 #define USB_OTG_DOEPCTL_SNAK_Pos                 (27U)
14785 #define USB_OTG_DOEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
14786 #define USB_OTG_DOEPCTL_SNAK                     USB_OTG_DOEPCTL_SNAK_Msk      /*!< Set NAK */
14787 #define USB_OTG_DOEPCTL_EPDIS_Pos                (30U)
14788 #define USB_OTG_DOEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
14789 #define USB_OTG_DOEPCTL_EPDIS                    USB_OTG_DOEPCTL_EPDIS_Msk     /*!< Endpoint disable */
14790 #define USB_OTG_DOEPCTL_EPENA_Pos                (31U)
14791 #define USB_OTG_DOEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
14792 #define USB_OTG_DOEPCTL_EPENA                    USB_OTG_DOEPCTL_EPENA_Msk     /*!< Endpoint enable */
14793 
14794 /********************  Bit definition for USB_OTG_DOEPINT register  ********************/
14795 #define USB_OTG_DOEPINT_XFRC_Pos                 (0U)
14796 #define USB_OTG_DOEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
14797 #define USB_OTG_DOEPINT_XFRC                     USB_OTG_DOEPINT_XFRC_Msk      /*!< Transfer completed interrupt */
14798 #define USB_OTG_DOEPINT_EPDISD_Pos               (1U)
14799 #define USB_OTG_DOEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
14800 #define USB_OTG_DOEPINT_EPDISD                   USB_OTG_DOEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */
14801 #define USB_OTG_DOEPINT_AHBERR_Pos               (2U)
14802 #define USB_OTG_DOEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */
14803 #define USB_OTG_DOEPINT_AHBERR                   USB_OTG_DOEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an OUT transaction */
14804 #define USB_OTG_DOEPINT_STUP_Pos                 (3U)
14805 #define USB_OTG_DOEPINT_STUP_Msk                 (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
14806 #define USB_OTG_DOEPINT_STUP                     USB_OTG_DOEPINT_STUP_Msk      /*!< SETUP phase done */
14807 #define USB_OTG_DOEPINT_OTEPDIS_Pos              (4U)
14808 #define USB_OTG_DOEPINT_OTEPDIS_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
14809 #define USB_OTG_DOEPINT_OTEPDIS                  USB_OTG_DOEPINT_OTEPDIS_Msk   /*!< OUT token received when endpoint disabled */
14810 #define USB_OTG_DOEPINT_OTEPSPR_Pos              (5U)
14811 #define USB_OTG_DOEPINT_OTEPSPR_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */
14812 #define USB_OTG_DOEPINT_OTEPSPR                  USB_OTG_DOEPINT_OTEPSPR_Msk   /*!< Status Phase Received For Control Write */
14813 #define USB_OTG_DOEPINT_B2BSTUP_Pos              (6U)
14814 #define USB_OTG_DOEPINT_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
14815 #define USB_OTG_DOEPINT_B2BSTUP                  USB_OTG_DOEPINT_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received */
14816 #define USB_OTG_DOEPINT_OUTPKTERR_Pos            (8U)
14817 #define USB_OTG_DOEPINT_OUTPKTERR_Msk            (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */
14818 #define USB_OTG_DOEPINT_OUTPKTERR                USB_OTG_DOEPINT_OUTPKTERR_Msk   /*!< OUT packet error */
14819 #define USB_OTG_DOEPINT_NAK_Pos                  (13U)
14820 #define USB_OTG_DOEPINT_NAK_Msk                  (0x1UL << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */
14821 #define USB_OTG_DOEPINT_NAK                      USB_OTG_DOEPINT_NAK_Msk   /*!< NAK Packet is transmitted by the device */
14822 #define USB_OTG_DOEPINT_NYET_Pos                 (14U)
14823 #define USB_OTG_DOEPINT_NYET_Msk                 (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
14824 #define USB_OTG_DOEPINT_NYET                     USB_OTG_DOEPINT_NYET_Msk      /*!< NYET interrupt */
14825 #define USB_OTG_DOEPINT_STPKTRX_Pos              (15U)
14826 #define USB_OTG_DOEPINT_STPKTRX_Msk              (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */
14827 #define USB_OTG_DOEPINT_STPKTRX                  USB_OTG_DOEPINT_STPKTRX_Msk   /*!< Setup Packet Received */
14828 /********************  Bit definition for USB_OTG_DOEPTSIZ register  ********************/
14829 
14830 #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos              (0U)
14831 #define USB_OTG_DOEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
14832 #define USB_OTG_DOEPTSIZ_XFRSIZ                  USB_OTG_DOEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */
14833 #define USB_OTG_DOEPTSIZ_PKTCNT_Pos              (19U)
14834 #define USB_OTG_DOEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
14835 #define USB_OTG_DOEPTSIZ_PKTCNT                  USB_OTG_DOEPTSIZ_PKTCNT_Msk   /*!< Packet count */
14836 
14837 #define USB_OTG_DOEPTSIZ_STUPCNT_Pos             (29U)
14838 #define USB_OTG_DOEPTSIZ_STUPCNT_Msk             (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
14839 #define USB_OTG_DOEPTSIZ_STUPCNT                 USB_OTG_DOEPTSIZ_STUPCNT_Msk  /*!< SETUP packet count */
14840 #define USB_OTG_DOEPTSIZ_STUPCNT_0               (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
14841 #define USB_OTG_DOEPTSIZ_STUPCNT_1               (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
14842 
14843 /********************  Bit definition for PCGCCTL register  ********************/
14844 #define USB_OTG_PCGCCTL_STOPCLK_Pos              (0U)
14845 #define USB_OTG_PCGCCTL_STOPCLK_Msk              (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
14846 #define USB_OTG_PCGCCTL_STOPCLK                  USB_OTG_PCGCCTL_STOPCLK_Msk   /*!< SETUP packet count */
14847 #define USB_OTG_PCGCCTL_GATECLK_Pos              (1U)
14848 #define USB_OTG_PCGCCTL_GATECLK_Msk              (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
14849 #define USB_OTG_PCGCCTL_GATECLK                  USB_OTG_PCGCCTL_GATECLK_Msk   /*!<Bit 0 */
14850 #define USB_OTG_PCGCCTL_PHYSUSP_Pos              (4U)
14851 #define USB_OTG_PCGCCTL_PHYSUSP_Msk              (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
14852 #define USB_OTG_PCGCCTL_PHYSUSP                  USB_OTG_PCGCCTL_PHYSUSP_Msk   /*!<Bit 1 */
14853 
14854 /* Legacy define */
14855 /********************  Bit definition for OTG register  ********************/
14856 #define USB_OTG_CHNUM_Pos                        (0U)
14857 #define USB_OTG_CHNUM_Msk                        (0xFUL << USB_OTG_CHNUM_Pos)   /*!< 0x0000000F */
14858 #define USB_OTG_CHNUM                            USB_OTG_CHNUM_Msk             /*!< Channel number */
14859 #define USB_OTG_CHNUM_0                          (0x1UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000001 */
14860 #define USB_OTG_CHNUM_1                          (0x2UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000002 */
14861 #define USB_OTG_CHNUM_2                          (0x4UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000004 */
14862 #define USB_OTG_CHNUM_3                          (0x8UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000008 */
14863 #define USB_OTG_BCNT_Pos                         (4U)
14864 #define USB_OTG_BCNT_Msk                         (0x7FFUL << USB_OTG_BCNT_Pos)  /*!< 0x00007FF0 */
14865 #define USB_OTG_BCNT                             USB_OTG_BCNT_Msk              /*!< Byte count */
14866 
14867 #define USB_OTG_DPID_Pos                         (15U)
14868 #define USB_OTG_DPID_Msk                         (0x3UL << USB_OTG_DPID_Pos)    /*!< 0x00018000 */
14869 #define USB_OTG_DPID                             USB_OTG_DPID_Msk              /*!< Data PID */
14870 #define USB_OTG_DPID_0                           (0x1UL << USB_OTG_DPID_Pos)    /*!< 0x00008000 */
14871 #define USB_OTG_DPID_1                           (0x2UL << USB_OTG_DPID_Pos)    /*!< 0x00010000 */
14872 
14873 #define USB_OTG_PKTSTS_Pos                       (17U)
14874 #define USB_OTG_PKTSTS_Msk                       (0xFUL << USB_OTG_PKTSTS_Pos)  /*!< 0x001E0000 */
14875 #define USB_OTG_PKTSTS                           USB_OTG_PKTSTS_Msk            /*!< Packet status */
14876 #define USB_OTG_PKTSTS_0                         (0x1UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00020000 */
14877 #define USB_OTG_PKTSTS_1                         (0x2UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00040000 */
14878 #define USB_OTG_PKTSTS_2                         (0x4UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00080000 */
14879 #define USB_OTG_PKTSTS_3                         (0x8UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00100000 */
14880 
14881 #define USB_OTG_EPNUM_Pos                        (0U)
14882 #define USB_OTG_EPNUM_Msk                        (0xFUL << USB_OTG_EPNUM_Pos)   /*!< 0x0000000F */
14883 #define USB_OTG_EPNUM                            USB_OTG_EPNUM_Msk             /*!< Endpoint number */
14884 #define USB_OTG_EPNUM_0                          (0x1UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000001 */
14885 #define USB_OTG_EPNUM_1                          (0x2UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000002 */
14886 #define USB_OTG_EPNUM_2                          (0x4UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000004 */
14887 #define USB_OTG_EPNUM_3                          (0x8UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000008 */
14888 
14889 #define USB_OTG_FRMNUM_Pos                       (21U)
14890 #define USB_OTG_FRMNUM_Msk                       (0xFUL << USB_OTG_FRMNUM_Pos)  /*!< 0x01E00000 */
14891 #define USB_OTG_FRMNUM                           USB_OTG_FRMNUM_Msk            /*!< Frame number */
14892 #define USB_OTG_FRMNUM_0                         (0x1UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00200000 */
14893 #define USB_OTG_FRMNUM_1                         (0x2UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00400000 */
14894 #define USB_OTG_FRMNUM_2                         (0x4UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00800000 */
14895 #define USB_OTG_FRMNUM_3                         (0x8UL << USB_OTG_FRMNUM_Pos)  /*!< 0x01000000 */
14896 /**
14897   * @}
14898   */
14899 
14900 /**
14901   * @}
14902   */
14903 
14904 /** @addtogroup Exported_macros
14905   * @{
14906   */
14907 
14908 /******************************* ADC Instances ********************************/
14909 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
14910 
14911 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
14912 
14913 /******************************* CAN Instances ********************************/
14914 #define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
14915                                        ((INSTANCE) == CAN2) || \
14916                                        ((INSTANCE) == CAN3))
14917 
14918 /****************************** DFSDM Instances *******************************/
14919 #define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
14920                                                 ((INSTANCE) == DFSDM1_Filter1) || \
14921                                                 ((INSTANCE) == DFSDM2_Filter0) || \
14922                                                 ((INSTANCE) == DFSDM2_Filter1) || \
14923                                                 ((INSTANCE) == DFSDM2_Filter2) || \
14924                                                 ((INSTANCE) == DFSDM2_Filter3))
14925 
14926 #define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
14927                                                  ((INSTANCE) == DFSDM1_Channel1) || \
14928                                                  ((INSTANCE) == DFSDM1_Channel2) || \
14929                                                  ((INSTANCE) == DFSDM1_Channel3) || \
14930                                                  ((INSTANCE) == DFSDM2_Channel0) || \
14931                                                  ((INSTANCE) == DFSDM2_Channel1) || \
14932                                                  ((INSTANCE) == DFSDM2_Channel2) || \
14933                                                  ((INSTANCE) == DFSDM2_Channel3) || \
14934                                                  ((INSTANCE) == DFSDM2_Channel4) || \
14935                                                  ((INSTANCE) == DFSDM2_Channel5) || \
14936                                                  ((INSTANCE) == DFSDM2_Channel6) || \
14937                                                  ((INSTANCE) == DFSDM2_Channel7))
14938 /******************************* CRC Instances ********************************/
14939 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
14940 
14941 /******************************* DAC Instances ********************************/
14942 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
14943 
14944 
14945 /******************************** DMA Instances *******************************/
14946 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
14947                                               ((INSTANCE) == DMA1_Stream1) || \
14948                                               ((INSTANCE) == DMA1_Stream2) || \
14949                                               ((INSTANCE) == DMA1_Stream3) || \
14950                                               ((INSTANCE) == DMA1_Stream4) || \
14951                                               ((INSTANCE) == DMA1_Stream5) || \
14952                                               ((INSTANCE) == DMA1_Stream6) || \
14953                                               ((INSTANCE) == DMA1_Stream7) || \
14954                                               ((INSTANCE) == DMA2_Stream0) || \
14955                                               ((INSTANCE) == DMA2_Stream1) || \
14956                                               ((INSTANCE) == DMA2_Stream2) || \
14957                                               ((INSTANCE) == DMA2_Stream3) || \
14958                                               ((INSTANCE) == DMA2_Stream4) || \
14959                                               ((INSTANCE) == DMA2_Stream5) || \
14960                                               ((INSTANCE) == DMA2_Stream6) || \
14961                                               ((INSTANCE) == DMA2_Stream7))
14962 
14963 /******************************* GPIO Instances *******************************/
14964 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
14965                                         ((INSTANCE) == GPIOB) || \
14966                                         ((INSTANCE) == GPIOC) || \
14967                                         ((INSTANCE) == GPIOD) || \
14968                                         ((INSTANCE) == GPIOE) || \
14969                                         ((INSTANCE) == GPIOF) || \
14970                                         ((INSTANCE) == GPIOG) || \
14971                                         ((INSTANCE) == GPIOH))
14972 
14973 /******************************** I2C Instances *******************************/
14974 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
14975                                        ((INSTANCE) == I2C2) || \
14976                                        ((INSTANCE) == I2C3))
14977 
14978 /******************************* SMBUS Instances ******************************/
14979 #define IS_SMBUS_ALL_INSTANCE         IS_I2C_ALL_INSTANCE
14980 
14981 /******************************** I2S Instances *******************************/
14982 #define IS_I2S_APB1_INSTANCE(INSTANCE)  (((INSTANCE) == SPI2) || \
14983                                          ((INSTANCE) == SPI3))
14984 
14985 #define IS_I2S_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == SPI1) || \
14986                                         ((INSTANCE) == SPI2) || \
14987                                         ((INSTANCE) == SPI3) || \
14988                                         ((INSTANCE) == SPI4) || \
14989                                         ((INSTANCE) == SPI5))
14990 
14991 /*************************** I2S Extended Instances ***************************/
14992 #define IS_I2S_EXT_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2S2ext)|| \
14993                                            ((INSTANCE) == I2S3ext))
14994 /* Legacy Defines */
14995 #define IS_I2S_ALL_INSTANCE_EXT    IS_I2S_EXT_ALL_INSTANCE
14996 
14997 /******************************* LPTIM Instances ******************************/
14998 #define IS_LPTIM_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
14999 
15000 /******************************* RNG Instances ********************************/
15001 #define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)
15002 
15003 /****************************** RTC Instances *********************************/
15004 #define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
15005 
15006 
15007 /******************************** SPI Instances *******************************/
15008 
15009 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
15010                                        ((INSTANCE) == SPI2) || \
15011                                        ((INSTANCE) == SPI3) || \
15012                                        ((INSTANCE) == SPI4) || \
15013                                        ((INSTANCE) == SPI5))
15014 
15015 
15016 /*************************** SPI Extended Instances ***************************/
15017 #define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1)    || \
15018                                            ((INSTANCE) == SPI2)    || \
15019                                            ((INSTANCE) == SPI3)    || \
15020                                            ((INSTANCE) == SPI4)    || \
15021                                            ((INSTANCE) == SPI5)    || \
15022                                            ((INSTANCE) == I2S2ext) || \
15023                                            ((INSTANCE) == I2S3ext))
15024 /******************************* SAI Instances ********************************/
15025 #define IS_SAI_ALL_INSTANCE(PERIPH) (((PERIPH) == SAI1_Block_A) || \
15026                                      ((PERIPH) == SAI1_Block_B))
15027 /****************** TIM Instances : All supported instances *******************/
15028 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)  || \
15029                                     ((INSTANCE) == TIM2) || \
15030                                     ((INSTANCE) == TIM3) || \
15031                                     ((INSTANCE) == TIM4) || \
15032                                     ((INSTANCE) == TIM5) || \
15033                                     ((INSTANCE) == TIM6) || \
15034                                     ((INSTANCE) == TIM7) || \
15035                                     ((INSTANCE) == TIM8) || \
15036                                     ((INSTANCE) == TIM9) || \
15037                                     ((INSTANCE) == TIM10)|| \
15038                                     ((INSTANCE) == TIM11)|| \
15039                                     ((INSTANCE) == TIM12)|| \
15040                                     ((INSTANCE) == TIM13)|| \
15041                                     ((INSTANCE) == TIM14))
15042 
15043 /************* TIM Instances : at least 1 capture/compare channel *************/
15044 #define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
15045                                          ((INSTANCE) == TIM2)  || \
15046                                          ((INSTANCE) == TIM3)  || \
15047                                          ((INSTANCE) == TIM4)  || \
15048                                          ((INSTANCE) == TIM5)  || \
15049                                          ((INSTANCE) == TIM8)  || \
15050                                          ((INSTANCE) == TIM9)  || \
15051                                          ((INSTANCE) == TIM10) || \
15052                                          ((INSTANCE) == TIM11) || \
15053                                          ((INSTANCE) == TIM12) || \
15054                                          ((INSTANCE) == TIM13) || \
15055                                          ((INSTANCE) == TIM14))
15056 
15057 /************ TIM Instances : at least 2 capture/compare channels *************/
15058 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15059                                        ((INSTANCE) == TIM2) || \
15060                                        ((INSTANCE) == TIM3) || \
15061                                        ((INSTANCE) == TIM4) || \
15062                                        ((INSTANCE) == TIM5) || \
15063                                        ((INSTANCE) == TIM8) || \
15064                                        ((INSTANCE) == TIM9) || \
15065                                        ((INSTANCE) == TIM12))
15066 
15067 /************ TIM Instances : at least 3 capture/compare channels *************/
15068 #define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \
15069                                          ((INSTANCE) == TIM2) || \
15070                                          ((INSTANCE) == TIM3) || \
15071                                          ((INSTANCE) == TIM4) || \
15072                                          ((INSTANCE) == TIM5) || \
15073                                          ((INSTANCE) == TIM8))
15074 
15075 /************ TIM Instances : at least 4 capture/compare channels *************/
15076 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15077                                        ((INSTANCE) == TIM2) || \
15078                                        ((INSTANCE) == TIM3) || \
15079                                        ((INSTANCE) == TIM4) || \
15080                                        ((INSTANCE) == TIM5) || \
15081                                        ((INSTANCE) == TIM8))
15082 
15083 /******************** TIM Instances : Advanced-control timers *****************/
15084 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15085                                            ((INSTANCE) == TIM8))
15086 
15087 /******************* TIM Instances : Timer input XOR function *****************/
15088 #define IS_TIM_XOR_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \
15089                                          ((INSTANCE) == TIM2) || \
15090                                          ((INSTANCE) == TIM3) || \
15091                                          ((INSTANCE) == TIM4) || \
15092                                          ((INSTANCE) == TIM5) || \
15093                                          ((INSTANCE) == TIM8))
15094 
15095 /****************** TIM Instances : DMA requests generation (UDE) *************/
15096 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15097                                        ((INSTANCE) == TIM2) || \
15098                                        ((INSTANCE) == TIM3) || \
15099                                        ((INSTANCE) == TIM4) || \
15100                                        ((INSTANCE) == TIM5) || \
15101                                        ((INSTANCE) == TIM6) || \
15102                                        ((INSTANCE) == TIM7) || \
15103                                        ((INSTANCE) == TIM8))
15104 
15105 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
15106 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15107                                           ((INSTANCE) == TIM2) || \
15108                                           ((INSTANCE) == TIM3) || \
15109                                           ((INSTANCE) == TIM4) || \
15110                                           ((INSTANCE) == TIM5) || \
15111                                           ((INSTANCE) == TIM8))
15112 
15113 /************ TIM Instances : DMA requests generation (COMDE) *****************/
15114 #define IS_TIM_CCDMA_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
15115                                           ((INSTANCE) == TIM2) || \
15116                                           ((INSTANCE) == TIM3) || \
15117                                           ((INSTANCE) == TIM4) || \
15118                                           ((INSTANCE) == TIM5) || \
15119                                           ((INSTANCE) == TIM8))
15120 
15121 /******************** TIM Instances : DMA burst feature ***********************/
15122 #define IS_TIM_DMABURST_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
15123                                              ((INSTANCE) == TIM2) || \
15124                                              ((INSTANCE) == TIM3) || \
15125                                              ((INSTANCE) == TIM4) || \
15126                                              ((INSTANCE) == TIM5) || \
15127                                              ((INSTANCE) == TIM8))
15128 
15129 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
15130 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)  || \
15131                                           ((INSTANCE) == TIM2)  || \
15132                                           ((INSTANCE) == TIM3)  || \
15133                                           ((INSTANCE) == TIM4)  || \
15134                                           ((INSTANCE) == TIM5)  || \
15135                                           ((INSTANCE) == TIM6)  || \
15136                                           ((INSTANCE) == TIM7)  || \
15137                                           ((INSTANCE) == TIM8))
15138 
15139 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
15140 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15141                                          ((INSTANCE) == TIM2) || \
15142                                          ((INSTANCE) == TIM3) || \
15143                                          ((INSTANCE) == TIM4) || \
15144                                          ((INSTANCE) == TIM5) || \
15145                                          ((INSTANCE) == TIM8) || \
15146                                          ((INSTANCE) == TIM9) || \
15147                                          ((INSTANCE) == TIM12))
15148 /********************** TIM Instances : 32 bit Counter ************************/
15149 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
15150                                               ((INSTANCE) == TIM5))
15151 
15152 /***************** TIM Instances : external trigger input availabe ************/
15153 #define IS_TIM_ETR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
15154                                         ((INSTANCE) == TIM2) || \
15155                                         ((INSTANCE) == TIM3) || \
15156                                         ((INSTANCE) == TIM4) || \
15157                                         ((INSTANCE) == TIM5) || \
15158                                         ((INSTANCE) == TIM8))
15159 
15160 /****************** TIM Instances : remapping capability **********************/
15161 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
15162                                          ((INSTANCE) == TIM5)  || \
15163                                          ((INSTANCE) == TIM11))
15164 
15165 /******************* TIM Instances : output(s) available **********************/
15166 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
15167     ((((INSTANCE) == TIM1) &&                  \
15168      (((CHANNEL) == TIM_CHANNEL_1) ||          \
15169       ((CHANNEL) == TIM_CHANNEL_2) ||          \
15170       ((CHANNEL) == TIM_CHANNEL_3) ||          \
15171       ((CHANNEL) == TIM_CHANNEL_4)))           \
15172     ||                                         \
15173     (((INSTANCE) == TIM2) &&                   \
15174      (((CHANNEL) == TIM_CHANNEL_1) ||          \
15175       ((CHANNEL) == TIM_CHANNEL_2) ||          \
15176       ((CHANNEL) == TIM_CHANNEL_3) ||          \
15177       ((CHANNEL) == TIM_CHANNEL_4)))           \
15178     ||                                         \
15179     (((INSTANCE) == TIM3) &&                   \
15180      (((CHANNEL) == TIM_CHANNEL_1) ||          \
15181       ((CHANNEL) == TIM_CHANNEL_2) ||          \
15182       ((CHANNEL) == TIM_CHANNEL_3) ||          \
15183       ((CHANNEL) == TIM_CHANNEL_4)))           \
15184     ||                                         \
15185     (((INSTANCE) == TIM4) &&                   \
15186      (((CHANNEL) == TIM_CHANNEL_1) ||          \
15187       ((CHANNEL) == TIM_CHANNEL_2) ||          \
15188       ((CHANNEL) == TIM_CHANNEL_3) ||          \
15189       ((CHANNEL) == TIM_CHANNEL_4)))           \
15190     ||                                         \
15191     (((INSTANCE) == TIM5) &&                   \
15192      (((CHANNEL) == TIM_CHANNEL_1) ||          \
15193       ((CHANNEL) == TIM_CHANNEL_2) ||          \
15194       ((CHANNEL) == TIM_CHANNEL_3) ||          \
15195       ((CHANNEL) == TIM_CHANNEL_4)))           \
15196     ||                                         \
15197     (((INSTANCE) == TIM8) &&                   \
15198      (((CHANNEL) == TIM_CHANNEL_1) ||          \
15199       ((CHANNEL) == TIM_CHANNEL_2) ||          \
15200       ((CHANNEL) == TIM_CHANNEL_3) ||          \
15201       ((CHANNEL) == TIM_CHANNEL_4)))           \
15202     ||                                         \
15203     (((INSTANCE) == TIM9) &&                   \
15204      (((CHANNEL) == TIM_CHANNEL_1) ||          \
15205       ((CHANNEL) == TIM_CHANNEL_2)))           \
15206     ||                                         \
15207     (((INSTANCE) == TIM10) &&                  \
15208      (((CHANNEL) == TIM_CHANNEL_1)))           \
15209     ||                                         \
15210     (((INSTANCE) == TIM11) &&                  \
15211      (((CHANNEL) == TIM_CHANNEL_1)))           \
15212     ||                                         \
15213     (((INSTANCE) == TIM12) &&                  \
15214      (((CHANNEL) == TIM_CHANNEL_1) ||          \
15215       ((CHANNEL) == TIM_CHANNEL_2)))           \
15216     ||                                         \
15217     (((INSTANCE) == TIM13) &&                  \
15218      (((CHANNEL) == TIM_CHANNEL_1)))           \
15219     ||                                         \
15220     (((INSTANCE) == TIM14) &&                  \
15221      (((CHANNEL) == TIM_CHANNEL_1))))
15222 
15223 /************ TIM Instances : complementary output(s) available ***************/
15224 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
15225    ((((INSTANCE) == TIM1) &&                    \
15226      (((CHANNEL) == TIM_CHANNEL_1) ||           \
15227       ((CHANNEL) == TIM_CHANNEL_2) ||           \
15228       ((CHANNEL) == TIM_CHANNEL_3)))            \
15229     ||                                          \
15230     (((INSTANCE) == TIM8) &&                    \
15231      (((CHANNEL) == TIM_CHANNEL_1) ||           \
15232       ((CHANNEL) == TIM_CHANNEL_2) ||           \
15233       ((CHANNEL) == TIM_CHANNEL_3))))
15234 
15235 /****************** TIM Instances : supporting counting mode selection ********/
15236 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
15237                                                         ((INSTANCE) == TIM2) || \
15238                                                         ((INSTANCE) == TIM3) || \
15239                                                         ((INSTANCE) == TIM4) || \
15240                                                         ((INSTANCE) == TIM5) || \
15241                                                         ((INSTANCE) == TIM8))
15242 
15243 /****************** TIM Instances : supporting clock division *****************/
15244 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)  || \
15245                                                   ((INSTANCE) == TIM2) || \
15246                                                   ((INSTANCE) == TIM3) || \
15247                                                   ((INSTANCE) == TIM4) || \
15248                                                   ((INSTANCE) == TIM5) || \
15249                                                   ((INSTANCE) == TIM8) || \
15250                                                   ((INSTANCE) == TIM9) || \
15251                                                   ((INSTANCE) == TIM10)|| \
15252                                                   ((INSTANCE) == TIM11)|| \
15253                                                   ((INSTANCE) == TIM12)|| \
15254                                                   ((INSTANCE) == TIM13)|| \
15255                                                   ((INSTANCE) == TIM14))
15256 
15257 /****************** TIM Instances : supporting commutation event generation ***/
15258 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)|| \
15259                                                      ((INSTANCE) == TIM8))
15260 
15261 
15262 /****************** TIM Instances : supporting OCxREF clear *******************/
15263 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)        (((INSTANCE) == TIM1) || \
15264                                                        ((INSTANCE) == TIM2) || \
15265                                                        ((INSTANCE) == TIM3) || \
15266                                                        ((INSTANCE) == TIM4) || \
15267                                                        ((INSTANCE) == TIM5) || \
15268                                                        ((INSTANCE) == TIM8))
15269 
15270 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
15271 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15272                                                         ((INSTANCE) == TIM2) || \
15273                                                         ((INSTANCE) == TIM3) || \
15274                                                         ((INSTANCE) == TIM4) || \
15275                                                         ((INSTANCE) == TIM5) || \
15276                                                         ((INSTANCE) == TIM8) || \
15277                                                         ((INSTANCE) == TIM9) || \
15278                                                         ((INSTANCE) == TIM12))
15279 
15280 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
15281 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15282                                                         ((INSTANCE) == TIM2) || \
15283                                                         ((INSTANCE) == TIM3) || \
15284                                                         ((INSTANCE) == TIM4) || \
15285                                                         ((INSTANCE) == TIM5) || \
15286                                                         ((INSTANCE) == TIM8))
15287 
15288 /****** TIM Instances : supporting external clock mode 1 for TIX inputs ******/
15289 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1) || \
15290                                                         ((INSTANCE) == TIM2) || \
15291                                                         ((INSTANCE) == TIM3) || \
15292                                                         ((INSTANCE) == TIM4) || \
15293                                                         ((INSTANCE) == TIM5) || \
15294                                                         ((INSTANCE) == TIM8) || \
15295                                                         ((INSTANCE) == TIM9) || \
15296                                                         ((INSTANCE) == TIM12))
15297 
15298 /********** TIM Instances : supporting internal trigger inputs(ITRX) *********/
15299 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1) || \
15300                                                         ((INSTANCE) == TIM2) || \
15301                                                         ((INSTANCE) == TIM3) || \
15302                                                         ((INSTANCE) == TIM4) || \
15303                                                         ((INSTANCE) == TIM5) || \
15304                                                         ((INSTANCE) == TIM8) || \
15305                                                         ((INSTANCE) == TIM9) || \
15306                                                         ((INSTANCE) == TIM12))
15307 
15308 /****************** TIM Instances : supporting repetition counter *************/
15309 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
15310                                                        ((INSTANCE) == TIM8))
15311 
15312 /****************** TIM Instances : supporting encoder interface **************/
15313 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
15314                                                       ((INSTANCE) == TIM2) || \
15315                                                       ((INSTANCE) == TIM3) || \
15316                                                       ((INSTANCE) == TIM4) || \
15317                                                       ((INSTANCE) == TIM5) || \
15318                                                       ((INSTANCE) == TIM8) || \
15319                                                       ((INSTANCE) == TIM9))
15320 /****************** TIM Instances : supporting Hall sensor interface **********/
15321 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
15322                                                           ((INSTANCE) == TIM2) || \
15323                                                           ((INSTANCE) == TIM3) || \
15324                                                           ((INSTANCE) == TIM4) || \
15325                                                           ((INSTANCE) == TIM5) || \
15326                                                           ((INSTANCE) == TIM8))
15327 /****************** TIM Instances : supporting the break function *************/
15328 #define IS_TIM_BREAK_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
15329                                           ((INSTANCE) == TIM8))
15330 
15331 /******************** USART Instances : Synchronous mode **********************/
15332 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15333                                      ((INSTANCE) == USART2) || \
15334                                      ((INSTANCE) == USART3) || \
15335                                      ((INSTANCE) == USART6))
15336 
15337 /******************** UART Instances : Half-Duplex mode **********************/
15338 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15339                                                ((INSTANCE) == USART2) || \
15340                                                ((INSTANCE) == USART3) || \
15341                                                ((INSTANCE) == UART4)  || \
15342                                                ((INSTANCE) == UART5)  || \
15343                                                ((INSTANCE) == USART6) || \
15344                                                ((INSTANCE) == UART7)  || \
15345                                                ((INSTANCE) == UART8)  || \
15346                                                ((INSTANCE) == UART9)  || \
15347                                                ((INSTANCE) == UART10))
15348 
15349 /* Legacy defines */
15350 #define IS_UART_INSTANCE          IS_UART_HALFDUPLEX_INSTANCE
15351 
15352 /****************** UART Instances : Hardware Flow control ********************/
15353 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15354                                            ((INSTANCE) == USART2) || \
15355                                            ((INSTANCE) == USART3) || \
15356                                            ((INSTANCE) == USART6))
15357 /******************** UART Instances : LIN mode **********************/
15358 #define IS_UART_LIN_INSTANCE          IS_UART_HALFDUPLEX_INSTANCE
15359 
15360 /********************* UART Instances : Smart card mode ***********************/
15361 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15362                                          ((INSTANCE) == USART2) || \
15363                                          ((INSTANCE) == USART3) || \
15364                                          ((INSTANCE) == USART6))
15365 
15366 /*********************** UART Instances : IRDA mode ***************************/
15367 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15368                                     ((INSTANCE) == USART2) || \
15369                                     ((INSTANCE) == USART3) || \
15370                                     ((INSTANCE) == UART4)  || \
15371                                     ((INSTANCE) == UART5)  || \
15372                                     ((INSTANCE) == USART6) || \
15373                                     ((INSTANCE) == UART7)  || \
15374                                     ((INSTANCE) == UART8)  || \
15375                                     ((INSTANCE) == UART9)  || \
15376                                     ((INSTANCE) == UART10))
15377 
15378 /*********************** PCD Instances ****************************************/
15379 #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
15380 
15381 /*********************** HCD Instances ****************************************/
15382 #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
15383 
15384 /****************************** SDIO Instances ********************************/
15385 #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
15386 
15387 /****************************** IWDG Instances ********************************/
15388 #define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
15389 
15390 /****************************** WWDG Instances ********************************/
15391 #define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
15392 
15393 
15394 /***************************** FMPI2C Instances *******************************/
15395 #define IS_FMPI2C_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FMPI2C1)
15396 #define IS_FMPSMBUS_ALL_INSTANCE         IS_FMPI2C_ALL_INSTANCE
15397 
15398 /****************************** QSPI Instances ********************************/
15399 #define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
15400 /****************************** USB Exported Constants ************************/
15401 #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR                12U
15402 #define USB_OTG_FS_MAX_IN_ENDPOINTS                    6U    /* Including EP0 */
15403 #define USB_OTG_FS_MAX_OUT_ENDPOINTS                   6U    /* Including EP0 */
15404 #define USB_OTG_FS_TOTAL_FIFO_SIZE                     1280U /* in Bytes */
15405 
15406 /*
15407  * @brief Specific devices reset values definitions
15408  */
15409 #define RCC_PLLCFGR_RST_VALUE              0x24003010U
15410 #define RCC_PLLI2SCFGR_RST_VALUE           0x24003010U
15411 
15412 #define RCC_MAX_FREQUENCY           100000000U         /*!< Max frequency of family in Hz*/
15413 #define RCC_MAX_FREQUENCY_SCALE1    RCC_MAX_FREQUENCY  /*!< Maximum frequency for system clock at power scale1, in Hz */
15414 #define RCC_MAX_FREQUENCY_SCALE2     84000000U         /*!< Maximum frequency for system clock at power scale2, in Hz */
15415 #define RCC_MAX_FREQUENCY_SCALE3     64000000U         /*!< Maximum frequency for system clock at power scale3, in Hz */
15416 #define RCC_PLLVCO_OUTPUT_MIN       100000000U       /*!< Frequency min for PLLVCO output, in Hz */
15417 #define RCC_PLLVCO_INPUT_MIN           950000U       /*!< Frequency min for PLLVCO input, in Hz  */
15418 #define RCC_PLLVCO_INPUT_MAX          2100000U       /*!< Frequency max for PLLVCO input, in Hz  */
15419 #define RCC_PLLVCO_OUTPUT_MAX       432000000U       /*!< Frequency max for PLLVCO output, in Hz */
15420 
15421 #define RCC_PLLN_MIN_VALUE                 50U
15422 #define RCC_PLLN_MAX_VALUE                432U
15423 
15424 #define FLASH_SCALE1_LATENCY1_FREQ   30000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 1  */
15425 #define FLASH_SCALE1_LATENCY2_FREQ   64000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 1  */
15426 #define FLASH_SCALE1_LATENCY3_FREQ   90000000U      /*!< HCLK frequency to set FLASH latency 3 in power scale 1  */
15427 
15428 #define FLASH_SCALE2_LATENCY1_FREQ   30000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 2  */
15429 #define FLASH_SCALE2_LATENCY2_FREQ   64000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 2  */
15430 
15431 #define FLASH_SCALE3_LATENCY1_FREQ   30000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 3  */
15432 #define FLASH_SCALE3_LATENCY2_FREQ   64000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 3  */
15433 
15434 
15435 /**
15436   * @}
15437   */
15438 
15439 /**
15440   * @}
15441   */
15442 
15443 /**
15444   * @}
15445   */
15446 
15447 #ifdef __cplusplus
15448 }
15449 #endif /* __cplusplus */
15450 
15451 #endif /* __STM32F413xx_H */
15452 
15453 
15454 
15455 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
15456