| /aosp_15_r20/external/intel-media-driver/media_softlet/agnostic/Xe_R/Xe_HPG_Base/hw/ |
| H A D | mhw_render_xe_hpg_impl.h | 236 _MHW_SETCMD_OVERRIDE_DECL(STATE_BASE_ADDRESS) in _MHW_SETCMD_OVERRIDE_DECL() argument
238 _MHW_SETCMD_CALLBASE(STATE_BASE_ADDRESS); in _MHW_SETCMD_OVERRIDE_DECL()
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| /aosp_15_r20/external/mesa3d/docs/drivers/ |
| H A D | anv.rst | 176 programmed in ``STATE_BASE_ADDRESS::Surface State Base Address`` or
181 tables we need to reposition ``STATE_BASE_ADDRESS::Surface State Base
185 relative to ``STATE_BASE_ADDRESS::Surface State Base Address`` so as
186 we change ``STATE_BASE_ADDRESS::Surface State Base Address`` we need
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| /aosp_15_r20/external/mesa3d/docs/relnotes/ |
| H A D | 13.0.5.rst | 146 - anv: Flush render cache before STATE_BASE_ADDRESS on gen7
147 - anv: Improve flushing around STATE_BASE_ADDRESS
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| H A D | 19.0.7.rst | 81 - anv: Set STATE_BASE_ADDRESS upper bounds on gen7
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| H A D | 19.1.1.rst | 82 - anv: Set STATE_BASE_ADDRESS upper bounds on gen7
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| H A D | 17.1.4.rst | 120 - i965: Do an end-of-pipe sync prior to STATE_BASE_ADDRESS
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| H A D | 22.3.7.rst | 99 - genxml: Fix STATE_BASE_ADDRESS::BindlessSurfaceStateSize field size
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| H A D | 23.0.1.rst | 154 - genxml: Fix STATE_BASE_ADDRESS::BindlessSurfaceStateSize field size
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| H A D | 19.3.0.rst | 2051 - iris: Set MOCS in all STATE_BASE_ADDRESS commands
2072 STATE_BASE_ADDRESS
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| H A D | 22.0.0.rst | 2442 - crocus: Tidy the ifdefs for emitting STATE_BASE_ADDRESS
2456 - i965: Port STATE_BASE_ADDRESS to genxml and fix bugs
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| /aosp_15_r20/external/intel-media-driver/media_softlet/agnostic/common/hw/ |
| H A D | mhw_render_itf.h | 37 DEF(STATE_BASE_ADDRESS); \
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| H A D | mhw_render_impl.h | 321 _MHW_SETCMD_OVERRIDE_DECL(STATE_BASE_ADDRESS) in _MHW_SETCMD_OVERRIDE_DECL() argument
323 _MHW_SETCMD_CALLBASE(STATE_BASE_ADDRESS); in _MHW_SETCMD_OVERRIDE_DECL()
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| H A D | mhw_render_cmdpar.h | 211 struct _MHW_PAR_T(STATE_BASE_ADDRESS) in _MHW_PAR_T() argument
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| /aosp_15_r20/external/mesa3d/src/intel/executor/ |
| H A D | executor_genx.c | 55 executor_batch_emit(GENX(STATE_BASE_ADDRESS), sba) { in emit_state_base_address()
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| /aosp_15_r20/external/intel-media-driver/media_softlet/agnostic/common/renderhal/ |
| H A D | renderhal_platform_interface_next.h | 468 MHW_SETPAR_DECL_HDR(STATE_BASE_ADDRESS);
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| H A D | renderhal_platform_interface_next.cpp | 89 SETPAR_AND_ADDCMD(STATE_BASE_ADDRESS, m_renderItf, pCmdBuffer); in SendStateBaseAddress()
1488 MHW_SETPAR_DECL_SRC(STATE_BASE_ADDRESS, XRenderHal_Platform_Interface_Next) in MHW_SETPAR_DECL_SRC() argument
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| /aosp_15_r20/external/libdrm/intel/tests/ |
| H A D | gen7-3d.batch-ref.txt | 11 0x12300028: 0x61010008: STATE_BASE_ADDRESS
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| H A D | gen4-3d.batch-ref.txt | 7 0x12300018: 0x61010004: STATE_BASE_ADDRESS
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| H A D | gm45-3d.batch-ref.txt | 7 0x12300018: 0x61010004: STATE_BASE_ADDRESS
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| H A D | gen5-3d.batch-ref.txt | 7 0x12300018: 0x61010006: STATE_BASE_ADDRESS
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| H A D | gen6-3d.batch-ref.txt | 34 0x12300084: 0x61010008: STATE_BASE_ADDRESS
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| /aosp_15_r20/external/mesa3d/src/intel/vulkan/ |
| H A D | genX_cmd_buffer.c | 82 struct GENX(STATE_BASE_ADDRESS) *sba) in fill_state_base_addr()
99 *sba = (struct GENX(STATE_BASE_ADDRESS)) { GENX(STATE_BASE_ADDRESS_header), }; in fill_state_base_addr()
234 struct GENX(STATE_BASE_ADDRESS) sba = {}; in genX()
275 anv_batch_emit(&cmd_buffer->batch, GENX(STATE_BASE_ADDRESS), _sba) { in genX()
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| H A D | genX_init_state.c | 238 anv_batch_emit(batch, GENX(STATE_BASE_ADDRESS), sba) { in init_common_queue_state()
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| /aosp_15_r20/external/mesa3d/src/gallium/drivers/iris/ |
| H A D | iris_state.c | 799 iris_emit_cmd(batch, GENX(STATE_BASE_ADDRESS), sba) { in init_state_base_address()
6072 iris_emit_cmd(batch, GENX(STATE_BASE_ADDRESS), sba) { in iris_update_binder_address()
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| /aosp_15_r20/external/mesa3d/src/intel/vulkan_hasvk/ |
| H A D | genX_cmd_buffer.c | 113 anv_batch_emit(&cmd_buffer->batch, GENX(STATE_BASE_ADDRESS), sba) { in genX()
|