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/linux-6.14.4/drivers/usb/common/
Dulpi.c1 // SPDX-License-Identifier: GPL-2.0
3 * ulpi.c - USB ULPI PHY bus
10 #include <linux/ulpi/interface.h>
11 #include <linux/ulpi/driver.h>
12 #include <linux/ulpi/regs.h>
19 #include <linux/clk/clk-conf.h>
21 /* -------------------------------------------------------------------------- */
23 int ulpi_read(struct ulpi *ulpi, u8 addr) in ulpi_read() argument
25 return ulpi->ops->read(ulpi->dev.parent, addr); in ulpi_read()
29 int ulpi_write(struct ulpi *ulpi, u8 addr, u8 val) in ulpi_write() argument
[all …]
/linux-6.14.4/drivers/phy/qualcomm/
Dphy-qcom-usb-hsic.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/ulpi/driver.h>
7 #include <linux/ulpi/regs.h>
10 #include <linux/pinctrl/pinctrl-state.h>
14 #define ULPI_HSIC_CFG 0x30
15 #define ULPI_HSIC_IO_CAL 0x33
18 struct ulpi *ulpi; member
29 struct ulpi *ulpi = uphy->ulpi; in qcom_usb_hsic_phy_power_on() local
33 ret = clk_prepare_enable(uphy->phy_clk); in qcom_usb_hsic_phy_power_on()
37 ret = clk_prepare_enable(uphy->cal_clk); in qcom_usb_hsic_phy_power_on()
[all …]
Dphy-qcom-usb-hs.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/ulpi/driver.h>
7 #include <linux/ulpi/regs.h>
16 #define ULPI_PWR_CLK_MNG_REG 0x88
17 # define ULPI_PWR_OTG_COMP_DISABLE BIT(0)
19 #define ULPI_MISC_A 0x96
21 # define ULPI_MISC_A_VBUSVLDEXT BIT(0)
30 struct ulpi *ulpi; member
49 if (!uphy->vbus_edev) { in qcom_usb_hs_phy_set_mode()
50 u8 val = 0; in qcom_usb_hs_phy_set_mode()
[all …]
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
36 Support for the USB PHY-s on Qualcomm IPQ40xx SoC-s.
124 controllers on Qualcomm chips. This driver supports the high-speed
133 Enable support for the USB high-speed SNPS eUSB2 phy on Qualcomm
142 Enable support for the USB high-speed SNPS eUSB2 repeater on Qualcomm
160 depends on EXTCON || !EXTCON # if EXTCON=m, this cannot be built-in
163 Support for the USB high-speed ULPI compliant phy on Qualcomm
171 Enable support for the USB high-speed SNPS Femto phy on Qualcomm
177 tristate "Qualcomm USB HSIC ULPI PHY module"
181 Support for the USB HSIC ULPI compliant PHY on QCOM chipsets.
[all …]
/linux-6.14.4/drivers/usb/dwc3/
Dulpi.c1 // SPDX-License-Identifier: GPL-2.0
3 * ulpi.c - DesignWare USB3 Controller's ULPI PHY interface
12 #include <linux/ulpi/regs.h>
36 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); in dwc3_ulpi_busyloop()
40 while (count--) { in dwc3_ulpi_busyloop()
42 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYACC(0)); in dwc3_ulpi_busyloop()
44 return 0; in dwc3_ulpi_busyloop()
48 return -ETIMEDOUT; in dwc3_ulpi_busyloop()
58 dwc3_writel(dwc->regs, DWC3_GUSB2PHYACC(0), reg); in dwc3_ulpi_read()
64 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYACC(0)); in dwc3_ulpi_read()
[all …]
/linux-6.14.4/drivers/usb/chipidea/
Dulpi.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/ulpi/interface.h>
23 while (usec--) { in ci_ulpi_wait()
25 return 0; in ci_ulpi_wait()
30 return -ETIMEDOUT; in ci_ulpi_wait()
38 hw_write(ci, OP_ULPI_VIEWPORT, 0xffffffff, ULPI_WRITE | ULPI_WAKEUP); in ci_ulpi_read()
43 hw_write(ci, OP_ULPI_VIEWPORT, 0xffffffff, ULPI_RUN | ULPI_ADDR(addr)); in ci_ulpi_read()
56 hw_write(ci, OP_ULPI_VIEWPORT, 0xffffffff, ULPI_WRITE | ULPI_WAKEUP); in ci_ulpi_write()
61 hw_write(ci, OP_ULPI_VIEWPORT, 0xffffffff, in ci_ulpi_write()
68 if (ci->platdata->phy_mode != USBPHY_INTERFACE_MODE_ULPI) in ci_ulpi_init()
[all …]
Dci.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * ci.h - common structures, functions, and macros of the ChipIdea driver
5 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
17 #include <linux/usb/otg-fsm.h>
20 #include <linux/ulpi/interface.h>
35 #define ID_ID 0x0
36 #define ID_HWGENERAL 0x4
37 #define ID_HWHOST 0x8
38 #define ID_HWDEVICE 0xc
39 #define ID_HWTXBUF 0x10
[all …]
/linux-6.14.4/drivers/usb/phy/
Dphy-ulpi.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Generic ULPI USB transceiver support
18 #include <linux/usb/ulpi.h>
33 /* ULPI hardcoded IDs, used for probing */
35 ULPI_INFO(ULPI_ID(0x04cc, 0x1504), "NXP ISP1504"),
36 ULPI_INFO(ULPI_ID(0x0424, 0x0006), "SMSC USB331x"),
37 ULPI_INFO(ULPI_ID(0x0424, 0x0007), "SMSC USB3320"),
38 ULPI_INFO(ULPI_ID(0x0424, 0x0009), "SMSC USB334x"),
39 ULPI_INFO(ULPI_ID(0x0451, 0x1507), "TI TUSB1210"),
47 if (phy->flags & ULPI_OTG_ID_PULLUP) in ulpi_set_otg_flags()
[all …]
/linux-6.14.4/drivers/phy/ti/
Dphy-tusb1210.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * tusb1210.c - TUSB1210 USB ULPI PHY driver
12 #include <linux/ulpi/driver.h>
13 #include <linux/ulpi/regs.h>
20 #define TI_VENDOR_ID 0x0451
21 #define TI_DEVICE_TUSB1210 0x1507
22 #define TI_DEVICE_TUSB1211 0x1508
24 #define TUSB1211_POWER_CONTROL 0x3d
25 #define TUSB1211_POWER_CONTROL_SET 0x3e
26 #define TUSB1211_POWER_CONTROL_CLEAR 0x3f
[all …]
/linux-6.14.4/drivers/phy/tegra/
Dxusb-tegra124.c1 // SPDX-License-Identifier: GPL-2.0-only
21 #define FUSE_SKU_CALIB_HS_CURR_LEVEL_PADX_SHIFT(x) ((x) ? 15 : 0)
22 #define FUSE_SKU_CALIB_HS_CURR_LEVEL_PAD_MASK 0x3f
24 #define FUSE_SKU_CALIB_HS_IREF_CAP_MASK 0x3
26 #define FUSE_SKU_CALIB_HS_SQUELCH_LEVEL_MASK 0x3
28 #define FUSE_SKU_CALIB_HS_TERM_RANGE_ADJ_MASK 0xf
30 #define XUSB_PADCTL_USB2_PORT_CAP 0x008
32 #define XUSB_PADCTL_USB2_PORT_CAP_PORT_CAP_MASK 0x3
33 #define XUSB_PADCTL_USB2_PORT_CAP_DISABLED 0x0
34 #define XUSB_PADCTL_USB2_PORT_CAP_HOST 0x1
[all …]
Dxusb.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2022, NVIDIA CORPORATION. All rights reserved.
31 if (args->args_count != 0) in tegra_xusb_pad_of_xlate()
32 return ERR_PTR(-EINVAL); in tegra_xusb_pad_of_xlate()
34 for (i = 0; i < pad->soc->num_lanes; i++) { in tegra_xusb_pad_of_xlate()
35 if (!pad->lanes[i]) in tegra_xusb_pad_of_xlate()
38 if (pad->lanes[i]->dev.of_node == args->np) { in tegra_xusb_pad_of_xlate()
39 phy = pad->lanes[i]; in tegra_xusb_pad_of_xlate()
45 phy = ERR_PTR(-ENODEV); in tegra_xusb_pad_of_xlate()
53 .compatible = "nvidia,tegra124-xusb-padctl",
[all …]
/linux-6.14.4/include/linux/mfd/
Dmotorola-cpcap.h1 /* SPDX-License-Identifier: GPL-2.0-only */
6 * Copyright (C) 2007-2009 Motorola, Inc.
17 #define CPCAP_VENDOR_ST 0
21 #define CPCAP_REVISION_MINOR(r) ((r) & 0xf)
23 #define CPCAP_REVISION_1_0 0x08
24 #define CPCAP_REVISION_1_1 0x09
25 #define CPCAP_REVISION_2_0 0x10
26 #define CPCAP_REVISION_2_1 0x11
29 #define CPCAP_REG_INT1 0x0000 /* Interrupt 1 */
30 #define CPCAP_REG_INT2 0x0004 /* Interrupt 2 */
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/phy/
Dnvidia,tegra20-usb-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra20-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Osipenko <[email protected]>
11 - Jon Hunter <[email protected]>
12 - Thierry Reding <[email protected]>
17 - items:
18 - enum:
19 - nvidia,tegra124-usb-phy
[all …]
Dnvidia,tegra124-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra124-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <[email protected]>
11 - Jon Hunter <[email protected]>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
Dqcom,usb-hs-phy.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,usb-hs-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <[email protected]>
17 - qcom,usb-hs-phy-apq8064
18 - qcom,usb-hs-phy-msm8660
19 - qcom,usb-hs-phy-msm8960
25 reset-names:
34 reset-names:
[all …]
/linux-6.14.4/include/linux/usb/
Dulpi.h1 // SPDX-License-Identifier: GPL-2.0
3 * ulpi.h -- ULPI defines and function prorotypes
12 #include <linux/ulpi/regs.h>
14 /*-------------------------------------------------------------------------*/
17 * ULPI Flags
19 #define ULPI_OTG_ID_PULLUP (1 << 0)
49 /*-------------------------------------------------------------------------*/
/linux-6.14.4/arch/powerpc/platforms/83xx/
Dusb_831x.c1 // SPDX-License-Identifier: GPL-2.0-or-later
28 int ret = 0; in mpc831x_usb_cfg()
33 np = of_find_compatible_node(NULL, NULL, "fsl-usb2-dr"); in mpc831x_usb_cfg()
35 return -ENODEV; in mpc831x_usb_cfg()
39 immap = ioremap(get_immrbase(), 0x1000); in mpc831x_usb_cfg()
42 return -ENOMEM; in mpc831x_usb_cfg()
47 if (immr_node && (of_device_is_compatible(immr_node, "fsl,mpc8315-immr") || in mpc831x_usb_cfg()
48 of_device_is_compatible(immr_node, "fsl,mpc8308-immr"))) in mpc831x_usb_cfg()
57 /* Configure pin mux for ULPI. There is no pin mux for UTMI */ in mpc831x_usb_cfg()
58 if (prop && !strcmp(prop, "ulpi")) { in mpc831x_usb_cfg()
[all …]
Dusb_837x.c1 // SPDX-License-Identifier: GPL-2.0-or-later
25 int ret = 0; in mpc837x_usb_cfg()
27 np = of_find_compatible_node(NULL, NULL, "fsl-usb2-dr"); in mpc837x_usb_cfg()
30 return -ENODEV; in mpc837x_usb_cfg()
34 if (!prop || (strcmp(prop, "ulpi") && strcmp(prop, "serial"))) { in mpc837x_usb_cfg()
37 return -EINVAL; in mpc837x_usb_cfg()
41 immap = ioremap(get_immrbase(), 0x1000); in mpc837x_usb_cfg()
44 return -ENOMEM; in mpc837x_usb_cfg()
51 /* Configure pin mux for ULPI/serial */ in mpc837x_usb_cfg()
/linux-6.14.4/Documentation/devicetree/bindings/usb/
Dsnps,dwc3-common.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/usb/snps,dwc3-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Felipe Balbi <[email protected]>
14 vendor-specific implementation or as a standalone component.
17 - $ref: usb-drd.yaml#
18 - if:
24 - dr_mode
28 $ref: usb-xhci.yaml#
[all …]
/linux-6.14.4/arch/arm/boot/dts/nvidia/
Dtegra124-apalis.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR X11
3 * Copyright 2016-2019 Toradex AG
7 #include "tegra124-apalis-emc.dtsi"
11 * Compatible for Revisions 2GB: V1.0A, V1.0B, V1.1A
15 reg = <0x0 0x80000000 0x0 0x80000000>;
20 avddio-pex-supply = <&reg_1v05_vdd>;
21 avdd-pex-pll-supply = <&reg_1v05_vdd>;
22 avdd-pll-erefe-supply = <&reg_1v05_avdd>;
23 dvddio-pex-supply = <&reg_1v05_vdd>;
24 hvdd-pex-pll-e-supply = <&reg_module_3v3>;
[all …]
Dtegra124-apalis-v1.2.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
3 * Copyright 2016-2018 Toradex AG
7 #include "tegra124-apalis-emc.dtsi"
15 reg = <0x0 0x80000000 0x0 0x80000000>;
21 avddio-pex-supply = <&reg_1v05_vdd>;
22 avdd-pex-pll-supply = <&reg_1v05_vdd>;
23 avdd-pll-erefe-supply = <&reg_1v05_avdd>;
24 dvddio-pex-supply = <&reg_1v05_vdd>;
25 hvdd-pex-pll-e-supply = <&reg_module_3v3>;
26 hvdd-pex-supply = <&reg_module_3v3>;
[all …]
/linux-6.14.4/arch/powerpc/boot/dts/
Dasp834x-redboot.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /dts-v1/;
12 compatible = "analogue-and-micro,asp8347e";
13 #address-cells = <1>;
14 #size-cells = <1>;
24 #address-cells = <1>;
25 #size-cells = <0>;
27 PowerPC,8347@0 {
29 reg = <0x0>;
30 d-cache-line-size = <32>;
[all …]
/linux-6.14.4/arch/powerpc/boot/dts/fsl/
Dmpc8536ds.dtsi2 * MPC8536DS Device Tree Source stub (no addresses or top-level ranges)
36 nor@0,0 {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
40 reg = <0x0 0x0 0x8000000>;
41 bank-width = <2>;
42 device-width = <1>;
44 partition@0 {
45 reg = <0x0 0x03000000>;
[all …]
/linux-6.14.4/drivers/usb/dwc2/
Dcore.h1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
3 * core.h - DesignWare HS OTG Controller common declarations
5 * Copyright (C) 2004-2013 Synopsys, Inc.
21 * - no_printk: Disable tracing
22 * - pr_info: Print this info to the console
23 * - trace_printk: Print this info to trace buffer (good for verbose logging)
32 dev_name(hsotg->dev), ##__VA_ARGS__)
37 dev_name(hsotg->dev), ##__VA_ARGS__)
42 /* dwc2-hsotg declarations */
74 * struct dwc2_hsotg_ep - driver endpoint definition.
[all …]
/linux-6.14.4/arch/arm/boot/dts/nxp/imx/
Dimx27-phytec-phycard-s-som.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2012 Sascha Hauer, Uwe Kleine-König, Steffen Trumtrar
7 /dts-v1/;
12 compatible = "phytec,imx27-pca100", "fsl,imx27";
16 reg = <0xa0000000 0x08000000>; /* 128MB */
20 compatible = "usb-nop-xceiv";
21 pinctrl-names = "default";
22 pinctrl-0 = <&pinctrl_usbotgphy>;
23 reset-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>;
24 #phy-cells = <0>;
[all …]

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