1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/usb/snps,dwc3-common.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Synopsys DesignWare USB3 Controller common properties 8 9maintainers: 10 - Felipe Balbi <[email protected]> 11 12description: 13 Defines the properties of the DWC3 core as being embedded in either an 14 vendor-specific implementation or as a standalone component. 15 16allOf: 17 - $ref: usb-drd.yaml# 18 - if: 19 properties: 20 dr_mode: 21 const: peripheral 22 23 required: 24 - dr_mode 25 then: 26 $ref: usb.yaml# 27 else: 28 $ref: usb-xhci.yaml# 29 30properties: 31 extcon: 32 maxItems: 1 33 deprecated: true 34 35 usb-phy: 36 minItems: 1 37 items: 38 - description: USB2/HS PHY 39 - description: USB3/SS PHY 40 41 phys: 42 minItems: 1 43 maxItems: 19 44 45 phy-names: 46 minItems: 1 47 maxItems: 19 48 oneOf: 49 - items: 50 enum: [ usb2-phy, usb3-phy ] 51 - items: 52 pattern: "^usb(2-([0-9]|1[0-4])|3-[0-3])$" 53 54 snps,usb2-lpm-disable: 55 description: Indicate if we don't want to enable USB2 HW LPM for host 56 mode. 57 type: boolean 58 59 snps,usb3_lpm_capable: 60 description: Determines if platform is USB3 LPM capable 61 type: boolean 62 63 snps,usb2-gadget-lpm-disable: 64 description: Indicate if we don't want to enable USB2 HW LPM for gadget 65 mode. 66 type: boolean 67 68 snps,dis-start-transfer-quirk: 69 description: 70 When set, disable isoc START TRANSFER command failure SW work-around 71 for DWC_usb31 version 1.70a-ea06 and prior. 72 type: boolean 73 74 snps,disable_scramble_quirk: 75 description: 76 True when SW should disable data scrambling. Only really useful for FPGA 77 builds. 78 type: boolean 79 80 snps,has-lpm-erratum: 81 description: True when DWC3 was configured with LPM Erratum enabled 82 type: boolean 83 84 snps,lpm-nyet-threshold: 85 description: LPM NYET threshold 86 $ref: /schemas/types.yaml#/definitions/uint8 87 88 snps,u2exit_lfps_quirk: 89 description: Set if we want to enable u2exit lfps quirk 90 type: boolean 91 92 snps,u2ss_inp3_quirk: 93 description: Set if we enable P3 OK for U2/SS Inactive quirk 94 type: boolean 95 96 snps,req_p1p2p3_quirk: 97 description: 98 When set, the core will always request for P1/P2/P3 transition sequence. 99 type: boolean 100 101 snps,del_p1p2p3_quirk: 102 description: 103 When set core will delay P1/P2/P3 until a certain amount of 8B10B errors 104 occur. 105 type: boolean 106 107 snps,del_phy_power_chg_quirk: 108 description: When set core will delay PHY power change from P0 to P1/P2/P3. 109 type: boolean 110 111 snps,lfps_filter_quirk: 112 description: When set core will filter LFPS reception. 113 type: boolean 114 115 snps,rx_detect_poll_quirk: 116 description: 117 when set core will disable a 400us delay to start Polling LFPS after 118 RX.Detect. 119 type: boolean 120 121 snps,tx_de_emphasis_quirk: 122 description: When set core will set Tx de-emphasis value 123 type: boolean 124 125 snps,tx_de_emphasis: 126 description: 127 The value driven to the PHY is controlled by the LTSSM during USB3 128 Compliance mode. 129 $ref: /schemas/types.yaml#/definitions/uint8 130 enum: 131 - 0 # -6dB de-emphasis 132 - 1 # -3.5dB de-emphasis 133 - 2 # No de-emphasis 134 135 snps,dis_u3_susphy_quirk: 136 description: When set core will disable USB3 suspend phy 137 type: boolean 138 139 snps,dis_u2_susphy_quirk: 140 description: When set core will disable USB2 suspend phy 141 type: boolean 142 143 snps,dis_enblslpm_quirk: 144 description: 145 When set clears the enblslpm in GUSB2PHYCFG, disabling the suspend signal 146 to the PHY. 147 type: boolean 148 149 snps,dis-u1-entry-quirk: 150 description: Set if link entering into U1 needs to be disabled 151 type: boolean 152 153 snps,dis-u2-entry-quirk: 154 description: Set if link entering into U2 needs to be disabled 155 type: boolean 156 157 snps,dis_rxdet_inp3_quirk: 158 description: 159 When set core will disable receiver detection in PHY P3 power state. 160 type: boolean 161 162 snps,dis-u2-freeclk-exists-quirk: 163 description: 164 When set, clear the u2_freeclk_exists in GUSB2PHYCFG, specify that USB2 165 PHY doesn't provide a free-running PHY clock. 166 type: boolean 167 168 snps,dis-del-phy-power-chg-quirk: 169 description: 170 When set core will change PHY power from P0 to P1/P2/P3 without delay. 171 type: boolean 172 173 snps,dis-tx-ipgap-linecheck-quirk: 174 description: When set, disable u2mac linestate check during HS transmit 175 type: boolean 176 177 snps,parkmode-disable-ss-quirk: 178 description: 179 When set, all SuperSpeed bus instances in park mode are disabled. 180 type: boolean 181 182 snps,parkmode-disable-hs-quirk: 183 description: 184 When set, all HighSpeed bus instances in park mode are disabled. 185 type: boolean 186 187 snps,dis_metastability_quirk: 188 description: 189 When set, disable metastability workaround. CAUTION! Use only if you are 190 absolutely sure of it. 191 type: boolean 192 193 snps,dis-split-quirk: 194 description: 195 When set, change the way URBs are handled by the driver. Needed to 196 avoid -EPROTO errors with usbhid on some devices (Hikey 970). 197 type: boolean 198 199 snps,gfladj-refclk-lpm-sel-quirk: 200 description: 201 When set, run the SOF/ITP counter based on ref_clk. 202 type: boolean 203 204 snps,resume-hs-terminations: 205 description: 206 Fix the issue of HS terminations CRC error on resume by enabling this 207 quirk. When set, all the termsel, xcvrsel, opmode becomes 0 during end 208 of resume. This option is to support certain legacy ULPI PHYs. 209 type: boolean 210 211 snps,ulpi-ext-vbus-drv: 212 description: 213 Some ULPI USB PHY does not support internal VBUS supply, and driving 214 the CPEN pin, requires the configuration of the ulpi DRVVBUSEXTERNAL 215 bit. When set, the xhci host will configure the USB2 PHY drives VBUS 216 with an external supply. 217 type: boolean 218 219 snps,is-utmi-l1-suspend: 220 description: 221 True when DWC3 asserts output signal utmi_l1_suspend_n, false when 222 asserts utmi_sleep_n. 223 type: boolean 224 225 snps,hird-threshold: 226 description: HIRD threshold 227 $ref: /schemas/types.yaml#/definitions/uint8 228 229 snps,hsphy_interface: 230 description: 231 High-Speed PHY interface selection between UTMI+ and ULPI when the 232 DWC_USB3_HSPHY_INTERFACE has value 3. 233 $ref: /schemas/types.yaml#/definitions/string 234 enum: [utmi, ulpi] 235 236 snps,quirk-frame-length-adjustment: 237 description: 238 Value for GFLADJ_30MHZ field of GFLADJ register for post-silicon frame 239 length adjustment when the fladj_30mhz_sdbnd signal is invalid or 240 incorrect. 241 $ref: /schemas/types.yaml#/definitions/uint32 242 minimum: 0 243 maximum: 0x3f 244 245 snps,ref-clock-period-ns: 246 description: 247 Value for REFCLKPER field of GUCTL register for reference clock period in 248 nanoseconds, when the hardware set default does not match the actual 249 clock. 250 251 This binding is deprecated. Instead, provide an appropriate reference clock. 252 minimum: 8 253 maximum: 62 254 deprecated: true 255 256 snps,rx-thr-num-pkt: 257 description: 258 USB RX packet threshold count. In host mode, this field specifies 259 the space that must be available in the RX FIFO before the core can 260 start the corresponding USB RX transaction (burst). 261 In device mode, this field specifies the space that must be 262 available in the RX FIFO before the core can send ERDY for a 263 flow-controlled endpoint. It is only used for SuperSpeed. 264 The valid values for this field are from 1 to 15. (DWC3 SuperSpeed 265 USB 3.0 Controller Databook) 266 $ref: /schemas/types.yaml#/definitions/uint8 267 minimum: 1 268 maximum: 15 269 270 snps,rx-max-burst: 271 description: 272 Max USB RX burst size. In host mode, this field specifies the 273 Maximum Bulk IN burst the DWC_usb3 core can perform. When the system 274 bus is slower than the USB, RX FIFO can overrun during a long burst. 275 You can program a smaller value to this field to limit the RX burst 276 size that the core can perform. It only applies to SS Bulk, 277 Isochronous, and Interrupt IN endpoints in the host mode. 278 In device mode, this field specifies the NUMP value that is sent in 279 ERDY for an OUT endpoint. 280 The valid values for this field are from 1 to 16. (DWC3 SuperSpeed 281 USB 3.0 Controller Databook) 282 $ref: /schemas/types.yaml#/definitions/uint8 283 minimum: 1 284 maximum: 16 285 286 snps,tx-thr-num-pkt: 287 description: 288 USB TX packet threshold count. This field specifies the number of 289 packets that must be in the TXFIFO before the core can start 290 transmission for the corresponding USB transaction (burst). 291 This count is valid in both host and device modes. It is only used 292 for SuperSpeed operation. 293 Valid values are from 1 to 15. (DWC3 SuperSpeed USB 3.0 Controller 294 Databook) 295 $ref: /schemas/types.yaml#/definitions/uint8 296 minimum: 1 297 maximum: 15 298 299 snps,tx-max-burst: 300 description: 301 Max USB TX burst size. When the system bus is slower than the USB, 302 TX FIFO can underrun during a long burst. Program a smaller value 303 to this field to limit the TX burst size that the core can execute. 304 In Host mode, it only applies to SS Bulk, Isochronous, and Interrupt 305 OUT endpoints. This value is not used in device mode. 306 Valid values are from 1 to 16. (DWC3 SuperSpeed USB 3.0 Controller 307 Databook) 308 $ref: /schemas/types.yaml#/definitions/uint8 309 minimum: 1 310 maximum: 16 311 312 snps,rx-thr-num-pkt-prd: 313 description: 314 Periodic ESS RX packet threshold count (host mode only). Set this and 315 snps,rx-max-burst-prd to a valid, non-zero value 1-16 (DWC_usb31 316 programming guide section 1.2.4) to enable periodic ESS RX threshold. 317 $ref: /schemas/types.yaml#/definitions/uint8 318 minimum: 1 319 maximum: 16 320 321 snps,rx-max-burst-prd: 322 description: 323 Max periodic ESS RX burst size (host mode only). Set this and 324 snps,rx-thr-num-pkt-prd to a valid, non-zero value 1-16 (DWC_usb31 325 programming guide section 1.2.4) to enable periodic ESS RX threshold. 326 $ref: /schemas/types.yaml#/definitions/uint8 327 minimum: 1 328 maximum: 16 329 330 snps,tx-thr-num-pkt-prd: 331 description: 332 Periodic ESS TX packet threshold count (host mode only). Set this and 333 snps,tx-max-burst-prd to a valid, non-zero value 1-16 (DWC_usb31 334 programming guide section 1.2.3) to enable periodic ESS TX threshold. 335 $ref: /schemas/types.yaml#/definitions/uint8 336 minimum: 1 337 maximum: 16 338 339 snps,tx-max-burst-prd: 340 description: 341 Max periodic ESS TX burst size (host mode only). Set this and 342 snps,tx-thr-num-pkt-prd to a valid, non-zero value 1-16 (DWC_usb31 343 programming guide section 1.2.3) to enable periodic ESS TX threshold. 344 $ref: /schemas/types.yaml#/definitions/uint8 345 minimum: 1 346 maximum: 16 347 348 tx-fifo-resize: 349 description: Determines if the TX fifos can be dynamically resized depending 350 on the number of IN endpoints used and if bursting is supported. This 351 may help improve bandwidth on platforms with higher system latencies, as 352 increased fifo space allows for the controller to prefetch data into its 353 internal memory. 354 type: boolean 355 356 tx-fifo-max-num: 357 description: Specifies the max number of packets the txfifo resizing logic 358 can account for when higher endpoint bursting is used. (bMaxBurst > 6) The 359 higher the number, the more fifo space the txfifo resizing logic will 360 allocate for that endpoint. 361 $ref: /schemas/types.yaml#/definitions/uint8 362 minimum: 3 363 364 snps,incr-burst-type-adjustment: 365 description: 366 Value for INCR burst type of GSBUSCFG0 register, undefined length INCR 367 burst type enable and INCRx type. A single value means INCRX burst mode 368 enabled. If more than one value specified, undefined length INCR burst 369 type will be enabled with burst lengths utilized up to the maximum 370 of the values passed in this property. 371 $ref: /schemas/types.yaml#/definitions/uint32-array 372 minItems: 1 373 maxItems: 8 374 uniqueItems: true 375 items: 376 enum: [1, 4, 8, 16, 32, 64, 128, 256] 377 378 num-hc-interrupters: 379 maximum: 8 380 default: 1 381 382 port: 383 $ref: /schemas/graph.yaml#/properties/port 384 description: 385 This port is used with the 'usb-role-switch' property to connect the 386 dwc3 to type C connector. 387 388 ports: 389 $ref: /schemas/graph.yaml#/properties/ports 390 description: 391 Those ports should be used with any connector to the data bus of this 392 controller using the OF graph bindings specified if the "usb-role-switch" 393 property is used. 394 395 properties: 396 port@0: 397 $ref: /schemas/graph.yaml#/properties/port 398 description: High Speed (HS) data bus. 399 400 port@1: 401 $ref: /schemas/graph.yaml#/properties/port 402 description: Super Speed (SS) data bus. 403 404 wakeup-source: 405 $ref: /schemas/types.yaml#/definitions/flag 406 description: 407 Enable USB remote wakeup. 408 409required: 410 - compatible 411 - reg 412 413additionalProperties: true 414... 415 416