Lines Matching +full:ulpi +full:- +full:0
1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
3 * core.h - DesignWare HS OTG Controller common declarations
5 * Copyright (C) 2004-2013 Synopsys, Inc.
21 * - no_printk: Disable tracing
22 * - pr_info: Print this info to the console
23 * - trace_printk: Print this info to trace buffer (good for verbose logging)
32 dev_name(hsotg->dev), ##__VA_ARGS__)
37 dev_name(hsotg->dev), ##__VA_ARGS__)
42 /* dwc2-hsotg declarations */
74 * struct dwc2_hsotg_ep - driver endpoint definition.
88 * @mc: Multi Count - number of transactions per microframe
94 * @send_zlp: Set if we need to send a zero-length packet.
119 * as in shared-fifo mode periodic in acts like a single-frame packet
148 #define TARGET_FRAME_INITIAL 0xFFFFFFFF
162 * struct dwc2_hsotg_req - data transfer request
177 if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \
178 (_hs)->driver && (_hs)->driver->_entry) { \
179 spin_unlock(&_hs->lock); \
180 (_hs)->driver->_entry(&(_hs)->gadget); \
181 spin_lock(&_hs->lock); \
183 } while (0)
185 #define call_gadget(_hs, _entry) do {} while (0)
209 * struct dwc2_core_params - Parameters for configuring the core
213 * - HNP and SRP capable
214 * - SRP Only capable
215 * - No HNP/SRP capable (always available)
217 * - OTG revision number the device is compliant with, in binary-coded
222 * 0 - Slave (always available)
223 * 1 - DMA (default, if available)
228 * 0 - Address DMA
229 * 1 - Descriptor DMA (default, if available)
235 * 0 - Address DMA
236 * 1 - Descriptor DMA in FS (default, if available)
240 * 0 - High Speed
241 * (default when phy_type is UTMI+ or ULPI)
242 * 1 - Full Speed
244 * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters
245 * 1 - Allow dynamic FIFO sizing (default, if available)
246 * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs
247 * are enabled for non-periodic IN endpoints in device
249 * @host_rx_fifo_size: Number of 4-byte words in the Rx FIFO in host mode when
254 * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO
259 * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in
278 * 0 - Full Speed Phy
279 * 1 - UTMI+ Phy
280 * 2 - ULPI Phy
281 * Defaults to best available option (2, 1, then 0)
283 * is applicable for a phy_type of UTMI+ or ULPI. (For a
284 * ULPI phy_type, this parameter indicates the data width
285 * between the MAC and the ULPI Wrapper.) Also, this
294 * 0 - eUSB2 PHY disconnect support flow not applicable
295 * 1 - eUSB2 PHY disconnect support flow applicable
296 * @phy_ulpi_ddr: Specifies whether the ULPI operates at double or single
298 * is ULPI.
299 * 0 - single data rate ULPI interface with 8 bit wide
301 * 1 - double data rate ULPI interface with 4 bit wide
303 * @phy_ulpi_ext_vbus: For a ULPI phy, specifies whether to use the internal or
305 * 0 - Internal supply (default)
306 * 1 - External supply
310 * 0 - No (default)
311 * 1 - Yes
313 * 0 - Disable (default)
314 * 1 - Enable
316 * 0 - No
317 * 1 - Yes
318 * @ulpi_fs_ls: Make ULPI phy operate in FS/LS mode only
319 * 0 - No (default)
320 * 1 - Yes
324 * 0 - Don't support low power mode (default)
325 * 1 - Support low power mode
330 * 0 - 48 MHz
331 * (default when phy_type is UTMI+ or ULPI)
332 * 1 - 6 MHz
335 * 0 - Allow overcurrent condition to get detected
336 * 1 - Disable overcurrent condtion to get detected
338 * 0 - No (default)
339 * 1 - Yes
341 * 0 - No (default for core < 2.92a)
342 * 1 - Yes (default for core >= 2.92a)
345 * -1 - GAHBCFG value will be set to 0x06
347 * all others - GAHBCFG value will be overridden with
357 * 0 - No (default)
358 * 1 - Yes
363 * 0 - No (default)
364 * 1 - Partial power down
365 * 2 - Hibernation
367 * 0 - No (use clock gating)
368 * 1 - Yes (avoid it)
370 * 0 - No
371 * 1 - Yes
373 * 0 - No
374 * 1 - Yes
376 * 0 - No
377 * 1 - Yes
379 * 0 - No
380 * 1 - Yes
384 * 62500 - 16MHz
385 * 58823 - 17MHz
386 * 52083 - 19.2MHz
387 * 50000 - 20MHz
388 * 41666 - 24MHz
389 * 33333 - 30MHz (default)
390 * 25000 - 40MHz
398 * 0 - Deactivate the transceiver (default)
399 * 1 - Activate the transceiver
402 * 0 - Deactivate the external level detection (default)
403 * 1 - Activate the external level detection
406 * 0 - Deactivate the overcurrent detection
407 * 1 - Activate the overcurrent detection (default)
411 * DWORDS from 16-32768 (default: 2048 if
413 * @g_np_tx_fifo_size: The non-periodic tx fifo size for the device in
414 * DWORDS from 16-32768 (default: 1024 if
420 * 16-32768 (default: 256, 256, 256, 256, 768,
421 * 768, 768, 768, 0, 0, 0, 0, 0, 0, 0).
425 * 0 - No (default)
426 * 1 - Yes
428 * 0 - No
429 * 1 - Yes
433 * value of -1 (or any other out of range value) for any parameter means
440 #define DWC2_PHY_TYPE_PARAM_FS 0
445 #define DWC2_SPEED_PARAM_HIGH 0
464 #define DWC2_POWER_DOWN_PARAM_NONE 0
511 * struct dwc2_hw_params - Autodetected parameters.
521 * 0 - HNP- and SRP-Capable OTG (Host & Device)
522 * 1 - SRP-Capable OTG (Host & Device)
523 * 2 - Non-HNP and Non-SRP Capable OTG (Host & Device)
524 * 3 - SRP-Capable Device
525 * 4 - Non-OTG Device
526 * 5 - SRP-Capable Host
527 * 6 - Non-OTG Host
529 * 0 - Slave only
530 * 1 - External DMA
531 * 2 - Internal DMA
533 * the worst-case scenario of Rx followed by Rx
536 * 0 - Don't support
537 * 1 - Support
545 * 0 to 30
550 * Non-Periodic Request Queue Depth
552 * @hs_phy_type: High-speed PHY interface type
553 * 0 - High-speed interface not supported
554 * 1 - UTMI+
555 * 2 - ULPI
556 * 3 - UTMI+ and ULPI
557 * @fs_phy_type: Full-speed PHY interface type
558 * 0 - Full speed interface not supported
559 * 1 - Dedicated full speed interface
560 * 2 - FS pins shared with UTMI+ pins
561 * 3 - FS pins shared with ULPI pins
565 * 0 - 8 bits
566 * 1 - 16 bits
567 * 2 - 8 or 16 bits
570 * @g_tx_fifo_size: Power-on values of TxFIFO sizes
575 * 0 - Address DMA
576 * 1 - Descriptor DMA (default, if available)
577 * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters
578 * 1 - Allow dynamic FIFO sizing (default, if available)
579 * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs
580 * are enabled for non-periodic IN endpoints in device
582 * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO
587 * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in
604 * @dev_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO
612 * 0 - No (default)
613 * 1 - Yes
615 * 0 - Disable
616 * 1 - Enable
618 * 0 - Disable
619 * 1 - Enable
620 * @rx_fifo_size: Number of 4-byte words in the Rx FIFO when dynamic
626 * 0 - Disable
627 * 1 - Enable
668 * struct dwc2_gregs_backup - Holds global registers state before
702 * struct dwc2_dregs_backup - Holds device registers state before
735 * struct dwc2_hregs_backup - Holds host registers state before
791 * - DWC2_HS_SCHEDULE_UFRAMES must even divide 0x4000 (HFNUM_MAX_FRNUM + 1)
792 * - DWC2_HS_SCHEDULE_UFRAMES must be 8 times DWC2_LS_SCHEDULE_FRAMES (probably
826 * - DWC2_US_PER_SLICE must evenly divide DWC2_LS_PERIODIC_US_PER_FRAME.
846 * struct dwc2_hsotg - Holds the state of the driver, including the non-periodic
861 * - USB_DR_MODE_PERIPHERAL
862 * - USB_DR_MODE_HOST
863 * - USB_DR_MODE_OTG
867 * @hcd_enabled: Host mode sub-driver initialization indicator.
868 * @gadget_enabled: Peripheral mode sub-driver initialization indicator.
869 * @ll_hw_enabled: Status of low-level hardware resources.
879 * and host modes. The value ranges are from 0
892 * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth
921 * @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule.
924 * @non_periodic_sched_active: Active QHs in the non-periodic schedule.
928 * non-periodic schedule
929 * @non_periodic_sched_waiting: Waiting QHs in the non-periodic schedule.
944 * counter is 0 at SOF.
978 * host channel is available for non-periodic transactions.
979 * @non_periodic_channels: Number of host channels assigned to non-periodic
990 * @start_work: Delayed work for handling host A-cable connection
999 * @unaligned_cache: Kmem cache for DMA mode to handle non-aligned buf
1004 * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos.
1014 * @remote_wakeup_allowed: True if device is allowed to wake-up host by
1015 * remote-wakeup signalling
1031 * @last_frame_num: Number of last frame. Range from 0 to 32768
1040 * @dumped_frame_num_array: 1 - if missed SOFs frame numbers dumbed
1041 * 0 - if missed SOFs frame numbers not dumbed
1107 #define DWC2_CORE_REV_4_30a 0x4f54430a
1108 #define DWC2_CORE_REV_2_71a 0x4f54271a
1109 #define DWC2_CORE_REV_2_72a 0x4f54272a
1110 #define DWC2_CORE_REV_2_80a 0x4f54280a
1111 #define DWC2_CORE_REV_2_90a 0x4f54290a
1112 #define DWC2_CORE_REV_2_91a 0x4f54291a
1113 #define DWC2_CORE_REV_2_92a 0x4f54292a
1114 #define DWC2_CORE_REV_2_94a 0x4f54294a
1115 #define DWC2_CORE_REV_3_00a 0x4f54300a
1116 #define DWC2_CORE_REV_3_10a 0x4f54310a
1117 #define DWC2_CORE_REV_4_00a 0x4f54400a
1118 #define DWC2_CORE_REV_4_20a 0x4f54420a
1119 #define DWC2_CORE_REV_5_00a 0x4f54500a
1120 #define DWC2_FS_IOT_REV_1_00a 0x5531100a
1121 #define DWC2_HS_IOT_REV_1_00a 0x5532100a
1122 #define DWC2_HS_IOT_REV_5_00a 0x5532500a
1123 #define DWC2_CORE_REV_MASK 0x0000ffff
1126 #define DWC2_OTG_ID 0x4f540000
1127 #define DWC2_FS_IOT_ID 0x55310000
1128 #define DWC2_HS_IOT_ID 0x55320000
1230 val = readl(hsotg->regs + offset); in dwc2_readl()
1231 if (hsotg->needs_byte_swap) in dwc2_readl()
1239 if (hsotg->needs_byte_swap) in dwc2_writel()
1240 writel(swab32(value), hsotg->regs + offset); in dwc2_writel()
1242 writel(value, hsotg->regs + offset); in dwc2_writel()
1245 pr_info("info:: wrote %08x to %p\n", value, hsotg->regs + offset); in dwc2_writel()
1258 } while (--count); in dwc2_readl_rep()
1270 } while (--count); in dwc2_writel_rep()
1295 return (hsotg->hw_params.snpsid & 0xfff00000) == 0x55300000; in dwc2_is_iot()
1300 return (hsotg->hw_params.snpsid & 0xffff0000) == 0x55310000; in dwc2_is_fs_iot()
1305 return (hsotg->hw_params.snpsid & 0xffff0000) == 0x55320000; in dwc2_is_hs_iot()
1373 * These functions can be used before the internal hsotg->hw_params
1387 return (dwc2_readl(hsotg, GINTSTS) & GINTSTS_CURMODE_HOST) != 0; in dwc2_is_host_mode()
1392 return (dwc2_readl(hsotg, GINTSTS) & GINTSTS_CURMODE_HOST) == 0; in dwc2_is_device_mode()
1420 #define dwc2_is_device_connected(hsotg) (hsotg->connected)
1421 #define dwc2_is_device_enabled(hsotg) (hsotg->enabled)
1439 { hsotg->fifo_map = 0; } in dwc2_clear_fifo_map()
1442 { return 0; } in dwc2_hsotg_remove()
1444 { return 0; } in dwc2_hsotg_suspend()
1446 { return 0; } in dwc2_hsotg_resume()
1448 { return 0; } in dwc2_gadget_init()
1456 { return 0; } in dwc2_hsotg_set_test_mode()
1457 #define dwc2_is_device_connected(hsotg) (0)
1458 #define dwc2_is_device_enabled(hsotg) (0)
1460 { return 0; } in dwc2_backup_device_registers()
1463 { return 0; } in dwc2_restore_device_registers()
1465 { return 0; } in dwc2_gadget_enter_hibernation()
1468 { return 0; } in dwc2_gadget_exit_hibernation()
1470 { return 0; } in dwc2_gadget_enter_partial_power_down()
1473 { return 0; } in dwc2_gadget_exit_partial_power_down()
1478 { return 0; } in dwc2_hsotg_tx_fifo_count()
1480 { return 0; } in dwc2_hsotg_tx_fifo_total_depth()
1482 { return 0; } in dwc2_hsotg_tx_fifo_average_depth()
1509 { schedule_work(&hsotg->phy_reset_work); } in dwc2_host_schedule_phy_reset()
1512 { return 0; } in dwc2_hcd_get_frame_number()
1515 { return 0; } in dwc2_hcd_get_future_frame_number()
1521 { return 0; } in dwc2_core_init()
1523 { return 0; } in dwc2_port_suspend()
1525 { return 0; } in dwc2_port_resume()
1527 { return 0; } in dwc2_hcd_init()
1529 { return 0; } in dwc2_backup_host_registers()
1531 { return 0; } in dwc2_restore_host_registers()
1533 { return 0; } in dwc2_host_enter_hibernation()
1536 { return 0; } in dwc2_host_exit_hibernation()
1538 { return 0; } in dwc2_host_enter_partial_power_down()
1541 { return 0; } in dwc2_host_exit_partial_power_down()