| /linux-6.14.4/Documentation/devicetree/bindings/reset/ |
| D | microchip,rst.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reset/microchip,rst.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip Sparx5 Switch Reset Controller
10 - Steen Hegelund <[email protected]>
11 - Lars Povlsen <[email protected]>
14 The Microchip Sparx5 Switch provides reset control and implements the following
16 - One Time Switch Core Reset (Soft Reset)
20 pattern: "^reset-controller@[0-9a-f]+$"
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| /linux-6.14.4/arch/arm64/boot/dts/microchip/ |
| D | sparx5.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/clock/microchip,sparx5.h>
11 compatible = "microchip,sparx5";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <1>;
23 stdout-path = "serial0:115200n8";
27 #address-cells = <1>;
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| /linux-6.14.4/drivers/net/ethernet/microchip/sparx5/ |
| D | sparx5_main.c | 1 // SPDX-License-Identifier: GPL-2.0+
2 /* Microchip Sparx5 Switch driver
6 * The Sparx5 Chip Register Model can be browsed at this location:
7 * https://github.com/microchip-ung/sparx-5_reginfo
25 #include <linux/reset.h>
215 bool is_sparx5(struct sparx5 *sparx5) in is_sparx5() argument
217 switch (sparx5->target_ct) { in is_sparx5()
234 static void sparx5_init_features(struct sparx5 *sparx5) in sparx5_init_features() argument
236 switch (sparx5->target_ct) { in sparx5_init_features()
256 sparx5->features = (SPX5_FEATURE_PSFP | SPX5_FEATURE_PTP); in sparx5_init_features()
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| D | sparx5_port.c | 1 // SPDX-License-Identifier: GPL-2.0+
2 /* Microchip Sparx5 Switch driver
31 status->an_complete = true; in decode_sgmii_word()
33 status->link = false; in decode_sgmii_word()
37 switch (lp_abil & LPA_SGMII_SPD_MASK) { in decode_sgmii_word()
39 status->speed = SPEED_10; in decode_sgmii_word()
42 status->speed = SPEED_100; in decode_sgmii_word()
45 status->speed = SPEED_1000; in decode_sgmii_word()
48 status->link = false; in decode_sgmii_word()
52 status->duplex = DUPLEX_FULL; in decode_sgmii_word()
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| D | sparx5_packet.c | 1 // SPDX-License-Identifier: GPL-2.0+
2 /* Microchip Sparx5 Switch driver
19 #define XTR_VALID_BYTES(x) (4 - ((x) & 3))
23 void sparx5_xtr_flush(struct sparx5 *sparx5, u8 grp) in sparx5_xtr_flush() argument
26 spx5_wr(QS_XTR_FLUSH_FLUSH_SET(BIT(grp)), sparx5, QS_XTR_FLUSH); in sparx5_xtr_flush()
32 spx5_wr(0, sparx5, QS_XTR_FLUSH); in sparx5_xtr_flush()
35 void sparx5_ifh_parse(struct sparx5 *sparx5, u32 *ifh, struct frame_info *info) in sparx5_ifh_parse() argument
39 /* FWD is bit 45-72 (28 bits), but we only read the 27 LSB for now */ in sparx5_ifh_parse()
46 info->src_port = spx5_field_get(GENMASK(is_sparx5(sparx5) ? 7 : 6, 1), in sparx5_ifh_parse()
50 * Bit 270-271 are occasionally unexpectedly set by the hardware, in sparx5_ifh_parse()
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| D | sparx5_fdma.c | 1 // SPDX-License-Identifier: GPL-2.0+
2 /* Microchip Sparx5 Switch driver
6 * The Sparx5 Chip Register Model can be browsed at this location:
7 * https://github.com/microchip-ung/sparx-5_reginfo
15 #include <linux/dma-mapping.h>
27 *dataptr = fdma->dma + (sizeof(struct fdma_dcb) * fdma->n_dcbs) + in sparx5_fdma_tx_dataptr_cb()
28 ((dcb * fdma->n_dbs + db) * fdma->db_size); in sparx5_fdma_tx_dataptr_cb()
36 struct sparx5 *sparx5 = fdma->priv; in sparx5_fdma_rx_dataptr_cb() local
37 struct sparx5_rx *rx = &sparx5->rx; in sparx5_fdma_rx_dataptr_cb()
40 skb = __netdev_alloc_skb(rx->ndev, fdma->db_size, GFP_ATOMIC); in sparx5_fdma_rx_dataptr_cb()
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| D | sparx5_psfp.c | 1 // SPDX-License-Identifier: GPL-2.0+
2 /* Microchip Sparx5 Switch driver
23 static int sparx5_psfp_sf_get(struct sparx5 *sparx5, u32 *id) in sparx5_psfp_sf_get() argument
26 sparx5->data->consts->n_filters, id); in sparx5_psfp_sf_get()
29 static int sparx5_psfp_sf_put(struct sparx5 *sparx5, u32 id) in sparx5_psfp_sf_put() argument
32 sparx5->data->consts->n_filters, id); in sparx5_psfp_sf_put()
35 static int sparx5_psfp_sg_get(struct sparx5 *sparx5, u32 idx, u32 *id) in sparx5_psfp_sg_get() argument
38 sparx5->data->consts->n_gates, idx, id); in sparx5_psfp_sg_get()
41 static int sparx5_psfp_sg_put(struct sparx5 *sparx5, u32 id) in sparx5_psfp_sg_put() argument
44 sparx5->data->consts->n_gates, id); in sparx5_psfp_sg_put()
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| D | sparx5_mactable.c | 1 // SPDX-License-Identifier: GPL-2.0+
2 /* Microchip Sparx5 Switch driver
44 static int sparx5_mact_get_status(struct sparx5 *sparx5) in sparx5_mact_get_status() argument
46 return spx5_rd(sparx5, LRN_COMMON_ACCESS_CTRL); in sparx5_mact_get_status()
49 static int sparx5_mact_wait_for_completion(struct sparx5 *sparx5) in sparx5_mact_wait_for_completion() argument
54 sparx5, val, in sparx5_mact_wait_for_completion()
59 static void sparx5_mact_select(struct sparx5 *sparx5, in sparx5_mact_select() argument
76 spx5_wr(mach, sparx5, LRN_MAC_ACCESS_CFG_0); in sparx5_mact_select()
77 spx5_wr(macl, sparx5, LRN_MAC_ACCESS_CFG_1); in sparx5_mact_select()
80 int sparx5_mact_learn(struct sparx5 *sparx5, int pgid, in sparx5_mact_learn() argument
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| /linux-6.14.4/drivers/reset/ |
| D | reset-microchip-sparx5.c | 1 // SPDX-License-Identifier: GPL-2.0+
2 /* Microchip Sparx5 Switch Reset driver
6 * The Sparx5 Chip Register Model can be browsed at this location:
7 * https://github.com/microchip-ung/sparx-5_reginfo
16 #include <linux/reset-controller.h>
42 /* Make sure the core is PROTECTED from reset */ in sparx5_switch_reset()
43 regmap_update_bits(ctx->cpu_ctrl, ctx->props->protect_reg, in sparx5_switch_reset()
44 ctx->props->protect_bit, ctx->props->protect_bit); in sparx5_switch_reset()
46 /* Start soft reset */ in sparx5_switch_reset()
47 regmap_write(ctx->gcb_ctrl, ctx->props->reset_reg, in sparx5_switch_reset()
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| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
6 bool "Reset Controller Support"
9 Generic Reset Controller support.
11 This framework is designed to abstract reset handling of devices
12 via GPIOs or SoC-internal reset controller modules.
19 tristate "Altera Arria10 System Resource Reset"
22 This option enables support for the external reset functions for
26 bool "AR71xx Reset Driver" if COMPILE_TEST
29 This enables the ATH79 reset controller driver that supports the
30 AR71xx SoC reset controller.
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| /linux-6.14.4/Documentation/devicetree/bindings/net/ |
| D | microchip,sparx5-switch.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/microchip,sparx5-switch.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip Sparx5 Ethernet switch controller
10 - Steen Hegelund <[email protected]>
11 - Lars Povlsen <[email protected]>
12 - Daniel Machon <[email protected]>
15 The SparX-5 Enterprise Ethernet switch family provides a rich set of
16 Enterprise switching features such as advanced TCAM-based VLAN and
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| /linux-6.14.4/drivers/net/ethernet/microchip/sparx5/lan969x/ |
| D | lan969x_rgmii.c | 1 // SPDX-License-Identifier: GPL-2.0+
2 /* Microchip lan969x Switch driver
32 #define RGMII_PORT_IDX(port) ((port)->portno - LAN969X_RGMII_PORT_START_IDX)
54 switch (delay_ps) { in lan969x_rgmii_get_clk_delay_sel()
78 dev_err(port->sparx5->dev, "Invalid RGMII delay: %u", delay_ps); in lan969x_rgmii_get_clk_delay_sel()
79 return -EINVAL; in lan969x_rgmii_get_clk_delay_sel()
89 u32 clk_sel = lan969x_rgmii_get_clk_sel(conf->speed); in lan969x_rgmii_tx_clk_config()
92 /* Take the RGMII clock domain out of reset and set tx clock in lan969x_rgmii_tx_clk_config()
101 port->sparx5, HSIO_WRAP_RGMII_CFG(idx)); in lan969x_rgmii_tx_clk_config()
110 speed_sel = lan969x_rgmii_get_speed_sel(conf->speed); in lan969x_rgmii_port_device_config()
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| D | lan969x_fdma.c | 1 // SPDX-License-Identifier: GPL-2.0+
2 /* Microchip lan969x Switch driver
15 #define FDMA_PRIV(fdma) ((struct sparx5 *)((fdma)->priv))
20 *dataptr = FDMA_PRIV(fdma)->tx.dbs[dcb].dma_addr; in lan969x_fdma_tx_dataptr_cb()
28 struct sparx5_rx *rx = &FDMA_PRIV(fdma)->rx; in lan969x_fdma_rx_dataptr_cb()
31 page = page_pool_dev_alloc_pages(rx->page_pool); in lan969x_fdma_rx_dataptr_cb()
33 return -ENOMEM; in lan969x_fdma_rx_dataptr_cb()
35 rx->page[dcb][db] = page; in lan969x_fdma_rx_dataptr_cb()
44 struct fdma *fdma = &tx->fdma; in lan969x_fdma_get_next_dcb()
46 for (int i = 0; i < fdma->n_dcbs; ++i) in lan969x_fdma_get_next_dcb()
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| /linux-6.14.4/Documentation/devicetree/bindings/pinctrl/ |
| D | microchip,sparx5-sgpio.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/microchip,sparx5-sgpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lars Povlsen <[email protected]>
21 pattern: "^gpio@[0-9a-f]+$"
25 - microchip,sparx5-sgpio
26 - mscc,ocelot-sgpio
27 - mscc,luton-sgpio
29 "#address-cells":
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| D | mscc,ocelot-pinctrl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mscc,ocelot-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandre Belloni <[email protected]>
11 - Lars Povlsen <[email protected]>
16 - enum:
17 - microchip,lan966x-pinctrl
18 - microchip,lan9691-pinctrl
19 - microchip,sparx5-pinctrl
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| /linux-6.14.4/arch/arm/boot/dts/microchip/ |
| D | lan966x.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * lan966x.dtsi - Device Tree Include file for Microchip LAN966 family SoC
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/mfd/atmel-flexcom.h>
14 #include <dt-bindings/dma/at91.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/clock/microchip,lan966x.h>
21 interrupt-parent = <&gic>;
22 #address-cells = <1>;
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| /linux-6.14.4/drivers/phy/microchip/ |
| D | sparx5_serdes.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Microchip Sparx5 Switch SerDes driver
6 * The Sparx5 Chip Register Model can be browsed at this location:
7 * https://github.com/microchip-ung/sparx-5_reginfo
9 …* https://ww1.microchip.com/downloads/en/DeviceDoc/SparX-5_Family_L2L3_Enterprise_10G_Ethernet_Swi…
114 u8 if_width; /* UDL if-width: 10/16/20/32/64 */
117 bool no_pwrcycle:1; /* Omit initial power-cycle */
256 bool no_pwrcycle:1; /* Omit initial power-cycle */
629 switch (interface_width) { in sd25g28_get_iw_setting()
645 switch (interface_width) { in sd10g28_get_iw_setting()
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| /linux-6.14.4/drivers/pinctrl/ |
| D | pinctrl-microchip-sgpio.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
21 #include <linux/reset.h>
138 addr->port = pin / priv->bitcount; in sgpio_pin_to_addr()
139 addr->bit = pin % priv->bitcount; in sgpio_pin_to_addr()
144 return bit + port * priv->bitcount; in sgpio_addr_to_pin()
149 return (priv->properties->regoff[rno] + off) * in sgpio_get_addr()
150 regmap_get_reg_stride(priv->regs); in sgpio_get_addr()
159 ret = regmap_read(priv->regs, addr, &val); in sgpio_readl()
171 ret = regmap_write(priv->regs, addr, val); in sgpio_writel()
181 ret = regmap_update_bits(priv->regs, addr, clear | set, set); in sgpio_clrsetbits()
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| D | pinctrl-ocelot.c | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 * Author: <alexandre.belloni@free-electrons.com>
17 #include <linux/reset.h>
21 #include <linux/pinctrl/pinconf-generic.h>
1342 *groups = info->func[function].groups; in ocelot_get_function_groups()
1343 *num_groups = info->func[function].ngroups; in ocelot_get_function_groups()
1351 struct ocelot_pin_caps *p = info->desc->pins[pin].drv_data; in ocelot_pin_function_idx()
1355 if (function == p->functions[i]) in ocelot_pin_function_idx()
1358 if (function == p->a_functions[i]) in ocelot_pin_function_idx()
1362 return -1; in ocelot_pin_function_idx()
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| /linux-6.14.4/ |
| D | MAINTAINERS | 5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-[email protected]
88 F: drivers/scsi/3w-*
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