Lines Matching +full:sparx5 +full:- +full:switch +full:- +full:reset
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Microchip Sparx5 Switch SerDes driver
6 * The Sparx5 Chip Register Model can be browsed at this location:
7 * https://github.com/microchip-ung/sparx-5_reginfo
9 …* https://ww1.microchip.com/downloads/en/DeviceDoc/SparX-5_Family_L2L3_Enterprise_10G_Ethernet_Swi…
114 u8 if_width; /* UDL if-width: 10/16/20/32/64 */
117 bool no_pwrcycle:1; /* Omit initial power-cycle */
256 bool no_pwrcycle:1; /* Omit initial power-cycle */
629 switch (interface_width) { in sd25g28_get_iw_setting()
645 switch (interface_width) { in sd10g28_get_iw_setting()
662 switch (macro->serdesmode) { in sparx5_sd10g25_get_mode_preset()
664 if (macro->speed == SPEED_25000) in sparx5_sd10g25_get_mode_preset()
666 else if (macro->speed == SPEED_10000) in sparx5_sd10g25_get_mode_preset()
668 else if (macro->speed == SPEED_5000) in sparx5_sd10g25_get_mode_preset()
679 return -EINVAL; in sparx5_sd10g25_get_mode_preset()
691 switch (macro->serdesmode) { in sparx5_sd10g28_get_mode_preset()
693 if (macro->speed == SPEED_10000) { in sparx5_sd10g28_get_mode_preset()
695 } else if (macro->speed == SPEED_5000) { in sparx5_sd10g28_get_mode_preset()
696 if (args->is_6g) in sparx5_sd10g28_get_mode_preset()
701 dev_err(macro->priv->dev, "%s: Illegal speed: %02u, sidx: %02u, mode (%u)", in sparx5_sd10g28_get_mode_preset()
702 __func__, macro->speed, macro->sidx, in sparx5_sd10g28_get_mode_preset()
703 macro->serdesmode); in sparx5_sd10g28_get_mode_preset()
704 return -EINVAL; in sparx5_sd10g28_get_mode_preset()
730 u8 iw = sd25g28_get_iw_setting(macro->priv->dev, mode->bitwidth); in sparx5_sd25g28_get_params()
733 .r_txfifo_ck_div_pmad_2_0 = mode->fifo_ck_div, in sparx5_sd25g28_get_params()
734 .r_rxfifo_ck_div_pmad_2_0 = mode->fifo_ck_div, in sparx5_sd25g28_get_params()
735 .cfg_vco_div_mode_1_0 = mode->vco_div_mode, in sparx5_sd25g28_get_params()
736 .cfg_pre_divsel_1_0 = mode->pre_divsel, in sparx5_sd25g28_get_params()
737 .cfg_sel_div_3_0 = mode->sel_div, in sparx5_sd25g28_get_params()
739 .cfg_pma_tx_ck_bitwidth_2_0 = mode->ck_bitwidth, in sparx5_sd25g28_get_params()
740 .cfg_tx_prediv_1_0 = mode->tx_pre_div, in sparx5_sd25g28_get_params()
741 .cfg_rxdiv_sel_2_0 = mode->ck_bitwidth, in sparx5_sd25g28_get_params()
742 .cfg_tx_subrate_2_0 = mode->subrate, in sparx5_sd25g28_get_params()
743 .cfg_rx_subrate_2_0 = mode->subrate, in sparx5_sd25g28_get_params()
746 .cfg_dfeck_en = mode->dfe_enable, in sparx5_sd25g28_get_params()
747 .cfg_dfe_pd = mode->dfe_enable == 1 ? 0 : 1, in sparx5_sd25g28_get_params()
749 .cfg_dfetap_en_5_1 = mode->dfe_tap, in sparx5_sd25g28_get_params()
752 .cfg_erramp_pd = mode->dfe_enable == 1 ? 0 : 1, in sparx5_sd25g28_get_params()
753 .cfg_pi_DFE_en = mode->dfe_enable, in sparx5_sd25g28_get_params()
766 .cfg_itx_ipdriver_base_2_0 = mode->txmargin, in sparx5_sd25g28_get_params()
767 .cfg_tap_dly_4_0 = media->cfg_tap_dly_4_0, in sparx5_sd25g28_get_params()
768 .cfg_tap_main = media->cfg_tap_main, in sparx5_sd25g28_get_params()
769 .cfg_en_main = media->cfg_en_main, in sparx5_sd25g28_get_params()
770 .cfg_tap_adv_3_0 = media->cfg_tap_adv_3_0, in sparx5_sd25g28_get_params()
771 .cfg_en_adv = media->cfg_en_adv, in sparx5_sd25g28_get_params()
772 .cfg_en_dly = media->cfg_en_dly, in sparx5_sd25g28_get_params()
777 .cfg_pll_reserve_3_0 = args->com_pll_reserve, in sparx5_sd25g28_get_params()
778 .l0_cfg_txcal_en = mode->com_txcal_en, in sparx5_sd25g28_get_params()
779 .l0_cfg_tx_reserve_15_8 = mode->com_tx_reserve_msb, in sparx5_sd25g28_get_params()
780 .l0_cfg_tx_reserve_7_0 = mode->com_tx_reserve_lsb, in sparx5_sd25g28_get_params()
781 .cfg_tx_reserve_15_8 = mode->tx_reserve_msb, in sparx5_sd25g28_get_params()
782 .cfg_tx_reserve_7_0 = mode->tx_reserve_lsb, in sparx5_sd25g28_get_params()
783 .cfg_bw_1_0 = mode->bw, in sparx5_sd25g28_get_params()
792 .cfg_pi_bw_3_0 = mode->cfg_pi_bw_3_0, in sparx5_sd25g28_get_params()
795 .cfg_ctle_rstn = mode->cfg_ctle_rstn, in sparx5_sd25g28_get_params()
796 .r_dfe_rstn = mode->r_dfe_rstn, in sparx5_sd25g28_get_params()
797 .cfg_alos_thr_2_0 = media->cfg_alos_thr_2_0, in sparx5_sd25g28_get_params()
798 .cfg_itx_ipcml_base_1_0 = mode->cfg_itx_ipcml_base, in sparx5_sd25g28_get_params()
801 .cfg_rxterm_2_0 = mode->rxterm, in sparx5_sd25g28_get_params()
805 .cfg_vga_ctrl_byp_4_0 = media->cfg_vga_ctrl_byp_4_0, in sparx5_sd25g28_get_params()
809 .cfg_eqr_force_3_0 = media->cfg_eq_r_force_3_0, in sparx5_sd25g28_get_params()
810 .cfg_eqc_force_3_0 = media->cfg_eq_c_force_3_0, in sparx5_sd25g28_get_params()
816 .cfg_en_dfedig = mode->dfe_enable, in sparx5_sd25g28_get_params()
819 .reg_rst = args->reg_rst, in sparx5_sd25g28_get_params()
827 .r_tx_pol_inv = args->txinvert, in sparx5_sd25g28_get_params()
828 .r_rx_pol_inv = args->rxinvert, in sparx5_sd25g28_get_params()
840 u8 iw = sd10g28_get_iw_setting(macro->priv->dev, mode->bwidth); in sparx5_sd10g28_get_params()
842 .skip_cmu_cfg = args->skip_cmu_cfg, in sparx5_sd10g28_get_params()
843 .is_6g = args->is_6g, in sparx5_sd10g28_get_params()
844 .cmu_sel = mode->cmu_sel, in sparx5_sd10g28_get_params()
845 .cfg_lane_reserve_7_0 = (mode->cmu_sel % 2) << 6, in sparx5_sd10g28_get_params()
846 .cfg_ssc_rtl_clk_sel = (mode->cmu_sel / 2), in sparx5_sd10g28_get_params()
847 .cfg_lane_reserve_15_8 = mode->duty_cycle, in sparx5_sd10g28_get_params()
848 .cfg_txrate_1_0 = mode->rate, in sparx5_sd10g28_get_params()
849 .cfg_rxrate_1_0 = mode->rate, in sparx5_sd10g28_get_params()
850 .fx_100 = macro->serdesmode == SPX5_SD_MODE_100FX, in sparx5_sd10g28_get_params()
857 .cfg_dfeck_en = mode->dfe_enable, in sparx5_sd10g28_get_params()
858 .cfg_dfe_pd = (mode->dfe_enable == 1) ? 0 : 1, in sparx5_sd10g28_get_params()
859 .cfg_dfetap_en_5_1 = mode->dfe_tap, in sparx5_sd10g28_get_params()
860 .cfg_erramp_pd = (mode->dfe_enable == 1) ? 0 : 1, in sparx5_sd10g28_get_params()
861 .cfg_pi_DFE_en = mode->dfe_enable, in sparx5_sd10g28_get_params()
871 .cfg_pd_sq = mode->dfe_enable, in sparx5_sd10g28_get_params()
875 .cfg_en_adv = media->cfg_en_adv, in sparx5_sd10g28_get_params()
877 .cfg_en_dly = media->cfg_en_dly, in sparx5_sd10g28_get_params()
878 .cfg_tap_adv_3_0 = media->cfg_tap_adv_3_0, in sparx5_sd10g28_get_params()
879 .cfg_tap_main = media->cfg_tap_main, in sparx5_sd10g28_get_params()
880 .cfg_tap_dly_4_0 = media->cfg_tap_dly_4_0, in sparx5_sd10g28_get_params()
881 .cfg_vga_ctrl_3_0 = media->cfg_vga_ctrl_3_0, in sparx5_sd10g28_get_params()
882 .cfg_vga_cp_2_0 = media->cfg_vga_cp_2_0, in sparx5_sd10g28_get_params()
883 .cfg_eq_res_3_0 = media->cfg_eq_res_3_0, in sparx5_sd10g28_get_params()
884 .cfg_eq_r_byp = media->cfg_eq_r_byp, in sparx5_sd10g28_get_params()
885 .cfg_eq_c_force_3_0 = media->cfg_eq_c_force_3_0, in sparx5_sd10g28_get_params()
886 .cfg_en_dfedig = mode->dfe_enable, in sparx5_sd10g28_get_params()
890 .cfg_itx_ipdriver_base_2_0 = (args->txswing >> 6), in sparx5_sd10g28_get_params()
891 .cfg_ibias_tune_reserve_5_0 = (args->txswing & 63), in sparx5_sd10g28_get_params()
892 .cfg_txswing_half = (args->txmargin), in sparx5_sd10g28_get_params()
904 .cfg_pi_bw_gen1_3_0 = mode->pi_bw_gen1, in sparx5_sd10g28_get_params()
905 .cfg_pi_bw_gen2 = mode->pi_bw_gen1, in sparx5_sd10g28_get_params()
906 .cfg_pi_bw_gen3 = mode->pi_bw_gen1, in sparx5_sd10g28_get_params()
907 .cfg_pi_bw_gen4 = mode->pi_bw_gen1, in sparx5_sd10g28_get_params()
911 .cfg_rstn_dfedig = mode->dfe_enable, in sparx5_sd10g28_get_params()
912 .cfg_alos_thr_3_0 = media->cfg_alos_thr_3_0, in sparx5_sd10g28_get_params()
933 .r_tx_pol_inv = args->txinvert, in sparx5_sd10g28_get_params()
934 .r_rx_pol_inv = args->rxinvert, in sparx5_sd10g28_get_params()
946 void __iomem **regs = priv->regs; in sparx5_cmu_apply_cfg()
947 struct device *dev = priv->dev; in sparx5_cmu_apply_cfg()
1050 return -EINVAL; in sparx5_cmu_apply_cfg()
1132 for (i = 0; i < priv->data->consts.cmu_max; i++) { in sparx5_serdes_cmu_power_off()
1178 if (params->reg_rst == 1) { in sparx5_sd25g28_reset()
1194 struct sparx5_serdes_private *priv = macro->priv; in sparx5_sd25g28_apply_params()
1195 void __iomem **regs = priv->regs; in sparx5_sd25g28_apply_params()
1196 struct device *dev = priv->dev; in sparx5_sd25g28_apply_params()
1197 u32 sd_index = macro->stpidx; in sparx5_sd25g28_apply_params()
1211 (params->r_d_width_ctrl_from_hwt) | in sparx5_sd25g28_apply_params()
1212 SD25G_LANE_CMU_1A_R_REG_MANUAL_SET(params->r_reg_manual), in sparx5_sd25g28_apply_params()
1219 (params->cfg_common_reserve_7_0), in sparx5_sd25g28_apply_params()
1224 sdx5_rmw(SD25G_LANE_CMU_09_CFG_EN_DUMMY_SET(params->cfg_en_dummy), in sparx5_sd25g28_apply_params()
1230 (params->cfg_pll_reserve_3_0), in sparx5_sd25g28_apply_params()
1235 sdx5_rmw(SD25G_LANE_CMU_40_L0_CFG_TXCAL_EN_SET(params->l0_cfg_txcal_en), in sparx5_sd25g28_apply_params()
1241 (params->l0_cfg_tx_reserve_15_8), in sparx5_sd25g28_apply_params()
1247 (params->l0_cfg_tx_reserve_7_0), in sparx5_sd25g28_apply_params()
1282 sdx5_rmw(SD25G_LANE_CMU_1A_R_DWIDTHCTRL_2_0_SET(params->r_d_width_ctrl_2_0), in sparx5_sd25g28_apply_params()
1288 (params->r_txfifo_ck_div_pmad_2_0) | in sparx5_sd25g28_apply_params()
1290 (params->r_rxfifo_ck_div_pmad_2_0), in sparx5_sd25g28_apply_params()
1296 sdx5_rmw(SD25G_LANE_CMU_0C_CFG_PLL_LOL_SET_SET(params->cfg_pll_lol_set) | in sparx5_sd25g28_apply_params()
1298 (params->cfg_vco_div_mode_1_0), in sparx5_sd25g28_apply_params()
1305 (params->cfg_pre_divsel_1_0), in sparx5_sd25g28_apply_params()
1310 sdx5_rmw(SD25G_LANE_CMU_0E_CFG_SEL_DIV_3_0_SET(params->cfg_sel_div_3_0), in sparx5_sd25g28_apply_params()
1321 (params->cfg_pma_tx_ck_bitwidth_2_0), in sparx5_sd25g28_apply_params()
1327 (params->cfg_tx_prediv_1_0), in sparx5_sd25g28_apply_params()
1333 (params->cfg_rxdiv_sel_2_0), in sparx5_sd25g28_apply_params()
1339 (params->cfg_tx_subrate_2_0), in sparx5_sd25g28_apply_params()
1345 (params->cfg_rx_subrate_2_0), in sparx5_sd25g28_apply_params()
1350 sdx5_rmw(SD25G_LANE_LANE_18_LN_CFG_CDRCK_EN_SET(params->cfg_cdrck_en), in sparx5_sd25g28_apply_params()
1356 (params->cfg_dfetap_en_5_1), in sparx5_sd25g28_apply_params()
1361 sdx5_rmw(SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD_SET(params->cfg_erramp_pd), in sparx5_sd25g28_apply_params()
1366 sdx5_rmw(SD25G_LANE_LANE_1D_LN_CFG_PI_DFE_EN_SET(params->cfg_pi_dfe_en), in sparx5_sd25g28_apply_params()
1371 sdx5_rmw(SD25G_LANE_LANE_19_LN_CFG_ECDR_PD_SET(params->cfg_ecdr_pd), in sparx5_sd25g28_apply_params()
1377 (params->cfg_itx_ipdriver_base_2_0), in sparx5_sd25g28_apply_params()
1382 sdx5_rmw(SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0_SET(params->cfg_tap_dly_4_0), in sparx5_sd25g28_apply_params()
1387 sdx5_rmw(SD25G_LANE_LANE_06_LN_CFG_TAP_ADV_3_0_SET(params->cfg_tap_adv_3_0), in sparx5_sd25g28_apply_params()
1392 sdx5_rmw(SD25G_LANE_LANE_07_LN_CFG_EN_ADV_SET(params->cfg_en_adv) | in sparx5_sd25g28_apply_params()
1393 SD25G_LANE_LANE_07_LN_CFG_EN_DLY_SET(params->cfg_en_dly), in sparx5_sd25g28_apply_params()
1400 (params->cfg_tx_reserve_15_8), in sparx5_sd25g28_apply_params()
1406 (params->cfg_tx_reserve_7_0), in sparx5_sd25g28_apply_params()
1411 sdx5_rmw(SD25G_LANE_LANE_05_LN_CFG_BW_1_0_SET(params->cfg_bw_1_0), in sparx5_sd25g28_apply_params()
1417 (params->cfg_txcal_man_en), in sparx5_sd25g28_apply_params()
1423 (params->cfg_txcal_shift_code_5_0), in sparx5_sd25g28_apply_params()
1429 (params->cfg_txcal_valid_sel_3_0), in sparx5_sd25g28_apply_params()
1434 sdx5_rmw(SD25G_LANE_LANE_1A_LN_CFG_CDR_KF_2_0_SET(params->cfg_cdr_kf_2_0), in sparx5_sd25g28_apply_params()
1439 sdx5_rmw(SD25G_LANE_LANE_1B_LN_CFG_CDR_M_7_0_SET(params->cfg_cdr_m_7_0), in sparx5_sd25g28_apply_params()
1444 sdx5_rmw(SD25G_LANE_LANE_2B_LN_CFG_PI_BW_3_0_SET(params->cfg_pi_bw_3_0), in sparx5_sd25g28_apply_params()
1450 (params->cfg_dis_2ndorder), in sparx5_sd25g28_apply_params()
1455 sdx5_rmw(SD25G_LANE_LANE_2E_LN_CFG_CTLE_RSTN_SET(params->cfg_ctle_rstn), in sparx5_sd25g28_apply_params()
1461 (params->cfg_itx_ipcml_base_1_0), in sparx5_sd25g28_apply_params()
1467 (params->cfg_rx_reserve_7_0), in sparx5_sd25g28_apply_params()
1473 (params->cfg_rx_reserve_15_8), in sparx5_sd25g28_apply_params()
1478 sdx5_rmw(SD25G_LANE_LANE_0D_LN_CFG_DFECK_EN_SET(params->cfg_dfeck_en) | in sparx5_sd25g28_apply_params()
1479 SD25G_LANE_LANE_0D_LN_CFG_RXTERM_2_0_SET(params->cfg_rxterm_2_0), in sparx5_sd25g28_apply_params()
1486 (params->cfg_vga_ctrl_byp_4_0), in sparx5_sd25g28_apply_params()
1492 (params->cfg_eqr_force_3_0), in sparx5_sd25g28_apply_params()
1498 (params->cfg_eqc_force_3_0) | in sparx5_sd25g28_apply_params()
1499 SD25G_LANE_LANE_1C_LN_CFG_DFE_PD_SET(params->cfg_dfe_pd), in sparx5_sd25g28_apply_params()
1506 (params->cfg_sum_setcm_en), in sparx5_sd25g28_apply_params()
1512 (params->cfg_init_pos_iscan_6_0), in sparx5_sd25g28_apply_params()
1518 (params->cfg_init_pos_ipi_6_0), in sparx5_sd25g28_apply_params()
1523 sdx5_rmw(SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD_SET(params->cfg_erramp_pd), in sparx5_sd25g28_apply_params()
1529 (params->cfg_dfedig_m_2_0), in sparx5_sd25g28_apply_params()
1534 sdx5_rmw(SD25G_LANE_LANE_0E_LN_CFG_EN_DFEDIG_SET(params->cfg_en_dfedig), in sparx5_sd25g28_apply_params()
1539 sdx5_rmw(SD25G_LANE_LANE_40_LN_R_TX_POL_INV_SET(params->r_tx_pol_inv) | in sparx5_sd25g28_apply_params()
1540 SD25G_LANE_LANE_40_LN_R_RX_POL_INV_SET(params->r_rx_pol_inv), in sparx5_sd25g28_apply_params()
1546 sdx5_rmw(SD25G_LANE_LANE_04_LN_CFG_RX2TX_LP_EN_SET(params->cfg_rx2tx_lp_en) | in sparx5_sd25g28_apply_params()
1547 SD25G_LANE_LANE_04_LN_CFG_TX2RX_LP_EN_SET(params->cfg_tx2rx_lp_en), in sparx5_sd25g28_apply_params()
1553 sdx5_rmw(SD25G_LANE_LANE_1E_LN_CFG_RXLB_EN_SET(params->cfg_rxlb_en), in sparx5_sd25g28_apply_params()
1558 sdx5_rmw(SD25G_LANE_LANE_19_LN_CFG_TXLB_EN_SET(params->cfg_txlb_en), in sparx5_sd25g28_apply_params()
1602 return -EINVAL; in sparx5_sd25g28_apply_params()
1609 dev_err(dev, "25G PMA Reset failed: 0x%x\n", value); in sparx5_sd25g28_apply_params()
1610 return -EINVAL; in sparx5_sd25g28_apply_params()
1633 (params->cfg_alos_thr_2_0), in sparx5_sd25g28_apply_params()
1668 struct sparx5_serdes_private *priv = macro->priv; in sparx5_sd10g28_apply_params()
1669 void __iomem **regs = priv->regs; in sparx5_sd10g28_apply_params()
1670 struct device *dev = priv->dev; in sparx5_sd10g28_apply_params()
1671 u32 lane_index = macro->sidx; in sparx5_sd10g28_apply_params()
1672 u32 sd_index = macro->stpidx; in sparx5_sd10g28_apply_params()
1678 if (params->skip_cmu_cfg) in sparx5_sd10g28_apply_params()
1681 cmu_idx = priv->data->ops.serdes_cmu_get(params->cmu_sel, macro->sidx); in sparx5_sd10g28_apply_params()
1686 if (params->is_6g) in sparx5_sd10g28_apply_params()
1734 sdx5_rmw(SD_LANE_SD_LANE_CFG_RX_REF_SEL_SET(params->cmu_sel) | in sparx5_sd10g28_apply_params()
1735 SD_LANE_SD_LANE_CFG_TX_REF_SEL_SET(params->cmu_sel), in sparx5_sd10g28_apply_params()
1742 (params->cfg_lane_reserve_7_0), in sparx5_sd10g28_apply_params()
1748 (params->cfg_ssc_rtl_clk_sel), in sparx5_sd10g28_apply_params()
1754 (params->cfg_txrate_1_0) | in sparx5_sd10g28_apply_params()
1756 (params->cfg_rxrate_1_0), in sparx5_sd10g28_apply_params()
1763 (params->r_d_width_ctrl_2_0), in sparx5_sd10g28_apply_params()
1769 (params->cfg_pma_tx_ck_bitwidth_2_0), in sparx5_sd10g28_apply_params()
1775 (params->cfg_rxdiv_sel_2_0), in sparx5_sd10g28_apply_params()
1781 (params->r_pcs2pma_phymode_4_0), in sparx5_sd10g28_apply_params()
1786 sdx5_inst_rmw(SD10G_LANE_LANE_13_CFG_CDRCK_EN_SET(params->cfg_cdrck_en), in sparx5_sd10g28_apply_params()
1792 (params->cfg_dfeck_en) | in sparx5_sd10g28_apply_params()
1793 SD10G_LANE_LANE_23_CFG_DFE_PD_SET(params->cfg_dfe_pd) | in sparx5_sd10g28_apply_params()
1795 (params->cfg_erramp_pd), in sparx5_sd10g28_apply_params()
1803 (params->cfg_dfetap_en_5_1), in sparx5_sd10g28_apply_params()
1809 (params->cfg_pi_DFE_en), in sparx5_sd10g28_apply_params()
1814 sdx5_inst_rmw(SD10G_LANE_LANE_02_CFG_EN_ADV_SET(params->cfg_en_adv) | in sparx5_sd10g28_apply_params()
1815 SD10G_LANE_LANE_02_CFG_EN_MAIN_SET(params->cfg_en_main) | in sparx5_sd10g28_apply_params()
1816 SD10G_LANE_LANE_02_CFG_EN_DLY_SET(params->cfg_en_dly) | in sparx5_sd10g28_apply_params()
1818 (params->cfg_tap_adv_3_0), in sparx5_sd10g28_apply_params()
1826 sdx5_inst_rmw(SD10G_LANE_LANE_03_CFG_TAP_MAIN_SET(params->cfg_tap_main), in sparx5_sd10g28_apply_params()
1832 (params->cfg_tap_dly_4_0), in sparx5_sd10g28_apply_params()
1838 (params->cfg_vga_ctrl_3_0), in sparx5_sd10g28_apply_params()
1844 (params->cfg_vga_cp_2_0), in sparx5_sd10g28_apply_params()
1850 (params->cfg_eq_res_3_0), in sparx5_sd10g28_apply_params()
1855 sdx5_inst_rmw(SD10G_LANE_LANE_0D_CFG_EQR_BYP_SET(params->cfg_eq_r_byp), in sparx5_sd10g28_apply_params()
1861 (params->cfg_eq_c_force_3_0) | in sparx5_sd10g28_apply_params()
1863 (params->cfg_sum_setcm_en), in sparx5_sd10g28_apply_params()
1870 (params->cfg_en_dfedig), in sparx5_sd10g28_apply_params()
1876 (params->cfg_en_preemph), in sparx5_sd10g28_apply_params()
1882 (params->cfg_itx_ippreemp_base_1_0) | in sparx5_sd10g28_apply_params()
1884 (params->cfg_itx_ipdriver_base_2_0), in sparx5_sd10g28_apply_params()
1891 (params->cfg_ibias_tune_reserve_5_0), in sparx5_sd10g28_apply_params()
1897 (params->cfg_txswing_half), in sparx5_sd10g28_apply_params()
1903 (params->cfg_dis_2nd_order), in sparx5_sd10g28_apply_params()
1909 (params->cfg_rx_ssc_lh), in sparx5_sd10g28_apply_params()
1915 (params->cfg_pi_floop_steps_1_0), in sparx5_sd10g28_apply_params()
1921 (params->cfg_pi_ext_dac_23_16), in sparx5_sd10g28_apply_params()
1927 (params->cfg_pi_ext_dac_15_8), in sparx5_sd10g28_apply_params()
1933 (params->cfg_iscan_ext_dac_7_0), in sparx5_sd10g28_apply_params()
1939 (params->cfg_cdr_kf_gen1_2_0), in sparx5_sd10g28_apply_params()
1945 (params->r_cdr_m_gen1_7_0), in sparx5_sd10g28_apply_params()
1951 (params->cfg_pi_bw_gen1_3_0), in sparx5_sd10g28_apply_params()
1957 (params->cfg_pi_ext_dac_7_0), in sparx5_sd10g28_apply_params()
1962 sdx5_inst_rmw(SD10G_LANE_LANE_1A_CFG_PI_STEPS_SET(params->cfg_pi_steps), in sparx5_sd10g28_apply_params()
1968 (params->cfg_mp_max_3_0), in sparx5_sd10g28_apply_params()
1974 (params->cfg_rstn_dfedig), in sparx5_sd10g28_apply_params()
1980 (params->cfg_alos_thr_3_0), in sparx5_sd10g28_apply_params()
1986 (params->cfg_predrv_slewrate_1_0), in sparx5_sd10g28_apply_params()
1992 (params->cfg_itx_ipcml_base_1_0), in sparx5_sd10g28_apply_params()
1998 (params->cfg_ip_pre_base_1_0), in sparx5_sd10g28_apply_params()
2004 (params->cfg_lane_reserve_15_8), in sparx5_sd10g28_apply_params()
2010 (params->r_en_auto_cdr_rstn), in sparx5_sd10g28_apply_params()
2016 (params->cfg_oscal_afe) | in sparx5_sd10g28_apply_params()
2018 (params->cfg_pd_osdac_afe), in sparx5_sd10g28_apply_params()
2025 (params->cfg_resetb_oscal_afe[0]), in sparx5_sd10g28_apply_params()
2031 (params->cfg_resetb_oscal_afe[1]), in sparx5_sd10g28_apply_params()
2037 (params->r_tx_pol_inv) | in sparx5_sd10g28_apply_params()
2039 (params->r_rx_pol_inv), in sparx5_sd10g28_apply_params()
2046 (params->cfg_rx2tx_lp_en) | in sparx5_sd10g28_apply_params()
2048 (params->cfg_tx2rx_lp_en), in sparx5_sd10g28_apply_params()
2054 sdx5_inst_rmw(SD10G_LANE_LANE_0E_CFG_RXLB_EN_SET(params->cfg_rxlb_en) | in sparx5_sd10g28_apply_params()
2055 SD10G_LANE_LANE_0E_CFG_TXLB_EN_SET(params->cfg_txlb_en), in sparx5_sd10g28_apply_params()
2076 sdx5_rmw(SD_LANE_MISC_SD_125_RST_DIS_SET(params->fx_100), in sparx5_sd10g28_apply_params()
2081 sdx5_rmw(SD_LANE_MISC_RX_ENA_SET(params->fx_100), in sparx5_sd10g28_apply_params()
2086 sdx5_rmw(SD_LANE_MISC_MUX_ENA_SET(params->fx_100), in sparx5_sd10g28_apply_params()
2096 dev_err(dev, "10G PMA Reset failed: 0x%x\n", value); in sparx5_sd10g28_apply_params()
2097 return -EINVAL; in sparx5_sd10g28_apply_params()
2113 static int sparx5_sd25g28_config(struct sparx5_serdes_macro *macro, bool reset) in sparx5_sd25g28_config() argument
2115 struct sparx5_sd25g28_media_preset media = media_presets_25g[macro->media]; in sparx5_sd25g28_config()
2122 .reg_rst = reset, in sparx5_sd25g28_config()
2131 sparx5_sd25g28_reset(macro->priv->regs, ¶ms, macro->stpidx); in sparx5_sd25g28_config()
2135 static int sparx5_sd10g28_config(struct sparx5_serdes_macro *macro, bool reset) in sparx5_sd10g28_config() argument
2137 struct sparx5_sd10g28_media_preset media = media_presets_10g[macro->media]; in sparx5_sd10g28_config()
2141 .is_6g = (macro->serdestype == SPX5_SDT_6G), in sparx5_sd10g28_config()
2145 .reg_rst = reset, in sparx5_sd10g28_config()
2146 .skip_cmu_cfg = reset, in sparx5_sd10g28_config()
2154 sparx5_sd10g28_reset(macro->priv->regs, macro->sidx); in sparx5_sd10g28_config()
2161 struct sparx5_serdes_private *priv = macro->priv; in sparx5_serdes_power_save()
2164 if (macro->serdestype == SPX5_SDT_6G) in sparx5_serdes_power_save()
2165 sd_inst = sdx5_inst_get(priv, TARGET_SD6G_LANE, macro->stpidx); in sparx5_serdes_power_save()
2166 else if (macro->serdestype == SPX5_SDT_10G) in sparx5_serdes_power_save()
2167 sd_inst = sdx5_inst_get(priv, TARGET_SD10G_LANE, macro->stpidx); in sparx5_serdes_power_save()
2169 sd_inst = sdx5_inst_get(priv, TARGET_SD25G_LANE, macro->stpidx); in sparx5_serdes_power_save()
2171 if (macro->serdestype == SPX5_SDT_25G) { in sparx5_serdes_power_save()
2173 macro->stpidx); in sparx5_serdes_power_save()
2174 /* Take serdes out of reset */ in sparx5_serdes_power_save()
2190 sd_lane_inst = sdx5_inst_get(priv, TARGET_SD_LANE, macro->sidx); in sparx5_serdes_power_save()
2192 /* Take serdes out of reset */ in sparx5_serdes_power_save()
2212 struct sparx5_serdes_private *priv = macro->priv; in sparx5_serdes_clock_config()
2214 /* Clock is auto-detected in 100Base-FX mode on lan969x */ in sparx5_serdes_clock_config()
2215 if (priv->data->type == SPX5_TARGET_LAN969X) in sparx5_serdes_clock_config()
2218 if (macro->serdesmode == SPX5_SD_MODE_100FX) { in sparx5_serdes_clock_config()
2219 u32 freq = priv->coreclock == 250000000 ? 2 : in sparx5_serdes_clock_config()
2220 priv->coreclock == 500000000 ? 1 : 0; in sparx5_serdes_clock_config()
2225 SD_LANE_MISC(macro->sidx)); in sparx5_serdes_clock_config()
2232 switch (portmode) { in sparx5_serdes_get_serdesmode()
2248 return -EINVAL; in sparx5_serdes_get_serdesmode()
2254 struct device *dev = macro->priv->dev; in sparx5_serdes_config()
2258 serdesmode = sparx5_serdes_get_serdesmode(macro->portmode, macro->speed); in sparx5_serdes_config()
2261 macro->sidx, in sparx5_serdes_config()
2262 phy_modes(macro->portmode)); in sparx5_serdes_config()
2265 macro->serdesmode = serdesmode; in sparx5_serdes_config()
2269 if (macro->serdestype == SPX5_SDT_25G) in sparx5_serdes_config()
2275 macro->sidx, err); in sparx5_serdes_config()
2299 return -EINVAL; in sparx5_serdes_set_mode()
2301 switch (submode) { in sparx5_serdes_set_mode()
2308 macro->portmode = submode; in sparx5_serdes_set_mode()
2312 return -EINVAL; in sparx5_serdes_set_mode()
2320 if (media != macro->media) { in sparx5_serdes_set_media()
2321 macro->media = media; in sparx5_serdes_set_media()
2322 if (macro->serdesmode != SPX5_SD_MODE_NONE) in sparx5_serdes_set_media()
2332 if (macro->priv->data->type == SPX5_TARGET_SPARX5) { in sparx5_serdes_set_speed()
2333 if (macro->sidx < SPX5_SERDES_10G_START && speed > SPEED_5000) in sparx5_serdes_set_speed()
2334 return -EINVAL; in sparx5_serdes_set_speed()
2335 if (macro->sidx < SPX5_SERDES_25G_START && speed > SPEED_10000) in sparx5_serdes_set_speed()
2336 return -EINVAL; in sparx5_serdes_set_speed()
2338 if (speed != macro->speed) { in sparx5_serdes_set_speed()
2339 macro->speed = speed; in sparx5_serdes_set_speed()
2340 if (macro->serdesmode != SPX5_SD_MODE_NONE) in sparx5_serdes_set_speed()
2351 if (macro->serdestype == SPX5_SDT_25G) in sparx5_serdes_reset()
2356 dev_err(&phy->dev, "SerDes %u, reset error: %d\n", in sparx5_serdes_reset()
2357 macro->sidx, err); in sparx5_serdes_reset()
2369 return -EINVAL; in sparx5_serdes_validate()
2371 if (macro->speed == 0) in sparx5_serdes_validate()
2372 return -EINVAL; in sparx5_serdes_validate()
2374 if (macro->priv->data->type == SPX5_TARGET_SPARX5) { in sparx5_serdes_validate()
2375 if (macro->sidx < SPX5_SERDES_10G_START && in sparx5_serdes_validate()
2376 macro->speed > SPEED_5000) in sparx5_serdes_validate()
2377 return -EINVAL; in sparx5_serdes_validate()
2378 if (macro->sidx < SPX5_SERDES_25G_START && in sparx5_serdes_validate()
2379 macro->speed > SPEED_10000) in sparx5_serdes_validate()
2380 return -EINVAL; in sparx5_serdes_validate()
2382 switch (submode) { in sparx5_serdes_validate()
2384 if (macro->speed != SPEED_100 && /* This is for 100BASE-FX */ in sparx5_serdes_validate()
2385 macro->speed != SPEED_1000) in sparx5_serdes_validate()
2386 return -EINVAL; in sparx5_serdes_validate()
2391 if (macro->speed >= SPEED_5000) in sparx5_serdes_validate()
2392 return -EINVAL; in sparx5_serdes_validate()
2395 if (macro->speed < SPEED_5000) in sparx5_serdes_validate()
2396 return -EINVAL; in sparx5_serdes_validate()
2399 return -EINVAL; in sparx5_serdes_validate()
2410 .reset = sparx5_serdes_reset,
2418 macro->serdestype = SPX5_SDT_6G; in sparx5_serdes_type_set()
2419 macro->stpidx = macro->sidx; in sparx5_serdes_type_set()
2421 macro->serdestype = SPX5_SDT_10G; in sparx5_serdes_type_set()
2422 macro->stpidx = macro->sidx - SPX5_SERDES_10G_START; in sparx5_serdes_type_set()
2424 macro->serdestype = SPX5_SDT_25G; in sparx5_serdes_type_set()
2425 macro->stpidx = macro->sidx - SPX5_SERDES_25G_START; in sparx5_serdes_type_set()
2431 macro->serdestype = SPX5_SDT_10G; in lan969x_serdes_type_set()
2432 macro->stpidx = macro->sidx; in lan969x_serdes_type_set()
2440 *phy = devm_phy_create(priv->dev, NULL, &sparx5_serdes_ops); in sparx5_phy_create()
2444 macro = devm_kzalloc(priv->dev, sizeof(*macro), GFP_KERNEL); in sparx5_phy_create()
2446 return -ENOMEM; in sparx5_phy_create()
2448 macro->sidx = idx; in sparx5_phy_create()
2449 macro->priv = priv; in sparx5_phy_create()
2450 macro->speed = SPEED_UNKNOWN; in sparx5_phy_create()
2452 priv->data->ops.serdes_type_set(macro, idx); in sparx5_phy_create()
2632 if (args->args_count != 1) in sparx5_serdes_xlate()
2633 return ERR_PTR(-EINVAL); in sparx5_serdes_xlate()
2635 sidx = args->args[0]; in sparx5_serdes_xlate()
2637 /* Check validity: ERR_PTR(-ENODEV) if not valid */ in sparx5_serdes_xlate()
2638 for (idx = 0; idx < priv->data->consts.sd_max; idx++) { in sparx5_serdes_xlate()
2640 phy_get_drvdata(priv->phys[idx]); in sparx5_serdes_xlate()
2642 if (sidx != macro->sidx) in sparx5_serdes_xlate()
2645 return priv->phys[idx]; in sparx5_serdes_xlate()
2647 return ERR_PTR(-ENODEV); in sparx5_serdes_xlate()
2652 struct device_node *np = pdev->dev.of_node; in sparx5_serdes_probe()
2662 if (!np && !pdev->dev.platform_data) in sparx5_serdes_probe()
2663 return -ENODEV; in sparx5_serdes_probe()
2665 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); in sparx5_serdes_probe()
2667 return -ENOMEM; in sparx5_serdes_probe()
2670 priv->dev = &pdev->dev; in sparx5_serdes_probe()
2672 priv->data = device_get_match_data(priv->dev); in sparx5_serdes_probe()
2673 if (!priv->data) in sparx5_serdes_probe()
2674 return -EINVAL; in sparx5_serdes_probe()
2676 tsize = priv->data->tsize; in sparx5_serdes_probe()
2679 clk = devm_clk_get(priv->dev, NULL); in sparx5_serdes_probe()
2681 dev_err(priv->dev, "Failed to get coreclock\n"); in sparx5_serdes_probe()
2686 dev_err(priv->dev, "Invalid coreclock %lu\n", clock); in sparx5_serdes_probe()
2687 return -EINVAL; in sparx5_serdes_probe()
2689 priv->coreclock = clock; in sparx5_serdes_probe()
2693 dev_err(priv->dev, "Invalid resource\n"); in sparx5_serdes_probe()
2694 return -EINVAL; in sparx5_serdes_probe()
2696 iomem = devm_ioremap(priv->dev, iores->start, resource_size(iores)); in sparx5_serdes_probe()
2698 dev_err(priv->dev, "Unable to get serdes registers: %s\n", in sparx5_serdes_probe()
2699 iores->name); in sparx5_serdes_probe()
2700 return -ENOMEM; in sparx5_serdes_probe()
2702 for (idx = 0; idx < priv->data->iomap_size; idx++) { in sparx5_serdes_probe()
2704 &priv->data->iomap[idx]; in sparx5_serdes_probe()
2706 priv->regs[iomap->id] = iomem + iomap->offset; in sparx5_serdes_probe()
2708 for (idx = 0; idx < priv->data->consts.sd_max; idx++) { in sparx5_serdes_probe()
2709 err = sparx5_phy_create(priv, idx, &priv->phys[idx]); in sparx5_serdes_probe()
2715 if (priv->data->type == SPX5_TARGET_SPARX5) in sparx5_serdes_probe()
2718 provider = devm_of_phy_provider_register(priv->dev, sparx5_serdes_xlate); in sparx5_serdes_probe()
2724 { .compatible = "microchip,sparx5-serdes", .data = &sparx5_desc },
2725 { .compatible = "microchip,lan9691-serdes", .data = &lan969x_desc },
2733 .name = "sparx5-serdes",
2740 MODULE_DESCRIPTION("Microchip Sparx5 switch serdes driver");