Lines Matching +full:sparx5 +full:- +full:switch +full:- +full:reset
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mscc,ocelot-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandre Belloni <[email protected]>
11 - Lars Povlsen <[email protected]>
16 - enum:
17 - microchip,lan966x-pinctrl
18 - microchip,lan9691-pinctrl
19 - microchip,sparx5-pinctrl
20 - mscc,jaguar2-pinctrl
21 - mscc,luton-pinctrl
22 - mscc,ocelot-pinctrl
23 - mscc,serval-pinctrl
24 - mscc,servalt-pinctrl
25 - items:
26 - enum:
27 - microchip,lan9698-pinctrl
28 - microchip,lan9696-pinctrl
29 - microchip,lan9694-pinctrl
30 - microchip,lan9693-pinctrl
31 - microchip,lan9692-pinctrl
32 - const: microchip,lan9691-pinctrl
36 - description: Base address
37 - description: Extended pin configuration registers
40 gpio-controller: true
42 '#gpio-cells':
45 gpio-ranges: true
50 interrupt-controller: true
52 "#interrupt-cells":
58 reset-names:
59 description: Optional shared switch reset.
61 - const: switch
64 '-pins$':
67 - $ref: pinmux-node.yaml
68 - $ref: pincfg-node.yaml
73 output-high: true
74 output-low: true
75 drive-strength: true
78 - function
79 - pins
84 - compatible
85 - reg
86 - gpio-controller
87 - '#gpio-cells'
88 - gpio-ranges
91 - $ref: pinctrl.yaml#
92 - if:
97 - microchip,lan966x-pinctrl
98 - microchip,lan9691-pinctrl
99 - microchip,sparx5-pinctrl
108 - |
110 compatible = "mscc,ocelot-pinctrl";
112 gpio-controller;
113 #gpio-cells = <2>;
114 gpio-ranges = <&gpio 0 0 22>;
116 uart_pins: uart-pins {
121 uart2_pins: uart2-pins {