1 // SPDX-License-Identifier: GPL-2.0+
2 /* Microchip lan969x Switch driver
3 *
4 * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries.
5 */
6
7 #include "lan969x.h"
8
9 /* Tx clock selectors */
10 #define LAN969X_RGMII_TX_CLK_SEL_125MHZ 1 /* 1000Mbps */
11 #define LAN969X_RGMII_TX_CLK_SEL_25MHZ 2 /* 100Mbps */
12 #define LAN969X_RGMII_TX_CLK_SEL_2M5MHZ 3 /* 10Mbps */
13
14 /* Port speed selectors */
15 #define LAN969X_RGMII_SPEED_SEL_10 0 /* Select 10Mbps speed */
16 #define LAN969X_RGMII_SPEED_SEL_100 1 /* Select 100Mbps speed */
17 #define LAN969X_RGMII_SPEED_SEL_1000 2 /* Select 1000Mbps speed */
18
19 /* Clock delay selectors */
20 #define LAN969X_RGMII_CLK_DELAY_SEL_1_0_NS 2 /* Phase shift 45deg */
21 #define LAN969X_RGMII_CLK_DELAY_SEL_1_7_NS 3 /* Phase shift 77deg */
22 #define LAN969X_RGMII_CLK_DELAY_SEL_2_0_NS 4 /* Phase shift 90deg */
23 #define LAN969X_RGMII_CLK_DELAY_SEL_2_5_NS 5 /* Phase shift 112deg */
24 #define LAN969X_RGMII_CLK_DELAY_SEL_3_0_NS 6 /* Phase shift 135deg */
25 #define LAN969X_RGMII_CLK_DELAY_SEL_3_3_NS 7 /* Phase shift 147deg */
26
27 #define LAN969X_RGMII_PORT_START_IDX 28 /* Index of the first RGMII port */
28 #define LAN969X_RGMII_IFG_TX 4 /* TX Inter Frame Gap value */
29 #define LAN969X_RGMII_IFG_RX1 5 /* RX1 Inter Frame Gap value */
30 #define LAN969X_RGMII_IFG_RX2 1 /* RX2 Inter Frame Gap value */
31
32 #define RGMII_PORT_IDX(port) ((port)->portno - LAN969X_RGMII_PORT_START_IDX)
33
34 /* Get the tx clock selector based on the port speed. */
lan969x_rgmii_get_clk_sel(int speed)35 static int lan969x_rgmii_get_clk_sel(int speed)
36 {
37 return (speed == SPEED_10 ? LAN969X_RGMII_TX_CLK_SEL_2M5MHZ :
38 speed == SPEED_100 ? LAN969X_RGMII_TX_CLK_SEL_25MHZ :
39 LAN969X_RGMII_TX_CLK_SEL_125MHZ);
40 }
41
42 /* Get the port speed selector based on the port speed. */
lan969x_rgmii_get_speed_sel(int speed)43 static int lan969x_rgmii_get_speed_sel(int speed)
44 {
45 return (speed == SPEED_10 ? LAN969X_RGMII_SPEED_SEL_10 :
46 speed == SPEED_100 ? LAN969X_RGMII_SPEED_SEL_100 :
47 LAN969X_RGMII_SPEED_SEL_1000);
48 }
49
50 /* Get the clock delay selector based on the clock delay in picoseconds. */
lan969x_rgmii_get_clk_delay_sel(struct sparx5_port * port,u32 delay_ps,u32 * clk_delay_sel)51 static int lan969x_rgmii_get_clk_delay_sel(struct sparx5_port *port,
52 u32 delay_ps, u32 *clk_delay_sel)
53 {
54 switch (delay_ps) {
55 case 0:
56 /* Hardware default selector. */
57 *clk_delay_sel = LAN969X_RGMII_CLK_DELAY_SEL_2_5_NS;
58 break;
59 case 1000:
60 *clk_delay_sel = LAN969X_RGMII_CLK_DELAY_SEL_1_0_NS;
61 break;
62 case 1700:
63 *clk_delay_sel = LAN969X_RGMII_CLK_DELAY_SEL_1_7_NS;
64 break;
65 case 2000:
66 *clk_delay_sel = LAN969X_RGMII_CLK_DELAY_SEL_2_0_NS;
67 break;
68 case 2500:
69 *clk_delay_sel = LAN969X_RGMII_CLK_DELAY_SEL_2_5_NS;
70 break;
71 case 3000:
72 *clk_delay_sel = LAN969X_RGMII_CLK_DELAY_SEL_3_0_NS;
73 break;
74 case 3300:
75 *clk_delay_sel = LAN969X_RGMII_CLK_DELAY_SEL_3_3_NS;
76 break;
77 default:
78 dev_err(port->sparx5->dev, "Invalid RGMII delay: %u", delay_ps);
79 return -EINVAL;
80 }
81
82 return 0;
83 }
84
85 /* Configure the RGMII tx clock frequency. */
lan969x_rgmii_tx_clk_config(struct sparx5_port * port,struct sparx5_port_config * conf)86 static void lan969x_rgmii_tx_clk_config(struct sparx5_port *port,
87 struct sparx5_port_config *conf)
88 {
89 u32 clk_sel = lan969x_rgmii_get_clk_sel(conf->speed);
90 u32 idx = RGMII_PORT_IDX(port);
91
92 /* Take the RGMII clock domain out of reset and set tx clock
93 * frequency.
94 */
95 spx5_rmw(HSIO_WRAP_RGMII_CFG_TX_CLK_CFG_SET(clk_sel) |
96 HSIO_WRAP_RGMII_CFG_RGMII_TX_RST_SET(0) |
97 HSIO_WRAP_RGMII_CFG_RGMII_RX_RST_SET(0),
98 HSIO_WRAP_RGMII_CFG_TX_CLK_CFG |
99 HSIO_WRAP_RGMII_CFG_RGMII_TX_RST |
100 HSIO_WRAP_RGMII_CFG_RGMII_RX_RST,
101 port->sparx5, HSIO_WRAP_RGMII_CFG(idx));
102 }
103
104 /* Configure the RGMII port device. */
lan969x_rgmii_port_device_config(struct sparx5_port * port,struct sparx5_port_config * conf)105 static void lan969x_rgmii_port_device_config(struct sparx5_port *port,
106 struct sparx5_port_config *conf)
107 {
108 u32 dtag, dotag, etype, speed_sel, idx = RGMII_PORT_IDX(port);
109
110 speed_sel = lan969x_rgmii_get_speed_sel(conf->speed);
111
112 etype = (port->vlan_type == SPX5_VLAN_PORT_TYPE_S_CUSTOM ?
113 port->custom_etype :
114 port->vlan_type == SPX5_VLAN_PORT_TYPE_C ?
115 ETH_P_8021Q : ETH_P_8021AD);
116
117 dtag = port->max_vlan_tags == SPX5_PORT_MAX_TAGS_TWO;
118 dotag = port->max_vlan_tags != SPX5_PORT_MAX_TAGS_NONE;
119
120 /* Enable the MAC. */
121 spx5_wr(DEVRGMII_MAC_ENA_CFG_RX_ENA_SET(1) |
122 DEVRGMII_MAC_ENA_CFG_TX_ENA_SET(1),
123 port->sparx5, DEVRGMII_MAC_ENA_CFG(idx));
124
125 /* Configure the Inter Frame Gap. */
126 spx5_wr(DEVRGMII_MAC_IFG_CFG_TX_IFG_SET(LAN969X_RGMII_IFG_TX) |
127 DEVRGMII_MAC_IFG_CFG_RX_IFG1_SET(LAN969X_RGMII_IFG_RX1) |
128 DEVRGMII_MAC_IFG_CFG_RX_IFG2_SET(LAN969X_RGMII_IFG_RX2),
129 port->sparx5, DEVRGMII_MAC_IFG_CFG(idx));
130
131 /* Configure port data rate. */
132 spx5_wr(DEVRGMII_DEV_RST_CTRL_SPEED_SEL_SET(speed_sel),
133 port->sparx5, DEVRGMII_DEV_RST_CTRL(idx));
134
135 /* Configure VLAN awareness. */
136 spx5_wr(DEVRGMII_MAC_TAGS_CFG_TAG_ID_SET(etype) |
137 DEVRGMII_MAC_TAGS_CFG_PB_ENA_SET(dtag) |
138 DEVRGMII_MAC_TAGS_CFG_VLAN_AWR_ENA_SET(dotag) |
139 DEVRGMII_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA_SET(dotag),
140 port->sparx5,
141 DEVRGMII_MAC_TAGS_CFG(idx));
142 }
143
144 /* Configure the RGMII delay lines in the MAC.
145 *
146 * We use the rx-internal-delay-ps" and "tx-internal-delay-ps" properties to
147 * configure the rx and tx delays for the MAC. If these properties are missing
148 * or set to zero, the MAC will not apply any delay.
149 *
150 * The PHY side delays are determined by the PHY mode
151 * (e.g. PHY_INTERFACE_MODE_RGMII_{ID, RXID, TXID}), and ignored by the MAC side
152 * entirely.
153 */
lan969x_rgmii_delay_config(struct sparx5_port * port,struct sparx5_port_config * conf)154 static int lan969x_rgmii_delay_config(struct sparx5_port *port,
155 struct sparx5_port_config *conf)
156 {
157 u32 tx_clk_sel, rx_clk_sel, tx_delay_ps = 0, rx_delay_ps = 0;
158 u32 idx = RGMII_PORT_IDX(port);
159 int err;
160
161 of_property_read_u32(port->of_node, "rx-internal-delay-ps",
162 &rx_delay_ps);
163
164 of_property_read_u32(port->of_node, "tx-internal-delay-ps",
165 &tx_delay_ps);
166
167 err = lan969x_rgmii_get_clk_delay_sel(port, rx_delay_ps, &rx_clk_sel);
168 if (err)
169 return err;
170
171 err = lan969x_rgmii_get_clk_delay_sel(port, tx_delay_ps, &tx_clk_sel);
172 if (err)
173 return err;
174
175 /* Configure rx delay. */
176 spx5_rmw(HSIO_WRAP_DLL_CFG_DLL_RST_SET(0) |
177 HSIO_WRAP_DLL_CFG_DLL_ENA_SET(1) |
178 HSIO_WRAP_DLL_CFG_DLL_CLK_ENA_SET(!!rx_delay_ps) |
179 HSIO_WRAP_DLL_CFG_DLL_CLK_SEL_SET(rx_clk_sel),
180 HSIO_WRAP_DLL_CFG_DLL_RST |
181 HSIO_WRAP_DLL_CFG_DLL_ENA |
182 HSIO_WRAP_DLL_CFG_DLL_CLK_ENA |
183 HSIO_WRAP_DLL_CFG_DLL_CLK_SEL,
184 port->sparx5, HSIO_WRAP_DLL_CFG(idx, 0));
185
186 /* Configure tx delay. */
187 spx5_rmw(HSIO_WRAP_DLL_CFG_DLL_RST_SET(0) |
188 HSIO_WRAP_DLL_CFG_DLL_ENA_SET(1) |
189 HSIO_WRAP_DLL_CFG_DLL_CLK_ENA_SET(!!tx_delay_ps) |
190 HSIO_WRAP_DLL_CFG_DLL_CLK_SEL_SET(tx_clk_sel),
191 HSIO_WRAP_DLL_CFG_DLL_RST |
192 HSIO_WRAP_DLL_CFG_DLL_ENA |
193 HSIO_WRAP_DLL_CFG_DLL_CLK_ENA |
194 HSIO_WRAP_DLL_CFG_DLL_CLK_SEL,
195 port->sparx5, HSIO_WRAP_DLL_CFG(idx, 1));
196
197 return 0;
198 }
199
200 /* Configure GPIO's to be used as RGMII interface. */
lan969x_rgmii_gpio_config(struct sparx5_port * port)201 static void lan969x_rgmii_gpio_config(struct sparx5_port *port)
202 {
203 u32 idx = RGMII_PORT_IDX(port);
204
205 /* Enable the RGMII on the GPIOs. */
206 spx5_wr(HSIO_WRAP_XMII_CFG_GPIO_XMII_CFG_SET(1), port->sparx5,
207 HSIO_WRAP_XMII_CFG(!idx));
208 }
209
lan969x_port_config_rgmii(struct sparx5_port * port,struct sparx5_port_config * conf)210 int lan969x_port_config_rgmii(struct sparx5_port *port,
211 struct sparx5_port_config *conf)
212 {
213 int err;
214
215 err = lan969x_rgmii_delay_config(port, conf);
216 if (err)
217 return err;
218
219 lan969x_rgmii_tx_clk_config(port, conf);
220 lan969x_rgmii_gpio_config(port);
221 lan969x_rgmii_port_device_config(port, conf);
222
223 return 0;
224 }
225