| /linux-6.14.4/Documentation/devicetree/bindings/clock/ |
| D | qcom,gcc-qcs404.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-qcs404.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller on QCS404
10 - Stephen Boyd <[email protected]>
11 - Taniya Das <[email protected]>
15 domains on QCS404.
17 See also:: include/dt-bindings/clock/qcom,gcc-qcs404.h
21 const: qcom,gcc-qcs404
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| D | qcom,qcs404-turingcc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,qcs404-turingcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Turing Clock & Reset Controller on QCS404
10 - Bjorn Andersson <[email protected]>
14 const: qcom,qcs404-turingcc
22 '#clock-cells':
25 '#reset-cells':
29 - compatible
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| D | qcom,q6sstopcc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <[email protected]>
14 const: qcom,qcs404-q6sstopcc
18 - description: Q6SSTOP clocks register region
19 - description: Q6SSTOP_TCSR register region
23 - description: ahb clock for the q6sstopCC
25 '#clock-cells':
29 - compatible
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| /linux-6.14.4/arch/arm64/boot/dts/qcom/ |
| D | qcs404.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-qcs404.h>
8 #include <dt-bindings/clock/qcom,turingcc-qcs404.h>
9 #include <dt-bindings/clock/qcom,rpmcc.h>
10 #include <dt-bindings/power/qcom-rpmpd.h>
11 #include <dt-bindings/thermal/thermal.h>
14 interrupt-parent = <&intc>;
16 #address-cells = <2>;
17 #size-cells = <2>;
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| D | qcs404-evb.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/gpio/gpio.h>
7 #include "qcs404.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
19 stdout-path = "serial0";
22 vph_pwr: vph-pwr-regulator {
23 compatible = "regulator-fixed";
24 regulator-name = "vph_pwr";
25 regulator-always-on;
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| D | msm8917.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
3 #include <dt-bindings/clock/qcom,gcc-msm8917.h>
4 #include <dt-bindings/clock/qcom,rpmcc.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/power/qcom-rpmpd.h>
7 #include <dt-bindings/thermal/thermal.h>
10 interrupt-parent = <&intc>;
12 #address-cells = <2>;
13 #size-cells = <2>;
18 sleep_clk: sleep-clk {
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| /linux-6.14.4/Documentation/devicetree/bindings/remoteproc/ |
| D | qcom,qcs404-cdsp-pil.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/qcom,qcs404-cdsp-pil.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm QCS404 CDSP Peripheral Image Loader
10 - Bjorn Andersson <[email protected]>
19 - qcom,qcs404-cdsp-pil
28 - description: Watchdog interrupt
29 - description: Fatal interrupt
30 - description: Ready interrupt
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| /linux-6.14.4/Documentation/devicetree/bindings/net/ |
| D | qcom,ethqos.yaml | 1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <[email protected]>
11 - Konrad Dybcio <[email protected]>
18 - $ref: snps,dwmac.yaml#
23 - items:
24 - enum:
25 - qcom,qcs615-ethqos
26 - const: qcom,qcs404-ethqos
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| /linux-6.14.4/Documentation/devicetree/bindings/phy/ |
| D | qcom,pcie2-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,pcie2-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vinod Koul <[email protected]>
19 - const: qcom,qcs404-pcie2-phy
20 - const: qcom,pcie2-phy
24 - description: PHY register set
28 - description: a clock-specifier pair for the "pipe" clock
30 clock-output-names:
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| D | qcom,usb-ss.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,usb-ss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bryan O'Donoghue <[email protected]>
18 - qcom,usb-ss-28nm-phy
23 "#phy-cells":
28 - description: rpmcc clock
29 - description: PHY AHB clock
30 - description: SuperSpeed pipe clock
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| D | qcom,usb-hs-28nm.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,usb-hs-28nm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Synopsys DesignWare Core 28nm High-Speed PHY
10 - Bryan O'Donoghue <[email protected]>
13 Qualcomm Low-Speed, Full-Speed, Hi-Speed 28nm USB PHY
18 - qcom,usb-hs-28nm-femtophy
23 "#phy-cells":
28 - description: rpmcc ref clock
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| /linux-6.14.4/Documentation/devicetree/bindings/mailbox/ |
| D | qcom,apcs-kpss-global.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/qcom,apcs-kpss-global.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - Jassi Brar <[email protected]>
19 - items:
20 - enum:
21 - qcom,ipq5018-apcs-apps-global
22 - qcom,ipq5332-apcs-apps-global
23 - qcom,ipq5424-apcs-apps-global
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| /linux-6.14.4/drivers/clk/qcom/ |
| D | Makefile | 1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_COMMON_CLK_QCOM) += clk-qcom.o
4 clk-qcom-y += common.o
5 clk-qcom-y += clk-regmap.o
6 clk-qcom-y += clk-alpha-pll.o
7 clk-qcom-y += clk-pll.o
8 clk-qcom-y += clk-rcg.o
9 clk-qcom-y += clk-rcg2.o
10 clk-qcom-y += clk-branch.o
11 clk-qcom-y += clk-regmap-divider.o
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| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
206 CMN PLL consumes the AHB/SYS clocks from GCC and supplies
207 the output clocks to the networking hardware and GCC blocks.
490 tristate "QCS404 Global Clock Controller"
492 Support for the global clock controller on QCS404 devices.
793 tristate "QCS404 Turing Clock Controller"
795 Support for the Turing Clock Controller on QCS404, provides clocks
799 tristate "QCS404 Q6SSTOP Clock Controller"
802 Support for the Q6SSTOP clock controller on QCS404 devices.
1287 Say Y if you want to toggle LPASS-adjacent resets within
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| D | gcc-qcs404.c | 1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/clk-provider.h>
12 #include <linux/reset-controller.h>
14 #include <dt-bindings/clock/qcom,gcc-qcs404.h>
16 #include "clk-alpha-pll.h"
17 #include "clk-branch.h"
18 #include "clk-pll.h"
19 #include "clk-rcg.h"
20 #include "clk-regmap.h"
53 { .index = DT_XO, .name = "xo-board" },
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| D | gcc-msm8917.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Based on gcc-msm8953.c:
7 * with parts taken from gcc-qcs404.c:
9 * and gcc-msm8939.c:
11 * adapted with data from clock-gcc-8952.c in Qualcomm's msm-4.9 release:
12 * Copyright (c) 2014-2020, The Linux Foundation. All rights reserved.
16 #include <linux/clk-provider.h>
23 #include <linux/reset-controller.h>
25 #include <dt-bindings/clock/qcom,gcc-msm8917.h>
27 #include "clk-alpha-pll.h"
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| /linux-6.14.4/Documentation/devicetree/bindings/pci/ |
| D | qcom,pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <[email protected]>
11 - Manivannan Sadhasivam <[email protected]>
20 - enum:
21 - qcom,pcie-apq8064
22 - qcom,pcie-apq8084
23 - qcom,pcie-ipq4019
24 - qcom,pcie-ipq6018
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| /linux-6.14.4/Documentation/devicetree/bindings/usb/ |
| D | qcom,dwc3.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Wesley Cheng <[email protected]>
15 - enum:
16 - qcom,ipq4019-dwc3
17 - qcom,ipq5018-dwc3
18 - qcom,ipq5332-dwc3
19 - qcom,ipq5424-dwc3
20 - qcom,ipq6018-dwc3
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| /linux-6.14.4/Documentation/devicetree/bindings/firmware/ |
| D | qcom,scm.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
16 - Bjorn Andersson <[email protected]>
17 - Robert Marko <[email protected]>
18 - Guru Das Srinagesh <[email protected]>
23 - enum:
24 - qcom,scm-apq8064
25 - qcom,scm-apq8084
26 - qcom,scm-ipq4019
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| /linux-6.14.4/Documentation/devicetree/bindings/nvmem/ |
| D | qcom,qfprom.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <[email protected]>
13 - $ref: nvmem.yaml#
14 - $ref: nvmem-deprecated-cells.yaml#
19 - enum:
20 - qcom,apq8064-qfprom
21 - qcom,apq8084-qfprom
22 - qcom,ipq5332-qfprom
[all …]
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| /linux-6.14.4/Documentation/devicetree/bindings/mmc/ |
| D | sdhci-msm.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/sdhci-msm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SDHCI controller (sdhci-msm)
10 - Bjorn Andersson <[email protected]>
11 - Konrad Dybcio <[email protected]>
20 - enum:
21 - qcom,sdhci-msm-v4
23 - items:
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| /linux-6.14.4/drivers/mailbox/ |
| D | qcom-apcs-ipc-mailbox.c | 1 // SPDX-License-Identifier: GPL-2.0-only
33 .offset = 8, .clk_name = "qcom,apss-ipq6018-clk"
37 .offset = 8, .clk_name = "qcom-apcs-msm8916-clk"
45 .offset = 16, .clk_name = "qcom-apcs-msm8996-clk"
53 .offset = 0x1008, .clk_name = "qcom-sdx55-acps-clk"
66 struct qcom_apcs_ipc *apcs = container_of(chan->mbox, in qcom_apcs_ipc_send_data()
68 unsigned long idx = (unsigned long)chan->con_priv; in qcom_apcs_ipc_send_data()
70 return regmap_write(apcs->regmap, apcs->offset, BIT(idx)); in qcom_apcs_ipc_send_data()
86 apcs = devm_kzalloc(&pdev->dev, sizeof(*apcs), GFP_KERNEL); in qcom_apcs_ipc_probe()
88 return -ENOMEM; in qcom_apcs_ipc_probe()
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| /linux-6.14.4/drivers/remoteproc/ |
| D | qcom_q6v5_wcss.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2018 Linaro Ltd.
5 * Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
162 val = readl(wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_reset()
164 writel(val, wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_reset()
167 val = readl(wcss->reg_base + Q6SS_XO_CBCR); in q6v5_wcss_reset()
169 writel(val, wcss->reg_base + Q6SS_XO_CBCR); in q6v5_wcss_reset()
172 ret = readl_poll_timeout(wcss->reg_base + Q6SS_XO_CBCR, in q6v5_wcss_reset()
176 dev_err(wcss->dev, in q6v5_wcss_reset()
181 val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_reset()
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