1# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/qcom,ethqos.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Ethernet ETHQOS device
8
9maintainers:
10  - Bjorn Andersson <[email protected]>
11  - Konrad Dybcio <[email protected]>
12
13description:
14  dwmmac based Qualcomm ethernet devices which support Gigabit
15  ethernet (version v2.3.0 and onwards).
16
17allOf:
18  - $ref: snps,dwmac.yaml#
19
20properties:
21  compatible:
22    oneOf:
23      - items:
24          - enum:
25              - qcom,qcs615-ethqos
26          - const: qcom,qcs404-ethqos
27      - items:
28          - enum:
29              - qcom,qcs8300-ethqos
30          - const: qcom,sa8775p-ethqos
31      - enum:
32          - qcom,qcs404-ethqos
33          - qcom,sa8775p-ethqos
34          - qcom,sc8280xp-ethqos
35          - qcom,sm8150-ethqos
36
37  reg:
38    maxItems: 2
39
40  reg-names:
41    items:
42      - const: stmmaceth
43      - const: rgmii
44
45  interrupts:
46    minItems: 1
47    items:
48      - description: Combined signal for various interrupt events
49      - description: The interrupt that occurs when Rx exits the LPI state
50      - description: The interrupt that occurs when HW safety error triggered
51
52  interrupt-names:
53    minItems: 1
54    items:
55      - const: macirq
56      - enum: [eth_lpi, sfty]
57      - const: sfty
58
59  clocks:
60    maxItems: 4
61
62  clock-names:
63    items:
64      - const: stmmaceth
65      - const: pclk
66      - const: ptp_ref
67      - enum:
68          - rgmii
69          - phyaux
70
71  iommus:
72    maxItems: 1
73
74  dma-coherent: true
75
76  phys: true
77
78  phy-names:
79    const: serdes
80
81required:
82  - compatible
83  - clocks
84  - clock-names
85  - reg-names
86
87unevaluatedProperties: false
88
89examples:
90  - |
91    #include <dt-bindings/interrupt-controller/arm-gic.h>
92    #include <dt-bindings/clock/qcom,gcc-qcs404.h>
93    #include <dt-bindings/gpio/gpio.h>
94
95    ethernet: ethernet@7a80000 {
96      compatible = "qcom,qcs404-ethqos";
97      reg = <0x07a80000 0x10000>,
98            <0x07a96000 0x100>;
99      reg-names = "stmmaceth", "rgmii";
100      clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii";
101      clocks = <&gcc GCC_ETH_AXI_CLK>,
102               <&gcc GCC_ETH_SLAVE_AHB_CLK>,
103               <&gcc GCC_ETH_PTP_CLK>,
104               <&gcc GCC_ETH_RGMII_CLK>;
105      interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
106                   <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
107                   <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>;
108      interrupt-names = "macirq", "eth_lpi", "sfty";
109
110      rx-fifo-depth = <4096>;
111      tx-fifo-depth = <4096>;
112
113      snps,tso;
114      snps,reset-gpio = <&tlmm 60 GPIO_ACTIVE_LOW>;
115      snps,reset-active-low;
116      snps,reset-delays-us = <0 10000 10000>;
117
118      pinctrl-names = "default";
119      pinctrl-0 = <&ethernet_defaults>;
120
121      phy-handle = <&phy1>;
122      phy-mode = "rgmii";
123      mdio {
124        #address-cells = <0x1>;
125        #size-cells = <0x0>;
126
127        compatible = "snps,dwmac-mdio";
128        phy1: phy@4 {
129          compatible = "ethernet-phy-ieee802.3-c22";
130          device_type = "ethernet-phy";
131          reg = <0x4>;
132
133          #phy-cells = <0>;
134        };
135      };
136    };
137