1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mmc/sdhci-msm.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SDHCI controller (sdhci-msm)
8
9maintainers:
10  - Bjorn Andersson <[email protected]>
11  - Konrad Dybcio <[email protected]>
12
13description:
14  Secure Digital Host Controller Interface (SDHCI) present on
15  Qualcomm SOCs supports SD/MMC/SDIO devices.
16
17properties:
18  compatible:
19    oneOf:
20      - enum:
21          - qcom,sdhci-msm-v4
22        deprecated: true
23      - items:
24          - enum:
25              - qcom,apq8084-sdhci
26              - qcom,ipq4019-sdhci
27              - qcom,ipq8074-sdhci
28              - qcom,msm8226-sdhci
29              - qcom,msm8953-sdhci
30              - qcom,msm8974-sdhci
31              - qcom,msm8976-sdhci
32              - qcom,msm8916-sdhci
33              - qcom,msm8992-sdhci
34              - qcom,msm8994-sdhci
35              - qcom,msm8996-sdhci
36              - qcom,msm8998-sdhci
37          - const: qcom,sdhci-msm-v4 # for sdcc versions less than 5.0
38      - items:
39          - enum:
40              - qcom,ipq5018-sdhci
41              - qcom,ipq5332-sdhci
42              - qcom,ipq5424-sdhci
43              - qcom,ipq6018-sdhci
44              - qcom,ipq9574-sdhci
45              - qcom,qcm2290-sdhci
46              - qcom,qcs404-sdhci
47              - qcom,qcs615-sdhci
48              - qcom,qdu1000-sdhci
49              - qcom,sar2130p-sdhci
50              - qcom,sc7180-sdhci
51              - qcom,sc7280-sdhci
52              - qcom,sc8280xp-sdhci
53              - qcom,sdm630-sdhci
54              - qcom,sdm670-sdhci
55              - qcom,sdm845-sdhci
56              - qcom,sdx55-sdhci
57              - qcom,sdx65-sdhci
58              - qcom,sdx75-sdhci
59              - qcom,sm6115-sdhci
60              - qcom,sm6125-sdhci
61              - qcom,sm6350-sdhci
62              - qcom,sm6375-sdhci
63              - qcom,sm8150-sdhci
64              - qcom,sm8250-sdhci
65              - qcom,sm8350-sdhci
66              - qcom,sm8450-sdhci
67              - qcom,sm8550-sdhci
68              - qcom,sm8650-sdhci
69              - qcom,x1e80100-sdhci
70          - const: qcom,sdhci-msm-v5 # for sdcc version 5.0
71
72  reg:
73    minItems: 1
74    maxItems: 4
75
76  reg-names:
77    minItems: 1
78    maxItems: 4
79
80  clocks:
81    minItems: 2
82    items:
83      - description: Main peripheral bus clock, PCLK/HCLK - AHB Bus clock
84      - description: SDC MMC clock, MCLK
85      - description: TCXO clock
86      - description: clock for Inline Crypto Engine
87      - description: SDCC bus voter clock
88      - description: reference clock for RCLK delay calibration
89      - description: sleep clock for RCLK delay calibration
90
91  clock-names:
92    minItems: 2
93    items:
94      - const: iface
95      - const: core
96      - const: xo
97      - enum: [ice, bus, cal, sleep]
98      - enum: [ice, bus, cal, sleep]
99      - enum: [ice, bus, cal, sleep]
100      - enum: [ice, bus, cal, sleep]
101
102  dma-coherent: true
103
104  interrupts:
105    maxItems: 2
106
107  interrupt-names:
108    items:
109      - const: hc_irq
110      - const: pwr_irq
111
112  pinctrl-names:
113    minItems: 1
114    items:
115      - const: default
116      - const: sleep
117
118  pinctrl-0:
119    description:
120      Should specify pin control groups used for this controller.
121
122  pinctrl-1:
123    description:
124      Should specify sleep pin control groups used for this controller.
125
126  resets:
127    maxItems: 1
128
129  qcom,ddr-config:
130    $ref: /schemas/types.yaml#/definitions/uint32
131    description: platform specific settings for DDR_CONFIG reg.
132
133  qcom,dll-config:
134    $ref: /schemas/types.yaml#/definitions/uint32
135    description: platform specific settings for DLL_CONFIG reg.
136
137  iommus:
138    minItems: 1
139    maxItems: 8
140    description: |
141      phandle to apps_smmu node with sid mask.
142
143  interconnects:
144    minItems: 1
145    items:
146      - description: data path, sdhc to ddr
147      - description: config path, cpu to sdhc
148
149  interconnect-names:
150    minItems: 1
151    items:
152      - const: sdhc-ddr
153      - const: cpu-sdhc
154
155  power-domains:
156    description: A phandle to sdhci power domain node
157    maxItems: 1
158
159  operating-points-v2: true
160
161patternProperties:
162  '^opp-table(-[a-z0-9]+)?$':
163    if:
164      properties:
165        compatible:
166          const: operating-points-v2
167    then:
168      patternProperties:
169        '^opp-?[0-9]+$':
170          required:
171            - required-opps
172
173required:
174  - compatible
175  - reg
176  - clocks
177  - clock-names
178  - interrupts
179
180allOf:
181  - $ref: sdhci-common.yaml#
182
183  - if:
184      properties:
185        compatible:
186          contains:
187            enum:
188              - qcom,sdhci-msm-v4
189    then:
190      properties:
191        reg:
192          minItems: 2
193          items:
194            - description: Host controller register map
195            - description: SD Core register map
196            - description: CQE register map
197            - description: Inline Crypto Engine register map
198        reg-names:
199          minItems: 2
200          items:
201            - const: hc
202            - const: core
203            - const: cqhci
204            - const: ice
205    else:
206      properties:
207        reg:
208          minItems: 1
209          items:
210            - description: Host controller register map
211            - description: CQE register map
212            - description: Inline Crypto Engine register map
213        reg-names:
214          minItems: 1
215          items:
216            - const: hc
217            - const: cqhci
218            - const: ice
219
220unevaluatedProperties: false
221
222examples:
223  - |
224    #include <dt-bindings/interrupt-controller/arm-gic.h>
225    #include <dt-bindings/clock/qcom,gcc-sm8250.h>
226    #include <dt-bindings/clock/qcom,rpmh.h>
227    #include <dt-bindings/power/qcom,rpmhpd.h>
228
229    sdhc_2: mmc@8804000 {
230      compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5";
231      reg = <0 0x08804000 0 0x1000>;
232
233      interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
234                   <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
235      interrupt-names = "hc_irq", "pwr_irq";
236
237      clocks = <&gcc GCC_SDCC2_AHB_CLK>,
238               <&gcc GCC_SDCC2_APPS_CLK>,
239               <&rpmhcc RPMH_CXO_CLK>;
240      clock-names = "iface", "core", "xo";
241      iommus = <&apps_smmu 0x4a0 0x0>;
242      qcom,dll-config = <0x0007642c>;
243      qcom,ddr-config = <0x80040868>;
244      power-domains = <&rpmhpd RPMHPD_CX>;
245
246      operating-points-v2 = <&sdhc2_opp_table>;
247
248      sdhc2_opp_table: opp-table {
249        compatible = "operating-points-v2";
250
251        opp-19200000 {
252          opp-hz = /bits/ 64 <19200000>;
253          required-opps = <&rpmhpd_opp_min_svs>;
254        };
255
256        opp-50000000 {
257          opp-hz = /bits/ 64 <50000000>;
258          required-opps = <&rpmhpd_opp_low_svs>;
259        };
260
261        opp-100000000 {
262          opp-hz = /bits/ 64 <100000000>;
263          required-opps = <&rpmhpd_opp_svs>;
264        };
265
266        opp-202000000 {
267          opp-hz = /bits/ 64 <202000000>;
268          required-opps = <&rpmhpd_opp_svs_l1>;
269        };
270      };
271    };
272