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/linux-6.14.4/arch/arm64/boot/dts/intel/
Dkeembay-soc.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 interrupt-parent = <&gic>;
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <1>;
17 #size-cells = <0>;
20 compatible = "arm,cortex-a53";
23 enable-method = "psci";
27 compatible = "arm,cortex-a53";
[all …]
/linux-6.14.4/include/linux/
Dclocksource.h1 /* SPDX-License-Identifier: GPL-2.0 */
36 * struct clocksource - hardware abstraction for a free running counter
37 * Provides mostly state-free accessors to the underlying hardware.
44 * @shift: Cycle to nanosecond divisor (power of two)
49 * @archdata: Optional arch-specific data
55 * @freq_khz: Clocksource frequency in khz.
60 * 1-99: Unfit for real use
62 * 100-199: Base level usability.
64 * 200-299: Good.
66 * 300-399: Desired.
[all …]
/linux-6.14.4/drivers/clk/tegra/
Dclk.h1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <linux/clk-provider.h>
73 * struct tegra_clk_sync_source - external clock source from codec
75 * @hw: handle between common and hardware-specific interfaces
76 * @rate: input frequency from source
95 * struct tegra_clk_frac_div - fractional divider clock
97 * @hw: handle between common and hardware-specific interfaces
99 * @flags: hardware-specific flags
100 * @shift: shift to the divider bit field
106 * TEGRA_DIVIDER_ROUND_UP - This flags indicates to round up the divider value.
[all …]
/linux-6.14.4/drivers/net/ethernet/intel/ixgbe/
Dixgbe_ptp.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
16 * clock frequency of the oscillator in combination with the TIMINCA
21 * of only a right shift (division by power of 2). The following math
30 * Period * [ 2 ^ ( MaxWidth - PeriodWidth ) ]
40 * The calculated value allows us to right shift the SYSTIME register
47 * +--------------+ +--------------+
49 * *--------------+ +--------------+
52 * +--------------+ +--------------+
54 * *--------------+ +--------------+
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/clock/ti/
Dapll.txt4 register-mapped APLL with usually two selectable input clocks
11 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
15 - compatible : shall be "ti,dra7-apll-clock" or "ti,omap2-apll-clock"
16 - #clock-cells : from common clock binding; shall be set to 0.
17 - clocks : link phandles of parent clocks (clk-ref and clk-bypass)
18 - reg : address and length of the register set for controlling the APLL.
20 "control" - contains the control register offset
21 "idlest" - contains the idlest register offset
22 "autoidle" - contains the autoidle register offset (OMAP2 only)
23 - ti,clock-frequency : static clock frequency for the clock (OMAP2 only)
[all …]
/linux-6.14.4/arch/arm64/boot/dts/rockchip/
Drk3528.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <2>;
15 #size-cells = <2>;
29 #address-cells = <1>;
30 #size-cells = <0>;
32 cpu-map {
50 compatible = "arm,cortex-a53";
[all …]
/linux-6.14.4/drivers/clk/bcm/
Dclk-iproc-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
13 #include "clk-iproc.h"
19 * PLL MACRO_SELECT modes 0 to 5 choose pre-calculated PLL output frequencies
20 * from a look-up table. Mode 7 allows user to manipulate PLL clock dividers
27 /* number of VCO frequency bands */
90 return -EINVAL; in pll_calc_param()
92 residual = target_rate - (ndiv_int * parent_rate); in pll_calc_param()
102 vco_out->ndiv_int = ndiv_int; in pll_calc_param()
103 vco_out->ndiv_frac = ndiv_frac; in pll_calc_param()
[all …]
Dclk-iproc.h1 /* SPDX-License-Identifier: GPL-2.0-only */
13 #include <linux/clk-provider.h>
17 #define bit_mask(width) ((1 << (width)) - 1)
62 * auto calculates VCO frequency parameters based on the provided leaf
79 * Parameters for VCO frequency configuration
81 * VCO frequency =
82 * ((ndiv_int + ndiv_frac / 2^20) * (ref frequency / pdiv)
93 unsigned int shift; member
140 * To enable SW control of the PLL
144 unsigned int shift; member
[all …]
/linux-6.14.4/arch/arm64/boot/dts/amazon/
Dalpine-v2.dtsi4 * Antoine Tenart <antoine.tenart@free-electrons.com>
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
35 /dts-v1/;
37 #include <dt-bindings/interrupt-controller/arm-gic.h>
41 compatible = "al,alpine-v2";
42 interrupt-parent = <&gic>;
43 #address-cells = <2>;
44 #size-cells = <2>;
47 #address-cells = <2>;
[all …]
Dalpine-v3.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 compatible = "amazon,al-alpine-v3";
14 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
20 #address-cells = <1>;
21 #size-cells = <0>;
25 compatible = "arm,cortex-a72";
[all …]
/linux-6.14.4/drivers/pwm/
Dpwm-brcmstb.c1 // SPDX-License-Identifier: GPL-2.0-or-later
41 * Maximum control word value allowed when variable-frequency PWM is used as a
42 * clock for the constant-frequency PMW.
63 return __raw_readl(p->base + offset); in brcmstb_pwm_readl()
65 return readl_relaxed(p->base + offset); in brcmstb_pwm_readl()
72 __raw_writel(value, p->base + offset); in brcmstb_pwm_writel()
74 writel_relaxed(value, p->base + offset); in brcmstb_pwm_writel()
83 * Fv is derived from the variable frequency output. The variable frequency
86 * W = cword, if cword < 2 ^ 15 else 16-bit 2's complement of cword
88 * Fv = W x 2 ^ -16 x 27Mhz (reference clock)
[all …]
/linux-6.14.4/drivers/clk/sunxi-ng/
Dccu_mux.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
8 #include <linux/clk-provider.h>
24 if (!((common->features & CCU_FEATURE_FIXED_PREDIV) || in ccu_mux_get_prediv()
25 (common->features & CCU_FEATURE_VARIABLE_PREDIV) || in ccu_mux_get_prediv()
26 (common->features & CCU_FEATURE_ALL_PREDIV))) in ccu_mux_get_prediv()
29 if (common->features & CCU_FEATURE_ALL_PREDIV) in ccu_mux_get_prediv()
30 return common->prediv; in ccu_mux_get_prediv()
32 reg = readl(common->base + common->reg); in ccu_mux_get_prediv()
34 parent_index = reg >> cm->shift; in ccu_mux_get_prediv()
[all …]
/linux-6.14.4/include/uapi/linux/
Dtimex.h28 * Added defines for hybrid phase/frequency-lock loop.
32 * defines for PPS phase-lock loop.
46 * 1995-08-13 Torsten Duwe
47 * kernel PLL updated to 1994-12-13 specs (rfc-1589)
48 * 1997-08-30 Ulrich Windl
50 * 2004-08-12 Christoph Lameter
62 * syscall interface - used (mainly by NTP daemon)
68 __kernel_long_t freq; /* frequency offset (scaled ppm) */
74 __kernel_long_t tolerance;/* clock frequency tolerance (ppm)
80 __kernel_long_t ppsfreq;/* pps frequency (scaled ppm) (ro) */
[all …]
/linux-6.14.4/arch/arm64/boot/dts/realtek/
Drtd16xx.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <1>;
15 #size-cells = <1>;
17 reserved-memory {
18 #address-cells = <1>;
19 #size-cells = <1>;
32 no-map;
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/regulator/
Dmaxim,max8973.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <[email protected]>
13 - $ref: regulator.yaml#
18 - maxim,max8973
19 - maxim,max77621
21 junction-warn-millicelsius:
30 maxim,dvs-gpio:
35 maxim,dvs-default-state:
[all …]
/linux-6.14.4/drivers/clk/sunxi/
Dclk-sunxi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/clk-provider.h>
14 #include <linux/reset-controller.h>
19 #include "clk-factors.h"
27 * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1
38 div = req->rate / 6000000; in sun4i_get_pll1_factors()
39 req->rate = 6000000 * div; in sun4i_get_pll1_factors()
42 req->m = 0; in sun4i_get_pll1_factors()
45 if (req->rate >= 768000000 || req->rate == 42000000 || in sun4i_get_pll1_factors()
46 req->rate == 54000000) in sun4i_get_pll1_factors()
[all …]
/linux-6.14.4/drivers/net/ethernet/mellanox/mlx4/
Den_clock.c14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
39 /* mlx4_en_read_clock - read raw cycle counter (to be used by time counter)
45 struct mlx4_dev *dev = mdev->dev; in mlx4_en_read_clock()
47 return mlx4_read_clock(dev) & tc->mask; in mlx4_en_read_clock()
55 lo = (u64)be16_to_cpu(ts_cqe->timestamp_lo); in mlx4_en_get_cqe_ts()
56 hi = ((u64)be32_to_cpu(ts_cqe->timestamp_hi) + !lo) << 16; in mlx4_en_get_cqe_ts()
67 seq = read_seqbegin(&mdev->clock_lock); in mlx4_en_get_hwtstamp()
68 nsec = timecounter_cyc2time(&mdev->clock, timestamp); in mlx4_en_get_hwtstamp()
69 } while (read_seqretry(&mdev->clock_lock, seq)); in mlx4_en_get_hwtstamp()
[all …]
/linux-6.14.4/drivers/clk/actions/
Dowl-pll.c1 // SPDX-License-Identifier: GPL-2.0+
6 // Author: David Liu <liuwei@actions-semi.com>
11 #include <linux/clk-provider.h>
16 #include "owl-pll.h"
22 mul = DIV_ROUND_CLOSEST(rate, pll_hw->bfreq); in owl_pll_calculate_mul()
23 if (mul < pll_hw->min_mul) in owl_pll_calculate_mul()
24 mul = pll_hw->min_mul; in owl_pll_calculate_mul()
25 else if (mul > pll_hw->max_mul) in owl_pll_calculate_mul()
26 mul = pll_hw->max_mul; in owl_pll_calculate_mul()
36 for (clkt = table; clkt->rate; clkt++) in _get_table_rate()
[all …]
/linux-6.14.4/arch/powerpc/kernel/
Dtime.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 * Converted for 64-bit by Mike Corrigan ([email protected])
11 * to make clock more stable (2.4.0-test5). The only thing
20 * - improve precision and reproducibility of timebase frequency
22 * - for astronomical applications: add a new function to get
26 * 1997-09-10 Updated NTP code according to technical memorandum Jan '96
50 #include <linux/posix-timers.h>
179 deltascaled = nowscaled - acct->startspurr; in vtime_delta_scaled()
180 acct->startspurr = nowscaled; in vtime_delta_scaled()
181 utime = acct->utime - acct->utime_sspurr; in vtime_delta_scaled()
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/gpio/
Dfairchild,74hc595.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic 8-bit shift register
11 have a rising-edge triggered latch clock (or storage register clock) pin,
12 which behaves like an active-low chip select.
14 After the bits are shifted into the shift register, CS# is driven high, which
16 transfer of the bits from the shift register to the storage register and thus
19 shift clock ____| |_| |_..._| |_| |_________
27 - Maxime Ripard <[email protected]>
[all …]
/linux-6.14.4/drivers/net/ethernet/microchip/sparx5/lan969x/
Dlan969x_rgmii.c1 // SPDX-License-Identifier: GPL-2.0+
20 #define LAN969X_RGMII_CLK_DELAY_SEL_1_0_NS 2 /* Phase shift 45deg */
21 #define LAN969X_RGMII_CLK_DELAY_SEL_1_7_NS 3 /* Phase shift 77deg */
22 #define LAN969X_RGMII_CLK_DELAY_SEL_2_0_NS 4 /* Phase shift 90deg */
23 #define LAN969X_RGMII_CLK_DELAY_SEL_2_5_NS 5 /* Phase shift 112deg */
24 #define LAN969X_RGMII_CLK_DELAY_SEL_3_0_NS 6 /* Phase shift 135deg */
25 #define LAN969X_RGMII_CLK_DELAY_SEL_3_3_NS 7 /* Phase shift 147deg */
32 #define RGMII_PORT_IDX(port) ((port)->portno - LAN969X_RGMII_PORT_START_IDX)
78 dev_err(port->sparx5->dev, "Invalid RGMII delay: %u", delay_ps); in lan969x_rgmii_get_clk_delay_sel()
79 return -EINVAL; in lan969x_rgmii_get_clk_delay_sel()
[all …]
/linux-6.14.4/arch/microblaze/kernel/
Dtimer.c2 * Copyright (C) 2007-2013 Michal Simek <[email protected]>
3 * Copyright (C) 2012-2013 Xilinx, Inc.
4 * Copyright (C) 2007-2009 PetaLogix
88 * !ENALL - don't enable 'em all in xilinx_timer0_start_periodic()
89 * !PWMA - disable pwm in xilinx_timer0_start_periodic()
90 * TINT - clear interrupt status in xilinx_timer0_start_periodic()
91 * ENT- enable timer itself in xilinx_timer0_start_periodic()
92 * ENIT - enable interrupt in xilinx_timer0_start_periodic()
93 * !LOAD - clear the bit to let go in xilinx_timer0_start_periodic()
94 * ARHT - auto reload in xilinx_timer0_start_periodic()
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/serial/
D8250.yaml3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - [email protected]
13 - $ref: serial.yaml#
14 - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml#
15 - if:
17 - required:
18 - aspeed,lpc-io-reg
19 - required:
20 - aspeed,lpc-interrupts
[all …]
/linux-6.14.4/drivers/clk/ti/
Dclk-3xxx.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Tero Kristo (t-[email protected])
12 #include <linux/clk-provider.h>
24 * In AM35xx IPSS, the {ICK,FCK} enable bits for modules are exported
26 * at an offset of 4 from ICK enable bit.
36 * omap3430es2_clk_ssi_find_idlest - return CM_IDLEST info for SSI
39 * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
42 * The OMAP3430ES2 SSI target CM_IDLEST bit is at a different shift
51 memcpy(idlest_reg, &clk->enable_reg, sizeof(*idlest_reg)); in omap3430es2_clk_ssi_find_idlest()
52 idlest_reg->offset &= ~0xf0; in omap3430es2_clk_ssi_find_idlest()
[all …]
/linux-6.14.4/arch/arm64/boot/dts/marvell/
Dac5-98dx25xx.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
20 #address-cells = <2>;
21 #size-cells = <0>;
23 cpu-map {
36 compatible = "arm,cortex-a55";
[all …]

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