1# Copyright 2020 Lubomir Rintel <[email protected]>
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/serial/8250.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: UART (Universal Asynchronous Receiver/Transmitter)
8
9maintainers:
10  - [email protected]
11
12allOf:
13  - $ref: serial.yaml#
14  - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml#
15  - if:
16      anyOf:
17        - required:
18            - aspeed,lpc-io-reg
19        - required:
20            - aspeed,lpc-interrupts
21        - required:
22            - aspeed,sirq-polarity-sense
23    then:
24      properties:
25        compatible:
26          const: aspeed,ast2500-vuart
27  - if:
28      properties:
29        compatible:
30          const: mrvl,mmp-uart
31    then:
32      properties:
33        reg-shift:
34          const: 2
35      required:
36        - reg-shift
37  - if:
38      not:
39        properties:
40          compatible:
41            items:
42              - enum:
43                  - ns8250
44                  - ns16450
45                  - ns16550
46                  - ns16550a
47    then:
48      anyOf:
49        - required: [ clock-frequency ]
50        - required: [ clocks ]
51
52properties:
53  compatible:
54    oneOf:
55      - const: ns8250
56      - const: ns16450
57      - const: ns16550
58      - const: ns16550a
59      - const: ns16850
60      - const: aspeed,ast2400-vuart
61      - const: aspeed,ast2500-vuart
62      - const: intel,xscale-uart
63      - const: mrvl,pxa-uart
64      - const: nuvoton,wpcm450-uart
65      - const: nuvoton,npcm750-uart
66      - const: nvidia,tegra20-uart
67      - const: nxp,lpc3220-uart
68      - items:
69          - enum:
70              - exar,xr16l2552
71              - exar,xr16l2551
72              - exar,xr16l2550
73          - const: ns8250
74      - items:
75          - enum:
76              - altr,16550-FIFO32
77              - altr,16550-FIFO64
78              - altr,16550-FIFO128
79              - fsl,16550-FIFO64
80              - fsl,ns16550
81              - andestech,uart16550
82              - nxp,lpc1850-uart
83              - opencores,uart16550-rtlsvn105
84              - ti,da830-uart
85          - const: ns16550a
86      - items:
87          - enum:
88              - ns16750
89              - cavium,octeon-3860-uart
90              - xlnx,xps-uart16550-2.00.b
91              - ralink,rt2880-uart
92          - enum:
93              - ns16550 # Deprecated, unless the FIFO really is broken
94              - ns16550a
95      - items:
96          - enum:
97              - nuvoton,npcm845-uart
98          - const: nuvoton,npcm750-uart
99      - items:
100          - enum:
101              - ralink,mt7620a-uart
102              - ralink,rt3052-uart
103              - ralink,rt3883-uart
104          - const: ralink,rt2880-uart
105          - enum:
106              - ns16550 # Deprecated, unless the FIFO really is broken
107              - ns16550a
108      - items:
109          - enum:
110              - mediatek,mt7622-btif
111              - mediatek,mt7623-btif
112          - const: mediatek,mtk-btif
113      - items:
114          - enum:
115              - mrvl,mmp-uart
116              - spacemit,k1-uart
117          - const: intel,xscale-uart
118      - items:
119          - enum:
120              - nvidia,tegra30-uart
121              - nvidia,tegra114-uart
122              - nvidia,tegra124-uart
123              - nvidia,tegra210-uart
124              - nvidia,tegra186-uart
125              - nvidia,tegra194-uart
126              - nvidia,tegra234-uart
127          - const: nvidia,tegra20-uart
128
129  reg:
130    maxItems: 1
131
132  interrupts:
133    maxItems: 1
134
135  clock-frequency: true
136
137  clocks:
138    maxItems: 1
139
140  resets:
141    maxItems: 1
142
143  current-speed:
144    $ref: /schemas/types.yaml#/definitions/uint32
145    description: The current active speed of the UART.
146
147  reg-offset:
148    $ref: /schemas/types.yaml#/definitions/uint32
149    description: |
150      Offset to apply to the mapbase from the start of the registers.
151
152  reg-shift:
153    description: Quantity to shift the register offsets by.
154
155  reg-io-width:
156    description: |
157      The size (in bytes) of the IO accesses that should be performed on the
158      device. There are some systems that require 32-bit accesses to the
159      UART (e.g. TI davinci).
160
161  used-by-rtas:
162    type: boolean
163    description: |
164      Set to indicate that the port is in use by the OpenFirmware RTAS and
165      should not be registered.
166
167  no-loopback-test:
168    type: boolean
169    description: |
170      Set to indicate that the port does not implement loopback test mode.
171
172  fifo-size:
173    $ref: /schemas/types.yaml#/definitions/uint32
174    description: The fifo size of the UART.
175
176  auto-flow-control:
177    type: boolean
178    description: |
179      One way to enable automatic flow control support. The driver is
180      allowed to detect support for the capability even without this
181      property.
182
183  tx-threshold:
184    description: |
185      Specify the TX FIFO low water indication for parts with programmable
186      TX FIFO thresholds.
187
188  overrun-throttle-ms:
189    description: |
190      How long to pause uart rx when input overrun is encountered.
191
192  rts-gpios: true
193  cts-gpios: true
194  dtr-gpios: true
195  dsr-gpios: true
196  rng-gpios: true
197  dcd-gpios: true
198
199  aspeed,sirq-polarity-sense:
200    $ref: /schemas/types.yaml#/definitions/phandle-array
201    description: |
202      Phandle to aspeed,ast2500-scu compatible syscon alongside register
203      offset and bit number to identify how the SIRQ polarity should be
204      configured. One possible data source is the LPC/eSPI mode bit. Only
205      applicable to aspeed,ast2500-vuart.
206    deprecated: true
207
208  aspeed,lpc-io-reg:
209    $ref: /schemas/types.yaml#/definitions/uint32-array
210    maxItems: 1
211    description: |
212      The VUART LPC address.  Only applicable to aspeed,ast2500-vuart.
213
214  aspeed,lpc-interrupts:
215    $ref: /schemas/types.yaml#/definitions/uint32-array
216    minItems: 2
217    maxItems: 2
218    description: |
219      A 2-cell property describing the VUART SIRQ number and SIRQ
220      polarity (IRQ_TYPE_LEVEL_LOW or IRQ_TYPE_LEVEL_HIGH).  Only
221      applicable to aspeed,ast2500-vuart.
222
223required:
224  - reg
225  - interrupts
226
227unevaluatedProperties: false
228
229examples:
230  - |
231    serial@80230000 {
232        compatible = "ns8250";
233        reg = <0x80230000 0x100>;
234        interrupts = <10>;
235        reg-shift = <2>;
236        clock-frequency = <48000000>;
237    };
238  - |
239    #include <dt-bindings/gpio/gpio.h>
240    serial@49042000 {
241        compatible = "andestech,uart16550", "ns16550a";
242        reg = <0x49042000 0x400>;
243        interrupts = <80>;
244        clock-frequency = <48000000>;
245        cts-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>;
246        rts-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
247        dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
248        dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
249        dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
250        rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
251    };
252  - |
253    #include <dt-bindings/clock/aspeed-clock.h>
254    #include <dt-bindings/interrupt-controller/irq.h>
255    serial@1e787000 {
256        compatible = "aspeed,ast2500-vuart";
257        reg = <0x1e787000 0x40>;
258        reg-shift = <2>;
259        interrupts = <8>;
260        clocks = <&syscon ASPEED_CLK_APB>;
261        no-loopback-test;
262        aspeed,lpc-io-reg = <0x3f8>;
263        aspeed,lpc-interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
264    };
265
266...
267