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/linux-6.14.4/Documentation/devicetree/bindings/dma/
Dfsl-qdma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/fsl-qdma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <[email protected]>
15 - const: fsl,ls1021a-qdma
16 - items:
17 - enum:
18 - fsl,ls1028a-qdma
19 - fsl,ls1043a-qdma
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/soc/ti/
Dkeystone-navigator-qmss.txt5 multi-core Navigator. QMSS consist of queue managers, packed-data structure
7 Packet DMA.
9 management of the packet queues. Packets are queued/de-queued by writing or
20 - compatible : Must be "ti,keystone-navigator-qmss".
21 : Must be "ti,66ak2g-navss-qm" for QMSS on K2G SoC.
22 - clocks : phandle to the reference clock for this device.
23 - queue-range : <start number> total range of queue numbers for the device.
24 - linkram0 : <address size> for internal link ram, where size is the total
26 - linkram1 : <address size> for external link ram, where size is the total
29 - qmgrs : child node describing the individual queue managers on the
[all …]
/linux-6.14.4/Documentation/misc-devices/
Dmrvl_cn10k_dpi.rst1 .. SPDX-License-Identifier: GPL-2.0
4 Marvell CN10K DMA packet interface (DPI) driver
10 DPI is a DMA packet interface hardware block in Marvell's CN10K silicon.
12 mailbox logic, and a set of DMA engines & DMA command queues.
15 requests from its VF functions and provisions DMA engine resources to
20 the DMA engines and VF device's DMA command queues. Also, driver creates
21 /dev/mrvl-cn10k-dpi node to set DMA engine and PEM (PCIe interface) port
25 queues and provisions the hardware resources, it cannot initiate any
26 DMA operations. Only VF devices are provisioned with DMA capabilities.
38 a pem port to which DMA engines are wired.
[all …]
/linux-6.14.4/drivers/net/ethernet/intel/idpf/
Didpf_controlq_setup.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * idpf_ctlq_alloc_desc_ring - Allocate Control Queue (CQ) rings
14 size_t size = cq->ring_size * sizeof(struct idpf_ctlq_desc); in idpf_ctlq_alloc_desc_ring()
16 cq->desc_ring.va = idpf_alloc_dma_mem(hw, &cq->desc_ring, size); in idpf_ctlq_alloc_desc_ring()
17 if (!cq->desc_ring.va) in idpf_ctlq_alloc_desc_ring()
18 return -ENOMEM; in idpf_ctlq_alloc_desc_ring()
24 * idpf_ctlq_alloc_bufs - Allocate Control Queue (CQ) buffers
28 * Allocate the buffer head for all control queues, and if it's a receive
29 * queue, allocate DMA buffers
36 /* Do not allocate DMA buffers for transmit queues */ in idpf_ctlq_alloc_bufs()
[all …]
Didpf_txrx.h1 /* SPDX-License-Identifier: GPL-2.0-only */
67 * queues. E.g.: If you have two buffer queues of 512 descriptors and buffers,
70 * number of buffer queues to calculate how many descriptors each buffer queue
83 #define IDPF_RX_BUFQ_WORKING_SET(rxq) ((rxq)->desc_count - 1)
87 if (unlikely(++(ntc) == (rxq)->desc_count)) { \
95 if (unlikely(++(idx) == (q)->desc_count)) \
117 ((((txq)->next_to_clean > (txq)->next_to_use) ? 0 : (txq)->desc_count) + \
118 (txq)->next_to_clean - (txq)->next_to_use - 1)
120 #define IDPF_TX_BUF_RSV_UNUSED(txq) ((txq)->stash->buf_stack.top)
122 (txq)->desc_count >> 2)
[all …]
Didpf_controlq.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * idpf_ctlq_setup_regs - initialize control queue registers
15 cq->reg.head = q_create_info->reg.head; in idpf_ctlq_setup_regs()
16 cq->reg.tail = q_create_info->reg.tail; in idpf_ctlq_setup_regs()
17 cq->reg.len = q_create_info->reg.len; in idpf_ctlq_setup_regs()
18 cq->reg.bah = q_create_info->reg.bah; in idpf_ctlq_setup_regs()
19 cq->reg.bal = q_create_info->reg.bal; in idpf_ctlq_setup_regs()
20 cq->reg.len_mask = q_create_info->reg.len_mask; in idpf_ctlq_setup_regs()
21 cq->reg.len_ena_mask = q_create_info->reg.len_ena_mask; in idpf_ctlq_setup_regs()
22 cq->reg.head_mask = q_create_info->reg.head_mask; in idpf_ctlq_setup_regs()
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/linux-6.14.4/drivers/crypto/cavium/nitrox/
Dnitrox_dev.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 #include <linux/dma-mapping.h>
11 /* Maximum queues in PF mode */
13 /* Maximum device queues */
19 * struct nitrox_cmdq - NITROX command queue
29 * @dma: dma address of the base
37 * @unalign_dma: unaligned dma address
51 dma_addr_t dma; member
68 * struct nitrox_hw - NITROX hardware information
69 * @partname: partname ex: CNN55xxx-xxx
[all …]
/linux-6.14.4/drivers/net/ethernet/sfc/siena/
Dvfdi.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2010-2012 Solarflare Communications Inc.
17 * alignment of 4K. All addresses are DMA addresses to be used within
20 * The only hardware-defined channels for a VF driver to communicate
28 * The PF driver can send arbitrary events to arbitrary event queues.
51 * The address must be page-aligned. After receiving such a valid
54 * sequence of events or a DMA error, there will be no response.
70 * reinitialisation of its queues.
91 * enum vfdi_op - VFDI operation enumeration
96 * @VFDI_OP_FINI_ALL_QUEUES: Flush all queues, finalize all queues, then
[all …]
Dnet_driver.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2005-2006 Fen Systems Ltd.
5 * Copyright 2005-2013 Solarflare Communications Inc.
61 /* Checksum generation is a per-queue option in hardware, so each
63 * queues. */
68 #define EFX_TXQ_TYPE_HIGHPRI 4 /* High-priority (for TC) */
70 /* HIGHPRI is Siena-only, and INNER_CSUM is EF10, so no need for both */
86 #define EFX_RX_USR_BUF_SIZE (2048 - 256)
89 * of every buffer. Otherwise, we just need to ensure 4-byte
98 /* Non-standard XDP_PACKET_HEADROOM and tailroom to satisfy XDP_REDIRECT and
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/net/
Dsnps,dwmac.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandre Torgue <[email protected]>
11 - Giuseppe Cavallaro <[email protected]>
12 - Jose Abreu <[email protected]>
23 - snps,dwmac
24 - snps,dwmac-3.40a
25 - snps,dwmac-3.50a
26 - snps,dwmac-3.610
[all …]
Dintel,dwmac-plat.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/intel,dwmac-plat.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vineetha G. Jaya Kumaran <[email protected]>
17 - intel,keembay-dwmac
19 - compatible
22 - $ref: snps,dwmac.yaml#
27 - items:
28 - enum:
[all …]
/linux-6.14.4/drivers/net/ethernet/cavium/liquidio/
Dcn66xx_regs.h7 * Copyright (c) 2003-2016 Cavium, Inc.
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
89 /* 1 register (32-bit) to enable Input queues */
92 /* 1 register (32-bit) to enable Output queues */
95 /* 1 register (32-bit) to determine whether Output queues are in reset. */
98 /* 1 register (32-bit) to determine whether Input queues are in reset. */
103 /* 1 register (32-bit) - instr. size of each input queue. */
106 /* 32 registers for Input Queue Instr Count - SLI_PKT_IN_DONE0_CNTS */
109 /* 32 registers for Input Queue Start Addr - SLI_PKT0_INSTR_BADDR */
112 /* 32 registers for Input Doorbell - SLI_PKT0_INSTR_BAOFF_DBELL */
[all …]
/linux-6.14.4/drivers/net/ethernet/netronome/nfp/
Dnfp_net_debugfs.c1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 /* Copyright (C) 2015-2019 Netronome Systems, Inc. */
14 struct nfp_net_r_vector *r_vec = file->private; in nfp_rx_q_show()
24 if (!r_vec->nfp_net || !r_vec->rx_ring) in nfp_rx_q_show()
26 nn = r_vec->nfp_net; in nfp_rx_q_show()
27 rx_ring = r_vec->rx_ring; in nfp_rx_q_show()
31 rxd_cnt = rx_ring->cnt; in nfp_rx_q_show()
33 fl_rd_p = nfp_qcp_rd_ptr_read(rx_ring->qcp_fl); in nfp_rx_q_show()
34 fl_wr_p = nfp_qcp_wr_ptr_read(rx_ring->qcp_fl); in nfp_rx_q_show()
36 seq_printf(file, "RX[%02d,%02d]: cnt=%u dma=%pad host=%p H_RD=%u H_WR=%u FL_RD=%u FL_WR=%u\n", in nfp_rx_q_show()
[all …]
/linux-6.14.4/drivers/dma/fsl-dpaa2-qdma/
Ddpdmai.h1 /* SPDX-License-Identifier: GPL-2.0 */
15 * Maximum number of Tx/Rx queues per DPDMAI object
42 ((u64)((_width) < 64 ? ((u64)1 << (_width)) - 1 : (u64)-1))
44 /* Data Path DMA Interface API
66 * struct dpdmai_cfg - Structure representing DPDMAI configuration
67 * @num_queues: Number of the DMA queues
68 * @priorities: Priorities for the DMA hardware processing; valid priorities are
69 * configured with values 1-8; the entry following last valid entry
78 * struct dpdmai_attr - Structure representing DPDMAI attributes
84 * @num_of_queues: number of the DMA queues
[all …]
/linux-6.14.4/arch/arm64/boot/dts/qcom/
Dsa8540p-ride.dts1 // SPDX-License-Identifier: BSD-3-Clause
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
13 #include "sa8540p-pmics.dtsi"
17 compatible = "qcom,sa8540p-ride", "qcom,sa8540p";
29 stdout-path = "serial0:115200n8";
34 regulators-0 {
35 compatible = "qcom,pm8150-rpmh-regulators";
36 qcom,pmic-id = "a";
[all …]
/linux-6.14.4/drivers/crypto/ccp/
Dccp-dev-v5.c1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/dma-mapping.h>
17 #include "ccp-dev.h"
31 if (cmd_q->lsb >= 0) { in ccp_lsb_alloc()
32 start = (u32)bitmap_find_next_zero_area(cmd_q->lsbmap, in ccp_lsb_alloc()
36 bitmap_set(cmd_q->lsbmap, start, count); in ccp_lsb_alloc()
37 return start + cmd_q->lsb * LSB_SIZE; in ccp_lsb_alloc()
42 ccp = cmd_q->ccp; in ccp_lsb_alloc()
44 mutex_lock(&ccp->sb_mutex); in ccp_lsb_alloc()
46 start = (u32)bitmap_find_next_zero_area(ccp->lsbmap, in ccp_lsb_alloc()
[all …]
/linux-6.14.4/drivers/net/ethernet/sfc/falcon/
Dnet_driver.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2005-2006 Fen Systems Ltd.
5 * Copyright 2005-2013 Solarflare Communications Inc.
63 /* Checksum generation is a per-queue option in hardware, so each
65 * queues. */
82 #define EF4_RX_USR_BUF_SIZE (2048 - 256)
85 * of every buffer. Otherwise, we just need to ensure 4-byte
97 * struct ef4_buffer - A general-purpose DMA buffer
99 * @dma_addr: DMA base address of the buffer
112 * struct ef4_special_buffer - DMA buffer entered into buffer table
[all …]
/linux-6.14.4/Documentation/driver-api/media/drivers/
Dipu6.rst1 .. SPDX-License-Identifier: GPL-2.0
34 ------------------------
51 ---------
61 -------------------------------------
76 -----------------
80 Buttress with a copy of the SoC time, this counter maintains the up-to-date time
86 DMA and MMU
90 32-bit virtual address space. The IPU6 has MMU address translation hardware to
94 IPU6 driver. The IPU6 driver sets the level-1 page table base address to MMU
97 The IPU6 driver exports its own DMA operations. The IPU6 driver will update the
[all …]
/linux-6.14.4/drivers/net/ethernet/sfc/
Dnet_driver.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2005-2006 Fen Systems Ltd.
5 * Copyright 2005-2013 Solarflare Communications Inc.
63 /* Checksum generation is a per-queue option in hardware, so each
65 * queues. */
86 #define EFX_RX_USR_BUF_SIZE (2048 - 256)
89 * of every buffer. Otherwise, we just need to ensure 4-byte
98 /* Non-standard XDP_PACKET_HEADROOM and tailroom to satisfy XDP_REDIRECT and
111 * struct efx_buffer - A general-purpose DMA buffer
113 * @dma_addr: DMA base address of the buffer
[all …]
/linux-6.14.4/Documentation/nvme/
Dnvme-pci-endpoint-target.rst1 .. SPDX-License-Identifier: GPL-2.0
27 host. However, using the PCI endpoint framework API and DMA API, the driver is
32 1) The driver manages retrieval of NVMe commands in submission queues using DMA
36 constantly poll the doorbell of all submission queues to detect command
39 2) The driver transfers completion queues entries of completed commands to the
49 PCI address segments using DMA, if supported. If DMA is not supported, MMIO
57 -----------------------
64 CQR bit to request "Contiguous Queues Required". This is to facilitate the
78 ------------------
84 The maximum number of queues and the maximum data transfer size (MDTS) are
[all …]
/linux-6.14.4/drivers/net/wireless/intel/iwlegacy/
Dprph.h8 * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
33 * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
106 * processor is sleeping (e.g. for periodic power-saving shutdowns of radio).
113 * This bootstrap program loads (via PCI busmaster DMA) instructions and data
119 * The uCode used for open-source drivers includes two programs:
121 * 1) Initialization -- performs hardware calibration and sets up some
128 * 2) Runtime/Protocol -- performs all normal runtime operations. This
170 * Data caching during power-downs:
173 * power-saving modes, or for RFKILL), uCode stores (via PCI busmaster DMA)
[all …]
/linux-6.14.4/drivers/atm/
Dfore200e.h1 /* SPDX-License-Identifier: GPL-2.0 */
52 #define RSD_REQUIRED (((MAX_PDU_SIZE - SMALL_BUFFER_SIZE + LARGE_BUFFER_SIZE) / LARGE_BUFFER_SIZE)…
56 /* RSD_REQUIRED receive segment descriptors are enough to describe a max-sized PDU,
61 #define RSD_EXTENSION ((RSD_REQUIRED - RSD_FIXED) + 1)
65 #define FORE200E_DEV(d) ((struct fore200e*)((d)->dev_data))
66 #define FORE200E_VCC(d) ((struct fore200e_vcc*)((d)->dev_data))
135 u32 buffer; /* transmit buffer DMA address */
190 u32 buffer_haddr; /* host DMA address of host buffer */
201 /* tpd DMA address */
207 u32 haddr : 27 /* tpd DMA addr aligned on 32 byte boundary */
[all …]
/linux-6.14.4/drivers/crypto/hisilicon/sec/
Dsec_drv.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2016-2017 HiSilicon Limited. */
71 /* Multi purpose field - gran size bits for send, flag for recv */
173 * struct sec_queue_ring_cmd - store information about a SEC HW cmd ring
177 * @paddr: Physical address of the dma mapped region of ram used for the ring.
231 * struct sec_alg_tfm_ctx - hardware specific tranformation context
234 * @pkey: DMA address for the key storage.
254 * struct sec_request - data associate with a single crypto request
261 * @dma_iv: initialization vector - phsyical address
289 * struct sec_request_el - A subpart of a request.
[all …]
/linux-6.14.4/Documentation/networking/device_drivers/ethernet/google/
Dgve.rst1 .. SPDX-License-Identifier: GPL-2.0+
12 +--------------+----------+---------+
16 +--------------+----------+---------+
18 +--------------+----------+---------+
19 |Sub-vendor ID | `0x1AE0` | Google |
20 +--------------+----------+---------+
21 |Sub-device ID | `0x0058` | |
22 +--------------+----------+---------+
24 +--------------+----------+---------+
26 +--------------+----------+---------+
[all …]
/linux-6.14.4/arch/arm/boot/dts/axis/
Dartpec6.dtsi2 * Device Tree Source for the Axis ARTPEC-6 SoC
4 * This file is dual-licensed: you can use it either under the terms
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/dma/nbpfaxi.h>
45 #include <dt-bindings/clock/axis,artpec6-clkctrl.h>
48 #address-cells = <1>;
49 #size-cells = <1>;
51 interrupt-parent = <&intc>;
54 #address-cells = <1>;
55 #size-cells = <0>;
[all …]

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