Lines Matching +full:dma +full:- +full:queues

1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2016-2017 HiSilicon Limited. */
71 /* Multi purpose field - gran size bits for send, flag for recv */
173  * struct sec_queue_ring_cmd - store information about a SEC HW cmd ring
177  * @paddr: Physical address of the dma mapped region of ram used for the ring.
231  * struct sec_alg_tfm_ctx - hardware specific tranformation context
234  * @pkey: DMA address for the key storage.
254  * struct sec_request - data associate with a single crypto request
261  * @dma_iv: initialization vector - phsyical address
289  * struct sec_request_el - A subpart of a request.
292  * @in: hardware sgl for input - virtual address
293  * @dma_in: hardware sgl for input - physical address
295  * @out: hardware sgl for output - virtual address
296  * @dma_out: hardware sgl for output - physical address
316  * struct sec_queue - All the information about a HW queue
327  *   use of the hardware queues.
328  * @havesoftqueue: A flag to say we have a queues - as we may need one for the
356  * @buf: The IOV dma address for this entry.
368  * @next_sgl: The next entry if we need to chain dma address. Null if last.
369  * @entry_sum_in_chain: The full count of SGEs - only matters for first SGL.
375  * @next: Virtual address used to stash the next sgl - useful in completion.
397  * struct sec_dev_info: The full SEC unit comprising queues and processors.
402  * @queues: The 16 queues that this SEC instance provides.
404  * @hw_sgl_pool: DMA pool used to mimise mapping for the scatter gather lists.
412 	struct sec_queue queues[SEC_Q_NUM];  member