Lines Matching +full:dma +full:- +full:queues

1 .. SPDX-License-Identifier: GPL-2.0
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80 Buttress with a copy of the SoC time, this counter maintains the up-to-date time
86 DMA and MMU
90 32-bit virtual address space. The IPU6 has MMU address translation hardware to
94 IPU6 driver. The IPU6 driver sets the level-1 page table base address to MMU
97 The IPU6 driver exports its own DMA operations. The IPU6 driver will update the
98 page table entries for each DMA operation and invalidate the MMU TLB after each
106 component includes 3 entries - manifest, metadata and module data. Manifest and
109 directory. The IPU6 driver (``ipu6-cpd.c`` in particular) parses and validates
111 firmware, copies it to specific DMA buffer and sets its base address to Buttress
120 inter-processor communication mechanism between the IPU scalar processors and
122 A system memory region where the message queues reside, firmware can access the
123 memory region via the IPU MMU. The Syscom queues are FIFO fixed depth queues
126 function as producer and consumer of tokens in the queues and update the write
130 queues, configure the count of tokens per queue and the size of per token before
140 IPU6 input system consists of MIPI D-PHY and several CSI-2 receivers.  It can
141 capture image pixel data from camera sensors or other MIPI CSI-2 output devices.
143 D-PHYs and CSI-2 ports lane mapping
144 -----------------------------------
146 The IPU6 integrates different D-PHY IPs on different SoCs, on Tiger Lake and
147 Alder Lake, IPU6 integrates MCD10 D-PHY, IPU6SE on Jasper Lake integrates JSL
148 D-PHY and IPU6EP on Meteor Lake integrates a Synopsys DWC D-PHY. There is an
149 adaptional layer between D-PHY and CSI-2 receiver controller which includes port
150 configuration, PHY wrapper or private test interfaces for D-PHY. There are 3
151 D-PHY drivers ``ipu6-isys-mcd-phy.c``, ``ipu6-isys-jsl-phy.c`` and
152 ``ipu6-isys-dwc-phy.c`` program the above 3 D-PHYs in IPU6.
154 Different IPU6 versions have different D-PHY lanes mappings, On Tiger Lake,
155 there are 12 data lanes and 8 clock lanes, IPU6 support maximum 8 CSI-2 ports,
156 see the PPI mmapping in ``ipu6-isys-mcd-phy.c`` for more information. On Jasper
157 Lake and Alder Lake, D-PHY has 8 data lanes and 4 clock lanes, the IPU6 supports
158 maximum 4 CSI-2 ports. For Meteor Lake, D-PHY has 12 data lanes and 6 clock
159 lanes so IPU6 support maximum 6 CSI-2 ports.
161 .. Note:: Each pair of CSI-2 two ports is a single unit that can share the data
162 	  lanes. For example, for CSI-2 port 0 and 1, CSI-2 port 0 support
163 	  maximum 4 data lanes, CSI-2 port 1 support maximum 2 data lanes, CSI-2
164 	  port 0 with 2 data lanes can work together with CSI-2 port 1 with 2
165 	  data lanes. If trying to use CSI-2 port 0 with 4 lanes, CSI-2 port 1
166 	  will not be available as the 4 data lanes are shared by CSI-2 port 0
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184 command queues the buffers to firmware with ``struct