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/linux-6.14.4/Documentation/devicetree/bindings/clock/
Dti,cdce925.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexander Stein <[email protected]-group.com>
15 - CDCE(L)913: 1-PLL, 3 Outputs https://www.ti.com/product/cdce913
16 - CDCE(L)925: 2-PLL, 5 Outputs https://www.ti.com/product/cdce925
17 - CDCE(L)937: 3-PLL, 7 Outputs https://www.ti.com/product/cdce937
18 - CDCE(L)949: 4-PLL, 9 Outputs https://www.ti.com/product/cdce949
23 - ti,cdce913
24 - ti,cdce925
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Dst,stm32-rcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/st,stm32-rcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dario Binacchi <[email protected]>
20 - items:
21 - enum:
22 - st,stm32f42xx-rcc
23 - st,stm32f746-rcc
24 - st,stm32h743-rcc
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/linux-6.14.4/drivers/scsi/isci/
Dprobe_roms.h7 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
20 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
26 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
103 * - A value of 1 indicates generation 1 (i.e. 1.5 Gb/s).
104 * - A value of 2 indicates generation 2 (i.e. 3.0 Gb/s).
105 * - A value of 3 indicates generation 3 (i.e. 6.0 Gb/s).
228 * Spread Spectrum Clocking (SSC) settings for SATA and SAS.
234 * NOTE: Max spread for SATA is +0 / -5000 PPM.
235 * Down-spreading SSC (only method allowed for SATA):
237 * SATA SSC Tx at +0 / -1419 PPM Spread = 0x2
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/linux-6.14.4/Documentation/driver-api/thermal/
Dintel_dptf.rst1 .. SPDX-License-Identifier: GPL-2.0
12 ------------
31 ----------------------------
43 "42A441D6-AE6A-462b-A84B-4A8CE79027D3" : Passive 1
45 "3A95C389-E4B8-4629-A526-C52C88626BAE" : Active
47 "97C68AE7-15FA-499c-B8C9-5DA81D606E0A" : Critical
49 "63BE270F-1C11-48FD-A6F7-3AF253FF3E2D" : Adaptive performance
51 "5349962F-71E6-431D-9AE8-0A635B710AEE" : Emergency call
53 "9E04115A-AE87-4D1C-9500-0F3E340BFE75" : Passive 2
55 "F5A35014-C209-46A4-993A-EB56DE7530A1" : Power Boss
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/linux-6.14.4/drivers/gpu/drm/amd/display/include/
Dbios_parser_types.h2 * Copyright 2012-15 Advanced Micro Devices, Inc.
197 /* Input: Signal Type - to be converted to Encoder mode */
207 /* Output: If non-zero, this refDiv value should be used to calculate
210 /* Output: If non-zero, this postDiv value should be used to calculate
213 /* Input: Enable spread spectrum */
220 /* signal_type -> Encoder Mode - needed by VBIOS Exec table */
234 /* VBIOS returns a fixed display clock when DFS-bypass feature
285 /* 1 = Center Spread; 0 = down spread */
289 /* 1 = delta-sigma type parameter; 0 = ver1 */
/linux-6.14.4/sound/pci/ac97/
Dac97_patch.c1 // SPDX-License-Identifier: GPL-2.0-or-later
33 err = snd_ctl_add(ac97->bus->card, snd_ac97_cnew(&controls[idx], ac97)); in patch_build_controls()
46 kctl = snd_ctl_find_id_mixer(ac97->bus->card, name); in reset_tlv()
47 if (kctl && kctl->tlv.p) in reset_tlv()
48 kctl->tlv.p = tlv; in reset_tlv()
57 mutex_lock(&ac97->page_mutex); in ac97_update_bits_page()
62 mutex_unlock(&ac97->page_mutex); /* unlock paging */ in ac97_update_bits_page()
67 * shared line-in/mic controls
80 ucontrol->value.enumerated.item[0] = ac97->indep_surround; in ac97_surround_jack_mode_get()
87 unsigned char indep = !!ucontrol->value.enumerated.item[0]; in ac97_surround_jack_mode_put()
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/linux-6.14.4/drivers/clk/
Dclk-eyeq.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * - Read-only PLLs, all derived from the same main crystal clock.
7 * - It also exposes divider clocks, those are children to PLLs.
8 * - Fixed factor clocks, children to PLLs.
11 * shared region called OLB. Some PLLs and fixed-factors are initialised early
14 * We use eqc_ as prefix, as-in "EyeQ Clock", but way shorter.
23 #define pr_fmt(fmt) "clk-eyeq: " fmt
29 #include <linux/clk-provider.h>
34 #include <linux/io-64-nonatomic-hi-lo.h>
47 #include <dt-bindings/clock/mobileye,eyeq5-clk.h>
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Dclk-cdce925.c5 * Y4/Y5 to PLL2, and so on. PLL frequency is set on a first-come-first-serve
14 #include <linux/clk-provider.h>
54 u16 pdiv; /* 1..127 for Y2-Y9; 1..1023 for Y1 */
92 return cdce925_pll_calculate_rate(parent_rate, data->n, data->m); in cdce925_pll_recalc_rate()
146 data->m = 0; /* Bypass mode */ in cdce925_pll_set_rate()
147 data->n = 0; in cdce925_pll_set_rate()
154 return -EINVAL; in cdce925_pll_set_rate()
160 return -EINVAL; in cdce925_pll_set_rate()
163 cdce925_pll_find_rate(rate, parent_rate, &data->n, &data->m); in cdce925_pll_set_rate()
168 /* calculate p = max(0, 4 - int(log2 (n/m))) */
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Dclk-stm32f4.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Inspired by clk-asm9260.c .
9 #include <linux/clk-provider.h>
26 #include <dt-bindings/clock/stm32fx-clock.h>
52 #define NONE -1
383 [STM32F4_PLL_SSC_DOWN_SPREAD] = "down-spread",
384 [STM32F4_PLL_SSC_CENTER_SPREAD] = "center-spread",
423 * The APBx dividers are power-of-two dividers and, if *not* running in 1:1
440 if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx)) in clk_apb_mul_recalc_rate()
452 if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx)) in clk_apb_mul_round_rate()
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/linux-6.14.4/drivers/gpu/drm/radeon/
Datombios.h2 * Copyright 2006-2007 Advanced Micro Devices, Inc.
214 UCHAR uaFirmWareSignature[4]; /*Signature to distinguish between Atombios and non-atombios,
397 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
403 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
410 …ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Di…
504 …UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0)…
536 #define ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN 1 // 1-StrobeMode, 0-PerformanceMode
544 …bDiv; //Output:UPPER_WORD=FB_DIV_INTEGER, LOWER_WORD=FB_DIV_FRAC shl (16-FB_FRACTION_BITS)
549 … //Input : ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN: 1-StrobeMode, 0-PerformanceMode
815 // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disab…
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/linux-6.14.4/drivers/gpu/drm/amd/include/
Datombios.h2 * Copyright 2006-2007 Advanced Micro Devices, Inc.
107 #define ATOM_SCALER_DISABLE 0 //For Fudo, it's bypass and auto-cengter & no replication
108 #define ATOM_SCALER_CENTER 1 //For Fudo, it's bypass and auto-center & auto replication
110 #define ATOM_SCALER_MULTI_EX 3 //For Fudo only, it's multi-tap mode only used to drive TV or CV,…
222 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
245 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
427 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
433 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
440 …ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Di…
538 …UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0)…
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Datomfirmware.h6 * Description header file of general definitions for OS and pre-OS video drivers
31 * If a change in VBIOS/Driver/Tool's interface is only needed for pre-SoC15 products, then the chan…
115 ATOM_SCALER_DISABLE =0, /*scaler bypass mode, auto-center & no replication*/
116 ATOM_SCALER_CENTER =1, //For Fudo, it's bypass and auto-center & auto replication
202 #define BIOS_VERSION_PREFIX "ATOMBIOSBK-AMD"
245 …tom_string_def atom_bios_string; //Signature to distinguish between Atombios and non-atombios,
604 uint32_t maco_pwrlimit_mw; // bomaco mode power limit in unit of m-watt
605 uint32_t usb_pwrlimit_mw; // power limit when USB is enable in unit of m-watt
636 uint32_t maco_pwrlimit_mw; // bomaco mode power limit in unit of m-watt
637 uint32_t usb_pwrlimit_mw; // power limit when USB is enable in unit of m-watt
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/linux-6.14.4/drivers/gpu/drm/msm/dsi/phy/
Ddsi_phy_14nm.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
17 * DSI PLL 14nm - clock diagram (eg: DSI0):
22 * +----+ | +----+
23 * dsi0vco_clk ---| n1 |--o--| /8 |-- dsi0pllbyte
24 * +----+ | +----+
26 * | +----+ |
27 * o---| /2 |--o--|\
28 * | +----+ | \ +----+
29 * | | |--| n2 |-- dsi0pll
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/linux-6.14.4/drivers/clk/renesas/
Drcar-gen4-cpg.c1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car Gen4 Clock Pulse Generator
7 * Based on rcar-gen3-cpg.c
9 * Copyright (C) 2015-2018 Glider bvba
15 #include <linux/clk-provider.h>
23 #include "renesas-cpg-mssr.h"
24 #include "rcar-gen4-cpg.h"
25 #include "rcar-cpg-lib.h"
33 #define CPG_PLLECR_PLLST(n) BIT(8 + ((n) < 3 ? (n) - 1 : \
51 #define CPG_PLLxCR0_SSMODE_CENT BIT(16) /* Center (vs. Down) Spread Dithering */
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/linux-6.14.4/drivers/phy/broadcom/
Dphy-brcm-sata.c1 // SPDX-License-Identifier: GPL-2.0-or-later
196 struct brcm_sata_phy *priv = port->phy_priv; in brcm_sata_ctrl_base()
199 switch (priv->version) { in brcm_sata_ctrl_base()
204 dev_err(priv->dev, "invalid phy version\n"); in brcm_sata_ctrl_base()
208 return priv->ctrl_base + (port->portnum * size); in brcm_sata_ctrl_base()
214 struct brcm_sata_phy *priv = port->phy_priv; in brcm_sata_phy_wr()
215 void __iomem *pcb_base = priv->phy_base; in brcm_sata_phy_wr()
218 if (priv->version == BRCM_SATA_PHY_STB_40NM) in brcm_sata_phy_wr()
219 bank += (port->portnum * SATA_PCB_REG_40NM_SPACE_SIZE); in brcm_sata_phy_wr()
221 pcb_base += (port->portnum * SATA_PCB_REG_28NM_SPACE_SIZE); in brcm_sata_phy_wr()
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/linux-6.14.4/Documentation/input/devices/
Delantech.rst4 Copyright (C) 2007-2008 Arjan Opmeer <[email protected]>
25 5.2.1 Parity checking and packet re-synchronization
114 non-zero value will turn it ON. For hardware version 1 the default is ON.
145 4 bytes version: (after the arrow is the name given in the Dell-provided driver)
173 ---------
179 echo -n 0x16 > reg_10
236 -----------------------------------------
298 -----------------------------------------
360 ---------
366 echo -n 0x56 > reg_10
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/linux-6.14.4/include/uapi/linux/
Dnl80211.h6 * Copyright 2006-2010 Johannes Berg <[email protected]>
13 * Copyright 2015-2017 Intel Deutschland GmbH
14 * Copyright (C) 2018-2024 Intel Corporation
32 * be careful not to break things - i.e. don't move anything around or so
74 * - a setup station entry is added, not yet authorized, without any rate
76 * - when the TDLS setup is done, a single NL80211_CMD_SET_STATION is valid
79 * - %NL80211_TDLS_ENABLE_LINK is then used
80 * - after this, the only valid operation is to remove it by tearing down
95 * Frame registration is done on a per-interface basis and registrations
137 * software, like the AP-VLAN type in mac80211 for example, there's
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/linux-6.14.4/include/net/
Dcfg80211.h1 /* SPDX-License-Identifier: GPL-2.0-only */
7 * Copyright 2006-2010 Johannes Berg <[email protected]>
8 * Copyright 2013-2014 Intel Mobile Communications GmbH
9 * Copyright 2015-2017 Intel Deutschland GmbH
10 * Copyright (C) 2018-2024 Intel Corporation
72 * enum ieee80211_channel_flags - channel flags
167 * struct ieee80211_channel - channel definition
172 * @center_freq: center frequency in MHz
174 * @hw_value: hardware-specific value for the channel
212 * enum ieee80211_rate_flags - rate flags
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/linux-6.14.4/drivers/net/wireless/ath/ath12k/
Dhal_desc.h1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2022, 2024 Qualcomm Innovation Center, Inc. All rights reserved.
649 * Indicates the MPDU was received as part of an A-MPDU.
661 * 'RAW' MPDU might be spread out over multiple MSDU buffers.
724 * is spread out over multiple buffers and thus msdu_continuation
739 * field is still valid for MPDU frames without A-MSDU. It still
780 * This packet needs intra-BSS routing by SW as the 'vdev_id'
786 * to support intra-BSS routing with multi-chip multi-link operation.
810 * Opaque service code between PPE and Wi-Fi
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Ddp_rx.c1 // SPDX-License-Identifier: BSD-3-Clause-Clear
3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
27 if (!ab->hal_rx_ops->rx_desc_encrypt_valid(desc)) in ath12k_dp_rx_h_enctype()
30 return ab->hal_rx_ops->rx_desc_get_encrypt_type(desc); in ath12k_dp_rx_h_enctype()
36 return ab->hal_rx_ops->rx_desc_get_decap_type(desc); in ath12k_dp_rx_h_decap_type()
42 return ab->hal_rx_ops->rx_desc_get_mesh_ctl(desc); in ath12k_dp_rx_h_mesh_ctl_present()
48 return ab->hal_rx_ops->rx_desc_get_mpdu_seq_ctl_vld(desc); in ath12k_dp_rx_h_seq_ctrl_valid()
54 return ab->hal_rx_ops->rx_desc_get_mpdu_fc_valid(desc); in ath12k_dp_rx_h_fc_valid()
62 hdr = (struct ieee80211_hdr *)(skb->data + ab->hal.hal_desc_sz); in ath12k_dp_rx_h_more_frags()
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/linux-6.14.4/drivers/phy/rockchip/
Dphy-rockchip-inno-hdmi.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Author: Zheng Yang <zhengyang@rock-chips.com>
10 #include <linux/clk-provider.h>
16 #include <linux/nvmem-consumer.h>
127 /* for all RK3328_INT_TMDS_*, ESD_DET as defined in 0xc8-0xcb */
140 /* unset means center spread */
206 /* REG 0xc8 - 0xcb */
526 * but instead the databook simply numbers the registers in one-increments.
532 regmap_write(inno->regmap, reg * 4, val); in inno_write()
539 regmap_read(inno->regmap, reg * 4, &val); in inno_read()
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/linux-6.14.4/drivers/net/wireless/ath/ath11k/
Dhal_desc.h1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
531 * Indicates the MPDU was received as part of an A-MPDU.
602 * is spread out over multiple buffers and thus msdu_continuation
617 * field is still valid for MPDU frames without A-MSDU. It still
749 * re-ordering of frames for this queue, but just to insert
761 * 0 - Idle ring
762 * 1 - N refers to other rings.
855 * 0 - Idle ring
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Ddp_rx.c1 // SPDX-License-Identifier: BSD-3-Clause-Clear
3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
27 return ab->hw_params.hw_ops->rx_desc_get_hdr_status(desc); in ath11k_dp_rx_h_80211_hdr()
34 if (!ab->hw_params.hw_ops->rx_desc_encrypt_valid(desc)) in ath11k_dp_rx_h_mpdu_start_enctype()
37 return ab->hw_params.hw_ops->rx_desc_get_encrypt_type(desc); in ath11k_dp_rx_h_mpdu_start_enctype()
43 return ab->hw_params.hw_ops->rx_desc_get_decap_type(desc); in ath11k_dp_rx_h_msdu_start_decap_type()
50 return ab->hw_params.hw_ops->rx_desc_get_ldpc_support(desc); in ath11k_dp_rx_h_msdu_start_ldpc_support()
57 return ab->hw_params.hw_ops->rx_desc_get_mesh_ctl(desc); in ath11k_dp_rx_h_msdu_start_mesh_ctl_present()
64 return ab->hw_params.hw_ops->rx_desc_get_mpdu_seq_ctl_vld(desc); in ath11k_dp_rx_h_mpdu_start_seq_ctrl_valid()
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/linux-6.14.4/drivers/media/i2c/
Dov5640.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved.
4 * Copyright (C) 2014-2017 Mentor Graphics Inc.
8 #include <linux/clk-provider.h>
22 #include <media/v4l2-async.h>
23 #include <media/v4l2-ctrls.h>
24 #include <media/v4l2-device.h>
25 #include <media/v4l2-event.h>
26 #include <media/v4l2-fwnode.h>
27 #include <media/v4l2-subdev.h>
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/linux-6.14.4/drivers/gpu/drm/i915/display/
Dintel_display.c2 * Copyright © 2006-2007 Intel Corporation
27 #include <linux/dma-resv.h>
161 drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) != in vlv_get_cck_clock()
175 if (dev_priv->hpll_freq == 0) in vlv_get_cck_clock_hpll()
176 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv); in vlv_get_cck_clock_hpll()
178 hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq); in vlv_get_cck_clock_hpll()
190 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", in intel_update_czclk()
193 drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n", in intel_update_czclk()
194 dev_priv->czclk_freq); in intel_update_czclk()
199 return (crtc_state->active_planes & in is_hdr_mode()
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