2  * Copyright © 2006-2007 Intel Corporation
27 #include <linux/dma-resv.h>
161 	drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) !=  in vlv_get_cck_clock()
175 	if (dev_priv->hpll_freq == 0)  in vlv_get_cck_clock_hpll()
176 		dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);  in vlv_get_cck_clock_hpll()
178 	hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq);  in vlv_get_cck_clock_hpll()
190 	dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",  in intel_update_czclk()
193 	drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n",  in intel_update_czclk()
194 		dev_priv->czclk_freq);  in intel_update_czclk()
199 	return (crtc_state->active_planes &  in is_hdr_mode()
235 	return crtc_state->master_transcoder != INVALID_TRANSCODER;  in is_trans_port_sync_slave()
241 	return crtc_state->sync_mode_slaves_mask != 0;  in is_trans_port_sync_master()
253 	return ffs(crtc_state->joiner_pipes) - 1;  in joiner_primary_pipe()
262 	return hweight8(crtc_state->joiner_pipes) >= 2;  in is_bigjoiner()
270 	return crtc_state->joiner_pipes & (0b01010101 << joiner_primary_pipe(crtc_state));  in bigjoiner_primary_pipes()
278 	return crtc_state->joiner_pipes & (0b10101010 << joiner_primary_pipe(crtc_state));  in bigjoiner_secondary_pipes()
283 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_crtc_is_bigjoiner_primary()
288 	return BIT(crtc->pipe) & bigjoiner_primary_pipes(crtc_state);  in intel_crtc_is_bigjoiner_primary()
293 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_crtc_is_bigjoiner_secondary()
298 	return BIT(crtc->pipe) & bigjoiner_secondary_pipes(crtc_state);  in intel_crtc_is_bigjoiner_secondary()
303 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in _intel_modeset_primary_pipes()
306 		return BIT(crtc->pipe);  in _intel_modeset_primary_pipes()
326 	return crtc_state->joiner_pipes & (0b00010001 << joiner_primary_pipe(crtc_state));  in ultrajoiner_primary_pipes()
331 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_crtc_is_ultrajoiner_primary()
334 	       BIT(crtc->pipe) & ultrajoiner_primary_pipes(crtc_state);  in intel_crtc_is_ultrajoiner_primary()
347 	return crtc_state->joiner_pipes & (0b01110111 << joiner_primary_pipe(crtc_state));  in ultrajoiner_enable_pipes()
352 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_crtc_ultrajoiner_enable_needed()
355 	       BIT(crtc->pipe) & ultrajoiner_enable_pipes(crtc_state);  in intel_crtc_ultrajoiner_enable_needed()
360 	if (crtc_state->joiner_pipes)  in intel_crtc_joiner_secondary_pipes()
361 		return crtc_state->joiner_pipes & ~BIT(joiner_primary_pipe(crtc_state));  in intel_crtc_joiner_secondary_pipes()
368 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_crtc_is_joiner_secondary()
370 	return crtc_state->joiner_pipes &&  in intel_crtc_is_joiner_secondary()
371 		crtc->pipe != joiner_primary_pipe(crtc_state);  in intel_crtc_is_joiner_secondary()
376 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_crtc_is_joiner_primary()
378 	return crtc_state->joiner_pipes &&  in intel_crtc_is_joiner_primary()
379 		crtc->pipe == joiner_primary_pipe(crtc_state);  in intel_crtc_is_joiner_primary()
389 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_crtc_joined_pipe_mask()
391 	return BIT(crtc->pipe) | crtc_state->joiner_pipes;  in intel_crtc_joined_pipe_mask()
401 		return to_intel_crtc(crtc_state->uapi.crtc);  in intel_primary_crtc()
407 	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);  in intel_wait_for_pipe_off()
408 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_wait_for_pipe_off()
411 		enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;  in intel_wait_for_pipe_off()
416 			drm_WARN(&dev_priv->drm, 1, "pipe_off wait timed out\n");  in intel_wait_for_pipe_off()
425 	struct intel_display *display = &dev_priv->display;  in assert_transcoder()
454 	struct intel_display *display = to_intel_display(plane->base.dev);  in assert_plane()
458 	cur_state = plane->get_hw_state(plane, &pipe);  in assert_plane()
462 				 plane->base.name, str_on_off(state),  in assert_plane()
471 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in assert_planes_disabled()
474 	for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)  in assert_planes_disabled()
485 	switch (dig_port->base.port) {  in vlv_wait_port_ready()
487 		MISSING_CASE(dig_port->base.port);  in vlv_wait_port_ready()
505 		drm_WARN(display->drm, 1,  in vlv_wait_port_ready()
507 			 dig_port->base.base.base.id, dig_port->base.base.name,  in vlv_wait_port_ready()
515 	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);  in intel_enable_transcoder()
516 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_enable_transcoder()
517 	enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;  in intel_enable_transcoder()
518 	enum pipe pipe = crtc->pipe;  in intel_enable_transcoder()
521 	drm_dbg_kms(&dev_priv->drm, "enabling pipe %c\n", pipe_name(pipe));  in intel_enable_transcoder()
536 		if (new_crtc_state->has_pch_encoder) {  in intel_enable_transcoder()
546 	/* Wa_22012358565:adl-p */  in intel_enable_transcoder()
565 		drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv));  in intel_enable_transcoder()
571 	    new_crtc_state->dsc.compression_enable) {  in intel_enable_transcoder()
595 	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);  in intel_disable_transcoder()
596 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_disable_transcoder()
597 	enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;  in intel_disable_transcoder()
598 	enum pipe pipe = crtc->pipe;  in intel_disable_transcoder()
601 	drm_dbg_kms(&dev_priv->drm, "disabling pipe %c\n", pipe_name(pipe));  in intel_disable_transcoder()
617 	if (old_crtc_state->double_wide)  in intel_disable_transcoder()
626 	    old_crtc_state->dsc.compression_enable)  in intel_disable_transcoder()
644 	for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)  in intel_rotation_info_size()
645 		size += rot_info->plane[i].dst_stride * rot_info->plane[i].width;  in intel_rotation_info_size()
655 	for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++) {  in intel_remapped_info_size()
658 		if (rem_info->plane[i].linear)  in intel_remapped_info_size()
659 			plane_size = rem_info->plane[i].size;  in intel_remapped_info_size()
661 			plane_size = rem_info->plane[i].dst_stride * rem_info->plane[i].height;  in intel_remapped_info_size()
666 		if (rem_info->plane_alignment)  in intel_remapped_info_size()
667 			size = ALIGN(size, rem_info->plane_alignment);  in intel_remapped_info_size()
677 	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);  in intel_plane_uses_fence()
678 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);  in intel_plane_uses_fence()
681 		(plane->fbc && !plane_state->no_fbc_reason &&  in intel_plane_uses_fence()
682 		 plane_state->view.gtt.type == I915_GTT_VIEW_NORMAL);  in intel_plane_uses_fence()
688  * offset is only used with linear buffers on pre-hsw and tiled buffers
695 	const struct drm_framebuffer *fb = state->hw.fb;  in intel_fb_xy_to_linear()
696 	unsigned int cpp = fb->format->cpp[color_plane];  in intel_fb_xy_to_linear()
697 	unsigned int pitch = state->view.color_plane[color_plane].mapping_stride;  in intel_fb_xy_to_linear()
703  * Add the x/y offsets derived from fb->offsets[] to the user
712 	*x += state->view.color_plane[color_plane].x;  in intel_add_fb_offsets()
713 	*y += state->view.color_plane[color_plane].y;  in intel_add_fb_offsets()
734 	plane = to_intel_plane(crtc->base.primary);  in intel_plane_fb_max_stride()
736 	return plane->max_stride(plane, pixel_format, modifier,  in intel_plane_fb_max_stride()
744 	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);  in intel_set_plane_visible()
746 	plane_state->uapi.visible = visible;  in intel_set_plane_visible()
749 		crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base);  in intel_set_plane_visible()
751 		crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base);  in intel_set_plane_visible()
756 	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);  in intel_plane_fixup_bitmasks()
764 	crtc_state->enabled_planes = 0;  in intel_plane_fixup_bitmasks()
765 	crtc_state->active_planes = 0;  in intel_plane_fixup_bitmasks()
767 	drm_for_each_plane_mask(plane, &dev_priv->drm,  in intel_plane_fixup_bitmasks()
768 				crtc_state->uapi.plane_mask) {  in intel_plane_fixup_bitmasks()
769 		crtc_state->enabled_planes |= BIT(to_intel_plane(plane)->id);  in intel_plane_fixup_bitmasks()
770 		crtc_state->active_planes |= BIT(to_intel_plane(plane)->id);  in intel_plane_fixup_bitmasks()
777 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_plane_disable_noatomic()
779 		to_intel_crtc_state(crtc->base.state);  in intel_plane_disable_noatomic()
781 		to_intel_plane_state(plane->base.state);  in intel_plane_disable_noatomic()
783 	drm_dbg_kms(&dev_priv->drm,  in intel_plane_disable_noatomic()
785 		    plane->base.base.id, plane->base.name,  in intel_plane_disable_noatomic()
786 		    crtc->base.base.id, crtc->base.name);  in intel_plane_disable_noatomic()
790 	crtc_state->data_rate[plane->id] = 0;  in intel_plane_disable_noatomic()
791 	crtc_state->data_rate_y[plane->id] = 0;  in intel_plane_disable_noatomic()
792 	crtc_state->rel_data_rate[plane->id] = 0;  in intel_plane_disable_noatomic()
793 	crtc_state->rel_data_rate_y[plane->id] = 0;  in intel_plane_disable_noatomic()
794 	crtc_state->min_cdclk[plane->id] = 0;  in intel_plane_disable_noatomic()
796 	if ((crtc_state->active_planes & ~BIT(PLANE_CURSOR)) == 0 &&  in intel_plane_disable_noatomic()
798 		crtc_state->ips_enabled = false;  in intel_plane_disable_noatomic()
804 	 * are blocked if the memory self-refresh mode is active at that  in intel_plane_disable_noatomic()
806 	 * first the self-refresh mode. The self-refresh enable bit in turn  in intel_plane_disable_noatomic()
809 	 * wait-for-vblank between disabling the plane and the pipe.  in intel_plane_disable_noatomic()
819 	if (DISPLAY_VER(dev_priv) == 2 && !crtc_state->active_planes)  in intel_plane_disable_noatomic()
820 		intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);  in intel_plane_disable_noatomic()
832 					  plane_state->view.color_plane[0].offset, 0);  in intel_plane_fence_y_offset()
839 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in icl_set_pipe_chicken()
840 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in icl_set_pipe_chicken()
841 	enum pipe pipe = crtc->pipe;  in icl_set_pipe_chicken()
849 	 * and rounding for per-pixel values 00 and 0xff  in icl_set_pipe_chicken()
881 	drm_for_each_crtc(crtc, &dev_priv->drm) {  in intel_has_pending_fb_unpin()
883 		spin_lock(&crtc->commit_lock);  in intel_has_pending_fb_unpin()
884 		commit = list_first_entry_or_null(&crtc->commit_list,  in intel_has_pending_fb_unpin()
887 			try_wait_for_completion(&commit->cleanup_done) : true;  in intel_has_pending_fb_unpin()
888 		spin_unlock(&crtc->commit_lock);  in intel_has_pending_fb_unpin()
918 	for_each_new_connector_in_state(&state->base, connector, connector_state, i) {  in intel_get_crtc_new_encoder()
919 		if (connector_state->crtc != &primary_crtc->base)  in intel_get_crtc_new_encoder()
922 		encoder = to_intel_encoder(connector_state->best_encoder);  in intel_get_crtc_new_encoder()
926 	drm_WARN(state->base.dev, num_encoders != 1,  in intel_get_crtc_new_encoder()
928 		 num_encoders, pipe_name(primary_crtc->pipe));  in intel_get_crtc_new_encoder()
935 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in ilk_pfit_enable()
936 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in ilk_pfit_enable()
937 	const struct drm_rect *dst = &crtc_state->pch_pfit.dst;  in ilk_pfit_enable()
938 	enum pipe pipe = crtc->pipe;  in ilk_pfit_enable()
941 	int x = dst->x1;  in ilk_pfit_enable()
942 	int y = dst->y1;  in ilk_pfit_enable()
944 	if (!crtc_state->pch_pfit.enabled)  in ilk_pfit_enable()
947 	/* Force use of hard-coded filter coefficients  in ilk_pfit_enable()
948 	 * as some pre-programmed values are broken,  in ilk_pfit_enable()
965 	if (crtc->overlay)  in intel_crtc_dpms_overlay_disable()
966 		(void) intel_overlay_switch_off(crtc->overlay);  in intel_crtc_dpms_overlay_disable()
975 	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);  in needs_nv12_wa()
977 	if (!crtc_state->nv12_planes)  in needs_nv12_wa()
989 	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);  in needs_scalerclk_wa()
992 	if (crtc_state->scaler_state.scaler_users > 0 && DISPLAY_VER(dev_priv) == 11)  in needs_scalerclk_wa()
1000 	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);  in needs_cursorclk_wa()
1004 	    crtc_state->active_planes & BIT(PLANE_CURSOR) &&  in needs_cursorclk_wa()
1032 	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);  in needs_async_flip_vtd_wa()
1034 	return crtc_state->uapi.async_flip && i915_vtd_active(i915) &&  in needs_async_flip_vtd_wa()
1047 	for_each_new_connector_in_state(&state->base, conn, conn_state, i) {  in intel_encoders_audio_enable()
1049 			to_intel_encoder(conn_state->best_encoder);  in intel_encoders_audio_enable()
1051 		if (conn_state->crtc != &crtc->base)  in intel_encoders_audio_enable()
1054 		if (encoder->audio_enable)  in intel_encoders_audio_enable()
1055 			encoder->audio_enable(encoder, crtc_state, conn_state);  in intel_encoders_audio_enable()
1068 	for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {  in intel_encoders_audio_disable()
1070 			to_intel_encoder(old_conn_state->best_encoder);  in intel_encoders_audio_disable()
1072 		if (old_conn_state->crtc != &crtc->base)  in intel_encoders_audio_disable()
1075 		if (encoder->audio_disable)  in intel_encoders_audio_disable()
1076 			encoder->audio_disable(encoder, old_crtc_state, old_conn_state);  in intel_encoders_audio_disable()
1081 	((!(old_crtc_state)->feature || intel_crtc_needs_modeset(new_crtc_state)) && \
1082 	 (new_crtc_state)->feature)
1084 	((old_crtc_state)->feature && \
1085 	 (!(new_crtc_state)->feature || intel_crtc_needs_modeset(new_crtc_state)))
1090 	if (!new_crtc_state->hw.active)  in planes_enabling()
1099 	if (!old_crtc_state->hw.active)  in planes_disabling()
1108 	return old_crtc_state->vrr.flipline != new_crtc_state->vrr.flipline ||  in vrr_params_changed()
1109 		old_crtc_state->vrr.vmin != new_crtc_state->vrr.vmin ||  in vrr_params_changed()
1110 		old_crtc_state->vrr.vmax != new_crtc_state->vrr.vmax ||  in vrr_params_changed()
1111 		old_crtc_state->vrr.guardband != new_crtc_state->vrr.guardband ||  in vrr_params_changed()
1112 		old_crtc_state->vrr.pipeline_full != new_crtc_state->vrr.pipeline_full ||  in vrr_params_changed()
1113 		old_crtc_state->vrr.vsync_start != new_crtc_state->vrr.vsync_start ||  in vrr_params_changed()
1114 		old_crtc_state->vrr.vsync_end != new_crtc_state->vrr.vsync_end;  in vrr_params_changed()
1120 	return old_crtc_state->cmrr.cmrr_m != new_crtc_state->cmrr.cmrr_m ||  in cmrr_params_changed()
1121 		old_crtc_state->cmrr.cmrr_n != new_crtc_state->cmrr.cmrr_n;  in cmrr_params_changed()
1132 	if (!new_crtc_state->hw.active)  in intel_crtc_vrr_enabling()
1136 		(new_crtc_state->vrr.enable &&  in intel_crtc_vrr_enabling()
1137 		 (new_crtc_state->update_m_n || new_crtc_state->update_lrr ||  in intel_crtc_vrr_enabling()
1149 	if (!old_crtc_state->hw.active)  in intel_crtc_vrr_disabling()
1153 		(old_crtc_state->vrr.enable &&  in intel_crtc_vrr_disabling()
1154 		 (new_crtc_state->update_m_n || new_crtc_state->update_lrr ||  in intel_crtc_vrr_disabling()
1161 	if (!new_crtc_state->hw.active)  in audio_enabling()
1165 		(new_crtc_state->has_audio &&  in audio_enabling()
1166 		 memcmp(old_crtc_state->eld, new_crtc_state->eld, MAX_ELD_BYTES) != 0);  in audio_enabling()
1172 	if (!old_crtc_state->hw.active)  in audio_disabling()
1176 		(old_crtc_state->has_audio &&  in audio_disabling()
1177 		 memcmp(old_crtc_state->eld, new_crtc_state->eld, MAX_ELD_BYTES) != 0);  in audio_disabling()
1186 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);  in intel_post_plane_update()
1191 	enum pipe pipe = crtc->pipe;  in intel_post_plane_update()
1195 	intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits);  in intel_post_plane_update()
1197 	if (new_crtc_state->update_wm_post && new_crtc_state->hw.active)  in intel_post_plane_update()
1246 	u8 update_planes = crtc_state->update_planes;  in intel_crtc_enable_flip_done()
1252 		if (plane->pipe == crtc->pipe &&  in intel_crtc_enable_flip_done()
1253 		    update_planes & BIT(plane->id))  in intel_crtc_enable_flip_done()
1254 			plane->enable_flip_done(plane);  in intel_crtc_enable_flip_done()
1263 	u8 update_planes = crtc_state->update_planes;  in intel_crtc_disable_flip_done()
1269 		if (plane->pipe == crtc->pipe &&  in intel_crtc_disable_flip_done()
1270 		    update_planes & BIT(plane->id))  in intel_crtc_disable_flip_done()
1271 			plane->disable_flip_done(plane);  in intel_crtc_disable_flip_done()
1282 	u8 disable_async_flip_planes = old_crtc_state->async_flip_planes &  in intel_crtc_async_flip_disable_wa()
1283 				       ~new_crtc_state->async_flip_planes;  in intel_crtc_async_flip_disable_wa()
1290 		if (plane->need_async_flip_toggle_wa &&  in intel_crtc_async_flip_disable_wa()
1291 		    plane->pipe == crtc->pipe &&  in intel_crtc_async_flip_disable_wa()
1292 		    disable_async_flip_planes & BIT(plane->id)) {  in intel_crtc_async_flip_disable_wa()
1310 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);  in intel_pre_plane_update()
1315 	enum pipe pipe = crtc->pipe;  in intel_pre_plane_update()
1356 	 * are blocked if the memory self-refresh mode is active at that  in intel_pre_plane_update()
1358 	 * first the self-refresh mode. The self-refresh enable bit in turn  in intel_pre_plane_update()
1361 	 * wait-for-vblank between disabling the plane and the pipe.  in intel_pre_plane_update()
1363 	if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active &&  in intel_pre_plane_update()
1364 	    new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))  in intel_pre_plane_update()
1369 	 * one frame before enabling scaling.  LP watermarks can be re-enabled  in intel_pre_plane_update()
1374 	if (!HAS_GMCH(dev_priv) && old_crtc_state->hw.active &&  in intel_pre_plane_update()
1375 	    new_crtc_state->disable_cxsr && ilk_disable_cxsr(dev_priv))  in intel_pre_plane_update()
1380 	 * pre-vblank watermark programming here.  in intel_pre_plane_update()
1385 		 * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these  in intel_pre_plane_update()
1386 		 * will be the intermediate values that are safe for both pre- and  in intel_pre_plane_update()
1387 		 * post- vblank; when vblank happens, the 'active' values will be set  in intel_pre_plane_update()
1398 			if (new_crtc_state->update_wm_pre)  in intel_pre_plane_update()
1417 	if (old_crtc_state->async_flip_planes & ~new_crtc_state->async_flip_planes)  in intel_pre_plane_update()
1424 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_crtc_disable_planes()
1427 	unsigned int update_mask = new_crtc_state->update_planes;  in intel_crtc_disable_planes()
1436 		if (crtc->pipe != plane->pipe ||  in intel_crtc_disable_planes()
1437 		    !(update_mask & BIT(plane->id)))  in intel_crtc_disable_planes()
1442 		if (old_plane_state->uapi.visible)  in intel_crtc_disable_planes()
1443 			fb_bits |= plane->frontbuffer_bit;  in intel_crtc_disable_planes()
1451 	struct drm_i915_private *i915 = to_i915(state->base.dev);  in intel_encoders_update_prepare()
1457 	 * Make sure the DPLL state is up-to-date for fastset TypeC ports after non-blocking commits.  in intel_encoders_update_prepare()
1458 	 * TODO: Update the DPLL state for all cases in the encoder->update_prepare() hook.  in intel_encoders_update_prepare()
1460 	if (i915->display.dpll.mgr) {  in intel_encoders_update_prepare()
1465 			new_crtc_state->shared_dpll = old_crtc_state->shared_dpll;  in intel_encoders_update_prepare()
1466 			new_crtc_state->dpll_hw_state = old_crtc_state->dpll_hw_state;  in intel_encoders_update_prepare()
1480 	for_each_new_connector_in_state(&state->base, conn, conn_state, i) {  in intel_encoders_pre_pll_enable()
1482 			to_intel_encoder(conn_state->best_encoder);  in intel_encoders_pre_pll_enable()
1484 		if (conn_state->crtc != &crtc->base)  in intel_encoders_pre_pll_enable()
1487 		if (encoder->pre_pll_enable)  in intel_encoders_pre_pll_enable()
1488 			encoder->pre_pll_enable(state, encoder,  in intel_encoders_pre_pll_enable()
1502 	for_each_new_connector_in_state(&state->base, conn, conn_state, i) {  in intel_encoders_pre_enable()
1504 			to_intel_encoder(conn_state->best_encoder);  in intel_encoders_pre_enable()
1506 		if (conn_state->crtc != &crtc->base)  in intel_encoders_pre_enable()
1509 		if (encoder->pre_enable)  in intel_encoders_pre_enable()
1510 			encoder->pre_enable(state, encoder,  in intel_encoders_pre_enable()
1524 	for_each_new_connector_in_state(&state->base, conn, conn_state, i) {  in intel_encoders_enable()
1526 			to_intel_encoder(conn_state->best_encoder);  in intel_encoders_enable()
1528 		if (conn_state->crtc != &crtc->base)  in intel_encoders_enable()
1531 		if (encoder->enable)  in intel_encoders_enable()
1532 			encoder->enable(state, encoder,  in intel_encoders_enable()
1547 	for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {  in intel_encoders_disable()
1549 			to_intel_encoder(old_conn_state->best_encoder);  in intel_encoders_disable()
1551 		if (old_conn_state->crtc != &crtc->base)  in intel_encoders_disable()
1555 		if (encoder->disable)  in intel_encoders_disable()
1556 			encoder->disable(state, encoder,  in intel_encoders_disable()
1570 	for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {  in intel_encoders_post_disable()
1572 			to_intel_encoder(old_conn_state->best_encoder);  in intel_encoders_post_disable()
1574 		if (old_conn_state->crtc != &crtc->base)  in intel_encoders_post_disable()
1577 		if (encoder->post_disable)  in intel_encoders_post_disable()
1578 			encoder->post_disable(state, encoder,  in intel_encoders_post_disable()
1592 	for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {  in intel_encoders_post_pll_disable()
1594 			to_intel_encoder(old_conn_state->best_encoder);  in intel_encoders_post_pll_disable()
1596 		if (old_conn_state->crtc != &crtc->base)  in intel_encoders_post_pll_disable()
1599 		if (encoder->post_pll_disable)  in intel_encoders_post_pll_disable()
1600 			encoder->post_pll_disable(state, encoder,  in intel_encoders_post_pll_disable()
1614 	for_each_new_connector_in_state(&state->base, conn, conn_state, i) {  in intel_encoders_update_pipe()
1616 			to_intel_encoder(conn_state->best_encoder);  in intel_encoders_update_pipe()
1618 		if (conn_state->crtc != &crtc->base)  in intel_encoders_update_pipe()
1621 		if (encoder->update_pipe)  in intel_encoders_update_pipe()
1622 			encoder->update_pipe(state, encoder,  in intel_encoders_update_pipe()
1629 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in ilk_configure_cpu_transcoder()
1630 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;  in ilk_configure_cpu_transcoder()
1632 	if (crtc_state->has_pch_encoder) {  in ilk_configure_cpu_transcoder()
1634 					       &crtc_state->fdi_m_n);  in ilk_configure_cpu_transcoder()
1637 					       &crtc_state->dp_m_n);  in ilk_configure_cpu_transcoder()
1639 					       &crtc_state->dp_m2_n2);  in ilk_configure_cpu_transcoder()
1652 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in ilk_crtc_enable()
1653 	enum pipe pipe = crtc->pipe;  in ilk_crtc_enable()
1655 	if (drm_WARN_ON(&dev_priv->drm, crtc->active))  in ilk_crtc_enable()
1675 	crtc->active = true;  in ilk_crtc_enable()
1679 	if (new_crtc_state->has_pch_encoder) {  in ilk_crtc_enable()
1697 	if (new_crtc_state->has_pch_encoder)  in ilk_crtc_enable()
1713 	if (new_crtc_state->has_pch_encoder) {  in ilk_crtc_enable()
1724 	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);  in glk_need_scaler_clock_gating_wa()
1726 	return DISPLAY_VER(i915) == 10 && crtc_state->pch_pfit.enabled;  in glk_need_scaler_clock_gating_wa()
1731 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);  in glk_pipe_scaler_clock_gating_wa()
1734 	intel_de_rmw(i915, CLKGATE_DIS_PSL(crtc->pipe),  in glk_pipe_scaler_clock_gating_wa()
1740 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in hsw_set_linetime_wm()
1741 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in hsw_set_linetime_wm()
1743 	intel_de_write(dev_priv, WM_LINETIME(crtc->pipe),  in hsw_set_linetime_wm()
1744 		       HSW_LINETIME(crtc_state->linetime) |  in hsw_set_linetime_wm()
1745 		       HSW_IPS_LINETIME(crtc_state->ips_linetime));  in hsw_set_linetime_wm()
1752 	intel_de_rmw(display, CHICKEN_TRANS(display, crtc_state->cpu_transcoder),  in hsw_set_frame_start_delay()
1754 		     HSW_FRAME_START_DELAY(crtc_state->framestart_delay - 1));  in hsw_set_frame_start_delay()
1759 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in hsw_configure_cpu_transcoder()
1760 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in hsw_configure_cpu_transcoder()
1761 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;  in hsw_configure_cpu_transcoder()
1763 	if (crtc_state->has_pch_encoder) {  in hsw_configure_cpu_transcoder()
1765 					       &crtc_state->fdi_m_n);  in hsw_configure_cpu_transcoder()
1768 					       &crtc_state->dp_m_n);  in hsw_configure_cpu_transcoder()
1770 					       &crtc_state->dp_m2_n2);  in hsw_configure_cpu_transcoder()
1779 			       crtc_state->pixel_multiplier - 1);  in hsw_configure_cpu_transcoder()
1792 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in hsw_crtc_enable()
1793 	enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;  in hsw_crtc_enable()
1797 	if (drm_WARN_ON(&dev_priv->drm, crtc->active))  in hsw_crtc_enable()
1800 		intel_dmc_enable_pipe(display, pipe_crtc->pipe);  in hsw_crtc_enable()
1808 		if (pipe_crtc_state->shared_dpll)  in hsw_crtc_enable()
1836 		pipe_crtc->active = true;  in hsw_crtc_enable()
1876 		hsw_workaround_pipe = pipe_crtc_state->hsw_workaround_pipe;  in hsw_crtc_enable()
1889 	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);  in ilk_pfit_disable()
1890 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in ilk_pfit_disable()
1891 	enum pipe pipe = crtc->pipe;  in ilk_pfit_disable()
1895 	if (!old_crtc_state->pch_pfit.enabled)  in ilk_pfit_disable()
1908 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in ilk_crtc_disable()
1909 	enum pipe pipe = crtc->pipe;  in ilk_crtc_disable()
1927 	if (old_crtc_state->has_pch_encoder)  in ilk_crtc_disable()
1932 	if (old_crtc_state->has_pch_encoder)  in ilk_crtc_disable()
1952 	 * Need care with mst->ddi interactions.  in hsw_crtc_disable()
1967 		intel_dmc_disable_pipe(display, pipe_crtc->pipe);  in hsw_crtc_disable()
1972 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in i9xx_pfit_enable()
1973 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in i9xx_pfit_enable()
1975 	if (!crtc_state->gmch_pfit.control)  in i9xx_pfit_enable()
1982 	drm_WARN_ON(&dev_priv->drm,  in i9xx_pfit_enable()
1984 	assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);  in i9xx_pfit_enable()
1987 		       crtc_state->gmch_pfit.pgm_ratios);  in i9xx_pfit_enable()
1989 		       crtc_state->gmch_pfit.control);  in i9xx_pfit_enable()
1993 	intel_de_write(dev_priv, BCLRPAT(dev_priv, crtc->pipe), 0);  in i9xx_pfit_enable()
2023 	 * subsystem Legacy or non-legacy, and only support native DP/HDMI  in intel_phy_is_tc()
2052 		return PHY_D + port - PORT_D_XELPD;  in intel_port_to_phy()
2054 		return PHY_F + port - PORT_TC1;  in intel_port_to_phy()
2056 		return PHY_B + port - PORT_TC1;  in intel_port_to_phy()
2058 		return PHY_C + port - PORT_TC1;  in intel_port_to_phy()
2063 	return PHY_A + port - PORT_A;  in intel_port_to_phy()
2073 		return TC_PORT_1 + port - PORT_TC1;  in intel_port_to_tc()
2075 		return TC_PORT_1 + port - PORT_C;  in intel_port_to_tc()
2080 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);  in intel_encoder_to_phy()
2082 	return intel_port_to_phy(i915, encoder->port);  in intel_encoder_to_phy()
2087 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);  in intel_encoder_is_combo()
2094 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);  in intel_encoder_is_snps()
2101 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);  in intel_encoder_is_tc()
2108 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);  in intel_encoder_to_tc()
2110 	return intel_port_to_tc(i915, encoder->port);  in intel_encoder_to_tc()
2116 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);  in intel_aux_power_domain()
2119 		return intel_display_power_tbt_aux_domain(i915, dig_port->aux_ch);  in intel_aux_power_domain()
2121 	return intel_display_power_legacy_aux_domain(i915, dig_port->aux_ch);  in intel_aux_power_domain()
2127 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in get_crtc_power_domains()
2128 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in get_crtc_power_domains()
2129 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;  in get_crtc_power_domains()
2131 	enum pipe pipe = crtc->pipe;  in get_crtc_power_domains()
2133 	bitmap_zero(mask->bits, POWER_DOMAIN_NUM);  in get_crtc_power_domains()
2135 	if (!crtc_state->hw.active)  in get_crtc_power_domains()
2138 	set_bit(POWER_DOMAIN_PIPE(pipe), mask->bits);  in get_crtc_power_domains()
2139 	set_bit(POWER_DOMAIN_TRANSCODER(cpu_transcoder), mask->bits);  in get_crtc_power_domains()
2140 	if (crtc_state->pch_pfit.enabled ||  in get_crtc_power_domains()
2141 	    crtc_state->pch_pfit.force_thru)  in get_crtc_power_domains()
2142 		set_bit(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe), mask->bits);  in get_crtc_power_domains()
2144 	drm_for_each_encoder_mask(encoder, &dev_priv->drm,  in get_crtc_power_domains()
2145 				  crtc_state->uapi.encoder_mask) {  in get_crtc_power_domains()
2148 		set_bit(intel_encoder->power_domain, mask->bits);  in get_crtc_power_domains()
2151 	if (HAS_DDI(dev_priv) && crtc_state->has_audio)  in get_crtc_power_domains()
2152 		set_bit(POWER_DOMAIN_AUDIO_MMIO, mask->bits);  in get_crtc_power_domains()
2154 	if (crtc_state->shared_dpll)  in get_crtc_power_domains()
2155 		set_bit(POWER_DOMAIN_DISPLAY_CORE, mask->bits);  in get_crtc_power_domains()
2157 	if (crtc_state->dsc.compression_enable)  in get_crtc_power_domains()
2158 		set_bit(intel_dsc_power_domain(crtc, cpu_transcoder), mask->bits);  in get_crtc_power_domains()
2164 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_modeset_get_crtc_power_domains()
2165 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_modeset_get_crtc_power_domains()
2173 		      crtc->enabled_power_domains.mask.bits,  in intel_modeset_get_crtc_power_domains()
2175 	bitmap_andnot(old_domains->bits,  in intel_modeset_get_crtc_power_domains()
2176 		      crtc->enabled_power_domains.mask.bits,  in intel_modeset_get_crtc_power_domains()
2182 					       &crtc->enabled_power_domains,  in intel_modeset_get_crtc_power_domains()
2189 	intel_display_power_put_mask_in_set(to_i915(crtc->base.dev),  in intel_modeset_put_crtc_power_domains()
2190 					    &crtc->enabled_power_domains,  in intel_modeset_put_crtc_power_domains()
2196 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in i9xx_configure_cpu_transcoder()
2197 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;  in i9xx_configure_cpu_transcoder()
2201 					       &crtc_state->dp_m_n);  in i9xx_configure_cpu_transcoder()
2203 					       &crtc_state->dp_m2_n2);  in i9xx_configure_cpu_transcoder()
2216 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in valleyview_crtc_enable()
2217 	enum pipe pipe = crtc->pipe;  in valleyview_crtc_enable()
2219 	if (drm_WARN_ON(&dev_priv->drm, crtc->active))  in valleyview_crtc_enable()
2234 	crtc->active = true;  in valleyview_crtc_enable()
2264 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in i9xx_crtc_enable()
2265 	enum pipe pipe = crtc->pipe;  in i9xx_crtc_enable()
2267 	if (drm_WARN_ON(&dev_priv->drm, crtc->active))  in i9xx_crtc_enable()
2274 	crtc->active = true;  in i9xx_crtc_enable()
2302 	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);  in i9xx_pfit_disable()
2303 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in i9xx_pfit_disable()
2305 	if (!old_crtc_state->gmch_pfit.control)  in i9xx_pfit_disable()
2308 	assert_transcoder_disabled(dev_priv, old_crtc_state->cpu_transcoder);  in i9xx_pfit_disable()
2310 	drm_dbg_kms(&dev_priv->drm, "disabling pfit, current: 0x%08x\n",  in i9xx_pfit_disable()
2319 	struct drm_i915_private *dev_priv = to_i915(display->drm);  in i9xx_crtc_disable()
2322 	enum pipe pipe = crtc->pipe;  in i9xx_crtc_disable()
2355 	if (!dev_priv->display.funcs.wm->initial_watermarks)  in i9xx_crtc_disable()
2373 	const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_crtc_supports_double_wide()
2377 		(crtc->pipe == PIPE_A || IS_I915G(dev_priv));  in intel_crtc_supports_double_wide()
2382 	u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock;  in ilk_pipe_pixel_rate()
2386 	 * We only use IF-ID interlacing. If we ever use  in ilk_pipe_pixel_rate()
2387 	 * PF-ID we'll need to adjust the pixel_rate here.  in ilk_pipe_pixel_rate()
2390 	if (!crtc_state->pch_pfit.enabled)  in ilk_pipe_pixel_rate()
2394 		      drm_rect_width(&crtc_state->pipe_src) << 16,  in ilk_pipe_pixel_rate()
2395 		      drm_rect_height(&crtc_state->pipe_src) << 16);  in ilk_pipe_pixel_rate()
2397 	return intel_adjusted_rate(&src, &crtc_state->pch_pfit.dst,  in ilk_pipe_pixel_rate()
2404 	mode->hdisplay = timings->crtc_hdisplay;  in intel_mode_from_crtc_timings()
2405 	mode->htotal = timings->crtc_htotal;  in intel_mode_from_crtc_timings()
2406 	mode->hsync_start = timings->crtc_hsync_start;  in intel_mode_from_crtc_timings()
2407 	mode->hsync_end = timings->crtc_hsync_end;  in intel_mode_from_crtc_timings()
2409 	mode->vdisplay = timings->crtc_vdisplay;  in intel_mode_from_crtc_timings()
2410 	mode->vtotal = timings->crtc_vtotal;  in intel_mode_from_crtc_timings()
2411 	mode->vsync_start = timings->crtc_vsync_start;  in intel_mode_from_crtc_timings()
2412 	mode->vsync_end = timings->crtc_vsync_end;  in intel_mode_from_crtc_timings()
2414 	mode->flags = timings->flags;  in intel_mode_from_crtc_timings()
2415 	mode->type = DRM_MODE_TYPE_DRIVER;  in intel_mode_from_crtc_timings()
2417 	mode->clock = timings->crtc_clock;  in intel_mode_from_crtc_timings()
2424 	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);  in intel_crtc_compute_pixel_rate()
2428 		crtc_state->pixel_rate =  in intel_crtc_compute_pixel_rate()
2429 			crtc_state->hw.pipe_mode.crtc_clock;  in intel_crtc_compute_pixel_rate()
2431 		crtc_state->pixel_rate =  in intel_crtc_compute_pixel_rate()
2443 	mode->crtc_clock /= num_pipes;  in intel_joiner_adjust_timings()
2444 	mode->crtc_hdisplay /= num_pipes;  in intel_joiner_adjust_timings()
2445 	mode->crtc_hblank_start /= num_pipes;  in intel_joiner_adjust_timings()
2446 	mode->crtc_hblank_end /= num_pipes;  in intel_joiner_adjust_timings()
2447 	mode->crtc_hsync_start /= num_pipes;  in intel_joiner_adjust_timings()
2448 	mode->crtc_hsync_end /= num_pipes;  in intel_joiner_adjust_timings()
2449 	mode->crtc_htotal /= num_pipes;  in intel_joiner_adjust_timings()
2455 	int overlap = crtc_state->splitter.pixel_overlap;  in intel_splitter_adjust_timings()
2456 	int n = crtc_state->splitter.link_count;  in intel_splitter_adjust_timings()
2458 	if (!crtc_state->splitter.enable)  in intel_splitter_adjust_timings()
2465 	 * h_full = (h_segment - pixel_overlap) * link_count  in intel_splitter_adjust_timings()
2467 	mode->crtc_hdisplay = (mode->crtc_hdisplay - overlap) * n;  in intel_splitter_adjust_timings()
2468 	mode->crtc_hblank_start = (mode->crtc_hblank_start - overlap) * n;  in intel_splitter_adjust_timings()
2469 	mode->crtc_hblank_end = (mode->crtc_hblank_end - overlap) * n;  in intel_splitter_adjust_timings()
2470 	mode->crtc_hsync_start = (mode->crtc_hsync_start - overlap) * n;  in intel_splitter_adjust_timings()
2471 	mode->crtc_hsync_end = (mode->crtc_hsync_end - overlap) * n;  in intel_splitter_adjust_timings()
2472 	mode->crtc_htotal = (mode->crtc_htotal - overlap) * n;  in intel_splitter_adjust_timings()
2473 	mode->crtc_clock *= n;  in intel_splitter_adjust_timings()
2478 	struct drm_display_mode *mode = &crtc_state->hw.mode;  in intel_crtc_readout_derived_state()
2479 	struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;  in intel_crtc_readout_derived_state()
2480 	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;  in intel_crtc_readout_derived_state()
2488 	/* Expand MSO per-segment transcoder timings to full */  in intel_crtc_readout_derived_state()
2501 	mode->hdisplay = drm_rect_width(&crtc_state->pipe_src) *  in intel_crtc_readout_derived_state()
2503 	mode->vdisplay = drm_rect_height(&crtc_state->pipe_src);  in intel_crtc_readout_derived_state()
2505 	/* Derive per-pipe timings in case joiner is used */  in intel_crtc_readout_derived_state()
2515 	encoder->get_config(encoder, crtc_state);  in intel_encoder_get_config()
2528 	width = drm_rect_width(&crtc_state->pipe_src);  in intel_joiner_compute_pipe_src()
2529 	height = drm_rect_height(&crtc_state->pipe_src);  in intel_joiner_compute_pipe_src()
2531 	drm_rect_init(&crtc_state->pipe_src, 0, 0,  in intel_joiner_compute_pipe_src()
2537 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_crtc_compute_pipe_src()
2538 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);  in intel_crtc_compute_pipe_src()
2544 	 * - DVO ganged mode  in intel_crtc_compute_pipe_src()
2545 	 * - LVDS dual channel mode  in intel_crtc_compute_pipe_src()
2546 	 * - Double wide pipe  in intel_crtc_compute_pipe_src()
2548 	if (drm_rect_width(&crtc_state->pipe_src) & 1) {  in intel_crtc_compute_pipe_src()
2549 		if (crtc_state->double_wide) {  in intel_crtc_compute_pipe_src()
2550 			drm_dbg_kms(&i915->drm,  in intel_crtc_compute_pipe_src()
2552 				    crtc->base.base.id, crtc->base.name);  in intel_crtc_compute_pipe_src()
2553 			return -EINVAL;  in intel_crtc_compute_pipe_src()
2558 			drm_dbg_kms(&i915->drm,  in intel_crtc_compute_pipe_src()
2560 				    crtc->base.base.id, crtc->base.name);  in intel_crtc_compute_pipe_src()
2561 			return -EINVAL;  in intel_crtc_compute_pipe_src()
2570 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_crtc_compute_pipe_mode()
2571 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);  in intel_crtc_compute_pipe_mode()
2572 	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;  in intel_crtc_compute_pipe_mode()
2573 	struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;  in intel_crtc_compute_pipe_mode()
2574 	int clock_limit = i915->display.cdclk.max_dotclk_freq;  in intel_crtc_compute_pipe_mode()
2582 	/* Expand MSO per-segment transcoder timings to full */  in intel_crtc_compute_pipe_mode()
2585 	/* Derive per-pipe timings in case joiner is used */  in intel_crtc_compute_pipe_mode()
2590 		clock_limit = i915->display.cdclk.max_cdclk_freq * 9 / 10;  in intel_crtc_compute_pipe_mode()
2597 		    pipe_mode->crtc_clock > clock_limit) {  in intel_crtc_compute_pipe_mode()
2598 			clock_limit = i915->display.cdclk.max_dotclk_freq;  in intel_crtc_compute_pipe_mode()
2599 			crtc_state->double_wide = true;  in intel_crtc_compute_pipe_mode()
2603 	if (pipe_mode->crtc_clock > clock_limit) {  in intel_crtc_compute_pipe_mode()
2604 		drm_dbg_kms(&i915->drm,  in intel_crtc_compute_pipe_mode()
2606 			    crtc->base.base.id, crtc->base.name,  in intel_crtc_compute_pipe_mode()
2607 			    pipe_mode->crtc_clock, clock_limit,  in intel_crtc_compute_pipe_mode()
2608 			    str_yes_no(crtc_state->double_wide));  in intel_crtc_compute_pipe_mode()
2609 		return -EINVAL;  in intel_crtc_compute_pipe_mode()
2618 	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;  in intel_crtc_needs_wa_14015401596()
2620 	return intel_vrr_possible(crtc_state) && crtc_state->has_psr &&  in intel_crtc_needs_wa_14015401596()
2621 		adjusted_mode->crtc_vblank_start == adjusted_mode->crtc_vdisplay &&  in intel_crtc_needs_wa_14015401596()
2631 		&crtc_state->hw.adjusted_mode;  in intel_crtc_compute_config()
2636 		adjusted_mode->crtc_vblank_start += 1;  in intel_crtc_compute_config()
2652 	if (crtc_state->has_pch_encoder)  in intel_crtc_compute_config()
2698 	m_n->tu = 64;  in intel_link_compute_m_n()
2699 	compute_m_n(&m_n->data_m, &m_n->data_n,  in intel_link_compute_m_n()
2703 	compute_m_n(&m_n->link_m, &m_n->link_n,  in intel_link_compute_m_n()
2721 		if (dev_priv->display.vbt.lvds_use_ssc != bios_lvds_use_ssc) {  in intel_panel_sanitize_ssc()
2722 			drm_dbg_kms(&dev_priv->drm,  in intel_panel_sanitize_ssc()
2725 				    str_enabled_disabled(dev_priv->display.vbt.lvds_use_ssc));  in intel_panel_sanitize_ssc()
2726 			dev_priv->display.vbt.lvds_use_ssc = bios_lvds_use_ssc;  in intel_panel_sanitize_ssc()
2735 	m_n->tu = 1;  in intel_zero_m_n()
2743 	intel_de_write(i915, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m);  in intel_set_m_n()
2744 	intel_de_write(i915, data_n_reg, m_n->data_n);  in intel_set_m_n()
2745 	intel_de_write(i915, link_m_reg, m_n->link_m);  in intel_set_m_n()
2750 	intel_de_write(i915, link_n_reg, m_n->link_n);  in intel_set_m_n()
2766 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_cpu_transcoder_set_m1_n1()
2767 	enum pipe pipe = crtc->pipe;  in intel_cpu_transcoder_set_m1_n1()
2785 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_cpu_transcoder_set_m2_n2()
2799 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_set_transcoder_timings()
2800 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_set_transcoder_timings()
2801 	enum pipe pipe = crtc->pipe;  in intel_set_transcoder_timings()
2802 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;  in intel_set_transcoder_timings()
2803 	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;  in intel_set_transcoder_timings()
2809 	crtc_vdisplay = adjusted_mode->crtc_vdisplay;  in intel_set_transcoder_timings()
2810 	crtc_vtotal = adjusted_mode->crtc_vtotal;  in intel_set_transcoder_timings()
2811 	crtc_vblank_start = adjusted_mode->crtc_vblank_start;  in intel_set_transcoder_timings()
2812 	crtc_vblank_end = adjusted_mode->crtc_vblank_end;  in intel_set_transcoder_timings()
2814 	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {  in intel_set_transcoder_timings()
2816 		crtc_vtotal -= 1;  in intel_set_transcoder_timings()
2817 		crtc_vblank_end -= 1;  in intel_set_transcoder_timings()
2820 			vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;  in intel_set_transcoder_timings()
2822 			vsyncshift = adjusted_mode->crtc_hsync_start -  in intel_set_transcoder_timings()
2823 				adjusted_mode->crtc_htotal / 2;  in intel_set_transcoder_timings()
2825 			vsyncshift += adjusted_mode->crtc_htotal;  in intel_set_transcoder_timings()
2835 			       crtc_vblank_start - crtc_vdisplay);  in intel_set_transcoder_timings()
2850 		       HACTIVE(adjusted_mode->crtc_hdisplay - 1) |  in intel_set_transcoder_timings()
2851 		       HTOTAL(adjusted_mode->crtc_htotal - 1));  in intel_set_transcoder_timings()
2853 		       HBLANK_START(adjusted_mode->crtc_hblank_start - 1) |  in intel_set_transcoder_timings()
2854 		       HBLANK_END(adjusted_mode->crtc_hblank_end - 1));  in intel_set_transcoder_timings()
2856 		       HSYNC_START(adjusted_mode->crtc_hsync_start - 1) |  in intel_set_transcoder_timings()
2857 		       HSYNC_END(adjusted_mode->crtc_hsync_end - 1));  in intel_set_transcoder_timings()
2860 		       VACTIVE(crtc_vdisplay - 1) |  in intel_set_transcoder_timings()
2861 		       VTOTAL(crtc_vtotal - 1));  in intel_set_transcoder_timings()
2863 		       VBLANK_START(crtc_vblank_start - 1) |  in intel_set_transcoder_timings()
2864 		       VBLANK_END(crtc_vblank_end - 1));  in intel_set_transcoder_timings()
2866 		       VSYNC_START(adjusted_mode->crtc_vsync_start - 1) |  in intel_set_transcoder_timings()
2867 		       VSYNC_END(adjusted_mode->crtc_vsync_end - 1));  in intel_set_transcoder_timings()
2876 			       VACTIVE(crtc_vdisplay - 1) |  in intel_set_transcoder_timings()
2877 			       VTOTAL(crtc_vtotal - 1));  in intel_set_transcoder_timings()
2882 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_set_transcoder_timings_lrr()
2883 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_set_transcoder_timings_lrr()
2884 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;  in intel_set_transcoder_timings_lrr()
2885 	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;  in intel_set_transcoder_timings_lrr()
2888 	crtc_vdisplay = adjusted_mode->crtc_vdisplay;  in intel_set_transcoder_timings_lrr()
2889 	crtc_vtotal = adjusted_mode->crtc_vtotal;  in intel_set_transcoder_timings_lrr()
2890 	crtc_vblank_start = adjusted_mode->crtc_vblank_start;  in intel_set_transcoder_timings_lrr()
2891 	crtc_vblank_end = adjusted_mode->crtc_vblank_end;  in intel_set_transcoder_timings_lrr()
2893 	drm_WARN_ON(&dev_priv->drm, adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE);  in intel_set_transcoder_timings_lrr()
2900 		       VBLANK_START(crtc_vblank_start - 1) |  in intel_set_transcoder_timings_lrr()
2901 		       VBLANK_END(crtc_vblank_end - 1));  in intel_set_transcoder_timings_lrr()
2907 		       VACTIVE(crtc_vdisplay - 1) |  in intel_set_transcoder_timings_lrr()
2908 		       VTOTAL(crtc_vtotal - 1));  in intel_set_transcoder_timings_lrr()
2913 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_set_pipe_src_size()
2914 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_set_pipe_src_size()
2915 	int width = drm_rect_width(&crtc_state->pipe_src);  in intel_set_pipe_src_size()
2916 	int height = drm_rect_height(&crtc_state->pipe_src);  in intel_set_pipe_src_size()
2917 	enum pipe pipe = crtc->pipe;  in intel_set_pipe_src_size()
2923 		       PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1));  in intel_set_pipe_src_size()
2928 	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);  in intel_pipe_is_interlaced()
2929 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;  in intel_pipe_is_interlaced()
2946 	struct drm_device *dev = crtc->base.dev;  in intel_get_transcoder_timings()
2948 	enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;  in intel_get_transcoder_timings()
2949 	struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;  in intel_get_transcoder_timings()
2953 	adjusted_mode->crtc_hdisplay = REG_FIELD_GET(HACTIVE_MASK, tmp) + 1;  in intel_get_transcoder_timings()
2954 	adjusted_mode->crtc_htotal = REG_FIELD_GET(HTOTAL_MASK, tmp) + 1;  in intel_get_transcoder_timings()
2959 		adjusted_mode->crtc_hblank_start = REG_FIELD_GET(HBLANK_START_MASK, tmp) + 1;  in intel_get_transcoder_timings()
2960 		adjusted_mode->crtc_hblank_end = REG_FIELD_GET(HBLANK_END_MASK, tmp) + 1;  in intel_get_transcoder_timings()
2964 	adjusted_mode->crtc_hsync_start = REG_FIELD_GET(HSYNC_START_MASK, tmp) + 1;  in intel_get_transcoder_timings()
2965 	adjusted_mode->crtc_hsync_end = REG_FIELD_GET(HSYNC_END_MASK, tmp) + 1;  in intel_get_transcoder_timings()
2968 	adjusted_mode->crtc_vdisplay = REG_FIELD_GET(VACTIVE_MASK, tmp) + 1;  in intel_get_transcoder_timings()
2969 	adjusted_mode->crtc_vtotal = REG_FIELD_GET(VTOTAL_MASK, tmp) + 1;  in intel_get_transcoder_timings()
2975 		adjusted_mode->crtc_vblank_start = REG_FIELD_GET(VBLANK_START_MASK, tmp) + 1;  in intel_get_transcoder_timings()
2976 		adjusted_mode->crtc_vblank_end = REG_FIELD_GET(VBLANK_END_MASK, tmp) + 1;  in intel_get_transcoder_timings()
2979 	adjusted_mode->crtc_vsync_start = REG_FIELD_GET(VSYNC_START_MASK, tmp) + 1;  in intel_get_transcoder_timings()
2980 	adjusted_mode->crtc_vsync_end = REG_FIELD_GET(VSYNC_END_MASK, tmp) + 1;  in intel_get_transcoder_timings()
2983 		adjusted_mode->flags |= DRM_MODE_FLAG_INTERLACE;  in intel_get_transcoder_timings()
2984 		adjusted_mode->crtc_vtotal += 1;  in intel_get_transcoder_timings()
2985 		adjusted_mode->crtc_vblank_end += 1;  in intel_get_transcoder_timings()
2989 		adjusted_mode->crtc_vblank_start =  in intel_get_transcoder_timings()
2990 			adjusted_mode->crtc_vdisplay +  in intel_get_transcoder_timings()
2997 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_joiner_adjust_pipe_src()
2999 	enum pipe primary_pipe, pipe = crtc->pipe;  in intel_joiner_adjust_pipe_src()
3006 	width = drm_rect_width(&crtc_state->pipe_src);  in intel_joiner_adjust_pipe_src()
3008 	drm_rect_translate_to(&crtc_state->pipe_src,  in intel_joiner_adjust_pipe_src()
3009 			      (pipe - primary_pipe) * width, 0);  in intel_joiner_adjust_pipe_src()
3015 	struct drm_device *dev = crtc->base.dev;  in intel_get_pipe_src_size()
3019 	tmp = intel_de_read(dev_priv, PIPESRC(dev_priv, crtc->pipe));  in intel_get_pipe_src_size()
3021 	drm_rect_init(&pipe_config->pipe_src, 0, 0,  in intel_get_pipe_src_size()
3030 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in i9xx_set_pipeconf()
3031 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in i9xx_set_pipeconf()
3032 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;  in i9xx_set_pipeconf()
3036 	 * - We keep both pipes enabled on 830  in i9xx_set_pipeconf()
3037 	 * - During modeset the pipe is still disabled and must remain so  in i9xx_set_pipeconf()
3038 	 * - During fastset the pipe is already enabled and must remain so  in i9xx_set_pipeconf()
3043 	if (crtc_state->double_wide)  in i9xx_set_pipeconf()
3050 		if (crtc_state->dither && crtc_state->pipe_bpp != 30)  in i9xx_set_pipeconf()
3054 		switch (crtc_state->pipe_bpp) {  in i9xx_set_pipeconf()
3057 			MISSING_CASE(crtc_state->pipe_bpp);  in i9xx_set_pipeconf()
3071 	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {  in i9xx_set_pipeconf()
3082 	     crtc_state->limited_color_range)  in i9xx_set_pipeconf()
3085 	val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode);  in i9xx_set_pipeconf()
3087 	if (crtc_state->wgc_enable)  in i9xx_set_pipeconf()
3090 	val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1);  in i9xx_set_pipeconf()
3107 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in i9xx_get_pfit_config()
3108 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in i9xx_get_pfit_config()
3125 	if (pipe != crtc->pipe)  in i9xx_get_pfit_config()
3128 	crtc_state->gmch_pfit.control = tmp;  in i9xx_get_pfit_config()
3129 	crtc_state->gmch_pfit.pgm_ratios =  in i9xx_get_pfit_config()
3136 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in bdw_get_pipe_misc_output_format()
3139 	tmp = intel_de_read(dev_priv, PIPE_MISC(crtc->pipe));  in bdw_get_pipe_misc_output_format()
3148 			drm_WARN_ON(&dev_priv->drm,  in bdw_get_pipe_misc_output_format()
3162 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in i9xx_get_pipe_config()
3168 	power_domain = POWER_DOMAIN_PIPE(crtc->pipe);  in i9xx_get_pipe_config()
3173 	pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;  in i9xx_get_pipe_config()
3174 	pipe_config->sink_format = pipe_config->output_format;  in i9xx_get_pipe_config()
3175 	pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;  in i9xx_get_pipe_config()
3176 	pipe_config->shared_dpll = NULL;  in i9xx_get_pipe_config()
3181 			    TRANSCONF(dev_priv, pipe_config->cpu_transcoder));  in i9xx_get_pipe_config()
3189 			pipe_config->pipe_bpp = 18;  in i9xx_get_pipe_config()
3192 			pipe_config->pipe_bpp = 24;  in i9xx_get_pipe_config()
3195 			pipe_config->pipe_bpp = 30;  in i9xx_get_pipe_config()
3205 		pipe_config->limited_color_range = true;  in i9xx_get_pipe_config()
3207 	pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_I9XX, tmp);  in i9xx_get_pipe_config()
3209 	pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1;  in i9xx_get_pipe_config()
3213 		pipe_config->wgc_enable = true;  in i9xx_get_pipe_config()
3218 		pipe_config->double_wide = tmp & TRANSCONF_DOUBLE_WIDE;  in i9xx_get_pipe_config()
3225 	i9xx_dpll_get_hw_state(crtc, &pipe_config->dpll_hw_state);  in i9xx_get_pipe_config()
3228 		tmp = pipe_config->dpll_hw_state.i9xx.dpll_md;  in i9xx_get_pipe_config()
3229 		pipe_config->pixel_multiplier =  in i9xx_get_pipe_config()
3234 		tmp = pipe_config->dpll_hw_state.i9xx.dpll;  in i9xx_get_pipe_config()
3235 		pipe_config->pixel_multiplier =  in i9xx_get_pipe_config()
3240 		 * port and will be fixed up in the encoder->get_config  in i9xx_get_pipe_config()
3242 		pipe_config->pixel_multiplier = 1;  in i9xx_get_pipe_config()
3257 	pipe_config->hw.adjusted_mode.crtc_clock =  in i9xx_get_pipe_config()
3258 		pipe_config->port_clock / pipe_config->pixel_multiplier;  in i9xx_get_pipe_config()
3270 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in ilk_set_pipeconf()
3271 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in ilk_set_pipeconf()
3272 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;  in ilk_set_pipeconf()
3276 	 * - During modeset the pipe is still disabled and must remain so  in ilk_set_pipeconf()
3277 	 * - During fastset the pipe is already enabled and must remain so  in ilk_set_pipeconf()
3282 	switch (crtc_state->pipe_bpp) {  in ilk_set_pipeconf()
3285 		MISSING_CASE(crtc_state->pipe_bpp);  in ilk_set_pipeconf()
3301 	if (crtc_state->dither)  in ilk_set_pipeconf()
3304 	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)  in ilk_set_pipeconf()
3313 	drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range &&  in ilk_set_pipeconf()
3314 		    crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);  in ilk_set_pipeconf()
3316 	if (crtc_state->limited_color_range &&  in ilk_set_pipeconf()
3320 	if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)  in ilk_set_pipeconf()
3323 	val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode);  in ilk_set_pipeconf()
3325 	val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1);  in ilk_set_pipeconf()
3326 	val |= TRANSCONF_MSA_TIMING_DELAY(crtc_state->msa_timing_delay);  in ilk_set_pipeconf()
3334 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in hsw_set_transconf()
3335 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in hsw_set_transconf()
3336 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;  in hsw_set_transconf()
3340 	 * - During modeset the pipe is still disabled and must remain so  in hsw_set_transconf()
3341 	 * - During fastset the pipe is already enabled and must remain so  in hsw_set_transconf()
3346 	if (IS_HASWELL(dev_priv) && crtc_state->dither)  in hsw_set_transconf()
3349 	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)  in hsw_set_transconf()
3355 	    crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)  in hsw_set_transconf()
3365 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in bdw_set_pipe_misc()
3366 	struct intel_display *display = to_intel_display(crtc->base.dev);  in bdw_set_pipe_misc()
3367 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in bdw_set_pipe_misc()
3370 	switch (crtc_state->pipe_bpp) {  in bdw_set_pipe_misc()
3386 		MISSING_CASE(crtc_state->pipe_bpp);  in bdw_set_pipe_misc()
3390 	if (crtc_state->dither)  in bdw_set_pipe_misc()
3393 	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||  in bdw_set_pipe_misc()
3394 	    crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)  in bdw_set_pipe_misc()
3397 	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)  in bdw_set_pipe_misc()
3411 	intel_de_write_dsb(display, dsb, PIPE_MISC(crtc->pipe), val);  in bdw_set_pipe_misc()
3416 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in bdw_get_pipe_misc_bpp()
3419 	tmp = intel_de_read(dev_priv, PIPE_MISC(crtc->pipe));  in bdw_get_pipe_misc_bpp()
3451 	 * Account for spread spectrum to avoid  in ilk_get_lanes_required()
3452 	 * oversubscribing the link. Max center spread  in ilk_get_lanes_required()
3464 	m_n->link_m = intel_de_read(i915, link_m_reg) & DATA_LINK_M_N_MASK;  in intel_get_m_n()
3465 	m_n->link_n = intel_de_read(i915, link_n_reg) & DATA_LINK_M_N_MASK;  in intel_get_m_n()
3466 	m_n->data_m = intel_de_read(i915, data_m_reg) & DATA_LINK_M_N_MASK;  in intel_get_m_n()
3467 	m_n->data_n = intel_de_read(i915, data_n_reg) & DATA_LINK_M_N_MASK;  in intel_get_m_n()
3468 	m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(i915, data_m_reg)) + 1;  in intel_get_m_n()
3475 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_cpu_transcoder_get_m1_n1()
3476 	enum pipe pipe = crtc->pipe;  in intel_cpu_transcoder_get_m1_n1()
3494 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_cpu_transcoder_get_m2_n2()
3508 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in ilk_get_pfit_config()
3509 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in ilk_get_pfit_config()
3513 	ctl = intel_de_read(dev_priv, PF_CTL(crtc->pipe));  in ilk_get_pfit_config()
3520 		pipe = crtc->pipe;  in ilk_get_pfit_config()
3522 	crtc_state->pch_pfit.enabled = true;  in ilk_get_pfit_config()
3524 	pos = intel_de_read(dev_priv, PF_WIN_POS(crtc->pipe));  in ilk_get_pfit_config()
3525 	size = intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe));  in ilk_get_pfit_config()
3527 	drm_rect_init(&crtc_state->pch_pfit.dst,  in ilk_get_pfit_config()
3538 	drm_WARN_ON(&dev_priv->drm, pipe != crtc->pipe);  in ilk_get_pfit_config()
3544 	struct drm_device *dev = crtc->base.dev;  in ilk_get_pipe_config()
3551 	power_domain = POWER_DOMAIN_PIPE(crtc->pipe);  in ilk_get_pipe_config()
3556 	pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;  in ilk_get_pipe_config()
3557 	pipe_config->shared_dpll = NULL;  in ilk_get_pipe_config()
3561 			    TRANSCONF(dev_priv, pipe_config->cpu_transcoder));  in ilk_get_pipe_config()
3567 		pipe_config->pipe_bpp = 18;  in ilk_get_pipe_config()
3570 		pipe_config->pipe_bpp = 24;  in ilk_get_pipe_config()
3573 		pipe_config->pipe_bpp = 30;  in ilk_get_pipe_config()
3576 		pipe_config->pipe_bpp = 36;  in ilk_get_pipe_config()
3583 		pipe_config->limited_color_range = true;  in ilk_get_pipe_config()
3588 		pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;  in ilk_get_pipe_config()
3591 		pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;  in ilk_get_pipe_config()
3595 	pipe_config->sink_format = pipe_config->output_format;  in ilk_get_pipe_config()
3597 	pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_ILK, tmp);  in ilk_get_pipe_config()
3599 	pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1;  in ilk_get_pipe_config()
3601 	pipe_config->msa_timing_delay = REG_FIELD_GET(TRANSCONF_MSA_TIMING_DELAY_MASK, tmp);  in ilk_get_pipe_config()
3605 	pipe_config->pixel_multiplier = 1;  in ilk_get_pipe_config()
3633 	return pipes & DISPLAY_RUNTIME_INFO(i915)->pipe_mask;  in joiner_pipes()
3655 	struct drm_i915_private *i915 = to_i915(display->drm);  in enabled_uncompressed_joiner_pipes()
3664 	for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc,  in enabled_uncompressed_joiner_pipes()
3667 		enum pipe pipe = crtc->pipe;  in enabled_uncompressed_joiner_pipes()
3685 	struct drm_i915_private *i915 = to_i915(display->drm);  in enabled_bigjoiner_pipes()
3694 	for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc,  in enabled_bigjoiner_pipes()
3697 		enum pipe pipe = crtc->pipe;  in enabled_bigjoiner_pipes()
3739 	return primary_pipes ? BIT(fls(primary_pipes) - 1) : 0;  in get_joiner_primary_pipe()
3756 	struct intel_display *display = &i915->display;  in enabled_ultrajoiner_pipes()
3765 	for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc,  in enabled_ultrajoiner_pipes()
3768 		enum pipe pipe = crtc->pipe;  in enabled_ultrajoiner_pipes()
3790 	struct intel_display *display = to_intel_display(&dev_priv->drm);  in enabled_joiner_pipes()
3805 	drm_WARN_ON(&dev_priv->drm,  in enabled_joiner_pipes()
3812 	drm_WARN_ON(&dev_priv->drm, (primary_ultrajoiner_pipes & secondary_ultrajoiner_pipes) != 0);  in enabled_joiner_pipes()
3817 	drm_WARN_ON(display->drm,  in enabled_joiner_pipes()
3823 	drm_WARN_ON(display->drm,  in enabled_joiner_pipes()
3831 	drm_WARN(display->drm, (ultrajoiner_pipes & bigjoiner_pipes) != ultrajoiner_pipes,  in enabled_joiner_pipes()
3835 	drm_WARN(display->drm, secondary_ultrajoiner_pipes !=  in enabled_joiner_pipes()
3841 	drm_WARN(display->drm, (uncompressed_joiner_pipes & bigjoiner_pipes) != 0,  in enabled_joiner_pipes()
3845 	drm_WARN(display->drm, secondary_bigjoiner_pipes !=  in enabled_joiner_pipes()
3851 	drm_WARN(display->drm, secondary_uncompressed_joiner_pipes !=  in enabled_joiner_pipes()
3865 		drm_WARN(display->drm,  in enabled_joiner_pipes()
3880 		drm_WARN(display->drm,  in enabled_joiner_pipes()
3895 		drm_WARN(display->drm,  in enabled_joiner_pipes()
3918 	struct drm_device *dev = crtc->base.dev;  in hsw_enabled_transcoders()
3965 		if (trans_pipe == crtc->pipe)  in hsw_enabled_transcoders()
3970 	cpu_transcoder = (enum transcoder) crtc->pipe;  in hsw_enabled_transcoders()
3974 	/* joiner secondary -> consider the primary pipe's transcoder as well */  in hsw_enabled_transcoders()
3975 	enabled_joiner_pipes(dev_priv, crtc->pipe, &primary_pipe, &secondary_pipes);  in hsw_enabled_transcoders()
3976 	if (secondary_pipes & BIT(crtc->pipe)) {  in hsw_enabled_transcoders()
3977 		cpu_transcoder = (enum transcoder)ffs(primary_pipe) - 1;  in hsw_enabled_transcoders()
4007 	drm_WARN_ON(&i915->drm,  in assert_enabled_transcoders()
4013 	drm_WARN_ON(&i915->drm,  in assert_enabled_transcoders()
4022 	struct drm_device *dev = crtc->base.dev;  in hsw_get_transcoder_state()
4038 	pipe_config->cpu_transcoder = ffs(enabled_transcoders) - 1;  in hsw_get_transcoder_state()
4041 						       POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))  in hsw_get_transcoder_state()
4044 	if (hsw_panel_transcoders(dev_priv) & BIT(pipe_config->cpu_transcoder)) {  in hsw_get_transcoder_state()
4046 				    TRANS_DDI_FUNC_CTL(dev_priv, pipe_config->cpu_transcoder));  in hsw_get_transcoder_state()
4049 			pipe_config->pch_pfit.force_thru = true;  in hsw_get_transcoder_state()
4053 			    TRANSCONF(dev_priv, pipe_config->cpu_transcoder));  in hsw_get_transcoder_state()
4063 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in bxt_get_dsi_transcoder_state()
4094 		if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))  in bxt_get_dsi_transcoder_state()
4097 		pipe_config->cpu_transcoder = cpu_transcoder;  in bxt_get_dsi_transcoder_state()
4101 	return transcoder_is_dsi(pipe_config->cpu_transcoder);  in bxt_get_dsi_transcoder_state()
4106 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_joiner_get_config()
4107 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);  in intel_joiner_get_config()
4109 	enum pipe pipe = crtc->pipe;  in intel_joiner_get_config()
4116 	crtc_state->joiner_pipes = primary_pipe | secondary_pipes;  in intel_joiner_get_config()
4123 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in hsw_get_pipe_config()
4127 	if (!intel_display_power_get_in_set_if_enabled(dev_priv, &crtc->hw_readout_power_domains,  in hsw_get_pipe_config()
4128 						       POWER_DOMAIN_PIPE(crtc->pipe)))  in hsw_get_pipe_config()
4131 	pipe_config->shared_dpll = NULL;  in hsw_get_pipe_config()
4133 	active = hsw_get_transcoder_state(crtc, pipe_config, &crtc->hw_readout_power_domains);  in hsw_get_pipe_config()
4136 	    bxt_get_dsi_transcoder_state(crtc, pipe_config, &crtc->hw_readout_power_domains)) {  in hsw_get_pipe_config()
4137 		drm_WARN_ON(&dev_priv->drm, active);  in hsw_get_pipe_config()
4147 	if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||  in hsw_get_pipe_config()
4151 	if (HAS_VRR(dev_priv) && !transcoder_is_dsi(pipe_config->cpu_transcoder))  in hsw_get_pipe_config()
4158 					TRANSCONF(dev_priv, pipe_config->cpu_transcoder));  in hsw_get_pipe_config()
4161 			pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;  in hsw_get_pipe_config()
4163 			pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;  in hsw_get_pipe_config()
4165 		pipe_config->output_format =  in hsw_get_pipe_config()
4169 	pipe_config->sink_format = pipe_config->output_format;  in hsw_get_pipe_config()
4173 	tmp = intel_de_read(dev_priv, WM_LINETIME(crtc->pipe));  in hsw_get_pipe_config()
4174 	pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp);  in hsw_get_pipe_config()
4176 		pipe_config->ips_linetime =  in hsw_get_pipe_config()
4179 	if (intel_display_power_get_in_set_if_enabled(dev_priv, &crtc->hw_readout_power_domains,  in hsw_get_pipe_config()
4180 						      POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe))) {  in hsw_get_pipe_config()
4189 	if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&  in hsw_get_pipe_config()
4190 	    !transcoder_is_dsi(pipe_config->cpu_transcoder)) {  in hsw_get_pipe_config()
4191 		pipe_config->pixel_multiplier =  in hsw_get_pipe_config()
4193 				      TRANS_MULT(dev_priv, pipe_config->cpu_transcoder)) + 1;  in hsw_get_pipe_config()
4195 		pipe_config->pixel_multiplier = 1;  in hsw_get_pipe_config()
4198 	if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {  in hsw_get_pipe_config()
4199 		tmp = intel_de_read(display, CHICKEN_TRANS(display, pipe_config->cpu_transcoder));  in hsw_get_pipe_config()
4201 		pipe_config->framestart_delay = REG_FIELD_GET(HSW_FRAME_START_DELAY_MASK, tmp) + 1;  in hsw_get_pipe_config()
4204 		pipe_config->framestart_delay = 1;  in hsw_get_pipe_config()
4208 	intel_display_power_put_all_in_set(dev_priv, &crtc->hw_readout_power_domains);  in hsw_get_pipe_config()
4215 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_crtc_get_pipe_config()
4216 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);  in intel_crtc_get_pipe_config()
4218 	if (!i915->display.funcs.display->get_pipe_config(crtc, crtc_state))  in intel_crtc_get_pipe_config()
4221 	crtc_state->hw.active = true;  in intel_crtc_get_pipe_config()
4232 	 * The calculation for the data clock -> pixel clock is:  in intel_dotclock_calculate()
4237 	 * and for link freq (10kbs units) -> pixel clock it is:  in intel_dotclock_calculate()
4244 	if (!m_n->link_n)  in intel_dotclock_calculate()
4247 	return DIV_ROUND_UP_ULL(mul_u32_u32(m_n->link_m, link_freq * 10),  in intel_dotclock_calculate()
4248 				m_n->link_n * intel_dp_link_symbol_size(link_freq));  in intel_dotclock_calculate()
4256 		dotclock = intel_dotclock_calculate(pipe_config->port_clock,  in intel_crtc_dotclock()
4257 						    &pipe_config->dp_m_n);  in intel_crtc_dotclock()
4258 	else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24)  in intel_crtc_dotclock()
4259 		dotclock = DIV_ROUND_CLOSEST(pipe_config->port_clock * 24,  in intel_crtc_dotclock()
4260 					     pipe_config->pipe_bpp);  in intel_crtc_dotclock()
4262 		dotclock = pipe_config->port_clock;  in intel_crtc_dotclock()
4264 	if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&  in intel_crtc_dotclock()
4268 	if (pipe_config->pixel_multiplier)  in intel_crtc_dotclock()
4269 		dotclock /= pipe_config->pixel_multiplier;  in intel_crtc_dotclock()
4284 	if (!encoder->get_hw_state(encoder, &pipe))  in intel_encoder_current_mode()
4300 		intel_crtc_destroy_state(&crtc->base, &crtc_state->uapi);  in intel_encoder_current_mode()
4307 	intel_mode_from_crtc_timings(mode, &crtc_state->hw.adjusted_mode);  in intel_encoder_current_mode()
4309 	intel_crtc_destroy_state(&crtc->base, &crtc_state->uapi);  in intel_encoder_current_mode()
4318 	return a == b || (a->cloneable & BIT(b->type) &&  in encoders_cloneable()
4319 			  b->cloneable & BIT(a->type));  in encoders_cloneable()
4331 	for_each_new_connector_in_state(&state->base, connector, connector_state, i) {  in check_single_encoder_cloning()
4332 		if (connector_state->crtc != &crtc->base)  in check_single_encoder_cloning()
4336 			to_intel_encoder(connector_state->best_encoder);  in check_single_encoder_cloning()
4351 		linked = plane_state->planar_linked_plane;  in icl_add_linked_planes()
4360 		drm_WARN_ON(state->base.dev,  in icl_add_linked_planes()
4361 			    linked_plane_state->planar_linked_plane != plane);  in icl_add_linked_planes()
4362 		drm_WARN_ON(state->base.dev,  in icl_add_linked_planes()
4363 			    linked_plane_state->planar_slave == plane_state->planar_slave);  in icl_add_linked_planes()
4372 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);  in icl_check_nv12_planes()
4384 	 * in the crtc_state->active_planes mask.  in icl_check_nv12_planes()
4387 		if (plane->pipe != crtc->pipe || !plane_state->planar_linked_plane)  in icl_check_nv12_planes()
4390 		plane_state->planar_linked_plane = NULL;  in icl_check_nv12_planes()
4391 		if (plane_state->planar_slave && !plane_state->uapi.visible) {  in icl_check_nv12_planes()
4392 			crtc_state->enabled_planes &= ~BIT(plane->id);  in icl_check_nv12_planes()
4393 			crtc_state->active_planes &= ~BIT(plane->id);  in icl_check_nv12_planes()
4394 			crtc_state->update_planes |= BIT(plane->id);  in icl_check_nv12_planes()
4395 			crtc_state->data_rate[plane->id] = 0;  in icl_check_nv12_planes()
4396 			crtc_state->rel_data_rate[plane->id] = 0;  in icl_check_nv12_planes()
4399 		plane_state->planar_slave = false;  in icl_check_nv12_planes()
4402 	if (!crtc_state->nv12_planes)  in icl_check_nv12_planes()
4408 		if (plane->pipe != crtc->pipe ||  in icl_check_nv12_planes()
4409 		    !(crtc_state->nv12_planes & BIT(plane->id)))  in icl_check_nv12_planes()
4412 		for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) {  in icl_check_nv12_planes()
4413 			if (!icl_is_nv12_y_plane(dev_priv, linked->id))  in icl_check_nv12_planes()
4416 			if (crtc_state->active_planes & BIT(linked->id))  in icl_check_nv12_planes()
4427 			drm_dbg_kms(&dev_priv->drm,  in icl_check_nv12_planes()
4429 				    hweight8(crtc_state->nv12_planes));  in icl_check_nv12_planes()
4431 			return -EINVAL;  in icl_check_nv12_planes()
4434 		plane_state->planar_linked_plane = linked;  in icl_check_nv12_planes()
4436 		linked_state->planar_slave = true;  in icl_check_nv12_planes()
4437 		linked_state->planar_linked_plane = plane;  in icl_check_nv12_planes()
4438 		crtc_state->enabled_planes |= BIT(linked->id);  in icl_check_nv12_planes()
4439 		crtc_state->active_planes |= BIT(linked->id);  in icl_check_nv12_planes()
4440 		crtc_state->update_planes |= BIT(linked->id);  in icl_check_nv12_planes()
4441 		crtc_state->data_rate[linked->id] =  in icl_check_nv12_planes()
4442 			crtc_state->data_rate_y[plane->id];  in icl_check_nv12_planes()
4443 		crtc_state->rel_data_rate[linked->id] =  in icl_check_nv12_planes()
4444 			crtc_state->rel_data_rate_y[plane->id];  in icl_check_nv12_planes()
4445 		drm_dbg_kms(&dev_priv->drm, "Using %s as Y plane for %s\n",  in icl_check_nv12_planes()
4446 			    linked->base.name, plane->base.name);  in icl_check_nv12_planes()
4449 		linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE;  in icl_check_nv12_planes()
4450 		linked_state->color_ctl = plane_state->color_ctl;  in icl_check_nv12_planes()
4451 		linked_state->view = plane_state->view;  in icl_check_nv12_planes()
4452 		linked_state->decrypt = plane_state->decrypt;  in icl_check_nv12_planes()
4455 		linked_state->uapi.src = plane_state->uapi.src;  in icl_check_nv12_planes()
4456 		linked_state->uapi.dst = plane_state->uapi.dst;  in icl_check_nv12_planes()
4458 		if (icl_is_hdr_plane(dev_priv, plane->id)) {  in icl_check_nv12_planes()
4459 			if (linked->id == PLANE_7)  in icl_check_nv12_planes()
4460 				plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_7_ICL;  in icl_check_nv12_planes()
4461 			else if (linked->id == PLANE_6)  in icl_check_nv12_planes()
4462 				plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_6_ICL;  in icl_check_nv12_planes()
4463 			else if (linked->id == PLANE_5)  in icl_check_nv12_planes()
4464 				plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_5_RKL;  in icl_check_nv12_planes()
4465 			else if (linked->id == PLANE_4)  in icl_check_nv12_planes()
4466 				plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_4_RKL;  in icl_check_nv12_planes()
4468 				MISSING_CASE(linked->id);  in icl_check_nv12_planes()
4478 		&crtc_state->hw.pipe_mode;  in hsw_linetime_wm()
4481 	if (!crtc_state->hw.enable)  in hsw_linetime_wm()
4484 	linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8,  in hsw_linetime_wm()
4485 					pipe_mode->crtc_clock);  in hsw_linetime_wm()
4494 		&crtc_state->hw.pipe_mode;  in hsw_ips_linetime_wm()
4497 	if (!crtc_state->hw.enable)  in hsw_ips_linetime_wm()
4500 	linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8,  in hsw_ips_linetime_wm()
4501 					cdclk_state->logical.cdclk);  in hsw_ips_linetime_wm()
4508 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in skl_linetime_wm()
4509 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in skl_linetime_wm()
4511 		&crtc_state->hw.pipe_mode;  in skl_linetime_wm()
4514 	if (!crtc_state->hw.enable)  in skl_linetime_wm()
4517 	linetime_wm = DIV_ROUND_UP(pipe_mode->crtc_htotal * 1000 * 8,  in skl_linetime_wm()
4518 				   crtc_state->pixel_rate);  in skl_linetime_wm()
4531 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in hsw_compute_linetime_wm()
4537 		crtc_state->linetime = skl_linetime_wm(crtc_state);  in hsw_compute_linetime_wm()
4539 		crtc_state->linetime = hsw_linetime_wm(crtc_state);  in hsw_compute_linetime_wm()
4548 	crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state,  in hsw_compute_linetime_wm()
4558 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_crtc_atomic_check()
4565 	    !crtc_state->hw.active)  in intel_crtc_atomic_check()
4566 		crtc_state->update_wm_post = true;  in intel_crtc_atomic_check()
4580 		drm_dbg_kms(&dev_priv->drm,  in intel_crtc_atomic_check()
4582 			    crtc->base.base.id, crtc->base.name);  in intel_crtc_atomic_check()
4624 	struct drm_connector *connector = conn_state->connector;  in compute_sink_pipe_bpp()
4625 	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);  in compute_sink_pipe_bpp()
4626 	const struct drm_display_info *info = &connector->display_info;  in compute_sink_pipe_bpp()
4629 	switch (conn_state->max_bpc) {  in compute_sink_pipe_bpp()
4643 		MISSING_CASE(conn_state->max_bpc);  in compute_sink_pipe_bpp()
4644 		return -EINVAL;  in compute_sink_pipe_bpp()
4647 	if (bpp < crtc_state->pipe_bpp) {  in compute_sink_pipe_bpp()
4648 		drm_dbg_kms(&i915->drm,  in compute_sink_pipe_bpp()
4651 			    connector->base.id, connector->name,  in compute_sink_pipe_bpp()
4652 			    bpp, 3 * info->bpc,  in compute_sink_pipe_bpp()
4653 			    3 * conn_state->max_requested_bpc,  in compute_sink_pipe_bpp()
4654 			    crtc_state->pipe_bpp);  in compute_sink_pipe_bpp()
4656 		crtc_state->pipe_bpp = bpp;  in compute_sink_pipe_bpp()
4666 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in compute_baseline_pipe_bpp()
4681 	crtc_state->pipe_bpp = bpp;  in compute_baseline_pipe_bpp()
4684 	for_each_new_connector_in_state(&state->base, connector, connector_state, i) {  in compute_baseline_pipe_bpp()
4687 		if (connector_state->crtc != &crtc->base)  in compute_baseline_pipe_bpp()
4700 	struct drm_device *dev = state->base.dev;  in check_digital_port_conflicts()
4708 	 * We're going to peek into connector->state,  in check_digital_port_conflicts()
4711 	drm_modeset_lock_assert_held(&dev->mode_config.connection_mutex);  in check_digital_port_conflicts()
4724 			drm_atomic_get_new_connector_state(&state->base,  in check_digital_port_conflicts()
4727 			connector_state = connector->state;  in check_digital_port_conflicts()
4729 		if (!connector_state->best_encoder)  in check_digital_port_conflicts()
4732 		encoder = to_intel_encoder(connector_state->best_encoder);  in check_digital_port_conflicts()
4734 		drm_WARN_ON(dev, !connector_state->crtc);  in check_digital_port_conflicts()
4736 		switch (encoder->type) {  in check_digital_port_conflicts()
4745 			if (used_ports & BIT(encoder->port))  in check_digital_port_conflicts()
4748 			used_ports |= BIT(encoder->port);  in check_digital_port_conflicts()
4752 				1 << encoder->port;  in check_digital_port_conflicts()
4776 	drm_property_replace_blob(&crtc_state->hw.degamma_lut,  in intel_crtc_copy_uapi_to_hw_state_nomodeset()
4777 				  crtc_state->uapi.degamma_lut);  in intel_crtc_copy_uapi_to_hw_state_nomodeset()
4778 	drm_property_replace_blob(&crtc_state->hw.gamma_lut,  in intel_crtc_copy_uapi_to_hw_state_nomodeset()
4779 				  crtc_state->uapi.gamma_lut);  in intel_crtc_copy_uapi_to_hw_state_nomodeset()
4780 	drm_property_replace_blob(&crtc_state->hw.ctm,  in intel_crtc_copy_uapi_to_hw_state_nomodeset()
4781 				  crtc_state->uapi.ctm);  in intel_crtc_copy_uapi_to_hw_state_nomodeset()
4793 	crtc_state->hw.enable = crtc_state->uapi.enable;  in intel_crtc_copy_uapi_to_hw_state_modeset()
4794 	crtc_state->hw.active = crtc_state->uapi.active;  in intel_crtc_copy_uapi_to_hw_state_modeset()
4795 	drm_mode_copy(&crtc_state->hw.mode,  in intel_crtc_copy_uapi_to_hw_state_modeset()
4796 		      &crtc_state->uapi.mode);  in intel_crtc_copy_uapi_to_hw_state_modeset()
4797 	drm_mode_copy(&crtc_state->hw.adjusted_mode,  in intel_crtc_copy_uapi_to_hw_state_modeset()
4798 		      &crtc_state->uapi.adjusted_mode);  in intel_crtc_copy_uapi_to_hw_state_modeset()
4799 	crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter;  in intel_crtc_copy_uapi_to_hw_state_modeset()
4814 	drm_property_replace_blob(&secondary_crtc_state->hw.degamma_lut,  in copy_joiner_crtc_state_nomodeset()
4815 				  primary_crtc_state->hw.degamma_lut);  in copy_joiner_crtc_state_nomodeset()
4816 	drm_property_replace_blob(&secondary_crtc_state->hw.gamma_lut,  in copy_joiner_crtc_state_nomodeset()
4817 				  primary_crtc_state->hw.gamma_lut);  in copy_joiner_crtc_state_nomodeset()
4818 	drm_property_replace_blob(&secondary_crtc_state->hw.ctm,  in copy_joiner_crtc_state_nomodeset()
4819 				  primary_crtc_state->hw.ctm);  in copy_joiner_crtc_state_nomodeset()
4821 	secondary_crtc_state->uapi.color_mgmt_changed = primary_crtc_state->uapi.color_mgmt_changed;  in copy_joiner_crtc_state_nomodeset()
4835 	WARN_ON(primary_crtc_state->joiner_pipes !=  in copy_joiner_crtc_state_modeset()
4836 		secondary_crtc_state->joiner_pipes);  in copy_joiner_crtc_state_modeset()
4840 		return -ENOMEM;  in copy_joiner_crtc_state_modeset()
4843 	saved_state->uapi = secondary_crtc_state->uapi;  in copy_joiner_crtc_state_modeset()
4844 	saved_state->scaler_state = secondary_crtc_state->scaler_state;  in copy_joiner_crtc_state_modeset()
4845 	saved_state->shared_dpll = secondary_crtc_state->shared_dpll;  in copy_joiner_crtc_state_modeset()
4846 	saved_state->crc_enabled = secondary_crtc_state->crc_enabled;  in copy_joiner_crtc_state_modeset()
4849 	if (secondary_crtc_state->dp_tunnel_ref.tunnel)  in copy_joiner_crtc_state_modeset()
4850 		drm_dp_tunnel_ref_put(&secondary_crtc_state->dp_tunnel_ref);  in copy_joiner_crtc_state_modeset()
4854 	/* Re-init hw state */  in copy_joiner_crtc_state_modeset()
4855 	memset(&secondary_crtc_state->hw, 0, sizeof(secondary_crtc_state->hw));  in copy_joiner_crtc_state_modeset()
4856 	secondary_crtc_state->hw.enable = primary_crtc_state->hw.enable;  in copy_joiner_crtc_state_modeset()
4857 	secondary_crtc_state->hw.active = primary_crtc_state->hw.active;  in copy_joiner_crtc_state_modeset()
4858 	drm_mode_copy(&secondary_crtc_state->hw.mode,  in copy_joiner_crtc_state_modeset()
4859 		      &primary_crtc_state->hw.mode);  in copy_joiner_crtc_state_modeset()
4860 	drm_mode_copy(&secondary_crtc_state->hw.pipe_mode,  in copy_joiner_crtc_state_modeset()
4861 		      &primary_crtc_state->hw.pipe_mode);  in copy_joiner_crtc_state_modeset()
4862 	drm_mode_copy(&secondary_crtc_state->hw.adjusted_mode,  in copy_joiner_crtc_state_modeset()
4863 		      &primary_crtc_state->hw.adjusted_mode);  in copy_joiner_crtc_state_modeset()
4864 	secondary_crtc_state->hw.scaling_filter = primary_crtc_state->hw.scaling_filter;  in copy_joiner_crtc_state_modeset()
4866 	if (primary_crtc_state->dp_tunnel_ref.tunnel)  in copy_joiner_crtc_state_modeset()
4867 		drm_dp_tunnel_ref_get(primary_crtc_state->dp_tunnel_ref.tunnel,  in copy_joiner_crtc_state_modeset()
4868 				      &secondary_crtc_state->dp_tunnel_ref);  in copy_joiner_crtc_state_modeset()
4872 	secondary_crtc_state->uapi.mode_changed = primary_crtc_state->uapi.mode_changed;  in copy_joiner_crtc_state_modeset()
4873 	secondary_crtc_state->uapi.connectors_changed = primary_crtc_state->uapi.connectors_changed;  in copy_joiner_crtc_state_modeset()
4874 	secondary_crtc_state->uapi.active_changed = primary_crtc_state->uapi.active_changed;  in copy_joiner_crtc_state_modeset()
4876 	WARN_ON(primary_crtc_state->joiner_pipes !=  in copy_joiner_crtc_state_modeset()
4877 		secondary_crtc_state->joiner_pipes);  in copy_joiner_crtc_state_modeset()
4888 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_crtc_prepare_cleared_state()
4893 		return -ENOMEM;  in intel_crtc_prepare_cleared_state()
4895 	/* free the old crtc_state->hw members */  in intel_crtc_prepare_cleared_state()
4905 	saved_state->uapi = crtc_state->uapi;  in intel_crtc_prepare_cleared_state()
4906 	saved_state->inherited = crtc_state->inherited;  in intel_crtc_prepare_cleared_state()
4907 	saved_state->scaler_state = crtc_state->scaler_state;  in intel_crtc_prepare_cleared_state()
4908 	saved_state->shared_dpll = crtc_state->shared_dpll;  in intel_crtc_prepare_cleared_state()
4909 	saved_state->dpll_hw_state = crtc_state->dpll_hw_state;  in intel_crtc_prepare_cleared_state()
4910 	memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls,  in intel_crtc_prepare_cleared_state()
4911 	       sizeof(saved_state->icl_port_dplls));  in intel_crtc_prepare_cleared_state()
4912 	saved_state->crc_enabled = crtc_state->crc_enabled;  in intel_crtc_prepare_cleared_state()
4915 		saved_state->wm = crtc_state->wm;  in intel_crtc_prepare_cleared_state()
4930 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);  in intel_modeset_pipe_config()
4938 	crtc_state->cpu_transcoder = (enum transcoder) crtc->pipe;  in intel_modeset_pipe_config()
4940 	crtc_state->framestart_delay = 1;  in intel_modeset_pipe_config()
4947 	if (!(crtc_state->hw.adjusted_mode.flags &  in intel_modeset_pipe_config()
4949 		crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;  in intel_modeset_pipe_config()
4951 	if (!(crtc_state->hw.adjusted_mode.flags &  in intel_modeset_pipe_config()
4953 		crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;  in intel_modeset_pipe_config()
4959 	crtc_state->fec_enable = limits->force_fec_pipes & BIT(crtc->pipe);  in intel_modeset_pipe_config()
4960 	crtc_state->max_link_bpp_x16 = limits->max_bpp_x16[crtc->pipe];  in intel_modeset_pipe_config()
4962 	if (crtc_state->pipe_bpp > fxp_q4_to_int(crtc_state->max_link_bpp_x16)) {  in intel_modeset_pipe_config()
4963 		drm_dbg_kms(&i915->drm,  in intel_modeset_pipe_config()
4965 			    crtc->base.base.id, crtc->base.name,  in intel_modeset_pipe_config()
4966 			    FXP_Q4_ARGS(crtc_state->max_link_bpp_x16));  in intel_modeset_pipe_config()
4967 		crtc_state->bw_constrained = true;  in intel_modeset_pipe_config()
4970 	base_bpp = crtc_state->pipe_bpp;  in intel_modeset_pipe_config()
4980 	drm_mode_get_hv_timing(&crtc_state->hw.mode,  in intel_modeset_pipe_config()
4982 	drm_rect_init(&crtc_state->pipe_src, 0, 0,  in intel_modeset_pipe_config()
4985 	for_each_new_connector_in_state(&state->base, connector, connector_state, i) {  in intel_modeset_pipe_config()
4987 			to_intel_encoder(connector_state->best_encoder);  in intel_modeset_pipe_config()
4989 		if (connector_state->crtc != &crtc->base)  in intel_modeset_pipe_config()
4993 			drm_dbg_kms(&i915->drm,  in intel_modeset_pipe_config()
4995 				    encoder->base.base.id, encoder->base.name);  in intel_modeset_pipe_config()
4996 			return -EINVAL;  in intel_modeset_pipe_config()
5003 		if (encoder->compute_output_type)  in intel_modeset_pipe_config()
5004 			crtc_state->output_types |=  in intel_modeset_pipe_config()
5005 				BIT(encoder->compute_output_type(encoder, crtc_state,  in intel_modeset_pipe_config()
5008 			crtc_state->output_types |= BIT(encoder->type);  in intel_modeset_pipe_config()
5012 	crtc_state->port_clock = 0;  in intel_modeset_pipe_config()
5013 	crtc_state->pixel_multiplier = 1;  in intel_modeset_pipe_config()
5016 	drm_mode_set_crtcinfo(&crtc_state->hw.adjusted_mode,  in intel_modeset_pipe_config()
5023 	for_each_new_connector_in_state(&state->base, connector, connector_state, i) {  in intel_modeset_pipe_config()
5025 			to_intel_encoder(connector_state->best_encoder);  in intel_modeset_pipe_config()
5027 		if (connector_state->crtc != &crtc->base)  in intel_modeset_pipe_config()
5030 		ret = encoder->compute_config(encoder, crtc_state,  in intel_modeset_pipe_config()
5032 		if (ret == -EDEADLK)  in intel_modeset_pipe_config()
5035 			drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] config failure: %d\n",  in intel_modeset_pipe_config()
5036 				    encoder->base.base.id, encoder->base.name, ret);  in intel_modeset_pipe_config()
5043 	if (!crtc_state->port_clock)  in intel_modeset_pipe_config()
5044 		crtc_state->port_clock = crtc_state->hw.adjusted_mode.crtc_clock  in intel_modeset_pipe_config()
5045 			* crtc_state->pixel_multiplier;  in intel_modeset_pipe_config()
5048 	if (ret == -EDEADLK)  in intel_modeset_pipe_config()
5051 		drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] config failure: %d\n",  in intel_modeset_pipe_config()
5052 			    crtc->base.base.id, crtc->base.name, ret);  in intel_modeset_pipe_config()
5056 	/* Dithering seems to not pass-through bits correctly when it should, so  in intel_modeset_pipe_config()
5060 	crtc_state->dither = (crtc_state->pipe_bpp == 6*3) &&  in intel_modeset_pipe_config()
5061 		!crtc_state->dither_force_disable;  in intel_modeset_pipe_config()
5062 	drm_dbg_kms(&i915->drm,  in intel_modeset_pipe_config()
5064 		    crtc->base.base.id, crtc->base.name,  in intel_modeset_pipe_config()
5065 		    base_bpp, crtc_state->pipe_bpp, crtc_state->dither);  in intel_modeset_pipe_config()
5082 	for_each_new_connector_in_state(&state->base, connector,  in intel_modeset_pipe_config_late()
5085 			to_intel_encoder(conn_state->best_encoder);  in intel_modeset_pipe_config_late()
5088 		if (conn_state->crtc != &crtc->base ||  in intel_modeset_pipe_config_late()
5089 		    !encoder->compute_config_late)  in intel_modeset_pipe_config_late()
5092 		ret = encoder->compute_config_late(encoder, crtc_state,  in intel_modeset_pipe_config_late()
5111 	diff = abs(clock1 - clock2);  in intel_fuzzy_clock_check()
5123 	return m_n->tu == m2_n2->tu &&  in intel_compare_link_m_n()
5124 		m_n->data_m == m2_n2->data_m &&  in intel_compare_link_m_n()
5125 		m_n->data_n == m2_n2->data_n &&  in intel_compare_link_m_n()
5126 		m_n->link_m == m2_n2->link_m &&  in intel_compare_link_m_n()
5127 		m_n->link_n == m2_n2->link_n;  in intel_compare_link_m_n()
5141 	return a->pixelformat == b->pixelformat &&  in intel_compare_dp_vsc_sdp()
5142 		a->colorimetry == b->colorimetry &&  in intel_compare_dp_vsc_sdp()
5143 		a->bpc == b->bpc &&  in intel_compare_dp_vsc_sdp()
5144 		a->dynamic_range == b->dynamic_range &&  in intel_compare_dp_vsc_sdp()
5145 		a->content_type == b->content_type;  in intel_compare_dp_vsc_sdp()
5152 	return a->vtotal == b->vtotal &&  in intel_compare_dp_as_sdp()
5153 		a->target_rr == b->target_rr &&  in intel_compare_dp_as_sdp()
5154 		a->duration_incr_ms == b->duration_incr_ms &&  in intel_compare_dp_as_sdp()
5155 		a->duration_decr_ms == b->duration_decr_ms &&  in intel_compare_dp_as_sdp()
5156 		a->mode == b->mode;  in intel_compare_dp_as_sdp()
5179 			   crtc->base.base.id, crtc->base.name, name, &vaf);  in pipe_config_mismatch()
5182 			   crtc->base.base.id, crtc->base.name, name, &vaf);  in pipe_config_mismatch()
5194 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);  in pipe_config_infoframe_mismatch()
5209 	hdmi_infoframe_log(loglevel, i915->drm.dev, a);  in pipe_config_infoframe_mismatch()
5211 	hdmi_infoframe_log(loglevel, i915->drm.dev, b);  in pipe_config_infoframe_mismatch()
5250 	for (i = len - 1; i >= 0; i--) {  in memcmp_diff_len()
5280 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);  in pipe_config_pll_mismatch()
5282 	pipe_config_mismatch(p, fastset, crtc, name, " "); /* stupid -Werror=format-zero-length */  in pipe_config_pll_mismatch()
5298 	char *chipname = a->use_c10 ? "C10" : "C20";  in pipe_config_cx0pll_mismatch()
5314 	struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev);  in intel_pipe_config_compare()
5315 	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);  in intel_pipe_config_compare()
5320 		p = drm_dbg_printer(&dev_priv->drm, DRM_UT_KMS, NULL);  in intel_pipe_config_compare()
5322 		p = drm_err_printer(&dev_priv->drm, NULL);  in intel_pipe_config_compare()
5325 	if (current_config->name != pipe_config->name) { \  in intel_pipe_config_compare()
5326 		BUILD_BUG_ON_MSG(__same_type(current_config->name, bool), \  in intel_pipe_config_compare()
5330 				     current_config->name, \  in intel_pipe_config_compare()
5331 				     pipe_config->name); \  in intel_pipe_config_compare()
5337 	if ((current_config->name & (mask)) != (pipe_config->name & (mask))) { \  in intel_pipe_config_compare()
5338 		BUILD_BUG_ON_MSG(__same_type(current_config->name, bool), \  in intel_pipe_config_compare()
5342 				     current_config->name & (mask), \  in intel_pipe_config_compare()
5343 				     pipe_config->name & (mask)); \  in intel_pipe_config_compare()
5349 	if (current_config->name != pipe_config->name) { \  in intel_pipe_config_compare()
5350 		BUILD_BUG_ON_MSG(__same_type(current_config->name, bool), \  in intel_pipe_config_compare()
5354 				     current_config->name, \  in intel_pipe_config_compare()
5355 				     pipe_config->name); \  in intel_pipe_config_compare()
5361 	if (current_config->name != pipe_config->name) { \  in intel_pipe_config_compare()
5364 				     current_config->name, \  in intel_pipe_config_compare()
5365 				     pipe_config->name); \  in intel_pipe_config_compare()
5371 	if (current_config->name != pipe_config->name) { \  in intel_pipe_config_compare()
5372 		BUILD_BUG_ON_MSG(!__same_type(current_config->name, bool), \  in intel_pipe_config_compare()
5376 				     str_yes_no(current_config->name), \  in intel_pipe_config_compare()
5377 				     str_yes_no(pipe_config->name)); \  in intel_pipe_config_compare()
5383 	if (current_config->name != pipe_config->name) { \  in intel_pipe_config_compare()
5386 				     current_config->name, \  in intel_pipe_config_compare()
5387 				     pipe_config->name); \  in intel_pipe_config_compare()
5393 	if (!intel_compare_link_m_n(&current_config->name, \  in intel_pipe_config_compare()
5394 				    &pipe_config->name)) { \  in intel_pipe_config_compare()
5398 				     current_config->name.tu, \  in intel_pipe_config_compare()
5399 				     current_config->name.data_m, \  in intel_pipe_config_compare()
5400 				     current_config->name.data_n, \  in intel_pipe_config_compare()
5401 				     current_config->name.link_m, \  in intel_pipe_config_compare()
5402 				     current_config->name.link_n, \  in intel_pipe_config_compare()
5403 				     pipe_config->name.tu, \  in intel_pipe_config_compare()
5404 				     pipe_config->name.data_m, \  in intel_pipe_config_compare()
5405 				     pipe_config->name.data_n, \  in intel_pipe_config_compare()
5406 				     pipe_config->name.link_m, \  in intel_pipe_config_compare()
5407 				     pipe_config->name.link_n); \  in intel_pipe_config_compare()
5413 	if (!intel_dpll_compare_hw_state(dev_priv, &current_config->name, \  in intel_pipe_config_compare()
5414 					 &pipe_config->name)) { \  in intel_pipe_config_compare()
5416 					 &current_config->name, \  in intel_pipe_config_compare()
5417 					 &pipe_config->name); \  in intel_pipe_config_compare()
5423 	if (!intel_cx0pll_compare_hw_state(&current_config->name, \  in intel_pipe_config_compare()
5424 					   &pipe_config->name)) { \  in intel_pipe_config_compare()
5426 					    &current_config->name, \  in intel_pipe_config_compare()
5427 					    &pipe_config->name); \  in intel_pipe_config_compare()
5443 	if (!fastset || !pipe_config->update_lrr) { \  in intel_pipe_config_compare()
5457 	if ((current_config->name ^ pipe_config->name) & (mask)) { \  in intel_pipe_config_compare()
5461 				     current_config->name & (mask), \  in intel_pipe_config_compare()
5462 				     pipe_config->name & (mask)); \  in intel_pipe_config_compare()
5468 	if (!intel_compare_infoframe(&current_config->infoframes.name, \  in intel_pipe_config_compare()
5469 				     &pipe_config->infoframes.name)) { \  in intel_pipe_config_compare()
5471 					       &current_config->infoframes.name, \  in intel_pipe_config_compare()
5472 					       &pipe_config->infoframes.name); \  in intel_pipe_config_compare()
5478 	if (!intel_compare_dp_vsc_sdp(&current_config->infoframes.name, \  in intel_pipe_config_compare()
5479 				      &pipe_config->infoframes.name)) { \  in intel_pipe_config_compare()
5481 						&current_config->infoframes.name, \  in intel_pipe_config_compare()
5482 						&pipe_config->infoframes.name); \  in intel_pipe_config_compare()
5488 	if (!intel_compare_dp_as_sdp(&current_config->infoframes.name, \  in intel_pipe_config_compare()
5489 				      &pipe_config->infoframes.name)) { \  in intel_pipe_config_compare()
5491 						&current_config->infoframes.name, \  in intel_pipe_config_compare()
5492 						&pipe_config->infoframes.name); \  in intel_pipe_config_compare()
5498 	BUILD_BUG_ON(sizeof(current_config->name) != (len)); \  in intel_pipe_config_compare()
5499 	BUILD_BUG_ON(sizeof(pipe_config->name) != (len)); \  in intel_pipe_config_compare()
5500 	if (!intel_compare_buffer(current_config->name, pipe_config->name, (len))) { \  in intel_pipe_config_compare()
5502 					    current_config->name, \  in intel_pipe_config_compare()
5503 					    pipe_config->name, \  in intel_pipe_config_compare()
5510 	if (current_config->gamma_mode == pipe_config->gamma_mode && \  in intel_pipe_config_compare()
5512 				   current_config->lut, pipe_config->lut, \  in intel_pipe_config_compare()
5539 	((current_config->quirks | pipe_config->quirks) & (quirk))  in intel_pipe_config_compare()
5555 		if (!fastset || !pipe_config->update_m_n)  in intel_pipe_config_compare()
5645 	 * this requirement -> check these only if using panel replay  in intel_pipe_config_compare()
5647 	if (current_config->active_planes &&  in intel_pipe_config_compare()
5648 	    (current_config->has_panel_replay ||  in intel_pipe_config_compare()
5649 	     pipe_config->has_panel_replay)) {  in intel_pipe_config_compare()
5659 	if (dev_priv->display.dpll.mgr)  in intel_pipe_config_compare()
5663 	if (dev_priv->display.dpll.mgr || HAS_GMCH(dev_priv))  in intel_pipe_config_compare()
5676 	if (!fastset || !pipe_config->update_m_n) {  in intel_pipe_config_compare()
5684 	if (current_config->has_psr || pipe_config->has_psr)  in intel_pipe_config_compare()
5779 		assert_plane(plane, plane_state->planar_slave ||  in intel_verify_planes()
5780 			     plane_state->uapi.visible);  in intel_verify_planes()
5787 	struct drm_i915_private *i915 = to_i915(state->base.dev);  in intel_modeset_pipe()
5788 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_modeset_pipe()
5791 	drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] Full modeset due to %s\n",  in intel_modeset_pipe()
5792 		    crtc->base.base.id, crtc->base.name, reason);  in intel_modeset_pipe()
5794 	ret = drm_atomic_add_affected_connectors(&state->base,  in intel_modeset_pipe()
5795 						 &crtc->base);  in intel_modeset_pipe()
5811 	crtc_state->uapi.mode_changed = true;  in intel_modeset_pipe()
5817  * intel_modeset_pipes_in_mask_early - force a full modeset on a set of pipes
5831 	struct drm_i915_private *i915 = to_i915(state->base.dev);  in intel_modeset_pipes_in_mask_early()
5834 	for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, mask) {  in intel_modeset_pipes_in_mask_early()
5838 		crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);  in intel_modeset_pipes_in_mask_early()
5842 		if (!crtc_state->hw.enable ||  in intel_modeset_pipes_in_mask_early()
5857 	crtc_state->uapi.mode_changed = true;  in intel_crtc_flag_modeset()
5859 	crtc_state->update_pipe = false;  in intel_crtc_flag_modeset()
5860 	crtc_state->update_m_n = false;  in intel_crtc_flag_modeset()
5861 	crtc_state->update_lrr = false;  in intel_crtc_flag_modeset()
5865  * intel_modeset_all_pipes_late - force a full modeset on all pipes
5878 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);  in intel_modeset_all_pipes_late()
5881 	for_each_intel_crtc(&dev_priv->drm, crtc) {  in intel_modeset_all_pipes_late()
5885 		crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);  in intel_modeset_all_pipes_late()
5889 		if (!crtc_state->hw.active ||  in intel_modeset_all_pipes_late()
5899 		crtc_state->update_planes |= crtc_state->active_planes;  in intel_modeset_all_pipes_late()
5900 		crtc_state->async_flip_planes = 0;  in intel_modeset_all_pipes_late()
5901 		crtc_state->do_async_flip = false;  in intel_modeset_all_pipes_late()
5915 	state = drm_atomic_state_alloc(&i915->drm);  in intel_modeset_commit_pipes()
5917 		return -ENOMEM;  in intel_modeset_commit_pipes()
5919 	state->acquire_ctx = ctx;  in intel_modeset_commit_pipes()
5920 	to_intel_atomic_state(state)->internal = true;  in intel_modeset_commit_pipes()
5922 	for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, pipe_mask) {  in intel_modeset_commit_pipes()
5931 		crtc_state->uapi.connectors_changed = true;  in intel_modeset_commit_pipes()
5958 		if (!crtc_state->hw.active ||  in hsw_mode_set_planes_workaround()
5967 			first_pipe = crtc->pipe;  in hsw_mode_set_planes_workaround()
5976 	for_each_intel_crtc(state->base.dev, crtc) {  in hsw_mode_set_planes_workaround()
5977 		crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);  in hsw_mode_set_planes_workaround()
5981 		crtc_state->hsw_workaround_pipe = INVALID_PIPE;  in hsw_mode_set_planes_workaround()
5983 		if (!crtc_state->hw.active ||  in hsw_mode_set_planes_workaround()
5991 		enabled_pipe = crtc->pipe;  in hsw_mode_set_planes_workaround()
5995 		first_crtc_state->hsw_workaround_pipe = enabled_pipe;  in hsw_mode_set_planes_workaround()
5997 		other_crtc_state->hsw_workaround_pipe = first_pipe;  in hsw_mode_set_planes_workaround()
6010 		if (crtc_state->hw.active)  in intel_calc_active_pipes()
6011 			active_pipes |= BIT(crtc->pipe);  in intel_calc_active_pipes()
6013 			active_pipes &= ~BIT(crtc->pipe);  in intel_calc_active_pipes()
6021 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);  in intel_modeset_checks()
6023 	state->modeset = true;  in intel_modeset_checks()
6034 	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);  in intel_crtc_check_fastset()
6035 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);  in intel_crtc_check_fastset()
6038 	if (old_crtc_state->vrr.in_range != new_crtc_state->vrr.in_range)  in intel_crtc_check_fastset()
6039 		new_crtc_state->update_lrr = false;  in intel_crtc_check_fastset()
6042 		drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] fastset requirement not met, forcing full modeset\n",  in intel_crtc_check_fastset()
6043 			    crtc->base.base.id, crtc->base.name);  in intel_crtc_check_fastset()
6045 		new_crtc_state->uapi.mode_changed = false;  in intel_crtc_check_fastset()
6047 	if (intel_compare_link_m_n(&old_crtc_state->dp_m_n,  in intel_crtc_check_fastset()
6048 				   &new_crtc_state->dp_m_n))  in intel_crtc_check_fastset()
6049 		new_crtc_state->update_m_n = false;  in intel_crtc_check_fastset()
6051 …if ((old_crtc_state->hw.adjusted_mode.crtc_vtotal == new_crtc_state->hw.adjusted_mode.crtc_vtotal …  in intel_crtc_check_fastset()
6052 …old_crtc_state->hw.adjusted_mode.crtc_vblank_end == new_crtc_state->hw.adjusted_mode.crtc_vblank_e…  in intel_crtc_check_fastset()
6053 		new_crtc_state->update_lrr = false;  in intel_crtc_check_fastset()
6058 		new_crtc_state->update_pipe = true;  in intel_crtc_check_fastset()
6065 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);  in intel_crtc_add_planes_to_state()
6068 	for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {  in intel_crtc_add_planes_to_state()
6071 		if ((plane_ids_mask & BIT(plane->id)) == 0)  in intel_crtc_add_planes_to_state()
6091 					      old_crtc_state->enabled_planes |  in intel_atomic_add_affected_planes()
6092 					      new_crtc_state->enabled_planes);  in intel_atomic_add_affected_planes()
6113 		if (plane->pipe == crtc->pipe)  in intel_crtc_add_joiner_planes()
6114 			plane_ids |= BIT(plane->id);  in intel_crtc_add_joiner_planes()
6122 	struct drm_i915_private *i915 = to_i915(state->base.dev);  in intel_joiner_add_affected_planes()
6130 		for_each_intel_crtc_in_pipe_mask(&i915->drm, other,  in intel_joiner_add_affected_planes()
6131 						 crtc_state->joiner_pipes) {  in intel_joiner_add_affected_planes()
6148 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);  in intel_atomic_check_planes()
6166 			drm_dbg_atomic(&dev_priv->drm,  in intel_atomic_check_planes()
6168 				       plane->base.base.id, plane->base.name);  in intel_atomic_check_planes()
6189 		old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR);  in intel_atomic_check_planes()
6190 		new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR);  in intel_atomic_check_planes()
6210 		struct drm_i915_private *i915 = to_i915(crtc->base.dev);  in intel_atomic_check_crtcs()
6215 			drm_dbg_atomic(&i915->drm,  in intel_atomic_check_crtcs()
6217 				       crtc->base.base.id, crtc->base.name);  in intel_atomic_check_crtcs()
6233 		if (new_crtc_state->hw.enable &&  in intel_cpu_transcoders_need_modeset()
6234 		    transcoders & BIT(new_crtc_state->cpu_transcoder) &&  in intel_cpu_transcoders_need_modeset()
6250 		if (new_crtc_state->hw.enable &&  in intel_pipes_need_modeset()
6251 		    pipes & BIT(crtc->pipe) &&  in intel_pipes_need_modeset()
6262 	struct drm_i915_private *i915 = to_i915(state->base.dev);  in intel_atomic_check_joiner()
6267 	if (!primary_crtc_state->joiner_pipes)  in intel_atomic_check_joiner()
6271 	if (drm_WARN_ON(&i915->drm,  in intel_atomic_check_joiner()
6272 			primary_crtc->pipe != joiner_primary_pipe(primary_crtc_state)))  in intel_atomic_check_joiner()
6273 		return -EINVAL;  in intel_atomic_check_joiner()
6275 	if (primary_crtc_state->joiner_pipes & ~joiner_pipes(i915)) {  in intel_atomic_check_joiner()
6276 		drm_dbg_kms(&i915->drm,  in intel_atomic_check_joiner()
6279 			    primary_crtc->base.base.id, primary_crtc->base.name,  in intel_atomic_check_joiner()
6280 			    primary_crtc_state->joiner_pipes, joiner_pipes(i915));  in intel_atomic_check_joiner()
6281 		return -EINVAL;  in intel_atomic_check_joiner()
6284 	for_each_intel_crtc_in_pipe_mask(&i915->drm, secondary_crtc,  in intel_atomic_check_joiner()
6289 		secondary_crtc_state = intel_atomic_get_crtc_state(&state->base, secondary_crtc);  in intel_atomic_check_joiner()
6294 		if (secondary_crtc_state->uapi.enable) {  in intel_atomic_check_joiner()
6295 			drm_dbg_kms(&i915->drm,  in intel_atomic_check_joiner()
6298 				    secondary_crtc->base.base.id, secondary_crtc->base.name,  in intel_atomic_check_joiner()
6299 				    primary_crtc->base.base.id, primary_crtc->base.name);  in intel_atomic_check_joiner()
6300 			return -EINVAL;  in intel_atomic_check_joiner()
6310 		if (WARN_ON(drm_crtc_index(&primary_crtc->base) >  in intel_atomic_check_joiner()
6311 			    drm_crtc_index(&secondary_crtc->base)))  in intel_atomic_check_joiner()
6312 			return -EINVAL;  in intel_atomic_check_joiner()
6314 		drm_dbg_kms(&i915->drm,  in intel_atomic_check_joiner()
6316 			    secondary_crtc->base.base.id, secondary_crtc->base.name,  in intel_atomic_check_joiner()
6317 			    primary_crtc->base.base.id, primary_crtc->base.name);  in intel_atomic_check_joiner()
6319 		secondary_crtc_state->joiner_pipes =  in intel_atomic_check_joiner()
6320 			primary_crtc_state->joiner_pipes;  in intel_atomic_check_joiner()
6333 	struct drm_i915_private *i915 = to_i915(state->base.dev);  in kill_joiner_secondaries()
6338 	for_each_intel_crtc_in_pipe_mask(&i915->drm, secondary_crtc,  in kill_joiner_secondaries()
6343 		secondary_crtc_state->joiner_pipes = 0;  in kill_joiner_secondaries()
6348 	primary_crtc_state->joiner_pipes = 0;  in kill_joiner_secondaries()
6372 	struct drm_i915_private *i915 = to_i915(state->base.dev);  in intel_async_flip_check_uapi()
6380 	if (!new_crtc_state->uapi.async_flip)  in intel_async_flip_check_uapi()
6383 	if (!new_crtc_state->uapi.active) {  in intel_async_flip_check_uapi()
6384 		drm_dbg_kms(&i915->drm,  in intel_async_flip_check_uapi()
6386 			    crtc->base.base.id, crtc->base.name);  in intel_async_flip_check_uapi()
6387 		return -EINVAL;  in intel_async_flip_check_uapi()
6391 		drm_dbg_kms(&i915->drm,  in intel_async_flip_check_uapi()
6393 			    crtc->base.base.id, crtc->base.name);  in intel_async_flip_check_uapi()
6394 		return -EINVAL;  in intel_async_flip_check_uapi()
6401 	if (new_crtc_state->joiner_pipes) {  in intel_async_flip_check_uapi()
6402 		drm_dbg_kms(&i915->drm,  in intel_async_flip_check_uapi()
6404 			    crtc->base.base.id, crtc->base.name);  in intel_async_flip_check_uapi()
6405 		return -EINVAL;  in intel_async_flip_check_uapi()
6410 		if (plane->pipe != crtc->pipe)  in intel_async_flip_check_uapi()
6420 		if (!plane->async_flip) {  in intel_async_flip_check_uapi()
6421 			drm_dbg_kms(&i915->drm,  in intel_async_flip_check_uapi()
6423 				    plane->base.base.id, plane->base.name);  in intel_async_flip_check_uapi()
6424 			return -EINVAL;  in intel_async_flip_check_uapi()
6427 		if (!old_plane_state->uapi.fb || !new_plane_state->uapi.fb) {  in intel_async_flip_check_uapi()
6428 			drm_dbg_kms(&i915->drm,  in intel_async_flip_check_uapi()
6430 				    plane->base.base.id, plane->base.name);  in intel_async_flip_check_uapi()
6431 			return -EINVAL;  in intel_async_flip_check_uapi()
6440 	struct drm_i915_private *i915 = to_i915(state->base.dev);  in intel_async_flip_check_hw()
6449 	if (!new_crtc_state->uapi.async_flip)  in intel_async_flip_check_hw()
6452 	if (!new_crtc_state->hw.active) {  in intel_async_flip_check_hw()
6453 		drm_dbg_kms(&i915->drm,  in intel_async_flip_check_hw()
6455 			    crtc->base.base.id, crtc->base.name);  in intel_async_flip_check_hw()
6456 		return -EINVAL;  in intel_async_flip_check_hw()
6460 		drm_dbg_kms(&i915->drm,  in intel_async_flip_check_hw()
6462 			    crtc->base.base.id, crtc->base.name);  in intel_async_flip_check_hw()
6463 		return -EINVAL;  in intel_async_flip_check_hw()
6466 	if (old_crtc_state->active_planes != new_crtc_state->active_planes) {  in intel_async_flip_check_hw()
6467 		drm_dbg_kms(&i915->drm,  in intel_async_flip_check_hw()
6469 			    crtc->base.base.id, crtc->base.name);  in intel_async_flip_check_hw()
6470 		return -EINVAL;  in intel_async_flip_check_hw()
6475 		if (plane->pipe != crtc->pipe)  in intel_async_flip_check_hw()
6483 		if (drm_WARN_ON(&i915->drm,  in intel_async_flip_check_hw()
6484 				new_crtc_state->do_async_flip && !plane->async_flip))  in intel_async_flip_check_hw()
6485 			return -EINVAL;  in intel_async_flip_check_hw()
6495 		if (!plane->async_flip)  in intel_async_flip_check_hw()
6503 		switch (new_plane_state->hw.fb->modifier) {  in intel_async_flip_check_hw()
6512 				drm_dbg_kms(&i915->drm,  in intel_async_flip_check_hw()
6514 					    plane->base.base.id, plane->base.name,  in intel_async_flip_check_hw()
6515 					    new_plane_state->hw.fb->modifier, DISPLAY_VER(i915));  in intel_async_flip_check_hw()
6516 				return -EINVAL;  in intel_async_flip_check_hw()
6528 			drm_dbg_kms(&i915->drm,  in intel_async_flip_check_hw()
6530 				    plane->base.base.id, plane->base.name,  in intel_async_flip_check_hw()
6531 				    new_plane_state->hw.fb->modifier);  in intel_async_flip_check_hw()
6532 			return -EINVAL;  in intel_async_flip_check_hw()
6535 		if (new_plane_state->hw.fb->format->num_planes > 1) {  in intel_async_flip_check_hw()
6536 			drm_dbg_kms(&i915->drm,  in intel_async_flip_check_hw()
6538 				    plane->base.base.id, plane->base.name);  in intel_async_flip_check_hw()
6539 			return -EINVAL;  in intel_async_flip_check_hw()
6546 		if (!new_crtc_state->do_async_flip)  in intel_async_flip_check_hw()
6549 		if (old_plane_state->view.color_plane[0].mapping_stride !=  in intel_async_flip_check_hw()
6550 		    new_plane_state->view.color_plane[0].mapping_stride) {  in intel_async_flip_check_hw()
6551 			drm_dbg_kms(&i915->drm,  in intel_async_flip_check_hw()
6553 				    plane->base.base.id, plane->base.name);  in intel_async_flip_check_hw()
6554 			return -EINVAL;  in intel_async_flip_check_hw()
6557 		if (old_plane_state->hw.fb->modifier !=  in intel_async_flip_check_hw()
6558 		    new_plane_state->hw.fb->modifier) {  in intel_async_flip_check_hw()
6559 			drm_dbg_kms(&i915->drm,  in intel_async_flip_check_hw()
6561 				    plane->base.base.id, plane->base.name);  in intel_async_flip_check_hw()
6562 			return -EINVAL;  in intel_async_flip_check_hw()
6565 		if (old_plane_state->hw.fb->format !=  in intel_async_flip_check_hw()
6566 		    new_plane_state->hw.fb->format) {  in intel_async_flip_check_hw()
6567 			drm_dbg_kms(&i915->drm,  in intel_async_flip_check_hw()
6569 				    plane->base.base.id, plane->base.name);  in intel_async_flip_check_hw()
6570 			return -EINVAL;  in intel_async_flip_check_hw()
6573 		if (old_plane_state->hw.rotation !=  in intel_async_flip_check_hw()
6574 		    new_plane_state->hw.rotation) {  in intel_async_flip_check_hw()
6575 			drm_dbg_kms(&i915->drm,  in intel_async_flip_check_hw()
6577 				    plane->base.base.id, plane->base.name);  in intel_async_flip_check_hw()
6578 			return -EINVAL;  in intel_async_flip_check_hw()
6581 		if (!drm_rect_equals(&old_plane_state->uapi.src, &new_plane_state->uapi.src) ||  in intel_async_flip_check_hw()
6582 		    !drm_rect_equals(&old_plane_state->uapi.dst, &new_plane_state->uapi.dst)) {  in intel_async_flip_check_hw()
6583 			drm_dbg_kms(&i915->drm,  in intel_async_flip_check_hw()
6584 				    "[PLANE:%d:%s] Size/co-ordinates cannot be changed in async flip\n",  in intel_async_flip_check_hw()
6585 				    plane->base.base.id, plane->base.name);  in intel_async_flip_check_hw()
6586 			return -EINVAL;  in intel_async_flip_check_hw()
6589 		if (old_plane_state->hw.alpha != new_plane_state->hw.alpha) {  in intel_async_flip_check_hw()
6590 			drm_dbg_kms(&i915->drm,  in intel_async_flip_check_hw()
6592 				    plane->base.base.id, plane->base.name);  in intel_async_flip_check_hw()
6593 			return -EINVAL;  in intel_async_flip_check_hw()
6596 		if (old_plane_state->hw.pixel_blend_mode !=  in intel_async_flip_check_hw()
6597 		    new_plane_state->hw.pixel_blend_mode) {  in intel_async_flip_check_hw()
6598 			drm_dbg_kms(&i915->drm,  in intel_async_flip_check_hw()
6600 				    plane->base.base.id, plane->base.name);  in intel_async_flip_check_hw()
6601 			return -EINVAL;  in intel_async_flip_check_hw()
6604 		if (old_plane_state->hw.color_encoding != new_plane_state->hw.color_encoding) {  in intel_async_flip_check_hw()
6605 			drm_dbg_kms(&i915->drm,  in intel_async_flip_check_hw()
6607 				    plane->base.base.id, plane->base.name);  in intel_async_flip_check_hw()
6608 			return -EINVAL;  in intel_async_flip_check_hw()
6611 		if (old_plane_state->hw.color_range != new_plane_state->hw.color_range) {  in intel_async_flip_check_hw()
6612 			drm_dbg_kms(&i915->drm,  in intel_async_flip_check_hw()
6614 				    plane->base.base.id, plane->base.name);  in intel_async_flip_check_hw()
6615 			return -EINVAL;  in intel_async_flip_check_hw()
6619 		if (old_plane_state->decrypt != new_plane_state->decrypt) {  in intel_async_flip_check_hw()
6620 			drm_dbg_kms(&i915->drm,  in intel_async_flip_check_hw()
6622 				    plane->base.base.id, plane->base.name);  in intel_async_flip_check_hw()
6623 			return -EINVAL;  in intel_async_flip_check_hw()
6632 	struct drm_i915_private *i915 = to_i915(state->base.dev);  in intel_joiner_add_affected_crtcs()
6647 		crtc = to_intel_crtc(plane_state->hw.crtc);  in intel_joiner_add_affected_crtcs()
6651 		crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);  in intel_joiner_add_affected_crtcs()
6658 		affected_pipes |= crtc_state->joiner_pipes;  in intel_joiner_add_affected_crtcs()
6660 			modeset_pipes |= crtc_state->joiner_pipes;  in intel_joiner_add_affected_crtcs()
6663 	for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, affected_pipes) {  in intel_joiner_add_affected_crtcs()
6664 		crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);  in intel_joiner_add_affected_crtcs()
6669 	for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, modeset_pipes) {  in intel_joiner_add_affected_crtcs()
6674 		crtc_state->uapi.mode_changed = true;  in intel_joiner_add_affected_crtcs()
6676 		ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base);  in intel_joiner_add_affected_crtcs()
6686 		/* Kill old joiner link, we may re-establish afterwards */  in intel_joiner_add_affected_crtcs()
6699 	struct drm_i915_private *i915 = to_i915(state->base.dev);  in intel_atomic_check_config()
6724 		if (drm_WARN_ON(&i915->drm, intel_crtc_is_joiner_secondary(new_crtc_state)))  in intel_atomic_check_config()
6731 		if (!new_crtc_state->hw.enable)  in intel_atomic_check_config()
6743 		if (drm_WARN_ON(&i915->drm, intel_crtc_is_joiner_secondary(new_crtc_state)))  in intel_atomic_check_config()
6746 		if (!new_crtc_state->hw.enable)  in intel_atomic_check_config()
6756 		*failed_pipe = crtc->pipe;  in intel_atomic_check_config()
6780 			if (ret == -EINVAL &&  in intel_atomic_check_config_and_link()
6793 		if (ret != -EAGAIN)  in intel_atomic_check_config_and_link()
6800  * intel_atomic_check - validate state object
6816 		return -ENODEV;  in intel_atomic_check()
6824 		if (!state->internal)  in intel_atomic_check()
6825 			new_crtc_state->inherited = false;  in intel_atomic_check()
6827 		if (new_crtc_state->inherited != old_crtc_state->inherited)  in intel_atomic_check()
6828 			new_crtc_state->uapi.mode_changed = true;  in intel_atomic_check()
6830 		if (new_crtc_state->uapi.scaling_filter !=  in intel_atomic_check()
6831 		    old_crtc_state->uapi.scaling_filter)  in intel_atomic_check()
6832 			new_crtc_state->uapi.mode_changed = true;  in intel_atomic_check()
6837 	ret = drm_atomic_helper_check_modeset(dev, &state->base);  in intel_atomic_check()
6856 			drm_WARN_ON(&dev_priv->drm, new_crtc_state->uapi.enable);  in intel_atomic_check()
6887 		if (!new_crtc_state->hw.enable || intel_crtc_needs_modeset(new_crtc_state))  in intel_atomic_check()
6894 			enum transcoder master = new_crtc_state->mst_master_transcoder;  in intel_atomic_check()
6901 			u8 trans = new_crtc_state->sync_mode_slaves_mask;  in intel_atomic_check()
6903 			if (new_crtc_state->master_transcoder != INVALID_TRANSCODER)  in intel_atomic_check()
6904 				trans |= BIT(new_crtc_state->master_transcoder);  in intel_atomic_check()
6910 		if (new_crtc_state->joiner_pipes) {  in intel_atomic_check()
6911 			if (intel_pipes_need_modeset(state, new_crtc_state->joiner_pipes))  in intel_atomic_check()
6927 		drm_dbg_kms(&dev_priv->drm,  in intel_atomic_check()
6929 		ret = -EINVAL;  in intel_atomic_check()
6983 		drm_WARN_ON(&dev_priv->drm,  in intel_atomic_check()
6999 	if (ret == -EDEADLK)  in intel_atomic_check()
7017 	ret = drm_atomic_helper_prepare_planes(state->base.dev, &state->base);  in intel_atomic_prepare_commit()
7027 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_crtc_arm_fifo_underrun()
7029 	if (DISPLAY_VER(dev_priv) != 2 || crtc_state->active_planes)  in intel_crtc_arm_fifo_underrun()
7030 		intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);  in intel_crtc_arm_fifo_underrun()
7032 	if (crtc_state->has_pch_encoder) {  in intel_crtc_arm_fifo_underrun()
7043 	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);  in intel_pipe_fastset()
7044 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_pipe_fastset()
7058 		if (new_crtc_state->pch_pfit.enabled)  in intel_pipe_fastset()
7061 		if (new_crtc_state->pch_pfit.enabled)  in intel_pipe_fastset()
7063 		else if (old_crtc_state->pch_pfit.enabled)  in intel_pipe_fastset()
7079 	if (new_crtc_state->update_m_n)  in intel_pipe_fastset()
7080 		intel_cpu_transcoder_set_m1_n1(crtc, new_crtc_state->cpu_transcoder,  in intel_pipe_fastset()
7081 					       &new_crtc_state->dp_m_n);  in intel_pipe_fastset()
7083 	if (new_crtc_state->update_lrr)  in intel_pipe_fastset()
7090 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);  in commit_pipe_pre_planes()
7101 	if (!modeset && !new_crtc_state->use_dsb) {  in commit_pipe_pre_planes()
7120 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);  in commit_pipe_post_planes()
7140 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);  in intel_enable_crtc()
7148 	for_each_intel_crtc_in_pipe_mask_reverse(&dev_priv->drm, pipe_crtc,  in intel_enable_crtc()
7157 	dev_priv->display.funcs.display->crtc_enable(state, crtc);  in intel_enable_crtc()
7159 	/* vblanks work again, re-enable pipe CRC. */  in intel_enable_crtc()
7166 	struct drm_i915_private *i915 = to_i915(state->base.dev);  in intel_pre_update_crtc()
7173 	if (old_crtc_state->inherited ||  in intel_pre_update_crtc()
7180 		if (new_crtc_state->preload_luts &&  in intel_pre_update_crtc()
7200 	drm_WARN_ON(&i915->drm, !intel_display_power_is_enabled(i915, POWER_DOMAIN_DC_OFF));  in intel_pre_update_crtc()
7204 	    !new_crtc_state->use_dsb)  in intel_pre_update_crtc()
7207 	if (!new_crtc_state->use_dsb)  in intel_pre_update_crtc()
7219 	if (new_crtc_state->use_dsb) {  in intel_update_crtc()
7220 		intel_crtc_prepare_vblank_event(new_crtc_state, &crtc->dsb_event);  in intel_update_crtc()
7222 		intel_dsb_commit(new_crtc_state->dsb_commit, false);  in intel_update_crtc()
7227 		if (new_crtc_state->dsb_commit)  in intel_update_crtc()
7228 			intel_dsb_commit(new_crtc_state->dsb_commit, false);  in intel_update_crtc()
7245 	    new_crtc_state->update_m_n || new_crtc_state->update_lrr)  in intel_update_crtc()
7247 						 new_crtc_state->vrr.enable);  in intel_update_crtc()
7256 	    old_crtc_state->inherited)  in intel_update_crtc()
7263 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);  in intel_old_crtc_state_disables()
7272 	for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, pipe_crtc,  in intel_old_crtc_state_disables()
7276 	dev_priv->display.funcs.display->crtc_disable(state, crtc);  in intel_old_crtc_state_disables()
7278 	for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, pipe_crtc,  in intel_old_crtc_state_disables()
7283 		pipe_crtc->active = false;  in intel_old_crtc_state_disables()
7286 		if (!new_pipe_crtc_state->hw.active)  in intel_old_crtc_state_disables()
7293 	struct drm_i915_private *i915 = to_i915(state->base.dev);  in intel_commit_modeset_disables()
7310 		if (!old_crtc_state->hw.active)  in intel_commit_modeset_disables()
7313 		disable_pipes |= BIT(crtc->pipe);  in intel_commit_modeset_disables()
7317 		if ((disable_pipes & BIT(crtc->pipe)) == 0)  in intel_commit_modeset_disables()
7322 		drm_vblank_work_flush_all(&crtc->base);  in intel_commit_modeset_disables()
7327 		if ((disable_pipes & BIT(crtc->pipe)) == 0)  in intel_commit_modeset_disables()
7349 		if ((disable_pipes & BIT(crtc->pipe)) == 0)  in intel_commit_modeset_disables()
7360 	drm_WARN_ON(&i915->drm, disable_pipes);  in intel_commit_modeset_disables()
7370 		if (!new_crtc_state->hw.active)  in intel_commit_modeset_enables()
7378 		if (!new_crtc_state->hw.active)  in intel_commit_modeset_enables()
7387 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);  in skl_commit_modeset_enables()
7395 		enum pipe pipe = crtc->pipe;  in skl_commit_modeset_enables()
7397 		if (!new_crtc_state->hw.active)  in skl_commit_modeset_enables()
7402 			entries[pipe] = old_crtc_state->wm.skl.ddb;  in skl_commit_modeset_enables()
7419 		enum pipe pipe = crtc->pipe;  in skl_commit_modeset_enables()
7436 			enum pipe pipe = crtc->pipe;  in skl_commit_modeset_enables()
7441 			if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,  in skl_commit_modeset_enables()
7445 			entries[pipe] = new_crtc_state->wm.skl.ddb;  in skl_commit_modeset_enables()
7456 			if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb,  in skl_commit_modeset_enables()
7457 						 &old_crtc_state->wm.skl.ddb) &&  in skl_commit_modeset_enables()
7472 		enum pipe pipe = crtc->pipe;  in skl_commit_modeset_enables()
7494 		enum pipe pipe = crtc->pipe;  in skl_commit_modeset_enables()
7511 		enum pipe pipe = crtc->pipe;  in skl_commit_modeset_enables()
7524 		enum pipe pipe = crtc->pipe;  in skl_commit_modeset_enables()
7529 		drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,  in skl_commit_modeset_enables()
7532 		entries[pipe] = new_crtc_state->wm.skl.ddb;  in skl_commit_modeset_enables()
7538 	drm_WARN_ON(&dev_priv->drm, modeset_pipes);  in skl_commit_modeset_enables()
7539 	drm_WARN_ON(&dev_priv->drm, update_pipes);  in skl_commit_modeset_enables()
7544 	struct drm_i915_private *i915 = to_i915(intel_state->base.dev);  in intel_atomic_commit_fence_wait()
7549 	for_each_new_plane_in_state(&intel_state->base, plane, new_plane_state, i) {  in intel_atomic_commit_fence_wait()
7550 		if (new_plane_state->fence) {  in intel_atomic_commit_fence_wait()
7551 			ret = dma_fence_wait_timeout(new_plane_state->fence, false,  in intel_atomic_commit_fence_wait()
7556 			dma_fence_put(new_plane_state->fence);  in intel_atomic_commit_fence_wait()
7557 			new_plane_state->fence = NULL;  in intel_atomic_commit_fence_wait()
7564 	if (crtc_state->dsb_commit)  in intel_atomic_dsb_wait_commit()
7565 		intel_dsb_wait(crtc_state->dsb_commit);  in intel_atomic_dsb_wait_commit()
7572 	if (crtc_state->dsb_commit) {  in intel_atomic_dsb_cleanup()
7573 		intel_dsb_cleanup(crtc_state->dsb_commit);  in intel_atomic_dsb_cleanup()
7574 		crtc_state->dsb_commit = NULL;  in intel_atomic_dsb_cleanup()
7584 	struct drm_i915_private *i915 = to_i915(state->base.dev);  in intel_atomic_cleanup_work()
7592 	drm_atomic_helper_cleanup_planes(&i915->drm, &state->base);  in intel_atomic_cleanup_work()
7593 	drm_atomic_helper_commit_cleanup_done(&state->base);  in intel_atomic_cleanup_work()
7594 	drm_atomic_state_put(&state->base);  in intel_atomic_cleanup_work()
7599 	struct drm_i915_private *i915 = to_i915(state->base.dev);  in intel_atomic_prepare_plane_clear_colors()
7605 		struct drm_framebuffer *fb = plane_state->hw.fb;  in intel_atomic_prepare_plane_clear_colors()
7621 		 * - 4 x 4 bytes per-channel value  in intel_atomic_prepare_plane_clear_colors()
7623 		 * - 8 bytes native color value used by the display  in intel_atomic_prepare_plane_clear_colors()
7625 		 *    above per-channel values)  in intel_atomic_prepare_plane_clear_colors()
7632 					      fb->offsets[cc_plane] + 16,  in intel_atomic_prepare_plane_clear_colors()
7633 					      &plane_state->ccval,  in intel_atomic_prepare_plane_clear_colors()
7634 					      sizeof(plane_state->ccval));  in intel_atomic_prepare_plane_clear_colors()
7636 		drm_WARN_ON(&i915->drm, ret);  in intel_atomic_prepare_plane_clear_colors()
7654 	if (!new_crtc_state->hw.active)  in intel_atomic_dsb_finish()
7657 	if (state->base.legacy_cursor_update)  in intel_atomic_dsb_finish()
7661 	new_crtc_state->use_dsb =  in intel_atomic_dsb_finish()
7662 		new_crtc_state->update_planes &&  in intel_atomic_dsb_finish()
7663 		!new_crtc_state->vrr.enable &&  in intel_atomic_dsb_finish()
7664 		!new_crtc_state->do_async_flip &&  in intel_atomic_dsb_finish()
7665 		!new_crtc_state->has_psr &&  in intel_atomic_dsb_finish()
7666 		!new_crtc_state->scaler_state.scaler_users &&  in intel_atomic_dsb_finish()
7667 		!old_crtc_state->scaler_state.scaler_users &&  in intel_atomic_dsb_finish()
7671 	if (!new_crtc_state->use_dsb && !new_crtc_state->dsb_color_vblank)  in intel_atomic_dsb_finish()
7679 	new_crtc_state->dsb_commit = intel_dsb_prepare(state, crtc, INTEL_DSB_0,  in intel_atomic_dsb_finish()
7680 						       new_crtc_state->use_dsb ? 1024 : 16);  in intel_atomic_dsb_finish()
7681 	if (!new_crtc_state->dsb_commit) {  in intel_atomic_dsb_finish()
7682 		new_crtc_state->use_dsb = false;  in intel_atomic_dsb_finish()
7687 	if (new_crtc_state->use_dsb) {  in intel_atomic_dsb_finish()
7689 			intel_color_commit_noarm(new_crtc_state->dsb_commit,  in intel_atomic_dsb_finish()
7691 		intel_crtc_planes_update_noarm(new_crtc_state->dsb_commit,  in intel_atomic_dsb_finish()
7694 		intel_dsb_vblank_evade(state, new_crtc_state->dsb_commit);  in intel_atomic_dsb_finish()
7697 			intel_color_commit_arm(new_crtc_state->dsb_commit,  in intel_atomic_dsb_finish()
7699 		bdw_set_pipe_misc(new_crtc_state->dsb_commit,  in intel_atomic_dsb_finish()
7701 		intel_crtc_planes_update_arm(new_crtc_state->dsb_commit,  in intel_atomic_dsb_finish()
7704 		if (!new_crtc_state->dsb_color_vblank) {  in intel_atomic_dsb_finish()
7705 			intel_dsb_wait_vblanks(new_crtc_state->dsb_commit, 1);  in intel_atomic_dsb_finish()
7706 			intel_dsb_wait_vblank_delay(state, new_crtc_state->dsb_commit);  in intel_atomic_dsb_finish()
7707 			intel_dsb_interrupt(new_crtc_state->dsb_commit);  in intel_atomic_dsb_finish()
7711 	if (new_crtc_state->dsb_color_vblank)  in intel_atomic_dsb_finish()
7712 		intel_dsb_chain(state, new_crtc_state->dsb_commit,  in intel_atomic_dsb_finish()
7713 				new_crtc_state->dsb_color_vblank, true);  in intel_atomic_dsb_finish()
7715 	intel_dsb_finish(new_crtc_state->dsb_commit);  in intel_atomic_dsb_finish()
7720 	struct drm_device *dev = state->base.dev;  in intel_atomic_commit_tail()
7740 	drm_atomic_helper_wait_for_dependencies(&state->base);  in intel_atomic_commit_tail()
7741 	drm_dp_mst_atomic_wait_for_dependencies(&state->base);  in intel_atomic_commit_tail()
7753 	 * 3. Due to some long delay PSR is re-entered  in intel_atomic_commit_tail()
7754 	 * 4. DC5 entry -> DMC saves the already written new  in intel_atomic_commit_tail()
7757 	 * 5. DC5 exit -> DMC restores a mixture of old and  in intel_atomic_commit_tail()
7759 	 * 6. PSR exit -> hardware latches a mixture of old and  in intel_atomic_commit_tail()
7760 	 *    new register values -> corrupted frame, or worse  in intel_atomic_commit_tail()
7777 			intel_modeset_get_crtc_power_domains(new_crtc_state, &put_domains[crtc->pipe]);  in intel_atomic_commit_tail()
7784 	/* FIXME: Eventually get rid of our crtc->config pointer */  in intel_atomic_commit_tail()
7786 		crtc->config = new_crtc_state;  in intel_atomic_commit_tail()
7796 	if (state->modeset) {  in intel_atomic_commit_tail()
7797 		drm_atomic_helper_update_legacy_modeset_state(dev, &state->base);  in intel_atomic_commit_tail()
7811 		if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) {  in intel_atomic_commit_tail()
7812 			spin_lock_irq(&dev->event_lock);  in intel_atomic_commit_tail()
7813 			drm_crtc_send_vblank_event(&crtc->base,  in intel_atomic_commit_tail()
7814 						   new_crtc_state->uapi.event);  in intel_atomic_commit_tail()
7815 			spin_unlock_irq(&dev->event_lock);  in intel_atomic_commit_tail()
7817 			new_crtc_state->uapi.event = NULL;  in intel_atomic_commit_tail()
7826 		if (new_crtc_state->do_async_flip)  in intel_atomic_commit_tail()
7831 	dev_priv->display.funcs.display->commit_modeset_enables(state);  in intel_atomic_commit_tail()
7840 	 * - wrap the optimization/post_plane_update stuff into a per-crtc work.  in intel_atomic_commit_tail()
7841 	 * - schedule that vblank worker _before_ calling hw_done  in intel_atomic_commit_tail()
7842 	 * - at the start of commit_tail, cancel it _synchrously  in intel_atomic_commit_tail()
7843 	 * - switch over to the vblank wait helper in the core after that since  in intel_atomic_commit_tail()
7846 	drm_atomic_helper_wait_for_flip_done(dev, &state->base);  in intel_atomic_commit_tail()
7849 		if (new_crtc_state->do_async_flip)  in intel_atomic_commit_tail()
7857 	 * optimal watermarks on platforms that need two-step watermark  in intel_atomic_commit_tail()
7866 		 * So re-enable underrun reporting after some planes get enabled.  in intel_atomic_commit_tail()
7873 			intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);  in intel_atomic_commit_tail()
7883 		intel_modeset_put_crtc_power_domains(crtc, &put_domains[crtc->pipe]);  in intel_atomic_commit_tail()
7894 		 * FIXME get rid of this funny new->old swapping  in intel_atomic_commit_tail()
7896 		old_crtc_state->dsb_color_vblank = fetch_and_zero(&new_crtc_state->dsb_color_vblank);  in intel_atomic_commit_tail()
7897 		old_crtc_state->dsb_commit = fetch_and_zero(&new_crtc_state->dsb_commit);  in intel_atomic_commit_tail()
7904 	if (state->modeset)  in intel_atomic_commit_tail()
7908 	if (state->modeset)  in intel_atomic_commit_tail()
7912 	drm_atomic_helper_commit_hw_done(&state->base);  in intel_atomic_commit_tail()
7915 	if (state->modeset) {  in intel_atomic_commit_tail()
7919 		 * so enable debugging for the next modeset - and hope we catch  in intel_atomic_commit_tail()
7922 		intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);  in intel_atomic_commit_tail()
7925 	 * Delay re-enabling DC states by 17 ms to avoid the off->on->off  in intel_atomic_commit_tail()
7929 	intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);  in intel_atomic_commit_tail()
7934 	 * are executed inline. For out-of-line asynchronous modesets/flips,  in intel_atomic_commit_tail()
7939 	INIT_WORK(&state->cleanup_work, intel_atomic_cleanup_work);  in intel_atomic_commit_tail()
7940 	queue_work(dev_priv->display.wq.cleanup, &state->cleanup_work);  in intel_atomic_commit_tail()
7959 		intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),  in intel_atomic_track_fbs()
7960 					to_intel_frontbuffer(new_plane_state->hw.fb),  in intel_atomic_track_fbs()
7961 					plane->frontbuffer_bit);  in intel_atomic_track_fbs()
7968 	ret = drm_atomic_helper_setup_commit(&state->base, nonblock);  in intel_atomic_setup_commit()
7983 	ret = drm_atomic_helper_swap_state(&state->base, true);  in intel_atomic_swap_state()
8003 	state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);  in intel_atomic_commit()
8013 	 * Unset state->legacy_cursor_update before the call to  in intel_atomic_commit()
8022 	if (DISPLAY_VER(dev_priv) < 9 && state->base.legacy_cursor_update) {  in intel_atomic_commit()
8028 			if (new_crtc_state->wm.need_postvbl_update ||  in intel_atomic_commit()
8029 			    new_crtc_state->update_wm_post)  in intel_atomic_commit()
8030 				state->base.legacy_cursor_update = false;  in intel_atomic_commit()
8035 		drm_dbg_atomic(&dev_priv->drm,  in intel_atomic_commit()
8037 		intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);  in intel_atomic_commit()
8046 		drm_atomic_helper_unprepare_planes(dev, &state->base);  in intel_atomic_commit()
8047 		intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);  in intel_atomic_commit()
8051 	drm_atomic_state_get(&state->base);  in intel_atomic_commit()
8052 	INIT_WORK(&state->base.commit_work, intel_atomic_commit_work);  in intel_atomic_commit()
8054 	if (nonblock && state->modeset) {  in intel_atomic_commit()
8055 		queue_work(dev_priv->display.wq.modeset, &state->base.commit_work);  in intel_atomic_commit()
8057 		queue_work(dev_priv->display.wq.flip, &state->base.commit_work);  in intel_atomic_commit()
8059 		if (state->modeset)  in intel_atomic_commit()
8060 			flush_workqueue(dev_priv->display.wq.modeset);  in intel_atomic_commit()
8068  * intel_plane_destroy - destroy a plane
8082 	struct drm_device *dev = encoder->base.dev;  in intel_encoder_possible_clones()
8088 			possible_clones |= drm_encoder_mask(&source_encoder->base);  in intel_encoder_possible_clones()
8096 	struct drm_device *dev = encoder->base.dev;  in intel_encoder_possible_crtcs()
8100 	for_each_intel_crtc_in_pipe_mask(dev, crtc, encoder->pipe_mask)  in intel_encoder_possible_crtcs()
8101 		possible_crtcs |= drm_crtc_mask(&crtc->base);  in intel_encoder_possible_crtcs()
8136 	if (!dev_priv->display.vbt.int_crt_support)  in intel_ddi_crt_present()
8144 	return !drm_WARN(&i915->drm, !(DISPLAY_RUNTIME_INFO(i915)->port_mask & BIT(port)),  in assert_port_valid()
8150 	struct intel_display *display = &dev_priv->display;  in intel_setup_outputs()
8206 		if (IS_VALLEYVIEW(dev_priv) && dev_priv->display.vbt.int_crt_support)  in intel_setup_outputs()
8212 		 * (no way to plug in a DP->HDMI dongle) the DDC pins for  in intel_setup_outputs()
8219 		 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap  in intel_setup_outputs()
8263 			drm_dbg_kms(&dev_priv->drm, "probing SDVOB\n");  in intel_setup_outputs()
8266 				drm_dbg_kms(&dev_priv->drm,  in intel_setup_outputs()
8278 			drm_dbg_kms(&dev_priv->drm, "probing SDVOC\n");  in intel_setup_outputs()
8285 				drm_dbg_kms(&dev_priv->drm,  in intel_setup_outputs()
8306 	for_each_intel_encoder(&dev_priv->drm, encoder) {  in intel_setup_outputs()
8307 		encoder->base.possible_crtcs =  in intel_setup_outputs()
8309 		encoder->base.possible_clones =  in intel_setup_outputs()
8315 	drm_helper_move_panel_connectors_to_head(&dev_priv->drm);  in intel_setup_outputs()
8320 	struct intel_display *display = &i915->display;  in max_dotclock()
8321 	int max_dotclock = display->cdclk.max_dotclk_freq;  in max_dotclock()
8346 	 * reject modes with the DBLSCAN flag in encoder->compute_config().  in intel_mode_valid()
8347 	 * And we always reject DBLSCAN modes in connector->mode_valid()  in intel_mode_valid()
8351 	if (mode->vscan > 1)  in intel_mode_valid()
8354 	if (mode->flags & DRM_MODE_FLAG_HSKEW)  in intel_mode_valid()
8357 	if (mode->flags & (DRM_MODE_FLAG_CSYNC |  in intel_mode_valid()
8362 	if (mode->flags & (DRM_MODE_FLAG_BCAST |  in intel_mode_valid()
8371 	if (mode->clock > max_dotclock(dev_priv))  in intel_mode_valid()
8398 	if (mode->hdisplay > hdisplay_max ||  in intel_mode_valid()
8399 	    mode->hsync_start > htotal_max ||  in intel_mode_valid()
8400 	    mode->hsync_end > htotal_max ||  in intel_mode_valid()
8401 	    mode->htotal > htotal_max)  in intel_mode_valid()
8404 	if (mode->vdisplay > vdisplay_max ||  in intel_mode_valid()
8405 	    mode->vsync_start > vtotal_max ||  in intel_mode_valid()
8406 	    mode->vsync_end > vtotal_max ||  in intel_mode_valid()
8407 	    mode->vtotal > vtotal_max)  in intel_mode_valid()
8421 		if (mode->hdisplay < 64 ||  in intel_cpu_transcoder_mode_valid()
8422 		    mode->htotal - mode->hdisplay < 32)  in intel_cpu_transcoder_mode_valid()
8425 		if (mode->vtotal - mode->vdisplay < 5)  in intel_cpu_transcoder_mode_valid()
8428 		if (mode->htotal - mode->hdisplay < 32)  in intel_cpu_transcoder_mode_valid()
8431 		if (mode->vtotal - mode->vdisplay < 3)  in intel_cpu_transcoder_mode_valid()
8440 	    mode->hsync_start == mode->hdisplay)  in intel_cpu_transcoder_mode_valid()
8476 	if (mode->hdisplay > plane_width_max)  in intel_mode_valid_max_plane_size()
8479 	if (mode->vdisplay > plane_height_max)  in intel_mode_valid_max_plane_size()
8531  * intel_init_display_hooks - initialize the display modesetting hooks
8537 		dev_priv->display.funcs.display = &skl_display_funcs;  in intel_init_display_hooks()
8539 		dev_priv->display.funcs.display = &ddi_display_funcs;  in intel_init_display_hooks()
8541 		dev_priv->display.funcs.display = &pch_split_display_funcs;  in intel_init_display_hooks()
8544 		dev_priv->display.funcs.display = &vlv_display_funcs;  in intel_init_display_hooks()
8546 		dev_priv->display.funcs.display = &i9xx_display_funcs;  in intel_init_display_hooks()
8559 		return -ENOMEM;  in intel_initial_commit()
8563 	state->acquire_ctx = &ctx;  in intel_initial_commit()
8564 	to_intel_atomic_state(state)->internal = true;  in intel_initial_commit()
8576 		if (crtc_state->hw.active) {  in intel_initial_commit()
8579 			ret = drm_atomic_add_affected_planes(state, &crtc->base);  in intel_initial_commit()
8589 			crtc_state->uapi.color_mgmt_changed = true;  in intel_initial_commit()
8592 						    crtc_state->uapi.encoder_mask) {  in intel_initial_commit()
8593 				if (encoder->initial_fastset_check &&  in intel_initial_commit()
8594 				    !encoder->initial_fastset_check(encoder, crtc_state)) {  in intel_initial_commit()
8596 										 &crtc->base);  in intel_initial_commit()
8607 	if (ret == -EDEADLK) {  in intel_initial_commit()
8636 	drm_WARN_ON(display->drm,  in i830_enable_pipe()
8639 	drm_dbg_kms(display->drm,  in i830_enable_pipe()
8646 		((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |  in i830_enable_pipe()
8652 		       HACTIVE(640 - 1) | HTOTAL(800 - 1));  in i830_enable_pipe()
8654 		       HBLANK_START(640 - 1) | HBLANK_END(800 - 1));  in i830_enable_pipe()
8656 		       HSYNC_START(656 - 1) | HSYNC_END(752 - 1));  in i830_enable_pipe()
8658 		       VACTIVE(480 - 1) | VTOTAL(525 - 1));  in i830_enable_pipe()
8660 		       VBLANK_START(480 - 1) | VBLANK_END(525 - 1));  in i830_enable_pipe()
8662 		       VSYNC_START(490 - 1) | VSYNC_END(492 - 1));  in i830_enable_pipe()
8664 		       PIPESRC_WIDTH(640 - 1) | PIPESRC_HEIGHT(480 - 1));  in i830_enable_pipe()
8706 	drm_dbg_kms(display->drm, "disabling pipe %c due to force quirk\n",  in i830_disable_pipe()
8709 	drm_WARN_ON(display->drm,  in i830_disable_pipe()
8711 	drm_WARN_ON(display->drm,  in i830_disable_pipe()
8713 	drm_WARN_ON(display->drm,  in i830_disable_pipe()
8715 	drm_WARN_ON(display->drm,  in i830_disable_pipe()
8717 	drm_WARN_ON(display->drm,  in i830_disable_pipe()
8735 	drm_connector_list_iter_begin(&i915->drm, &conn_iter);  in intel_hpd_poll_fini()
8737 		if (connector->modeset_retry_work.func &&  in intel_hpd_poll_fini()
8738 		    cancel_work_sync(&connector->modeset_retry_work))  in intel_hpd_poll_fini()
8739 			drm_connector_put(&connector->base);  in intel_hpd_poll_fini()
8740 		if (connector->hdcp.shim) {  in intel_hpd_poll_fini()
8741 			cancel_delayed_work_sync(&connector->hdcp.check_work);  in intel_hpd_poll_fini()
8742 			cancel_work_sync(&connector->hdcp.prop_work);  in intel_hpd_poll_fini()