1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /*
3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7 #include <linux/ieee80211.h>
8 #include <linux/kernel.h>
9 #include <linux/skbuff.h>
10 #include <crypto/hash.h>
11 #include "core.h"
12 #include "debug.h"
13 #include "hal_desc.h"
14 #include "hw.h"
15 #include "dp_rx.h"
16 #include "hal_rx.h"
17 #include "dp_tx.h"
18 #include "peer.h"
19 #include "dp_mon.h"
20 #include "debugfs_htt_stats.h"
21
22 #define ATH12K_DP_RX_FRAGMENT_TIMEOUT_MS (2 * HZ)
23
ath12k_dp_rx_h_enctype(struct ath12k_base * ab,struct hal_rx_desc * desc)24 static enum hal_encrypt_type ath12k_dp_rx_h_enctype(struct ath12k_base *ab,
25 struct hal_rx_desc *desc)
26 {
27 if (!ab->hal_rx_ops->rx_desc_encrypt_valid(desc))
28 return HAL_ENCRYPT_TYPE_OPEN;
29
30 return ab->hal_rx_ops->rx_desc_get_encrypt_type(desc);
31 }
32
ath12k_dp_rx_h_decap_type(struct ath12k_base * ab,struct hal_rx_desc * desc)33 u8 ath12k_dp_rx_h_decap_type(struct ath12k_base *ab,
34 struct hal_rx_desc *desc)
35 {
36 return ab->hal_rx_ops->rx_desc_get_decap_type(desc);
37 }
38
ath12k_dp_rx_h_mesh_ctl_present(struct ath12k_base * ab,struct hal_rx_desc * desc)39 static u8 ath12k_dp_rx_h_mesh_ctl_present(struct ath12k_base *ab,
40 struct hal_rx_desc *desc)
41 {
42 return ab->hal_rx_ops->rx_desc_get_mesh_ctl(desc);
43 }
44
ath12k_dp_rx_h_seq_ctrl_valid(struct ath12k_base * ab,struct hal_rx_desc * desc)45 static bool ath12k_dp_rx_h_seq_ctrl_valid(struct ath12k_base *ab,
46 struct hal_rx_desc *desc)
47 {
48 return ab->hal_rx_ops->rx_desc_get_mpdu_seq_ctl_vld(desc);
49 }
50
ath12k_dp_rx_h_fc_valid(struct ath12k_base * ab,struct hal_rx_desc * desc)51 static bool ath12k_dp_rx_h_fc_valid(struct ath12k_base *ab,
52 struct hal_rx_desc *desc)
53 {
54 return ab->hal_rx_ops->rx_desc_get_mpdu_fc_valid(desc);
55 }
56
ath12k_dp_rx_h_more_frags(struct ath12k_base * ab,struct sk_buff * skb)57 static bool ath12k_dp_rx_h_more_frags(struct ath12k_base *ab,
58 struct sk_buff *skb)
59 {
60 struct ieee80211_hdr *hdr;
61
62 hdr = (struct ieee80211_hdr *)(skb->data + ab->hal.hal_desc_sz);
63 return ieee80211_has_morefrags(hdr->frame_control);
64 }
65
ath12k_dp_rx_h_frag_no(struct ath12k_base * ab,struct sk_buff * skb)66 static u16 ath12k_dp_rx_h_frag_no(struct ath12k_base *ab,
67 struct sk_buff *skb)
68 {
69 struct ieee80211_hdr *hdr;
70
71 hdr = (struct ieee80211_hdr *)(skb->data + ab->hal.hal_desc_sz);
72 return le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG;
73 }
74
ath12k_dp_rx_h_seq_no(struct ath12k_base * ab,struct hal_rx_desc * desc)75 static u16 ath12k_dp_rx_h_seq_no(struct ath12k_base *ab,
76 struct hal_rx_desc *desc)
77 {
78 return ab->hal_rx_ops->rx_desc_get_mpdu_start_seq_no(desc);
79 }
80
ath12k_dp_rx_h_msdu_done(struct ath12k_base * ab,struct hal_rx_desc * desc)81 static bool ath12k_dp_rx_h_msdu_done(struct ath12k_base *ab,
82 struct hal_rx_desc *desc)
83 {
84 return ab->hal_rx_ops->dp_rx_h_msdu_done(desc);
85 }
86
ath12k_dp_rx_h_l4_cksum_fail(struct ath12k_base * ab,struct hal_rx_desc * desc)87 static bool ath12k_dp_rx_h_l4_cksum_fail(struct ath12k_base *ab,
88 struct hal_rx_desc *desc)
89 {
90 return ab->hal_rx_ops->dp_rx_h_l4_cksum_fail(desc);
91 }
92
ath12k_dp_rx_h_ip_cksum_fail(struct ath12k_base * ab,struct hal_rx_desc * desc)93 static bool ath12k_dp_rx_h_ip_cksum_fail(struct ath12k_base *ab,
94 struct hal_rx_desc *desc)
95 {
96 return ab->hal_rx_ops->dp_rx_h_ip_cksum_fail(desc);
97 }
98
ath12k_dp_rx_h_is_decrypted(struct ath12k_base * ab,struct hal_rx_desc * desc)99 static bool ath12k_dp_rx_h_is_decrypted(struct ath12k_base *ab,
100 struct hal_rx_desc *desc)
101 {
102 return ab->hal_rx_ops->dp_rx_h_is_decrypted(desc);
103 }
104
ath12k_dp_rx_h_mpdu_err(struct ath12k_base * ab,struct hal_rx_desc * desc)105 u32 ath12k_dp_rx_h_mpdu_err(struct ath12k_base *ab,
106 struct hal_rx_desc *desc)
107 {
108 return ab->hal_rx_ops->dp_rx_h_mpdu_err(desc);
109 }
110
ath12k_dp_rx_h_msdu_len(struct ath12k_base * ab,struct hal_rx_desc * desc)111 static u16 ath12k_dp_rx_h_msdu_len(struct ath12k_base *ab,
112 struct hal_rx_desc *desc)
113 {
114 return ab->hal_rx_ops->rx_desc_get_msdu_len(desc);
115 }
116
ath12k_dp_rx_h_sgi(struct ath12k_base * ab,struct hal_rx_desc * desc)117 static u8 ath12k_dp_rx_h_sgi(struct ath12k_base *ab,
118 struct hal_rx_desc *desc)
119 {
120 return ab->hal_rx_ops->rx_desc_get_msdu_sgi(desc);
121 }
122
ath12k_dp_rx_h_rate_mcs(struct ath12k_base * ab,struct hal_rx_desc * desc)123 static u8 ath12k_dp_rx_h_rate_mcs(struct ath12k_base *ab,
124 struct hal_rx_desc *desc)
125 {
126 return ab->hal_rx_ops->rx_desc_get_msdu_rate_mcs(desc);
127 }
128
ath12k_dp_rx_h_rx_bw(struct ath12k_base * ab,struct hal_rx_desc * desc)129 static u8 ath12k_dp_rx_h_rx_bw(struct ath12k_base *ab,
130 struct hal_rx_desc *desc)
131 {
132 return ab->hal_rx_ops->rx_desc_get_msdu_rx_bw(desc);
133 }
134
ath12k_dp_rx_h_freq(struct ath12k_base * ab,struct hal_rx_desc * desc)135 static u32 ath12k_dp_rx_h_freq(struct ath12k_base *ab,
136 struct hal_rx_desc *desc)
137 {
138 return ab->hal_rx_ops->rx_desc_get_msdu_freq(desc);
139 }
140
ath12k_dp_rx_h_pkt_type(struct ath12k_base * ab,struct hal_rx_desc * desc)141 static u8 ath12k_dp_rx_h_pkt_type(struct ath12k_base *ab,
142 struct hal_rx_desc *desc)
143 {
144 return ab->hal_rx_ops->rx_desc_get_msdu_pkt_type(desc);
145 }
146
ath12k_dp_rx_h_nss(struct ath12k_base * ab,struct hal_rx_desc * desc)147 static u8 ath12k_dp_rx_h_nss(struct ath12k_base *ab,
148 struct hal_rx_desc *desc)
149 {
150 return hweight8(ab->hal_rx_ops->rx_desc_get_msdu_nss(desc));
151 }
152
ath12k_dp_rx_h_tid(struct ath12k_base * ab,struct hal_rx_desc * desc)153 static u8 ath12k_dp_rx_h_tid(struct ath12k_base *ab,
154 struct hal_rx_desc *desc)
155 {
156 return ab->hal_rx_ops->rx_desc_get_mpdu_tid(desc);
157 }
158
ath12k_dp_rx_h_peer_id(struct ath12k_base * ab,struct hal_rx_desc * desc)159 static u16 ath12k_dp_rx_h_peer_id(struct ath12k_base *ab,
160 struct hal_rx_desc *desc)
161 {
162 return ab->hal_rx_ops->rx_desc_get_mpdu_peer_id(desc);
163 }
164
ath12k_dp_rx_h_l3pad(struct ath12k_base * ab,struct hal_rx_desc * desc)165 u8 ath12k_dp_rx_h_l3pad(struct ath12k_base *ab,
166 struct hal_rx_desc *desc)
167 {
168 return ab->hal_rx_ops->rx_desc_get_l3_pad_bytes(desc);
169 }
170
ath12k_dp_rx_h_first_msdu(struct ath12k_base * ab,struct hal_rx_desc * desc)171 static bool ath12k_dp_rx_h_first_msdu(struct ath12k_base *ab,
172 struct hal_rx_desc *desc)
173 {
174 return ab->hal_rx_ops->rx_desc_get_first_msdu(desc);
175 }
176
ath12k_dp_rx_h_last_msdu(struct ath12k_base * ab,struct hal_rx_desc * desc)177 static bool ath12k_dp_rx_h_last_msdu(struct ath12k_base *ab,
178 struct hal_rx_desc *desc)
179 {
180 return ab->hal_rx_ops->rx_desc_get_last_msdu(desc);
181 }
182
ath12k_dp_rx_desc_end_tlv_copy(struct ath12k_base * ab,struct hal_rx_desc * fdesc,struct hal_rx_desc * ldesc)183 static void ath12k_dp_rx_desc_end_tlv_copy(struct ath12k_base *ab,
184 struct hal_rx_desc *fdesc,
185 struct hal_rx_desc *ldesc)
186 {
187 ab->hal_rx_ops->rx_desc_copy_end_tlv(fdesc, ldesc);
188 }
189
ath12k_dp_rxdesc_set_msdu_len(struct ath12k_base * ab,struct hal_rx_desc * desc,u16 len)190 static void ath12k_dp_rxdesc_set_msdu_len(struct ath12k_base *ab,
191 struct hal_rx_desc *desc,
192 u16 len)
193 {
194 ab->hal_rx_ops->rx_desc_set_msdu_len(desc, len);
195 }
196
ath12k_dp_rx_h_is_da_mcbc(struct ath12k_base * ab,struct hal_rx_desc * desc)197 static bool ath12k_dp_rx_h_is_da_mcbc(struct ath12k_base *ab,
198 struct hal_rx_desc *desc)
199 {
200 return (ath12k_dp_rx_h_first_msdu(ab, desc) &&
201 ab->hal_rx_ops->rx_desc_is_da_mcbc(desc));
202 }
203
ath12k_dp_rxdesc_mac_addr2_valid(struct ath12k_base * ab,struct hal_rx_desc * desc)204 static bool ath12k_dp_rxdesc_mac_addr2_valid(struct ath12k_base *ab,
205 struct hal_rx_desc *desc)
206 {
207 return ab->hal_rx_ops->rx_desc_mac_addr2_valid(desc);
208 }
209
ath12k_dp_rxdesc_get_mpdu_start_addr2(struct ath12k_base * ab,struct hal_rx_desc * desc)210 static u8 *ath12k_dp_rxdesc_get_mpdu_start_addr2(struct ath12k_base *ab,
211 struct hal_rx_desc *desc)
212 {
213 return ab->hal_rx_ops->rx_desc_mpdu_start_addr2(desc);
214 }
215
ath12k_dp_rx_desc_get_dot11_hdr(struct ath12k_base * ab,struct hal_rx_desc * desc,struct ieee80211_hdr * hdr)216 static void ath12k_dp_rx_desc_get_dot11_hdr(struct ath12k_base *ab,
217 struct hal_rx_desc *desc,
218 struct ieee80211_hdr *hdr)
219 {
220 ab->hal_rx_ops->rx_desc_get_dot11_hdr(desc, hdr);
221 }
222
ath12k_dp_rx_desc_get_crypto_header(struct ath12k_base * ab,struct hal_rx_desc * desc,u8 * crypto_hdr,enum hal_encrypt_type enctype)223 static void ath12k_dp_rx_desc_get_crypto_header(struct ath12k_base *ab,
224 struct hal_rx_desc *desc,
225 u8 *crypto_hdr,
226 enum hal_encrypt_type enctype)
227 {
228 ab->hal_rx_ops->rx_desc_get_crypto_header(desc, crypto_hdr, enctype);
229 }
230
ath12k_dp_rxdesc_get_mpdu_frame_ctrl(struct ath12k_base * ab,struct hal_rx_desc * desc)231 static u16 ath12k_dp_rxdesc_get_mpdu_frame_ctrl(struct ath12k_base *ab,
232 struct hal_rx_desc *desc)
233 {
234 return ab->hal_rx_ops->rx_desc_get_mpdu_frame_ctl(desc);
235 }
236
ath12k_dp_rx_get_msdu_src_link(struct ath12k_base * ab,struct hal_rx_desc * desc)237 static inline u8 ath12k_dp_rx_get_msdu_src_link(struct ath12k_base *ab,
238 struct hal_rx_desc *desc)
239 {
240 return ab->hal_rx_ops->rx_desc_get_msdu_src_link_id(desc);
241 }
242
ath12k_dp_clean_up_skb_list(struct sk_buff_head * skb_list)243 static void ath12k_dp_clean_up_skb_list(struct sk_buff_head *skb_list)
244 {
245 struct sk_buff *skb;
246
247 while ((skb = __skb_dequeue(skb_list)))
248 dev_kfree_skb_any(skb);
249 }
250
ath12k_dp_list_cut_nodes(struct list_head * list,struct list_head * head,size_t count)251 static size_t ath12k_dp_list_cut_nodes(struct list_head *list,
252 struct list_head *head,
253 size_t count)
254 {
255 struct list_head *cur;
256 struct ath12k_rx_desc_info *rx_desc;
257 size_t nodes = 0;
258
259 if (!count) {
260 INIT_LIST_HEAD(list);
261 goto out;
262 }
263
264 list_for_each(cur, head) {
265 if (!count)
266 break;
267
268 rx_desc = list_entry(cur, struct ath12k_rx_desc_info, list);
269 rx_desc->in_use = true;
270
271 count--;
272 nodes++;
273 }
274
275 list_cut_before(list, head, cur);
276 out:
277 return nodes;
278 }
279
ath12k_dp_rx_enqueue_free(struct ath12k_dp * dp,struct list_head * used_list)280 static void ath12k_dp_rx_enqueue_free(struct ath12k_dp *dp,
281 struct list_head *used_list)
282 {
283 struct ath12k_rx_desc_info *rx_desc, *safe;
284
285 /* Reset the use flag */
286 list_for_each_entry_safe(rx_desc, safe, used_list, list)
287 rx_desc->in_use = false;
288
289 spin_lock_bh(&dp->rx_desc_lock);
290 list_splice_tail(used_list, &dp->rx_desc_free_list);
291 spin_unlock_bh(&dp->rx_desc_lock);
292 }
293
294 /* Returns number of Rx buffers replenished */
ath12k_dp_rx_bufs_replenish(struct ath12k_base * ab,struct dp_rxdma_ring * rx_ring,struct list_head * used_list,int req_entries)295 int ath12k_dp_rx_bufs_replenish(struct ath12k_base *ab,
296 struct dp_rxdma_ring *rx_ring,
297 struct list_head *used_list,
298 int req_entries)
299 {
300 struct ath12k_buffer_addr *desc;
301 struct hal_srng *srng;
302 struct sk_buff *skb;
303 int num_free;
304 int num_remain;
305 u32 cookie;
306 dma_addr_t paddr;
307 struct ath12k_dp *dp = &ab->dp;
308 struct ath12k_rx_desc_info *rx_desc;
309 enum hal_rx_buf_return_buf_manager mgr = ab->hw_params->hal_params->rx_buf_rbm;
310
311 req_entries = min(req_entries, rx_ring->bufs_max);
312
313 srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id];
314
315 spin_lock_bh(&srng->lock);
316
317 ath12k_hal_srng_access_begin(ab, srng);
318
319 num_free = ath12k_hal_srng_src_num_free(ab, srng, true);
320 if (!req_entries && (num_free > (rx_ring->bufs_max * 3) / 4))
321 req_entries = num_free;
322
323 req_entries = min(num_free, req_entries);
324 num_remain = req_entries;
325
326 if (!num_remain)
327 goto out;
328
329 /* Get the descriptor from free list */
330 if (list_empty(used_list)) {
331 spin_lock_bh(&dp->rx_desc_lock);
332 req_entries = ath12k_dp_list_cut_nodes(used_list,
333 &dp->rx_desc_free_list,
334 num_remain);
335 spin_unlock_bh(&dp->rx_desc_lock);
336 num_remain = req_entries;
337 }
338
339 while (num_remain > 0) {
340 skb = dev_alloc_skb(DP_RX_BUFFER_SIZE +
341 DP_RX_BUFFER_ALIGN_SIZE);
342 if (!skb)
343 break;
344
345 if (!IS_ALIGNED((unsigned long)skb->data,
346 DP_RX_BUFFER_ALIGN_SIZE)) {
347 skb_pull(skb,
348 PTR_ALIGN(skb->data, DP_RX_BUFFER_ALIGN_SIZE) -
349 skb->data);
350 }
351
352 paddr = dma_map_single(ab->dev, skb->data,
353 skb->len + skb_tailroom(skb),
354 DMA_FROM_DEVICE);
355 if (dma_mapping_error(ab->dev, paddr))
356 goto fail_free_skb;
357
358 rx_desc = list_first_entry_or_null(used_list,
359 struct ath12k_rx_desc_info,
360 list);
361 if (!rx_desc)
362 goto fail_dma_unmap;
363
364 rx_desc->skb = skb;
365 cookie = rx_desc->cookie;
366
367 desc = ath12k_hal_srng_src_get_next_entry(ab, srng);
368 if (!desc)
369 goto fail_dma_unmap;
370
371 list_del(&rx_desc->list);
372 ATH12K_SKB_RXCB(skb)->paddr = paddr;
373
374 num_remain--;
375
376 ath12k_hal_rx_buf_addr_info_set(desc, paddr, cookie, mgr);
377 }
378
379 goto out;
380
381 fail_dma_unmap:
382 dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb),
383 DMA_FROM_DEVICE);
384 fail_free_skb:
385 dev_kfree_skb_any(skb);
386 out:
387 ath12k_hal_srng_access_end(ab, srng);
388
389 if (!list_empty(used_list))
390 ath12k_dp_rx_enqueue_free(dp, used_list);
391
392 spin_unlock_bh(&srng->lock);
393
394 return req_entries - num_remain;
395 }
396
ath12k_dp_rxdma_mon_buf_ring_free(struct ath12k_base * ab,struct dp_rxdma_mon_ring * rx_ring)397 static int ath12k_dp_rxdma_mon_buf_ring_free(struct ath12k_base *ab,
398 struct dp_rxdma_mon_ring *rx_ring)
399 {
400 struct sk_buff *skb;
401 int buf_id;
402
403 spin_lock_bh(&rx_ring->idr_lock);
404 idr_for_each_entry(&rx_ring->bufs_idr, skb, buf_id) {
405 idr_remove(&rx_ring->bufs_idr, buf_id);
406 /* TODO: Understand where internal driver does this dma_unmap
407 * of rxdma_buffer.
408 */
409 dma_unmap_single(ab->dev, ATH12K_SKB_RXCB(skb)->paddr,
410 skb->len + skb_tailroom(skb), DMA_FROM_DEVICE);
411 dev_kfree_skb_any(skb);
412 }
413
414 idr_destroy(&rx_ring->bufs_idr);
415 spin_unlock_bh(&rx_ring->idr_lock);
416
417 return 0;
418 }
419
ath12k_dp_rxdma_buf_free(struct ath12k_base * ab)420 static int ath12k_dp_rxdma_buf_free(struct ath12k_base *ab)
421 {
422 struct ath12k_dp *dp = &ab->dp;
423
424 ath12k_dp_rxdma_mon_buf_ring_free(ab, &dp->rxdma_mon_buf_ring);
425
426 return 0;
427 }
428
ath12k_dp_rxdma_mon_ring_buf_setup(struct ath12k_base * ab,struct dp_rxdma_mon_ring * rx_ring,u32 ringtype)429 static int ath12k_dp_rxdma_mon_ring_buf_setup(struct ath12k_base *ab,
430 struct dp_rxdma_mon_ring *rx_ring,
431 u32 ringtype)
432 {
433 int num_entries;
434
435 num_entries = rx_ring->refill_buf_ring.size /
436 ath12k_hal_srng_get_entrysize(ab, ringtype);
437
438 rx_ring->bufs_max = num_entries;
439 ath12k_dp_mon_buf_replenish(ab, rx_ring, num_entries);
440
441 return 0;
442 }
443
ath12k_dp_rxdma_ring_buf_setup(struct ath12k_base * ab,struct dp_rxdma_ring * rx_ring)444 static int ath12k_dp_rxdma_ring_buf_setup(struct ath12k_base *ab,
445 struct dp_rxdma_ring *rx_ring)
446 {
447 LIST_HEAD(list);
448
449 rx_ring->bufs_max = rx_ring->refill_buf_ring.size /
450 ath12k_hal_srng_get_entrysize(ab, HAL_RXDMA_BUF);
451
452 ath12k_dp_rx_bufs_replenish(ab, rx_ring, &list, 0);
453
454 return 0;
455 }
456
ath12k_dp_rxdma_buf_setup(struct ath12k_base * ab)457 static int ath12k_dp_rxdma_buf_setup(struct ath12k_base *ab)
458 {
459 struct ath12k_dp *dp = &ab->dp;
460 int ret;
461
462 ret = ath12k_dp_rxdma_ring_buf_setup(ab, &dp->rx_refill_buf_ring);
463 if (ret) {
464 ath12k_warn(ab,
465 "failed to setup HAL_RXDMA_BUF\n");
466 return ret;
467 }
468
469 if (ab->hw_params->rxdma1_enable) {
470 ret = ath12k_dp_rxdma_mon_ring_buf_setup(ab,
471 &dp->rxdma_mon_buf_ring,
472 HAL_RXDMA_MONITOR_BUF);
473 if (ret) {
474 ath12k_warn(ab,
475 "failed to setup HAL_RXDMA_MONITOR_BUF\n");
476 return ret;
477 }
478 }
479
480 return 0;
481 }
482
ath12k_dp_rx_pdev_srng_free(struct ath12k * ar)483 static void ath12k_dp_rx_pdev_srng_free(struct ath12k *ar)
484 {
485 struct ath12k_pdev_dp *dp = &ar->dp;
486 struct ath12k_base *ab = ar->ab;
487 int i;
488
489 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++)
490 ath12k_dp_srng_cleanup(ab, &dp->rxdma_mon_dst_ring[i]);
491 }
492
ath12k_dp_rx_pdev_reo_cleanup(struct ath12k_base * ab)493 void ath12k_dp_rx_pdev_reo_cleanup(struct ath12k_base *ab)
494 {
495 struct ath12k_dp *dp = &ab->dp;
496 int i;
497
498 for (i = 0; i < DP_REO_DST_RING_MAX; i++)
499 ath12k_dp_srng_cleanup(ab, &dp->reo_dst_ring[i]);
500 }
501
ath12k_dp_rx_pdev_reo_setup(struct ath12k_base * ab)502 int ath12k_dp_rx_pdev_reo_setup(struct ath12k_base *ab)
503 {
504 struct ath12k_dp *dp = &ab->dp;
505 int ret;
506 int i;
507
508 for (i = 0; i < DP_REO_DST_RING_MAX; i++) {
509 ret = ath12k_dp_srng_setup(ab, &dp->reo_dst_ring[i],
510 HAL_REO_DST, i, 0,
511 DP_REO_DST_RING_SIZE);
512 if (ret) {
513 ath12k_warn(ab, "failed to setup reo_dst_ring\n");
514 goto err_reo_cleanup;
515 }
516 }
517
518 return 0;
519
520 err_reo_cleanup:
521 ath12k_dp_rx_pdev_reo_cleanup(ab);
522
523 return ret;
524 }
525
ath12k_dp_rx_pdev_srng_alloc(struct ath12k * ar)526 static int ath12k_dp_rx_pdev_srng_alloc(struct ath12k *ar)
527 {
528 struct ath12k_pdev_dp *dp = &ar->dp;
529 struct ath12k_base *ab = ar->ab;
530 int i;
531 int ret;
532 u32 mac_id = dp->mac_id;
533
534 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) {
535 ret = ath12k_dp_srng_setup(ar->ab,
536 &dp->rxdma_mon_dst_ring[i],
537 HAL_RXDMA_MONITOR_DST,
538 0, mac_id + i,
539 DP_RXDMA_MONITOR_DST_RING_SIZE);
540 if (ret) {
541 ath12k_warn(ar->ab,
542 "failed to setup HAL_RXDMA_MONITOR_DST\n");
543 return ret;
544 }
545 }
546
547 return 0;
548 }
549
ath12k_dp_rx_reo_cmd_list_cleanup(struct ath12k_base * ab)550 void ath12k_dp_rx_reo_cmd_list_cleanup(struct ath12k_base *ab)
551 {
552 struct ath12k_dp *dp = &ab->dp;
553 struct ath12k_dp_rx_reo_cmd *cmd, *tmp;
554 struct ath12k_dp_rx_reo_cache_flush_elem *cmd_cache, *tmp_cache;
555
556 spin_lock_bh(&dp->reo_cmd_lock);
557 list_for_each_entry_safe(cmd, tmp, &dp->reo_cmd_list, list) {
558 list_del(&cmd->list);
559 dma_unmap_single(ab->dev, cmd->data.paddr,
560 cmd->data.size, DMA_BIDIRECTIONAL);
561 kfree(cmd->data.vaddr);
562 kfree(cmd);
563 }
564
565 list_for_each_entry_safe(cmd_cache, tmp_cache,
566 &dp->reo_cmd_cache_flush_list, list) {
567 list_del(&cmd_cache->list);
568 dp->reo_cmd_cache_flush_count--;
569 dma_unmap_single(ab->dev, cmd_cache->data.paddr,
570 cmd_cache->data.size, DMA_BIDIRECTIONAL);
571 kfree(cmd_cache->data.vaddr);
572 kfree(cmd_cache);
573 }
574 spin_unlock_bh(&dp->reo_cmd_lock);
575 }
576
ath12k_dp_reo_cmd_free(struct ath12k_dp * dp,void * ctx,enum hal_reo_cmd_status status)577 static void ath12k_dp_reo_cmd_free(struct ath12k_dp *dp, void *ctx,
578 enum hal_reo_cmd_status status)
579 {
580 struct ath12k_dp_rx_tid *rx_tid = ctx;
581
582 if (status != HAL_REO_CMD_SUCCESS)
583 ath12k_warn(dp->ab, "failed to flush rx tid hw desc, tid %d status %d\n",
584 rx_tid->tid, status);
585
586 dma_unmap_single(dp->ab->dev, rx_tid->paddr, rx_tid->size,
587 DMA_BIDIRECTIONAL);
588 kfree(rx_tid->vaddr);
589 rx_tid->vaddr = NULL;
590 }
591
ath12k_dp_reo_cmd_send(struct ath12k_base * ab,struct ath12k_dp_rx_tid * rx_tid,enum hal_reo_cmd_type type,struct ath12k_hal_reo_cmd * cmd,void (* cb)(struct ath12k_dp * dp,void * ctx,enum hal_reo_cmd_status status))592 static int ath12k_dp_reo_cmd_send(struct ath12k_base *ab, struct ath12k_dp_rx_tid *rx_tid,
593 enum hal_reo_cmd_type type,
594 struct ath12k_hal_reo_cmd *cmd,
595 void (*cb)(struct ath12k_dp *dp, void *ctx,
596 enum hal_reo_cmd_status status))
597 {
598 struct ath12k_dp *dp = &ab->dp;
599 struct ath12k_dp_rx_reo_cmd *dp_cmd;
600 struct hal_srng *cmd_ring;
601 int cmd_num;
602
603 cmd_ring = &ab->hal.srng_list[dp->reo_cmd_ring.ring_id];
604 cmd_num = ath12k_hal_reo_cmd_send(ab, cmd_ring, type, cmd);
605
606 /* cmd_num should start from 1, during failure return the error code */
607 if (cmd_num < 0)
608 return cmd_num;
609
610 /* reo cmd ring descriptors has cmd_num starting from 1 */
611 if (cmd_num == 0)
612 return -EINVAL;
613
614 if (!cb)
615 return 0;
616
617 /* Can this be optimized so that we keep the pending command list only
618 * for tid delete command to free up the resource on the command status
619 * indication?
620 */
621 dp_cmd = kzalloc(sizeof(*dp_cmd), GFP_ATOMIC);
622
623 if (!dp_cmd)
624 return -ENOMEM;
625
626 memcpy(&dp_cmd->data, rx_tid, sizeof(*rx_tid));
627 dp_cmd->cmd_num = cmd_num;
628 dp_cmd->handler = cb;
629
630 spin_lock_bh(&dp->reo_cmd_lock);
631 list_add_tail(&dp_cmd->list, &dp->reo_cmd_list);
632 spin_unlock_bh(&dp->reo_cmd_lock);
633
634 return 0;
635 }
636
ath12k_dp_reo_cache_flush(struct ath12k_base * ab,struct ath12k_dp_rx_tid * rx_tid)637 static void ath12k_dp_reo_cache_flush(struct ath12k_base *ab,
638 struct ath12k_dp_rx_tid *rx_tid)
639 {
640 struct ath12k_hal_reo_cmd cmd = {0};
641 unsigned long tot_desc_sz, desc_sz;
642 int ret;
643
644 tot_desc_sz = rx_tid->size;
645 desc_sz = ath12k_hal_reo_qdesc_size(0, HAL_DESC_REO_NON_QOS_TID);
646
647 while (tot_desc_sz > desc_sz) {
648 tot_desc_sz -= desc_sz;
649 cmd.addr_lo = lower_32_bits(rx_tid->paddr + tot_desc_sz);
650 cmd.addr_hi = upper_32_bits(rx_tid->paddr);
651 ret = ath12k_dp_reo_cmd_send(ab, rx_tid,
652 HAL_REO_CMD_FLUSH_CACHE, &cmd,
653 NULL);
654 if (ret)
655 ath12k_warn(ab,
656 "failed to send HAL_REO_CMD_FLUSH_CACHE, tid %d (%d)\n",
657 rx_tid->tid, ret);
658 }
659
660 memset(&cmd, 0, sizeof(cmd));
661 cmd.addr_lo = lower_32_bits(rx_tid->paddr);
662 cmd.addr_hi = upper_32_bits(rx_tid->paddr);
663 cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS;
664 ret = ath12k_dp_reo_cmd_send(ab, rx_tid,
665 HAL_REO_CMD_FLUSH_CACHE,
666 &cmd, ath12k_dp_reo_cmd_free);
667 if (ret) {
668 ath12k_err(ab, "failed to send HAL_REO_CMD_FLUSH_CACHE cmd, tid %d (%d)\n",
669 rx_tid->tid, ret);
670 dma_unmap_single(ab->dev, rx_tid->paddr, rx_tid->size,
671 DMA_BIDIRECTIONAL);
672 kfree(rx_tid->vaddr);
673 rx_tid->vaddr = NULL;
674 }
675 }
676
ath12k_dp_rx_tid_del_func(struct ath12k_dp * dp,void * ctx,enum hal_reo_cmd_status status)677 static void ath12k_dp_rx_tid_del_func(struct ath12k_dp *dp, void *ctx,
678 enum hal_reo_cmd_status status)
679 {
680 struct ath12k_base *ab = dp->ab;
681 struct ath12k_dp_rx_tid *rx_tid = ctx;
682 struct ath12k_dp_rx_reo_cache_flush_elem *elem, *tmp;
683
684 if (status == HAL_REO_CMD_DRAIN) {
685 goto free_desc;
686 } else if (status != HAL_REO_CMD_SUCCESS) {
687 /* Shouldn't happen! Cleanup in case of other failure? */
688 ath12k_warn(ab, "failed to delete rx tid %d hw descriptor %d\n",
689 rx_tid->tid, status);
690 return;
691 }
692
693 elem = kzalloc(sizeof(*elem), GFP_ATOMIC);
694 if (!elem)
695 goto free_desc;
696
697 elem->ts = jiffies;
698 memcpy(&elem->data, rx_tid, sizeof(*rx_tid));
699
700 spin_lock_bh(&dp->reo_cmd_lock);
701 list_add_tail(&elem->list, &dp->reo_cmd_cache_flush_list);
702 dp->reo_cmd_cache_flush_count++;
703
704 /* Flush and invalidate aged REO desc from HW cache */
705 list_for_each_entry_safe(elem, tmp, &dp->reo_cmd_cache_flush_list,
706 list) {
707 if (dp->reo_cmd_cache_flush_count > ATH12K_DP_RX_REO_DESC_FREE_THRES ||
708 time_after(jiffies, elem->ts +
709 msecs_to_jiffies(ATH12K_DP_RX_REO_DESC_FREE_TIMEOUT_MS))) {
710 list_del(&elem->list);
711 dp->reo_cmd_cache_flush_count--;
712
713 /* Unlock the reo_cmd_lock before using ath12k_dp_reo_cmd_send()
714 * within ath12k_dp_reo_cache_flush. The reo_cmd_cache_flush_list
715 * is used in only two contexts, one is in this function called
716 * from napi and the other in ath12k_dp_free during core destroy.
717 * Before dp_free, the irqs would be disabled and would wait to
718 * synchronize. Hence there wouldn’t be any race against add or
719 * delete to this list. Hence unlock-lock is safe here.
720 */
721 spin_unlock_bh(&dp->reo_cmd_lock);
722
723 ath12k_dp_reo_cache_flush(ab, &elem->data);
724 kfree(elem);
725 spin_lock_bh(&dp->reo_cmd_lock);
726 }
727 }
728 spin_unlock_bh(&dp->reo_cmd_lock);
729
730 return;
731 free_desc:
732 dma_unmap_single(ab->dev, rx_tid->paddr, rx_tid->size,
733 DMA_BIDIRECTIONAL);
734 kfree(rx_tid->vaddr);
735 rx_tid->vaddr = NULL;
736 }
737
ath12k_peer_rx_tid_qref_setup(struct ath12k_base * ab,u16 peer_id,u16 tid,dma_addr_t paddr)738 static void ath12k_peer_rx_tid_qref_setup(struct ath12k_base *ab, u16 peer_id, u16 tid,
739 dma_addr_t paddr)
740 {
741 struct ath12k_reo_queue_ref *qref;
742 struct ath12k_dp *dp = &ab->dp;
743 bool ml_peer = false;
744
745 if (!ab->hw_params->reoq_lut_support)
746 return;
747
748 if (peer_id & ATH12K_PEER_ML_ID_VALID) {
749 peer_id &= ~ATH12K_PEER_ML_ID_VALID;
750 ml_peer = true;
751 }
752
753 if (ml_peer)
754 qref = (struct ath12k_reo_queue_ref *)dp->ml_reoq_lut.vaddr +
755 (peer_id * (IEEE80211_NUM_TIDS + 1) + tid);
756 else
757 qref = (struct ath12k_reo_queue_ref *)dp->reoq_lut.vaddr +
758 (peer_id * (IEEE80211_NUM_TIDS + 1) + tid);
759
760 qref->info0 = u32_encode_bits(lower_32_bits(paddr),
761 BUFFER_ADDR_INFO0_ADDR);
762 qref->info1 = u32_encode_bits(upper_32_bits(paddr),
763 BUFFER_ADDR_INFO1_ADDR) |
764 u32_encode_bits(tid, DP_REO_QREF_NUM);
765 }
766
ath12k_peer_rx_tid_qref_reset(struct ath12k_base * ab,u16 peer_id,u16 tid)767 static void ath12k_peer_rx_tid_qref_reset(struct ath12k_base *ab, u16 peer_id, u16 tid)
768 {
769 struct ath12k_reo_queue_ref *qref;
770 struct ath12k_dp *dp = &ab->dp;
771 bool ml_peer = false;
772
773 if (!ab->hw_params->reoq_lut_support)
774 return;
775
776 if (peer_id & ATH12K_PEER_ML_ID_VALID) {
777 peer_id &= ~ATH12K_PEER_ML_ID_VALID;
778 ml_peer = true;
779 }
780
781 if (ml_peer)
782 qref = (struct ath12k_reo_queue_ref *)dp->ml_reoq_lut.vaddr +
783 (peer_id * (IEEE80211_NUM_TIDS + 1) + tid);
784 else
785 qref = (struct ath12k_reo_queue_ref *)dp->reoq_lut.vaddr +
786 (peer_id * (IEEE80211_NUM_TIDS + 1) + tid);
787
788 qref->info0 = u32_encode_bits(0, BUFFER_ADDR_INFO0_ADDR);
789 qref->info1 = u32_encode_bits(0, BUFFER_ADDR_INFO1_ADDR) |
790 u32_encode_bits(tid, DP_REO_QREF_NUM);
791 }
792
ath12k_dp_rx_peer_tid_delete(struct ath12k * ar,struct ath12k_peer * peer,u8 tid)793 void ath12k_dp_rx_peer_tid_delete(struct ath12k *ar,
794 struct ath12k_peer *peer, u8 tid)
795 {
796 struct ath12k_hal_reo_cmd cmd = {0};
797 struct ath12k_dp_rx_tid *rx_tid = &peer->rx_tid[tid];
798 int ret;
799
800 if (!rx_tid->active)
801 return;
802
803 cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS;
804 cmd.addr_lo = lower_32_bits(rx_tid->paddr);
805 cmd.addr_hi = upper_32_bits(rx_tid->paddr);
806 cmd.upd0 = HAL_REO_CMD_UPD0_VLD;
807 ret = ath12k_dp_reo_cmd_send(ar->ab, rx_tid,
808 HAL_REO_CMD_UPDATE_RX_QUEUE, &cmd,
809 ath12k_dp_rx_tid_del_func);
810 if (ret) {
811 ath12k_err(ar->ab, "failed to send HAL_REO_CMD_UPDATE_RX_QUEUE cmd, tid %d (%d)\n",
812 tid, ret);
813 dma_unmap_single(ar->ab->dev, rx_tid->paddr, rx_tid->size,
814 DMA_BIDIRECTIONAL);
815 kfree(rx_tid->vaddr);
816 rx_tid->vaddr = NULL;
817 }
818
819 if (peer->mlo)
820 ath12k_peer_rx_tid_qref_reset(ar->ab, peer->ml_id, tid);
821 else
822 ath12k_peer_rx_tid_qref_reset(ar->ab, peer->peer_id, tid);
823
824 rx_tid->active = false;
825 }
826
827 /* TODO: it's strange (and ugly) that struct hal_reo_dest_ring is converted
828 * to struct hal_wbm_release_ring, I couldn't figure out the logic behind
829 * that.
830 */
ath12k_dp_rx_link_desc_return(struct ath12k_base * ab,struct hal_reo_dest_ring * ring,enum hal_wbm_rel_bm_act action)831 static int ath12k_dp_rx_link_desc_return(struct ath12k_base *ab,
832 struct hal_reo_dest_ring *ring,
833 enum hal_wbm_rel_bm_act action)
834 {
835 struct hal_wbm_release_ring *link_desc = (struct hal_wbm_release_ring *)ring;
836 struct hal_wbm_release_ring *desc;
837 struct ath12k_dp *dp = &ab->dp;
838 struct hal_srng *srng;
839 int ret = 0;
840
841 srng = &ab->hal.srng_list[dp->wbm_desc_rel_ring.ring_id];
842
843 spin_lock_bh(&srng->lock);
844
845 ath12k_hal_srng_access_begin(ab, srng);
846
847 desc = ath12k_hal_srng_src_get_next_entry(ab, srng);
848 if (!desc) {
849 ret = -ENOBUFS;
850 goto exit;
851 }
852
853 ath12k_hal_rx_msdu_link_desc_set(ab, desc, link_desc, action);
854
855 exit:
856 ath12k_hal_srng_access_end(ab, srng);
857
858 spin_unlock_bh(&srng->lock);
859
860 return ret;
861 }
862
ath12k_dp_rx_frags_cleanup(struct ath12k_dp_rx_tid * rx_tid,bool rel_link_desc)863 static void ath12k_dp_rx_frags_cleanup(struct ath12k_dp_rx_tid *rx_tid,
864 bool rel_link_desc)
865 {
866 struct ath12k_base *ab = rx_tid->ab;
867
868 lockdep_assert_held(&ab->base_lock);
869
870 if (rx_tid->dst_ring_desc) {
871 if (rel_link_desc)
872 ath12k_dp_rx_link_desc_return(ab, rx_tid->dst_ring_desc,
873 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
874 kfree(rx_tid->dst_ring_desc);
875 rx_tid->dst_ring_desc = NULL;
876 }
877
878 rx_tid->cur_sn = 0;
879 rx_tid->last_frag_no = 0;
880 rx_tid->rx_frag_bitmap = 0;
881 __skb_queue_purge(&rx_tid->rx_frags);
882 }
883
ath12k_dp_rx_peer_tid_cleanup(struct ath12k * ar,struct ath12k_peer * peer)884 void ath12k_dp_rx_peer_tid_cleanup(struct ath12k *ar, struct ath12k_peer *peer)
885 {
886 struct ath12k_dp_rx_tid *rx_tid;
887 int i;
888
889 lockdep_assert_held(&ar->ab->base_lock);
890
891 for (i = 0; i <= IEEE80211_NUM_TIDS; i++) {
892 rx_tid = &peer->rx_tid[i];
893
894 ath12k_dp_rx_peer_tid_delete(ar, peer, i);
895 ath12k_dp_rx_frags_cleanup(rx_tid, true);
896
897 spin_unlock_bh(&ar->ab->base_lock);
898 del_timer_sync(&rx_tid->frag_timer);
899 spin_lock_bh(&ar->ab->base_lock);
900 }
901 }
902
ath12k_peer_rx_tid_reo_update(struct ath12k * ar,struct ath12k_peer * peer,struct ath12k_dp_rx_tid * rx_tid,u32 ba_win_sz,u16 ssn,bool update_ssn)903 static int ath12k_peer_rx_tid_reo_update(struct ath12k *ar,
904 struct ath12k_peer *peer,
905 struct ath12k_dp_rx_tid *rx_tid,
906 u32 ba_win_sz, u16 ssn,
907 bool update_ssn)
908 {
909 struct ath12k_hal_reo_cmd cmd = {0};
910 int ret;
911
912 cmd.addr_lo = lower_32_bits(rx_tid->paddr);
913 cmd.addr_hi = upper_32_bits(rx_tid->paddr);
914 cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS;
915 cmd.upd0 = HAL_REO_CMD_UPD0_BA_WINDOW_SIZE;
916 cmd.ba_window_size = ba_win_sz;
917
918 if (update_ssn) {
919 cmd.upd0 |= HAL_REO_CMD_UPD0_SSN;
920 cmd.upd2 = u32_encode_bits(ssn, HAL_REO_CMD_UPD2_SSN);
921 }
922
923 ret = ath12k_dp_reo_cmd_send(ar->ab, rx_tid,
924 HAL_REO_CMD_UPDATE_RX_QUEUE, &cmd,
925 NULL);
926 if (ret) {
927 ath12k_warn(ar->ab, "failed to update rx tid queue, tid %d (%d)\n",
928 rx_tid->tid, ret);
929 return ret;
930 }
931
932 rx_tid->ba_win_sz = ba_win_sz;
933
934 return 0;
935 }
936
ath12k_dp_rx_peer_tid_setup(struct ath12k * ar,const u8 * peer_mac,int vdev_id,u8 tid,u32 ba_win_sz,u16 ssn,enum hal_pn_type pn_type)937 int ath12k_dp_rx_peer_tid_setup(struct ath12k *ar, const u8 *peer_mac, int vdev_id,
938 u8 tid, u32 ba_win_sz, u16 ssn,
939 enum hal_pn_type pn_type)
940 {
941 struct ath12k_base *ab = ar->ab;
942 struct ath12k_dp *dp = &ab->dp;
943 struct hal_rx_reo_queue *addr_aligned;
944 struct ath12k_peer *peer;
945 struct ath12k_dp_rx_tid *rx_tid;
946 u32 hw_desc_sz;
947 void *vaddr;
948 dma_addr_t paddr;
949 int ret;
950
951 spin_lock_bh(&ab->base_lock);
952
953 peer = ath12k_peer_find(ab, vdev_id, peer_mac);
954 if (!peer) {
955 spin_unlock_bh(&ab->base_lock);
956 ath12k_warn(ab, "failed to find the peer to set up rx tid\n");
957 return -ENOENT;
958 }
959
960 if (!peer->primary_link) {
961 spin_unlock_bh(&ab->base_lock);
962 return 0;
963 }
964
965 if (ab->hw_params->reoq_lut_support &&
966 (!dp->reoq_lut.vaddr || !dp->ml_reoq_lut.vaddr)) {
967 spin_unlock_bh(&ab->base_lock);
968 ath12k_warn(ab, "reo qref table is not setup\n");
969 return -EINVAL;
970 }
971
972 if (peer->peer_id > DP_MAX_PEER_ID || tid > IEEE80211_NUM_TIDS) {
973 ath12k_warn(ab, "peer id of peer %d or tid %d doesn't allow reoq setup\n",
974 peer->peer_id, tid);
975 spin_unlock_bh(&ab->base_lock);
976 return -EINVAL;
977 }
978
979 rx_tid = &peer->rx_tid[tid];
980 /* Update the tid queue if it is already setup */
981 if (rx_tid->active) {
982 paddr = rx_tid->paddr;
983 ret = ath12k_peer_rx_tid_reo_update(ar, peer, rx_tid,
984 ba_win_sz, ssn, true);
985 spin_unlock_bh(&ab->base_lock);
986 if (ret) {
987 ath12k_warn(ab, "failed to update reo for rx tid %d\n", tid);
988 return ret;
989 }
990
991 if (!ab->hw_params->reoq_lut_support) {
992 ret = ath12k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id,
993 peer_mac,
994 paddr, tid, 1,
995 ba_win_sz);
996 if (ret) {
997 ath12k_warn(ab, "failed to setup peer rx reorder queuefor tid %d: %d\n",
998 tid, ret);
999 return ret;
1000 }
1001 }
1002
1003 return 0;
1004 }
1005
1006 rx_tid->tid = tid;
1007
1008 rx_tid->ba_win_sz = ba_win_sz;
1009
1010 /* TODO: Optimize the memory allocation for qos tid based on
1011 * the actual BA window size in REO tid update path.
1012 */
1013 if (tid == HAL_DESC_REO_NON_QOS_TID)
1014 hw_desc_sz = ath12k_hal_reo_qdesc_size(ba_win_sz, tid);
1015 else
1016 hw_desc_sz = ath12k_hal_reo_qdesc_size(DP_BA_WIN_SZ_MAX, tid);
1017
1018 vaddr = kzalloc(hw_desc_sz + HAL_LINK_DESC_ALIGN - 1, GFP_ATOMIC);
1019 if (!vaddr) {
1020 spin_unlock_bh(&ab->base_lock);
1021 return -ENOMEM;
1022 }
1023
1024 addr_aligned = PTR_ALIGN(vaddr, HAL_LINK_DESC_ALIGN);
1025
1026 ath12k_hal_reo_qdesc_setup(addr_aligned, tid, ba_win_sz,
1027 ssn, pn_type);
1028
1029 paddr = dma_map_single(ab->dev, addr_aligned, hw_desc_sz,
1030 DMA_BIDIRECTIONAL);
1031
1032 ret = dma_mapping_error(ab->dev, paddr);
1033 if (ret) {
1034 spin_unlock_bh(&ab->base_lock);
1035 goto err_mem_free;
1036 }
1037
1038 rx_tid->vaddr = vaddr;
1039 rx_tid->paddr = paddr;
1040 rx_tid->size = hw_desc_sz;
1041 rx_tid->active = true;
1042
1043 if (ab->hw_params->reoq_lut_support) {
1044 /* Update the REO queue LUT at the corresponding peer id
1045 * and tid with qaddr.
1046 */
1047 if (peer->mlo)
1048 ath12k_peer_rx_tid_qref_setup(ab, peer->ml_id, tid, paddr);
1049 else
1050 ath12k_peer_rx_tid_qref_setup(ab, peer->peer_id, tid, paddr);
1051
1052 spin_unlock_bh(&ab->base_lock);
1053 } else {
1054 spin_unlock_bh(&ab->base_lock);
1055 ret = ath12k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id, peer_mac,
1056 paddr, tid, 1, ba_win_sz);
1057 }
1058
1059 return ret;
1060
1061 err_mem_free:
1062 kfree(vaddr);
1063
1064 return ret;
1065 }
1066
ath12k_dp_rx_ampdu_start(struct ath12k * ar,struct ieee80211_ampdu_params * params,u8 link_id)1067 int ath12k_dp_rx_ampdu_start(struct ath12k *ar,
1068 struct ieee80211_ampdu_params *params,
1069 u8 link_id)
1070 {
1071 struct ath12k_base *ab = ar->ab;
1072 struct ath12k_sta *ahsta = ath12k_sta_to_ahsta(params->sta);
1073 struct ath12k_link_sta *arsta;
1074 int vdev_id;
1075 int ret;
1076
1077 lockdep_assert_wiphy(ath12k_ar_to_hw(ar)->wiphy);
1078
1079 arsta = wiphy_dereference(ath12k_ar_to_hw(ar)->wiphy,
1080 ahsta->link[link_id]);
1081 if (!arsta)
1082 return -ENOLINK;
1083
1084 vdev_id = arsta->arvif->vdev_id;
1085
1086 ret = ath12k_dp_rx_peer_tid_setup(ar, arsta->addr, vdev_id,
1087 params->tid, params->buf_size,
1088 params->ssn, arsta->ahsta->pn_type);
1089 if (ret)
1090 ath12k_warn(ab, "failed to setup rx tid %d\n", ret);
1091
1092 return ret;
1093 }
1094
ath12k_dp_rx_ampdu_stop(struct ath12k * ar,struct ieee80211_ampdu_params * params,u8 link_id)1095 int ath12k_dp_rx_ampdu_stop(struct ath12k *ar,
1096 struct ieee80211_ampdu_params *params,
1097 u8 link_id)
1098 {
1099 struct ath12k_base *ab = ar->ab;
1100 struct ath12k_peer *peer;
1101 struct ath12k_sta *ahsta = ath12k_sta_to_ahsta(params->sta);
1102 struct ath12k_link_sta *arsta;
1103 int vdev_id;
1104 bool active;
1105 int ret;
1106
1107 lockdep_assert_wiphy(ath12k_ar_to_hw(ar)->wiphy);
1108
1109 arsta = wiphy_dereference(ath12k_ar_to_hw(ar)->wiphy,
1110 ahsta->link[link_id]);
1111 if (!arsta)
1112 return -ENOLINK;
1113
1114 vdev_id = arsta->arvif->vdev_id;
1115
1116 spin_lock_bh(&ab->base_lock);
1117
1118 peer = ath12k_peer_find(ab, vdev_id, arsta->addr);
1119 if (!peer) {
1120 spin_unlock_bh(&ab->base_lock);
1121 ath12k_warn(ab, "failed to find the peer to stop rx aggregation\n");
1122 return -ENOENT;
1123 }
1124
1125 active = peer->rx_tid[params->tid].active;
1126
1127 if (!active) {
1128 spin_unlock_bh(&ab->base_lock);
1129 return 0;
1130 }
1131
1132 ret = ath12k_peer_rx_tid_reo_update(ar, peer, peer->rx_tid, 1, 0, false);
1133 spin_unlock_bh(&ab->base_lock);
1134 if (ret) {
1135 ath12k_warn(ab, "failed to update reo for rx tid %d: %d\n",
1136 params->tid, ret);
1137 return ret;
1138 }
1139
1140 return ret;
1141 }
1142
ath12k_dp_rx_peer_pn_replay_config(struct ath12k_link_vif * arvif,const u8 * peer_addr,enum set_key_cmd key_cmd,struct ieee80211_key_conf * key)1143 int ath12k_dp_rx_peer_pn_replay_config(struct ath12k_link_vif *arvif,
1144 const u8 *peer_addr,
1145 enum set_key_cmd key_cmd,
1146 struct ieee80211_key_conf *key)
1147 {
1148 struct ath12k *ar = arvif->ar;
1149 struct ath12k_base *ab = ar->ab;
1150 struct ath12k_hal_reo_cmd cmd = {0};
1151 struct ath12k_peer *peer;
1152 struct ath12k_dp_rx_tid *rx_tid;
1153 u8 tid;
1154 int ret = 0;
1155
1156 /* NOTE: Enable PN/TSC replay check offload only for unicast frames.
1157 * We use mac80211 PN/TSC replay check functionality for bcast/mcast
1158 * for now.
1159 */
1160 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE))
1161 return 0;
1162
1163 cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS;
1164 cmd.upd0 = HAL_REO_CMD_UPD0_PN |
1165 HAL_REO_CMD_UPD0_PN_SIZE |
1166 HAL_REO_CMD_UPD0_PN_VALID |
1167 HAL_REO_CMD_UPD0_PN_CHECK |
1168 HAL_REO_CMD_UPD0_SVLD;
1169
1170 switch (key->cipher) {
1171 case WLAN_CIPHER_SUITE_TKIP:
1172 case WLAN_CIPHER_SUITE_CCMP:
1173 case WLAN_CIPHER_SUITE_CCMP_256:
1174 case WLAN_CIPHER_SUITE_GCMP:
1175 case WLAN_CIPHER_SUITE_GCMP_256:
1176 if (key_cmd == SET_KEY) {
1177 cmd.upd1 |= HAL_REO_CMD_UPD1_PN_CHECK;
1178 cmd.pn_size = 48;
1179 }
1180 break;
1181 default:
1182 break;
1183 }
1184
1185 spin_lock_bh(&ab->base_lock);
1186
1187 peer = ath12k_peer_find(ab, arvif->vdev_id, peer_addr);
1188 if (!peer) {
1189 spin_unlock_bh(&ab->base_lock);
1190 ath12k_warn(ab, "failed to find the peer %pM to configure pn replay detection\n",
1191 peer_addr);
1192 return -ENOENT;
1193 }
1194
1195 for (tid = 0; tid <= IEEE80211_NUM_TIDS; tid++) {
1196 rx_tid = &peer->rx_tid[tid];
1197 if (!rx_tid->active)
1198 continue;
1199 cmd.addr_lo = lower_32_bits(rx_tid->paddr);
1200 cmd.addr_hi = upper_32_bits(rx_tid->paddr);
1201 ret = ath12k_dp_reo_cmd_send(ab, rx_tid,
1202 HAL_REO_CMD_UPDATE_RX_QUEUE,
1203 &cmd, NULL);
1204 if (ret) {
1205 ath12k_warn(ab, "failed to configure rx tid %d queue of peer %pM for pn replay detection %d\n",
1206 tid, peer_addr, ret);
1207 break;
1208 }
1209 }
1210
1211 spin_unlock_bh(&ab->base_lock);
1212
1213 return ret;
1214 }
1215
ath12k_get_ppdu_user_index(struct htt_ppdu_stats * ppdu_stats,u16 peer_id)1216 static int ath12k_get_ppdu_user_index(struct htt_ppdu_stats *ppdu_stats,
1217 u16 peer_id)
1218 {
1219 int i;
1220
1221 for (i = 0; i < HTT_PPDU_STATS_MAX_USERS - 1; i++) {
1222 if (ppdu_stats->user_stats[i].is_valid_peer_id) {
1223 if (peer_id == ppdu_stats->user_stats[i].peer_id)
1224 return i;
1225 } else {
1226 return i;
1227 }
1228 }
1229
1230 return -EINVAL;
1231 }
1232
ath12k_htt_tlv_ppdu_stats_parse(struct ath12k_base * ab,u16 tag,u16 len,const void * ptr,void * data)1233 static int ath12k_htt_tlv_ppdu_stats_parse(struct ath12k_base *ab,
1234 u16 tag, u16 len, const void *ptr,
1235 void *data)
1236 {
1237 const struct htt_ppdu_stats_usr_cmpltn_ack_ba_status *ba_status;
1238 const struct htt_ppdu_stats_usr_cmpltn_cmn *cmplt_cmn;
1239 const struct htt_ppdu_stats_user_rate *user_rate;
1240 struct htt_ppdu_stats_info *ppdu_info;
1241 struct htt_ppdu_user_stats *user_stats;
1242 int cur_user;
1243 u16 peer_id;
1244
1245 ppdu_info = data;
1246
1247 switch (tag) {
1248 case HTT_PPDU_STATS_TAG_COMMON:
1249 if (len < sizeof(struct htt_ppdu_stats_common)) {
1250 ath12k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1251 len, tag);
1252 return -EINVAL;
1253 }
1254 memcpy(&ppdu_info->ppdu_stats.common, ptr,
1255 sizeof(struct htt_ppdu_stats_common));
1256 break;
1257 case HTT_PPDU_STATS_TAG_USR_RATE:
1258 if (len < sizeof(struct htt_ppdu_stats_user_rate)) {
1259 ath12k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1260 len, tag);
1261 return -EINVAL;
1262 }
1263 user_rate = ptr;
1264 peer_id = le16_to_cpu(user_rate->sw_peer_id);
1265 cur_user = ath12k_get_ppdu_user_index(&ppdu_info->ppdu_stats,
1266 peer_id);
1267 if (cur_user < 0)
1268 return -EINVAL;
1269 user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user];
1270 user_stats->peer_id = peer_id;
1271 user_stats->is_valid_peer_id = true;
1272 memcpy(&user_stats->rate, ptr,
1273 sizeof(struct htt_ppdu_stats_user_rate));
1274 user_stats->tlv_flags |= BIT(tag);
1275 break;
1276 case HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON:
1277 if (len < sizeof(struct htt_ppdu_stats_usr_cmpltn_cmn)) {
1278 ath12k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1279 len, tag);
1280 return -EINVAL;
1281 }
1282
1283 cmplt_cmn = ptr;
1284 peer_id = le16_to_cpu(cmplt_cmn->sw_peer_id);
1285 cur_user = ath12k_get_ppdu_user_index(&ppdu_info->ppdu_stats,
1286 peer_id);
1287 if (cur_user < 0)
1288 return -EINVAL;
1289 user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user];
1290 user_stats->peer_id = peer_id;
1291 user_stats->is_valid_peer_id = true;
1292 memcpy(&user_stats->cmpltn_cmn, ptr,
1293 sizeof(struct htt_ppdu_stats_usr_cmpltn_cmn));
1294 user_stats->tlv_flags |= BIT(tag);
1295 break;
1296 case HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS:
1297 if (len <
1298 sizeof(struct htt_ppdu_stats_usr_cmpltn_ack_ba_status)) {
1299 ath12k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1300 len, tag);
1301 return -EINVAL;
1302 }
1303
1304 ba_status = ptr;
1305 peer_id = le16_to_cpu(ba_status->sw_peer_id);
1306 cur_user = ath12k_get_ppdu_user_index(&ppdu_info->ppdu_stats,
1307 peer_id);
1308 if (cur_user < 0)
1309 return -EINVAL;
1310 user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user];
1311 user_stats->peer_id = peer_id;
1312 user_stats->is_valid_peer_id = true;
1313 memcpy(&user_stats->ack_ba, ptr,
1314 sizeof(struct htt_ppdu_stats_usr_cmpltn_ack_ba_status));
1315 user_stats->tlv_flags |= BIT(tag);
1316 break;
1317 }
1318 return 0;
1319 }
1320
ath12k_dp_htt_tlv_iter(struct ath12k_base * ab,const void * ptr,size_t len,int (* iter)(struct ath12k_base * ar,u16 tag,u16 len,const void * ptr,void * data),void * data)1321 int ath12k_dp_htt_tlv_iter(struct ath12k_base *ab, const void *ptr, size_t len,
1322 int (*iter)(struct ath12k_base *ar, u16 tag, u16 len,
1323 const void *ptr, void *data),
1324 void *data)
1325 {
1326 const struct htt_tlv *tlv;
1327 const void *begin = ptr;
1328 u16 tlv_tag, tlv_len;
1329 int ret = -EINVAL;
1330
1331 while (len > 0) {
1332 if (len < sizeof(*tlv)) {
1333 ath12k_err(ab, "htt tlv parse failure at byte %zd (%zu bytes left, %zu expected)\n",
1334 ptr - begin, len, sizeof(*tlv));
1335 return -EINVAL;
1336 }
1337 tlv = (struct htt_tlv *)ptr;
1338 tlv_tag = le32_get_bits(tlv->header, HTT_TLV_TAG);
1339 tlv_len = le32_get_bits(tlv->header, HTT_TLV_LEN);
1340 ptr += sizeof(*tlv);
1341 len -= sizeof(*tlv);
1342
1343 if (tlv_len > len) {
1344 ath12k_err(ab, "htt tlv parse failure of tag %u at byte %zd (%zu bytes left, %u expected)\n",
1345 tlv_tag, ptr - begin, len, tlv_len);
1346 return -EINVAL;
1347 }
1348 ret = iter(ab, tlv_tag, tlv_len, ptr, data);
1349 if (ret == -ENOMEM)
1350 return ret;
1351
1352 ptr += tlv_len;
1353 len -= tlv_len;
1354 }
1355 return 0;
1356 }
1357
1358 static void
ath12k_update_per_peer_tx_stats(struct ath12k * ar,struct htt_ppdu_stats * ppdu_stats,u8 user)1359 ath12k_update_per_peer_tx_stats(struct ath12k *ar,
1360 struct htt_ppdu_stats *ppdu_stats, u8 user)
1361 {
1362 struct ath12k_base *ab = ar->ab;
1363 struct ath12k_peer *peer;
1364 struct ieee80211_sta *sta;
1365 struct ath12k_sta *ahsta;
1366 struct ath12k_link_sta *arsta;
1367 struct htt_ppdu_stats_user_rate *user_rate;
1368 struct ath12k_per_peer_tx_stats *peer_stats = &ar->peer_tx_stats;
1369 struct htt_ppdu_user_stats *usr_stats = &ppdu_stats->user_stats[user];
1370 struct htt_ppdu_stats_common *common = &ppdu_stats->common;
1371 int ret;
1372 u8 flags, mcs, nss, bw, sgi, dcm, rate_idx = 0;
1373 u32 v, succ_bytes = 0;
1374 u16 tones, rate = 0, succ_pkts = 0;
1375 u32 tx_duration = 0;
1376 u8 tid = HTT_PPDU_STATS_NON_QOS_TID;
1377 bool is_ampdu = false;
1378
1379 if (!(usr_stats->tlv_flags & BIT(HTT_PPDU_STATS_TAG_USR_RATE)))
1380 return;
1381
1382 if (usr_stats->tlv_flags & BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON))
1383 is_ampdu =
1384 HTT_USR_CMPLTN_IS_AMPDU(usr_stats->cmpltn_cmn.flags);
1385
1386 if (usr_stats->tlv_flags &
1387 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS)) {
1388 succ_bytes = le32_to_cpu(usr_stats->ack_ba.success_bytes);
1389 succ_pkts = le32_get_bits(usr_stats->ack_ba.info,
1390 HTT_PPDU_STATS_ACK_BA_INFO_NUM_MSDU_M);
1391 tid = le32_get_bits(usr_stats->ack_ba.info,
1392 HTT_PPDU_STATS_ACK_BA_INFO_TID_NUM);
1393 }
1394
1395 if (common->fes_duration_us)
1396 tx_duration = le32_to_cpu(common->fes_duration_us);
1397
1398 user_rate = &usr_stats->rate;
1399 flags = HTT_USR_RATE_PREAMBLE(user_rate->rate_flags);
1400 bw = HTT_USR_RATE_BW(user_rate->rate_flags) - 2;
1401 nss = HTT_USR_RATE_NSS(user_rate->rate_flags) + 1;
1402 mcs = HTT_USR_RATE_MCS(user_rate->rate_flags);
1403 sgi = HTT_USR_RATE_GI(user_rate->rate_flags);
1404 dcm = HTT_USR_RATE_DCM(user_rate->rate_flags);
1405
1406 /* Note: If host configured fixed rates and in some other special
1407 * cases, the broadcast/management frames are sent in different rates.
1408 * Firmware rate's control to be skipped for this?
1409 */
1410
1411 if (flags == WMI_RATE_PREAMBLE_HE && mcs > ATH12K_HE_MCS_MAX) {
1412 ath12k_warn(ab, "Invalid HE mcs %d peer stats", mcs);
1413 return;
1414 }
1415
1416 if (flags == WMI_RATE_PREAMBLE_VHT && mcs > ATH12K_VHT_MCS_MAX) {
1417 ath12k_warn(ab, "Invalid VHT mcs %d peer stats", mcs);
1418 return;
1419 }
1420
1421 if (flags == WMI_RATE_PREAMBLE_HT && (mcs > ATH12K_HT_MCS_MAX || nss < 1)) {
1422 ath12k_warn(ab, "Invalid HT mcs %d nss %d peer stats",
1423 mcs, nss);
1424 return;
1425 }
1426
1427 if (flags == WMI_RATE_PREAMBLE_CCK || flags == WMI_RATE_PREAMBLE_OFDM) {
1428 ret = ath12k_mac_hw_ratecode_to_legacy_rate(mcs,
1429 flags,
1430 &rate_idx,
1431 &rate);
1432 if (ret < 0)
1433 return;
1434 }
1435
1436 rcu_read_lock();
1437 spin_lock_bh(&ab->base_lock);
1438 peer = ath12k_peer_find_by_id(ab, usr_stats->peer_id);
1439
1440 if (!peer || !peer->sta) {
1441 spin_unlock_bh(&ab->base_lock);
1442 rcu_read_unlock();
1443 return;
1444 }
1445
1446 sta = peer->sta;
1447 ahsta = ath12k_sta_to_ahsta(sta);
1448 arsta = &ahsta->deflink;
1449
1450 memset(&arsta->txrate, 0, sizeof(arsta->txrate));
1451
1452 switch (flags) {
1453 case WMI_RATE_PREAMBLE_OFDM:
1454 arsta->txrate.legacy = rate;
1455 break;
1456 case WMI_RATE_PREAMBLE_CCK:
1457 arsta->txrate.legacy = rate;
1458 break;
1459 case WMI_RATE_PREAMBLE_HT:
1460 arsta->txrate.mcs = mcs + 8 * (nss - 1);
1461 arsta->txrate.flags = RATE_INFO_FLAGS_MCS;
1462 if (sgi)
1463 arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
1464 break;
1465 case WMI_RATE_PREAMBLE_VHT:
1466 arsta->txrate.mcs = mcs;
1467 arsta->txrate.flags = RATE_INFO_FLAGS_VHT_MCS;
1468 if (sgi)
1469 arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
1470 break;
1471 case WMI_RATE_PREAMBLE_HE:
1472 arsta->txrate.mcs = mcs;
1473 arsta->txrate.flags = RATE_INFO_FLAGS_HE_MCS;
1474 arsta->txrate.he_dcm = dcm;
1475 arsta->txrate.he_gi = ath12k_he_gi_to_nl80211_he_gi(sgi);
1476 tones = le16_to_cpu(user_rate->ru_end) -
1477 le16_to_cpu(user_rate->ru_start) + 1;
1478 v = ath12k_he_ru_tones_to_nl80211_he_ru_alloc(tones);
1479 arsta->txrate.he_ru_alloc = v;
1480 break;
1481 }
1482
1483 arsta->txrate.nss = nss;
1484 arsta->txrate.bw = ath12k_mac_bw_to_mac80211_bw(bw);
1485 arsta->tx_duration += tx_duration;
1486 memcpy(&arsta->last_txrate, &arsta->txrate, sizeof(struct rate_info));
1487
1488 /* PPDU stats reported for mgmt packet doesn't have valid tx bytes.
1489 * So skip peer stats update for mgmt packets.
1490 */
1491 if (tid < HTT_PPDU_STATS_NON_QOS_TID) {
1492 memset(peer_stats, 0, sizeof(*peer_stats));
1493 peer_stats->succ_pkts = succ_pkts;
1494 peer_stats->succ_bytes = succ_bytes;
1495 peer_stats->is_ampdu = is_ampdu;
1496 peer_stats->duration = tx_duration;
1497 peer_stats->ba_fails =
1498 HTT_USR_CMPLTN_LONG_RETRY(usr_stats->cmpltn_cmn.flags) +
1499 HTT_USR_CMPLTN_SHORT_RETRY(usr_stats->cmpltn_cmn.flags);
1500 }
1501
1502 spin_unlock_bh(&ab->base_lock);
1503 rcu_read_unlock();
1504 }
1505
ath12k_htt_update_ppdu_stats(struct ath12k * ar,struct htt_ppdu_stats * ppdu_stats)1506 static void ath12k_htt_update_ppdu_stats(struct ath12k *ar,
1507 struct htt_ppdu_stats *ppdu_stats)
1508 {
1509 u8 user;
1510
1511 for (user = 0; user < HTT_PPDU_STATS_MAX_USERS - 1; user++)
1512 ath12k_update_per_peer_tx_stats(ar, ppdu_stats, user);
1513 }
1514
1515 static
ath12k_dp_htt_get_ppdu_desc(struct ath12k * ar,u32 ppdu_id)1516 struct htt_ppdu_stats_info *ath12k_dp_htt_get_ppdu_desc(struct ath12k *ar,
1517 u32 ppdu_id)
1518 {
1519 struct htt_ppdu_stats_info *ppdu_info;
1520
1521 lockdep_assert_held(&ar->data_lock);
1522 if (!list_empty(&ar->ppdu_stats_info)) {
1523 list_for_each_entry(ppdu_info, &ar->ppdu_stats_info, list) {
1524 if (ppdu_info->ppdu_id == ppdu_id)
1525 return ppdu_info;
1526 }
1527
1528 if (ar->ppdu_stat_list_depth > HTT_PPDU_DESC_MAX_DEPTH) {
1529 ppdu_info = list_first_entry(&ar->ppdu_stats_info,
1530 typeof(*ppdu_info), list);
1531 list_del(&ppdu_info->list);
1532 ar->ppdu_stat_list_depth--;
1533 ath12k_htt_update_ppdu_stats(ar, &ppdu_info->ppdu_stats);
1534 kfree(ppdu_info);
1535 }
1536 }
1537
1538 ppdu_info = kzalloc(sizeof(*ppdu_info), GFP_ATOMIC);
1539 if (!ppdu_info)
1540 return NULL;
1541
1542 list_add_tail(&ppdu_info->list, &ar->ppdu_stats_info);
1543 ar->ppdu_stat_list_depth++;
1544
1545 return ppdu_info;
1546 }
1547
ath12k_copy_to_delay_stats(struct ath12k_peer * peer,struct htt_ppdu_user_stats * usr_stats)1548 static void ath12k_copy_to_delay_stats(struct ath12k_peer *peer,
1549 struct htt_ppdu_user_stats *usr_stats)
1550 {
1551 peer->ppdu_stats_delayba.sw_peer_id = le16_to_cpu(usr_stats->rate.sw_peer_id);
1552 peer->ppdu_stats_delayba.info0 = le32_to_cpu(usr_stats->rate.info0);
1553 peer->ppdu_stats_delayba.ru_end = le16_to_cpu(usr_stats->rate.ru_end);
1554 peer->ppdu_stats_delayba.ru_start = le16_to_cpu(usr_stats->rate.ru_start);
1555 peer->ppdu_stats_delayba.info1 = le32_to_cpu(usr_stats->rate.info1);
1556 peer->ppdu_stats_delayba.rate_flags = le32_to_cpu(usr_stats->rate.rate_flags);
1557 peer->ppdu_stats_delayba.resp_rate_flags =
1558 le32_to_cpu(usr_stats->rate.resp_rate_flags);
1559
1560 peer->delayba_flag = true;
1561 }
1562
ath12k_copy_to_bar(struct ath12k_peer * peer,struct htt_ppdu_user_stats * usr_stats)1563 static void ath12k_copy_to_bar(struct ath12k_peer *peer,
1564 struct htt_ppdu_user_stats *usr_stats)
1565 {
1566 usr_stats->rate.sw_peer_id = cpu_to_le16(peer->ppdu_stats_delayba.sw_peer_id);
1567 usr_stats->rate.info0 = cpu_to_le32(peer->ppdu_stats_delayba.info0);
1568 usr_stats->rate.ru_end = cpu_to_le16(peer->ppdu_stats_delayba.ru_end);
1569 usr_stats->rate.ru_start = cpu_to_le16(peer->ppdu_stats_delayba.ru_start);
1570 usr_stats->rate.info1 = cpu_to_le32(peer->ppdu_stats_delayba.info1);
1571 usr_stats->rate.rate_flags = cpu_to_le32(peer->ppdu_stats_delayba.rate_flags);
1572 usr_stats->rate.resp_rate_flags =
1573 cpu_to_le32(peer->ppdu_stats_delayba.resp_rate_flags);
1574
1575 peer->delayba_flag = false;
1576 }
1577
ath12k_htt_pull_ppdu_stats(struct ath12k_base * ab,struct sk_buff * skb)1578 static int ath12k_htt_pull_ppdu_stats(struct ath12k_base *ab,
1579 struct sk_buff *skb)
1580 {
1581 struct ath12k_htt_ppdu_stats_msg *msg;
1582 struct htt_ppdu_stats_info *ppdu_info;
1583 struct ath12k_peer *peer = NULL;
1584 struct htt_ppdu_user_stats *usr_stats = NULL;
1585 u32 peer_id = 0;
1586 struct ath12k *ar;
1587 int ret, i;
1588 u8 pdev_id;
1589 u32 ppdu_id, len;
1590
1591 msg = (struct ath12k_htt_ppdu_stats_msg *)skb->data;
1592 len = le32_get_bits(msg->info, HTT_T2H_PPDU_STATS_INFO_PAYLOAD_SIZE);
1593 if (len > (skb->len - struct_size(msg, data, 0))) {
1594 ath12k_warn(ab,
1595 "HTT PPDU STATS event has unexpected payload size %u, should be smaller than %u\n",
1596 len, skb->len);
1597 return -EINVAL;
1598 }
1599
1600 pdev_id = le32_get_bits(msg->info, HTT_T2H_PPDU_STATS_INFO_PDEV_ID);
1601 ppdu_id = le32_to_cpu(msg->ppdu_id);
1602
1603 rcu_read_lock();
1604 ar = ath12k_mac_get_ar_by_pdev_id(ab, pdev_id);
1605 if (!ar) {
1606 ret = -EINVAL;
1607 goto exit;
1608 }
1609
1610 spin_lock_bh(&ar->data_lock);
1611 ppdu_info = ath12k_dp_htt_get_ppdu_desc(ar, ppdu_id);
1612 if (!ppdu_info) {
1613 spin_unlock_bh(&ar->data_lock);
1614 ret = -EINVAL;
1615 goto exit;
1616 }
1617
1618 ppdu_info->ppdu_id = ppdu_id;
1619 ret = ath12k_dp_htt_tlv_iter(ab, msg->data, len,
1620 ath12k_htt_tlv_ppdu_stats_parse,
1621 (void *)ppdu_info);
1622 if (ret) {
1623 spin_unlock_bh(&ar->data_lock);
1624 ath12k_warn(ab, "Failed to parse tlv %d\n", ret);
1625 goto exit;
1626 }
1627
1628 if (ppdu_info->ppdu_stats.common.num_users >= HTT_PPDU_STATS_MAX_USERS) {
1629 spin_unlock_bh(&ar->data_lock);
1630 ath12k_warn(ab,
1631 "HTT PPDU STATS event has unexpected num_users %u, should be smaller than %u\n",
1632 ppdu_info->ppdu_stats.common.num_users,
1633 HTT_PPDU_STATS_MAX_USERS);
1634 ret = -EINVAL;
1635 goto exit;
1636 }
1637
1638 /* back up data rate tlv for all peers */
1639 if (ppdu_info->frame_type == HTT_STATS_PPDU_FTYPE_DATA &&
1640 (ppdu_info->tlv_bitmap & (1 << HTT_PPDU_STATS_TAG_USR_COMMON)) &&
1641 ppdu_info->delay_ba) {
1642 for (i = 0; i < ppdu_info->ppdu_stats.common.num_users; i++) {
1643 peer_id = ppdu_info->ppdu_stats.user_stats[i].peer_id;
1644 spin_lock_bh(&ab->base_lock);
1645 peer = ath12k_peer_find_by_id(ab, peer_id);
1646 if (!peer) {
1647 spin_unlock_bh(&ab->base_lock);
1648 continue;
1649 }
1650
1651 usr_stats = &ppdu_info->ppdu_stats.user_stats[i];
1652 if (usr_stats->delay_ba)
1653 ath12k_copy_to_delay_stats(peer, usr_stats);
1654 spin_unlock_bh(&ab->base_lock);
1655 }
1656 }
1657
1658 /* restore all peers' data rate tlv to mu-bar tlv */
1659 if (ppdu_info->frame_type == HTT_STATS_PPDU_FTYPE_BAR &&
1660 (ppdu_info->tlv_bitmap & (1 << HTT_PPDU_STATS_TAG_USR_COMMON))) {
1661 for (i = 0; i < ppdu_info->bar_num_users; i++) {
1662 peer_id = ppdu_info->ppdu_stats.user_stats[i].peer_id;
1663 spin_lock_bh(&ab->base_lock);
1664 peer = ath12k_peer_find_by_id(ab, peer_id);
1665 if (!peer) {
1666 spin_unlock_bh(&ab->base_lock);
1667 continue;
1668 }
1669
1670 usr_stats = &ppdu_info->ppdu_stats.user_stats[i];
1671 if (peer->delayba_flag)
1672 ath12k_copy_to_bar(peer, usr_stats);
1673 spin_unlock_bh(&ab->base_lock);
1674 }
1675 }
1676
1677 spin_unlock_bh(&ar->data_lock);
1678
1679 exit:
1680 rcu_read_unlock();
1681
1682 return ret;
1683 }
1684
ath12k_htt_mlo_offset_event_handler(struct ath12k_base * ab,struct sk_buff * skb)1685 static void ath12k_htt_mlo_offset_event_handler(struct ath12k_base *ab,
1686 struct sk_buff *skb)
1687 {
1688 struct ath12k_htt_mlo_offset_msg *msg;
1689 struct ath12k_pdev *pdev;
1690 struct ath12k *ar;
1691 u8 pdev_id;
1692
1693 msg = (struct ath12k_htt_mlo_offset_msg *)skb->data;
1694 pdev_id = u32_get_bits(__le32_to_cpu(msg->info),
1695 HTT_T2H_MLO_OFFSET_INFO_PDEV_ID);
1696
1697 rcu_read_lock();
1698 ar = ath12k_mac_get_ar_by_pdev_id(ab, pdev_id);
1699 if (!ar) {
1700 /* It is possible that the ar is not yet active (started).
1701 * The above function will only look for the active pdev
1702 * and hence %NULL return is possible. Just silently
1703 * discard this message
1704 */
1705 goto exit;
1706 }
1707
1708 spin_lock_bh(&ar->data_lock);
1709 pdev = ar->pdev;
1710
1711 pdev->timestamp.info = __le32_to_cpu(msg->info);
1712 pdev->timestamp.sync_timestamp_lo_us = __le32_to_cpu(msg->sync_timestamp_lo_us);
1713 pdev->timestamp.sync_timestamp_hi_us = __le32_to_cpu(msg->sync_timestamp_hi_us);
1714 pdev->timestamp.mlo_offset_lo = __le32_to_cpu(msg->mlo_offset_lo);
1715 pdev->timestamp.mlo_offset_hi = __le32_to_cpu(msg->mlo_offset_hi);
1716 pdev->timestamp.mlo_offset_clks = __le32_to_cpu(msg->mlo_offset_clks);
1717 pdev->timestamp.mlo_comp_clks = __le32_to_cpu(msg->mlo_comp_clks);
1718 pdev->timestamp.mlo_comp_timer = __le32_to_cpu(msg->mlo_comp_timer);
1719
1720 spin_unlock_bh(&ar->data_lock);
1721 exit:
1722 rcu_read_unlock();
1723 }
1724
ath12k_dp_htt_htc_t2h_msg_handler(struct ath12k_base * ab,struct sk_buff * skb)1725 void ath12k_dp_htt_htc_t2h_msg_handler(struct ath12k_base *ab,
1726 struct sk_buff *skb)
1727 {
1728 struct ath12k_dp *dp = &ab->dp;
1729 struct htt_resp_msg *resp = (struct htt_resp_msg *)skb->data;
1730 enum htt_t2h_msg_type type;
1731 u16 peer_id;
1732 u8 vdev_id;
1733 u8 mac_addr[ETH_ALEN];
1734 u16 peer_mac_h16;
1735 u16 ast_hash = 0;
1736 u16 hw_peer_id;
1737
1738 type = le32_get_bits(resp->version_msg.version, HTT_T2H_MSG_TYPE);
1739
1740 ath12k_dbg(ab, ATH12K_DBG_DP_HTT, "dp_htt rx msg type :0x%0x\n", type);
1741
1742 switch (type) {
1743 case HTT_T2H_MSG_TYPE_VERSION_CONF:
1744 dp->htt_tgt_ver_major = le32_get_bits(resp->version_msg.version,
1745 HTT_T2H_VERSION_CONF_MAJOR);
1746 dp->htt_tgt_ver_minor = le32_get_bits(resp->version_msg.version,
1747 HTT_T2H_VERSION_CONF_MINOR);
1748 complete(&dp->htt_tgt_version_received);
1749 break;
1750 /* TODO: remove unused peer map versions after testing */
1751 case HTT_T2H_MSG_TYPE_PEER_MAP:
1752 vdev_id = le32_get_bits(resp->peer_map_ev.info,
1753 HTT_T2H_PEER_MAP_INFO_VDEV_ID);
1754 peer_id = le32_get_bits(resp->peer_map_ev.info,
1755 HTT_T2H_PEER_MAP_INFO_PEER_ID);
1756 peer_mac_h16 = le32_get_bits(resp->peer_map_ev.info1,
1757 HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16);
1758 ath12k_dp_get_mac_addr(le32_to_cpu(resp->peer_map_ev.mac_addr_l32),
1759 peer_mac_h16, mac_addr);
1760 ath12k_peer_map_event(ab, vdev_id, peer_id, mac_addr, 0, 0);
1761 break;
1762 case HTT_T2H_MSG_TYPE_PEER_MAP2:
1763 vdev_id = le32_get_bits(resp->peer_map_ev.info,
1764 HTT_T2H_PEER_MAP_INFO_VDEV_ID);
1765 peer_id = le32_get_bits(resp->peer_map_ev.info,
1766 HTT_T2H_PEER_MAP_INFO_PEER_ID);
1767 peer_mac_h16 = le32_get_bits(resp->peer_map_ev.info1,
1768 HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16);
1769 ath12k_dp_get_mac_addr(le32_to_cpu(resp->peer_map_ev.mac_addr_l32),
1770 peer_mac_h16, mac_addr);
1771 ast_hash = le32_get_bits(resp->peer_map_ev.info2,
1772 HTT_T2H_PEER_MAP_INFO2_AST_HASH_VAL);
1773 hw_peer_id = le32_get_bits(resp->peer_map_ev.info1,
1774 HTT_T2H_PEER_MAP_INFO1_HW_PEER_ID);
1775 ath12k_peer_map_event(ab, vdev_id, peer_id, mac_addr, ast_hash,
1776 hw_peer_id);
1777 break;
1778 case HTT_T2H_MSG_TYPE_PEER_MAP3:
1779 vdev_id = le32_get_bits(resp->peer_map_ev.info,
1780 HTT_T2H_PEER_MAP_INFO_VDEV_ID);
1781 peer_id = le32_get_bits(resp->peer_map_ev.info,
1782 HTT_T2H_PEER_MAP_INFO_PEER_ID);
1783 peer_mac_h16 = le32_get_bits(resp->peer_map_ev.info1,
1784 HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16);
1785 ath12k_dp_get_mac_addr(le32_to_cpu(resp->peer_map_ev.mac_addr_l32),
1786 peer_mac_h16, mac_addr);
1787 ath12k_peer_map_event(ab, vdev_id, peer_id, mac_addr, ast_hash,
1788 peer_id);
1789 break;
1790 case HTT_T2H_MSG_TYPE_PEER_UNMAP:
1791 case HTT_T2H_MSG_TYPE_PEER_UNMAP2:
1792 peer_id = le32_get_bits(resp->peer_unmap_ev.info,
1793 HTT_T2H_PEER_UNMAP_INFO_PEER_ID);
1794 ath12k_peer_unmap_event(ab, peer_id);
1795 break;
1796 case HTT_T2H_MSG_TYPE_PPDU_STATS_IND:
1797 ath12k_htt_pull_ppdu_stats(ab, skb);
1798 break;
1799 case HTT_T2H_MSG_TYPE_EXT_STATS_CONF:
1800 ath12k_debugfs_htt_ext_stats_handler(ab, skb);
1801 break;
1802 case HTT_T2H_MSG_TYPE_MLO_TIMESTAMP_OFFSET_IND:
1803 ath12k_htt_mlo_offset_event_handler(ab, skb);
1804 break;
1805 default:
1806 ath12k_dbg(ab, ATH12K_DBG_DP_HTT, "dp_htt event %d not handled\n",
1807 type);
1808 break;
1809 }
1810
1811 dev_kfree_skb_any(skb);
1812 }
1813
ath12k_dp_rx_msdu_coalesce(struct ath12k * ar,struct sk_buff_head * msdu_list,struct sk_buff * first,struct sk_buff * last,u8 l3pad_bytes,int msdu_len)1814 static int ath12k_dp_rx_msdu_coalesce(struct ath12k *ar,
1815 struct sk_buff_head *msdu_list,
1816 struct sk_buff *first, struct sk_buff *last,
1817 u8 l3pad_bytes, int msdu_len)
1818 {
1819 struct ath12k_base *ab = ar->ab;
1820 struct sk_buff *skb;
1821 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(first);
1822 int buf_first_hdr_len, buf_first_len;
1823 struct hal_rx_desc *ldesc;
1824 int space_extra, rem_len, buf_len;
1825 u32 hal_rx_desc_sz = ar->ab->hal.hal_desc_sz;
1826
1827 /* As the msdu is spread across multiple rx buffers,
1828 * find the offset to the start of msdu for computing
1829 * the length of the msdu in the first buffer.
1830 */
1831 buf_first_hdr_len = hal_rx_desc_sz + l3pad_bytes;
1832 buf_first_len = DP_RX_BUFFER_SIZE - buf_first_hdr_len;
1833
1834 if (WARN_ON_ONCE(msdu_len <= buf_first_len)) {
1835 skb_put(first, buf_first_hdr_len + msdu_len);
1836 skb_pull(first, buf_first_hdr_len);
1837 return 0;
1838 }
1839
1840 ldesc = (struct hal_rx_desc *)last->data;
1841 rxcb->is_first_msdu = ath12k_dp_rx_h_first_msdu(ab, ldesc);
1842 rxcb->is_last_msdu = ath12k_dp_rx_h_last_msdu(ab, ldesc);
1843
1844 /* MSDU spans over multiple buffers because the length of the MSDU
1845 * exceeds DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE. So assume the data
1846 * in the first buf is of length DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE.
1847 */
1848 skb_put(first, DP_RX_BUFFER_SIZE);
1849 skb_pull(first, buf_first_hdr_len);
1850
1851 /* When an MSDU spread over multiple buffers MSDU_END
1852 * tlvs are valid only in the last buffer. Copy those tlvs.
1853 */
1854 ath12k_dp_rx_desc_end_tlv_copy(ab, rxcb->rx_desc, ldesc);
1855
1856 space_extra = msdu_len - (buf_first_len + skb_tailroom(first));
1857 if (space_extra > 0 &&
1858 (pskb_expand_head(first, 0, space_extra, GFP_ATOMIC) < 0)) {
1859 /* Free up all buffers of the MSDU */
1860 while ((skb = __skb_dequeue(msdu_list)) != NULL) {
1861 rxcb = ATH12K_SKB_RXCB(skb);
1862 if (!rxcb->is_continuation) {
1863 dev_kfree_skb_any(skb);
1864 break;
1865 }
1866 dev_kfree_skb_any(skb);
1867 }
1868 return -ENOMEM;
1869 }
1870
1871 rem_len = msdu_len - buf_first_len;
1872 while ((skb = __skb_dequeue(msdu_list)) != NULL && rem_len > 0) {
1873 rxcb = ATH12K_SKB_RXCB(skb);
1874 if (rxcb->is_continuation)
1875 buf_len = DP_RX_BUFFER_SIZE - hal_rx_desc_sz;
1876 else
1877 buf_len = rem_len;
1878
1879 if (buf_len > (DP_RX_BUFFER_SIZE - hal_rx_desc_sz)) {
1880 WARN_ON_ONCE(1);
1881 dev_kfree_skb_any(skb);
1882 return -EINVAL;
1883 }
1884
1885 skb_put(skb, buf_len + hal_rx_desc_sz);
1886 skb_pull(skb, hal_rx_desc_sz);
1887 skb_copy_from_linear_data(skb, skb_put(first, buf_len),
1888 buf_len);
1889 dev_kfree_skb_any(skb);
1890
1891 rem_len -= buf_len;
1892 if (!rxcb->is_continuation)
1893 break;
1894 }
1895
1896 return 0;
1897 }
1898
ath12k_dp_rx_get_msdu_last_buf(struct sk_buff_head * msdu_list,struct sk_buff * first)1899 static struct sk_buff *ath12k_dp_rx_get_msdu_last_buf(struct sk_buff_head *msdu_list,
1900 struct sk_buff *first)
1901 {
1902 struct sk_buff *skb;
1903 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(first);
1904
1905 if (!rxcb->is_continuation)
1906 return first;
1907
1908 skb_queue_walk(msdu_list, skb) {
1909 rxcb = ATH12K_SKB_RXCB(skb);
1910 if (!rxcb->is_continuation)
1911 return skb;
1912 }
1913
1914 return NULL;
1915 }
1916
ath12k_dp_rx_h_csum_offload(struct ath12k * ar,struct sk_buff * msdu)1917 static void ath12k_dp_rx_h_csum_offload(struct ath12k *ar, struct sk_buff *msdu)
1918 {
1919 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu);
1920 struct ath12k_base *ab = ar->ab;
1921 bool ip_csum_fail, l4_csum_fail;
1922
1923 ip_csum_fail = ath12k_dp_rx_h_ip_cksum_fail(ab, rxcb->rx_desc);
1924 l4_csum_fail = ath12k_dp_rx_h_l4_cksum_fail(ab, rxcb->rx_desc);
1925
1926 msdu->ip_summed = (ip_csum_fail || l4_csum_fail) ?
1927 CHECKSUM_NONE : CHECKSUM_UNNECESSARY;
1928 }
1929
ath12k_dp_rx_crypto_mic_len(struct ath12k * ar,enum hal_encrypt_type enctype)1930 static int ath12k_dp_rx_crypto_mic_len(struct ath12k *ar,
1931 enum hal_encrypt_type enctype)
1932 {
1933 switch (enctype) {
1934 case HAL_ENCRYPT_TYPE_OPEN:
1935 case HAL_ENCRYPT_TYPE_TKIP_NO_MIC:
1936 case HAL_ENCRYPT_TYPE_TKIP_MIC:
1937 return 0;
1938 case HAL_ENCRYPT_TYPE_CCMP_128:
1939 return IEEE80211_CCMP_MIC_LEN;
1940 case HAL_ENCRYPT_TYPE_CCMP_256:
1941 return IEEE80211_CCMP_256_MIC_LEN;
1942 case HAL_ENCRYPT_TYPE_GCMP_128:
1943 case HAL_ENCRYPT_TYPE_AES_GCMP_256:
1944 return IEEE80211_GCMP_MIC_LEN;
1945 case HAL_ENCRYPT_TYPE_WEP_40:
1946 case HAL_ENCRYPT_TYPE_WEP_104:
1947 case HAL_ENCRYPT_TYPE_WEP_128:
1948 case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4:
1949 case HAL_ENCRYPT_TYPE_WAPI:
1950 break;
1951 }
1952
1953 ath12k_warn(ar->ab, "unsupported encryption type %d for mic len\n", enctype);
1954 return 0;
1955 }
1956
ath12k_dp_rx_crypto_param_len(struct ath12k * ar,enum hal_encrypt_type enctype)1957 static int ath12k_dp_rx_crypto_param_len(struct ath12k *ar,
1958 enum hal_encrypt_type enctype)
1959 {
1960 switch (enctype) {
1961 case HAL_ENCRYPT_TYPE_OPEN:
1962 return 0;
1963 case HAL_ENCRYPT_TYPE_TKIP_NO_MIC:
1964 case HAL_ENCRYPT_TYPE_TKIP_MIC:
1965 return IEEE80211_TKIP_IV_LEN;
1966 case HAL_ENCRYPT_TYPE_CCMP_128:
1967 return IEEE80211_CCMP_HDR_LEN;
1968 case HAL_ENCRYPT_TYPE_CCMP_256:
1969 return IEEE80211_CCMP_256_HDR_LEN;
1970 case HAL_ENCRYPT_TYPE_GCMP_128:
1971 case HAL_ENCRYPT_TYPE_AES_GCMP_256:
1972 return IEEE80211_GCMP_HDR_LEN;
1973 case HAL_ENCRYPT_TYPE_WEP_40:
1974 case HAL_ENCRYPT_TYPE_WEP_104:
1975 case HAL_ENCRYPT_TYPE_WEP_128:
1976 case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4:
1977 case HAL_ENCRYPT_TYPE_WAPI:
1978 break;
1979 }
1980
1981 ath12k_warn(ar->ab, "unsupported encryption type %d\n", enctype);
1982 return 0;
1983 }
1984
ath12k_dp_rx_crypto_icv_len(struct ath12k * ar,enum hal_encrypt_type enctype)1985 static int ath12k_dp_rx_crypto_icv_len(struct ath12k *ar,
1986 enum hal_encrypt_type enctype)
1987 {
1988 switch (enctype) {
1989 case HAL_ENCRYPT_TYPE_OPEN:
1990 case HAL_ENCRYPT_TYPE_CCMP_128:
1991 case HAL_ENCRYPT_TYPE_CCMP_256:
1992 case HAL_ENCRYPT_TYPE_GCMP_128:
1993 case HAL_ENCRYPT_TYPE_AES_GCMP_256:
1994 return 0;
1995 case HAL_ENCRYPT_TYPE_TKIP_NO_MIC:
1996 case HAL_ENCRYPT_TYPE_TKIP_MIC:
1997 return IEEE80211_TKIP_ICV_LEN;
1998 case HAL_ENCRYPT_TYPE_WEP_40:
1999 case HAL_ENCRYPT_TYPE_WEP_104:
2000 case HAL_ENCRYPT_TYPE_WEP_128:
2001 case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4:
2002 case HAL_ENCRYPT_TYPE_WAPI:
2003 break;
2004 }
2005
2006 ath12k_warn(ar->ab, "unsupported encryption type %d\n", enctype);
2007 return 0;
2008 }
2009
ath12k_dp_rx_h_undecap_nwifi(struct ath12k * ar,struct sk_buff * msdu,enum hal_encrypt_type enctype,struct ieee80211_rx_status * status)2010 static void ath12k_dp_rx_h_undecap_nwifi(struct ath12k *ar,
2011 struct sk_buff *msdu,
2012 enum hal_encrypt_type enctype,
2013 struct ieee80211_rx_status *status)
2014 {
2015 struct ath12k_base *ab = ar->ab;
2016 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu);
2017 u8 decap_hdr[DP_MAX_NWIFI_HDR_LEN];
2018 struct ieee80211_hdr *hdr;
2019 size_t hdr_len;
2020 u8 *crypto_hdr;
2021 u16 qos_ctl;
2022
2023 /* pull decapped header */
2024 hdr = (struct ieee80211_hdr *)msdu->data;
2025 hdr_len = ieee80211_hdrlen(hdr->frame_control);
2026 skb_pull(msdu, hdr_len);
2027
2028 /* Rebuild qos header */
2029 hdr->frame_control |= __cpu_to_le16(IEEE80211_STYPE_QOS_DATA);
2030
2031 /* Reset the order bit as the HT_Control header is stripped */
2032 hdr->frame_control &= ~(__cpu_to_le16(IEEE80211_FCTL_ORDER));
2033
2034 qos_ctl = rxcb->tid;
2035
2036 if (ath12k_dp_rx_h_mesh_ctl_present(ab, rxcb->rx_desc))
2037 qos_ctl |= IEEE80211_QOS_CTL_MESH_CONTROL_PRESENT;
2038
2039 /* TODO: Add other QoS ctl fields when required */
2040
2041 /* copy decap header before overwriting for reuse below */
2042 memcpy(decap_hdr, hdr, hdr_len);
2043
2044 /* Rebuild crypto header for mac80211 use */
2045 if (!(status->flag & RX_FLAG_IV_STRIPPED)) {
2046 crypto_hdr = skb_push(msdu, ath12k_dp_rx_crypto_param_len(ar, enctype));
2047 ath12k_dp_rx_desc_get_crypto_header(ar->ab,
2048 rxcb->rx_desc, crypto_hdr,
2049 enctype);
2050 }
2051
2052 memcpy(skb_push(msdu,
2053 IEEE80211_QOS_CTL_LEN), &qos_ctl,
2054 IEEE80211_QOS_CTL_LEN);
2055 memcpy(skb_push(msdu, hdr_len), decap_hdr, hdr_len);
2056 }
2057
ath12k_dp_rx_h_undecap_raw(struct ath12k * ar,struct sk_buff * msdu,enum hal_encrypt_type enctype,struct ieee80211_rx_status * status,bool decrypted)2058 static void ath12k_dp_rx_h_undecap_raw(struct ath12k *ar, struct sk_buff *msdu,
2059 enum hal_encrypt_type enctype,
2060 struct ieee80211_rx_status *status,
2061 bool decrypted)
2062 {
2063 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu);
2064 struct ieee80211_hdr *hdr;
2065 size_t hdr_len;
2066 size_t crypto_len;
2067
2068 if (!rxcb->is_first_msdu ||
2069 !(rxcb->is_first_msdu && rxcb->is_last_msdu)) {
2070 WARN_ON_ONCE(1);
2071 return;
2072 }
2073
2074 skb_trim(msdu, msdu->len - FCS_LEN);
2075
2076 if (!decrypted)
2077 return;
2078
2079 hdr = (void *)msdu->data;
2080
2081 /* Tail */
2082 if (status->flag & RX_FLAG_IV_STRIPPED) {
2083 skb_trim(msdu, msdu->len -
2084 ath12k_dp_rx_crypto_mic_len(ar, enctype));
2085
2086 skb_trim(msdu, msdu->len -
2087 ath12k_dp_rx_crypto_icv_len(ar, enctype));
2088 } else {
2089 /* MIC */
2090 if (status->flag & RX_FLAG_MIC_STRIPPED)
2091 skb_trim(msdu, msdu->len -
2092 ath12k_dp_rx_crypto_mic_len(ar, enctype));
2093
2094 /* ICV */
2095 if (status->flag & RX_FLAG_ICV_STRIPPED)
2096 skb_trim(msdu, msdu->len -
2097 ath12k_dp_rx_crypto_icv_len(ar, enctype));
2098 }
2099
2100 /* MMIC */
2101 if ((status->flag & RX_FLAG_MMIC_STRIPPED) &&
2102 !ieee80211_has_morefrags(hdr->frame_control) &&
2103 enctype == HAL_ENCRYPT_TYPE_TKIP_MIC)
2104 skb_trim(msdu, msdu->len - IEEE80211_CCMP_MIC_LEN);
2105
2106 /* Head */
2107 if (status->flag & RX_FLAG_IV_STRIPPED) {
2108 hdr_len = ieee80211_hdrlen(hdr->frame_control);
2109 crypto_len = ath12k_dp_rx_crypto_param_len(ar, enctype);
2110
2111 memmove(msdu->data + crypto_len, msdu->data, hdr_len);
2112 skb_pull(msdu, crypto_len);
2113 }
2114 }
2115
ath12k_get_dot11_hdr_from_rx_desc(struct ath12k * ar,struct sk_buff * msdu,struct ath12k_skb_rxcb * rxcb,struct ieee80211_rx_status * status,enum hal_encrypt_type enctype)2116 static void ath12k_get_dot11_hdr_from_rx_desc(struct ath12k *ar,
2117 struct sk_buff *msdu,
2118 struct ath12k_skb_rxcb *rxcb,
2119 struct ieee80211_rx_status *status,
2120 enum hal_encrypt_type enctype)
2121 {
2122 struct hal_rx_desc *rx_desc = rxcb->rx_desc;
2123 struct ath12k_base *ab = ar->ab;
2124 size_t hdr_len, crypto_len;
2125 struct ieee80211_hdr *hdr;
2126 u16 qos_ctl;
2127 __le16 fc;
2128 u8 *crypto_hdr;
2129
2130 if (!(status->flag & RX_FLAG_IV_STRIPPED)) {
2131 crypto_len = ath12k_dp_rx_crypto_param_len(ar, enctype);
2132 crypto_hdr = skb_push(msdu, crypto_len);
2133 ath12k_dp_rx_desc_get_crypto_header(ab, rx_desc, crypto_hdr, enctype);
2134 }
2135
2136 fc = cpu_to_le16(ath12k_dp_rxdesc_get_mpdu_frame_ctrl(ab, rx_desc));
2137 hdr_len = ieee80211_hdrlen(fc);
2138 skb_push(msdu, hdr_len);
2139 hdr = (struct ieee80211_hdr *)msdu->data;
2140 hdr->frame_control = fc;
2141
2142 /* Get wifi header from rx_desc */
2143 ath12k_dp_rx_desc_get_dot11_hdr(ab, rx_desc, hdr);
2144
2145 if (rxcb->is_mcbc)
2146 status->flag &= ~RX_FLAG_PN_VALIDATED;
2147
2148 /* Add QOS header */
2149 if (ieee80211_is_data_qos(hdr->frame_control)) {
2150 qos_ctl = rxcb->tid;
2151 if (ath12k_dp_rx_h_mesh_ctl_present(ab, rx_desc))
2152 qos_ctl |= IEEE80211_QOS_CTL_MESH_CONTROL_PRESENT;
2153
2154 /* TODO: Add other QoS ctl fields when required */
2155 memcpy(msdu->data + (hdr_len - IEEE80211_QOS_CTL_LEN),
2156 &qos_ctl, IEEE80211_QOS_CTL_LEN);
2157 }
2158 }
2159
ath12k_dp_rx_h_undecap_eth(struct ath12k * ar,struct sk_buff * msdu,enum hal_encrypt_type enctype,struct ieee80211_rx_status * status)2160 static void ath12k_dp_rx_h_undecap_eth(struct ath12k *ar,
2161 struct sk_buff *msdu,
2162 enum hal_encrypt_type enctype,
2163 struct ieee80211_rx_status *status)
2164 {
2165 struct ieee80211_hdr *hdr;
2166 struct ethhdr *eth;
2167 u8 da[ETH_ALEN];
2168 u8 sa[ETH_ALEN];
2169 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu);
2170 struct ath12k_dp_rx_rfc1042_hdr rfc = {0xaa, 0xaa, 0x03, {0x00, 0x00, 0x00}};
2171
2172 eth = (struct ethhdr *)msdu->data;
2173 ether_addr_copy(da, eth->h_dest);
2174 ether_addr_copy(sa, eth->h_source);
2175 rfc.snap_type = eth->h_proto;
2176 skb_pull(msdu, sizeof(*eth));
2177 memcpy(skb_push(msdu, sizeof(rfc)), &rfc,
2178 sizeof(rfc));
2179 ath12k_get_dot11_hdr_from_rx_desc(ar, msdu, rxcb, status, enctype);
2180
2181 /* original 802.11 header has a different DA and in
2182 * case of 4addr it may also have different SA
2183 */
2184 hdr = (struct ieee80211_hdr *)msdu->data;
2185 ether_addr_copy(ieee80211_get_DA(hdr), da);
2186 ether_addr_copy(ieee80211_get_SA(hdr), sa);
2187 }
2188
ath12k_dp_rx_h_undecap(struct ath12k * ar,struct sk_buff * msdu,struct hal_rx_desc * rx_desc,enum hal_encrypt_type enctype,struct ieee80211_rx_status * status,bool decrypted)2189 static void ath12k_dp_rx_h_undecap(struct ath12k *ar, struct sk_buff *msdu,
2190 struct hal_rx_desc *rx_desc,
2191 enum hal_encrypt_type enctype,
2192 struct ieee80211_rx_status *status,
2193 bool decrypted)
2194 {
2195 struct ath12k_base *ab = ar->ab;
2196 u8 decap;
2197 struct ethhdr *ehdr;
2198
2199 decap = ath12k_dp_rx_h_decap_type(ab, rx_desc);
2200
2201 switch (decap) {
2202 case DP_RX_DECAP_TYPE_NATIVE_WIFI:
2203 ath12k_dp_rx_h_undecap_nwifi(ar, msdu, enctype, status);
2204 break;
2205 case DP_RX_DECAP_TYPE_RAW:
2206 ath12k_dp_rx_h_undecap_raw(ar, msdu, enctype, status,
2207 decrypted);
2208 break;
2209 case DP_RX_DECAP_TYPE_ETHERNET2_DIX:
2210 ehdr = (struct ethhdr *)msdu->data;
2211
2212 /* mac80211 allows fast path only for authorized STA */
2213 if (ehdr->h_proto == cpu_to_be16(ETH_P_PAE)) {
2214 ATH12K_SKB_RXCB(msdu)->is_eapol = true;
2215 ath12k_dp_rx_h_undecap_eth(ar, msdu, enctype, status);
2216 break;
2217 }
2218
2219 /* PN for mcast packets will be validated in mac80211;
2220 * remove eth header and add 802.11 header.
2221 */
2222 if (ATH12K_SKB_RXCB(msdu)->is_mcbc && decrypted)
2223 ath12k_dp_rx_h_undecap_eth(ar, msdu, enctype, status);
2224 break;
2225 case DP_RX_DECAP_TYPE_8023:
2226 /* TODO: Handle undecap for these formats */
2227 break;
2228 }
2229 }
2230
2231 struct ath12k_peer *
ath12k_dp_rx_h_find_peer(struct ath12k_base * ab,struct sk_buff * msdu)2232 ath12k_dp_rx_h_find_peer(struct ath12k_base *ab, struct sk_buff *msdu)
2233 {
2234 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu);
2235 struct hal_rx_desc *rx_desc = rxcb->rx_desc;
2236 struct ath12k_peer *peer = NULL;
2237
2238 lockdep_assert_held(&ab->base_lock);
2239
2240 if (rxcb->peer_id)
2241 peer = ath12k_peer_find_by_id(ab, rxcb->peer_id);
2242
2243 if (peer)
2244 return peer;
2245
2246 if (!rx_desc || !(ath12k_dp_rxdesc_mac_addr2_valid(ab, rx_desc)))
2247 return NULL;
2248
2249 peer = ath12k_peer_find_by_addr(ab,
2250 ath12k_dp_rxdesc_get_mpdu_start_addr2(ab,
2251 rx_desc));
2252 return peer;
2253 }
2254
ath12k_dp_rx_h_mpdu(struct ath12k * ar,struct sk_buff * msdu,struct hal_rx_desc * rx_desc,struct ieee80211_rx_status * rx_status)2255 static void ath12k_dp_rx_h_mpdu(struct ath12k *ar,
2256 struct sk_buff *msdu,
2257 struct hal_rx_desc *rx_desc,
2258 struct ieee80211_rx_status *rx_status)
2259 {
2260 bool fill_crypto_hdr;
2261 struct ath12k_base *ab = ar->ab;
2262 struct ath12k_skb_rxcb *rxcb;
2263 enum hal_encrypt_type enctype;
2264 bool is_decrypted = false;
2265 struct ieee80211_hdr *hdr;
2266 struct ath12k_peer *peer;
2267 u32 err_bitmap;
2268
2269 /* PN for multicast packets will be checked in mac80211 */
2270 rxcb = ATH12K_SKB_RXCB(msdu);
2271 fill_crypto_hdr = ath12k_dp_rx_h_is_da_mcbc(ar->ab, rx_desc);
2272 rxcb->is_mcbc = fill_crypto_hdr;
2273
2274 if (rxcb->is_mcbc)
2275 rxcb->peer_id = ath12k_dp_rx_h_peer_id(ar->ab, rx_desc);
2276
2277 spin_lock_bh(&ar->ab->base_lock);
2278 peer = ath12k_dp_rx_h_find_peer(ar->ab, msdu);
2279 if (peer) {
2280 if (rxcb->is_mcbc)
2281 enctype = peer->sec_type_grp;
2282 else
2283 enctype = peer->sec_type;
2284 } else {
2285 enctype = HAL_ENCRYPT_TYPE_OPEN;
2286 }
2287 spin_unlock_bh(&ar->ab->base_lock);
2288
2289 err_bitmap = ath12k_dp_rx_h_mpdu_err(ab, rx_desc);
2290 if (enctype != HAL_ENCRYPT_TYPE_OPEN && !err_bitmap)
2291 is_decrypted = ath12k_dp_rx_h_is_decrypted(ab, rx_desc);
2292
2293 /* Clear per-MPDU flags while leaving per-PPDU flags intact */
2294 rx_status->flag &= ~(RX_FLAG_FAILED_FCS_CRC |
2295 RX_FLAG_MMIC_ERROR |
2296 RX_FLAG_DECRYPTED |
2297 RX_FLAG_IV_STRIPPED |
2298 RX_FLAG_MMIC_STRIPPED);
2299
2300 if (err_bitmap & HAL_RX_MPDU_ERR_FCS)
2301 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
2302 if (err_bitmap & HAL_RX_MPDU_ERR_TKIP_MIC)
2303 rx_status->flag |= RX_FLAG_MMIC_ERROR;
2304
2305 if (is_decrypted) {
2306 rx_status->flag |= RX_FLAG_DECRYPTED | RX_FLAG_MMIC_STRIPPED;
2307
2308 if (fill_crypto_hdr)
2309 rx_status->flag |= RX_FLAG_MIC_STRIPPED |
2310 RX_FLAG_ICV_STRIPPED;
2311 else
2312 rx_status->flag |= RX_FLAG_IV_STRIPPED |
2313 RX_FLAG_PN_VALIDATED;
2314 }
2315
2316 ath12k_dp_rx_h_csum_offload(ar, msdu);
2317 ath12k_dp_rx_h_undecap(ar, msdu, rx_desc,
2318 enctype, rx_status, is_decrypted);
2319
2320 if (!is_decrypted || fill_crypto_hdr)
2321 return;
2322
2323 if (ath12k_dp_rx_h_decap_type(ar->ab, rx_desc) !=
2324 DP_RX_DECAP_TYPE_ETHERNET2_DIX) {
2325 hdr = (void *)msdu->data;
2326 hdr->frame_control &= ~__cpu_to_le16(IEEE80211_FCTL_PROTECTED);
2327 }
2328 }
2329
ath12k_dp_rx_h_rate(struct ath12k * ar,struct hal_rx_desc * rx_desc,struct ieee80211_rx_status * rx_status)2330 static void ath12k_dp_rx_h_rate(struct ath12k *ar, struct hal_rx_desc *rx_desc,
2331 struct ieee80211_rx_status *rx_status)
2332 {
2333 struct ath12k_base *ab = ar->ab;
2334 struct ieee80211_supported_band *sband;
2335 enum rx_msdu_start_pkt_type pkt_type;
2336 u8 bw;
2337 u8 rate_mcs, nss;
2338 u8 sgi;
2339 bool is_cck;
2340
2341 pkt_type = ath12k_dp_rx_h_pkt_type(ab, rx_desc);
2342 bw = ath12k_dp_rx_h_rx_bw(ab, rx_desc);
2343 rate_mcs = ath12k_dp_rx_h_rate_mcs(ab, rx_desc);
2344 nss = ath12k_dp_rx_h_nss(ab, rx_desc);
2345 sgi = ath12k_dp_rx_h_sgi(ab, rx_desc);
2346
2347 switch (pkt_type) {
2348 case RX_MSDU_START_PKT_TYPE_11A:
2349 case RX_MSDU_START_PKT_TYPE_11B:
2350 is_cck = (pkt_type == RX_MSDU_START_PKT_TYPE_11B);
2351 sband = &ar->mac.sbands[rx_status->band];
2352 rx_status->rate_idx = ath12k_mac_hw_rate_to_idx(sband, rate_mcs,
2353 is_cck);
2354 break;
2355 case RX_MSDU_START_PKT_TYPE_11N:
2356 rx_status->encoding = RX_ENC_HT;
2357 if (rate_mcs > ATH12K_HT_MCS_MAX) {
2358 ath12k_warn(ar->ab,
2359 "Received with invalid mcs in HT mode %d\n",
2360 rate_mcs);
2361 break;
2362 }
2363 rx_status->rate_idx = rate_mcs + (8 * (nss - 1));
2364 if (sgi)
2365 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
2366 rx_status->bw = ath12k_mac_bw_to_mac80211_bw(bw);
2367 break;
2368 case RX_MSDU_START_PKT_TYPE_11AC:
2369 rx_status->encoding = RX_ENC_VHT;
2370 rx_status->rate_idx = rate_mcs;
2371 if (rate_mcs > ATH12K_VHT_MCS_MAX) {
2372 ath12k_warn(ar->ab,
2373 "Received with invalid mcs in VHT mode %d\n",
2374 rate_mcs);
2375 break;
2376 }
2377 rx_status->nss = nss;
2378 if (sgi)
2379 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
2380 rx_status->bw = ath12k_mac_bw_to_mac80211_bw(bw);
2381 break;
2382 case RX_MSDU_START_PKT_TYPE_11AX:
2383 rx_status->rate_idx = rate_mcs;
2384 if (rate_mcs > ATH12K_HE_MCS_MAX) {
2385 ath12k_warn(ar->ab,
2386 "Received with invalid mcs in HE mode %d\n",
2387 rate_mcs);
2388 break;
2389 }
2390 rx_status->encoding = RX_ENC_HE;
2391 rx_status->nss = nss;
2392 rx_status->he_gi = ath12k_he_gi_to_nl80211_he_gi(sgi);
2393 rx_status->bw = ath12k_mac_bw_to_mac80211_bw(bw);
2394 break;
2395 }
2396 }
2397
ath12k_dp_rx_h_ppdu(struct ath12k * ar,struct hal_rx_desc * rx_desc,struct ieee80211_rx_status * rx_status)2398 void ath12k_dp_rx_h_ppdu(struct ath12k *ar, struct hal_rx_desc *rx_desc,
2399 struct ieee80211_rx_status *rx_status)
2400 {
2401 struct ath12k_base *ab = ar->ab;
2402 u8 channel_num;
2403 u32 center_freq, meta_data;
2404 struct ieee80211_channel *channel;
2405
2406 rx_status->freq = 0;
2407 rx_status->rate_idx = 0;
2408 rx_status->nss = 0;
2409 rx_status->encoding = RX_ENC_LEGACY;
2410 rx_status->bw = RATE_INFO_BW_20;
2411 rx_status->enc_flags = 0;
2412
2413 rx_status->flag |= RX_FLAG_NO_SIGNAL_VAL;
2414
2415 meta_data = ath12k_dp_rx_h_freq(ab, rx_desc);
2416 channel_num = meta_data;
2417 center_freq = meta_data >> 16;
2418
2419 if (center_freq >= ATH12K_MIN_6G_FREQ &&
2420 center_freq <= ATH12K_MAX_6G_FREQ) {
2421 rx_status->band = NL80211_BAND_6GHZ;
2422 rx_status->freq = center_freq;
2423 } else if (channel_num >= 1 && channel_num <= 14) {
2424 rx_status->band = NL80211_BAND_2GHZ;
2425 } else if (channel_num >= 36 && channel_num <= 173) {
2426 rx_status->band = NL80211_BAND_5GHZ;
2427 } else {
2428 spin_lock_bh(&ar->data_lock);
2429 channel = ar->rx_channel;
2430 if (channel) {
2431 rx_status->band = channel->band;
2432 channel_num =
2433 ieee80211_frequency_to_channel(channel->center_freq);
2434 }
2435 spin_unlock_bh(&ar->data_lock);
2436 ath12k_dbg_dump(ar->ab, ATH12K_DBG_DATA, NULL, "rx_desc: ",
2437 rx_desc, sizeof(*rx_desc));
2438 }
2439
2440 if (rx_status->band != NL80211_BAND_6GHZ)
2441 rx_status->freq = ieee80211_channel_to_frequency(channel_num,
2442 rx_status->band);
2443
2444 ath12k_dp_rx_h_rate(ar, rx_desc, rx_status);
2445 }
2446
ath12k_dp_rx_deliver_msdu(struct ath12k * ar,struct napi_struct * napi,struct sk_buff * msdu,struct ieee80211_rx_status * status)2447 static void ath12k_dp_rx_deliver_msdu(struct ath12k *ar, struct napi_struct *napi,
2448 struct sk_buff *msdu,
2449 struct ieee80211_rx_status *status)
2450 {
2451 struct ath12k_base *ab = ar->ab;
2452 static const struct ieee80211_radiotap_he known = {
2453 .data1 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN |
2454 IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN),
2455 .data2 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN),
2456 };
2457 struct ieee80211_radiotap_he *he;
2458 struct ieee80211_rx_status *rx_status;
2459 struct ieee80211_sta *pubsta;
2460 struct ath12k_peer *peer;
2461 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu);
2462 u8 decap = DP_RX_DECAP_TYPE_RAW;
2463 bool is_mcbc = rxcb->is_mcbc;
2464 bool is_eapol = rxcb->is_eapol;
2465
2466 if (status->encoding == RX_ENC_HE && !(status->flag & RX_FLAG_RADIOTAP_HE) &&
2467 !(status->flag & RX_FLAG_SKIP_MONITOR)) {
2468 he = skb_push(msdu, sizeof(known));
2469 memcpy(he, &known, sizeof(known));
2470 status->flag |= RX_FLAG_RADIOTAP_HE;
2471 }
2472
2473 if (!(status->flag & RX_FLAG_ONLY_MONITOR))
2474 decap = ath12k_dp_rx_h_decap_type(ab, rxcb->rx_desc);
2475
2476 spin_lock_bh(&ab->base_lock);
2477 peer = ath12k_dp_rx_h_find_peer(ab, msdu);
2478
2479 pubsta = peer ? peer->sta : NULL;
2480
2481 if (pubsta && pubsta->valid_links) {
2482 status->link_valid = 1;
2483 status->link_id = peer->link_id;
2484 }
2485
2486 spin_unlock_bh(&ab->base_lock);
2487
2488 ath12k_dbg(ab, ATH12K_DBG_DATA,
2489 "rx skb %p len %u peer %pM %d %s sn %u %s%s%s%s%s%s%s%s%s rate_idx %u vht_nss %u freq %u band %u flag 0x%x fcs-err %i mic-err %i amsdu-more %i\n",
2490 msdu,
2491 msdu->len,
2492 peer ? peer->addr : NULL,
2493 rxcb->tid,
2494 is_mcbc ? "mcast" : "ucast",
2495 ath12k_dp_rx_h_seq_no(ab, rxcb->rx_desc),
2496 (status->encoding == RX_ENC_LEGACY) ? "legacy" : "",
2497 (status->encoding == RX_ENC_HT) ? "ht" : "",
2498 (status->encoding == RX_ENC_VHT) ? "vht" : "",
2499 (status->encoding == RX_ENC_HE) ? "he" : "",
2500 (status->bw == RATE_INFO_BW_40) ? "40" : "",
2501 (status->bw == RATE_INFO_BW_80) ? "80" : "",
2502 (status->bw == RATE_INFO_BW_160) ? "160" : "",
2503 (status->bw == RATE_INFO_BW_320) ? "320" : "",
2504 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? "sgi " : "",
2505 status->rate_idx,
2506 status->nss,
2507 status->freq,
2508 status->band, status->flag,
2509 !!(status->flag & RX_FLAG_FAILED_FCS_CRC),
2510 !!(status->flag & RX_FLAG_MMIC_ERROR),
2511 !!(status->flag & RX_FLAG_AMSDU_MORE));
2512
2513 ath12k_dbg_dump(ab, ATH12K_DBG_DP_RX, NULL, "dp rx msdu: ",
2514 msdu->data, msdu->len);
2515
2516 rx_status = IEEE80211_SKB_RXCB(msdu);
2517 *rx_status = *status;
2518
2519 /* TODO: trace rx packet */
2520
2521 /* PN for multicast packets are not validate in HW,
2522 * so skip 802.3 rx path
2523 * Also, fast_rx expects the STA to be authorized, hence
2524 * eapol packets are sent in slow path.
2525 */
2526 if (decap == DP_RX_DECAP_TYPE_ETHERNET2_DIX && !is_eapol &&
2527 !(is_mcbc && rx_status->flag & RX_FLAG_DECRYPTED))
2528 rx_status->flag |= RX_FLAG_8023;
2529
2530 ieee80211_rx_napi(ath12k_ar_to_hw(ar), pubsta, msdu, napi);
2531 }
2532
ath12k_dp_rx_check_nwifi_hdr_len_valid(struct ath12k_base * ab,struct hal_rx_desc * rx_desc,struct sk_buff * msdu)2533 static bool ath12k_dp_rx_check_nwifi_hdr_len_valid(struct ath12k_base *ab,
2534 struct hal_rx_desc *rx_desc,
2535 struct sk_buff *msdu)
2536 {
2537 struct ieee80211_hdr *hdr;
2538 u8 decap_type;
2539 u32 hdr_len;
2540
2541 decap_type = ath12k_dp_rx_h_decap_type(ab, rx_desc);
2542 if (decap_type != DP_RX_DECAP_TYPE_NATIVE_WIFI)
2543 return true;
2544
2545 hdr = (struct ieee80211_hdr *)msdu->data;
2546 hdr_len = ieee80211_hdrlen(hdr->frame_control);
2547
2548 if ((likely(hdr_len <= DP_MAX_NWIFI_HDR_LEN)))
2549 return true;
2550
2551 ab->soc_stats.invalid_rbm++;
2552 WARN_ON_ONCE(1);
2553 return false;
2554 }
2555
ath12k_dp_rx_process_msdu(struct ath12k * ar,struct sk_buff * msdu,struct sk_buff_head * msdu_list,struct ieee80211_rx_status * rx_status)2556 static int ath12k_dp_rx_process_msdu(struct ath12k *ar,
2557 struct sk_buff *msdu,
2558 struct sk_buff_head *msdu_list,
2559 struct ieee80211_rx_status *rx_status)
2560 {
2561 struct ath12k_base *ab = ar->ab;
2562 struct hal_rx_desc *rx_desc, *lrx_desc;
2563 struct ath12k_skb_rxcb *rxcb;
2564 struct sk_buff *last_buf;
2565 u8 l3_pad_bytes;
2566 u16 msdu_len;
2567 int ret;
2568 u32 hal_rx_desc_sz = ar->ab->hal.hal_desc_sz;
2569
2570 last_buf = ath12k_dp_rx_get_msdu_last_buf(msdu_list, msdu);
2571 if (!last_buf) {
2572 ath12k_warn(ab,
2573 "No valid Rx buffer to access MSDU_END tlv\n");
2574 ret = -EIO;
2575 goto free_out;
2576 }
2577
2578 rx_desc = (struct hal_rx_desc *)msdu->data;
2579 lrx_desc = (struct hal_rx_desc *)last_buf->data;
2580 if (!ath12k_dp_rx_h_msdu_done(ab, lrx_desc)) {
2581 ath12k_warn(ab, "msdu_done bit in msdu_end is not set\n");
2582 ret = -EIO;
2583 goto free_out;
2584 }
2585
2586 rxcb = ATH12K_SKB_RXCB(msdu);
2587 rxcb->rx_desc = rx_desc;
2588 msdu_len = ath12k_dp_rx_h_msdu_len(ab, lrx_desc);
2589 l3_pad_bytes = ath12k_dp_rx_h_l3pad(ab, lrx_desc);
2590
2591 if (rxcb->is_frag) {
2592 skb_pull(msdu, hal_rx_desc_sz);
2593 } else if (!rxcb->is_continuation) {
2594 if ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE) {
2595 ret = -EINVAL;
2596 ath12k_warn(ab, "invalid msdu len %u\n", msdu_len);
2597 ath12k_dbg_dump(ab, ATH12K_DBG_DATA, NULL, "", rx_desc,
2598 sizeof(*rx_desc));
2599 goto free_out;
2600 }
2601 skb_put(msdu, hal_rx_desc_sz + l3_pad_bytes + msdu_len);
2602 skb_pull(msdu, hal_rx_desc_sz + l3_pad_bytes);
2603 } else {
2604 ret = ath12k_dp_rx_msdu_coalesce(ar, msdu_list,
2605 msdu, last_buf,
2606 l3_pad_bytes, msdu_len);
2607 if (ret) {
2608 ath12k_warn(ab,
2609 "failed to coalesce msdu rx buffer%d\n", ret);
2610 goto free_out;
2611 }
2612 }
2613
2614 if (unlikely(!ath12k_dp_rx_check_nwifi_hdr_len_valid(ab, rx_desc, msdu))) {
2615 ret = -EINVAL;
2616 goto free_out;
2617 }
2618
2619 ath12k_dp_rx_h_ppdu(ar, rx_desc, rx_status);
2620 ath12k_dp_rx_h_mpdu(ar, msdu, rx_desc, rx_status);
2621
2622 rx_status->flag |= RX_FLAG_SKIP_MONITOR | RX_FLAG_DUP_VALIDATED;
2623
2624 return 0;
2625
2626 free_out:
2627 return ret;
2628 }
2629
ath12k_dp_rx_process_received_packets(struct ath12k_base * ab,struct napi_struct * napi,struct sk_buff_head * msdu_list,int ring_id)2630 static void ath12k_dp_rx_process_received_packets(struct ath12k_base *ab,
2631 struct napi_struct *napi,
2632 struct sk_buff_head *msdu_list,
2633 int ring_id)
2634 {
2635 struct ath12k_hw_group *ag = ab->ag;
2636 struct ieee80211_rx_status rx_status = {0};
2637 struct ath12k_skb_rxcb *rxcb;
2638 struct sk_buff *msdu;
2639 struct ath12k *ar;
2640 struct ath12k_hw_link *hw_links = ag->hw_links;
2641 struct ath12k_base *partner_ab;
2642 u8 hw_link_id, pdev_id;
2643 int ret;
2644
2645 if (skb_queue_empty(msdu_list))
2646 return;
2647
2648 rcu_read_lock();
2649
2650 while ((msdu = __skb_dequeue(msdu_list))) {
2651 rxcb = ATH12K_SKB_RXCB(msdu);
2652 hw_link_id = rxcb->hw_link_id;
2653 partner_ab = ath12k_ag_to_ab(ag,
2654 hw_links[hw_link_id].device_id);
2655 pdev_id = ath12k_hw_mac_id_to_pdev_id(partner_ab->hw_params,
2656 hw_links[hw_link_id].pdev_idx);
2657 ar = partner_ab->pdevs[pdev_id].ar;
2658 if (!rcu_dereference(partner_ab->pdevs_active[pdev_id])) {
2659 dev_kfree_skb_any(msdu);
2660 continue;
2661 }
2662
2663 if (test_bit(ATH12K_FLAG_CAC_RUNNING, &ar->dev_flags)) {
2664 dev_kfree_skb_any(msdu);
2665 continue;
2666 }
2667
2668 ret = ath12k_dp_rx_process_msdu(ar, msdu, msdu_list, &rx_status);
2669 if (ret) {
2670 ath12k_dbg(ab, ATH12K_DBG_DATA,
2671 "Unable to process msdu %d", ret);
2672 dev_kfree_skb_any(msdu);
2673 continue;
2674 }
2675
2676 ath12k_dp_rx_deliver_msdu(ar, napi, msdu, &rx_status);
2677 }
2678
2679 rcu_read_unlock();
2680 }
2681
ath12k_dp_rx_get_peer_id(struct ath12k_base * ab,enum ath12k_peer_metadata_version ver,__le32 peer_metadata)2682 static u16 ath12k_dp_rx_get_peer_id(struct ath12k_base *ab,
2683 enum ath12k_peer_metadata_version ver,
2684 __le32 peer_metadata)
2685 {
2686 switch (ver) {
2687 default:
2688 ath12k_warn(ab, "Unknown peer metadata version: %d", ver);
2689 fallthrough;
2690 case ATH12K_PEER_METADATA_V0:
2691 return le32_get_bits(peer_metadata,
2692 RX_MPDU_DESC_META_DATA_V0_PEER_ID);
2693 case ATH12K_PEER_METADATA_V1:
2694 return le32_get_bits(peer_metadata,
2695 RX_MPDU_DESC_META_DATA_V1_PEER_ID);
2696 case ATH12K_PEER_METADATA_V1A:
2697 return le32_get_bits(peer_metadata,
2698 RX_MPDU_DESC_META_DATA_V1A_PEER_ID);
2699 case ATH12K_PEER_METADATA_V1B:
2700 return le32_get_bits(peer_metadata,
2701 RX_MPDU_DESC_META_DATA_V1B_PEER_ID);
2702 }
2703 }
2704
ath12k_dp_rx_process(struct ath12k_base * ab,int ring_id,struct napi_struct * napi,int budget)2705 int ath12k_dp_rx_process(struct ath12k_base *ab, int ring_id,
2706 struct napi_struct *napi, int budget)
2707 {
2708 struct ath12k_hw_group *ag = ab->ag;
2709 struct list_head rx_desc_used_list[ATH12K_MAX_SOCS];
2710 struct ath12k_hw_link *hw_links = ag->hw_links;
2711 int num_buffs_reaped[ATH12K_MAX_SOCS] = {};
2712 struct ath12k_rx_desc_info *desc_info;
2713 struct ath12k_dp *dp = &ab->dp;
2714 struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring;
2715 struct hal_reo_dest_ring *desc;
2716 struct ath12k_base *partner_ab;
2717 struct sk_buff_head msdu_list;
2718 struct ath12k_skb_rxcb *rxcb;
2719 int total_msdu_reaped = 0;
2720 u8 hw_link_id, device_id;
2721 struct hal_srng *srng;
2722 struct sk_buff *msdu;
2723 bool done = false;
2724 u64 desc_va;
2725
2726 __skb_queue_head_init(&msdu_list);
2727
2728 for (device_id = 0; device_id < ATH12K_MAX_SOCS; device_id++)
2729 INIT_LIST_HEAD(&rx_desc_used_list[device_id]);
2730
2731 srng = &ab->hal.srng_list[dp->reo_dst_ring[ring_id].ring_id];
2732
2733 spin_lock_bh(&srng->lock);
2734
2735 try_again:
2736 ath12k_hal_srng_access_begin(ab, srng);
2737
2738 while ((desc = ath12k_hal_srng_dst_get_next_entry(ab, srng))) {
2739 struct rx_mpdu_desc *mpdu_info;
2740 struct rx_msdu_desc *msdu_info;
2741 enum hal_reo_dest_ring_push_reason push_reason;
2742 u32 cookie;
2743
2744 cookie = le32_get_bits(desc->buf_addr_info.info1,
2745 BUFFER_ADDR_INFO1_SW_COOKIE);
2746
2747 hw_link_id = le32_get_bits(desc->info0,
2748 HAL_REO_DEST_RING_INFO0_SRC_LINK_ID);
2749
2750 desc_va = ((u64)le32_to_cpu(desc->buf_va_hi) << 32 |
2751 le32_to_cpu(desc->buf_va_lo));
2752 desc_info = (struct ath12k_rx_desc_info *)((unsigned long)desc_va);
2753
2754 device_id = hw_links[hw_link_id].device_id;
2755 partner_ab = ath12k_ag_to_ab(ag, device_id);
2756 if (unlikely(!partner_ab)) {
2757 if (desc_info->skb) {
2758 dev_kfree_skb_any(desc_info->skb);
2759 desc_info->skb = NULL;
2760 }
2761
2762 continue;
2763 }
2764
2765 /* retry manual desc retrieval */
2766 if (!desc_info) {
2767 desc_info = ath12k_dp_get_rx_desc(partner_ab, cookie);
2768 if (!desc_info) {
2769 ath12k_warn(partner_ab, "Invalid cookie in manual descriptor retrieval: 0x%x\n",
2770 cookie);
2771 continue;
2772 }
2773 }
2774
2775 if (desc_info->magic != ATH12K_DP_RX_DESC_MAGIC)
2776 ath12k_warn(ab, "Check HW CC implementation");
2777
2778 msdu = desc_info->skb;
2779 desc_info->skb = NULL;
2780
2781 list_add_tail(&desc_info->list, &rx_desc_used_list[device_id]);
2782
2783 rxcb = ATH12K_SKB_RXCB(msdu);
2784 dma_unmap_single(partner_ab->dev, rxcb->paddr,
2785 msdu->len + skb_tailroom(msdu),
2786 DMA_FROM_DEVICE);
2787
2788 num_buffs_reaped[device_id]++;
2789
2790 push_reason = le32_get_bits(desc->info0,
2791 HAL_REO_DEST_RING_INFO0_PUSH_REASON);
2792 if (push_reason !=
2793 HAL_REO_DEST_RING_PUSH_REASON_ROUTING_INSTRUCTION) {
2794 dev_kfree_skb_any(msdu);
2795 ab->soc_stats.hal_reo_error[ring_id]++;
2796 continue;
2797 }
2798
2799 msdu_info = &desc->rx_msdu_info;
2800 mpdu_info = &desc->rx_mpdu_info;
2801
2802 rxcb->is_first_msdu = !!(le32_to_cpu(msdu_info->info0) &
2803 RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU);
2804 rxcb->is_last_msdu = !!(le32_to_cpu(msdu_info->info0) &
2805 RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU);
2806 rxcb->is_continuation = !!(le32_to_cpu(msdu_info->info0) &
2807 RX_MSDU_DESC_INFO0_MSDU_CONTINUATION);
2808 rxcb->hw_link_id = hw_link_id;
2809 rxcb->peer_id = ath12k_dp_rx_get_peer_id(ab, dp->peer_metadata_ver,
2810 mpdu_info->peer_meta_data);
2811 rxcb->tid = le32_get_bits(mpdu_info->info0,
2812 RX_MPDU_DESC_INFO0_TID);
2813
2814 __skb_queue_tail(&msdu_list, msdu);
2815
2816 if (!rxcb->is_continuation) {
2817 total_msdu_reaped++;
2818 done = true;
2819 } else {
2820 done = false;
2821 }
2822
2823 if (total_msdu_reaped >= budget)
2824 break;
2825 }
2826
2827 /* Hw might have updated the head pointer after we cached it.
2828 * In this case, even though there are entries in the ring we'll
2829 * get rx_desc NULL. Give the read another try with updated cached
2830 * head pointer so that we can reap complete MPDU in the current
2831 * rx processing.
2832 */
2833 if (!done && ath12k_hal_srng_dst_num_free(ab, srng, true)) {
2834 ath12k_hal_srng_access_end(ab, srng);
2835 goto try_again;
2836 }
2837
2838 ath12k_hal_srng_access_end(ab, srng);
2839
2840 spin_unlock_bh(&srng->lock);
2841
2842 if (!total_msdu_reaped)
2843 goto exit;
2844
2845 for (device_id = 0; device_id < ATH12K_MAX_SOCS; device_id++) {
2846 if (!num_buffs_reaped[device_id])
2847 continue;
2848
2849 partner_ab = ath12k_ag_to_ab(ag, device_id);
2850 rx_ring = &partner_ab->dp.rx_refill_buf_ring;
2851
2852 ath12k_dp_rx_bufs_replenish(partner_ab, rx_ring,
2853 &rx_desc_used_list[device_id],
2854 num_buffs_reaped[device_id]);
2855 }
2856
2857 ath12k_dp_rx_process_received_packets(ab, napi, &msdu_list,
2858 ring_id);
2859
2860 exit:
2861 return total_msdu_reaped;
2862 }
2863
ath12k_dp_rx_frag_timer(struct timer_list * timer)2864 static void ath12k_dp_rx_frag_timer(struct timer_list *timer)
2865 {
2866 struct ath12k_dp_rx_tid *rx_tid = from_timer(rx_tid, timer, frag_timer);
2867
2868 spin_lock_bh(&rx_tid->ab->base_lock);
2869 if (rx_tid->last_frag_no &&
2870 rx_tid->rx_frag_bitmap == GENMASK(rx_tid->last_frag_no, 0)) {
2871 spin_unlock_bh(&rx_tid->ab->base_lock);
2872 return;
2873 }
2874 ath12k_dp_rx_frags_cleanup(rx_tid, true);
2875 spin_unlock_bh(&rx_tid->ab->base_lock);
2876 }
2877
ath12k_dp_rx_peer_frag_setup(struct ath12k * ar,const u8 * peer_mac,int vdev_id)2878 int ath12k_dp_rx_peer_frag_setup(struct ath12k *ar, const u8 *peer_mac, int vdev_id)
2879 {
2880 struct ath12k_base *ab = ar->ab;
2881 struct crypto_shash *tfm;
2882 struct ath12k_peer *peer;
2883 struct ath12k_dp_rx_tid *rx_tid;
2884 int i;
2885
2886 tfm = crypto_alloc_shash("michael_mic", 0, 0);
2887 if (IS_ERR(tfm))
2888 return PTR_ERR(tfm);
2889
2890 spin_lock_bh(&ab->base_lock);
2891
2892 peer = ath12k_peer_find(ab, vdev_id, peer_mac);
2893 if (!peer) {
2894 spin_unlock_bh(&ab->base_lock);
2895 crypto_free_shash(tfm);
2896 ath12k_warn(ab, "failed to find the peer to set up fragment info\n");
2897 return -ENOENT;
2898 }
2899
2900 if (!peer->primary_link) {
2901 spin_unlock_bh(&ab->base_lock);
2902 crypto_free_shash(tfm);
2903 return 0;
2904 }
2905
2906 for (i = 0; i <= IEEE80211_NUM_TIDS; i++) {
2907 rx_tid = &peer->rx_tid[i];
2908 rx_tid->ab = ab;
2909 timer_setup(&rx_tid->frag_timer, ath12k_dp_rx_frag_timer, 0);
2910 skb_queue_head_init(&rx_tid->rx_frags);
2911 }
2912
2913 peer->tfm_mmic = tfm;
2914 peer->dp_setup_done = true;
2915 spin_unlock_bh(&ab->base_lock);
2916
2917 return 0;
2918 }
2919
ath12k_dp_rx_h_michael_mic(struct crypto_shash * tfm,u8 * key,struct ieee80211_hdr * hdr,u8 * data,size_t data_len,u8 * mic)2920 static int ath12k_dp_rx_h_michael_mic(struct crypto_shash *tfm, u8 *key,
2921 struct ieee80211_hdr *hdr, u8 *data,
2922 size_t data_len, u8 *mic)
2923 {
2924 SHASH_DESC_ON_STACK(desc, tfm);
2925 u8 mic_hdr[16] = {0};
2926 u8 tid = 0;
2927 int ret;
2928
2929 if (!tfm)
2930 return -EINVAL;
2931
2932 desc->tfm = tfm;
2933
2934 ret = crypto_shash_setkey(tfm, key, 8);
2935 if (ret)
2936 goto out;
2937
2938 ret = crypto_shash_init(desc);
2939 if (ret)
2940 goto out;
2941
2942 /* TKIP MIC header */
2943 memcpy(mic_hdr, ieee80211_get_DA(hdr), ETH_ALEN);
2944 memcpy(mic_hdr + ETH_ALEN, ieee80211_get_SA(hdr), ETH_ALEN);
2945 if (ieee80211_is_data_qos(hdr->frame_control))
2946 tid = ieee80211_get_tid(hdr);
2947 mic_hdr[12] = tid;
2948
2949 ret = crypto_shash_update(desc, mic_hdr, 16);
2950 if (ret)
2951 goto out;
2952 ret = crypto_shash_update(desc, data, data_len);
2953 if (ret)
2954 goto out;
2955 ret = crypto_shash_final(desc, mic);
2956 out:
2957 shash_desc_zero(desc);
2958 return ret;
2959 }
2960
ath12k_dp_rx_h_verify_tkip_mic(struct ath12k * ar,struct ath12k_peer * peer,struct sk_buff * msdu)2961 static int ath12k_dp_rx_h_verify_tkip_mic(struct ath12k *ar, struct ath12k_peer *peer,
2962 struct sk_buff *msdu)
2963 {
2964 struct ath12k_base *ab = ar->ab;
2965 struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)msdu->data;
2966 struct ieee80211_rx_status *rxs = IEEE80211_SKB_RXCB(msdu);
2967 struct ieee80211_key_conf *key_conf;
2968 struct ieee80211_hdr *hdr;
2969 u8 mic[IEEE80211_CCMP_MIC_LEN];
2970 int head_len, tail_len, ret;
2971 size_t data_len;
2972 u32 hdr_len, hal_rx_desc_sz = ar->ab->hal.hal_desc_sz;
2973 u8 *key, *data;
2974 u8 key_idx;
2975
2976 if (ath12k_dp_rx_h_enctype(ab, rx_desc) != HAL_ENCRYPT_TYPE_TKIP_MIC)
2977 return 0;
2978
2979 hdr = (struct ieee80211_hdr *)(msdu->data + hal_rx_desc_sz);
2980 hdr_len = ieee80211_hdrlen(hdr->frame_control);
2981 head_len = hdr_len + hal_rx_desc_sz + IEEE80211_TKIP_IV_LEN;
2982 tail_len = IEEE80211_CCMP_MIC_LEN + IEEE80211_TKIP_ICV_LEN + FCS_LEN;
2983
2984 if (!is_multicast_ether_addr(hdr->addr1))
2985 key_idx = peer->ucast_keyidx;
2986 else
2987 key_idx = peer->mcast_keyidx;
2988
2989 key_conf = peer->keys[key_idx];
2990
2991 data = msdu->data + head_len;
2992 data_len = msdu->len - head_len - tail_len;
2993 key = &key_conf->key[NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY];
2994
2995 ret = ath12k_dp_rx_h_michael_mic(peer->tfm_mmic, key, hdr, data, data_len, mic);
2996 if (ret || memcmp(mic, data + data_len, IEEE80211_CCMP_MIC_LEN))
2997 goto mic_fail;
2998
2999 return 0;
3000
3001 mic_fail:
3002 (ATH12K_SKB_RXCB(msdu))->is_first_msdu = true;
3003 (ATH12K_SKB_RXCB(msdu))->is_last_msdu = true;
3004
3005 rxs->flag |= RX_FLAG_MMIC_ERROR | RX_FLAG_MMIC_STRIPPED |
3006 RX_FLAG_IV_STRIPPED | RX_FLAG_DECRYPTED;
3007 skb_pull(msdu, hal_rx_desc_sz);
3008
3009 if (unlikely(!ath12k_dp_rx_check_nwifi_hdr_len_valid(ab, rx_desc, msdu)))
3010 return -EINVAL;
3011
3012 ath12k_dp_rx_h_ppdu(ar, rx_desc, rxs);
3013 ath12k_dp_rx_h_undecap(ar, msdu, rx_desc,
3014 HAL_ENCRYPT_TYPE_TKIP_MIC, rxs, true);
3015 ieee80211_rx(ath12k_ar_to_hw(ar), msdu);
3016 return -EINVAL;
3017 }
3018
ath12k_dp_rx_h_undecap_frag(struct ath12k * ar,struct sk_buff * msdu,enum hal_encrypt_type enctype,u32 flags)3019 static void ath12k_dp_rx_h_undecap_frag(struct ath12k *ar, struct sk_buff *msdu,
3020 enum hal_encrypt_type enctype, u32 flags)
3021 {
3022 struct ieee80211_hdr *hdr;
3023 size_t hdr_len;
3024 size_t crypto_len;
3025 u32 hal_rx_desc_sz = ar->ab->hal.hal_desc_sz;
3026
3027 if (!flags)
3028 return;
3029
3030 hdr = (struct ieee80211_hdr *)(msdu->data + hal_rx_desc_sz);
3031
3032 if (flags & RX_FLAG_MIC_STRIPPED)
3033 skb_trim(msdu, msdu->len -
3034 ath12k_dp_rx_crypto_mic_len(ar, enctype));
3035
3036 if (flags & RX_FLAG_ICV_STRIPPED)
3037 skb_trim(msdu, msdu->len -
3038 ath12k_dp_rx_crypto_icv_len(ar, enctype));
3039
3040 if (flags & RX_FLAG_IV_STRIPPED) {
3041 hdr_len = ieee80211_hdrlen(hdr->frame_control);
3042 crypto_len = ath12k_dp_rx_crypto_param_len(ar, enctype);
3043
3044 memmove(msdu->data + hal_rx_desc_sz + crypto_len,
3045 msdu->data + hal_rx_desc_sz, hdr_len);
3046 skb_pull(msdu, crypto_len);
3047 }
3048 }
3049
ath12k_dp_rx_h_defrag(struct ath12k * ar,struct ath12k_peer * peer,struct ath12k_dp_rx_tid * rx_tid,struct sk_buff ** defrag_skb)3050 static int ath12k_dp_rx_h_defrag(struct ath12k *ar,
3051 struct ath12k_peer *peer,
3052 struct ath12k_dp_rx_tid *rx_tid,
3053 struct sk_buff **defrag_skb)
3054 {
3055 struct ath12k_base *ab = ar->ab;
3056 struct hal_rx_desc *rx_desc;
3057 struct sk_buff *skb, *first_frag, *last_frag;
3058 struct ieee80211_hdr *hdr;
3059 enum hal_encrypt_type enctype;
3060 bool is_decrypted = false;
3061 int msdu_len = 0;
3062 int extra_space;
3063 u32 flags, hal_rx_desc_sz = ar->ab->hal.hal_desc_sz;
3064
3065 first_frag = skb_peek(&rx_tid->rx_frags);
3066 last_frag = skb_peek_tail(&rx_tid->rx_frags);
3067
3068 skb_queue_walk(&rx_tid->rx_frags, skb) {
3069 flags = 0;
3070 rx_desc = (struct hal_rx_desc *)skb->data;
3071 hdr = (struct ieee80211_hdr *)(skb->data + hal_rx_desc_sz);
3072
3073 enctype = ath12k_dp_rx_h_enctype(ab, rx_desc);
3074 if (enctype != HAL_ENCRYPT_TYPE_OPEN)
3075 is_decrypted = ath12k_dp_rx_h_is_decrypted(ab,
3076 rx_desc);
3077
3078 if (is_decrypted) {
3079 if (skb != first_frag)
3080 flags |= RX_FLAG_IV_STRIPPED;
3081 if (skb != last_frag)
3082 flags |= RX_FLAG_ICV_STRIPPED |
3083 RX_FLAG_MIC_STRIPPED;
3084 }
3085
3086 /* RX fragments are always raw packets */
3087 if (skb != last_frag)
3088 skb_trim(skb, skb->len - FCS_LEN);
3089 ath12k_dp_rx_h_undecap_frag(ar, skb, enctype, flags);
3090
3091 if (skb != first_frag)
3092 skb_pull(skb, hal_rx_desc_sz +
3093 ieee80211_hdrlen(hdr->frame_control));
3094 msdu_len += skb->len;
3095 }
3096
3097 extra_space = msdu_len - (DP_RX_BUFFER_SIZE + skb_tailroom(first_frag));
3098 if (extra_space > 0 &&
3099 (pskb_expand_head(first_frag, 0, extra_space, GFP_ATOMIC) < 0))
3100 return -ENOMEM;
3101
3102 __skb_unlink(first_frag, &rx_tid->rx_frags);
3103 while ((skb = __skb_dequeue(&rx_tid->rx_frags))) {
3104 skb_put_data(first_frag, skb->data, skb->len);
3105 dev_kfree_skb_any(skb);
3106 }
3107
3108 hdr = (struct ieee80211_hdr *)(first_frag->data + hal_rx_desc_sz);
3109 hdr->frame_control &= ~__cpu_to_le16(IEEE80211_FCTL_MOREFRAGS);
3110 ATH12K_SKB_RXCB(first_frag)->is_frag = 1;
3111
3112 if (ath12k_dp_rx_h_verify_tkip_mic(ar, peer, first_frag))
3113 first_frag = NULL;
3114
3115 *defrag_skb = first_frag;
3116 return 0;
3117 }
3118
ath12k_dp_rx_h_defrag_reo_reinject(struct ath12k * ar,struct ath12k_dp_rx_tid * rx_tid,struct sk_buff * defrag_skb)3119 static int ath12k_dp_rx_h_defrag_reo_reinject(struct ath12k *ar,
3120 struct ath12k_dp_rx_tid *rx_tid,
3121 struct sk_buff *defrag_skb)
3122 {
3123 struct ath12k_base *ab = ar->ab;
3124 struct ath12k_dp *dp = &ab->dp;
3125 struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)defrag_skb->data;
3126 struct hal_reo_entrance_ring *reo_ent_ring;
3127 struct hal_reo_dest_ring *reo_dest_ring;
3128 struct dp_link_desc_bank *link_desc_banks;
3129 struct hal_rx_msdu_link *msdu_link;
3130 struct hal_rx_msdu_details *msdu0;
3131 struct hal_srng *srng;
3132 dma_addr_t link_paddr, buf_paddr;
3133 u32 desc_bank, msdu_info, msdu_ext_info, mpdu_info;
3134 u32 cookie, hal_rx_desc_sz, dest_ring_info0, queue_addr_hi;
3135 int ret;
3136 struct ath12k_rx_desc_info *desc_info;
3137 enum hal_rx_buf_return_buf_manager idle_link_rbm = dp->idle_link_rbm;
3138 u8 dst_ind;
3139
3140 hal_rx_desc_sz = ab->hal.hal_desc_sz;
3141 link_desc_banks = dp->link_desc_banks;
3142 reo_dest_ring = rx_tid->dst_ring_desc;
3143
3144 ath12k_hal_rx_reo_ent_paddr_get(ab, &reo_dest_ring->buf_addr_info,
3145 &link_paddr, &cookie);
3146 desc_bank = u32_get_bits(cookie, DP_LINK_DESC_BANK_MASK);
3147
3148 msdu_link = (struct hal_rx_msdu_link *)(link_desc_banks[desc_bank].vaddr +
3149 (link_paddr - link_desc_banks[desc_bank].paddr));
3150 msdu0 = &msdu_link->msdu_link[0];
3151 msdu_ext_info = le32_to_cpu(msdu0->rx_msdu_ext_info.info0);
3152 dst_ind = u32_get_bits(msdu_ext_info, RX_MSDU_EXT_DESC_INFO0_REO_DEST_IND);
3153
3154 memset(msdu0, 0, sizeof(*msdu0));
3155
3156 msdu_info = u32_encode_bits(1, RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU) |
3157 u32_encode_bits(1, RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU) |
3158 u32_encode_bits(0, RX_MSDU_DESC_INFO0_MSDU_CONTINUATION) |
3159 u32_encode_bits(defrag_skb->len - hal_rx_desc_sz,
3160 RX_MSDU_DESC_INFO0_MSDU_LENGTH) |
3161 u32_encode_bits(1, RX_MSDU_DESC_INFO0_VALID_SA) |
3162 u32_encode_bits(1, RX_MSDU_DESC_INFO0_VALID_DA);
3163 msdu0->rx_msdu_info.info0 = cpu_to_le32(msdu_info);
3164 msdu0->rx_msdu_ext_info.info0 = cpu_to_le32(msdu_ext_info);
3165
3166 /* change msdu len in hal rx desc */
3167 ath12k_dp_rxdesc_set_msdu_len(ab, rx_desc, defrag_skb->len - hal_rx_desc_sz);
3168
3169 buf_paddr = dma_map_single(ab->dev, defrag_skb->data,
3170 defrag_skb->len + skb_tailroom(defrag_skb),
3171 DMA_TO_DEVICE);
3172 if (dma_mapping_error(ab->dev, buf_paddr))
3173 return -ENOMEM;
3174
3175 spin_lock_bh(&dp->rx_desc_lock);
3176 desc_info = list_first_entry_or_null(&dp->rx_desc_free_list,
3177 struct ath12k_rx_desc_info,
3178 list);
3179 if (!desc_info) {
3180 spin_unlock_bh(&dp->rx_desc_lock);
3181 ath12k_warn(ab, "failed to find rx desc for reinject\n");
3182 ret = -ENOMEM;
3183 goto err_unmap_dma;
3184 }
3185
3186 desc_info->skb = defrag_skb;
3187 desc_info->in_use = true;
3188
3189 list_del(&desc_info->list);
3190 spin_unlock_bh(&dp->rx_desc_lock);
3191
3192 ATH12K_SKB_RXCB(defrag_skb)->paddr = buf_paddr;
3193
3194 ath12k_hal_rx_buf_addr_info_set(&msdu0->buf_addr_info, buf_paddr,
3195 desc_info->cookie,
3196 HAL_RX_BUF_RBM_SW3_BM);
3197
3198 /* Fill mpdu details into reo entrance ring */
3199 srng = &ab->hal.srng_list[dp->reo_reinject_ring.ring_id];
3200
3201 spin_lock_bh(&srng->lock);
3202 ath12k_hal_srng_access_begin(ab, srng);
3203
3204 reo_ent_ring = ath12k_hal_srng_src_get_next_entry(ab, srng);
3205 if (!reo_ent_ring) {
3206 ath12k_hal_srng_access_end(ab, srng);
3207 spin_unlock_bh(&srng->lock);
3208 ret = -ENOSPC;
3209 goto err_free_desc;
3210 }
3211 memset(reo_ent_ring, 0, sizeof(*reo_ent_ring));
3212
3213 ath12k_hal_rx_buf_addr_info_set(&reo_ent_ring->buf_addr_info, link_paddr,
3214 cookie,
3215 idle_link_rbm);
3216
3217 mpdu_info = u32_encode_bits(1, RX_MPDU_DESC_INFO0_MSDU_COUNT) |
3218 u32_encode_bits(0, RX_MPDU_DESC_INFO0_FRAG_FLAG) |
3219 u32_encode_bits(1, RX_MPDU_DESC_INFO0_RAW_MPDU) |
3220 u32_encode_bits(1, RX_MPDU_DESC_INFO0_VALID_PN) |
3221 u32_encode_bits(rx_tid->tid, RX_MPDU_DESC_INFO0_TID);
3222
3223 reo_ent_ring->rx_mpdu_info.info0 = cpu_to_le32(mpdu_info);
3224 reo_ent_ring->rx_mpdu_info.peer_meta_data =
3225 reo_dest_ring->rx_mpdu_info.peer_meta_data;
3226
3227 reo_ent_ring->queue_addr_lo = cpu_to_le32(lower_32_bits(rx_tid->paddr));
3228 queue_addr_hi = upper_32_bits(rx_tid->paddr);
3229 reo_ent_ring->info0 = le32_encode_bits(queue_addr_hi,
3230 HAL_REO_ENTR_RING_INFO0_QUEUE_ADDR_HI) |
3231 le32_encode_bits(dst_ind,
3232 HAL_REO_ENTR_RING_INFO0_DEST_IND);
3233
3234 reo_ent_ring->info1 = le32_encode_bits(rx_tid->cur_sn,
3235 HAL_REO_ENTR_RING_INFO1_MPDU_SEQ_NUM);
3236 dest_ring_info0 = le32_get_bits(reo_dest_ring->info0,
3237 HAL_REO_DEST_RING_INFO0_SRC_LINK_ID);
3238 reo_ent_ring->info2 =
3239 cpu_to_le32(u32_get_bits(dest_ring_info0,
3240 HAL_REO_ENTR_RING_INFO2_SRC_LINK_ID));
3241
3242 ath12k_hal_srng_access_end(ab, srng);
3243 spin_unlock_bh(&srng->lock);
3244
3245 return 0;
3246
3247 err_free_desc:
3248 spin_lock_bh(&dp->rx_desc_lock);
3249 desc_info->in_use = false;
3250 desc_info->skb = NULL;
3251 list_add_tail(&desc_info->list, &dp->rx_desc_free_list);
3252 spin_unlock_bh(&dp->rx_desc_lock);
3253 err_unmap_dma:
3254 dma_unmap_single(ab->dev, buf_paddr, defrag_skb->len + skb_tailroom(defrag_skb),
3255 DMA_TO_DEVICE);
3256 return ret;
3257 }
3258
ath12k_dp_rx_h_cmp_frags(struct ath12k_base * ab,struct sk_buff * a,struct sk_buff * b)3259 static int ath12k_dp_rx_h_cmp_frags(struct ath12k_base *ab,
3260 struct sk_buff *a, struct sk_buff *b)
3261 {
3262 int frag1, frag2;
3263
3264 frag1 = ath12k_dp_rx_h_frag_no(ab, a);
3265 frag2 = ath12k_dp_rx_h_frag_no(ab, b);
3266
3267 return frag1 - frag2;
3268 }
3269
ath12k_dp_rx_h_sort_frags(struct ath12k_base * ab,struct sk_buff_head * frag_list,struct sk_buff * cur_frag)3270 static void ath12k_dp_rx_h_sort_frags(struct ath12k_base *ab,
3271 struct sk_buff_head *frag_list,
3272 struct sk_buff *cur_frag)
3273 {
3274 struct sk_buff *skb;
3275 int cmp;
3276
3277 skb_queue_walk(frag_list, skb) {
3278 cmp = ath12k_dp_rx_h_cmp_frags(ab, skb, cur_frag);
3279 if (cmp < 0)
3280 continue;
3281 __skb_queue_before(frag_list, skb, cur_frag);
3282 return;
3283 }
3284 __skb_queue_tail(frag_list, cur_frag);
3285 }
3286
ath12k_dp_rx_h_get_pn(struct ath12k * ar,struct sk_buff * skb)3287 static u64 ath12k_dp_rx_h_get_pn(struct ath12k *ar, struct sk_buff *skb)
3288 {
3289 struct ieee80211_hdr *hdr;
3290 u64 pn = 0;
3291 u8 *ehdr;
3292 u32 hal_rx_desc_sz = ar->ab->hal.hal_desc_sz;
3293
3294 hdr = (struct ieee80211_hdr *)(skb->data + hal_rx_desc_sz);
3295 ehdr = skb->data + hal_rx_desc_sz + ieee80211_hdrlen(hdr->frame_control);
3296
3297 pn = ehdr[0];
3298 pn |= (u64)ehdr[1] << 8;
3299 pn |= (u64)ehdr[4] << 16;
3300 pn |= (u64)ehdr[5] << 24;
3301 pn |= (u64)ehdr[6] << 32;
3302 pn |= (u64)ehdr[7] << 40;
3303
3304 return pn;
3305 }
3306
3307 static bool
ath12k_dp_rx_h_defrag_validate_incr_pn(struct ath12k * ar,struct ath12k_dp_rx_tid * rx_tid)3308 ath12k_dp_rx_h_defrag_validate_incr_pn(struct ath12k *ar, struct ath12k_dp_rx_tid *rx_tid)
3309 {
3310 struct ath12k_base *ab = ar->ab;
3311 enum hal_encrypt_type encrypt_type;
3312 struct sk_buff *first_frag, *skb;
3313 struct hal_rx_desc *desc;
3314 u64 last_pn;
3315 u64 cur_pn;
3316
3317 first_frag = skb_peek(&rx_tid->rx_frags);
3318 desc = (struct hal_rx_desc *)first_frag->data;
3319
3320 encrypt_type = ath12k_dp_rx_h_enctype(ab, desc);
3321 if (encrypt_type != HAL_ENCRYPT_TYPE_CCMP_128 &&
3322 encrypt_type != HAL_ENCRYPT_TYPE_CCMP_256 &&
3323 encrypt_type != HAL_ENCRYPT_TYPE_GCMP_128 &&
3324 encrypt_type != HAL_ENCRYPT_TYPE_AES_GCMP_256)
3325 return true;
3326
3327 last_pn = ath12k_dp_rx_h_get_pn(ar, first_frag);
3328 skb_queue_walk(&rx_tid->rx_frags, skb) {
3329 if (skb == first_frag)
3330 continue;
3331
3332 cur_pn = ath12k_dp_rx_h_get_pn(ar, skb);
3333 if (cur_pn != last_pn + 1)
3334 return false;
3335 last_pn = cur_pn;
3336 }
3337 return true;
3338 }
3339
ath12k_dp_rx_frag_h_mpdu(struct ath12k * ar,struct sk_buff * msdu,struct hal_reo_dest_ring * ring_desc)3340 static int ath12k_dp_rx_frag_h_mpdu(struct ath12k *ar,
3341 struct sk_buff *msdu,
3342 struct hal_reo_dest_ring *ring_desc)
3343 {
3344 struct ath12k_base *ab = ar->ab;
3345 struct hal_rx_desc *rx_desc;
3346 struct ath12k_peer *peer;
3347 struct ath12k_dp_rx_tid *rx_tid;
3348 struct sk_buff *defrag_skb = NULL;
3349 u32 peer_id;
3350 u16 seqno, frag_no;
3351 u8 tid;
3352 int ret = 0;
3353 bool more_frags;
3354
3355 rx_desc = (struct hal_rx_desc *)msdu->data;
3356 peer_id = ath12k_dp_rx_h_peer_id(ab, rx_desc);
3357 tid = ath12k_dp_rx_h_tid(ab, rx_desc);
3358 seqno = ath12k_dp_rx_h_seq_no(ab, rx_desc);
3359 frag_no = ath12k_dp_rx_h_frag_no(ab, msdu);
3360 more_frags = ath12k_dp_rx_h_more_frags(ab, msdu);
3361
3362 if (!ath12k_dp_rx_h_seq_ctrl_valid(ab, rx_desc) ||
3363 !ath12k_dp_rx_h_fc_valid(ab, rx_desc) ||
3364 tid > IEEE80211_NUM_TIDS)
3365 return -EINVAL;
3366
3367 /* received unfragmented packet in reo
3368 * exception ring, this shouldn't happen
3369 * as these packets typically come from
3370 * reo2sw srngs.
3371 */
3372 if (WARN_ON_ONCE(!frag_no && !more_frags))
3373 return -EINVAL;
3374
3375 spin_lock_bh(&ab->base_lock);
3376 peer = ath12k_peer_find_by_id(ab, peer_id);
3377 if (!peer) {
3378 ath12k_warn(ab, "failed to find the peer to de-fragment received fragment peer_id %d\n",
3379 peer_id);
3380 ret = -ENOENT;
3381 goto out_unlock;
3382 }
3383
3384 if (!peer->dp_setup_done) {
3385 ath12k_warn(ab, "The peer %pM [%d] has uninitialized datapath\n",
3386 peer->addr, peer_id);
3387 ret = -ENOENT;
3388 goto out_unlock;
3389 }
3390
3391 rx_tid = &peer->rx_tid[tid];
3392
3393 if ((!skb_queue_empty(&rx_tid->rx_frags) && seqno != rx_tid->cur_sn) ||
3394 skb_queue_empty(&rx_tid->rx_frags)) {
3395 /* Flush stored fragments and start a new sequence */
3396 ath12k_dp_rx_frags_cleanup(rx_tid, true);
3397 rx_tid->cur_sn = seqno;
3398 }
3399
3400 if (rx_tid->rx_frag_bitmap & BIT(frag_no)) {
3401 /* Fragment already present */
3402 ret = -EINVAL;
3403 goto out_unlock;
3404 }
3405
3406 if ((!rx_tid->rx_frag_bitmap || frag_no > __fls(rx_tid->rx_frag_bitmap)))
3407 __skb_queue_tail(&rx_tid->rx_frags, msdu);
3408 else
3409 ath12k_dp_rx_h_sort_frags(ab, &rx_tid->rx_frags, msdu);
3410
3411 rx_tid->rx_frag_bitmap |= BIT(frag_no);
3412 if (!more_frags)
3413 rx_tid->last_frag_no = frag_no;
3414
3415 if (frag_no == 0) {
3416 rx_tid->dst_ring_desc = kmemdup(ring_desc,
3417 sizeof(*rx_tid->dst_ring_desc),
3418 GFP_ATOMIC);
3419 if (!rx_tid->dst_ring_desc) {
3420 ret = -ENOMEM;
3421 goto out_unlock;
3422 }
3423 } else {
3424 ath12k_dp_rx_link_desc_return(ab, ring_desc,
3425 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
3426 }
3427
3428 if (!rx_tid->last_frag_no ||
3429 rx_tid->rx_frag_bitmap != GENMASK(rx_tid->last_frag_no, 0)) {
3430 mod_timer(&rx_tid->frag_timer, jiffies +
3431 ATH12K_DP_RX_FRAGMENT_TIMEOUT_MS);
3432 goto out_unlock;
3433 }
3434
3435 spin_unlock_bh(&ab->base_lock);
3436 del_timer_sync(&rx_tid->frag_timer);
3437 spin_lock_bh(&ab->base_lock);
3438
3439 peer = ath12k_peer_find_by_id(ab, peer_id);
3440 if (!peer)
3441 goto err_frags_cleanup;
3442
3443 if (!ath12k_dp_rx_h_defrag_validate_incr_pn(ar, rx_tid))
3444 goto err_frags_cleanup;
3445
3446 if (ath12k_dp_rx_h_defrag(ar, peer, rx_tid, &defrag_skb))
3447 goto err_frags_cleanup;
3448
3449 if (!defrag_skb)
3450 goto err_frags_cleanup;
3451
3452 if (ath12k_dp_rx_h_defrag_reo_reinject(ar, rx_tid, defrag_skb))
3453 goto err_frags_cleanup;
3454
3455 ath12k_dp_rx_frags_cleanup(rx_tid, false);
3456 goto out_unlock;
3457
3458 err_frags_cleanup:
3459 dev_kfree_skb_any(defrag_skb);
3460 ath12k_dp_rx_frags_cleanup(rx_tid, true);
3461 out_unlock:
3462 spin_unlock_bh(&ab->base_lock);
3463 return ret;
3464 }
3465
3466 static int
ath12k_dp_process_rx_err_buf(struct ath12k * ar,struct hal_reo_dest_ring * desc,struct list_head * used_list,bool drop,u32 cookie)3467 ath12k_dp_process_rx_err_buf(struct ath12k *ar, struct hal_reo_dest_ring *desc,
3468 struct list_head *used_list,
3469 bool drop, u32 cookie)
3470 {
3471 struct ath12k_base *ab = ar->ab;
3472 struct sk_buff *msdu;
3473 struct ath12k_skb_rxcb *rxcb;
3474 struct hal_rx_desc *rx_desc;
3475 u16 msdu_len;
3476 u32 hal_rx_desc_sz = ab->hal.hal_desc_sz;
3477 struct ath12k_rx_desc_info *desc_info;
3478 u64 desc_va;
3479
3480 desc_va = ((u64)le32_to_cpu(desc->buf_va_hi) << 32 |
3481 le32_to_cpu(desc->buf_va_lo));
3482 desc_info = (struct ath12k_rx_desc_info *)((unsigned long)desc_va);
3483
3484 /* retry manual desc retrieval */
3485 if (!desc_info) {
3486 desc_info = ath12k_dp_get_rx_desc(ab, cookie);
3487 if (!desc_info) {
3488 ath12k_warn(ab, "Invalid cookie in DP rx error descriptor retrieval: 0x%x\n",
3489 cookie);
3490 return -EINVAL;
3491 }
3492 }
3493
3494 if (desc_info->magic != ATH12K_DP_RX_DESC_MAGIC)
3495 ath12k_warn(ab, " RX Exception, Check HW CC implementation");
3496
3497 msdu = desc_info->skb;
3498 desc_info->skb = NULL;
3499
3500 list_add_tail(&desc_info->list, used_list);
3501
3502 rxcb = ATH12K_SKB_RXCB(msdu);
3503 dma_unmap_single(ar->ab->dev, rxcb->paddr,
3504 msdu->len + skb_tailroom(msdu),
3505 DMA_FROM_DEVICE);
3506
3507 if (drop) {
3508 dev_kfree_skb_any(msdu);
3509 return 0;
3510 }
3511
3512 rcu_read_lock();
3513 if (!rcu_dereference(ar->ab->pdevs_active[ar->pdev_idx])) {
3514 dev_kfree_skb_any(msdu);
3515 goto exit;
3516 }
3517
3518 if (test_bit(ATH12K_FLAG_CAC_RUNNING, &ar->dev_flags)) {
3519 dev_kfree_skb_any(msdu);
3520 goto exit;
3521 }
3522
3523 rx_desc = (struct hal_rx_desc *)msdu->data;
3524 msdu_len = ath12k_dp_rx_h_msdu_len(ar->ab, rx_desc);
3525 if ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE) {
3526 ath12k_warn(ar->ab, "invalid msdu leng %u", msdu_len);
3527 ath12k_dbg_dump(ar->ab, ATH12K_DBG_DATA, NULL, "", rx_desc,
3528 sizeof(*rx_desc));
3529 dev_kfree_skb_any(msdu);
3530 goto exit;
3531 }
3532
3533 skb_put(msdu, hal_rx_desc_sz + msdu_len);
3534
3535 if (ath12k_dp_rx_frag_h_mpdu(ar, msdu, desc)) {
3536 dev_kfree_skb_any(msdu);
3537 ath12k_dp_rx_link_desc_return(ar->ab, desc,
3538 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
3539 }
3540 exit:
3541 rcu_read_unlock();
3542 return 0;
3543 }
3544
ath12k_dp_rx_process_err(struct ath12k_base * ab,struct napi_struct * napi,int budget)3545 int ath12k_dp_rx_process_err(struct ath12k_base *ab, struct napi_struct *napi,
3546 int budget)
3547 {
3548 struct ath12k_hw_group *ag = ab->ag;
3549 struct list_head rx_desc_used_list[ATH12K_MAX_SOCS];
3550 u32 msdu_cookies[HAL_NUM_RX_MSDUS_PER_LINK_DESC];
3551 int num_buffs_reaped[ATH12K_MAX_SOCS] = {};
3552 struct dp_link_desc_bank *link_desc_banks;
3553 enum hal_rx_buf_return_buf_manager rbm;
3554 struct hal_rx_msdu_link *link_desc_va;
3555 int tot_n_bufs_reaped, quota, ret, i;
3556 struct hal_reo_dest_ring *reo_desc;
3557 struct dp_rxdma_ring *rx_ring;
3558 struct dp_srng *reo_except;
3559 struct ath12k_hw_link *hw_links = ag->hw_links;
3560 struct ath12k_base *partner_ab;
3561 u8 hw_link_id, device_id;
3562 u32 desc_bank, num_msdus;
3563 struct hal_srng *srng;
3564 struct ath12k *ar;
3565 dma_addr_t paddr;
3566 bool is_frag;
3567 bool drop;
3568 int pdev_id;
3569
3570 tot_n_bufs_reaped = 0;
3571 quota = budget;
3572
3573 for (device_id = 0; device_id < ATH12K_MAX_SOCS; device_id++)
3574 INIT_LIST_HEAD(&rx_desc_used_list[device_id]);
3575
3576 reo_except = &ab->dp.reo_except_ring;
3577
3578 srng = &ab->hal.srng_list[reo_except->ring_id];
3579
3580 spin_lock_bh(&srng->lock);
3581
3582 ath12k_hal_srng_access_begin(ab, srng);
3583
3584 while (budget &&
3585 (reo_desc = ath12k_hal_srng_dst_get_next_entry(ab, srng))) {
3586 drop = false;
3587 ab->soc_stats.err_ring_pkts++;
3588
3589 ret = ath12k_hal_desc_reo_parse_err(ab, reo_desc, &paddr,
3590 &desc_bank);
3591 if (ret) {
3592 ath12k_warn(ab, "failed to parse error reo desc %d\n",
3593 ret);
3594 continue;
3595 }
3596
3597 hw_link_id = le32_get_bits(reo_desc->info0,
3598 HAL_REO_DEST_RING_INFO0_SRC_LINK_ID);
3599 device_id = hw_links[hw_link_id].device_id;
3600 partner_ab = ath12k_ag_to_ab(ag, device_id);
3601
3602 pdev_id = ath12k_hw_mac_id_to_pdev_id(partner_ab->hw_params,
3603 hw_links[hw_link_id].pdev_idx);
3604 ar = partner_ab->pdevs[pdev_id].ar;
3605
3606 link_desc_banks = partner_ab->dp.link_desc_banks;
3607 link_desc_va = link_desc_banks[desc_bank].vaddr +
3608 (paddr - link_desc_banks[desc_bank].paddr);
3609 ath12k_hal_rx_msdu_link_info_get(link_desc_va, &num_msdus, msdu_cookies,
3610 &rbm);
3611 if (rbm != partner_ab->dp.idle_link_rbm &&
3612 rbm != HAL_RX_BUF_RBM_SW3_BM &&
3613 rbm != partner_ab->hw_params->hal_params->rx_buf_rbm) {
3614 ab->soc_stats.invalid_rbm++;
3615 ath12k_warn(ab, "invalid return buffer manager %d\n", rbm);
3616 ath12k_dp_rx_link_desc_return(partner_ab, reo_desc,
3617 HAL_WBM_REL_BM_ACT_REL_MSDU);
3618 continue;
3619 }
3620
3621 is_frag = !!(le32_to_cpu(reo_desc->rx_mpdu_info.info0) &
3622 RX_MPDU_DESC_INFO0_FRAG_FLAG);
3623
3624 /* Process only rx fragments with one msdu per link desc below, and drop
3625 * msdu's indicated due to error reasons.
3626 * Dynamic fragmentation not supported in Multi-link client, so drop the
3627 * partner device buffers.
3628 */
3629 if (!is_frag || num_msdus > 1 ||
3630 partner_ab->device_id != ab->device_id) {
3631 drop = true;
3632
3633 /* Return the link desc back to wbm idle list */
3634 ath12k_dp_rx_link_desc_return(partner_ab, reo_desc,
3635 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
3636 }
3637
3638 for (i = 0; i < num_msdus; i++) {
3639 if (!ath12k_dp_process_rx_err_buf(ar, reo_desc,
3640 &rx_desc_used_list[device_id],
3641 drop,
3642 msdu_cookies[i])) {
3643 num_buffs_reaped[device_id]++;
3644 tot_n_bufs_reaped++;
3645 }
3646 }
3647
3648 if (tot_n_bufs_reaped >= quota) {
3649 tot_n_bufs_reaped = quota;
3650 goto exit;
3651 }
3652
3653 budget = quota - tot_n_bufs_reaped;
3654 }
3655
3656 exit:
3657 ath12k_hal_srng_access_end(ab, srng);
3658
3659 spin_unlock_bh(&srng->lock);
3660
3661 for (device_id = 0; device_id < ATH12K_MAX_SOCS; device_id++) {
3662 if (!num_buffs_reaped[device_id])
3663 continue;
3664
3665 partner_ab = ath12k_ag_to_ab(ag, device_id);
3666 rx_ring = &partner_ab->dp.rx_refill_buf_ring;
3667
3668 ath12k_dp_rx_bufs_replenish(partner_ab, rx_ring,
3669 &rx_desc_used_list[device_id],
3670 num_buffs_reaped[device_id]);
3671 }
3672
3673 return tot_n_bufs_reaped;
3674 }
3675
ath12k_dp_rx_null_q_desc_sg_drop(struct ath12k * ar,int msdu_len,struct sk_buff_head * msdu_list)3676 static void ath12k_dp_rx_null_q_desc_sg_drop(struct ath12k *ar,
3677 int msdu_len,
3678 struct sk_buff_head *msdu_list)
3679 {
3680 struct sk_buff *skb, *tmp;
3681 struct ath12k_skb_rxcb *rxcb;
3682 int n_buffs;
3683
3684 n_buffs = DIV_ROUND_UP(msdu_len,
3685 (DP_RX_BUFFER_SIZE - ar->ab->hal.hal_desc_sz));
3686
3687 skb_queue_walk_safe(msdu_list, skb, tmp) {
3688 rxcb = ATH12K_SKB_RXCB(skb);
3689 if (rxcb->err_rel_src == HAL_WBM_REL_SRC_MODULE_REO &&
3690 rxcb->err_code == HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO) {
3691 if (!n_buffs)
3692 break;
3693 __skb_unlink(skb, msdu_list);
3694 dev_kfree_skb_any(skb);
3695 n_buffs--;
3696 }
3697 }
3698 }
3699
ath12k_dp_rx_h_null_q_desc(struct ath12k * ar,struct sk_buff * msdu,struct ieee80211_rx_status * status,struct sk_buff_head * msdu_list)3700 static int ath12k_dp_rx_h_null_q_desc(struct ath12k *ar, struct sk_buff *msdu,
3701 struct ieee80211_rx_status *status,
3702 struct sk_buff_head *msdu_list)
3703 {
3704 struct ath12k_base *ab = ar->ab;
3705 u16 msdu_len;
3706 struct hal_rx_desc *desc = (struct hal_rx_desc *)msdu->data;
3707 u8 l3pad_bytes;
3708 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu);
3709 u32 hal_rx_desc_sz = ar->ab->hal.hal_desc_sz;
3710
3711 msdu_len = ath12k_dp_rx_h_msdu_len(ab, desc);
3712
3713 if (!rxcb->is_frag && ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE)) {
3714 /* First buffer will be freed by the caller, so deduct it's length */
3715 msdu_len = msdu_len - (DP_RX_BUFFER_SIZE - hal_rx_desc_sz);
3716 ath12k_dp_rx_null_q_desc_sg_drop(ar, msdu_len, msdu_list);
3717 return -EINVAL;
3718 }
3719
3720 /* Even after cleaning up the sg buffers in the msdu list with above check
3721 * any msdu received with continuation flag needs to be dropped as invalid.
3722 * This protects against some random err frame with continuation flag.
3723 */
3724 if (rxcb->is_continuation)
3725 return -EINVAL;
3726
3727 if (!ath12k_dp_rx_h_msdu_done(ab, desc)) {
3728 ath12k_warn(ar->ab,
3729 "msdu_done bit not set in null_q_des processing\n");
3730 __skb_queue_purge(msdu_list);
3731 return -EIO;
3732 }
3733
3734 /* Handle NULL queue descriptor violations arising out a missing
3735 * REO queue for a given peer or a given TID. This typically
3736 * may happen if a packet is received on a QOS enabled TID before the
3737 * ADDBA negotiation for that TID, when the TID queue is setup. Or
3738 * it may also happen for MC/BC frames if they are not routed to the
3739 * non-QOS TID queue, in the absence of any other default TID queue.
3740 * This error can show up both in a REO destination or WBM release ring.
3741 */
3742
3743 if (rxcb->is_frag) {
3744 skb_pull(msdu, hal_rx_desc_sz);
3745 } else {
3746 l3pad_bytes = ath12k_dp_rx_h_l3pad(ab, desc);
3747
3748 if ((hal_rx_desc_sz + l3pad_bytes + msdu_len) > DP_RX_BUFFER_SIZE)
3749 return -EINVAL;
3750
3751 skb_put(msdu, hal_rx_desc_sz + l3pad_bytes + msdu_len);
3752 skb_pull(msdu, hal_rx_desc_sz + l3pad_bytes);
3753 }
3754 if (unlikely(!ath12k_dp_rx_check_nwifi_hdr_len_valid(ab, desc, msdu)))
3755 return -EINVAL;
3756
3757 ath12k_dp_rx_h_ppdu(ar, desc, status);
3758
3759 ath12k_dp_rx_h_mpdu(ar, msdu, desc, status);
3760
3761 rxcb->tid = ath12k_dp_rx_h_tid(ab, desc);
3762
3763 /* Please note that caller will having the access to msdu and completing
3764 * rx with mac80211. Need not worry about cleaning up amsdu_list.
3765 */
3766
3767 return 0;
3768 }
3769
ath12k_dp_rx_h_reo_err(struct ath12k * ar,struct sk_buff * msdu,struct ieee80211_rx_status * status,struct sk_buff_head * msdu_list)3770 static bool ath12k_dp_rx_h_reo_err(struct ath12k *ar, struct sk_buff *msdu,
3771 struct ieee80211_rx_status *status,
3772 struct sk_buff_head *msdu_list)
3773 {
3774 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu);
3775 bool drop = false;
3776
3777 ar->ab->soc_stats.reo_error[rxcb->err_code]++;
3778
3779 switch (rxcb->err_code) {
3780 case HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO:
3781 if (ath12k_dp_rx_h_null_q_desc(ar, msdu, status, msdu_list))
3782 drop = true;
3783 break;
3784 case HAL_REO_DEST_RING_ERROR_CODE_PN_CHECK_FAILED:
3785 /* TODO: Do not drop PN failed packets in the driver;
3786 * instead, it is good to drop such packets in mac80211
3787 * after incrementing the replay counters.
3788 */
3789 fallthrough;
3790 default:
3791 /* TODO: Review other errors and process them to mac80211
3792 * as appropriate.
3793 */
3794 drop = true;
3795 break;
3796 }
3797
3798 return drop;
3799 }
3800
ath12k_dp_rx_h_tkip_mic_err(struct ath12k * ar,struct sk_buff * msdu,struct ieee80211_rx_status * status)3801 static bool ath12k_dp_rx_h_tkip_mic_err(struct ath12k *ar, struct sk_buff *msdu,
3802 struct ieee80211_rx_status *status)
3803 {
3804 struct ath12k_base *ab = ar->ab;
3805 u16 msdu_len;
3806 struct hal_rx_desc *desc = (struct hal_rx_desc *)msdu->data;
3807 u8 l3pad_bytes;
3808 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu);
3809 u32 hal_rx_desc_sz = ar->ab->hal.hal_desc_sz;
3810
3811 rxcb->is_first_msdu = ath12k_dp_rx_h_first_msdu(ab, desc);
3812 rxcb->is_last_msdu = ath12k_dp_rx_h_last_msdu(ab, desc);
3813
3814 l3pad_bytes = ath12k_dp_rx_h_l3pad(ab, desc);
3815 msdu_len = ath12k_dp_rx_h_msdu_len(ab, desc);
3816 skb_put(msdu, hal_rx_desc_sz + l3pad_bytes + msdu_len);
3817 skb_pull(msdu, hal_rx_desc_sz + l3pad_bytes);
3818
3819 if (unlikely(!ath12k_dp_rx_check_nwifi_hdr_len_valid(ab, desc, msdu)))
3820 return true;
3821
3822 ath12k_dp_rx_h_ppdu(ar, desc, status);
3823
3824 status->flag |= (RX_FLAG_MMIC_STRIPPED | RX_FLAG_MMIC_ERROR |
3825 RX_FLAG_DECRYPTED);
3826
3827 ath12k_dp_rx_h_undecap(ar, msdu, desc,
3828 HAL_ENCRYPT_TYPE_TKIP_MIC, status, false);
3829 return false;
3830 }
3831
ath12k_dp_rx_h_rxdma_err(struct ath12k * ar,struct sk_buff * msdu,struct ieee80211_rx_status * status)3832 static bool ath12k_dp_rx_h_rxdma_err(struct ath12k *ar, struct sk_buff *msdu,
3833 struct ieee80211_rx_status *status)
3834 {
3835 struct ath12k_base *ab = ar->ab;
3836 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu);
3837 struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)msdu->data;
3838 bool drop = false;
3839 u32 err_bitmap;
3840
3841 ar->ab->soc_stats.rxdma_error[rxcb->err_code]++;
3842
3843 switch (rxcb->err_code) {
3844 case HAL_REO_ENTR_RING_RXDMA_ECODE_DECRYPT_ERR:
3845 case HAL_REO_ENTR_RING_RXDMA_ECODE_TKIP_MIC_ERR:
3846 err_bitmap = ath12k_dp_rx_h_mpdu_err(ab, rx_desc);
3847 if (err_bitmap & HAL_RX_MPDU_ERR_TKIP_MIC) {
3848 drop = ath12k_dp_rx_h_tkip_mic_err(ar, msdu, status);
3849 break;
3850 }
3851 fallthrough;
3852 default:
3853 /* TODO: Review other rxdma error code to check if anything is
3854 * worth reporting to mac80211
3855 */
3856 drop = true;
3857 break;
3858 }
3859
3860 return drop;
3861 }
3862
ath12k_dp_rx_wbm_err(struct ath12k * ar,struct napi_struct * napi,struct sk_buff * msdu,struct sk_buff_head * msdu_list)3863 static void ath12k_dp_rx_wbm_err(struct ath12k *ar,
3864 struct napi_struct *napi,
3865 struct sk_buff *msdu,
3866 struct sk_buff_head *msdu_list)
3867 {
3868 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu);
3869 struct ieee80211_rx_status rxs = {0};
3870 bool drop = true;
3871
3872 switch (rxcb->err_rel_src) {
3873 case HAL_WBM_REL_SRC_MODULE_REO:
3874 drop = ath12k_dp_rx_h_reo_err(ar, msdu, &rxs, msdu_list);
3875 break;
3876 case HAL_WBM_REL_SRC_MODULE_RXDMA:
3877 drop = ath12k_dp_rx_h_rxdma_err(ar, msdu, &rxs);
3878 break;
3879 default:
3880 /* msdu will get freed */
3881 break;
3882 }
3883
3884 if (drop) {
3885 dev_kfree_skb_any(msdu);
3886 return;
3887 }
3888
3889 ath12k_dp_rx_deliver_msdu(ar, napi, msdu, &rxs);
3890 }
3891
ath12k_dp_rx_process_wbm_err(struct ath12k_base * ab,struct napi_struct * napi,int budget)3892 int ath12k_dp_rx_process_wbm_err(struct ath12k_base *ab,
3893 struct napi_struct *napi, int budget)
3894 {
3895 struct list_head rx_desc_used_list[ATH12K_MAX_SOCS];
3896 struct ath12k_hw_group *ag = ab->ag;
3897 struct ath12k *ar;
3898 struct ath12k_dp *dp = &ab->dp;
3899 struct dp_rxdma_ring *rx_ring;
3900 struct hal_rx_wbm_rel_info err_info;
3901 struct hal_srng *srng;
3902 struct sk_buff *msdu;
3903 struct sk_buff_head msdu_list, scatter_msdu_list;
3904 struct ath12k_skb_rxcb *rxcb;
3905 void *rx_desc;
3906 int num_buffs_reaped[ATH12K_MAX_SOCS] = {};
3907 int total_num_buffs_reaped = 0;
3908 struct ath12k_rx_desc_info *desc_info;
3909 struct ath12k_hw_link *hw_links = ag->hw_links;
3910 struct ath12k_base *partner_ab;
3911 u8 hw_link_id, device_id;
3912 int ret, pdev_id;
3913 struct hal_rx_desc *msdu_data;
3914
3915 __skb_queue_head_init(&msdu_list);
3916 __skb_queue_head_init(&scatter_msdu_list);
3917
3918 for (device_id = 0; device_id < ATH12K_MAX_SOCS; device_id++)
3919 INIT_LIST_HEAD(&rx_desc_used_list[device_id]);
3920
3921 srng = &ab->hal.srng_list[dp->rx_rel_ring.ring_id];
3922 spin_lock_bh(&srng->lock);
3923
3924 ath12k_hal_srng_access_begin(ab, srng);
3925
3926 while (budget) {
3927 rx_desc = ath12k_hal_srng_dst_get_next_entry(ab, srng);
3928 if (!rx_desc)
3929 break;
3930
3931 ret = ath12k_hal_wbm_desc_parse_err(ab, rx_desc, &err_info);
3932 if (ret) {
3933 ath12k_warn(ab,
3934 "failed to parse rx error in wbm_rel ring desc %d\n",
3935 ret);
3936 continue;
3937 }
3938
3939 desc_info = err_info.rx_desc;
3940
3941 /* retry manual desc retrieval if hw cc is not done */
3942 if (!desc_info) {
3943 desc_info = ath12k_dp_get_rx_desc(ab, err_info.cookie);
3944 if (!desc_info) {
3945 ath12k_warn(ab, "Invalid cookie in DP WBM rx error descriptor retrieval: 0x%x\n",
3946 err_info.cookie);
3947 continue;
3948 }
3949 }
3950
3951 if (desc_info->magic != ATH12K_DP_RX_DESC_MAGIC)
3952 ath12k_warn(ab, "WBM RX err, Check HW CC implementation");
3953
3954 msdu = desc_info->skb;
3955 desc_info->skb = NULL;
3956
3957 device_id = desc_info->device_id;
3958 partner_ab = ath12k_ag_to_ab(ag, device_id);
3959 if (unlikely(!partner_ab)) {
3960 dev_kfree_skb_any(msdu);
3961
3962 /* In any case continuation bit is set
3963 * in the previous record, cleanup scatter_msdu_list
3964 */
3965 ath12k_dp_clean_up_skb_list(&scatter_msdu_list);
3966 continue;
3967 }
3968
3969 list_add_tail(&desc_info->list, &rx_desc_used_list[device_id]);
3970
3971 rxcb = ATH12K_SKB_RXCB(msdu);
3972 dma_unmap_single(partner_ab->dev, rxcb->paddr,
3973 msdu->len + skb_tailroom(msdu),
3974 DMA_FROM_DEVICE);
3975
3976 num_buffs_reaped[device_id]++;
3977 total_num_buffs_reaped++;
3978
3979 if (!err_info.continuation)
3980 budget--;
3981
3982 if (err_info.push_reason !=
3983 HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED) {
3984 dev_kfree_skb_any(msdu);
3985 continue;
3986 }
3987
3988 msdu_data = (struct hal_rx_desc *)msdu->data;
3989 rxcb->err_rel_src = err_info.err_rel_src;
3990 rxcb->err_code = err_info.err_code;
3991 rxcb->is_first_msdu = err_info.first_msdu;
3992 rxcb->is_last_msdu = err_info.last_msdu;
3993 rxcb->is_continuation = err_info.continuation;
3994 rxcb->rx_desc = msdu_data;
3995
3996 if (err_info.continuation) {
3997 __skb_queue_tail(&scatter_msdu_list, msdu);
3998 continue;
3999 }
4000
4001 hw_link_id = ath12k_dp_rx_get_msdu_src_link(partner_ab,
4002 msdu_data);
4003 if (hw_link_id >= ATH12K_GROUP_MAX_RADIO) {
4004 dev_kfree_skb_any(msdu);
4005
4006 /* In any case continuation bit is set
4007 * in the previous record, cleanup scatter_msdu_list
4008 */
4009 ath12k_dp_clean_up_skb_list(&scatter_msdu_list);
4010 continue;
4011 }
4012
4013 if (!skb_queue_empty(&scatter_msdu_list)) {
4014 struct sk_buff *msdu;
4015
4016 skb_queue_walk(&scatter_msdu_list, msdu) {
4017 rxcb = ATH12K_SKB_RXCB(msdu);
4018 rxcb->hw_link_id = hw_link_id;
4019 }
4020
4021 skb_queue_splice_tail_init(&scatter_msdu_list,
4022 &msdu_list);
4023 }
4024
4025 rxcb = ATH12K_SKB_RXCB(msdu);
4026 rxcb->hw_link_id = hw_link_id;
4027 __skb_queue_tail(&msdu_list, msdu);
4028 }
4029
4030 /* In any case continuation bit is set in the
4031 * last record, cleanup scatter_msdu_list
4032 */
4033 ath12k_dp_clean_up_skb_list(&scatter_msdu_list);
4034
4035 ath12k_hal_srng_access_end(ab, srng);
4036
4037 spin_unlock_bh(&srng->lock);
4038
4039 if (!total_num_buffs_reaped)
4040 goto done;
4041
4042 for (device_id = 0; device_id < ATH12K_MAX_SOCS; device_id++) {
4043 if (!num_buffs_reaped[device_id])
4044 continue;
4045
4046 partner_ab = ath12k_ag_to_ab(ag, device_id);
4047 rx_ring = &partner_ab->dp.rx_refill_buf_ring;
4048
4049 ath12k_dp_rx_bufs_replenish(ab, rx_ring,
4050 &rx_desc_used_list[device_id],
4051 num_buffs_reaped[device_id]);
4052 }
4053
4054 rcu_read_lock();
4055 while ((msdu = __skb_dequeue(&msdu_list))) {
4056 rxcb = ATH12K_SKB_RXCB(msdu);
4057 hw_link_id = rxcb->hw_link_id;
4058
4059 device_id = hw_links[hw_link_id].device_id;
4060 partner_ab = ath12k_ag_to_ab(ag, device_id);
4061 if (unlikely(!partner_ab)) {
4062 ath12k_dbg(ab, ATH12K_DBG_DATA,
4063 "Unable to process WBM error msdu due to invalid hw link id %d device id %d\n",
4064 hw_link_id, device_id);
4065 dev_kfree_skb_any(msdu);
4066 continue;
4067 }
4068
4069 pdev_id = ath12k_hw_mac_id_to_pdev_id(partner_ab->hw_params,
4070 hw_links[hw_link_id].pdev_idx);
4071 ar = partner_ab->pdevs[pdev_id].ar;
4072
4073 if (!ar || !rcu_dereference(ar->ab->pdevs_active[pdev_id])) {
4074 dev_kfree_skb_any(msdu);
4075 continue;
4076 }
4077
4078 if (test_bit(ATH12K_FLAG_CAC_RUNNING, &ar->dev_flags)) {
4079 dev_kfree_skb_any(msdu);
4080 continue;
4081 }
4082 ath12k_dp_rx_wbm_err(ar, napi, msdu, &msdu_list);
4083 }
4084 rcu_read_unlock();
4085 done:
4086 return total_num_buffs_reaped;
4087 }
4088
ath12k_dp_rx_process_reo_status(struct ath12k_base * ab)4089 void ath12k_dp_rx_process_reo_status(struct ath12k_base *ab)
4090 {
4091 struct ath12k_dp *dp = &ab->dp;
4092 struct hal_tlv_64_hdr *hdr;
4093 struct hal_srng *srng;
4094 struct ath12k_dp_rx_reo_cmd *cmd, *tmp;
4095 bool found = false;
4096 u16 tag;
4097 struct hal_reo_status reo_status;
4098
4099 srng = &ab->hal.srng_list[dp->reo_status_ring.ring_id];
4100
4101 memset(&reo_status, 0, sizeof(reo_status));
4102
4103 spin_lock_bh(&srng->lock);
4104
4105 ath12k_hal_srng_access_begin(ab, srng);
4106
4107 while ((hdr = ath12k_hal_srng_dst_get_next_entry(ab, srng))) {
4108 tag = le64_get_bits(hdr->tl, HAL_SRNG_TLV_HDR_TAG);
4109
4110 switch (tag) {
4111 case HAL_REO_GET_QUEUE_STATS_STATUS:
4112 ath12k_hal_reo_status_queue_stats(ab, hdr,
4113 &reo_status);
4114 break;
4115 case HAL_REO_FLUSH_QUEUE_STATUS:
4116 ath12k_hal_reo_flush_queue_status(ab, hdr,
4117 &reo_status);
4118 break;
4119 case HAL_REO_FLUSH_CACHE_STATUS:
4120 ath12k_hal_reo_flush_cache_status(ab, hdr,
4121 &reo_status);
4122 break;
4123 case HAL_REO_UNBLOCK_CACHE_STATUS:
4124 ath12k_hal_reo_unblk_cache_status(ab, hdr,
4125 &reo_status);
4126 break;
4127 case HAL_REO_FLUSH_TIMEOUT_LIST_STATUS:
4128 ath12k_hal_reo_flush_timeout_list_status(ab, hdr,
4129 &reo_status);
4130 break;
4131 case HAL_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS:
4132 ath12k_hal_reo_desc_thresh_reached_status(ab, hdr,
4133 &reo_status);
4134 break;
4135 case HAL_REO_UPDATE_RX_REO_QUEUE_STATUS:
4136 ath12k_hal_reo_update_rx_reo_queue_status(ab, hdr,
4137 &reo_status);
4138 break;
4139 default:
4140 ath12k_warn(ab, "Unknown reo status type %d\n", tag);
4141 continue;
4142 }
4143
4144 spin_lock_bh(&dp->reo_cmd_lock);
4145 list_for_each_entry_safe(cmd, tmp, &dp->reo_cmd_list, list) {
4146 if (reo_status.uniform_hdr.cmd_num == cmd->cmd_num) {
4147 found = true;
4148 list_del(&cmd->list);
4149 break;
4150 }
4151 }
4152 spin_unlock_bh(&dp->reo_cmd_lock);
4153
4154 if (found) {
4155 cmd->handler(dp, (void *)&cmd->data,
4156 reo_status.uniform_hdr.cmd_status);
4157 kfree(cmd);
4158 }
4159
4160 found = false;
4161 }
4162
4163 ath12k_hal_srng_access_end(ab, srng);
4164
4165 spin_unlock_bh(&srng->lock);
4166 }
4167
ath12k_dp_rx_free(struct ath12k_base * ab)4168 void ath12k_dp_rx_free(struct ath12k_base *ab)
4169 {
4170 struct ath12k_dp *dp = &ab->dp;
4171 int i;
4172
4173 ath12k_dp_srng_cleanup(ab, &dp->rx_refill_buf_ring.refill_buf_ring);
4174
4175 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) {
4176 if (ab->hw_params->rx_mac_buf_ring)
4177 ath12k_dp_srng_cleanup(ab, &dp->rx_mac_buf_ring[i]);
4178 }
4179
4180 for (i = 0; i < ab->hw_params->num_rxdma_dst_ring; i++)
4181 ath12k_dp_srng_cleanup(ab, &dp->rxdma_err_dst_ring[i]);
4182
4183 ath12k_dp_srng_cleanup(ab, &dp->rxdma_mon_buf_ring.refill_buf_ring);
4184
4185 ath12k_dp_rxdma_buf_free(ab);
4186 }
4187
ath12k_dp_rx_pdev_free(struct ath12k_base * ab,int mac_id)4188 void ath12k_dp_rx_pdev_free(struct ath12k_base *ab, int mac_id)
4189 {
4190 struct ath12k *ar = ab->pdevs[mac_id].ar;
4191
4192 ath12k_dp_rx_pdev_srng_free(ar);
4193 }
4194
ath12k_dp_rxdma_ring_sel_config_qcn9274(struct ath12k_base * ab)4195 int ath12k_dp_rxdma_ring_sel_config_qcn9274(struct ath12k_base *ab)
4196 {
4197 struct ath12k_dp *dp = &ab->dp;
4198 struct htt_rx_ring_tlv_filter tlv_filter = {0};
4199 u32 ring_id;
4200 int ret;
4201 u32 hal_rx_desc_sz = ab->hal.hal_desc_sz;
4202
4203 ring_id = dp->rx_refill_buf_ring.refill_buf_ring.ring_id;
4204
4205 tlv_filter.rx_filter = HTT_RX_TLV_FLAGS_RXDMA_RING;
4206 tlv_filter.pkt_filter_flags2 = HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR;
4207 tlv_filter.pkt_filter_flags3 = HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST |
4208 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST |
4209 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA;
4210 tlv_filter.offset_valid = true;
4211 tlv_filter.rx_packet_offset = hal_rx_desc_sz;
4212
4213 tlv_filter.rx_mpdu_start_offset =
4214 ab->hal_rx_ops->rx_desc_get_mpdu_start_offset();
4215 tlv_filter.rx_msdu_end_offset =
4216 ab->hal_rx_ops->rx_desc_get_msdu_end_offset();
4217
4218 if (ath12k_dp_wmask_compaction_rx_tlv_supported(ab)) {
4219 tlv_filter.rx_mpdu_start_wmask =
4220 ab->hw_params->hal_ops->rxdma_ring_wmask_rx_mpdu_start();
4221 tlv_filter.rx_msdu_end_wmask =
4222 ab->hw_params->hal_ops->rxdma_ring_wmask_rx_msdu_end();
4223 ath12k_dbg(ab, ATH12K_DBG_DATA,
4224 "Configuring compact tlv masks rx_mpdu_start_wmask 0x%x rx_msdu_end_wmask 0x%x\n",
4225 tlv_filter.rx_mpdu_start_wmask, tlv_filter.rx_msdu_end_wmask);
4226 }
4227
4228 ret = ath12k_dp_tx_htt_rx_filter_setup(ab, ring_id, 0,
4229 HAL_RXDMA_BUF,
4230 DP_RXDMA_REFILL_RING_SIZE,
4231 &tlv_filter);
4232
4233 return ret;
4234 }
4235
ath12k_dp_rxdma_ring_sel_config_wcn7850(struct ath12k_base * ab)4236 int ath12k_dp_rxdma_ring_sel_config_wcn7850(struct ath12k_base *ab)
4237 {
4238 struct ath12k_dp *dp = &ab->dp;
4239 struct htt_rx_ring_tlv_filter tlv_filter = {0};
4240 u32 ring_id;
4241 int ret = 0;
4242 u32 hal_rx_desc_sz = ab->hal.hal_desc_sz;
4243 int i;
4244
4245 ring_id = dp->rx_refill_buf_ring.refill_buf_ring.ring_id;
4246
4247 tlv_filter.rx_filter = HTT_RX_TLV_FLAGS_RXDMA_RING;
4248 tlv_filter.pkt_filter_flags2 = HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR;
4249 tlv_filter.pkt_filter_flags3 = HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST |
4250 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST |
4251 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA;
4252 tlv_filter.offset_valid = true;
4253 tlv_filter.rx_packet_offset = hal_rx_desc_sz;
4254
4255 tlv_filter.rx_header_offset = offsetof(struct hal_rx_desc_wcn7850, pkt_hdr_tlv);
4256
4257 tlv_filter.rx_mpdu_start_offset =
4258 ab->hal_rx_ops->rx_desc_get_mpdu_start_offset();
4259 tlv_filter.rx_msdu_end_offset =
4260 ab->hal_rx_ops->rx_desc_get_msdu_end_offset();
4261
4262 /* TODO: Selectively subscribe to required qwords within msdu_end
4263 * and mpdu_start and setup the mask in below msg
4264 * and modify the rx_desc struct
4265 */
4266
4267 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) {
4268 ring_id = dp->rx_mac_buf_ring[i].ring_id;
4269 ret = ath12k_dp_tx_htt_rx_filter_setup(ab, ring_id, i,
4270 HAL_RXDMA_BUF,
4271 DP_RXDMA_REFILL_RING_SIZE,
4272 &tlv_filter);
4273 }
4274
4275 return ret;
4276 }
4277
ath12k_dp_rx_htt_setup(struct ath12k_base * ab)4278 int ath12k_dp_rx_htt_setup(struct ath12k_base *ab)
4279 {
4280 struct ath12k_dp *dp = &ab->dp;
4281 u32 ring_id;
4282 int i, ret;
4283
4284 /* TODO: Need to verify the HTT setup for QCN9224 */
4285 ring_id = dp->rx_refill_buf_ring.refill_buf_ring.ring_id;
4286 ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id, 0, HAL_RXDMA_BUF);
4287 if (ret) {
4288 ath12k_warn(ab, "failed to configure rx_refill_buf_ring %d\n",
4289 ret);
4290 return ret;
4291 }
4292
4293 if (ab->hw_params->rx_mac_buf_ring) {
4294 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) {
4295 ring_id = dp->rx_mac_buf_ring[i].ring_id;
4296 ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id,
4297 i, HAL_RXDMA_BUF);
4298 if (ret) {
4299 ath12k_warn(ab, "failed to configure rx_mac_buf_ring%d %d\n",
4300 i, ret);
4301 return ret;
4302 }
4303 }
4304 }
4305
4306 for (i = 0; i < ab->hw_params->num_rxdma_dst_ring; i++) {
4307 ring_id = dp->rxdma_err_dst_ring[i].ring_id;
4308 ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id,
4309 i, HAL_RXDMA_DST);
4310 if (ret) {
4311 ath12k_warn(ab, "failed to configure rxdma_err_dest_ring%d %d\n",
4312 i, ret);
4313 return ret;
4314 }
4315 }
4316
4317 if (ab->hw_params->rxdma1_enable) {
4318 ring_id = dp->rxdma_mon_buf_ring.refill_buf_ring.ring_id;
4319 ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id,
4320 0, HAL_RXDMA_MONITOR_BUF);
4321 if (ret) {
4322 ath12k_warn(ab, "failed to configure rxdma_mon_buf_ring %d\n",
4323 ret);
4324 return ret;
4325 }
4326 }
4327
4328 ret = ab->hw_params->hw_ops->rxdma_ring_sel_config(ab);
4329 if (ret) {
4330 ath12k_warn(ab, "failed to setup rxdma ring selection config\n");
4331 return ret;
4332 }
4333
4334 return 0;
4335 }
4336
ath12k_dp_rx_alloc(struct ath12k_base * ab)4337 int ath12k_dp_rx_alloc(struct ath12k_base *ab)
4338 {
4339 struct ath12k_dp *dp = &ab->dp;
4340 int i, ret;
4341
4342 idr_init(&dp->rxdma_mon_buf_ring.bufs_idr);
4343 spin_lock_init(&dp->rxdma_mon_buf_ring.idr_lock);
4344
4345 ret = ath12k_dp_srng_setup(ab,
4346 &dp->rx_refill_buf_ring.refill_buf_ring,
4347 HAL_RXDMA_BUF, 0, 0,
4348 DP_RXDMA_BUF_RING_SIZE);
4349 if (ret) {
4350 ath12k_warn(ab, "failed to setup rx_refill_buf_ring\n");
4351 return ret;
4352 }
4353
4354 if (ab->hw_params->rx_mac_buf_ring) {
4355 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) {
4356 ret = ath12k_dp_srng_setup(ab,
4357 &dp->rx_mac_buf_ring[i],
4358 HAL_RXDMA_BUF, 1,
4359 i, DP_RX_MAC_BUF_RING_SIZE);
4360 if (ret) {
4361 ath12k_warn(ab, "failed to setup rx_mac_buf_ring %d\n",
4362 i);
4363 return ret;
4364 }
4365 }
4366 }
4367
4368 for (i = 0; i < ab->hw_params->num_rxdma_dst_ring; i++) {
4369 ret = ath12k_dp_srng_setup(ab, &dp->rxdma_err_dst_ring[i],
4370 HAL_RXDMA_DST, 0, i,
4371 DP_RXDMA_ERR_DST_RING_SIZE);
4372 if (ret) {
4373 ath12k_warn(ab, "failed to setup rxdma_err_dst_ring %d\n", i);
4374 return ret;
4375 }
4376 }
4377
4378 if (ab->hw_params->rxdma1_enable) {
4379 ret = ath12k_dp_srng_setup(ab,
4380 &dp->rxdma_mon_buf_ring.refill_buf_ring,
4381 HAL_RXDMA_MONITOR_BUF, 0, 0,
4382 DP_RXDMA_MONITOR_BUF_RING_SIZE);
4383 if (ret) {
4384 ath12k_warn(ab, "failed to setup HAL_RXDMA_MONITOR_BUF\n");
4385 return ret;
4386 }
4387 }
4388
4389 ret = ath12k_dp_rxdma_buf_setup(ab);
4390 if (ret) {
4391 ath12k_warn(ab, "failed to setup rxdma ring\n");
4392 return ret;
4393 }
4394
4395 return 0;
4396 }
4397
ath12k_dp_rx_pdev_alloc(struct ath12k_base * ab,int mac_id)4398 int ath12k_dp_rx_pdev_alloc(struct ath12k_base *ab, int mac_id)
4399 {
4400 struct ath12k *ar = ab->pdevs[mac_id].ar;
4401 struct ath12k_pdev_dp *dp = &ar->dp;
4402 u32 ring_id;
4403 int i;
4404 int ret;
4405
4406 if (!ab->hw_params->rxdma1_enable)
4407 goto out;
4408
4409 ret = ath12k_dp_rx_pdev_srng_alloc(ar);
4410 if (ret) {
4411 ath12k_warn(ab, "failed to setup rx srngs\n");
4412 return ret;
4413 }
4414
4415 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) {
4416 ring_id = dp->rxdma_mon_dst_ring[i].ring_id;
4417 ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id,
4418 mac_id + i,
4419 HAL_RXDMA_MONITOR_DST);
4420 if (ret) {
4421 ath12k_warn(ab,
4422 "failed to configure rxdma_mon_dst_ring %d %d\n",
4423 i, ret);
4424 return ret;
4425 }
4426 }
4427 out:
4428 return 0;
4429 }
4430
ath12k_dp_rx_pdev_mon_status_attach(struct ath12k * ar)4431 static int ath12k_dp_rx_pdev_mon_status_attach(struct ath12k *ar)
4432 {
4433 struct ath12k_pdev_dp *dp = &ar->dp;
4434 struct ath12k_mon_data *pmon = (struct ath12k_mon_data *)&dp->mon_data;
4435
4436 skb_queue_head_init(&pmon->rx_status_q);
4437
4438 pmon->mon_ppdu_status = DP_PPDU_STATUS_START;
4439
4440 memset(&pmon->rx_mon_stats, 0,
4441 sizeof(pmon->rx_mon_stats));
4442 return 0;
4443 }
4444
ath12k_dp_rx_pdev_mon_attach(struct ath12k * ar)4445 int ath12k_dp_rx_pdev_mon_attach(struct ath12k *ar)
4446 {
4447 struct ath12k_pdev_dp *dp = &ar->dp;
4448 struct ath12k_mon_data *pmon = &dp->mon_data;
4449 int ret = 0;
4450
4451 ret = ath12k_dp_rx_pdev_mon_status_attach(ar);
4452 if (ret) {
4453 ath12k_warn(ar->ab, "pdev_mon_status_attach() failed");
4454 return ret;
4455 }
4456
4457 /* if rxdma1_enable is false, no need to setup
4458 * rxdma_mon_desc_ring.
4459 */
4460 if (!ar->ab->hw_params->rxdma1_enable)
4461 return 0;
4462
4463 pmon->mon_last_linkdesc_paddr = 0;
4464 pmon->mon_last_buf_cookie = DP_RX_DESC_COOKIE_MAX + 1;
4465 spin_lock_init(&pmon->mon_lock);
4466
4467 return 0;
4468 }
4469