1 // SPDX-License-Identifier: GPL-2.0+
5  * Author: Zheng Yang <zhengyang@rock-chips.com>
10 #include <linux/clk-provider.h>
16 #include <linux/nvmem-consumer.h>
127 /* for all RK3328_INT_TMDS_*, ESD_DET as defined in 0xc8-0xcb */
140 /* unset means center spread */
206 /* REG 0xc8 - 0xcb */
526  * but instead the databook simply numbers the registers in one-increments.
532 	regmap_write(inno->regmap, reg * 4, val);  in inno_write()
539 	regmap_read(inno->regmap, reg * 4, &val);  in inno_read()
547 	regmap_update_bits(inno->regmap, reg * 4, mask, val);  in inno_update_bits()
551 	regmap_read_poll_timeout((inno)->regmap, (reg) * 4, val, cond, \
557 	int bus_width = phy_get_bus_width(inno->phy);  in inno_hdmi_phy_get_tmdsclk()
609 	const struct phy_config *phy_cfg = inno->plat_data->phy_cfg_table;  in inno_hdmi_phy_power_on()
611 							    inno->pixclock);  in inno_hdmi_phy_power_on()
615 		dev_err(inno->dev, "TMDS clock is zero!\n");  in inno_hdmi_phy_power_on()
616 		return -EINVAL;  in inno_hdmi_phy_power_on()
619 	if (!inno->plat_data->ops->power_on)  in inno_hdmi_phy_power_on()
620 		return -EINVAL;  in inno_hdmi_phy_power_on()
622 	for (; cfg->tmdsclock != 0; cfg++)  in inno_hdmi_phy_power_on()
623 		if (tmdsclock <= cfg->tmdsclock &&  in inno_hdmi_phy_power_on()
624 		    cfg->version & inno->chip_version)  in inno_hdmi_phy_power_on()
627 	for (; phy_cfg->tmdsclock != 0; phy_cfg++)  in inno_hdmi_phy_power_on()
628 		if (tmdsclock <= phy_cfg->tmdsclock)  in inno_hdmi_phy_power_on()
631 	if (cfg->tmdsclock == 0 || phy_cfg->tmdsclock == 0)  in inno_hdmi_phy_power_on()
632 		return -EINVAL;  in inno_hdmi_phy_power_on()
634 	dev_dbg(inno->dev, "Inno HDMI PHY Power On\n");  in inno_hdmi_phy_power_on()
636 	inno->plat_data->clk_ops->set_rate(&inno->hw, inno->pixclock, 24000000);  in inno_hdmi_phy_power_on()
638 	ret = clk_prepare_enable(inno->phyclk);  in inno_hdmi_phy_power_on()
642 	ret = inno->plat_data->ops->power_on(inno, cfg, phy_cfg);  in inno_hdmi_phy_power_on()
644 		clk_disable_unprepare(inno->phyclk);  in inno_hdmi_phy_power_on()
655 	if (!inno->plat_data->ops->power_off)  in inno_hdmi_phy_power_off()
656 		return -EINVAL;  in inno_hdmi_phy_power_off()
658 	inno->plat_data->ops->power_off(inno);  in inno_hdmi_phy_power_off()
660 	clk_disable_unprepare(inno->phyclk);  in inno_hdmi_phy_power_off()
662 	inno->tmdsclock = 0;  in inno_hdmi_phy_power_off()
664 	dev_dbg(inno->dev, "Inno HDMI PHY Power Off\n");  in inno_hdmi_phy_power_off()
682 	for (; cfg->pixclock != 0; cfg++)  in inno_hdmi_phy_get_pre_pll_cfg()
683 		if (cfg->pixclock == rate && cfg->tmdsclock == tmdsclock)  in inno_hdmi_phy_get_pre_pll_cfg()
686 	if (cfg->pixclock == 0)  in inno_hdmi_phy_get_pre_pll_cfg()
687 		return ERR_PTR(-EINVAL);  in inno_hdmi_phy_get_pre_pll_cfg()
745 	inno->pixclock = vco;  in inno_hdmi_phy_rk3228_clk_recalc_rate()
747 	dev_dbg(inno->dev, "%s rate %lu\n", __func__, inno->pixclock);  in inno_hdmi_phy_rk3228_clk_recalc_rate()
760 	for (; cfg->pixclock != 0; cfg++)  in inno_hdmi_phy_rk3228_clk_round_rate()
761 		if (cfg->pixclock == rate && !cfg->fracdiv)  in inno_hdmi_phy_rk3228_clk_round_rate()
764 	if (cfg->pixclock == 0)  in inno_hdmi_phy_rk3228_clk_round_rate()
765 		return -EINVAL;  in inno_hdmi_phy_rk3228_clk_round_rate()
767 	return cfg->pixclock;  in inno_hdmi_phy_rk3228_clk_round_rate()
780 	dev_dbg(inno->dev, "%s rate %lu tmdsclk %lu\n",  in inno_hdmi_phy_rk3228_clk_set_rate()
783 	if (inno->pixclock == rate && inno->tmdsclock == tmdsclock)  in inno_hdmi_phy_rk3228_clk_set_rate()
790 	/* Power down PRE-PLL */  in inno_hdmi_phy_rk3228_clk_set_rate()
797 			 RK3228_PRE_PLL_FB_DIV_8(cfg->fbdiv) |  in inno_hdmi_phy_rk3228_clk_set_rate()
798 			 RK3228_PCLK_VCO_DIV_5(cfg->vco_div_5_en) |  in inno_hdmi_phy_rk3228_clk_set_rate()
799 			 RK3228_PRE_PLL_PRE_DIV(cfg->prediv));  in inno_hdmi_phy_rk3228_clk_set_rate()
800 	inno_write(inno, 0xe3, RK3228_PRE_PLL_FB_DIV_7_0(cfg->fbdiv));  in inno_hdmi_phy_rk3228_clk_set_rate()
803 			 RK3228_PRE_PLL_PCLK_DIV_B(cfg->pclk_div_b) |  in inno_hdmi_phy_rk3228_clk_set_rate()
804 			 RK3228_PRE_PLL_PCLK_DIV_A(cfg->pclk_div_a));  in inno_hdmi_phy_rk3228_clk_set_rate()
807 			 RK3228_PRE_PLL_PCLK_DIV_C(cfg->pclk_div_c) |  in inno_hdmi_phy_rk3228_clk_set_rate()
808 			 RK3228_PRE_PLL_PCLK_DIV_D(cfg->pclk_div_d));  in inno_hdmi_phy_rk3228_clk_set_rate()
812 			 RK3228_PRE_PLL_TMDSCLK_DIV_C(cfg->tmds_div_c) |  in inno_hdmi_phy_rk3228_clk_set_rate()
813 			 RK3228_PRE_PLL_TMDSCLK_DIV_A(cfg->tmds_div_a) |  in inno_hdmi_phy_rk3228_clk_set_rate()
814 			 RK3228_PRE_PLL_TMDSCLK_DIV_B(cfg->tmds_div_b));  in inno_hdmi_phy_rk3228_clk_set_rate()
816 	/* Power up PRE-PLL */  in inno_hdmi_phy_rk3228_clk_set_rate()
819 	/* Wait for Pre-PLL lock */  in inno_hdmi_phy_rk3228_clk_set_rate()
823 		dev_err(inno->dev, "Pre-PLL locking failed\n");  in inno_hdmi_phy_rk3228_clk_set_rate()
827 	inno->pixclock = rate;  in inno_hdmi_phy_rk3228_clk_set_rate()
828 	inno->tmdsclock = tmdsclock;  in inno_hdmi_phy_rk3228_clk_set_rate()
901 	inno->pixclock = DIV_ROUND_CLOSEST((unsigned long)vco, 1000) * 1000;  in inno_hdmi_phy_rk3328_clk_recalc_rate()
903 	dev_dbg(inno->dev, "%s rate %lu vco %llu\n",  in inno_hdmi_phy_rk3328_clk_recalc_rate()
904 		__func__, inno->pixclock, vco);  in inno_hdmi_phy_rk3328_clk_recalc_rate()
906 	return inno->pixclock;  in inno_hdmi_phy_rk3328_clk_recalc_rate()
917 	for (; cfg->pixclock != 0; cfg++)  in inno_hdmi_phy_rk3328_clk_round_rate()
918 		if (cfg->pixclock == rate)  in inno_hdmi_phy_rk3328_clk_round_rate()
921 	if (cfg->pixclock == 0)  in inno_hdmi_phy_rk3328_clk_round_rate()
922 		return -EINVAL;  in inno_hdmi_phy_rk3328_clk_round_rate()
924 	return cfg->pixclock;  in inno_hdmi_phy_rk3328_clk_round_rate()
937 	dev_dbg(inno->dev, "%s rate %lu tmdsclk %lu\n",  in inno_hdmi_phy_rk3328_clk_set_rate()
940 	if (inno->pixclock == rate && inno->tmdsclock == tmdsclock)  in inno_hdmi_phy_rk3328_clk_set_rate()
950 	/* Configure pre-pll */  in inno_hdmi_phy_rk3328_clk_set_rate()
952 			 RK3328_PCLK_VCO_DIV_5(cfg->vco_div_5_en));  in inno_hdmi_phy_rk3328_clk_set_rate()
953 	inno_write(inno, 0xa1, RK3328_PRE_PLL_PRE_DIV(cfg->prediv));  in inno_hdmi_phy_rk3328_clk_set_rate()
956 	if (!cfg->fracdiv)  in inno_hdmi_phy_rk3328_clk_set_rate()
958 	inno_write(inno, 0xa2, RK3328_PRE_PLL_FB_DIV_11_8(cfg->fbdiv) | val);  in inno_hdmi_phy_rk3328_clk_set_rate()
959 	inno_write(inno, 0xa3, RK3328_PRE_PLL_FB_DIV_7_0(cfg->fbdiv));  in inno_hdmi_phy_rk3328_clk_set_rate()
960 	inno_write(inno, 0xa5, RK3328_PRE_PLL_PCLK_DIV_A(cfg->pclk_div_a) |  in inno_hdmi_phy_rk3328_clk_set_rate()
961 		   RK3328_PRE_PLL_PCLK_DIV_B(cfg->pclk_div_b));  in inno_hdmi_phy_rk3328_clk_set_rate()
962 	inno_write(inno, 0xa6, RK3328_PRE_PLL_PCLK_DIV_C(cfg->pclk_div_c) |  in inno_hdmi_phy_rk3328_clk_set_rate()
963 		   RK3328_PRE_PLL_PCLK_DIV_D(cfg->pclk_div_d));  in inno_hdmi_phy_rk3328_clk_set_rate()
964 	inno_write(inno, 0xa4, RK3328_PRE_PLL_TMDSCLK_DIV_C(cfg->tmds_div_c) |  in inno_hdmi_phy_rk3328_clk_set_rate()
965 		   RK3328_PRE_PLL_TMDSCLK_DIV_A(cfg->tmds_div_a) |  in inno_hdmi_phy_rk3328_clk_set_rate()
966 		   RK3328_PRE_PLL_TMDSCLK_DIV_B(cfg->tmds_div_b));  in inno_hdmi_phy_rk3328_clk_set_rate()
967 	inno_write(inno, 0xd3, RK3328_PRE_PLL_FRAC_DIV_7_0(cfg->fracdiv));  in inno_hdmi_phy_rk3328_clk_set_rate()
968 	inno_write(inno, 0xd2, RK3328_PRE_PLL_FRAC_DIV_15_8(cfg->fracdiv));  in inno_hdmi_phy_rk3328_clk_set_rate()
969 	inno_write(inno, 0xd1, RK3328_PRE_PLL_FRAC_DIV_23_16(cfg->fracdiv));  in inno_hdmi_phy_rk3328_clk_set_rate()
973 	/* Wait for Pre-PLL lock */  in inno_hdmi_phy_rk3328_clk_set_rate()
977 		dev_err(inno->dev, "Pre-PLL locking failed\n");  in inno_hdmi_phy_rk3328_clk_set_rate()
981 	inno->pixclock = rate;  in inno_hdmi_phy_rk3328_clk_set_rate()
982 	inno->tmdsclock = tmdsclock;  in inno_hdmi_phy_rk3328_clk_set_rate()
998 	struct device *dev = inno->dev;  in inno_hdmi_phy_clk_register()
999 	struct device_node *np = dev->of_node;  in inno_hdmi_phy_clk_register()
1004 	parent_name = __clk_get_name(inno->refoclk);  in inno_hdmi_phy_clk_register()
1010 	init.ops = inno->plat_data->clk_ops;  in inno_hdmi_phy_clk_register()
1013 	of_property_read_string(np, "clock-output-names", &init.name);  in inno_hdmi_phy_clk_register()
1015 	inno->hw.init = &init;  in inno_hdmi_phy_clk_register()
1017 	inno->phyclk = devm_clk_register(dev, &inno->hw);  in inno_hdmi_phy_clk_register()
1018 	if (IS_ERR(inno->phyclk)) {  in inno_hdmi_phy_clk_register()
1019 		ret = PTR_ERR(inno->phyclk);  in inno_hdmi_phy_clk_register()
1024 	ret = of_clk_add_provider(np, of_clk_src_simple_get, inno->phyclk);  in inno_hdmi_phy_clk_register()
1045 	/* manual power down post-PLL */  in inno_hdmi_phy_rk3228_init()
1049 	inno->chip_version = 1;  in inno_hdmi_phy_rk3228_init()
1069 	/* Post-PLL update */  in inno_hdmi_phy_rk3228_power_on()
1071 			 RK3228_POST_PLL_PRE_DIV(cfg->prediv));  in inno_hdmi_phy_rk3228_power_on()
1073 			 RK3228_POST_PLL_FB_DIV_8(cfg->fbdiv));  in inno_hdmi_phy_rk3228_power_on()
1074 	inno_write(inno, 0xea, RK3228_POST_PLL_FB_DIV_7_0(cfg->fbdiv));  in inno_hdmi_phy_rk3228_power_on()
1076 	if (cfg->postdiv == 1) {  in inno_hdmi_phy_rk3228_power_on()
1080 		int div = cfg->postdiv / 2 - 1;  in inno_hdmi_phy_rk3228_power_on()
1089 		inno_write(inno, 0xef + v, phy_cfg->regs[v]);  in inno_hdmi_phy_rk3228_power_on()
1102 		dev_err(inno->dev, "Post-PLL locking failed\n");  in inno_hdmi_phy_rk3228_power_on()
1106 	if (cfg->tmdsclock > 340000000)  in inno_hdmi_phy_rk3228_power_on()
1147 	/* try to read the chip-version */  in inno_hdmi_phy_rk3328_init()
1148 	inno->chip_version = 1;  in inno_hdmi_phy_rk3328_init()
1149 	cell = nvmem_cell_get(inno->dev, "cpu-version");  in inno_hdmi_phy_rk3328_init()
1151 		if (PTR_ERR(cell) == -EPROBE_DEFER)  in inno_hdmi_phy_rk3328_init()
1152 			return -EPROBE_DEFER;  in inno_hdmi_phy_rk3328_init()
1163 		inno->chip_version = efuse_buf[0] + 1;  in inno_hdmi_phy_rk3328_init()
1181 	inno_write(inno, 0xac, RK3328_POST_PLL_FB_DIV_7_0(cfg->fbdiv));  in inno_hdmi_phy_rk3328_power_on()
1182 	if (cfg->postdiv == 1) {  in inno_hdmi_phy_rk3328_power_on()
1183 		inno_write(inno, 0xab, RK3328_POST_PLL_FB_DIV_8(cfg->fbdiv) |  in inno_hdmi_phy_rk3328_power_on()
1184 			   RK3328_POST_PLL_PRE_DIV(cfg->prediv));  in inno_hdmi_phy_rk3328_power_on()
1188 		v = (cfg->postdiv / 2) - 1;  in inno_hdmi_phy_rk3328_power_on()
1191 		inno_write(inno, 0xab, RK3328_POST_PLL_FB_DIV_8(cfg->fbdiv) |  in inno_hdmi_phy_rk3328_power_on()
1192 			   RK3328_POST_PLL_PRE_DIV(cfg->prediv));  in inno_hdmi_phy_rk3328_power_on()
1199 		inno_write(inno, 0xb5 + v, phy_cfg->regs[v]);  in inno_hdmi_phy_rk3328_power_on()
1206 	if (phy_cfg->tmdsclock > 340000000) {  in inno_hdmi_phy_rk3328_power_on()
1208 		v = clk_get_rate(inno->sysclk) / 100000;  in inno_hdmi_phy_rk3328_power_on()
1219 		if (phy_cfg->tmdsclock > 165000000)  in inno_hdmi_phy_rk3328_power_on()
1242 		dev_err(inno->dev, "Post-PLL locking failed\n");  in inno_hdmi_phy_rk3328_power_on()
1246 	if (phy_cfg->tmdsclock > 340000000)  in inno_hdmi_phy_rk3328_power_on()
1300 	clk_disable_unprepare(inno->refpclk);  in inno_hdmi_phy_action()
1301 	clk_disable_unprepare(inno->sysclk);  in inno_hdmi_phy_action()
1311 	inno = devm_kzalloc(&pdev->dev, sizeof(*inno), GFP_KERNEL);  in inno_hdmi_phy_probe()
1313 		return -ENOMEM;  in inno_hdmi_phy_probe()
1315 	inno->dev = &pdev->dev;  in inno_hdmi_phy_probe()
1317 	inno->plat_data = of_device_get_match_data(inno->dev);  in inno_hdmi_phy_probe()
1318 	if (!inno->plat_data || !inno->plat_data->ops)  in inno_hdmi_phy_probe()
1319 		return -EINVAL;  in inno_hdmi_phy_probe()
1325 	inno->sysclk = devm_clk_get(inno->dev, "sysclk");  in inno_hdmi_phy_probe()
1326 	if (IS_ERR(inno->sysclk)) {  in inno_hdmi_phy_probe()
1327 		ret = PTR_ERR(inno->sysclk);  in inno_hdmi_phy_probe()
1328 		dev_err(inno->dev, "failed to get sysclk: %d\n", ret);  in inno_hdmi_phy_probe()
1332 	inno->refpclk = devm_clk_get(inno->dev, "refpclk");  in inno_hdmi_phy_probe()
1333 	if (IS_ERR(inno->refpclk)) {  in inno_hdmi_phy_probe()
1334 		ret = PTR_ERR(inno->refpclk);  in inno_hdmi_phy_probe()
1335 		dev_err(inno->dev, "failed to get ref clock: %d\n", ret);  in inno_hdmi_phy_probe()
1339 	inno->refoclk = devm_clk_get(inno->dev, "refoclk");  in inno_hdmi_phy_probe()
1340 	if (IS_ERR(inno->refoclk)) {  in inno_hdmi_phy_probe()
1341 		ret = PTR_ERR(inno->refoclk);  in inno_hdmi_phy_probe()
1342 		dev_err(inno->dev, "failed to get oscillator-ref clock: %d\n",  in inno_hdmi_phy_probe()
1347 	ret = clk_prepare_enable(inno->sysclk);  in inno_hdmi_phy_probe()
1349 		dev_err(inno->dev, "Cannot enable inno phy sysclk: %d\n", ret);  in inno_hdmi_phy_probe()
1357 	ret = clk_prepare_enable(inno->refpclk);  in inno_hdmi_phy_probe()
1359 		dev_err(inno->dev, "failed to enable refpclk\n");  in inno_hdmi_phy_probe()
1360 		clk_disable_unprepare(inno->sysclk);  in inno_hdmi_phy_probe()
1364 	ret = devm_add_action_or_reset(inno->dev, inno_hdmi_phy_action,  in inno_hdmi_phy_probe()
1369 	inno->regmap = devm_regmap_init_mmio(inno->dev, regs,  in inno_hdmi_phy_probe()
1371 	if (IS_ERR(inno->regmap))  in inno_hdmi_phy_probe()
1372 		return PTR_ERR(inno->regmap);  in inno_hdmi_phy_probe()
1375 	inno->irq = platform_get_irq(pdev, 0);  in inno_hdmi_phy_probe()
1376 	if (inno->irq > 0) {  in inno_hdmi_phy_probe()
1377 		ret = devm_request_threaded_irq(inno->dev, inno->irq,  in inno_hdmi_phy_probe()
1381 						dev_name(inno->dev), inno);  in inno_hdmi_phy_probe()
1386 	inno->phy = devm_phy_create(inno->dev, NULL, &inno_hdmi_phy_ops);  in inno_hdmi_phy_probe()
1387 	if (IS_ERR(inno->phy)) {  in inno_hdmi_phy_probe()
1388 		dev_err(inno->dev, "failed to create HDMI PHY\n");  in inno_hdmi_phy_probe()
1389 		return PTR_ERR(inno->phy);  in inno_hdmi_phy_probe()
1392 	phy_set_drvdata(inno->phy, inno);  in inno_hdmi_phy_probe()
1393 	phy_set_bus_width(inno->phy, 8);  in inno_hdmi_phy_probe()
1395 	if (inno->plat_data->ops->init) {  in inno_hdmi_phy_probe()
1396 		ret = inno->plat_data->ops->init(inno);  in inno_hdmi_phy_probe()
1405 	phy_provider = devm_of_phy_provider_register(inno->dev,  in inno_hdmi_phy_probe()
1412 	of_clk_del_provider(pdev->dev.of_node);  in inno_hdmi_phy_remove()
1417 		.compatible = "rockchip,rk3228-hdmi-phy",
1420 		.compatible = "rockchip,rk3328-hdmi-phy",
1430 		.name = "inno-hdmi-phy",
1436 MODULE_AUTHOR("Zheng Yang <zhengyang@rock-chips.com>");