Home
last modified time | relevance | path

Searched +full:0 +full:x1004 (Results 1 – 25 of 306) sorted by relevance

12345678910>>...13

/linux-6.14.4/include/linux/mtd/
Ddoc2000.h17 #define DoC_Sig1 0
20 #define DoC_ChipID 0x1000
21 #define DoC_DOCStatus 0x1001
22 #define DoC_DOCControl 0x1002
23 #define DoC_FloorSelect 0x1003
24 #define DoC_CDSNControl 0x1004
25 #define DoC_CDSNDeviceSelect 0x1005
26 #define DoC_ECCConf 0x1006
27 #define DoC_2k_ECCStatus 0x1007
29 #define DoC_CDSNSlowIO 0x100d
[all …]
/linux-6.14.4/drivers/clk/qcom/
Dgpucc-sc7180.c20 #define CX_GMU_CBCR_SLEEP_MASK 0xF
22 #define CX_GMU_CBCR_WAKE_MASK 0xF
33 { 249600000, 2000000000, 0 },
37 .offset = 0x100,
54 { P_BI_TCXO, 0 },
68 F(19200000, P_BI_TCXO, 1, 0, 0),
69 F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),
74 .cmd_rcgr = 0x1120,
75 .mnd_width = 0,
89 .halt_reg = 0x107c,
[all …]
Dgpucc-sm8150.c30 { 249600000, 2000000000, 0 },
34 .l = 0x1a,
35 .alpha = 0xaaa,
36 .config_ctl_val = 0x20485699,
37 .config_ctl_hi_val = 0x00002267,
38 .config_ctl_hi1_val = 0x00000024,
39 .test_ctl_val = 0x00000000,
40 .test_ctl_hi_val = 0x00000000,
41 .test_ctl_hi1_val = 0x00000020,
42 .user_ctl_val = 0x00000000,
[all …]
Dgpucc-sm8250.c22 #define CX_GMU_CBCR_SLEEP_MASK 0xf
24 #define CX_GMU_CBCR_WAKE_MASK 0xf
36 { 249600000, 2000000000, 0 },
40 .l = 0x1a,
41 .alpha = 0xaaa,
42 .config_ctl_val = 0x20485699,
43 .config_ctl_hi_val = 0x00002261,
44 .config_ctl_hi1_val = 0x029a699c,
45 .user_ctl_val = 0x00000000,
46 .user_ctl_hi_val = 0x00000805,
[all …]
Dgpucc-sm6125.c40 { 1000000000, 2000000000, 0 },
46 .l = 0x35,
47 .config_ctl_val = 0x4001055b,
48 .alpha_hi = 0x20,
49 .alpha = 0x00,
51 .vco_val = 0x0 << 20,
52 .vco_mask = 0x3 << 20,
58 .l = 0x30,
59 .config_ctl_val = 0x4001055b,
60 .alpha_hi = 0x70,
[all …]
Dgpucc-qcm2290.c45 { 600000000, 3300000000, 0 },
50 .l = 0x25,
51 .config_ctl_val = 0x200d4828,
52 .config_ctl_hi_val = 0x6,
55 .user_ctl_val = 0xf,
59 .offset = 0x0,
76 { P_BI_TCXO, 0 },
90 { P_BI_TCXO, 0 },
106 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
111 .cmd_rcgr = 0x1120,
[all …]
/linux-6.14.4/arch/x86/include/uapi/asm/
Dprctl.h5 #define ARCH_SET_GS 0x1001
6 #define ARCH_SET_FS 0x1002
7 #define ARCH_GET_FS 0x1003
8 #define ARCH_GET_GS 0x1004
10 #define ARCH_GET_CPUID 0x1011
11 #define ARCH_SET_CPUID 0x1012
13 #define ARCH_GET_XCOMP_SUPP 0x1021
14 #define ARCH_GET_XCOMP_PERM 0x1022
15 #define ARCH_REQ_XCOMP_PERM 0x1023
16 #define ARCH_GET_XCOMP_GUEST_PERM 0x1024
[all …]
/linux-6.14.4/tools/perf/trace/beauty/arch/x86/include/uapi/asm/
Dprctl.h5 #define ARCH_SET_GS 0x1001
6 #define ARCH_SET_FS 0x1002
7 #define ARCH_GET_FS 0x1003
8 #define ARCH_GET_GS 0x1004
10 #define ARCH_GET_CPUID 0x1011
11 #define ARCH_SET_CPUID 0x1012
13 #define ARCH_GET_XCOMP_SUPP 0x1021
14 #define ARCH_GET_XCOMP_PERM 0x1022
15 #define ARCH_REQ_XCOMP_PERM 0x1023
16 #define ARCH_GET_XCOMP_GUEST_PERM 0x1024
[all …]
/linux-6.14.4/include/linux/
Dkernelcapi.h19 #define CAPI_NOERROR 0x0000
21 #define CAPI_TOOMANYAPPLS 0x1001
22 #define CAPI_LOGBLKSIZETOSMALL 0x1002
23 #define CAPI_BUFFEXECEEDS64K 0x1003
24 #define CAPI_MSGBUFSIZETOOSMALL 0x1004
25 #define CAPI_ANZLOGCONNNOTSUPPORTED 0x1005
26 #define CAPI_REGRESERVED 0x1006
27 #define CAPI_REGBUSY 0x1007
28 #define CAPI_REGOSRESOURCEERR 0x1008
29 #define CAPI_REGNOTINSTALLED 0x1009
[all …]
/linux-6.14.4/arch/xtensa/include/asm/
Dbootparam.h18 #define BP_VERSION 0x0001
20 #define BP_TAG_COMMAND_LINE 0x1001 /* command line (0-terminated string)*/
21 #define BP_TAG_INITRD 0x1002 /* ramdisk addr and size (bp_meminfo) */
22 #define BP_TAG_MEMORY 0x1003 /* memory addr and size (bp_meminfo) */
23 #define BP_TAG_SERIAL_BAUDRATE 0x1004 /* baud rate of current console. */
24 #define BP_TAG_SERIAL_PORT 0x1005 /* serial device of current console */
25 #define BP_TAG_FDT 0x1006 /* flat device tree addr */
27 #define BP_TAG_FIRST 0x7B0B /* first tag with a version number */
28 #define BP_TAG_LAST 0x7E0B /* last tag */
46 #define MEMORY_TYPE_CONVENTIONAL 0x1000
[all …]
/linux-6.14.4/arch/m68k/include/asm/
Dmac_psc.h37 #define PSC_BASE (0x50F31000)
44 * To access a particular set of registers, add 0xn0 to the base
48 #define pIFRbase 0x100
49 #define pIERbase 0x104
55 #define PSC_MYSTERY 0x804
57 #define PSC_CTL_BASE 0xC00
59 #define PSC_SCSI_CTL 0xC00
60 #define PSC_ENETRD_CTL 0xC10
61 #define PSC_ENETWR_CTL 0xC20
62 #define PSC_FDC_CTL 0xC30
[all …]
/linux-6.14.4/drivers/gpu/drm/amd/display/dc/core/
Ddc_hw_sequencer.c36 #define NUM_ELEMENTS(a) (sizeof(a) / sizeof((a)[0]))
40 BLACK_COLOR_FORMAT_RGB_FULLRANGE = 0,
61 {0, 0, 0},
63 {0x40, 0x40, 0x40},
65 {0x200, 0x40, 0x200},
67 {0x1f4, 0x40, 0x1f4},
69 {0x1a2, 0x20, 0x1a2},
71 {0xff, 0xff, 0},
81 { 0x2000, 0, 0, 0,
82 0, 0x2000, 0, 0,
[all …]
/linux-6.14.4/arch/s390/include/asm/
Dirq.h5 #define EXT_INTERRUPT 0
15 #define EXT_IRQ_INTERRUPT_KEY 0x0040
16 #define EXT_IRQ_CLK_COMP 0x1004
17 #define EXT_IRQ_CPU_TIMER 0x1005
18 #define EXT_IRQ_WARNING_TRACK 0x1007
19 #define EXT_IRQ_MALFUNC_ALERT 0x1200
20 #define EXT_IRQ_EMERGENCY_SIG 0x1201
21 #define EXT_IRQ_EXTERNAL_CALL 0x1202
22 #define EXT_IRQ_TIMING_ALERT 0x1406
23 #define EXT_IRQ_MEASURE_ALERT 0x1407
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/timer/
Drenesas,cmt.yaml182 reg = <0xffca0000 0x1004>;
193 reg = <0xe6130000 0x1004>;
/linux-6.14.4/drivers/power/reset/
Daxxia-reset.c19 #define SC_CRIT_WRITE_KEY 0x1000
20 #define SC_LATCH_ON_RESET 0x1004
21 #define SC_RESET_CONTROL 0x1008
25 #define RSTCTL_RST_SYS (1<<0)
26 #define SC_EFUSE_INT_STATUS 0x180c
33 /* Access Key (0xab) */ in axxia_restart_handler()
34 regmap_write(syscon, SC_CRIT_WRITE_KEY, 0xab); in axxia_restart_handler()
35 /* Select internal boot from 0xffff0000 */ in axxia_restart_handler()
36 regmap_write(syscon, SC_LATCH_ON_RESET, 0x00000040); in axxia_restart_handler()
/linux-6.14.4/include/linux/soc/samsung/
Dexynos-regs-pmu.h17 #define S5P_CENTRAL_SEQ_CONFIGURATION 0x0200
21 #define S5P_CENTRAL_SEQ_OPTION 0x0208
42 #define EXYNOS_SWRESET 0x0400
44 #define S5P_WAKEUP_STAT 0x0600
46 #define EXYNOS_EINT_WAKEUP_MASK_DISABLED 0xffffffff
47 #define EXYNOS_EINT_WAKEUP_MASK 0x0604
48 #define S5P_WAKEUP_MASK 0x0608
49 #define S5P_WAKEUP_MASK2 0x0614
52 #define EXYNOS4_MIPI_PHY_CONTROL(n) (0x0710 + (n) * 4)
54 #define EXYNOS4_PHY_ENABLE (1 << 0)
[all …]
/linux-6.14.4/sound/soc/tegra/
Dtegra186_asrc.h13 #define TEGRA186_ASRC_CFG 0x0
14 #define TEGRA186_ASRC_RATIO_INT_PART 0x4
15 #define TEGRA186_ASRC_RATIO_FRAC_PART 0x8
16 #define TEGRA186_ASRC_RATIO_LOCK_STATUS 0xc
17 #define TEGRA186_ASRC_MUTE_UNMUTE_DURATION 0x10
18 #define TEGRA186_ASRC_TX_THRESHOLD 0x14
19 #define TEGRA186_ASRC_RX_THRESHOLD 0x18
20 #define TEGRA186_ASRC_RATIO_COMP 0x1c
21 #define TEGRA186_ASRC_RX_STATUS 0x20
22 #define TEGRA186_ASRC_RX_CIF_CTRL 0x24
[all …]
/linux-6.14.4/drivers/media/platform/samsung/exynos4-is/
Dfimc-is-command.h21 #define HIC_PREVIEW_STILL 0x0001
22 #define HIC_PREVIEW_VIDEO 0x0002
23 #define HIC_CAPTURE_STILL 0x0003
24 #define HIC_CAPTURE_VIDEO 0x0004
25 #define HIC_STREAM_ON 0x0005
26 #define HIC_STREAM_OFF 0x0006
27 #define HIC_SET_PARAMETER 0x0007
28 #define HIC_GET_PARAMETER 0x0008
29 #define HIC_SET_TUNE 0x0009
30 #define HIC_GET_STATUS 0x000b
[all …]
/linux-6.14.4/drivers/dma/amd/qdma/
Dqdma-comm-regs.c12 [QDMA_REGO_CTXT_DATA] = QDMA_REGO(0x804, 8),
13 [QDMA_REGO_CTXT_CMD] = QDMA_REGO(0x844, 1),
14 [QDMA_REGO_CTXT_MASK] = QDMA_REGO(0x824, 8),
15 [QDMA_REGO_MM_H2C_CTRL] = QDMA_REGO(0x1004, 1),
16 [QDMA_REGO_MM_C2H_CTRL] = QDMA_REGO(0x1204, 1),
17 [QDMA_REGO_QUEUE_COUNT] = QDMA_REGO(0x120, 1),
18 [QDMA_REGO_RING_SIZE] = QDMA_REGO(0x204, 1),
19 [QDMA_REGO_H2C_PIDX] = QDMA_REGO(0x18004, 1),
20 [QDMA_REGO_C2H_PIDX] = QDMA_REGO(0x18008, 1),
21 [QDMA_REGO_INTR_CIDX] = QDMA_REGO(0x18000, 1),
[all …]
/linux-6.14.4/drivers/net/dsa/xrs700x/
Dxrs700x_reg.h4 #define XRS_DEVICE_ID_BASE 0x0
5 #define XRS_GPIO_BASE 0x10000
6 #define XRS_PORT_OFFSET 0x10000
7 #define XRS_PORT_BASE(x) (0x200000 + XRS_PORT_OFFSET * (x))
8 #define XRS_RTC_BASE 0x280000
9 #define XRS_TS_OFFSET 0x8000
10 #define XRS_TS_BASE(x) (0x290000 + XRS_TS_OFFSET * (x))
11 #define XRS_SWITCH_CONF_BASE 0x300000
14 #define XRS_DEV_ID0 (XRS_DEVICE_ID_BASE + 0)
21 #define XRS_CONFIG0 (XRS_GPIO_BASE + 0x1000)
[all …]
/linux-6.14.4/sound/soc/sof/amd/
Dacp-dsp-offset.h15 #define ACP_DMA_CNTL_0 0x00
16 #define ACP_DMA_DSCR_STRT_IDX_0 0x20
17 #define ACP_DMA_DSCR_CNT_0 0x40
18 #define ACP_DMA_PRIO_0 0x60
19 #define ACP_DMA_CUR_DSCR_0 0x80
20 #define ACP_DMA_ERR_STS_0 0xC0
21 #define ACP_DMA_DESC_BASE_ADDR 0xE0
22 #define ACP_DMA_DESC_MAX_NUM_DSCR 0xE4
23 #define ACP_DMA_CH_STS 0xE8
24 #define ACP_DMA_CH_GROUP 0xEC
[all …]
/linux-6.14.4/arch/parisc/include/uapi/asm/
Dsocket.h9 #define SOL_SOCKET 0xffff
11 #define SO_DEBUG 0x0001
12 #define SO_REUSEADDR 0x0004
13 #define SO_KEEPALIVE 0x0008
14 #define SO_DONTROUTE 0x0010
15 #define SO_BROADCAST 0x0020
16 #define SO_LINGER 0x0080
17 #define SO_OOBINLINE 0x0100
18 #define SO_REUSEPORT 0x0200
19 #define SO_SNDBUF 0x1001
[all …]
/linux-6.14.4/drivers/remoteproc/
Dqcom_wcnss.c37 #define WCNSS_SSCTL_ID 0x13
44 #define WCNSS_PMU_IRIS_XO_CFG_STS BIT(6) /* 1: in progress, 0: done */
47 #define WCNSS_PMU_IRIS_RESET_STS BIT(8) /* 1: in progress, 0: done */
52 #define WCNSS_PMU_XO_MODE_19p2 0
105 .pmu_offset = 0x28,
106 .spare_offset = 0xb4,
109 { "vddmx", 1050000, 1150000, 0 },
110 { "vddcx", 1050000, 1150000, 0 },
111 { "vddpx", 1800000, 1800000, 0 },
117 .pmu_offset = 0x1004,
[all …]
/linux-6.14.4/drivers/net/ethernet/huawei/hinic/
Dhinic_hw_csr.h11 #define HINIC_CSR_FUNC_ATTR0_ADDR 0x0
12 #define HINIC_CSR_FUNC_ATTR1_ADDR 0x4
13 #define HINIC_CSR_FUNC_ATTR2_ADDR 0x8
14 #define HINIC_CSR_FUNC_ATTR4_ADDR 0x10
15 #define HINIC_CSR_FUNC_ATTR5_ADDR 0x14
17 #define HINIC_DMA_ATTR_BASE 0xC80
18 #define HINIC_ELECTION_BASE 0x4200
20 #define HINIC_DMA_ATTR_STRIDE 0x4
24 #define HINIC_PPF_ELECTION_STRIDE 0x4
30 #define HINIC_CSR_API_CMD_BASE 0xF000
[all …]
/linux-6.14.4/include/linux/firmware/cirrus/
Dwmfw.h21 #define WMFW_CTL_FLAG_SYS 0x8000
22 #define WMFW_CTL_FLAG_VOLATILE 0x0004
23 #define WMFW_CTL_FLAG_WRITEABLE 0x0002
24 #define WMFW_CTL_FLAG_READABLE 0x0001
26 #define WMFW_CTL_TYPE_BYTES 0x0004 /* byte control */
28 /* Non-ALSA coefficient types start at 0x1000 */
29 #define WMFW_CTL_TYPE_ACKED 0x1000 /* acked control */
30 #define WMFW_CTL_TYPE_HOSTEVENT 0x1001 /* event control */
31 #define WMFW_CTL_TYPE_HOST_BUFFER 0x1002 /* host buffer pointer */
32 #define WMFW_CTL_TYPE_FWEVENT 0x1004 /* firmware event control */
[all …]

12345678910>>...13