Lines Matching +full:0 +full:x1004
40 { 1000000000, 2000000000, 0 },
46 .l = 0x35,
47 .config_ctl_val = 0x4001055b,
48 .alpha_hi = 0x20,
49 .alpha = 0x00,
51 .vco_val = 0x0 << 20,
52 .vco_mask = 0x3 << 20,
58 .l = 0x30,
59 .config_ctl_val = 0x4001055b,
60 .alpha_hi = 0x70,
61 .alpha = 0x00,
63 .vco_val = 0x2 << 20,
64 .vco_mask = 0x3 << 20,
69 .offset = 0x0,
87 .offset = 0x100,
105 { P_BI_TCXO, 0 },
115 { P_BI_TCXO, 0 },
127 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
132 .cmd_rcgr = 0x1120,
133 .mnd_width = 0,
146 F(320000000, P_GPU_CC_PLL1_OUT_AUX2, 2, 0, 0),
147 F(465000000, P_GPU_CC_PLL1_OUT_AUX2, 2, 0, 0),
148 F(600000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
149 F(745000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
150 F(820000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
151 F(900000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
152 F(950000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
157 .cmd_rcgr = 0x101c,
158 .mnd_width = 0,
172 .halt_reg = 0x107c,
175 .enable_reg = 0x107c,
176 .enable_mask = BIT(0),
185 .halt_reg = 0x1088,
188 .enable_reg = 0x1088,
189 .enable_mask = BIT(0),
198 .halt_reg = 0x1054,
201 .enable_reg = 0x1054,
202 .enable_mask = BIT(0),
216 .halt_reg = 0x10a4,
219 .enable_reg = 0x10a4,
220 .enable_mask = BIT(0),
234 .halt_reg = 0x1098,
237 .enable_reg = 0x1098,
238 .enable_mask = BIT(0),
252 .halt_reg = 0x108c,
255 .enable_reg = 0x108c,
256 .enable_mask = BIT(0),
265 .halt_reg = 0x1004,
268 .enable_reg = 0x1004,
269 .enable_mask = BIT(0),
278 .halt_reg = 0x109c,
281 .enable_reg = 0x109c,
282 .enable_mask = BIT(0),
291 .halt_reg = 0x1090,
294 .enable_reg = 0x1090,
295 .enable_mask = BIT(0),
304 .halt_reg = 0x1078,
307 .enable_reg = 0x1078,
308 .enable_mask = BIT(0),
318 .halt_reg = 0x5000,
321 .enable_reg = 0x5000,
322 .enable_mask = BIT(0),
331 .gdscr = 0x106c,
332 .gds_hw_ctrl = 0x1540,
341 .gdscr = 0x100c,
376 .max_register = 0x9000,
406 qcom_branch_set_wakeup(regmap, gpu_cc_cx_gmu_clk, 0xf); in gpu_cc_sm6125_probe()
407 qcom_branch_set_sleep(regmap, gpu_cc_cx_gmu_clk, 0xf); in gpu_cc_sm6125_probe()