Lines Matching +full:0 +full:x1004
45 { 600000000, 3300000000, 0 },
50 .l = 0x25,
51 .config_ctl_val = 0x200d4828,
52 .config_ctl_hi_val = 0x6,
55 .user_ctl_val = 0xf,
59 .offset = 0x0,
76 { P_BI_TCXO, 0 },
90 { P_BI_TCXO, 0 },
106 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
111 .cmd_rcgr = 0x1120,
112 .mnd_width = 0,
126 F(355200000, P_GPU_CC_PLL0_OUT_AUX, 2, 0, 0),
127 F(537600000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
128 F(672000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
129 F(844800000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
130 F(921600000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
131 F(1017600000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
132 F(1123200000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
137 .cmd_rcgr = 0x101c,
138 .mnd_width = 0,
152 .halt_reg = 0x1078,
155 .enable_reg = 0x1078,
156 .enable_mask = BIT(0),
166 .halt_reg = 0x107c,
169 .enable_reg = 0x107c,
170 .enable_mask = BIT(0),
179 .halt_reg = 0x10a4,
182 .enable_reg = 0x10a4,
183 .enable_mask = BIT(0),
197 .halt_reg = 0x1098,
200 .enable_reg = 0x1098,
201 .enable_mask = BIT(0),
215 .halt_reg = 0x108c,
218 .enable_reg = 0x108c,
219 .enable_mask = BIT(0),
228 .halt_reg = 0x1004,
231 .enable_reg = 0x1004,
232 .enable_mask = BIT(0),
241 .halt_reg = 0x109c,
244 .enable_reg = 0x109c,
245 .enable_mask = BIT(0),
254 .halt_reg = 0x1054,
257 .enable_reg = 0x1054,
258 .enable_mask = BIT(0),
272 .halt_reg = 0x1090,
275 .enable_reg = 0x1090,
276 .enable_mask = BIT(0),
285 .halt_reg = 0x5000,
288 .enable_reg = 0x5000,
289 .enable_mask = BIT(0),
298 .gdscr = 0x106c,
299 .gds_hw_ctrl = 0x1540,
308 .gdscr = 0x100c,
309 .clamp_io_ctrl = 0x1508,
337 [GPU_GX_BCR] = { 0x1008 },
349 .max_register = 0x9000,
388 if (ret < 0) { in gpu_cc_qcm2290_probe()
399 regmap_update_bits(regmap, 0x1060, BIT(0), BIT(0)); /* GPU_CC_GX_CXO_CLK */ in gpu_cc_qcm2290_probe()
410 return 0; in gpu_cc_qcm2290_probe()